net: fsl_enetc: Update enetc driver to support i.MX95
i.MX95 uses enetc version 4.1 controller. Update the enetc for i.MX95.
Add ARM-specific cache handling and i.MX95 specific register layout
handling.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Clean up
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 82c2476..804df85 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -12,6 +12,7 @@
/* PCI function IDs */
#define PCI_DEVICE_ID_ENETC_ETH 0xE100
+#define PCI_DEVICE_ID_ENETC4_ETH 0xE101
#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
#define PCI_DEVICE_ID_ENETC4_EMDIO 0xEE00
@@ -23,7 +24,8 @@
/* write cache cfg: snoop, no allocate, data & BD coherent */
#define ENETC_SICAR_WR_CFG 0x6767
/* read cache cfg: coherent copy, look up, don't alloc in cache */
-#define ENETC_SICAR_RD_CFG 0x27270000
+#define ENETC_SICAR_RD_CFG_LS 0x27270000
+#define ENETC_SICAR_RD_CFG_IMX 0x2b2b0000
#define ENETC_SIROCT 0x300
#define ENETC_SIRFRM 0x308
#define ENETC_SITOCT 0x320
@@ -58,25 +60,37 @@
#define ENETC_PORT_REGS_OFF 0x10000
/* Port registers */
+#define ENETC_PMR_OFFSET_IMX 0x0010
#define ENETC_PMR_OFFSET_LS 0x0000
#define ENETC_PMR 0x0000
#define ENETC_PMR_SI0_EN BIT(16)
#define ENETC_PSIPMMR 0x0018
+#define ENETC_PSIPMARn_OFFSET_IMX 0x0000
#define ENETC_PSIPMARn_OFFSET_LS 0x0080
#define ENETC_PSIPMAR0 0x0080
#define ENETC_PSIPMAR1 0x0084
+#define ENETC_PCAPR_OFFSET_IMX 0x4008
#define ENETC_PCAPR_OFFSET_LS 0x0900
#define ENETC_PCAPR0 0x0000
-#define ENETC_PCAPRO_MDIO BIT(11)
+#define ENETC_PCAPRO_MDIO BIT(11) /* LS only */
+#define ENETC_PCS_PROT GENMASK(15, 0) /* IMX only */
+/* ENETC base registers */
#define ENETC_PSICFGR_OFFSET_LS 0x0940
#define ENETC_PSICFGR_SHIFT_LS 0x10
+#define ENETC_PSICFGR_OFFSET_IMX 0x2010
+#define ENETC_PSICFGR_SHIFT_IMX 0x80
#define ENETC_PSICFGR(n, s) ((n) * (s))
#define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx))
/* MAC configuration */
+#define ENETC_PM_OFFSET_IMX 0x5000
#define ENETC_PM_OFFSET_LS 0x8000
#define ENETC_PM_CC 0x0008
#define ENETC_PM_CC_DEFAULT 0x0810
-#define ENETC_PM_CC_RX_TX_EN 0x8813
+#define ENETC_PM_CC_TXP_IMX BIT(15)
+#define ENETC_PM_CC_TXP_LS BIT(11)
+#define ENETC_PM_CC_PROMIS BIT(4)
+#define ENETC_PM_CC_TX BIT(1)
+#define ENETC_PM_CC_RX BIT(0)
#define ENETC_PM_MAXFRM 0x0014
#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
#define ENETC_PM_IMDIO_BASE 0x0030
@@ -87,8 +101,19 @@
#define ENETC_PM_IFM_SSP_1000 (2 << 13)
#define ENETC_PM_IFM_SSP_100 (0 << 13)
#define ENETC_PM_IFM_SSP_10 (1 << 13)
-#define ENETC_PM_IFM_FULL_DPX BIT(12)
-#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
+#define ENETC_PM_IFM_FULL_DPX_IMX BIT(6)
+#define ENETC_PM_IFM_FULL_DPX_LS BIT(12)
+#define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0)
+#define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0)
+
+/* i.MX95 specific registers */
+#define IMX95_ENETC_SIPMAR0 0x80
+#define IMX95_ENETC_SIPMAR1 0x84
+
+/* Port registers */
+#define IMX95_ENETC_PMAR0 0x4020
+#define IMX95_ENETC_PMAR1 0x4024
+#define ENETC_POR 0x4100
/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER