* Patches by Denis Peter, 9 Sep 2003:
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index e2672f7..30dcdad 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -375,138 +375,6 @@
}
}
-/* ------------------------------------------------------------------------- */
-
- /* switches the cs0 and the cs1 to the locations.
- When boot is TRUE, the the mapping is switched
- to the boot configuration, If it is FALSE, the
- flash will be switched in the boot area */
-
-#undef SW_CS_DBG
-#ifdef SW_CS_DBG
-#define SW_CS_PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define SW_CS_PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int switch_cs(unsigned char boot)
-{
- unsigned long pbcr;
- int mode;
-
- mode=get_boot_mode();
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr (ebccfgd);
- if (mode & BOOT_MPS) {
- /* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
- /* we need only to switch if boot from MPS */
- /* printf(" MPS boot mode detected. ");*/
- /* printf("cs0 cfg: %lx\n",pbcr); */
- if(boot) {
- /* switch to boot configuration */
- /* this is a 8bit boot, switch cs0 to flash location */
- SW_CS_PRINTF("switch to boot mode (MPS on High address\n");
- pbcr&=0x000FFFFF; /*mask base address of the cs0 */
- pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
- mtdcr(ebccfga, pb0cr);
- mtdcr(ebccfgd, pbcr);
- SW_CS_PRINTF(" new cs0 cfg: %lx\n",pbcr);
- mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
- pbcr = mfdcr(ebccfgd);
- SW_CS_PRINTF(" old cs1 cfg: %lx\n",pbcr);
- pbcr&=0x000FFFFF; /*mask base address of the cs1 */
- pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
- mtdcr(ebccfga, pb1cr);
- mtdcr(ebccfgd, pbcr);
- SW_CS_PRINTF(" new cs1 cfg: %lx, MPS is on High Address\n",pbcr);
- }
- else {
- /* map flash to boot area, */
- SW_CS_PRINTF("map Flash to boot area\n");
- pbcr&=0x000FFFFF; /*mask base address of the cs0 */
- pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
- mtdcr(ebccfga, pb0cr);
- mtdcr(ebccfgd, pbcr);
- SW_CS_PRINTF(" new cs0 cfg: %lx\n",pbcr);
- mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
- pbcr = mfdcr(ebccfgd);
- SW_CS_PRINTF(" cs1 cfg: %lx\n",pbcr);
- pbcr&=0x000FFFFF; /*mask base address of the cs1 */
- pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
- mtdcr(ebccfga, pb1cr);
- mtdcr(ebccfgd, pbcr);
- SW_CS_PRINTF(" new cs1 cfg: %lx Flash is on High Address\n",pbcr);
- }
- return 1;
- }
- else {
- SW_CS_PRINTF("Normal boot, no switching necessary\n");
- return 0;
- }
-
-}
-
-int get_boot_mode(void)
-{
- unsigned long pbcr;
- int res = 0;
- pbcr = mfdcr (strap);
- if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
- /* boot via MPS or MPS mapping */
- res = BOOT_MPS;
- if(pbcr & PSR_ROM_LOC)
- /* boot via PCI.. */
- res |= BOOT_PCI;
- return res;
-}
-
-/* Setup cs0 parameter finally.
- Map the flash high (in boot area)
- This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
- unsigned long pbcr;
- /* Since we are relocated, we can set-up the CS finaly
- * but first of all, switch off PCI mapping (in case it was a PCI boot) */
- out32r(PMM0MA,0L);
- icache_enable (); /* we are relocated */
- /* for PCI Boot, we have to set-up the remaining CS correctly */
- pbcr = mfdcr (strap);
- if(pbcr & PSR_ROM_LOC) {
- /* boot via PCI.. */
- if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) {
- /* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
- #ifdef DEBUG
- printf("Mapping MPS to CS0 @ 0x%lx\n",(MPS_CR_B & 0xfff00000));
- #endif
- mtdcr (ebccfga, pb0ap);
- mtdcr (ebccfgd, MPS_AP);
- mtdcr (ebccfga, pb0cr);
- mtdcr (ebccfgd, MPS_CR_B);
- }
- else {
- /* Flash boot, set up the Flash on CS0 */
- #ifdef DEBUG
- printf("Mapping Flash to CS0 @ 0x%lx\n",(FLASH_CR_B & 0xfff00000));
- #endif
- mtdcr (ebccfga, pb0ap);
- mtdcr (ebccfgd, FLASH_AP);
- mtdcr (ebccfga, pb0cr);
- mtdcr (ebccfgd, FLASH_CR_B);
- }
- }
- switch_cs(0); /* map Flash High */
-}
-
-
-#elif defined(CONFIG_VCMA9)
-int switch_cs(unsigned char boot)
-{
- return 0;
-}
-#endif /* CONFIG_VCMA9 */
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@@ -625,6 +493,7 @@
#ifdef CONFIG_CONSOLE_EXTRA_INFO
extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
void video_get_info_str (int line_number, char *info)
{
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
index bcc7922..8f2ec03 100644
--- a/board/mpl/common/common_util.h
+++ b/board/mpl/common/common_util.h
@@ -31,10 +31,8 @@
} backup_t;
void get_backup_values(backup_t *buf);
-int switch_cs(unsigned char boot);
+
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-int get_boot_mode(void);
-void setup_cs_reloc(void);
#define BOOT_MPS 0x01
#define BOOT_PCI 0x02
#endif
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 4bdb8bd..99f97d7 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -39,6 +39,13 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include "common_util.h"
+#if defined(CONFIG_MIP405)
+#include "../mip405/mip405.h"
+#endif
+#if defined(CONFIG_PIP405)
+#include "../pip405/pip405.h"
+#endif
+#include <405gp_pci.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
@@ -66,23 +73,102 @@
#define TRUE 1
/*-----------------------------------------------------------------------
+ * Some CS switching routines:
+ *
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ *
+ * After flash detection we adjust the size of the CS area accordingly.
+ * The board_init_r will fill in wrong values in the board init structure,
+ * but this will be fixed in the misc_init_r routine:
+ * bd->bi_flashstart=0-flash_info[0].size
+ * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
+ * bd->bi_flashoffset=0
+ *
*/
+int get_boot_mode(void)
+{
+ unsigned long pbcr;
+ int res = 0;
+ pbcr = mfdcr (strap);
+ if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+ /* boot via MPS or MPS mapping */
+ res = BOOT_MPS;
+ if(pbcr & PSR_ROM_LOC)
+ /* boot via PCI.. */
+ res |= BOOT_PCI;
+ return res;
+}
+
+/* Map the flash high (in boot area)
+ This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+ int mode;
+ /* Since we are relocated, we can set-up the CS finaly
+ * but first of all, switch off PCI mapping (in case it was a PCI boot) */
+ out32r(PMM0MA,0L);
+ icache_enable (); /* we are relocated */
+ /* get boot mode */
+ mode=get_boot_mode();
+ /* we map the flash high in every case */
+ /* first findout on which cs the flash is */
+ if(mode & BOOT_MPS) {
+ /* map flash high on CS1 and MPS on CS0 */
+ mtdcr (ebccfga, pb0ap);
+ mtdcr (ebccfgd, MPS_AP);
+ mtdcr (ebccfga, pb0cr);
+ mtdcr (ebccfgd, MPS_CR);
+ /* we use the default values (max values) for the flash
+ * because its real size is not yet known */
+ mtdcr (ebccfga, pb1ap);
+ mtdcr (ebccfgd, FLASH_AP);
+ mtdcr (ebccfga, pb1cr);
+ mtdcr (ebccfgd, FLASH_CR_B);
+ }
+ else {
+ /* map flash high on CS0 and MPS on CS1 */
+ mtdcr (ebccfga, pb1ap);
+ mtdcr (ebccfgd, MPS_AP);
+ mtdcr (ebccfga, pb1cr);
+ mtdcr (ebccfgd, MPS_CR);
+ /* we use the default values (max values) for the flash
+ * because its real size is not yet known */
+ mtdcr (ebccfga, pb0ap);
+ mtdcr (ebccfgd, FLASH_AP);
+ mtdcr (ebccfga, pb0cr);
+ mtdcr (ebccfgd, FLASH_CR_B);
+ }
+}
+
unsigned long flash_init (void)
{
- unsigned long size_b0, size_b1;
- int i;
+ unsigned long size_b0, size_b1,flashcr;
+ int mode, i;
+ extern char version_string;
+ char *p=&version_string;
/* Since we are relocated, we can set-up the CS finally */
setup_cs_reloc();
/* get and display boot mode */
- i=get_boot_mode();
- if(i & BOOT_PCI)
- printf("(PCI Boot %s Map) ",(i & BOOT_MPS) ?
+ mode=get_boot_mode();
+ if(mode & BOOT_PCI)
+ printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
"MPS" : "Flash");
else
- printf("(%s Boot) ",(i & BOOT_MPS) ?
+ printf("(%s Boot) ",(mode & BOOT_MPS) ?
"MPS" : "Flash");
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -91,7 +177,7 @@
/* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -109,8 +195,31 @@
flash_info[0].protect[flash_info[0].sector_count-1] = 1;
size_b1 = 0 ;
flash_info[0].size = size_b0;
+ /* set up flash cs according to the size */
+ if(mode & BOOT_MPS) {
+ /* flash is on CS1 */
+ mtdcr(ebccfga, pb1cr);
+ flashcr = mfdcr (ebccfgd);
+ /* we map the flash high in every case */
+ flashcr&=0x0001FFFF; /* mask out address bits */
+ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+ flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+ mtdcr(ebccfga, pb1cr);
+ mtdcr(ebccfgd, flashcr);
+ }
+ else {
+ /* flash is on CS0 */
+ mtdcr(ebccfga, pb0cr);
+ flashcr = mfdcr (ebccfgd);
+ /* we map the flash high in every case */
+ flashcr&=0x0001FFFF; /* mask out address bits */
+ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+ flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, flashcr);
+ }
#if 0
- /* include this if you want to test if
+ /* enable this if you want to test if
the relocation has be done ok.
This will disable both Chipselects */
mtdcr (ebccfga, pb0cr);
@@ -119,6 +228,14 @@
mtdcr (ebccfgd, 0L);
printf("CS0 & CS1 switched off for test\n");
#endif
+ /* patch version_string */
+ for(i=0;i<0x100;i++) {
+ if(*p=='\n') {
+ *p=0;
+ break;
+ }
+ p++;
+ }
return (size_b0);
}
@@ -171,6 +288,8 @@
break;
case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n");
break;
+ case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
+ break;
default: printf ("Unknown Chip Type\n");
break;
}
@@ -211,7 +330,8 @@
/*-----------------------------------------------------------------------
- */
+
+*/
/*
* The following code cannot be run from FLASH!
@@ -220,7 +340,7 @@
{
short i;
FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
+ ulong base;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
@@ -250,7 +370,7 @@
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
- /* printf("Device value %x\n",value); */
+ /* printf("Device value %x\n",value); */
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
@@ -292,12 +412,17 @@
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
+ case (FLASH_WORD_SIZE)AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
@@ -328,10 +453,12 @@
return (0); /* => no or unknown flash */
}
-
+ /* base address calculation */
+ base=0-info->size;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)){
+ (info->flash_id == FLASH_AM040) ||
+ (info->flash_id == FLASH_AM640U)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
index 1788d51..793c34f 100644
--- a/board/mpl/common/isa.c
+++ b/board/mpl/common/isa.c
@@ -32,7 +32,6 @@
#include "kbd.h"
#include "video.h"
-extern int drv_isa_kbd_init (void);
#undef ISA_DEBUG
@@ -49,6 +48,9 @@
#define FALSE 0
#endif
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
/* fdc (logical device 0) */
const SIO_LOGDEV_TABLE sio_fdc[] = {
@@ -183,7 +185,7 @@
close_cfg_super_IO(0x3F0);
}
}
-
+#endif
/******************************************************************************
* IRQ Controller
@@ -202,7 +204,7 @@
/*
* This contains the irq mask for both 8259A irq controllers,
*/
-static unsigned int cached_irq_mask = 0xffff;
+static unsigned int cached_irq_mask = 0xfff9;
#define cached_imr1 (unsigned char)cached_irq_mask
#define cached_imr2 (unsigned char)(cached_irq_mask>>8)
@@ -387,19 +389,22 @@
isr2=in8(ISR_2);
isr1=in8(ISR_1);
irq=(unsigned char)irqack;
- if((irq==7)&&((isr1&0x80)==0)) {
+ irq-=32;
+/* if((irq==7)&&((isr1&0x80)==0)) {
PRINTF("IRQ7 detected but not in ISR\n");
}
else {
- /* we should handle cascaded interrupts here also */
- /* printf("ISA Irq %d\n",irq); */
- isa_irqs[irq].count++;
- if (isa_irqs[irq].handler != NULL)
- (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
- else
+*/ /* we should handle cascaded interrupts here also */
{
- PRINTF ("bogus interrupt vector 0x%x\n", irq);
- }
+/* printf("ISA Irq %d\n",irq); */
+ isa_irqs[irq].count++;
+ if(irq!=2) { /* just swallow the cascade irq 2 */
+ if (isa_irqs[irq].handler != NULL)
+ (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
+ else {
+ PRINTF ("bogus interrupt vector 0x%x\n", irq);
+ }
+ }
}
/* issue EOI instruction to clear the IRQ */
mask_and_ack_8259A(irq);
@@ -413,13 +418,13 @@
void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
- if (isa_irqs[vec].handler != NULL) {
- printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
- vec, (uint)handler, (uint)isa_irqs[vec].handler);
- }
- isa_irqs[vec].handler = handler;
- isa_irqs[vec].arg = arg;
- enable_8259A_irq(vec);
+ if (isa_irqs[vec].handler != NULL) {
+ printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+ vec, (uint)handler, (uint)isa_irqs[vec].handler);
+ }
+ isa_irqs[vec].handler = handler;
+ isa_irqs[vec].arg = arg;
+ enable_8259A_irq(vec);
PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
}
@@ -427,9 +432,9 @@
void isa_irq_free_handler(int vec)
{
disable_8259A_irq(vec);
- isa_irqs[vec].handler = NULL;
- isa_irqs[vec].arg = NULL;
- printf ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+ isa_irqs[vec].handler = NULL;
+ isa_irqs[vec].arg = NULL;
+ PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
}
@@ -448,16 +453,42 @@
init_8259A();
out8(IMR_2,0xFF);
}
+/*************************************************************************/
+void isa_show_irq(void)
+{
+ int vec;
+
+ printf ("\nISA Interrupt-Information:\n");
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<16; vec++) {
+ if (isa_irqs[vec].handler != NULL) {
+ printf ("%02d %08lx %08lx %d\n",
+ vec,
+ (ulong)isa_irqs[vec].handler,
+ (ulong)isa_irqs[vec].arg,
+ isa_irqs[vec].count);
+ }
+ }
+}
+
+int isa_irq_get_count(int vec)
+{
+ return(isa_irqs[vec].count);
+}
/******************************************************************
* Init the ISA bus and devices.
*/
+#if defined(CONFIG_PIP405)
int isa_init(void)
{
isa_sio_setup();
+ isa_init_irq_contr();
drv_isa_kbd_init();
return 0;
}
+#endif
diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h
index 578222d..28ed219 100644
--- a/board/mpl/common/isa.h
+++ b/board/mpl/common/isa.h
@@ -21,12 +21,12 @@
* MA 02111-1307 USA
*/
-#ifndef _PIP405_ISA_H_
-#define _PIP405_ISA_H_
+#ifndef _ISA_H_
+#define _ISA_H_
/* Super IO */
#define SIO_CFG_PORT 0x3F0 /* Config Port Address */
-
+#if defined(CONFIG_PIP405)
/* table fore SIO initialization */
typedef struct {
const uchar index;
@@ -44,10 +44,14 @@
void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
void close_cfg_super_IO(int address);
void isa_sio_setup(void);
-void isa_sio_setup(void);
+#endif
+
void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
void isa_irq_free_handler(int vec);
int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
#endif
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index e5627aa..a57b121 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -92,7 +92,7 @@
/* PIIX4 ISA Bridge Function 0 */
static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
{PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
- {PCI_CFG_PIIX4_GENCFG, 0x00010041, 4}, /* enable SERIRQs, ISA, PNP */
+ {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
{PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
{PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
{PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
@@ -106,6 +106,7 @@
/* PIIX4 IDE Controller Function 1 */
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+ {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
#if !defined(CONFIG_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
@@ -129,10 +130,10 @@
/* PIIX4 Power Management Function 3 */
static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
- {PCI_CFG_PIIX4_PMAB, 0x00004000, 4}, /* set PMBA to "valid" value */
- {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
+ {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
{PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
+ {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
+ {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
{ } /* end of device table */
};
/* PPC405 Dummy only used to prevent autosetup on this host bridge */
diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h
index 3c0523f..0ff802e 100644
--- a/board/mpl/common/piix4_pci.h
+++ b/board/mpl/common/piix4_pci.h
@@ -143,7 +143,7 @@
#define PCI_CFG_PIIX4_LEGSUP 0xC0
/* Function 3 Power Management */
-#define PCI_CFG_PIIX4_PMAB 0x40
+#define PCI_CFG_PIIX4_PMBA 0x40
#define PCI_CFG_PIIX4_CNTA 0x44
#define PCI_CFG_PIIX4_CNTB 0x48
#define PCI_CFG_PIIX4_GPICTL 0x4C