tree 45d4979a52bb5f62d9e95d0d178df967090b78ab
parent 804a50b0032c25bb76e0ffb9f595e5cdc168de72
author Dinh Nguyen <dinguyen@opensource.altera.com> 1427752865 -0500
committer Marek Vasut <marex@denx.de> 1429611796 +0200

arm: socfpga: spl: enable sdram, timer and uart

Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>