Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.

commit: 2a8bc03c860f913f8adf9bda8279ee9b718fc786 [log] [tgz]
author: Tom Rini <trini@konsulko.com> Mon Oct 05 10:54:27 2020 -0400
committer: Tom Rini <trini@konsulko.com> Mon Oct 05 10:54:27 2020 -0400
tree: 24fcdb0737bea1d87c0a36f7eb371017af83e5c2
parent: 8ac4a898eb101112d8703cb8f706ff47f637c38f [diff]
parent: 929f5cc1859dd679a6d8c5044760198c3e31fda2 [diff]
diff --git a/Kconfig b/Kconfig
index 883e3f7..837b2f5 100644
--- a/Kconfig
+++ b/Kconfig

@@ -659,12 +659,11 @@
 
 config USE_SPL_FIT_GENERATOR
 	bool "Use a script to generate the .its script"
-	default y if SPL_FIT
+	default y if SPL_FIT && !ARCH_SUNXI
 
 config SPL_FIT_GENERATOR
 	string ".its file generator script for U-Boot FIT image"
 	depends on USE_SPL_FIT_GENERATOR
-	default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
 	default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
 	default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
 	default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV

diff --git a/MAINTAINERS b/MAINTAINERS
index 91b06b4..85babd1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS

@@ -237,6 +237,10 @@
 M:	Luka Perkov <luka.perkov@sartura.hr>
 S:	Maintained
 F:	arch/arm/mach-ipq40xx/
+F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
+F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
+F:	drivers/reset/reset-ipq4019.c
+F:	drivers/phy/phy-qcom-ipq4019-usb.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
@@ -601,6 +605,8 @@
 
 BTRFS
 M:	Marek Behun <marek.behun@nic.cz>
+R:	Qu Wenruo <wqu@suse.com>
+L:	linux-btrfs@vger.kernel.org
 S:	Maintained
 F:	cmd/btrfs.c
 F:	fs/btrfs/
@@ -1007,6 +1013,10 @@
 F:	arch/arm/dts/ns3.dtsi
 F:	arch/arm/cpu/armv8/bcmns3
 F:	arch/arm/include/asm/arch-bcmns3/
+F:	cmd/broadcom/Makefile
+F:	cmd/broadcom/chimp_boot.c
+F:	cmd/broadcom/nitro_image_load.c
+F:	cmd/broadcom/chimp_handshake.c
 
 TDA19988 HDMI ENCODER
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>

diff --git a/Makefile b/Makefile
index dd98b43..2de0527 100644
--- a/Makefile
+++ b/Makefile

@@ -923,11 +923,6 @@
 INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi
 INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 
-# Build a combined spl + u-boot image for sunxi
-ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64)$(CONFIG_SPL),yyy)
-INPUTS-y += u-boot-sunxi-with-spl.bin
-endif
-
 # Generate this input file for binman
 ifeq ($(CONFIG_SPL),)
 INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
@@ -1024,13 +1019,9 @@
 inputs: $(INPUTS-y)
 
 all: .binman_stamp inputs
-# Hack for sunxi which doesn't have a proper binman definition for
-# 64-bit boards
-ifneq ($(CONFIG_ARCH_SUNXI)$(CONFIG_ARM64),yy)
 ifeq ($(CONFIG_BINMAN),y)
 	$(call if_changed,binman)
 endif
-endif
 
 # Timestamp file to make sure that binman always runs
 .binman_stamp: FORCE
@@ -1330,13 +1321,16 @@
 # binman
 # ---------------------------------------------------------------------------
 # Use 'make BINMAN_DEBUG=1' to enable debugging
+default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
-		build -u -d u-boot.dtb -O . \
-		$(if $(BUILD_ROM),,-m --allow-missing) \
+		build -u -d u-boot.dtb -O . -m --allow-missing \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
+		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
+		-a atf-bl31-path=${BL31} \
+		-a default-dt=$(default_dt) \
 		$(BINMAN_$(@F))
 
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1626,13 +1620,6 @@
 
 endif # CONFIG_X86
 
-ifneq ($(CONFIG_ARCH_SUNXI),)
-ifeq ($(CONFIG_ARM64),y)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
-	$(call if_changed,cat)
-endif
-endif
-
 OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
 u-boot-app.efi: u-boot FORCE
 	$(call if_changed,zobjcopy)

diff --git a/README b/README
index 6cb0567..5132b22 100644
--- a/README
+++ b/README

@@ -3425,6 +3425,10 @@
   mempos	- Index position of the last match found by the 'ms' command,
 		  in units of the size (.b, .w, .l) of the search
 
+  zbootbase	- (x86 only) Base address of the bzImage 'setup' block
+
+  zbootaddr	- (x86 only) Address of the loaded bzImage, typically
+		  BZIMAGE_LOAD_ADDR which is 0x100000
 
 The following image location variables contain the location of images
 used in booting. The "Image" column gives the role of the image and is

diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c
index 51cd328..e150966 100644
--- a/api/api_platform-mips.c
+++ b/api/api_platform-mips.c

@@ -24,8 +24,7 @@
 int platform_sys_info(struct sys_info *si)
 {
 
-	platform_set_mr(si, gd->bd->bi_memstart,
-			gd->bd->bi_memsize, MR_ATTR_DRAM);
+	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
 
 	return 1;
 }

diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 15930cf..847a4a3 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c

@@ -42,7 +42,7 @@
 	si->bar = 0;
 #endif
 
-	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
+	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
 	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
 	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
 

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c2..abbc89a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig

@@ -16,8 +16,8 @@
 	help
 	  U-Boot expects to be linked to a specific hard-coded address, and to
 	  be loaded to and run from that address. This option lifts that
-	  restriction, thus allowing the code to be loaded to and executed
-	  from almost any address. This logic relies on the relocation
+	  restriction, thus allowing the code to be loaded to and executed from
+	  almost any 4K aligned address. This logic relies on the relocation
 	  information that is embedded in the binary to support U-Boot
 	  relocating itself to the top-of-RAM later during execution.
 
@@ -767,8 +767,11 @@
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select DM_RESET
+	select MSM_SMEM
 	select PINCTRL
 	select CLK
+	select SMEM
 	select OF_CONTROL
 	imply CMD_DM
 
@@ -940,9 +943,9 @@
 
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
-	select BOARD_EARLY_INIT_F if !RZA1
 	select DM
 	select DM_SERIAL
+	imply BOARD_EARLY_INIT_F
 	imply CMD_DM
 	imply FAT_WRITE
 	imply SYS_THUMB_BUILD
@@ -1152,7 +1155,8 @@
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
-	select SPL_DM_SPI if SPI
+	select SPL_DM if SPL
+	select SPL_DM_SPI if SPI && SPL_DM
 	select SPL_DM_SPI_FLASH if SPL_DM_SPI
 	select SPL_DM_MAILBOX if SPL
 	select SPL_FIRMWARE if SPL
@@ -1997,10 +2001,6 @@
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
-source "board/xilinx/Kconfig"
-source "board/xilinx/zynq/Kconfig"
-source "board/xilinx/zynqmp/Kconfig"
-source "board/xilinx/versal/Kconfig"
 source "board/phytium/durian/Kconfig"
 source "board/xen/xenguest_arm64/Kconfig"
 

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 002698b..e5c2856 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S

@@ -59,6 +59,23 @@
 save_boot_params_ret:
 
 #if CONFIG_POSITION_INDEPENDENT
+	/* Verify that we're 4K aligned.  */
+	adr	x0, _start
+	ands	x0, x0, #0xfff
+	b.eq	1f
+0:
+	/*
+	 * FATAL, can't continue.
+	 * U-Boot needs to be loaded at a 4K aligned address.
+	 *
+	 * We use ADRP and ADD to load some symbol addresses during startup.
+	 * The ADD uses an absolute (non pc-relative) lo12 relocation
+	 * thus requiring 4K alignment.
+	 */
+	wfi
+	b	0b
+1:
+
 	/*
 	 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
 	 * executed at a different address than it was linked at.
@@ -67,8 +84,10 @@
 	adr	x0, _start		/* x0 <- Runtime value of _start */
 	ldr	x1, _TEXT_BASE		/* x1 <- Linked value of _start */
 	sub	x9, x0, x1		/* x9 <- Run-vs-link offset */
-	adr	x2, __rel_dyn_start	/* x2 <- Runtime &__rel_dyn_start */
-	adr	x3, __rel_dyn_end	/* x3 <- Runtime &__rel_dyn_end */
+	adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
+	add     x2, x2, #:lo12:__rel_dyn_start
+	adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
+	add     x3, x3, #:lo12:__rel_dyn_end
 pie_fix_loop:
 	ldp	x0, x1, [x2], #16	/* (x0, x1) <- (Link location, fixup) */
 	ldr	x4, [x2], #8		/* x4 <- addend */

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f5294..72b6fe1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile

@@ -938,7 +938,7 @@
 
 dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
 
-dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
+dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 

diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 37484cb..2a1b3a5 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts

@@ -436,3 +436,53 @@
 		reg = <3>;
 	};
 };
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins_default>;
+
+	sn65hvs882@1 {
+		compatible = "pisosr-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		spi-cpol;
+	};
+
+	spi_nor: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64", "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+		reg = <0>;
+
+		partition@0 {
+			label = "u-boot-spl";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@1 {
+			label = "u-boot";
+			reg = <0x80000 0x100000>;
+			read-only;
+		};
+
+		partition@2 {
+			label = "u-boot-env";
+			reg = <0x180000 0x20000>;
+			read-only;
+		};
+
+		partition@3 {
+			label = "misc";
+			reg = <0x1A0000 0x660000>;
+		};
+	};
+};

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 8ac4215..51a5244 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi

@@ -1,4 +1,5 @@
-#include <dt-bindings/clock/ast2500-scu.h>
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
@@ -25,7 +26,7 @@
 		reg = <0x1e6e0000 0x174
 			0x1e6e0200 0x1d4 >;
 		#reset-cells = <1>;
-		clocks = <&scu PLL_MPLL>;
+		clocks = <&scu ASPEED_CLK_MPLL>;
 		resets = <&rst AST_RESET_SDRAM>;
 	};
 
@@ -39,7 +40,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740100>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 
@@ -47,7 +48,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740200>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 		};
@@ -56,23 +57,23 @@
 };
 
 &uart1 {
-	clocks = <&scu PCLK_UART1>;
+	clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
 };
 
 &uart2 {
-	clocks = <&scu PCLK_UART2>;
+	clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
 };
 
 &uart3 {
-	clocks = <&scu PCLK_UART3>;
+	clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
 };
 
 &uart4 {
-	clocks = <&scu PCLK_UART4>;
+	clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
 };
 
 &uart5 {
-	clocks = <&scu PCLK_UART5>;
+	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
 };
 
 &timer {
@@ -80,9 +81,9 @@
 };
 
 &mac0 {
-	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
 
 &mac1 {
-	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 4972a75..0a5faa2 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi

@@ -131,3 +131,31 @@
 	dr_mode = "peripheral";
 	u-boot,dm-spl;
 };
+
+&wkup_gpio_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+	u-boot,dm-spl;
+};
+
+&mcu_fss0_hpb0_pins_default {
+	u-boot,dm-spl;
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&hbmc {
+	u-boot,dm-spl;
+
+	flash@0,0 {
+		u-boot,dm-spl;
+	};
+};
+
+&hbmc_mux {
+	u-boot,dm-spl;
+};

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 3f1d03c..cc3d933 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts

@@ -13,6 +13,13 @@
 		stdout-path = "serial2:115200n8";
 		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
 	};
+
+	aliases {
+		remoteproc0 = &mcu_r5fss0_core0;
+		remoteproc1 = &mcu_r5fss0_core1;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
+	};
 };
 
 &wkup_pmx0 {

diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index aaa1fdd..c25f03c 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi

@@ -340,4 +340,44 @@
 			dr_mode = "otg";
 		};
 	};
+
+	main_r5fss0: r5fss@5c00000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+			 <0x5d00000 0x00 0x5d00000 0x20000>;
+		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f@5c00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5c00000 0x00010000>,
+			      <0x5c10000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <245>;
+			ti,sci-proc-ids = <0x06 0xFF>;
+			resets = <&k3_reset 245 1>;
+			firmware-name = "j7200-main-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f@5d00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5d00000 0x00008000>,
+			      <0x5d10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <246>;
+			ti,sci-proc-ids = <0x07 0xFF>;
+			resets = <&k3_reset 246 1>;
+			firmware-name = "j7200-main-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };

diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 4c899c8..75c0c85 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi

@@ -269,4 +269,44 @@
 			ti,cpts-periodic-outputs = <2>;
 		};
 	};
+
+	mcu_r5fss0: r5fss@41000000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x41000000 0x00 0x41000000 0x20000>,
+			 <0x41400000 0x00 0x41400000 0x20000>;
+		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+		mcu_r5fss0_core0: r5f@41000000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41000000 0x00010000>,
+			      <0x41010000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <250>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 250 1>;
+			firmware-name = "j7200-mcu-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		mcu_r5fss0_core1: r5f@41400000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41400000 0x00008000>,
+			      <0x41410000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <251>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 251 1>;
+			firmware-name = "j7200-mcu-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f5e4166..db63d93 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts

@@ -18,8 +18,14 @@
 	chosen {
 		stdout-path = &main_uart0;
 		tick-timer = &timer1;
+		firmware-loader = &fs_loader0;
 	};
 
+	fs_loader0: fs_loader@0 {
+		u-boot,dm-pre-reloc;
+		compatible = "u-boot,fs-loader";
+	};
+
 	a72_0: a72@0 {
 		compatible = "ti,am654-rproc";
 		reg = <0x0 0x00a90000 0x0 0x10>;
@@ -107,6 +113,31 @@
 			J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
 		>;
 	};
+
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+		>;
+	};
+
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+		>;
+	};
 };
 
 &main_pmx0 {
@@ -214,4 +245,19 @@
 	maximum-speed = "high-speed";
 };
 
+&hbmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+	flash@0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+	};
+};
+
 #include "k3-j7200-common-proc-board-u-boot.dtsi"

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index a285b1a..33db74a 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi

@@ -302,7 +302,7 @@
 
 	main_r5fss1: r5fss@5e00000 {
 		compatible = "ti,j721e-r5fss";
-		lockstep-mode = <1>;
+		lockstep-mode = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,

diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 5f78bc5..e0e4188 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi

@@ -10,6 +10,8 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
 
 / {
 	#address-cells = <1>;
@@ -38,6 +40,11 @@
 		};
 	};
 
+	smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -52,6 +59,14 @@
 			u-boot,dm-pre-reloc;
 		};
 
+		reset: gcc-reset@1800000 {
+			compatible = "qcom,gcc-reset-ipq4019";
+			reg = <0x1800000 0x60000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
 		pinctrl: qcom,tlmm@1000000 {
 			compatible = "qcom,tlmm-ipq4019";
 			reg = <0x1000000 0x300000>;
@@ -61,7 +76,7 @@
 		blsp1_uart1: serial@78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78af000 0x200>;
-			clock = <&gcc 26>;
+			clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
 			bit-rate = <0xFF>;
 			status = "disabled";
 			u-boot,dm-pre-reloc;
@@ -75,5 +90,81 @@
 			gpio-bank-name="soc";
 			#gpio-cells = <2>;
 		};
+
+		usb3_ss_phy: ssphy@9a000 {
+			compatible = "qcom,usb-ss-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0x9a000 0x800>;
+			reg-names = "phy_base";
+			resets = <&reset USB3_UNIPHY_PHY_ARES>;
+			reset-names = "por_rst";
+			status = "disabled";
+		};
+
+		usb3_hs_phy: hsphy@a6000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa6000 0x40>;
+			reg-names = "phy_base";
+			resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb3: usb3@8af8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x8af8800 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gcc GCC_USB3_MASTER_CLK>,
+				 <&gcc GCC_USB3_SLEEP_CLK>,
+				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+			clock-names = "master", "sleep", "mock_utmi";
+			ranges;
+			status = "disabled";
+
+			dwc3@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x8a00000 0xf8000>;
+				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				dr_mode = "host";
+				maximum-speed = "super-speed";
+				snps,dis_u2_susphy_quirk;
+			};
+		};
+
+		usb2_hs_phy: hsphy@a8000 {
+			compatible = "qcom,usb-hs-ipq4019-phy";
+			#phy-cells = <0>;
+			reg = <0xa8000 0x40>;
+			reg-names = "phy_base";
+			resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
+			reset-names = "por_rst", "srif_rst";
+			status = "disabled";
+		};
+
+		usb2: usb2@60f8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x60f8800 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gcc GCC_USB2_MASTER_CLK>,
+				 <&gcc GCC_USB2_SLEEP_CLK>,
+				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+			clock-names = "master", "sleep", "mock_utmi";
+			ranges;
+			status = "disabled";
+
+			dwc3@6000000 {
+				compatible = "snps,dwc3";
+				reg = <0x6000000 0xf8000>;
+				phys = <&usb2_hs_phy>;
+				phy-names = "usb2-phy";
+				dr_mode = "host";
+				maximum-speed = "high-speed";
+				snps,dis_u2_susphy_quirk;
+			};
+		};
 	};
 };

diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi
index a603d94..8e80f50 100644
--- a/arch/arm/dts/r8a774a1.dtsi
+++ b/arch/arm/dts/r8a774a1.dtsi

@@ -10,6 +10,8 @@
 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
 #include <dt-bindings/power/r8a774a1-sysc.h>
 
+#define CPG_AUDIO_CLK_I		R8A774A1_CLK_S0D4
+
 / {
 	compatible = "renesas,r8a774a1";
 	#address-cells = <2>;
@@ -2250,7 +2252,7 @@
 			status = "disabled";
 		};
 
-		sdhi0: sd@ee100000 {
+		sdhi0: mmc@ee100000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee100000 0 0x2000>;
@@ -2262,7 +2264,7 @@
 			status = "disabled";
 		};
 
-		sdhi1: sd@ee120000 {
+		sdhi1: mmc@ee120000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee120000 0 0x2000>;
@@ -2274,7 +2276,7 @@
 			status = "disabled";
 		};
 
-		sdhi2: sd@ee140000 {
+		sdhi2: mmc@ee140000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee140000 0 0x2000>;
@@ -2286,7 +2288,7 @@
 			status = "disabled";
 		};
 
-		sdhi3: sd@ee160000 {
+		sdhi3: mmc@ee160000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee160000 0 0x2000>;

diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi
new file mode 100644
index 0000000..23119c0
--- /dev/null
+++ b/arch/arm/dts/r8a774b1.dtsi

@@ -0,0 +1,2630 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774b1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
+#include <dt-bindings/power/r8a774b1-sysc.h>
+
+#define CPG_AUDIO_CLK_I		R8A774B1_CLK_S0D4
+
+/ {
+	compatible = "renesas,r8a774b1";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/*
+	 * The external audio clocks are configured as 0 Hz fixed frequency
+	 * clocks by default.
+	 * Boards that provide audio clocks should override them.
+	 */
+	audio_clk_a: audio_clk_a {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_b: audio_clk_b {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_c: audio_clk_c {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a57_0: cpu@0 {
+			compatible = "arm,cortex-a57";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <854>;
+			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		a57_1: cpu@1 {
+			compatible = "arm,cortex-a57";
+			reg = <0x1>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		L2_CA57: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* External PCIe clock - can be overridden by the board */
+	pcie_bus_clk: pcie_bus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
+		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a57_0>, <&a57_1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a774b1-wdt",
+				     "renesas,rcar-gen3-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
+			status = "disabled";
+		};
+
+		gpio0: gpio@e6050000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio@e6051000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 29>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio@e6052000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 15>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio@e6053000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio@e6054000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio@e6055000 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 26>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio@e6055400 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 906>;
+		};
+
+		gpio7: gpio@e6055800 {
+			compatible = "renesas,gpio-r8a774b1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055800 0 0x50>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 224 4>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 905>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 905>;
+		};
+
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,pfc-r8a774b1";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
+		cmt0: timer@e60f0000 {
+			compatible = "renesas,r8a774b1-cmt0",
+				     "renesas,rcar-gen3-cmt0";
+			reg = <0 0xe60f0000 0 0x1004>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 303>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 303>;
+			status = "disabled";
+		};
+
+		cmt1: timer@e6130000 {
+			compatible = "renesas,r8a774b1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6130000 0 0x1004>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 302>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 302>;
+			status = "disabled";
+		};
+
+		cmt2: timer@e6140000 {
+			compatible = "renesas,r8a774b1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6140000 0 0x1004>;
+			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 301>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 301>;
+			status = "disabled";
+		};
+
+		cmt3: timer@e6148000 {
+			compatible = "renesas,r8a774b1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6148000 0 0x1004>;
+			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 300>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 300>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a774b1-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a774b1-rst";
+			reg = <0 0xe6160000 0 0x0200>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a774b1-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		tsc: thermal@e6198000 {
+			compatible = "renesas,r8a774b1-thermal";
+			reg = <0 0xe6198000 0 0x100>,
+			      <0 0xe61a0000 0 0x100>,
+			      <0 0xe61a8000 0 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 522>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 522>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		intc_ex: interrupt-controller@e61c0000 {
+			compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
+		tmu0: timer@e61e0000 {
+			compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
+			reg = <0 0xe61e0000 0 0x30>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 125>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 125>;
+			status = "disabled";
+		};
+
+		tmu1: timer@e6fc0000 {
+			compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
+			reg = <0 0xe6fc0000 0 0x30>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 124>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 124>;
+			status = "disabled";
+		};
+
+		tmu2: timer@e6fd0000 {
+			compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
+			reg = <0 0xe6fd0000 0 0x30>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 123>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 123>;
+			status = "disabled";
+		};
+
+		tmu3: timer@e6fe0000 {
+			compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
+			reg = <0 0xe6fe0000 0 0x30>;
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 122>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 122>;
+			status = "disabled";
+		};
+
+		tmu4: timer@ffc00000 {
+			compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
+			reg = <0 0xffc00000 0 0x30>;
+			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 121>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 121>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 931>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 930>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 929>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 928>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 927>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 919>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774b1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 918>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c_dvfs: i2c@e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a774b1",
+				     "renesas,rcar-gen3-iic",
+				     "renesas,rmobile-iic";
+			reg = <0 0xe60b0000 0 0x425>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 926>;
+			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a774b1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 520>;
+			status = "disabled";
+		};
+
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a774b1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 0x60>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+			       <&dmac2 0x33>, <&dmac2 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 519>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a774b1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 0x60>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+			       <&dmac2 0x35>, <&dmac2 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 518>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a774b1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		hscif4: serial@e66b0000 {
+			compatible = "renesas,hscif-r8a774b1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66b0000 0 0x60>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 516>;
+			status = "disabled";
+		};
+
+		hsusb: usb@e6590000 {
+			compatible = "renesas,usbhs-r8a774b1",
+				     "renesas,rcar-gen3-usbhs";
+			reg = <0 0xe6590000 0 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
+			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+			dma-names = "ch0", "ch1", "ch2", "ch3";
+			renesas,buswait = <11>;
+			phys = <&usb2_phy0 3>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 704>, <&cpg 703>;
+			status = "disabled";
+		};
+
+		usb_dmac0: dma-controller@e65a0000 {
+			compatible = "renesas,r8a774b1-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65a0000 0 0x100>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 330>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 330>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
+		usb_dmac1: dma-controller@e65b0000 {
+			compatible = "renesas,r8a774b1-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65b0000 0 0x100>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 331>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 331>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
+		usb3_phy0: usb-phy@e65ee000 {
+			compatible = "renesas,r8a774b1-usb3-phy",
+				     "renesas,rcar-gen3-usb3-phy";
+			reg = <0 0xe65ee000 0 0x90>;
+			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+				 <&usb_extal_clk>;
+			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 328>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		dmac0: dma-controller@e6700000 {
+			compatible = "renesas,dmac-r8a774b1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe6700000 0 0x10000>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 219>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 219>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+		};
+
+		dmac1: dma-controller@e7300000 {
+			compatible = "renesas,dmac-r8a774b1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7300000 0 0x10000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 218>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 218>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+		};
+
+		dmac2: dma-controller@e7310000 {
+			compatible = "renesas,dmac-r8a774b1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7310000 0 0x10000>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 217>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 217>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+		};
+
+		ipmmu_ds0: iommu@e6740000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xe6740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 0>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_ds1: iommu@e7740000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xe7740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 1>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_hc: iommu@e6570000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xe6570000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 2>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mm: iommu@e67b0000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xe67b0000 0 0x1000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mp: iommu@ec670000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xec670000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 4>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv0: iommu@fd800000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xfd800000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 6>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vc0: iommu@fe6b0000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xfe6b0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 12>;
+			power-domains = <&sysc R8A774B1_PD_A3VC>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vi0: iommu@febd0000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xfebd0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 14>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vp0: iommu@fe990000 {
+			compatible = "renesas,ipmmu-r8a774b1";
+			reg = <0 0xfe990000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 16>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			#iommu-cells = <1>;
+		};
+
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a774b1",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii";
+			iommus = <&ipmmu_ds0 16>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		can0: can@e6c30000 {
+			compatible = "renesas,can-r8a774b1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c30000 0 0x1000>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>,
+				 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 916>;
+			status = "disabled";
+		};
+
+		can1: can@e6c38000 {
+			compatible = "renesas,can-r8a774b1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c38000 0 0x1000>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>,
+				 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 915>;
+			status = "disabled";
+		};
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a774b1-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+				 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 914>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+		pwm0: pwm@e6e30000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e30000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@e6e31000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e31000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm2: pwm@e6e32000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e32000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm3: pwm@e6e33000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e33000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm4: pwm@e6e34000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e34000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm5: pwm@e6e35000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e35000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pwm6: pwm@e6e36000 {
+			compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
+			reg = <0 0xe6e36000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 0x40>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 207>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+			       <&dmac2 0x51>, <&dmac2 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 207>;
+			status = "disabled";
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 0x40>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 206>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+			       <&dmac2 0x53>, <&dmac2 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 206>;
+			status = "disabled";
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 0x40>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+			       <&dmac2 0x13>, <&dmac2 0x12>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		scif3: serial@e6c50000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c50000 0 0x40>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 204>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 204>;
+			status = "disabled";
+		};
+
+		scif4: serial@e6c40000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 0x40>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 203>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 203>;
+			status = "disabled";
+		};
+
+		scif5: serial@e6f30000 {
+			compatible = "renesas,scif-r8a774b1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6f30000 0 0x40>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 202>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 202>;
+			status = "disabled";
+		};
+
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		vin0: video@e6ef0000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef0000 0 0x1000>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 811>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 811>;
+			renesas,id = <0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin0csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin0>;
+					};
+					vin0csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin0>;
+					};
+				};
+			};
+		};
+
+		vin1: video@e6ef1000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef1000 0 0x1000>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 810>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 810>;
+			renesas,id = <1>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin1csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin1>;
+					};
+					vin1csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin1>;
+					};
+				};
+			};
+		};
+
+		vin2: video@e6ef2000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef2000 0 0x1000>;
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 809>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 809>;
+			renesas,id = <2>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin2csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin2>;
+					};
+					vin2csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin2>;
+					};
+				};
+			};
+		};
+
+		vin3: video@e6ef3000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef3000 0 0x1000>;
+			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 808>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 808>;
+			renesas,id = <3>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin3csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin3>;
+					};
+					vin3csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin3>;
+					};
+				};
+			};
+		};
+
+		vin4: video@e6ef4000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef4000 0 0x1000>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 807>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 807>;
+			renesas,id = <4>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin4csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin4>;
+					};
+					vin4csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin4>;
+					};
+				};
+			};
+		};
+
+		vin5: video@e6ef5000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef5000 0 0x1000>;
+			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 806>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 806>;
+			renesas,id = <5>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin5csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin5>;
+					};
+					vin5csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin5>;
+					};
+				};
+			};
+		};
+
+		vin6: video@e6ef6000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef6000 0 0x1000>;
+			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 805>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 805>;
+			renesas,id = <6>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin6csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin6>;
+					};
+					vin6csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin6>;
+					};
+				};
+			};
+		};
+
+		vin7: video@e6ef7000 {
+			compatible = "renesas,vin-r8a774b1";
+			reg = <0 0xe6ef7000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 804>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 804>;
+			renesas,id = <7>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin7csi20: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&csi20vin7>;
+					};
+					vin7csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&csi40vin7>;
+					};
+				};
+			};
+		};
+
+		rcar_sound: sound@ec500000 {
+			/*
+			 * #sound-dai-cells is required
+			 *
+			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
+			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
+			 */
+			/*
+			 * #clock-cells is required for audio_clkout0/1/2/3
+			 *
+			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
+			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
+			 */
+			compatible =  "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
+			reg = <0 0xec500000 0 0x1000>, /* SCU */
+			      <0 0xec5a0000 0 0x100>,  /* ADG */
+			      <0 0xec540000 0 0x1000>, /* SSIU */
+			      <0 0xec541000 0 0x280>,  /* SSI */
+			      <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
+			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+			clocks = <&cpg CPG_MOD 1005>,
+				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+				 <&audio_clk_a>, <&audio_clk_b>,
+				 <&audio_clk_c>,
+				 <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
+			clock-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0",
+				      "src.9", "src.8", "src.7", "src.6",
+				      "src.5", "src.4", "src.3", "src.2",
+				      "src.1", "src.0",
+				      "mix.1", "mix.0",
+				      "ctu.1", "ctu.0",
+				      "dvc.0", "dvc.1",
+				      "clk_a", "clk_b", "clk_c", "clk_i";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 1005>,
+				 <&cpg 1006>, <&cpg 1007>,
+				 <&cpg 1008>, <&cpg 1009>,
+				 <&cpg 1010>, <&cpg 1011>,
+				 <&cpg 1012>, <&cpg 1013>,
+				 <&cpg 1014>, <&cpg 1015>;
+			reset-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0";
+			status = "disabled";
+
+			rcar_sound,ctu {
+				ctu00: ctu-0 { };
+				ctu01: ctu-1 { };
+				ctu02: ctu-2 { };
+				ctu03: ctu-3 { };
+				ctu10: ctu-4 { };
+				ctu11: ctu-5 { };
+				ctu12: ctu-6 { };
+				ctu13: ctu-7 { };
+			};
+
+			rcar_sound,dvc {
+				dvc0: dvc-0 {
+					dmas = <&audma1 0xbc>;
+					dma-names = "tx";
+				};
+				dvc1: dvc-1 {
+					dmas = <&audma1 0xbe>;
+					dma-names = "tx";
+				};
+			};
+
+			rcar_sound,mix {
+				mix0: mix-0 { };
+				mix1: mix-1 { };
+			};
+
+			rcar_sound,src {
+				src0: src-0 {
+					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x85>, <&audma1 0x9a>;
+					dma-names = "rx", "tx";
+				};
+				src1: src-1 {
+					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x87>, <&audma1 0x9c>;
+					dma-names = "rx", "tx";
+				};
+				src2: src-2 {
+					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x89>, <&audma1 0x9e>;
+					dma-names = "rx", "tx";
+				};
+				src3: src-3 {
+					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+					dma-names = "rx", "tx";
+				};
+				src4: src-4 {
+					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+					dma-names = "rx", "tx";
+				};
+				src5: src-5 {
+					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+					dma-names = "rx", "tx";
+				};
+				src6: src-6 {
+					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x91>, <&audma1 0xb4>;
+					dma-names = "rx", "tx";
+				};
+				src7: src-7 {
+					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x93>, <&audma1 0xb6>;
+					dma-names = "rx", "tx";
+				};
+				src8: src-8 {
+					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x95>, <&audma1 0xb8>;
+					dma-names = "rx", "tx";
+				};
+				src9: src-9 {
+					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x97>, <&audma1 0xba>;
+					dma-names = "rx", "tx";
+				};
+			};
+
+			rcar_sound,ssi {
+				ssi0: ssi-0 {
+					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x01>, <&audma1 0x02>;
+					dma-names = "rx", "tx";
+				};
+				ssi1: ssi-1 {
+					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x03>, <&audma1 0x04>;
+					dma-names = "rx", "tx";
+				};
+				ssi2: ssi-2 {
+					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x05>, <&audma1 0x06>;
+					dma-names = "rx", "tx";
+				};
+				ssi3: ssi-3 {
+					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x07>, <&audma1 0x08>;
+					dma-names = "rx", "tx";
+				};
+				ssi4: ssi-4 {
+					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x09>, <&audma1 0x0a>;
+					dma-names = "rx", "tx";
+				};
+				ssi5: ssi-5 {
+					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+					dma-names = "rx", "tx";
+				};
+				ssi6: ssi-6 {
+					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+					dma-names = "rx", "tx";
+				};
+				ssi7: ssi-7 {
+					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0f>, <&audma1 0x10>;
+					dma-names = "rx", "tx";
+				};
+				ssi8: ssi-8 {
+					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x11>, <&audma1 0x12>;
+					dma-names = "rx", "tx";
+				};
+				ssi9: ssi-9 {
+					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x13>, <&audma1 0x14>;
+					dma-names = "rx", "tx";
+				};
+			};
+
+			rcar_sound,ssiu {
+				ssiu00: ssiu-0 {
+					dmas = <&audma0 0x15>, <&audma1 0x16>;
+					dma-names = "rx", "tx";
+				};
+				ssiu01: ssiu-1 {
+					dmas = <&audma0 0x35>, <&audma1 0x36>;
+					dma-names = "rx", "tx";
+				};
+				ssiu02: ssiu-2 {
+					dmas = <&audma0 0x37>, <&audma1 0x38>;
+					dma-names = "rx", "tx";
+				};
+				ssiu03: ssiu-3 {
+					dmas = <&audma0 0x47>, <&audma1 0x48>;
+					dma-names = "rx", "tx";
+				};
+				ssiu04: ssiu-4 {
+					dmas = <&audma0 0x3F>, <&audma1 0x40>;
+					dma-names = "rx", "tx";
+				};
+				ssiu05: ssiu-5 {
+					dmas = <&audma0 0x43>, <&audma1 0x44>;
+					dma-names = "rx", "tx";
+				};
+				ssiu06: ssiu-6 {
+					dmas = <&audma0 0x4F>, <&audma1 0x50>;
+					dma-names = "rx", "tx";
+				};
+				ssiu07: ssiu-7 {
+					dmas = <&audma0 0x53>, <&audma1 0x54>;
+					dma-names = "rx", "tx";
+				};
+				ssiu10: ssiu-8 {
+					dmas = <&audma0 0x49>, <&audma1 0x4a>;
+					dma-names = "rx", "tx";
+				};
+				ssiu11: ssiu-9 {
+					dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+					dma-names = "rx", "tx";
+				};
+				ssiu12: ssiu-10 {
+					dmas = <&audma0 0x57>, <&audma1 0x58>;
+					dma-names = "rx", "tx";
+				};
+				ssiu13: ssiu-11 {
+					dmas = <&audma0 0x59>, <&audma1 0x5A>;
+					dma-names = "rx", "tx";
+				};
+				ssiu14: ssiu-12 {
+					dmas = <&audma0 0x5F>, <&audma1 0x60>;
+					dma-names = "rx", "tx";
+				};
+				ssiu15: ssiu-13 {
+					dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+					dma-names = "rx", "tx";
+				};
+				ssiu16: ssiu-14 {
+					dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+					dma-names = "rx", "tx";
+				};
+				ssiu17: ssiu-15 {
+					dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+					dma-names = "rx", "tx";
+				};
+				ssiu20: ssiu-16 {
+					dmas = <&audma0 0x63>, <&audma1 0x64>;
+					dma-names = "rx", "tx";
+				};
+				ssiu21: ssiu-17 {
+					dmas = <&audma0 0x67>, <&audma1 0x68>;
+					dma-names = "rx", "tx";
+				};
+				ssiu22: ssiu-18 {
+					dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+					dma-names = "rx", "tx";
+				};
+				ssiu23: ssiu-19 {
+					dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+					dma-names = "rx", "tx";
+				};
+				ssiu24: ssiu-20 {
+					dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+					dma-names = "rx", "tx";
+				};
+				ssiu25: ssiu-21 {
+					dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+					dma-names = "rx", "tx";
+				};
+				ssiu26: ssiu-22 {
+					dmas = <&audma0 0xED>, <&audma1 0xEE>;
+					dma-names = "rx", "tx";
+				};
+				ssiu27: ssiu-23 {
+					dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+					dma-names = "rx", "tx";
+				};
+				ssiu30: ssiu-24 {
+					dmas = <&audma0 0x6f>, <&audma1 0x70>;
+					dma-names = "rx", "tx";
+				};
+				ssiu31: ssiu-25 {
+					dmas = <&audma0 0x21>, <&audma1 0x22>;
+					dma-names = "rx", "tx";
+				};
+				ssiu32: ssiu-26 {
+					dmas = <&audma0 0x23>, <&audma1 0x24>;
+					dma-names = "rx", "tx";
+				};
+				ssiu33: ssiu-27 {
+					dmas = <&audma0 0x25>, <&audma1 0x26>;
+					dma-names = "rx", "tx";
+				};
+				ssiu34: ssiu-28 {
+					dmas = <&audma0 0x27>, <&audma1 0x28>;
+					dma-names = "rx", "tx";
+				};
+				ssiu35: ssiu-29 {
+					dmas = <&audma0 0x29>, <&audma1 0x2A>;
+					dma-names = "rx", "tx";
+				};
+				ssiu36: ssiu-30 {
+					dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+					dma-names = "rx", "tx";
+				};
+				ssiu37: ssiu-31 {
+					dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+					dma-names = "rx", "tx";
+				};
+				ssiu40: ssiu-32 {
+					dmas =	<&audma0 0x71>, <&audma1 0x72>;
+					dma-names = "rx", "tx";
+				};
+				ssiu41: ssiu-33 {
+					dmas = <&audma0 0x17>, <&audma1 0x18>;
+					dma-names = "rx", "tx";
+				};
+				ssiu42: ssiu-34 {
+					dmas = <&audma0 0x19>, <&audma1 0x1A>;
+					dma-names = "rx", "tx";
+				};
+				ssiu43: ssiu-35 {
+					dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+					dma-names = "rx", "tx";
+				};
+				ssiu44: ssiu-36 {
+					dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+					dma-names = "rx", "tx";
+				};
+				ssiu45: ssiu-37 {
+					dmas = <&audma0 0x1F>, <&audma1 0x20>;
+					dma-names = "rx", "tx";
+				};
+				ssiu46: ssiu-38 {
+					dmas = <&audma0 0x31>, <&audma1 0x32>;
+					dma-names = "rx", "tx";
+				};
+				ssiu47: ssiu-39 {
+					dmas = <&audma0 0x33>, <&audma1 0x34>;
+					dma-names = "rx", "tx";
+				};
+				ssiu50: ssiu-40 {
+					dmas = <&audma0 0x73>, <&audma1 0x74>;
+					dma-names = "rx", "tx";
+				};
+				ssiu60: ssiu-41 {
+					dmas = <&audma0 0x75>, <&audma1 0x76>;
+					dma-names = "rx", "tx";
+				};
+				ssiu70: ssiu-42 {
+					dmas = <&audma0 0x79>, <&audma1 0x7a>;
+					dma-names = "rx", "tx";
+				};
+				ssiu80: ssiu-43 {
+					dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+					dma-names = "rx", "tx";
+				};
+				ssiu90: ssiu-44 {
+					dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+					dma-names = "rx", "tx";
+				};
+				ssiu91: ssiu-45 {
+					dmas = <&audma0 0x7F>, <&audma1 0x80>;
+					dma-names = "rx", "tx";
+				};
+				ssiu92: ssiu-46 {
+					dmas = <&audma0 0x81>, <&audma1 0x82>;
+					dma-names = "rx", "tx";
+				};
+				ssiu93: ssiu-47 {
+					dmas = <&audma0 0x83>, <&audma1 0x84>;
+					dma-names = "rx", "tx";
+				};
+				ssiu94: ssiu-48 {
+					dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+					dma-names = "rx", "tx";
+				};
+				ssiu95: ssiu-49 {
+					dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+					dma-names = "rx", "tx";
+				};
+				ssiu96: ssiu-50 {
+					dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+					dma-names = "rx", "tx";
+				};
+				ssiu97: ssiu-51 {
+					dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+					dma-names = "rx", "tx";
+				};
+			};
+		};
+
+		audma0: dma-controller@ec700000 {
+			compatible = "renesas,dmac-r8a774b1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xec700000 0 0x10000>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 502>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 502>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		audma1: dma-controller@ec720000 {
+			compatible = "renesas,dmac-r8a774b1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xec720000 0 0x10000>;
+			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 501>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 501>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		xhci0: usb@ee000000 {
+			compatible = "renesas,xhci-r8a774b1",
+				     "renesas,rcar-gen3-xhci";
+			reg = <0 0xee000000 0 0xc00>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
+		usb3_peri0: usb@ee020000 {
+			compatible = "renesas,r8a774b1-usb3-peri",
+				     "renesas,rcar-gen3-usb3-peri";
+			reg = <0 0xee020000 0 0x400>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
+		ohci0: usb@ee080000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee080000 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			phys = <&usb2_phy0 1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			status = "disabled";
+		};
+
+		ohci1: usb@ee0a0000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee0a0000 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1 1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			status = "disabled";
+		};
+
+		ehci0: usb@ee080100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			phys = <&usb2_phy0 2>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			status = "disabled";
+		};
+
+		ehci1: usb@ee0a0100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee0a0100 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1 2>;
+			phy-names = "usb";
+			companion = <&ohci1>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@ee080200 {
+			compatible = "renesas,usb2-phy-r8a774b1",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy@ee0a0200 {
+			compatible = "renesas,usb2-phy-r8a774b1",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee0a0200 0 0x700>;
+			clocks = <&cpg CPG_MOD 702>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		sdhi0: mmc@ee100000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: mmc@ee120000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 313>;
+			status = "disabled";
+		};
+
+		sdhi2: mmc@ee140000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi3: mmc@ee160000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
+
+		sata: sata@ee300000 {
+			compatible = "renesas,sata-r8a774b1",
+				     "renesas,rcar-gen3-sata";
+			reg = <0 0xee300000 0 0x200000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 815>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 815>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 408>;
+		};
+
+		pciec0: pcie@fe000000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
+			reg = <0 0xfe000000 0 0x80000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 319>;
+			status = "disabled";
+		};
+
+		pciec1: pcie@ee800000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
+			reg = <0 0xee800000 0 0x80000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 318>;
+			status = "disabled";
+		};
+
+		fdp1@fe940000 {
+			compatible = "renesas,fdp1";
+			reg = <0 0xfe940000 0 0x2400>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 119>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 119>;
+			renesas,fcp = <&fcpf0>;
+		};
+
+		fcpf0: fcp@fe950000 {
+			compatible = "renesas,fcpf";
+			reg = <0 0xfe950000 0 0x200>;
+			clocks = <&cpg CPG_MOD 615>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 615>;
+		};
+
+		vspb: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 626>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 626>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		vspi0: vsp@fe9a0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9a0000 0 0x8000>;
+			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 631>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 631>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x5000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x5000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		fcpvb0: fcp@fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 607>;
+		};
+
+		fcpvd0: fcp@fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 603>;
+		};
+
+		fcpvd1: fcp@fea2f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea2f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 602>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 602>;
+		};
+
+		fcpvi0: fcp@fe9af000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe9af000 0 0x200>;
+			clocks = <&cpg CPG_MOD 611>;
+			power-domains = <&sysc R8A774B1_PD_A3VP>;
+			resets = <&cpg 611>;
+		};
+
+		csi20: csi2@fea80000 {
+			compatible = "renesas,r8a774b1-csi2";
+			reg = <0 0xfea80000 0 0x10000>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 714>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 714>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					csi20vin0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vin0csi20>;
+					};
+					csi20vin1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vin1csi20>;
+					};
+					csi20vin2: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&vin2csi20>;
+					};
+					csi20vin3: endpoint@3 {
+						reg = <3>;
+						remote-endpoint = <&vin3csi20>;
+					};
+					csi20vin4: endpoint@4 {
+						reg = <4>;
+						remote-endpoint = <&vin4csi20>;
+					};
+					csi20vin5: endpoint@5 {
+						reg = <5>;
+						remote-endpoint = <&vin5csi20>;
+					};
+					csi20vin6: endpoint@6 {
+						reg = <6>;
+						remote-endpoint = <&vin6csi20>;
+					};
+					csi20vin7: endpoint@7 {
+						reg = <7>;
+						remote-endpoint = <&vin7csi20>;
+					};
+				};
+			};
+		};
+
+		csi40: csi2@feaa0000 {
+			compatible = "renesas,r8a774b1-csi2";
+			reg = <0 0xfeaa0000 0 0x10000>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 716>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 716>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					csi40vin0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vin0csi40>;
+					};
+					csi40vin1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vin1csi40>;
+					};
+					csi40vin2: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&vin2csi40>;
+					};
+					csi40vin3: endpoint@3 {
+						reg = <3>;
+						remote-endpoint = <&vin3csi40>;
+					};
+					csi40vin4: endpoint@4 {
+						reg = <4>;
+						remote-endpoint = <&vin4csi40>;
+					};
+					csi40vin5: endpoint@5 {
+						reg = <5>;
+						remote-endpoint = <&vin5csi40>;
+					};
+					csi40vin6: endpoint@6 {
+						reg = <6>;
+						remote-endpoint = <&vin6csi40>;
+					};
+					csi40vin7: endpoint@7 {
+						reg = <7>;
+						remote-endpoint = <&vin7csi40>;
+					};
+				};
+			};
+		};
+
+		hdmi0: hdmi@fead0000 {
+			compatible = "renesas,r8a774b1-hdmi",
+				     "renesas,rcar-gen3-hdmi";
+			reg = <0 0xfead0000 0 0x10000>;
+			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 729>,
+				 <&cpg CPG_CORE R8A774B1_CLK_HDMI>;
+			clock-names = "iahb", "isfr";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 729>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dw_hdmi0_in: endpoint {
+						remote-endpoint = <&du_out_hdmi0>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+				};
+				port@2 {
+					/* HDMI sound */
+					reg = <2>;
+				};
+			};
+		};
+
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a774b1";
+			reg = <0 0xfeb00000 0 0x80000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+				 <&cpg CPG_MOD 721>;
+			clock-names = "du.0", "du.1", "du.3";
+			resets = <&cpg 724>, <&cpg 722>;
+			reset-names = "du.0", "du.3";
+			status = "disabled";
+
+			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_rgb: endpoint {
+					};
+				};
+				port@1 {
+					reg = <1>;
+					du_out_hdmi0: endpoint {
+						remote-endpoint = <&dw_hdmi0_in>;
+					};
+				};
+				port@2 {
+					reg = <2>;
+					du_out_lvds0: endpoint {
+						remote-endpoint = <&lvds0_in>;
+					};
+				};
+			};
+		};
+
+		lvds0: lvds@feb90000 {
+			compatible = "renesas,r8a774b1-lvds";
+			reg = <0 0xfeb90000 0 0x14>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 727>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds0_in: endpoint {
+						remote-endpoint = <&du_out_lvds0>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					lvds0_out: endpoint {
+					};
+				};
+			};
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	thermal-zones {
+		sensor_thermal1: sensor-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 0>;
+			sustainable-power = <2439>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal2: sensor-thermal2 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 1>;
+			sustainable-power = <2439>;
+
+			trips {
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal3: sensor-thermal3 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 2>;
+			sustainable-power = <2439>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&a57_0 0 2>;
+					contribution = <1024>;
+				};
+			};
+			trips {
+				target: trip-point1 {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor3_crit: sensor3-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* External USB clocks - can be overridden by the board */
+	usb3s0_clk: usb3s0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	usb_extal_clk: usb_extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};

diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
new file mode 100644
index 0000000..0f86cfd
--- /dev/null
+++ b/arch/arm/dts/r8a774e1.dtsi

@@ -0,0 +1,1664 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774e1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
+#include <dt-bindings/power/r8a774e1-sysc.h>
+
+#define CPG_AUDIO_CLK_I		R8A774E1_CLK_S0D4
+
+/ {
+	compatible = "renesas,r8a774e1";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/*
+	 * The external audio clocks are configured as 0 Hz fixed frequency
+	 * clocks by default.
+	 * Boards that provide audio clocks should override them.
+	 */
+	audio_clk_a: audio_clk_a {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_c: audio_clk_c {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
+	cluster1_opp: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a57_0>;
+				};
+				core1 {
+					cpu = <&a57_1>;
+				};
+				core2 {
+					cpu = <&a57_2>;
+				};
+				core3 {
+					cpu = <&a57_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a53_0>;
+				};
+				core1 {
+					cpu = <&a53_1>;
+				};
+				core2 {
+					cpu = <&a53_2>;
+				};
+				core3 {
+					cpu = <&a53_3>;
+				};
+			};
+		};
+
+		a57_0: cpu@0 {
+			compatible = "arm,cortex-a57";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			dynamic-power-coefficient = <854>;
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_1: cpu@1 {
+			compatible = "arm,cortex-a57";
+			reg = <0x1>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_2: cpu@2 {
+			compatible = "arm,cortex-a57";
+			reg = <0x2>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a57_3: cpu@3 {
+			compatible = "arm,cortex-a57";
+			reg = <0x3>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
+			#cooling-cells = <2>;
+		};
+
+		a53_0: cpu@100 {
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+			dynamic-power-coefficient = <277>;
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_1: cpu@101 {
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_2: cpu@102 {
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		a53_3: cpu@103 {
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <535>;
+		};
+
+		L2_CA57: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		L2_CA53: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* External PCIe clock - can be overridden by the board */
+	pcie_bus_clk: pcie_bus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+	};
+
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
+		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a774e1-wdt",
+				     "renesas,rcar-gen3-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
+			status = "disabled";
+		};
+
+		gpio0: gpio@e6050000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio@e6051000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 29>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio@e6052000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 15>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio@e6053000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio@e6054000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio@e6055000 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 26>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio@e6055400 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 906>;
+		};
+
+		gpio7: gpio@e6055800 {
+			compatible = "renesas,gpio-r8a774e1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055800 0 0x50>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 224 4>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 905>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 905>;
+		};
+
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,pfc-r8a774e1";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
+		cmt0: timer@e60f0000 {
+			compatible = "renesas,r8a774e1-cmt0",
+				     "renesas,rcar-gen3-cmt0";
+			reg = <0 0xe60f0000 0 0x1004>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 303>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 303>;
+			status = "disabled";
+		};
+
+		cmt1: timer@e6130000 {
+			compatible = "renesas,r8a774e1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6130000 0 0x1004>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 302>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 302>;
+			status = "disabled";
+		};
+
+		cmt2: timer@e6140000 {
+			compatible = "renesas,r8a774e1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6140000 0 0x1004>;
+			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 301>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 301>;
+			status = "disabled";
+		};
+
+		cmt3: timer@e6148000 {
+			compatible = "renesas,r8a774e1-cmt1",
+				     "renesas,rcar-gen3-cmt1";
+			reg = <0 0xe6148000 0 0x1004>;
+			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 300>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 300>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a774e1-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a774e1-rst";
+			reg = <0 0xe6160000 0 0x0200>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a774e1-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		tsc: thermal@e6198000 {
+			compatible = "renesas,r8a774e1-thermal";
+			reg = <0 0xe6198000 0 0x100>,
+			      <0 0xe61a0000 0 0x100>,
+			      <0 0xe61a8000 0 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 522>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 522>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		intc_ex: interrupt-controller@e61c0000 {
+			compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
+		tmu0: timer@e61e0000 {
+			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
+			reg = <0 0xe61e0000 0 0x30>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 125>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 125>;
+			status = "disabled";
+		};
+
+		tmu1: timer@e6fc0000 {
+			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
+			reg = <0 0xe6fc0000 0 0x30>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 124>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 124>;
+			status = "disabled";
+		};
+
+		tmu2: timer@e6fd0000 {
+			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
+			reg = <0 0xe6fd0000 0 0x30>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 123>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 123>;
+			status = "disabled";
+		};
+
+		tmu3: timer@e6fe0000 {
+			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
+			reg = <0 0xe6fe0000 0 0x30>;
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 122>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 122>;
+			status = "disabled";
+		};
+
+		tmu4: timer@ffc00000 {
+			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
+			reg = <0 0xffc00000 0 0x30>;
+			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 121>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 121>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 931>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 930>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 929>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 928>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 927>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 919>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 918>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c_dvfs: i2c@e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a774e1",
+				     "renesas,rcar-gen3-iic",
+				     "renesas,rmobile-iic";
+			reg = <0 0xe60b0000 0 0x425>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 926>;
+			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 520>;
+			status = "disabled";
+		};
+
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 0x60>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+			       <&dmac2 0x33>, <&dmac2 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 519>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 0x60>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+			       <&dmac2 0x35>, <&dmac2 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 518>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		hscif4: serial@e66b0000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66b0000 0 0x60>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 516>;
+			status = "disabled";
+		};
+
+		hsusb: usb@e6590000 {
+			reg = <0 0xe6590000 0 0x200>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb3_phy0: usb-phy@e65ee000 {
+			reg = <0 0xe65ee000 0 0x90>;
+			#phy-cells = <0>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		dmac0: dma-controller@e6700000 {
+			compatible = "renesas,dmac-r8a774e1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe6700000 0 0x10000>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 219>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 219>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+				 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+				 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+				 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+				 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+				 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+				 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+				 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+		};
+
+		dmac1: dma-controller@e7300000 {
+			compatible = "renesas,dmac-r8a774e1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7300000 0 0x10000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 218>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 218>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+				 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+				 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+				 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+				 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+				 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+				 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+				 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+		};
+
+		dmac2: dma-controller@e7310000 {
+			compatible = "renesas,dmac-r8a774e1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7310000 0 0x10000>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 217>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 217>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+				 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+				 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+				 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+				 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+				 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+				 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+				 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+		};
+
+		ipmmu_ds0: iommu@e6740000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xe6740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 0>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_ds1: iommu@e7740000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xe7740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 1>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_hc: iommu@e6570000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xe6570000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 2>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mm: iommu@e67b0000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xe67b0000 0 0x1000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mp0: iommu@ec670000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xec670000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 4>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv0: iommu@fd800000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfd800000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 6>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv1: iommu@fd950000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfd950000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 7>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv2: iommu@fd960000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfd960000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 8>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv3: iommu@fd970000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfd970000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 9>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vc0: iommu@fe6b0000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfe6b0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 12>;
+			power-domains = <&sysc R8A774E1_PD_A3VC>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vc1: iommu@fe6f0000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfe6f0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 13>;
+			power-domains = <&sysc R8A774E1_PD_A3VC>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vi0: iommu@febd0000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfebd0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 14>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vi1: iommu@febe0000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfebe0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 15>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vp0: iommu@fe990000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfe990000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 16>;
+			power-domains = <&sysc R8A774E1_PD_A3VP>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vp1: iommu@fe980000 {
+			compatible = "renesas,ipmmu-r8a774e1";
+			reg = <0 0xfe980000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 17>;
+			power-domains = <&sysc R8A774E1_PD_A3VP>;
+			#iommu-cells = <1>;
+		};
+
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a774e1",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii";
+			iommus = <&ipmmu_ds0 16>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		can0: can@e6c30000 {
+			compatible = "renesas,can-r8a774e1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c30000 0 0x1000>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>,
+				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 916>;
+			status = "disabled";
+		};
+
+		can1: can@e6c38000 {
+			compatible = "renesas,can-r8a774e1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c38000 0 0x1000>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>,
+				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 915>;
+			status = "disabled";
+		};
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a774e1-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 914>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+		pwm0: pwm@e6e30000 {
+			reg = <0 0xe6e30000 0 0x8>;
+			#pwm-cells = <2>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 0x40>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 207>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+			       <&dmac2 0x51>, <&dmac2 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 207>;
+			status = "disabled";
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 0x40>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 206>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+			       <&dmac2 0x53>, <&dmac2 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 206>;
+			status = "disabled";
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 0x40>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+			       <&dmac2 0x13>, <&dmac2 0x12>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		scif3: serial@e6c50000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c50000 0 0x40>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 204>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 204>;
+			status = "disabled";
+		};
+
+		scif4: serial@e6c40000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 0x40>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 203>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 203>;
+			status = "disabled";
+		};
+
+		scif5: serial@e6f30000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6f30000 0 0x40>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 202>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 202>;
+			status = "disabled";
+		};
+
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		rcar_sound: sound@ec500000 {
+			reg = <0 0xec500000 0 0x1000>, /* SCU */
+			      <0 0xec5a0000 0 0x100>,  /* ADG */
+			      <0 0xec540000 0 0x1000>, /* SSIU */
+			      <0 0xec541000 0 0x280>,  /* SSI */
+			      <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
+			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+			status = "disabled";
+
+			/* placeholder */
+
+			rcar_sound,ssi {
+				ssi2: ssi-2 {
+					/* placeholder */
+				};
+			};
+		};
+
+		xhci0: usb@ee000000 {
+			reg = <0 0xee000000 0 0xc00>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb3_peri0: usb@ee020000 {
+			reg = <0 0xee020000 0 0x400>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ohci0: usb@ee080000 {
+			reg = <0 0xee080000 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ohci1: usb@ee0a0000 {
+			reg = <0 0xee0a0000 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ehci0: usb@ee080100 {
+			reg = <0 0xee080100 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		ehci1: usb@ee0a0100 {
+			reg = <0 0xee0a0100 0 0x100>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb2_phy0: usb-phy@ee080200 {
+			reg = <0 0xee080200 0 0x700>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		usb2_phy1: usb-phy@ee0a0200 {
+			reg = <0 0xee0a0200 0 0x700>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		sdhi0: mmc@ee100000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
+			status = "disabled";
+		};
+
+		sdhi1: mmc@ee120000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
+			status = "disabled";
+		};
+
+		sdhi2: mmc@ee140000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
+			status = "disabled";
+		};
+
+		sdhi3: mmc@ee160000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 408>;
+		};
+
+		pciec0: pcie@fe000000 {
+			reg = <0 0xfe000000 0 0x80000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			/* placeholder */
+		};
+
+		hdmi0: hdmi@fead0000 {
+			reg = <0 0xfead0000 0 0x10000>;
+			status = "disabled";
+
+			/* placeholder */
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+				port@1 {
+					reg = <1>;
+				};
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
+		du: display@feb00000 {
+			reg = <0 0xfeb00000 0 0x80000>;
+			status = "disabled";
+
+			/* placeholder */
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+				port@1 {
+					reg = <1>;
+				};
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	thermal-zones {
+		sensor_thermal1: sensor-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 0>;
+			sustainable-power = <6313>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal2: sensor-thermal2 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 1>;
+			sustainable-power = <6313>;
+
+			trips {
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal3: sensor-thermal3 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 2>;
+			sustainable-power = <6313>;
+
+			trips {
+				target: trip-point1 {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor3_crit: sensor3-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&a57_0 0 2>;
+					contribution = <1024>;
+				};
+
+				map1 {
+					trip = <&target>;
+					cooling-device = <&a53_0 0 2>;
+					contribution = <1024>;
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* External USB clocks - can be overridden by the board */
+	usb3s0_clk: usb3s0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	usb_extal_clk: usb_extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};

diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts
index e039e33..36c8a44 100644
--- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts

@@ -8,6 +8,11 @@
 #include "r8a77950-salvator-x.dts"
 #include "r8a77950-u-boot.dtsi"
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts
index b7f26c1..d3191c5 100644
--- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts

@@ -19,6 +19,11 @@
 	};
 };
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts
index d3b0924..439fd6c 100644
--- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts

@@ -8,6 +8,11 @@
 #include "r8a77960-salvator-x.dts"
 #include "r8a77960-u-boot.dtsi"
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts
index bd1d634..aab9c95 100644
--- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts

@@ -19,6 +19,11 @@
 	};
 };
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
index d6f0708..8cbef83 100644
--- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts

@@ -8,6 +8,11 @@
 #include "r8a77965-salvator-x.dts"
 #include "r8a77965-u-boot.dtsi"
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts
index 954d8b6..38966bf 100644
--- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts

@@ -19,6 +19,11 @@
 	};
 };
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
index 0ea0cc9..6afc0be 100644
--- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts
+++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts

@@ -18,6 +18,11 @@
 	};
 };
 
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};
+
 &sdhi0 {
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;

diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts
index 2f53970..10fb9cb 100644
--- a/arch/arm/dts/r8a77995-draak-u-boot.dts
+++ b/arch/arm/dts/r8a77995-draak-u-boot.dts

@@ -7,3 +7,8 @@
 
 #include "r8a77995-draak.dts"
 #include "r8a77995-u-boot.dtsi"
+
+&rpc {
+	reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
+	status = "okay";
+};

diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index e9525b5..1548329 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi

@@ -1573,6 +1573,20 @@
 		};
 	};
 
+	spi4_pins_a: spi4-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+				 <STM32_PINMUX('E', 6, AF5)>;  /* SPI4_MOSI */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+			bias-disable;
+		};
+	};
+
 	stusb1600_pins_a: stusb1600-0 {
 			pins {
 				pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
@@ -1580,6 +1594,133 @@
 		};
 	};
 
+	uart4_pins_a: uart4-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+			bias-disable;
+		};
+	};
+
+	uart4_idle_pins_a: uart4-idle-0 {
+		   pins1 {
+			 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+		   };
+		   pins2 {
+			 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+			 bias-disable;
+		   };
+	};
+
+	uart4_sleep_pins_a: uart4-sleep-0 {
+		   pins {
+			pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
+				 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
+		    };
+	};
+
+	uart4_pins_b: uart4-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+			bias-disable;
+		};
+	};
+
+	uart4_pins_c: uart4-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+			bias-disable;
+		};
+	};
+
+	uart7_pins_a: uart7-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
+				 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
+				 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
+			bias-disable;
+		};
+	};
+
+	uart7_pins_b: uart7-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
+			bias-disable;
+		};
+	};
+
+	uart7_pins_c: uart7-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+			bias-disable;
+		};
+	};
+
+	uart7_idle_pins_c: uart7-idle-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+			bias-disable;
+		};
+	};
+
+	uart7_sleep_pins_c: uart7-sleep-2 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
+				 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
+		};
+	};
+
+	uart8_pins_a: uart8-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
+			bias-disable;
+		};
+	};
+
 	usart2_pins_a: usart2-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -1628,6 +1769,42 @@
 		};
 	};
 
+	usart2_pins_c: usart2-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
+				 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <3>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+				 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
+			bias-disable;
+		};
+	};
+
+	usart2_idle_pins_c: usart2-idle-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+				 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+				 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+			bias-disable;
+		};
+	};
+
+	usart2_sleep_pins_c: usart2-sleep-2 {
+		pins {
+			pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+				 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+				 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
+				 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+		};
+	};
+
 	usart3_pins_a: usart3-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@@ -1636,11 +1813,83 @@
 			slew-rate = <0>;
 		};
 		pins2 {
+			pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+			bias-disable;
+		};
+	};
+
+	usart3_pins_b: usart3-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+				 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
+			bias-disable;
+		};
+	};
+
+	usart3_idle_pins_b: usart3-idle-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+				 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+			bias-disable;
+		};
+	};
+
+	usart3_sleep_pins_b: usart3-sleep-1 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+				 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
+				 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+		};
+	};
+
+	usart3_pins_c: usart3-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+				 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
+			bias-disable;
+		};
+	};
+
+	usart3_idle_pins_c: usart3-idle-2 {
+		pins1 {
+			pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+				 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
+		};
+		pins2 {
 			pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
 			bias-disable;
 		};
 	};
 
+	usart3_sleep_pins_c: usart3-sleep-2 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+				 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+				 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
+				 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+		};
+	};
+
 	uart4_pins_a: uart4-0 {
 		pins1 {
 			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -1782,18 +2031,4 @@
 			bias-disable;
 		};
 	};
-
-	spi4_pins_a: spi4-0 {
-		pins {
-			pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
-				 <STM32_PINMUX('E', 6, AF5)>;  /* SPI4_MOSI */
-			bias-disable;
-			drive-push-pull;
-			slew-rate = <1>;
-		};
-		pins2 {
-			pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
-			bias-disable;
-		};
-	};
 };

diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 39d9e54..206d3d3 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi

@@ -1153,7 +1153,7 @@
 		};
 
 		pwr_mcu: pwr_mcu@50001014 {
-			compatible = "syscon";
+			compatible = "st,stm32mp151-pwr-mcu", "syscon";
 			reg = <0x50001014 0x4>;
 		};
 
@@ -1372,6 +1372,8 @@
 			dma-names = "tx", "rx";
 			clocks = <&rcc QSPI_K>;
 			resets = <&rcc QSPI_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 		};
 

diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index d03d4cd..4c8be9c 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts

@@ -18,6 +18,8 @@
 	aliases {
 		ethernet0 = &ethernet0;
 		serial0 = &uart4;
+		serial1 = &usart3;
+		serial2 = &uart7;
 	};
 
 	chosen {

diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 9a8a267..0456365 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts

@@ -19,6 +19,9 @@
 	aliases {
 		ethernet0 = &ethernet0;
 		serial0 = &uart4;
+		serial1 = &usart3;
+		serial2 = &uart7;
+		serial3 = &usart2;
 	};
 
 	chosen {
@@ -84,3 +87,11 @@
 		};
 	};
 };
+
+&usart2 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&usart2_pins_c>;
+	pinctrl-1 = <&usart2_sleep_pins_c>;
+	pinctrl-2 = <&usart2_idle_pins_c>;
+	status = "disabled";
+};

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 072d646..dd911c9 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts

@@ -361,8 +361,10 @@
 };
 
 &uart4 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep", "idle";
 	pinctrl-0 = <&uart4_pins_a>;
+	pinctrl-1 = <&uart4_sleep_pins_a>;
+	pinctrl-2 = <&uart4_idle_pins_a>;
 	status = "okay";
 };
 

diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 46f81ce..a55e80c 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts

@@ -19,6 +19,7 @@
 
 	aliases {
 		serial0 = &uart4;
+		serial1 = &usart3;
 		ethernet0 = &ethernet0;
 	};
 
@@ -343,6 +344,20 @@
 	};
 };
 
+&usart3 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&usart3_pins_b>;
+	pinctrl-1 = <&usart3_sleep_pins_b>;
+	pinctrl-2 = <&usart3_idle_pins_b>;
+	/*
+	 * HW flow control USART3_RTS is optional, and isn't default wired to
+	 * the connector. SB23 needs to be soldered in order to use it, and R77
+	 * (ETH_CLK) should be removed.
+	 */
+	uart-has-rtscts;
+	status = "disabled";
+};
+
 &usbh_ehci {
 	phys = <&usbphyc_port0>;
 	status = "okay";

diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index d660dfb..aa4aa83 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi

@@ -62,7 +62,7 @@
 
 	led {
 		compatible = "gpio-leds";
-		blue {
+		led-blue {
 			label = "heartbeat";
 			gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -391,6 +391,19 @@
 	};
 };
 
+&i2c5 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c5_pins_a>;
+	pinctrl-1 = <&i2c5_sleep_pins_a>;
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
+	clock-frequency = <400000>;
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "disabled";
+};
+
 &i2s2 {
 	clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
 	clock-names = "pclk", "i2sclk", "x8k", "x11k";
@@ -610,20 +623,39 @@
 };
 
 &uart4 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "sleep", "idle";
 	pinctrl-0 = <&uart4_pins_a>;
+	pinctrl-1 = <&uart4_sleep_pins_a>;
+	pinctrl-2 = <&uart4_idle_pins_a>;
 	status = "okay";
 };
 
+&uart7 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&uart7_pins_c>;
+	pinctrl-1 = <&uart7_sleep_pins_c>;
+	pinctrl-2 = <&uart7_idle_pins_c>;
+	status = "disabled";
+};
+
+&usart3 {
+	pinctrl-names = "default", "sleep", "idle";
+	pinctrl-0 = <&usart3_pins_c>;
+	pinctrl-1 = <&usart3_sleep_pins_c>;
+	pinctrl-2 = <&usart3_idle_pins_c>;
+	uart-has-rtscts;
+	status = "disabled";
+};
+
 &usbh_ehci {
 	phys = <&usbphyc_port0>;
 	status = "okay";
 };
 
 &usbotg_hs {
-	dr_mode = "peripheral";
 	phys = <&usbphyc_port1 0>;
 	phy-names = "usb2-phy";
+	usb-role-switch;
 	status = "okay";
 };
 

diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index fdd4c80..c97943b 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi

@@ -5,14 +5,74 @@
 		mmc1 = &mmc2;
 	};
 
-	binman {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	u-boot-sunxi-with-spl {
 		filename = "u-boot-sunxi-with-spl.bin";
 		pad-byte = <0xff>;
 		blob {
 			filename = "spl/sunxi-spl.bin";
 		};
+#ifdef CONFIG_ARM64
+		fit {
+			description = "Configuration to load ATF before U-Boot";
+			#address-cells = <1>;
+			fit,fdt-list = "of-list";
+
+			images {
+				uboot {
+					description = "U-Boot (64-bit)";
+					type = "standalone";
+					arch = "arm64";
+					compression = "none";
+					load = <0x4a000000>;
+
+					u-boot-nodtb {
+					};
+				};
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+/* TODO: Do this with an overwrite in this board's dtb? */
+#ifdef CONFIG_MACH_SUN50I_H6
+					load = <0x104000>;
+					entry = <0x104000>;
+#else
+					load = <0x44000>;
+					entry = <0x44000>;
+#endif
+					atf-bl31 {
+						missing-msg = "atf-bl31-sunxi";
+					};
+				};
+
+				@fdt-SEQ {
+					description = "NAME";
+					type = "flat_dt";
+					compression = "none";
+				};
+			};
+
+			configurations {
+				default = "config-1";
+				@config-SEQ {
+					description = "NAME";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt-SEQ";
+				};
+			};
+		};
+#else
 		u-boot-img {
 			offset = <CONFIG_SPL_PAD_TO>;
 		};
+#endif
 	};
 };

diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index a8bbb14..aae3c62 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts

@@ -230,16 +230,16 @@
 				#io-channel-cells = <1>;
 				label = "ina226-vccint";
 				reg = <0x40>;
-				shunt-resistor = <5000>; /* R440 */
-				/* 0.78V @ 32A 1 of 6 Phases*/
+				shunt-resistor = <500>; /* R440 */
+				/* 0.80V @ 32A 1 of 6 Phases*/
 			};
 			vcc_soc: ina226@41 { /* u161 */
 				compatible = "ti,ina226";
 				#io-channel-cells = <1>;
 				label = "ina226-vcc-soc";
 				reg = <0x41>;
-				shunt-resistor = <2000>; /* R1186 */
-				/* 0.78V @ 18A */
+				shunt-resistor = <500>; /* R1702 */
+				/* 0.80V @ 18A */
 			};
 			vcc_pmc: ina226@42 { /* u163 */
 				compatible = "ti,ina226";
@@ -554,6 +554,31 @@
 			reg = <7>;
 		};
 	};
+	i2c-mux@75 { /* u214 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		i2c@0 { /* SFP0_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* SFP0 */
+		};
+		i2c@1 { /* SFP1_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* SFP1 */
+		};
+		i2c@2 { /* QSFP1_I2C */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* QSFP1 */
+		};
+		/* 3 - 7 unused */
+	};
 };
 
 &xilinx_ams {

diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 04afa51..9d2319c 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S

@@ -73,7 +73,12 @@
 #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	x0, =(CONFIG_SPL_STACK)
 #elif defined(CONFIG_INIT_SP_RELATIVE)
+#if CONFIG_POSITION_INDEPENDENT
+	adrp	x0, __bss_start     /* x0 <- Runtime &__bss_start */
+	add	x0, x0, #:lo12:__bss_start
+#else
 	adr	x0, __bss_start
+#endif
 	add	x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
 #else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -102,7 +107,8 @@
 	adr	lr, relocation_return
 #if CONFIG_POSITION_INDEPENDENT
 	/* Add in link-vs-runtime offset */
-	adr	x0, _start		/* x0 <- Runtime value of _start */
+	adrp	x0, _start		/* x0 <- Runtime value of _start */
+	add	x0, x0, #:lo12:_start
 	ldr	x9, _TEXT_BASE		/* x9 <- Linked value of _start */
 	sub	x9, x9, x0		/* x9 <- Run-vs-link offset */
 	add	lr, lr, x9

diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index a3adaa8..8536a70 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c

@@ -19,7 +19,7 @@
 #include <asm/arch/wdt.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 
 /* These configuration parameters are taken from Aspeed SDK */
 #define DDR4_MR46_MODE		0x08000000

diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c
index 7cf98a2..83a688e 100644
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c

@@ -13,6 +13,8 @@
 #include <dm.h>
 #include <errno.h>
 
+#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+
 struct msm_clk_priv {
 	phys_addr_t base;
 };
@@ -20,7 +22,7 @@
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
 	switch (clk->id) {
-	case 26: /*UART1*/
+	case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
 		/* This clock is already initialized by SBL1 */
 		return 0; 
 		break;

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 95f830b..a0da3df 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c

@@ -2,8 +2,9 @@
 /*
  * K3: ARM64 MMU setup
  *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
  *
  */
@@ -66,6 +67,8 @@
 #endif /* CONFIG_SOC_K3_AM6 */
 
 #ifdef CONFIG_SOC_K3_J721E
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
 
@@ -122,4 +125,58 @@
 };
 
 struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x04800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_NON_SHARE
+	}, {
+		.virt = 0xa4800000UL,
+		.phys = 0xa4800000UL,
+		.size = 0x5b800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = j7200_mem_map;
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
 #endif /* CONFIG_SOC_K3_J721E */

diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index 3fa85ca..e894791 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h

@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_ETHERNET		0x04
 #define BOOT_DEVICE_I2C			0x06
 #define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
 
 /* With BootMode B = 1 */
 #define BOOT_DEVICE_MMC2		0x10

diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c
index c4cc11f..b4fde46 100644
--- a/arch/arm/mach-meson/board-gx.c
+++ b/arch/arm/mach-meson/board-gx.c

@@ -196,8 +196,8 @@
 	for (i = 0; i < 2; i++) {
 		ret = generic_phy_init(&usb_phys[i]);
 		if (ret) {
-			pr_err("Can't init USB PHY%d for %s\n",
-			       i, ofnode_get_name(dwc2_node));
+			pr_debug("Can't init USB PHY%d for %s\n",
+				 i, ofnode_get_name(dwc2_node));
 			return ret;
 		}
 	}
@@ -205,8 +205,8 @@
 	for (i = 0; i < 2; i++) {
 		ret = generic_phy_power_on(&usb_phys[i]);
 		if (ret) {
-			pr_err("Can't power USB PHY%d for %s\n",
-			       i, ofnode_get_name(dwc2_node));
+			pr_debug("Can't power USB PHY%d for %s\n",
+				 i, ofnode_get_name(dwc2_node));
 			return ret;
 		}
 	}

diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6..2888390 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c

@@ -14,6 +14,7 @@
 #include <init.h>
 #include <net.h>
 #include <ns16550.h>
+#include <omap3_spi.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
@@ -49,6 +50,12 @@
 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET		0xDC
 #define AM43XX_RDWRLVLFULL_START			0x80000000
 
+/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#define AM33XX_SPI0_BASE	0x48030000
+#define AM33XX_SPI0_OFFSET	(AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
@@ -140,6 +147,17 @@
 	{ "gpio_omap", &am33xx_gpio[4] },
 	{ "gpio_omap", &am33xx_gpio[5] },
 #endif
+};
+#endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+	.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
+	.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+	.name = "omap3_spi",
+	.platdata = &omap3_spi_pdata,
 };
 #endif
 #endif

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index ce9312f..5bde24a 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c

@@ -10,6 +10,7 @@
 #define PRR_MASK		0x7fff
 #define R8A7796_REV_1_0		0x5200
 #define R8A7796_REV_1_1		0x5210
+#define R8A7796_REV_1_3		0x5211
 
 static u32 rmobile_get_prr(void)
 {
@@ -28,8 +29,9 @@
 u32 rmobile_get_cpu_rev_integer(void)
 {
 	const u32 prr = rmobile_get_prr();
+	const u32 rev = prr & PRR_MASK;
 
-	if ((prr & PRR_MASK) == R8A7796_REV_1_1)
+	if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3)
 		return 1;
 	else
 		return ((prr & 0x000000F0) >> 4) + 1;
@@ -38,9 +40,12 @@
 u32 rmobile_get_cpu_rev_fraction(void)
 {
 	const u32 prr = rmobile_get_prr();
+	const u32 rev = prr & PRR_MASK;
 
-	if ((prr & PRR_MASK) == R8A7796_REV_1_1)
+	if (rev == R8A7796_REV_1_1)
 		return 1;
+	else if (rev == R8A7796_REV_1_3)
+		return 3;
 	else
 		return prr & 0x0000000F;
 }

diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S
index 213ec14..1df2c40 100644
--- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S

@@ -31,6 +31,12 @@
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
+.pushsection .text.s_init, "ax"
+WEAK(s_init)
+	ret
+ENDPROC(s_init)
+.popsection
+
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 

diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index e1d66e8..ebd2da3 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig

@@ -62,4 +62,7 @@
 	  This option configures MMU with no DDR to avoid speculative
 	  access to DDR memory where DDR is not present.
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/versal/Kconfig"
+
 endif

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 79f831e..e543103 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig

@@ -70,4 +70,7 @@
 config ZYNQ_SDHCI_MAX_FREQ
 	default 52000000
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
+
 endif

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 77b7cb1..3befc12 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c

@@ -17,8 +17,7 @@
 #define ZYNQ_SILICON_VER_MASK	0xF0000000
 #define ZYNQ_SILICON_VER_SHIFT	28
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
 xilinx_desc fpga = {
 	.family = xilinx_zynq,
 	.iface = devcfg,
@@ -111,8 +110,7 @@
 #if defined(CONFIG_ARCH_EARLY_INIT_R)
 int arch_early_init_r(void)
 {
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
 	int cpu_id = cpu_desc_id();
 
 	if (cpu_id < 0)

diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 239ce34..cb8cfd2 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c

@@ -34,7 +34,7 @@
 void spl_board_init(void)
 {
 	preloader_console_init();
-#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
+#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
 	arch_early_init_r();
 #endif
 	board_init();

diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c
index b3402d7..87c1d75 100644
--- a/arch/arm/mach-zynqmp-r5/cpu.c
+++ b/arch/arm/mach-zynqmp-r5/cpu.c

@@ -11,11 +11,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct mpu_region_config region_config[] = {
-	{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
-	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
-	{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
-	  O_I_WB_RD_WR_ALLOC, REGION_512MB },
-	{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
+	{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
+	  SHARED_WRITE_BUFFERED, REGION_4GB },
+	{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
 	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
 };
 
@@ -23,8 +21,7 @@
 {
 	gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
 
-	setup_mpu_regions(region_config, sizeof(region_config) /
-			  sizeof(struct mpu_region_config));
+	setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
 
 	return 0;
 }

diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index d82a737..f1301f6 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig

@@ -171,4 +171,7 @@
 
 endchoice
 
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
+
 endif

diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index 64e5320..7d7ab9d 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c

@@ -65,7 +65,7 @@
 	struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
 };
 
-#ifdef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_ATF
 struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
 					     uintptr_t bl33_entry,
 					     uintptr_t fdt_addr)

diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8e6be0a..632bb23 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h

@@ -50,14 +50,24 @@
 #define outw(x, addr)	((void)writew(x, addr))
 #define outl(x, addr)	((void)writel(x, addr))
 
-/* Some #definitions to keep strange Xilinx code happy */
-#define in_8(addr)	readb(addr)
-#define in_be16(addr)	readw(addr)
-#define in_be32(addr)	readl(addr)
+#define out_arch(type, endian, addr, x)	\
+		 __raw_write##type(cpu_to_##endian(x), addr)
+#define in_arch(type, endian, addr)	\
+		endian##_to_cpu(__raw_read##type(addr))
+
+#define out_le16(addr, x)	out_arch(w, le16, addr, x)
+#define out_le32(addr, x)	out_arch(l, le32, addr, x)
+
+#define in_le16(addr)		in_arch(w, le16, addr)
+#define in_le32(addr)		in_arch(l, le32, addr)
+
+#define in_8(addr)		readb(addr)
+#define in_be16(addr)		in_arch(w, be16, addr)
+#define in_be32(addr)		in_arch(l, be32, addr)
 
 #define out_8(addr, x)		outb(x, addr)
-#define out_be16(addr, x)	outw(x, addr)
-#define out_be32(addr, x)	outl(x, addr)
+#define out_be16(addr, x)	out_arch(w, be16, addr, x)
+#define out_be32(addr, x)	out_arch(l, be32, addr, x)
 
 #define inb_p(port)		inb((port))
 #define outb_p(val, port)	outb((val), (port))

diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6..6ef9109 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c

@@ -17,7 +17,7 @@
 	 * whole SDRAM area, since we don't know the size of the image
 	 * that was loaded.
 	 */
-	flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
+	flush_cache(gd->ram_base, gd->ram_top - gd->ram_base);
 
 	return entry(argc, argv);
 }

diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 0a13f6e..d5c99d8 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c

@@ -242,7 +242,7 @@
 #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
 int arch_fixup_fdt(void *blob)
 {
-	u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
+	u64 mem_start = virt_to_phys((void *)gd->ram_base);
 	u64 mem_size = gd->ram_size;
 
 	return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 18808da..2bae08e 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig

@@ -101,34 +101,42 @@
 config TARGET_KMETER1
 	bool "Support kmeter1"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_KMCOGE5NE
 	bool "Support kmcoge5ne"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_KMTEGR1
 	bool "Support kmtegr1"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_TUXX1
 	bool "Support tuxx1"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_KMSUPX5
 	bool "Support kmsupx5"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_TUGE1
 	bool "Support tuge1"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_KMOPTI2
 	bool "Support kmopti2"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_KMTEPR2
 	bool "Support kmtepr2"
 	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
 
 config TARGET_TQM834X
 	bool "Support TQM834x"

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 3040299..aeb42b1 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile

@@ -27,7 +27,9 @@
 obj-y += speed.o
 obj-y += interrupts.o
 obj-y += ecc.o
+ifndef CONFIG_PINCTRL
 obj-$(CONFIG_QE) += qe_io.o
+endif
 obj-$(CONFIG_FSL_SERDES) += serdes.o
 ifndef CONFIG_ARCH_MPC8308
 obj-$(CONFIG_PCI) += pci.o

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 438b14b..840f907 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -9,10 +9,14 @@
 #include <ioports.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <fsl_qe.h>
 #ifdef CONFIG_USB_EHCI_FSL
 #include <usb/ehci-ci.h>
 #endif
 #include <linux/delay.h>
+#ifdef CONFIG_QE
+#include <fsl_qe.h>
+#endif
 
 #include "lblaw/lblaw.h"
 #include "elbc/elbc.h"
@@ -26,9 +30,8 @@
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 			 int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
 
+#if !defined(CONFIG_PINCTRL)
 static void config_qe_ioports(void)
 {
 	u8	port, pin;
@@ -45,6 +48,7 @@
 	}
 }
 #endif
+#endif
 
 /*
  * Breathe some life into the CPU...
@@ -191,10 +195,13 @@
 	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 #endif
 
+#if !defined(CONFIG_PINCTRL)
 #ifdef CONFIG_QE
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
+#endif
+
 	/* Set up preliminary BR/OR regs */
 	init_early_memctl_regs();
 

diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index ebdedb2..4ea7b27 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c

@@ -121,7 +121,7 @@
                 "clock-frequency", get_serial_clock(), 1);
 #endif
 
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+	fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
 	(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))

diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 88aa689..5236070 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c

@@ -12,57 +12,93 @@
 #include <asm/immap_83xx.h>
 
 #define	NUM_OF_PINS	32
-void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io:	pointer to parallel I/O base
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+			 int open_drain, int assign)
 {
-	u32			pin_2bit_mask;
-	u32			pin_2bit_dir;
-	u32			pin_2bit_assign;
-	u32			pin_1bit_mask;
-	u32			tmp_val;
-	volatile immap_t	*im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
+	u32	dbit_mask;
+	u32	dbit_dir;
+	u32	dbit_asgn;
+	u32	bit_mask;
+	u32	tmp_val;
+	int	offset;
+
+	offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
 
 	/* Calculate pin location and 2bit mask and dir */
-	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
-	pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+	dbit_mask = (u32)(0x3 << offset);
+	dbit_dir = (u32)(dir << offset);
 
 	/* Setup the direction */
-	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
 		in_be32(&par_io->ioport[port].dir2) :
 		in_be32(&par_io->ioport[port].dir1);
 
-	if (pin > (NUM_OF_PINS/2) -1) {
-		out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
 	} else {
-		out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
+		out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
 	}
 
 	/* Calculate pin location for 1bit mask */
-	pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+	bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
 
 	/* Setup the open drain */
 	tmp_val = in_be32(&par_io->ioport[port].podr);
-	if (open_drain) {
-		out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
-	} else {
-		out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
-	}
+	if (open_drain)
+		out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+	else
+		out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
 
 	/* Setup the assignment */
-	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
-		in_be32(&par_io->ioport[port].ppar2):
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].ppar2) :
 		in_be32(&par_io->ioport[port].ppar1);
-	pin_2bit_assign = (u32)(assign
-				<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+	dbit_asgn = (u32)(assign << offset);
 
 	/* Clear and set 2 bits mask */
-	if (pin > (NUM_OF_PINS/2) - 1) {
-		out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
 	} else {
-		out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
 	}
 }
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
+	qepio83xx_t    *par_io = (qepio83xx_t *)&im->qepio;
+
+	qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#endif

diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index c3cc119..ea8bc6c 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c

@@ -23,7 +23,7 @@
 /* Returns 0 if exception not found and fixup otherwise.  */
 extern unsigned long search_exception_table(unsigned long);
 
-#define END_OF_MEM	(gd->bd->bi_memstart + gd->bd->bi_memsize)
+#define END_OF_MEM	(gd->ram_base + gd->ram_size)
 
 /*
  * Trap & Exception support

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 753d075..54c7fd9 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig

@@ -40,14 +40,6 @@
 	imply CMD_SATA
 	imply PANIC_HANG
 
-config TARGET_P5020DS
-	bool "Support P5020DS"
-	select PHYS_64BIT
-	select ARCH_P5020
-	select BOARD_LATE_INIT if CHAIN_OF_TRUST
-	imply CMD_SATA
-	imply PANIC_HANG
-
 config TARGET_P5040DS
 	bool "Support P5040DS"
 	select PHYS_64BIT
@@ -109,22 +101,6 @@
 	imply CMD_SATA
 	imply PANIC_HANG
 
-config TARGET_P1023RDB
-	bool "Support P1023RDB"
-	select ARCH_P1023
-	select FSL_DDR_INTERACTIVE
-	imply CMD_EEPROM
-	imply PANIC_HANG
-
-config TARGET_P1020MBG
-	bool "Support P1020MBG-PC"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-	select ARCH_P1020
-	imply CMD_EEPROM
-	imply CMD_SATA
-	imply PANIC_HANG
-
 config TARGET_P1020RDB_PC
 	bool "Support P1020RDB-PC"
 	select SUPPORT_SPL
@@ -143,42 +119,6 @@
 	imply CMD_SATA
 	imply PANIC_HANG
 
-config TARGET_P1020UTM
-	bool "Support P1020UTM"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-	select ARCH_P1020
-	imply CMD_EEPROM
-	imply CMD_SATA
-	imply PANIC_HANG
-
-config TARGET_P1021RDB
-	bool "Support P1021RDB"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-	select ARCH_P1021
-	imply CMD_EEPROM
-	imply CMD_SATA
-	imply PANIC_HANG
-
-config TARGET_P1024RDB
-	bool "Support P1024RDB"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-	select ARCH_P1024
-	imply CMD_EEPROM
-	imply CMD_SATA
-	imply PANIC_HANG
-
-config TARGET_P1025RDB
-	bool "Support P1025RDB"
-	select SUPPORT_SPL
-	select SUPPORT_TPL
-	select ARCH_P1025
-	imply CMD_EEPROM
-	imply CMD_SATA
-	imply SATA_SIL
-
 config TARGET_P2020RDB
 	bool "Support P2020RDB-PC"
 	select SUPPORT_SPL
@@ -1506,7 +1446,6 @@
 source "board/freescale/mpc8569mds/Kconfig"
 source "board/freescale/mpc8572ds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
-source "board/freescale/p1023rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9569c1a..0d8353c 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c

@@ -672,10 +672,10 @@
 		"clock-frequency", get_bus_freq(0), 1);
 #endif
 
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+	fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
 
 #ifdef CONFIG_MP
-	ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
+	ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
 	ft_fixup_num_cores(blob);
 #endif
 

diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index f37a45e..db6ed1f 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c

@@ -37,7 +37,7 @@
  * amount of memory on the system if we're unable to keep all
  * the memory mapped in.
  */
-#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
+#define END_OF_MEM	(gd->ram_base + get_effective_memsize())
 
 static __inline__ void set_tsr(unsigned long val)
 {

diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 24e5311..010b6d4 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c

@@ -8,6 +8,8 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void ft_fixup_num_cores(void *blob);
 extern void ft_srio_setup(void *blob);
 
@@ -27,7 +29,7 @@
 	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 			     "bus-frequency", bd->bi_busfreq, 1);
 
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+	fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",

diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
index c0161e3..3ee0ec8 100644
--- a/arch/powerpc/cpu/mpc86xx/traps.c
+++ b/arch/powerpc/cpu/mpc86xx/traps.c

@@ -30,7 +30,7 @@
  * amount of memory on the system if we're unable to keep all
  * the memory mapped in.
  */
-#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
+#define END_OF_MEM	(gd->ram_base + get_effective_memsize())
 
 /*
  * Trap & Exception support

diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index 4d952a3..226e258 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c

@@ -25,5 +25,5 @@
 	do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
 			       gd->arch.brg_clk, 1);
 
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+	fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
 }

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2b24e75..b2d1dc5 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c

@@ -343,6 +343,7 @@
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
@@ -370,3 +371,4 @@
 #endif
 	return 0;
 }
+#endif

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 7eb005f..266d345 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile

@@ -1,5 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
+dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
+dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
+dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
+dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
+dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
 dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
 dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
 dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
@@ -16,6 +22,8 @@
 dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
 dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
 dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
+dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
+dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
 

diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi
new file mode 100644
index 0000000..c44ce7d
--- /dev/null
+++ b/arch/powerpc/dts/km8309-uboot.dtsi

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA 8309 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8309@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+	clock-frequency = <132000000>;
+	u-boot,dm-pre-reloc;
+};

diff --git a/arch/powerpc/dts/km8321-uboot.dtsi b/arch/powerpc/dts/km8321-uboot.dtsi
new file mode 100644
index 0000000..3488260
--- /dev/null
+++ b/arch/powerpc/dts/km8321-uboot.dtsi

@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA 8321 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8321@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&enet_piggy2 {
+	status = "okay";
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&serial0 {
+	clock-frequency = <132000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+
+	par_io@1400 {
+		compatible = "fsl,mpc8360-par_io";
+		u-boot,dm-pre-reloc;
+
+		serial_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@1 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@3 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@4 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@5 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@6 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@7 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/km8321.dtsi b/arch/powerpc/dts/km8321.dtsi
new file mode 100644
index 0000000..e493613
--- /dev/null
+++ b/arch/powerpc/dts/km8321.dtsi

@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA km8321 common ports Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8321@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <16384>;		// L1, 16K
+			i-cache-size = <16384>;		// L1, 16K
+			timebase-frequency = <66000000>;
+			bus-frequency = <264000000>;
+			clock-frequency = <528000000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc: soc8321@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <264000000>;
+
+		i2c0: i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <100000>;
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		dma@82a8 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
+			reg = <0x82a8 4>;
+			ranges = <0 0x8100 0x1a8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <71 8>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x80 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x100 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x180 0x28>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+		par_io: par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			device_type = "par_io";
+			num-ports = <7>;
+
+			qe_pio_d: gpio-controller@48 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360-qe-pario-bank",
+					     "fsl,mpc8323-qe-pario-bank";
+				reg = <0x1448 0x18>;
+				gpio-controller;
+			};
+		};
+	};
+
+	qe: qe@e0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe";
+		ranges = <0x0 0xe0100000 0x00100000>;
+		reg = <0xe0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <396000000>;
+
+		muram@10000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe-muram", "fsl,cpm-muram";
+			ranges = <0x0 0x00010000 0x00004000>;
+
+			data-only@0 {
+				compatible = "fsl,qe-muram-data",
+					     "fsl,cpm-muram-data";
+				reg = <0x0 0x4000>;
+			};
+		};
+
+		/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+		enet_piggy2: ucc@3200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <4>;
+			reg = <0x3200 0x200>;
+			interrupts = <35>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			rx-clock-name = "none";
+			tx-clock-name = "clk17";
+			phy-handle = <&phy_piggy2>;
+			phy-connection-type = "rmii";
+			pio-handle = <&pio_ucc4>;
+		};
+
+		mdio: mdio@3320 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3320 0x18>;
+			compatible = "fsl,ucc-mdio";
+
+			/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+			phy_piggy2: ethernet-phy@00 {
+				reg = <0x0>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		qeic: interrupt-controller@80 {
+			interrupt-controller;
+			compatible = "fsl,qe-ic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x80 0x80>;
+			big-endian;
+			interrupts = <32 8 33 8>;
+			interrupt-parent = <&ipic>;
+		};
+		bootcount@0x13ff8 {
+			device_type = "bootcount";
+			compatible = "u-boot,bootcount";
+			reg = <0x13ff8 0x08>;
+		};
+
+		spi0: spi@4c0 {
+			cell-index = <0>;
+			compatible = "fsl,spi";
+			reg = <0x4c0 0x40>;
+			interrupts = <2>;
+			interrupt-parent = <&qeic>;
+			mode = "qe";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pio-handle = <&pio_spi>;
+		};
+	};
+
+	localbus: localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+	};
+};
+
+#include "km8321-uboot.dtsi"

diff --git a/arch/powerpc/dts/km836x-uboot.dtsi b/arch/powerpc/dts/km836x-uboot.dtsi
new file mode 100644
index 0000000..ac5339e
--- /dev/null
+++ b/arch/powerpc/dts/km836x-uboot.dtsi

@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA km836x U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8360@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+
+	par_io@1400 {
+		u-boot,dm-pre-reloc;
+
+		serial_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@1 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@3 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@4 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@5 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@6 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@7 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+};

diff --git a/arch/powerpc/dts/km836x.dtsi b/arch/powerpc/dts/km836x.dtsi
new file mode 100644
index 0000000..a8c83fc
--- /dev/null
+++ b/arch/powerpc/dts/km836x.dtsi

@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA km836x common ports Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8360@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	/* 32 bytes */
+			i-cache-line-size = <32>;	/* 32 bytes */
+			d-cache-size = <32768>;	/* L1, 32K */
+			i-cache-size = <32768>;	/* L1, 32K */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			bus-frequency = <0>; /* Filled in by U-Boot */
+			clock-frequency = <0>; /* Filled in by U-Boot */
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0>;		/* Filled in by U-Boot */
+	};
+
+	soc: soc8360@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "fsl,mpc8360-immr", "simple-bus";
+		ranges = <0x0 0xe0000000 0x00200000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <0>;/* Filled in by U-Boot */
+
+		/* power management control module*/
+		pmc: power@b00 {
+			compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+			reg = <0xb00 0x100 0xa00 0x100>;
+			interrupts = <80 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		i2c0: i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <100000>;
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <133333333>;
+			interrupts = <10 0x8>;
+			interrupt-parent = <&ipic>;
+			status = "disabled";
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+		};
+
+		par_io: par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			compatible = "fsl,mpc8360-par_io";
+			device_type = "par_io";
+			num-ports = <7>;
+
+			qe_pio_c: gpio-controller@30 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360-qe-pario-bank",
+					     "fsl,mpc8323-qe-pario-bank";
+				reg = <0x1430 0x18>;
+				gpio-controller;
+			};
+		};
+
+		qe: qe@100000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe";
+			ranges = <0x0 0x100000 0x100000>;
+			reg = <0x100000 0x480>;
+			clock-frequency = <0>;	/* Filled in by U-Boot */
+			brg-frequency = <0>;	/* Filled in by U-Boot */
+			bus-frequency = <0>;	/* Filled in by U-Boot */
+
+			muram@10000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "fsl,qe-muram", "fsl,cpm-muram";
+				ranges = <0x0 0x00010000 0x0000c000>;
+
+				data-only@0 {
+					compatible = "fsl,qe-muram-data",
+						     "fsl,cpm-muram-data";
+					reg = <0x0 0xc000>;
+				};
+			};
+
+			qeic: interrupt-controller@80 {
+				interrupt-controller;
+				compatible = "fsl,qe-ic";
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				reg = <0x80 0x80>;
+				big-endian;
+				interrupts = <
+					32 0x8 /* ucc1 */
+					33 0x8 /* ucc2 */
+					34 0x8 /* ucc3 */
+					35 0x8 /* ucc4 */
+					40 0x8 /* ucc1 */
+				>;
+				interrupt-parent = <&ipic>;
+			};
+
+			spi0: spi@4c0 {
+				cell-index = <0>;
+				compatible = "fsl,spi";
+				reg = <0x4c0 0x40>;
+				interrupts = <2>;
+				interrupt-parent = <&qeic>;
+				mode = "qe";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				pio-handle = <&pio_spi>;
+			};
+
+			bootcount@0x1bff8 {
+				device_type = "bootcount";
+				compatible = "u-boot,bootcount";
+				reg = <0x1bff8 0x08>;
+			};
+		};
+	};
+
+	localbus: localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+	};
+};
+
+#include "km836x-uboot.dtsi"

diff --git a/arch/powerpc/dts/kmcoge5ne-uboot.dtsi b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi
new file mode 100644
index 0000000..6a5e74f
--- /dev/null
+++ b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	aliases {
+		/delete-property/ ethernet1;
+		/delete-property/ ethernet2;
+	};
+};
+
+&enet_switch {
+	status = "disabled";
+};
+
+&enet_mate {
+	status = "disabled";
+};

diff --git a/arch/powerpc/dts/kmcoge5ne.dts b/arch/powerpc/dts/kmcoge5ne.dts
new file mode 100644
index 0000000..467e5bd
--- /dev/null
+++ b/arch/powerpc/dts/kmcoge5ne.dts

@@ -0,0 +1,320 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA KMCOGE5ne Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km836x.dtsi"
+
+/ {
+	model = "kmcoge5ne";
+	compatible = "ABB,kmcoge5ne";
+
+	aliases {
+		ethernet0 = &enet_admin;
+		ethernet1 = &enet_mate;
+		ethernet2 = &enet_switch;
+		serial0 = &serial0;
+	};
+};
+
+&soc {
+	/* brg for hdlc clk */
+	brg@0 {
+		compatible = "fsl,mpc-brg";
+		brg-name = "brg16";
+		brg-frequency = <20000000>; /* 20 MHz */
+		pio-handle =  <&pio_brg>;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the fan unit */
+			fanu-ivm@50 {
+				label = "FANUV";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+
+			/* fan unit (GPIOs and so on) */
+			fanu@20 {
+				label = "FANUV_CTRL";
+				compatible = "dummy";
+				reg = <0x20>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			backplane@50 {
+				label = "BP_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&par_io {
+	pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC    (PA2,   in, f1) */
+
+			0   3  1  0  1  0	/* TxD0   (PA3,   in, f1) */
+			0   4  1  0  1  0	/* TxD1   (PA4,   in, f1) */
+			0   5  1  0  1  0	/* TxD2   (PA5,   in, f1) */
+			0   6  1  0  1  0	/* TxD3   (PA6,   in, f1) */
+			0   9  2  0  1  0	/* RxD0   (PA9,  out, f1) */
+			0  10  2  0  1  0	/* RxD1   (PA10, out, f1) */
+			0  11  2  0  1  0	/* RxD2   (PA11, out, f1) */
+			0  12  2  0  1  0	/* RxD3   (PA12, out, f1) */
+			0   7  1  0  1  0	/* TX_EN  (PA7,   in, f1) */
+			0  15  2  0  1  0	/* RX_DV  (PA15, out, f1) */
+			0   0  2  0  1  0	/* RX_CLK (PA0,  out, f1) */
+			2   9  1  0  3  0	/* GTX_CLK        (CLK10) */
+			2   8  2  0  1  0	/* GTX125          (CLK9) */
+		>;
+	};
+
+	pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC    (PA2,   in, f1) */
+
+			1  14  1  0  1  0	/* TxD0   (PB14, out, f1) */
+			1  15  1  0  1  0	/* TxD1   (PB15, out, f1) */
+			1  20  2  0  1  0	/* RxD0   (PB20, in,  f1) */
+			1  21  2  0  1  0	/* RxD1   (PB21, in,  f1) */
+			1  18  1  0  1  0	/* TX_EN  (PB18, out, f1) */
+			1  26  2  0  1  0	/* RX_DV  (PB26, in,  f1) */
+			1  27  2  0  1  0	/* RX_ER  (PB27, in,  f1) */
+
+			2  16  2  0  1  0	/* UCC4_RMII_CLK  (CLK17) */
+		>;
+	};
+
+	pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO  (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC   (PA2,   in, f1) */
+
+			3   0  1  0  1  0	/* TxD0  (PD0,  out, f1) */
+			3   1  1  0  1  0	/* TxD1  (PD1,  out, f1) */
+			3   6  2  0  1  0	/* RxD0  (PD6,   in, f1) */
+			3   7  2  0  1  0	/* RxD1  (PD7,   in, f1) */
+			3   4  1  0  1  0	/* TX_EN (PD4,  out, f1) */
+			3  12  2  0  1  0	/* RX_DV (PD12,  in, f1) */
+			3  13  2  0  1  0	/* RX_ER (PD13,  in, f1) */
+
+			2  15  2  0  1  0	/* UCCx_RMII_CLK  (CLK16) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			4  28  3  0  3  0	/* SPI_MOSI (PE28, out, f3) */
+			4  29  3  0  3  0	/* SPI_MISO (PE29, out, f3) */
+			4  30  3  0  3  0	/* SPI_CLK  (PE30, out, f3) */
+		>;
+	};
+
+	pio_brg: brg_pin@0 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			2  25  1  0  1  0	/* BRG	   (PC25, out, f1) */
+		>;
+	};
+
+	pio_tdm: tdm_pin@00 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			/* TDMa */
+			0  8  3  0  2  0	/* RxD0    (PA8,  bi, f2) */
+			0  13 3  0  2  0	/* TxD0    (PA13, bi, f2) */
+			0  14 2  0  2  0	/* RSync0  (PA14, in, f2) */
+			2  7  2  0  1  0	/* RxClk8  (PC7,  in, f1) */
+			/* TDMb */
+			0  27 3  0  2  0	/* RxD1    (PA27, bi, f2) */
+			0  22 3  0  2  0	/* TxD1    (PA22, bi, f2) */
+			0  28 2  0  2  0	/* RSync1  (PA28, in, f2) */
+			2  1  2  0  1  0	/* RxClk2  (PC1,  in, f1) */
+			/* TDMc */
+			1  5  3  0  2  0	/* RxD2    (PB5,  bi, f2) */
+			1  8  3  0  2  0	/* TxD2    (PB8,  bi, f2) */
+			1  2  2  0  3  0	/* RSync2  (PB2,  in, f3) */
+			2  6  2  0  1  0	/* RxClk7  (PC6,  in, f1) */
+			/* TDMd */
+			1  22 3  0  2  0	/* RxD3    (PB22, bi, f2) */
+			1  19 3  0  1  0	/* TxD3    (PB19, bi, f1) */
+			1  16 2  0  2  0	/* RSync3  (PB16, in, f2) */
+			2  13 2  0  1  0	/* RxClk14 (PC13, in, f1) */
+			/* TDMe */
+			3  8  3  0  2  0	/* RxD4    (PD8,  bi, f2) */
+			3  5  3  0  2  0	/* TxD4    (PD5,  bi, f2) */
+			3  2  2  0  2  0	/* RSync4  (PD2 , in, f2) */
+			2  22 2  0  1  0	/* RxClk23 (PC22, in, f1) */
+			/* TDMf */
+			3  19 3  0  2  0	/* RxD5    (PD19, bi, f2) */
+			3  22 3  0  2  0	/* TxD5    (PD22, bi, f2) */
+			3  16 2  0  1  0	/* RSync5  (PD16, in, f1) */
+			2  17 2  0  1  0	/* RxClk18 (PC17, in, f1) */
+			/* TDMg */
+			4  8  3  0  2  0	/* RxD6    (PE8,  bi, f2) */
+			4  5  3  0  2  0	/* TxD6    (PE5,  bi, f2) */
+			4  2  2  0  1  0	/* RSync6  (PE2,  in, f1) */
+			2  19 2  0  1  0	/* RxClk20 (PC19, in, f1) */
+			/* TDMh */
+			4  19 3  0  2  0	/* RxD7    (PE19, bi, f2) */
+			4  22 3  0  3  0	/* TxD7    (PE22, bi, f3) */
+			4  16 2  0  2  0	/* RSync7  (PE16, in, f2) */
+			2  21 2  0  1  0	/* RxClk22 (PC21, in, f1) */
+			/* RxTxClk0/1 */
+			2  0  2  0  1  0	/* Clk1    (PC0,  in, f1) */
+			2  23 2  0  1  0	/* Clk24   (PC23, in, f1) */
+			/* RxTxSync0/1 */
+			2  10 2  0  1  0	/* Clk11   (PC10, in, f1) */
+			2  20 2  0  1  0>;	/* Clk21   (PC20, in, f1) */
+	};
+};
+
+&qe {
+	/* mng-switch port (UCC1, MDIO 0x10, RGMII) */
+	enet_switch: ethernet@2000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <1>;
+		reg = <0x2000 0x200>;
+		interrupts = <32>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk9";
+		/*id=0, full-dup, 1G, no-pause, no-asym_p*/
+		fixed-link = <0 1 1000 0 0>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc1>;
+	};
+
+	/* admin and debug port (UCC4, MDIO 0x00, RMII) */
+	enet_admin: ucc@3200 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <4>;
+		reg = <0x3200 0x200>;
+		interrupts = <35>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk17";
+		phy-handle = <&phy_admin>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc4>;
+	};
+
+	/* mate backplane port (UCC5, MDIO 0x08, RMII) */
+	enet_mate: ucc@2400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <5>;
+		reg = <0x2400 0x200>;
+		interrupts = <40>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_mate>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc5>;
+	};
+
+	mdio@3320 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x3320 0x18>;
+		compatible = "fsl,ucc-mdio";
+
+		/* admin front port (UCC4, MDIO 0x00, RMII) */
+		phy_admin: ethernet-phy@00 {
+			reg = <0x0>;
+		};
+
+		/* mate bp port (UCC5, MDIO 0x08, RMII) */
+		phy_mate: ethernet-phy@08 {
+			reg = <0x08>;
+		};
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000
+		   1 0 0xe8000000 0x01000000
+		   3 0 0xa0000000 0x10000000
+		   4 0 0xb0000000 0x10000000>;
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x04000000>;
+		nornand = "nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xC0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xE0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
+
+#include "kmcoge5ne-uboot.dtsi"

diff --git a/arch/powerpc/dts/kmeter1-uboot.dtsi b/arch/powerpc/dts/kmeter1-uboot.dtsi
new file mode 100644
index 0000000..898fa7d
--- /dev/null
+++ b/arch/powerpc/dts/kmeter1-uboot.dtsi

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA kmeter1 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	aliases {
+		/delete-property/ ethernet1;
+		/delete-property/ ethernet2;
+		/delete-property/ ethernet3;
+		/delete-property/ ethernet4;
+		/delete-property/ ethernet5;
+		/delete-property/ ethernet6;
+	};
+};
+
+&enet_estar1 {
+	status = "disabled";
+};
+
+&enet_estar2 {
+	status = "disabled";
+};
+
+&enet_eth1 {
+	status = "disabled";
+};
+
+&enet_eth2 {
+	status = "disabled";
+};
+
+&enet_eth3 {
+	status = "disabled";
+};
+
+&enet_eth4 {
+	status = "disabled";
+};

diff --git a/arch/powerpc/dts/kmeter1.dts b/arch/powerpc/dts/kmeter1.dts
new file mode 100644
index 0000000..f1f7995
--- /dev/null
+++ b/arch/powerpc/dts/kmeter1.dts

@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA KMETER1 Device Tree Source
+ *
+ * 2008-2011 DENX Software Engineering GmbH
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include "km836x.dtsi"
+
+/ {
+	model = "KMETER1";
+	compatible = "ABB,KMETER1";
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		ethernet1 = &enet_estar1;
+		ethernet2 = &enet_estar2;
+		ethernet3 = &enet_eth1;
+		ethernet4 = &enet_eth2;
+		ethernet5 = &enet_eth3;
+		ethernet6 = &enet_eth4;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@48 {
+				label = "Top";
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+
+			temp@49 {
+				label = "Control";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "Power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+
+			temp@4b {
+				label = "Front";
+				compatible = "national,lm75";
+				reg = <0x4b>;
+			};
+		};
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&par_io {
+	pio_ucc1: ucc_pin@0 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   */
+			0   2  1  0  1  0	/* MDC    */
+
+			0   3  1  0  1  0	/* TxD0   */
+			0   4  1  0  1  0	/* TxD1   */
+			0   5  1  0  1  0	/* TxD2   */
+			0   6  1  0  1  0	/* TxD3   */
+			0   9  2  0  1  0	/* RxD0   */
+			0  10  2  0  1  0	/* RxD1   */
+			0  11  2  0  1  0	/* RxD2   */
+			0  12  2  0  1  0	/* RxD3   */
+			0   7  1  0  1  0	/* TX_EN  */
+			0   8  1  0  1  0	/* TX_ER  */
+			0  15  2  0  1  0	/* RX_DV  */
+			0  16  2  0  1  0	/* RX_ER  */
+			0   0  2  0  1  0	/* RX_CLK */
+			2   9  1  0  3  0	/* GTX_CLK - CLK10 */
+			2   8  2  0  1  0	/* GTX125  - CLK9  */
+		>;
+	};
+
+	pio_ucc2: ucc_pin@1 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   */
+			0   2  1  0  1  0	/* MDC    */
+
+			0  17  1  0  1  0	/* TxD0   */
+			0  18  1  0  1  0	/* TxD1   */
+			0  19  1  0  1  0	/* TxD2   */
+			0  20  1  0  1  0	/* TxD3   */
+			0  23  2  0  1  0	/* RxD0   */
+			0  24  2  0  1  0	/* RxD1   */
+			0  25  2  0  1  0	/* RxD2   */
+			0  26  2  0  1  0	/* RxD3   */
+			0  21  1  0  1  0	/* TX_EN  */
+			0  22  1  0  1  0	/* TX_ER  */
+			0  29  2  0  1  0	/* RX_DV  */
+			0  30  2  0  1  0	/* RX_ER  */
+			0  31  2  0  1  0	/* RX_CLK */
+			2  2   1  0  2  0	/* GTX_CLK - CLK3  */
+			2  3   2  0  1  0	/* GTX125  - CLK4  */
+		>;
+	};
+
+	pio_ucc4: ucc_pin@3 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			1  14  1  0  1  0	/* TxD0   (PB14, out, f1) */
+			1  15  1  0  1  0	/* TxD1   (PB15, out, f1) */
+			1  20  2  0  1  0	/* RxD0   (PB20, in,  f1) */
+			1  21  2  0  1  0	/* RxD1   (PB21, in,  f1) */
+			1  18  1  0  1  0	/* TX_EN  (PB18, out, f1) */
+			1  26  2  0  1  0	/* RX_DV  (PB26, in,  f1) */
+			1  27  2  0  1  0	/* RX_ER  (PB27, in,  f1) */
+
+			2  16  2  0  1  0	/* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_ucc5: ucc_pin@4 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			3   0  1  0  1  0	/* TxD0  (PD0,  out, f1) */
+			3   1  1  0  1  0	/* TxD1  (PD1,  out, f1) */
+			3   6  2  0  1  0	/* RxD0  (PD6,   in, f1) */
+			3   7  2  0  1  0	/* RxD1  (PD7,   in, f1) */
+			3   4  1  0  1  0	/* TX_EN (PD4,  out, f1) */
+			3  12  2  0  1  0	/* RX_DV (PD12,  in, f1) */
+			3  13  2  0  1  0	/* RX_ER (PD13,  in, f1) */
+		>;
+	};
+
+	pio_ucc6: ucc_pin@5 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			3  14  1  0  1  0	/* TxD0   (PD14, out, f1) */
+			3  15  1  0  1  0	/* TxD1   (PD15, out, f1) */
+			3  20  2  0  1  0	/* RxD0   (PD20, in,  f1) */
+			3  21  2  0  1  0	/* RxD1   (PD21, in,  f1) */
+			3  18  1  0  1  0	/* TX_EN  (PD18, out, f1) */
+			3  26  2  0  1  0	/* RX_DV  (PD26, in,  f1) */
+			3  27  2  0  1  0	/* RX_ER  (PD27, in,  f1) */
+		>;
+	};
+
+	pio_ucc7: ucc_pin@6 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			4   0  1  0  1  0	/* TxD0   (PE0,  out, f1) */
+			4   1  1  0  1  0	/* TxD1   (PE1,  out, f1) */
+			4   6  2  0  1  0	/* RxD0   (PE6,   in, f1) */
+			4   7  2  0  1  0	/* RxD1   (PE7,   in, f1) */
+			4   4  1  0  1  0	/* TX_EN  (PE4,  out, f1) */
+			4  12  2  0  1  0	/* RX_DV  (PE12,  in, f1) */
+			4  13  2  0  1  0	/* RX_ER  (PE13,  in, f1) */
+		>;
+	};
+
+	pio_ucc8: ucc_pin@7 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			4  14  1  0  2  0	/* TxD0   (PE14, out, f2) */
+			4  15  1  0  1  0	/* TxD1   (PE15, out, f1) */
+			4  20  2  0  1  0	/* RxD0   (PE20, in,  f1) */
+			4  21  2  0  1  0	/* RxD1   (PE21, in,  f1) */
+			4  18  1  0  1  0	/* TX_EN  (PE18, out, f1) */
+			4  26  2  0  1  0	/* RX_DV  (PE26, in,  f1) */
+			4  27  2  0  1  0	/* RX_ER  (PE27, in,  f1) */
+
+			2  15  2  0  1  0	/* UCCx_RMII_CLK (CLK16) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			4  28  3  0  3  0	/* SPI_MOSI (PE28, out, f3  */
+			4  30  3  0  3  0	/* SPI_CLK  (PE30, out, f3  */
+		>;
+	};
+
+	/* UCC3 as HDLC controller for ICN */
+	pio5: ucc_pin@02 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			1   0  1  0  1  0   /* TxD0 */
+			1   6  2  0  1  0   /* RxD0 */
+			1  12  2  0  1  0   /* CTS */
+			2  11  2  0  1  0   /* TX-CLK12 */
+		>;
+	};
+
+	pio_tdm: tdm_pin@00 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			/* TDMa */
+			0  8  3  0  2  0	/* RxD0    (PA8,  bi, f2) */
+			0  13 3  0  2  0	/* TxD0    (PA13, bi, f2) */
+			0  14 2  0  2  0	/* RSync0  (PA14, in, f2) */
+			2  7  2  0  1  0	/* RxClk8  (PC7,  in, f1) */
+			/* TDMb */
+			0  27 3  0  2  0	/* RxD1    (PA27, bi, f2) */
+			0  22 3  0  2  0	/* TxD1    (PA22, bi, f2) */
+			0  28 2  0  2  0	/* RSync1  (PA28, in, f2) */
+			2  1  2  0  1  0	/* RxClk2  (PC1,  in, f1) */
+			/* TDMc */
+			1  5  3  0  2  0	/* RxD2    (PB5,  bi, f2) */
+			1  8  3  0  2  0	/* TxD2    (PB8,  bi, f2) */
+			1  2  2  0  3  0	/* RSync2  (PB2,  in, f3) */
+			2  6  2  0  1  0	/* RxClk7  (PC6,  in, f1) */
+			/* TDMd */
+			1  22 3  0  2  0	/* RxD3    (PB22, bi, f2) */
+			1  19 3  0  1  0	/* TxD3    (PB19, bi, f1) */
+			1  16 2  0  2  0	/* RSync3  (PB16, in, f2) */
+			2  13 2  0  1  0	/* RxClk14 (PC13, in, f1) */
+			/* TDMe */
+			3  8  3  0  2  0	/* RxD4    (PD8,  bi, f2) */
+			3  5  3  0  2  0	/* TxD4    (PD5,  bi, f2) */
+			3  2  2  0  2  0	/* RSync4  (PD2 , in, f2) */
+			2  22 2  0  1  0	/* RxClk23 (PC22, in, f1) */
+			/* TDMf */
+			3  19 3  0  2  0	/* RxD5    (PD19, bi, f2) */
+			3  22 3  0  2  0	/* TxD5    (PD22, bi, f2) */
+			3  16 2  0  1  0	/* RSync5  (PD16, in, f1) */
+			2  17 2  0  1  0	/* RxClk18 (PC17, in, f1) */
+			/* TDMg */
+			4  8  3  0  2  0	/* RxD6    (PE8,  bi, f2) */
+			4  5  3  0  2  0	/* TxD6    (PE5,  bi, f2) */
+			4  2  2  0  1  0	/* RSync6  (PE2,  in, f1) */
+			2  19 2  0  1  0	/* RxClk20 (PC19, in, f1) */
+			/* TDMh */
+			4  19 3  0  2  0	/* RxD7    (PE19, bi, f2) */
+			4  22 3  0  3  0	/* TxD7    (PE22, bi, f3) */
+			4  16 2  0  2  0	/* RSync7  (PE16, in, f2) */
+			2  21 2  0  1  0	/* RxClk22 (PC21, in, f1) */
+			/* RxTxClk0/1 */
+			2  0  2  0  1  0	/* Clk1    (PC0,  in, f1) */
+			2  23 2  0  1  0	/* Clk24   (PC23, in, f1) */
+			/* RxTxSync0/1 */
+			2  10 2  0  1  0	/* Clk11   (PC10, in, f1) */
+			2  20 2  0  1  0>;	/* Clk21   (PC20, in, f1) */
+	};
+};
+
+&qe {
+	/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+	enet_estar1: ucc@2000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <1>;
+		reg = <0x2000 0x200>;
+		interrupts = <32>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk9";
+		phy-handle = <&phy_estar1>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc1>;
+	};
+
+	/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+	enet_estar2: ucc@3000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <2>;
+		reg = <0x3000 0x200>;
+		interrupts = <33>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk4";
+		phy-handle = <&phy_estar2>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc2>;
+	};
+
+	/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+	enet_piggy2: ucc@3200 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <4>;
+		reg = <0x3200 0x200>;
+		interrupts = <35>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk17";
+		phy-handle = <&phy_piggy2>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc4>;
+	};
+
+	/* Eth-1 (UCC5, MDIO 0x08, RMII) */
+	enet_eth1: ucc@2400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <5>;
+		reg = <0x2400 0x200>;
+		interrupts = <40>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth1>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc5>;
+	};
+
+	/* Eth-2 (UCC6, MDIO 0x09, RMII) */
+	enet_eth2: ucc@3400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <6>;
+		reg = <0x3400 0x200>;
+		interrupts = <41>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth2>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc6>;
+	};
+
+	/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+	enet_eth3: ucc@2600 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <7>;
+		reg = <0x2600 0x200>;
+		interrupts = <42>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth3>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc7>;
+	};
+
+	/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+	enet_eth4: ucc@3600 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <8>;
+		reg = <0x3600 0x200>;
+		interrupts = <43>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth4>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc8>;
+	};
+
+	mdio@3320 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x3320 0x18>;
+		compatible = "fsl,ucc-mdio";
+
+		/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+		phy_piggy2: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+
+		/* Eth-1 (UCC5, MDIO 0x08, RMII) */
+		phy_eth1: ethernet-phy@8 {
+			reg = <0x08>;
+		};
+
+		/* Eth-2 (UCC6, MDIO 0x09, RMII) */
+		phy_eth2: ethernet-phy@9 {
+			reg = <0x09>;
+		};
+
+		/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+		phy_eth3: ethernet-phy@a {
+			reg = <0x0a>;
+		};
+
+		/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+		phy_eth4: ethernet-phy@b {
+			reg = <0x0b>;
+		};
+
+		/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+		phy_estar1: ethernet-phy@10 {
+			interrupt-parent = <&ipic>;
+			interrupts = <17 0x8>;
+			reg = <0x10>;
+		};
+
+		/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+		phy_estar2: ethernet-phy@11 {
+			interrupt-parent = <&ipic>;
+			interrupts = <18 0x8>;
+			reg = <0x11>;
+		};
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000	/* LB 0 */
+		  1 0 0xe8000000 0x01000000	/* LB 1 */
+		  3 0 0xa0000000 0x10000000>;	/* LB 3 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x04000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xC0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xE0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
+
+#include "kmeter1-uboot.dtsi"

diff --git a/arch/powerpc/dts/kmopti2.dts b/arch/powerpc/dts/kmopti2.dts
new file mode 100644
index 0000000..23e3187
--- /dev/null
+++ b/arch/powerpc/dts/kmopti2.dts

@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA OPTI2 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "KMOPTI2";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0 /* TxD0 */
+			2   8  2  0  2  0 /* RxD0 */
+			2  29  2  0  2  0 /* CTS */
+			3  30  2  0  1  0 /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0 /* MDIO */
+			3   5  1  0  2  0 /* MDC  */
+
+			1 18  1  0  1  0 /* TxD0 */
+			1 19  1  0  1  0 /* TxD1 */
+			1 22  2  0  1  0 /* RxD0 */
+			1 23  2  0  1  0 /* RxD1 */
+			1 26  2  0  1  0 /* RX_ER */
+			1 28  2  0  1  0 /* RX_DV */
+			1 30  1  0  1  0 /* TX_EN */
+			1 31  2  0  1  0 /* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
+			3  1  3	 0  1  0 /* SPI_MISO (PD1, bi, f3)  */
+			3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
+		1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
+		2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
+		3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		use-advanced-sector-protection;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/kmsupc5.dts b/arch/powerpc/dts/kmsupc5.dts
new file mode 100644
index 0000000..60ca0d3
--- /dev/null
+++ b/arch/powerpc/dts/kmsupc5.dts

@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA SUPC5 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "SUPC5";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0	/* TxD0 */
+			2   8  2  0  2  0	/* RxD0 */
+			2  29  2  0  2  0	/* CTS */
+			3  30  2  0  1  0	/* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			/* UCC4_RMII_CLK (CLK17) */
+			3 10  2  0  3  0
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 * port  pin  dir  open_drain  assignment  has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&spi0 {
+	pio-handle = <&pio_spi>;
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/kmsupm5.dts b/arch/powerpc/dts/kmsupm5.dts
new file mode 100644
index 0000000..1cd11c3
--- /dev/null
+++ b/arch/powerpc/dts/kmsupm5.dts

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA SUPM5 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "SUPM5";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0	/* TxD0 */
+			2   8  2  0  2  0	/* RxD0 */
+			2  29  2  0  2  0	/* CTS */
+			3  30  2  0  1  0	/* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
+			3  1  3  0  1  0 /* SPI_MISO (PD1, bi, f3)  */
+			3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts
new file mode 100644
index 0000000..c9b21cf
--- /dev/null
+++ b/arch/powerpc/dts/kmtegr1.dts

@@ -0,0 +1,392 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA TEGR1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "KMTEGR1";
+	compatible = "ABB,kmpbec8309";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_zynq;
+		ethernet1 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8309@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <16384>;		// L1, 16K
+			i-cache-size = <16384>;		// L1, 16K
+			timebase-frequency = <66000000>;
+			bus-frequency = <264000000>;
+			clock-frequency = <264000000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc: soc8309@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <264000000>;
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <400000>;
+
+			mux@70 {
+				compatible = "nxp,pca9547";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/*
+					 * Inventory EEPROM of the
+					 * unit itself
+					 */
+					ivm@50 {
+						label = "MAIN_CTRL";
+						compatible = "dummy";
+						reg = <0x50>;
+					};
+				};
+
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/* Temperature sensors */
+					temp@48 {
+						label = "front";
+						compatible = "national,lm75";
+						reg = <0x48>;
+					};
+
+					temp@49 {
+						label = "board";
+						compatible = "national,lm75";
+						reg = <0x49>;
+					};
+
+					temp@4a {
+						label = "power";
+						compatible = "national,lm75";
+						reg = <0x4a>;
+					};
+
+					temp@4b {
+						label = "bottom";
+						compatible = "national,lm75";
+						reg = <0x4b>;
+					};
+				};
+
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+			};
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		dma@82a8 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
+			reg = <0x82a8 4>;
+			ranges = <0 0x8100 0x1a8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <71 8>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x80 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x100 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x180 0x28>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+		gpio1: gpio-controller@c00 {
+			#gpio-cells = <2>;
+			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
+			reg = <0xc00 0x100>;
+			interrupts = <75 0x8>;
+			interrupt-parent = <&ipic>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio-controller@d00 {
+			#gpio-cells = <2>;
+			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
+			reg = <0xd00 0x100>;
+			interrupts = <75 0x8>;
+			interrupt-parent = <&ipic>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		spi@7000 {
+			cell-index = <0>;
+			compatible = "fsl,spi";
+			reg = <0x7000 0x1000>;
+			interrupts = <16 0x8>;
+			interrupt-parent = <&ipic>;
+			mode = "cpu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* GPIO_15 chipselect for ZYNQ flash */
+			gpios = <&gpio1 15 0>;
+
+			zynq_flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spansion,m25p80";
+				reg = <0>;
+				spi-max-frequency = <4000000>;
+				m25p,fast-read;
+				partition@0 {
+					label = "bootloader";
+					reg = <0x0 0x01000000>;
+				};
+			};
+		};
+	};
+
+	qe: qe@e0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe";
+		ranges = <0x0 0xe0100000 0x00100000>;
+		reg = <0xe0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <396000000>;
+		fsl,qe-num-snums = <32>;
+
+		muram@10000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe-muram", "fsl,cpm-muram";
+			ranges = <0x0 0x00010000 0x00004000>;
+
+			data-only@0 {
+				compatible = "fsl,qe-muram-data",
+					     "fsl,cpm-muram-data";
+				reg = <0x0 0x4000>;
+			};
+		};
+
+		/* ZYNQ (UCC1, MDIO 0x10, MII) */
+		enet_zynq: ethernet@2000 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <1>;
+			reg = <0x2000 0x200>;
+			interrupts = <32>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			/*id=0, full-dup, 100M, no-pause, no-asym_p*/
+			fixed-link = <0 1 100 0 0>;
+			rx-clock-name = "clk9";
+			tx-clock-name = "clk10";
+			phy-connection-type = "mii";
+		};
+
+		/* Piggy2 (UCC3, MDIO 0x00, RMII) */
+		enet_piggy2: ucc@2200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <3>;
+			reg = <0x2200 0x200>;
+			interrupts = <34>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			rx-clock-name = "none";
+			tx-clock-name = "clk12";
+			phy-handle = <&phy_piggy2>;
+			phy-connection-type = "rmii";
+		};
+
+		mdio@2320 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2320 0x38>;
+			compatible = "fsl,ucc-mdio";
+
+			/* Piggy2 (UCC3, MDIO 0x00, RMII) */
+			phy_piggy2: ethernet-phy@0 {
+				reg = <0x0>;
+				device_type = "ethernet-phy";
+			};
+
+			/* Explicitly set the tbi-phy to a non-zero address
+			 * so that it does not conflict with phy_piggy2 that
+			 * is unfortunately at address 0
+			 */
+			tbi1: tbi-phy@1 {
+				reg = <0x1>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		qeic: interrupt-controller@80 {
+			interrupt-controller;
+			compatible = "fsl,qe-ic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x80 0x80>;
+			big-endian;
+			interrupts = <32 8 33 8>;
+			interrupt-parent = <&ipic>;
+		};
+		bootcount@0x13ff8 {
+			device_type = "bootcount";
+			compatible = "u-boot,bootcount";
+			reg = <0x13ff8 0x08>;
+		};
+
+	};
+	localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+		ranges = <0 0 0xf0000000 0x04000000
+			1 0 0xe8000000 0x01000000
+			2 0 0xe0000000 0x10000000
+			3 0 0xb0000000 0x10000000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0x00000000 0x04000000>;
+			bank-width = <2>;
+			nornand = "nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			use-advanced-sector-protection;
+			partition@0 { /* 768KB */
+				label = "u-boot";
+				reg = <0 0xc0000>;
+			};
+			partition@c0000 { /* 256KB */
+				label = "qe-fw";
+				reg = <0xc0000 0x40000>;
+			};
+			partition@100000 { /* 128KB */
+				label = "env";
+				reg = <0x100000 0x20000>;
+			};
+			partition@120000 { /* 128KB */
+				label = "envred";
+				reg = <0x120000 0x20000>;
+			};
+			partition@140000 { /* 64256KB */
+				label = "ubi0";
+				reg = <0x140000 0x3EC0000>;
+			};
+		};
+	};
+};
+
+#include "km8309-uboot.dtsi"

diff --git a/arch/powerpc/dts/kmtepr2.dts b/arch/powerpc/dts/kmtepr2.dts
new file mode 100644
index 0000000..5a272ec6
--- /dev/null
+++ b/arch/powerpc/dts/kmtepr2.dts

@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA TEPR2 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "KMTEPR2";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0	/* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port pin dir open_drain assignment has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
+		1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
+		2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
+		3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		use-advanced-sector-protection;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/kmtuge1.dts b/arch/powerpc/dts/kmtuge1.dts
new file mode 100644
index 0000000..8a7b5a4
--- /dev/null
+++ b/arch/powerpc/dts/kmtuge1.dts

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA TUGE1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "TUGE1";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3  10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port pin dir open_drain assignment has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 PAXI */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/kmtuxa1.dts b/arch/powerpc/dts/kmtuxa1.dts
new file mode 100644
index 0000000..c2681c5
--- /dev/null
+++ b/arch/powerpc/dts/kmtuxa1.dts

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ABB PGGA TUXA1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "TUXA1";
+	compatible = "ABB,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+		>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port  pin  dir  open_drain  assignment  has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000     /* LB 2 LPXF */
+		  3 0 0xb0000000 0x10000000>;	/* LB 3 PINC2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};

diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c492..360d254 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts

@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"

diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7..062086a 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts

@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"

diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2..c2aecde 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi

@@ -4,11 +4,78 @@
  *
  * Copyright 2020 NXP
  */
+/ {
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
 &soc {
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy1: ethernet-phy@1 {
+			reg = <0x0>;
+		};
+
+		phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		tbi-phy@3 {
+			device_type = "tbi-phy";
+			reg = <0x3>;
+		};
+	};
+
+	mdio@25000 {
+		tbi0: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		tbi-handle = <&tbi0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy2>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
 	i2c@3000 {
 		rtc@68 {
 			compatible = "pericom,pt7c4338";
 			reg = <0x68>;
 		};
 	};
+
+	spi@7000 {
+		status = "okay";
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>;
+			spi-max-frequency = <10000000>; /* input clock */
+		};
+	};
 };

diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441..2e7eb0e 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi

@@ -23,8 +23,43 @@
 		single-cpu-affinity;
 		last-interrupt-source = <255>;
 	};
+
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <1>;
+		status = "disabled";
+	};
+
 /include/ "pq3-i2c-0.dtsi"
 /include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-2.dtsi"
+	enet2: ethernet@b2000 {
+		queue-group@b2000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+
+	};
 };
 
 /* controller at 0x9000 */

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e8..03b6886 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi

@@ -44,10 +44,35 @@
 		clock-frequency = <0>;
 	};
 
-	/include/ "pq3-i2c-0.dtsi"
-	/include/ "pq3-i2c-1.dtsi"
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: enet0_grp2: ethernet@b0000 {
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: enet1_grp2: ethernet@b1000 {
+	};
+
+/include/ "pq3-etsec2-2.dtsi"
+	enet2: enet2_grp2: ethernet@b2000 {
+	};
 };
 
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
 /* PCIe controller base address 0x9000 */
 &pci1 {
 	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";

diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa61..ab42325 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts

@@ -30,6 +30,22 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
+/include/ "p1020rdb-pc.dtsi"
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};

diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 0000000..6bf424f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupt-parent = <&mpic>;
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupt-parent = <&mpic>;
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+		};
+
+		tbi0: tbi-phy@11 {
+			device_type = "tbi-phy";
+			reg = <0x11>;
+		};
+	};
+
+	mdio@25000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-connection-type = "rgmii-id";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy0>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};

diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4..708f9a9 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts

@@ -30,6 +30,22 @@
 		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
+/include/ "p1020rdb-pc.dtsi"
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};

diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a0..b05f3de 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts

@@ -17,6 +17,51 @@
 
 	soc: soc@ffe00000 {
 		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				interrupts = <3 1 0 0>;
+				reg = <0x0>;
+			};
+
+			phy1: ethernet-phy@1 {
+				interrupts = <2 1 0 0>;
+				reg = <0x1>;
+			};
+		};
+
+		mdio@25000 {
+			tbi1: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		mdio@26000 {
+			tbi2: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy0>;
+			tbi-handle = <&tbi1>;
+			phy-connection-type = "sgmii";
+		};
+
+		enet2: ethernet@b2000 {
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+		};
 	};
 
 	pci1: pcie@ffe09000 {
@@ -30,6 +75,21 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
 /include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093d..6d46f7d 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi

@@ -38,8 +38,21 @@
 		clock-frequency = <0>;
 	};
 
-	/include/ "pq3-i2c-0.dtsi"
-	/include/ "pq3-i2c-1.dtsi"
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
 };
 
 /* PCIe controller base address 0x8000 */

diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4..b37931a 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts

@@ -35,6 +35,22 @@
 		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};

diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 0000000..0d2acc7
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi

@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio@24520 {
+		phy0: ethernet-phy@0 {
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+			};
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+			};
+	};
+
+	mdio@25520 {
+		tbi0: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26520 {
+		status = "disabled";
+	};
+
+	enet0: ethernet@24000 {
+		phy-connection-type = "rgmii-id";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+	};
+
+	enet1: ethernet@25000 {
+		tbi-handle = <&tbi0>;
+		phy-handle = <&phy0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@26000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};

diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519..ecdc022 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts

@@ -35,6 +35,22 @@
 		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+
+	aliases {
+		spi0 = &espi0;
+	};
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 95931e2..ad09b13 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi

@@ -60,6 +60,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0: usb@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
index 9d59f9c..0fa1f09 100644
--- a/arch/powerpc/dts/p2041rdb.dts
+++ b/arch/powerpc/dts/p2041rdb.dts

@@ -26,6 +26,7 @@
 		phy_sgmii_1e = &phy_sgmii_1e;
 		phy_sgmii_1f = &phy_sgmii_1f;
 		phy_xgmii_2 = &phy_xgmii_2;
+		spi0 = &espi0;
 	};
 
 	soc: soc@ffe000000 {
@@ -111,4 +112,16 @@
 	};
 };
 
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
 /include/ "p2041si-post.dtsi"

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 3152683..e34117b 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi

@@ -60,6 +60,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0: usb@fe210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts
index b984dde..069dae3 100644
--- a/arch/powerpc/dts/p3041ds.dts
+++ b/arch/powerpc/dts/p3041ds.dts

@@ -27,6 +27,7 @@
 		emi1_rgmii = &hydra_mdio_rgmii;
 		emi1_sgmii = &hydra_mdio_sgmii;
 		emi2_xgmii = &hydra_mdio_xgmii;
+		spi0 = &espi0;
 	};
 
 	soc: soc@ffe000000 {
@@ -142,4 +143,16 @@
 	};
 };
 
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
 /include/ "p3041si-post.dtsi"

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 4a80561..8ab5cf5 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi

@@ -80,6 +80,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		esdhc: esdhc@114000 {
 			compatible = "fsl,esdhc";
 			reg = <0x114000 0x1000>;

diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts
index 53c51d4..d5618f1 100644
--- a/arch/powerpc/dts/p4080ds.dts
+++ b/arch/powerpc/dts/p4080ds.dts

@@ -27,6 +27,7 @@
 		emi1_rgmii = &p4080mdio0;
 		emi2_slot4 = &p4080xmdio1;
 		emi2_slot5 = &p4080xmdio3;
+		spi0 = &espi0;
 	};
 
 	soc: soc@ffe000000 {
@@ -204,4 +205,16 @@
 	};
 };
 
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
 /include/ "p4080si-post.dtsi"

diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index 4598857..10402cf 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi

@@ -59,6 +59,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts
index 6ebc801..c2ec765 100644
--- a/arch/powerpc/dts/p5040ds.dts
+++ b/arch/powerpc/dts/p5040ds.dts

@@ -39,6 +39,7 @@
 		hydra_sg_slot6 = &hydra_sg_slot6;
 		hydra_xg_slot1 = &hydra_xg_slot1;
 		hydra_xg_slot2 = &hydra_xg_slot2;
+		spi0 = &espi0;
 	};
 
 	soc: soc@ffe000000 {
@@ -265,4 +266,16 @@
 	};
 };
 
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
 /include/ "p5040si-post.dtsi"

diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 0000000..8800243
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x24000 0x1000>;
+	ranges = <0x0 0x24000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-mdio";
+	reg = <0x24520 0x20>;
+};

diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 0000000..2bc62d1
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@25000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x25000 0x1000>;
+	ranges = <0x0 0x25000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+
+mdio@25520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x25520 0x20>;
+};

diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi
new file mode 100644
index 0000000..d45865f
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@26000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <2>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x26000 0x1000>;
+	ranges = <0x0 0x26000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+
+mdio@26520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x26520 0x20>;
+};

diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi
new file mode 100644
index 0000000..853a273
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@27000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <3>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x27000 0x1000>;
+	ranges = <0x0 0x27000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+
+mdio@27520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x27520 0x20>;
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi
new file mode 100644
index 0000000..f9d3d04
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@24000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-mdio";
+	reg = <0x24000 0x1000 0xb0030 0x4>;
+};
+
+ethernet@b0000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb0000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b0000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb0000 0x1000>;
+		interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi
new file mode 100644
index 0000000..6c01481
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@25000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-tbi";
+	reg = <0x25000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b1000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb1000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b1000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb1000 0x1000>;
+		interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi
new file mode 100644
index 0000000..2a597c0
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@26000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-tbi";
+	reg = <0x26000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b2000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb2000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b2000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb2000 0x1000>;
+		interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 0000000..16752a7
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet0_grp2 {
+	queue-group@b4000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb4000 0x1000>;
+		interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 0000000..0464938
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet1_grp2 {
+	queue-group@b5000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb5000 0x1000>;
+		interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 0000000..fe8003c
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet2_grp2 {
+	queue-group@b6000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb6000 0x1000>;
+		interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
+	};
+};

diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
index 32aaa4a..eeba99f 100644
--- a/arch/powerpc/dts/t1024rdb.dts
+++ b/arch/powerpc/dts/t1024rdb.dts

@@ -17,6 +17,7 @@
 
 	aliases {
 		sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
+		spi0 = &espi0;
 	};
 
 	soc: soc@ffe000000 {
@@ -63,7 +64,18 @@
 			};
 		};
 	};
+};
 
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
 };
 
 #include "t1024si-post.dtsi"

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 521825d..cf8962a 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi

@@ -49,6 +49,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
index 16a8ed4..3584c06 100644
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ b/arch/powerpc/dts/t1042d4rdb.dts

@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index 0a08a69..2c7e5b4 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi

@@ -59,6 +59,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index a9e9b40..7e446b1 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi

@@ -69,6 +69,16 @@
 			voltage-ranges = <1800 1800 3300 3300>;
 		};
 
+		espi0: spi@110000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc8536-espi";
+			reg = <0x110000 0x1000>;
+			interrupts = <53 0x2 0 0>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb0: usb@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts
index 1819a08..f9e786b 100644
--- a/arch/powerpc/dts/t2080qds.dts
+++ b/arch/powerpc/dts/t2080qds.dts

@@ -14,4 +14,37 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25wf040", "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "eon,en25s64", "jedec,spi-nor";
+		reg = <2>;
+		spi-max-frequency = <10000000>;
+	};
+
 };

diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
index 49c1765..34ec6a7 100644
--- a/arch/powerpc/dts/t2080rdb.dts
+++ b/arch/powerpc/dts/t2080rdb.dts

@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor"; /* 16MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 9b5902f..498da4f 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi

@@ -99,6 +99,15 @@
 			clock-frequency = <0x0>;
 		};
 
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
 		usb@210000 {
 			compatible = "fsl-usb2-mph";
 			reg = <0x210000 0x1000>;

diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
index f67d7ce..635065a 100644
--- a/arch/powerpc/dts/t4240rdb.dts
+++ b/arch/powerpc/dts/t4240rdb.dts

@@ -14,4 +14,19 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
 };

diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 8c8ed99..b903e6e 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c

@@ -298,8 +298,8 @@
 	if (!images->ft_addr)
 		return;
 
-	base = (u64)gd->bd->bi_memstart;
-	size = (u64)gd->bd->bi_memsize;
+	base = (u64)gd->ram_base;
+	size = (u64)gd->ram_size;
 
 	off = fdt_path_offset(images->ft_addr, "/memory");
 	if (off < 0)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 009a545..aaa3b83 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig

@@ -155,10 +155,6 @@
 config SIFIVE_CLINT
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE
-	select REGMAP
-	select SYSCON
-	select SPL_REGMAP if SPL
-	select SPL_SYSCON if SPL
 	help
 	  The SiFive CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
@@ -177,22 +173,10 @@
 config ANDES_PLMT
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE
-	select REGMAP
-	select SYSCON
-	select SPL_REGMAP if SPL
-	select SPL_SYSCON if SPL
 	help
 	  The Andes PLMT block holds memory-mapped mtime register
 	  associated with timer tick.
 
-config RISCV_RDTIME
-	bool
-	default y if RISCV_SMODE || SPL_RISCV_SMODE
-	help
-	  The provides the riscv_get_time() API that is implemented using the
-	  standard rdtime instruction. This is the case for S-mode U-Boot, and
-	  is useful for processors that support rdtime in M-mode too.
-
 config SYS_MALLOC_F_LEN
 	default 0x1000
 

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 8d8d71d..5cb5bb5 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig

@@ -3,7 +3,7 @@
 	select ARCH_EARLY_INIT_R
 	imply CPU
 	imply CPU_RISCV
-	imply RISCV_TIMER
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply SPL_CPU_SUPPORT

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index bfa2d4a..85592f5 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c

@@ -72,6 +72,17 @@
 	return 0;
 }
 
+/*
+ * This is called on secondary harts just after the IPI is init'd. Currently
+ * there's nothing to do, since we just need to clear any existing IPIs, and
+ * that is handled by the sending of an ipi itself.
+ */
+#if CONFIG_IS_ENABLED(SMP)
+static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
+{
+}
+#endif
+
 int arch_cpu_init_dm(void)
 {
 	int ret;
@@ -111,6 +122,15 @@
 	ret = riscv_init_ipi();
 	if (ret)
 		return ret;
+
+	/*
+	 * Clear all pending IPIs on secondary harts. We don't do anything on
+	 * the boot hart, since we never send an IPI to ourselves, and no
+	 * interrupts are enabled
+	 */
+	ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
+	if (ret)
+		return ret;
 #endif
 
 	return 0;

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 53e1963..ac3f183 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig

@@ -10,7 +10,7 @@
 	select SPL_RAM if SPL
 	imply CPU
 	imply CPU_RISCV
-	imply RISCV_TIMER
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply CMD_CPU
 	imply SPL_CPU_SUPPORT

diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b2cb155..f4c2e26 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig

@@ -7,7 +7,7 @@
 	select ARCH_EARLY_INIT_R
 	imply CPU
 	imply CPU_RISCV
-	imply RISCV_TIMER
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply CMD_CPU
 	imply SPL_CPU_SUPPORT

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bf9fdf3..bbc737e 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S

@@ -43,14 +43,32 @@
 	csrr	a0, CSR_MHARTID
 #endif
 
-	/* save hart id and dtb pointer */
+	/*
+	 * Save hart id and dtb pointer. The thread pointer register is not
+	 * modified by C code. It is used by secondary_hart_loop.
+	 */
 	mv	tp, a0
 	mv	s1, a1
 
+	/*
+	 * Set the global data pointer to a known value in case we get a very
+	 * early trap. The global data pointer will be set its actual value only
+	 * after it has been initialized.
+	 */
+	mv	gp, zero
+
+	/*
+	 * Set the trap handler. This must happen after initializing gp because
+	 * the handler may use it.
+	 */
 	la	t0, trap_entry
 	csrw	MODE_PREFIX(tvec), t0
 
-	/* mask all interrupts */
+	/*
+	 * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
+	 * for U-Boot, but we will need to read m/sip to determine if we get an
+	 * IPI
+	 */
 	csrw	MODE_PREFIX(ie), zero
 
 #if CONFIG_IS_ENABLED(SMP)
@@ -65,8 +83,6 @@
 #else
 	li	t0, SIE_SSIE
 #endif
-	/* Clear any pending IPIs */
-	csrc	MODE_PREFIX(ip), t0
 	csrs	MODE_PREFIX(ie), t0
 #endif
 
@@ -87,10 +103,10 @@
 	jal	board_init_f_alloc_reserve
 
 	/*
-	 * Set global data pointer here for all harts, uninitialized at this
-	 * point.
+	 * Save global data pointer for later. We don't set it here because it
+	 * is not initialized yet.
 	 */
-	mv	gp, a0
+	mv	s0, a0
 
 	/* setup stack */
 #if CONFIG_IS_ENABLED(SMP)
@@ -111,6 +127,14 @@
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
 #else
+	/*
+	 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
+	 * encounters a pending IPI on boot it is liable to jump to whatever
+	 * memory happens to be in ipi_data.addr on boot. It may also run into
+	 * problems if it encounters an exception too early (because printf/puts
+	 * accesses gd).
+	 */
+	mv	gp, s0
 	bnez	tp, secondary_hart_loop
 #endif
 
@@ -127,16 +151,21 @@
 
 #ifndef CONFIG_XIP
 	la	t0, available_harts_lock
-	fence	rw, w
-	amoswap.w zero, zero, 0(t0)
+	amoswap.w.rl zero, zero, 0(t0)
 
 wait_for_gd_init:
 	la	t0, available_harts_lock
 	li	t1, 1
-1:	amoswap.w t1, t1, 0(t0)
-	fence	r, rw
+1:	amoswap.w.aq t1, t1, 0(t0)
 	bnez	t1, 1b
 
+	/*
+	 * Set the global data pointer only when gd_t has been initialized.
+	 * This was already set by arch_setup_gd on the boot hart, but all other
+	 * harts' global data pointers gets set here.
+	 */
+	mv	gp, s0
+
 	/* register available harts in the available_harts mask */
 	li	t1, 1
 	sll	t1, t1, tp
@@ -144,8 +173,7 @@
 	or	t2, t2, t1
 	SREG	t2, GD_AVAILABLE_HARTS(gp)
 
-	fence	rw, w
-	amoswap.w zero, zero, 0(t0)
+	amoswap.w.rl zero, zero, 0(t0)
 
 	/*
 	 * Continue on hart lottery winner, others branch to
@@ -395,6 +423,10 @@
 	mv	gp, a2
 #endif
 
+/*
+ * Interrupts are disabled globally, but they can still be read from m/sip. The
+ * wfi function will wake us up if we get an IPI, even if we do not trap.
+ */
 secondary_hart_loop:
 	wfi
 

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 5302677..a06e1b1 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi

@@ -55,9 +55,13 @@
 			reg = <0x0 0x10070000 0x0 0x1000>;
 			fuse-count = <0x1000>;
 		};
-		clint@2000000 {
+		clint: clint@2000000 {
 			compatible = "riscv,clint0";
-			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+					       &cpu1_intc 3 &cpu1_intc 7
+					       &cpu2_intc 3 &cpu2_intc 7
+					       &cpu3_intc 3 &cpu3_intc 7
+					       &cpu4_intc 3 &cpu4_intc 7>;
 			reg = <0x0 0x2000000 0x0 0xc0000>;
 			u-boot,dm-spl;
 		};

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 5d0c928..1996149 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi

@@ -34,6 +34,10 @@
 
 };
 
+&clint {
+	clocks = <&rtcclk>;
+};
+
 &qspi0 {
 	u-boot,dm-spl;
 

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2546c7d..84cff51 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi

@@ -17,6 +17,8 @@
 	compatible = "kendryte,k210";
 
 	aliases {
+		cpu0 = &cpu0;
+		cpu1 = &cpu1;
 		dma0 = &dmac0;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1_0;
@@ -126,14 +128,13 @@
 			read-only;
 		};
 
-		clint0: interrupt-controller@2000000 {
+		clint0: clint@2000000 {
 			#interrupt-cells = <1>;
 			compatible = "kendryte,k210-clint", "riscv,clint0";
 			reg = <0x2000000 0xC000>;
-			interrupt-controller;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>;
-			clocks = <&sysclk K210_CLK_CPU>;
+			clocks = <&sysclk K210_CLK_CLINT>;
 		};
 
 		plic0: interrupt-controller@C000000 {

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index b711fcc..d3a0b1d 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h

@@ -24,9 +24,6 @@
 #ifdef CONFIG_ANDES_PLIC
 	void __iomem *plic;	/* plic base address */
 #endif
-#ifdef CONFIG_ANDES_PLMT
-	void __iomem *plmt;	/* plmt base address */
-#endif
 #if CONFIG_IS_ENABLED(SMP)
 	struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif

diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 1b42885..2dae080 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h

@@ -18,14 +18,21 @@
  * IPI data structure. The hart ID is inserted by the hart handling the IPI and
  * calling the function.
  *
+ * @valid is used to determine whether a sent IPI originated from U-Boot. It is
+ * initialized to zero by board_init_f_alloc_reserve. When U-Boot sends its
+ * first IPI, it is set to 1. This prevents already-pending IPIs not sent by
+ * U-Boot from being taken.
+ *
  * @addr: Address of function
  * @arg0: First argument of function
  * @arg1: Second argument of function
+ * @valid: Whether this IPI is valid
  */
 struct ipi_data {
 	ulong addr;
 	ulong arg0;
 	ulong arg1;
+	unsigned int valid;
 };
 
 /**

diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index 26a008c..c3629e4 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h

@@ -7,13 +7,13 @@
 #define _ASM_SYSCON_H
 
 /*
- * System controllers in a RISC-V system
+ * System controllers in a RISC-V system. These should only be used for
+ * identifying IPI controllers. Other devices should use DM to probe.
  */
 enum {
 	RISCV_NONE,
 	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
 	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
-	RISCV_SYSCON_PLMT,	/* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 6c503ff..10ac5b0 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile

@@ -15,7 +15,6 @@
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 else
-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index c2a8fe4..267d6a1 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c

@@ -41,53 +41,45 @@
 	return 0;
 }
 
-static int init_plic(void)
+int riscv_init_ipi(void)
 {
-	struct udevice *dev;
-	ofnode node;
 	int ret;
+	long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+	ofnode node;
+	struct udevice *dev;
 	u32 reg;
 
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+	gd->arch.plic = base;
+
 	ret = uclass_find_first_device(UCLASS_CPU, &dev);
 	if (ret)
 		return ret;
+	else if (!dev)
+		return -ENODEV;
 
-	if (dev) {
-		ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
-			const char *device_type;
+	ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+		const char *device_type;
 
-			device_type = ofnode_read_string(node, "device_type");
-			if (!device_type)
-				continue;
+		device_type = ofnode_read_string(node, "device_type");
+		if (!device_type)
+			continue;
 
-			if (strcmp(device_type, "cpu"))
-				continue;
+		if (strcmp(device_type, "cpu"))
+			continue;
 
-			/* skip if hart is marked as not available */
-			if (!ofnode_is_available(node))
-				continue;
+		/* skip if hart is marked as not available */
+		if (!ofnode_is_available(node))
+			continue;
 
-			/* read hart ID of CPU */
-			ret = ofnode_read_u32(node, "reg", &reg);
-			if (ret == 0)
-				enable_ipi(reg);
-		}
-
-		return 0;
+		/* read hart ID of CPU */
+		ret = ofnode_read_u32(node, "reg", &reg);
+		if (ret == 0)
+			enable_ipi(reg);
 	}
 
-	return -ENODEV;
-}
-
-int riscv_init_ipi(void)
-{
-	long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
-
-	if (IS_ERR(ret))
-		return PTR_ERR(ret);
-	gd->arch.plic = ret;
-
-	return init_plic();
+	return 0;
 }
 
 int riscv_send_ipi(int hart)

diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index a7e90ca..a28c14c 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  *
  * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
  * The PLMT block holds memory-mapped mtime register
@@ -9,46 +10,43 @@
 
 #include <common.h>
 #include <dm.h>
-#include <regmap.h>
-#include <syscon.h>
+#include <timer.h>
 #include <asm/io.h>
-#include <asm/syscon.h>
 #include <linux/err.h>
 
 /* mtime register */
 #define MTIME_REG(base)			((ulong)(base))
 
-DECLARE_GLOBAL_DATA_PTR;
+static int andes_plmt_get_count(struct udevice *dev, u64 *count)
+{
+	*count = readq((void __iomem *)MTIME_REG(dev->priv));
 
-#define PLMT_BASE_GET(void)						\
-	do {								\
-		long *ret;						\
-									\
-		if (!gd->arch.plmt) {					\
-			ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
-			if (IS_ERR(ret))				\
-				return PTR_ERR(ret);			\
-			gd->arch.plmt = ret;				\
-		}							\
-	} while (0)
+	return 0;
+}
 
-int riscv_get_time(u64 *time)
-{
-	PLMT_BASE_GET();
+static const struct timer_ops andes_plmt_ops = {
+	.get_count = andes_plmt_get_count,
+};
 
-	*time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+static int andes_plmt_probe(struct udevice *dev)
+{
+	dev->priv = dev_read_addr_ptr(dev);
+	if (!dev->priv)
+		return -EINVAL;
 
-	return 0;
+	return timer_timebase_fallback(dev);
 }
 
 static const struct udevice_id andes_plmt_ids[] = {
-	{ .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+	{ .compatible = "riscv,plmt0" },
 	{ }
 };
 
 U_BOOT_DRIVER(andes_plmt) = {
 	.name		= "andes_plmt",
-	.id		= UCLASS_SYSCON,
+	.id		= UCLASS_TIMER,
 	.of_match	= andes_plmt_ids,
+	.ops		= &andes_plmt_ops,
+	.probe		= andes_plmt_probe,
 	.flags		= DM_FLAG_PRE_RELOC,
 };

diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 5b24202..d02062f 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c

@@ -75,7 +75,7 @@
 		pmp_mem.start = addr;
 		pmp_mem.end = addr + size - 1;
 		err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
-						 &phandle);
+						 &phandle, false);
 		if (err < 0 && err != -FDT_ERR_EXISTS) {
 			log_err("failed to add reserved memory: %d\n", err);
 			return err;

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index cd47e64..ad870e9 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c

@@ -78,7 +78,8 @@
 
 	printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
 	       epc, regs->ra, tval);
-	if (gd->flags & GD_FLG_RELOC)
+	/* Print relocation adjustments, but only if gd is initialized */
+	if (gd && gd->flags & GD_FLG_RELOC)
 		printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n",
 		       epc - gd->reloc_off, regs->ra - gd->reloc_off);
 

diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c
deleted file mode 100644
index e128d7f..0000000
--- a/arch/riscv/lib/rdtime.c
+++ /dev/null

@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
- * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- *
- * The riscv_get_time() API implementation that is using the
- * standard rdtime instruction.
- */
-
-#include <common.h>
-
-/* Implement the API required by RISC-V timer driver */
-int riscv_get_time(u64 *time)
-{
-#ifdef CONFIG_64BIT
-	u64 n;
-
-	__asm__ __volatile__ (
-		"rdtime %0"
-		: "=r" (n));
-
-	*time = n;
-#else
-	u32 lo, hi, tmp;
-
-	__asm__ __volatile__ (
-		"1:\n"
-		"rdtimeh %0\n"
-		"rdtime %1\n"
-		"rdtimeh %2\n"
-		"bne %0, %2, 1b"
-		: "=&r" (hi), "=&r" (lo), "=&r" (tmp));
-
-	*time = ((u64)hi << 32) | lo;
-#endif
-
-	return 0;
-}

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index b9a2c64..c9704c5 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c

@@ -8,9 +8,9 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
-#include <regmap.h>
-#include <syscon.h>
+#include <timer.h>
 #include <asm/io.h>
 #include <asm/syscon.h>
 #include <linux/err.h>
@@ -24,68 +24,74 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int riscv_get_time(u64 *time)
+int riscv_init_ipi(void)
 {
-	/* ensure timer register base has a sane value */
-	riscv_init_ipi();
+	int ret;
+	struct udevice *dev;
 
-	*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
+	ret = uclass_get_device_by_driver(UCLASS_TIMER,
+					  DM_GET_DRIVER(sifive_clint), &dev);
+	if (ret)
+		return ret;
+
+	gd->arch.clint = dev_read_addr_ptr(dev);
+	if (!gd->arch.clint)
+		return -EINVAL;
 
 	return 0;
 }
 
-int riscv_set_timecmp(int hart, u64 cmp)
+int riscv_send_ipi(int hart)
 {
-	/* ensure timer register base has a sane value */
-	riscv_init_ipi();
-
-	writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
+	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
 
 	return 0;
 }
 
-int riscv_init_ipi(void)
+int riscv_clear_ipi(int hart)
 {
-	if (!gd->arch.clint) {
-		long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
-
-		if (IS_ERR(ret))
-			return PTR_ERR(ret);
-		gd->arch.clint = ret;
-	}
+	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
 
 	return 0;
 }
 
-int riscv_send_ipi(int hart)
+int riscv_get_ipi(int hart, int *pending)
 {
-	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
 
 	return 0;
 }
 
-int riscv_clear_ipi(int hart)
+static int sifive_clint_get_count(struct udevice *dev, u64 *count)
 {
-	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	*count = readq((void __iomem *)MTIME_REG(dev->priv));
 
 	return 0;
 }
 
-int riscv_get_ipi(int hart, int *pending)
+static const struct timer_ops sifive_clint_ops = {
+	.get_count = sifive_clint_get_count,
+};
+
+static int sifive_clint_probe(struct udevice *dev)
 {
-	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+	dev->priv = dev_read_addr_ptr(dev);
+	if (!dev->priv)
+		return -EINVAL;
 
-	return 0;
+	return timer_timebase_fallback(dev);
 }
 
 static const struct udevice_id sifive_clint_ids[] = {
-	{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
+	{ .compatible = "riscv,clint0" },
 	{ }
 };
 
 U_BOOT_DRIVER(sifive_clint) = {
 	.name		= "sifive_clint",
-	.id		= UCLASS_SYSCON,
+	.id		= UCLASS_TIMER,
 	.of_match	= sifive_clint_ids,
+	.probe		= sifive_clint_probe,
+	.ops		= &sifive_clint_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
 };

diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ac22136..8f33ce1 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c

@@ -54,6 +54,14 @@
 		gd->arch.ipi[reg].arg0 = ipi->arg0;
 		gd->arch.ipi[reg].arg1 = ipi->arg1;
 
+		/*
+		 * Ensure valid only becomes set when the IPI parameters are
+		 * set. An IPI may already be pending on other harts, so we
+		 * need a way to signal that the IPI device has been
+		 * initialized, and that it is ok to call the function.
+		 */
+		__smp_store_release(&gd->arch.ipi[reg].valid, 1);
+
 		ret = riscv_send_ipi(reg);
 		if (ret) {
 			pr_err("Cannot send IPI to hart %d\n", reg);
@@ -81,7 +89,13 @@
 	if (hart >= CONFIG_NR_CPUS)
 		return;
 
-	__smp_mb();
+	/*
+	 * If valid is not set, then U-Boot has not requested the IPI. The
+	 * IPI device may not be initialized, so all we can do is wait for
+	 * U-Boot to initialize it and send an IPI
+	 */
+	if (!__smp_load_acquire(&gd->arch.ipi[hart].valid))
+		return;
 
 	smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
 	invalidate_icache_all();

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9f45c48..e6da47d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts

@@ -121,6 +121,9 @@
 			<&gpio_c 5 GPIO_IN>,
 			<&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
 			<&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
+		test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
+		test5-gpios = <&gpio_a 19>;
+
 		int-value = <1234>;
 		uint-value = <(-1234)>;
 		int64-value = /bits/ 64 <0x1111222233334444>;
@@ -270,6 +273,13 @@
 		compatible = "denx,u-boot-devres-test";
 	};
 
+	another-test {
+		reg = <0 2>;
+		compatible = "denx,u-boot-fdt-test";
+		test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
+		test5-gpios = <&gpio_a 19>;
+	};
+
 	acpi_test1: acpi-test {
 		compatible = "denx,u-boot-acpi-test";
 		acpi-ssdt-test-data = "ab";
@@ -356,6 +366,37 @@
 		sandbox_firmware: sandbox-firmware {
 			compatible = "sandbox,firmware";
 		};
+
+		sandbox-scmi-agent@0 {
+			compatible = "sandbox,scmi-agent";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clk_scmi0: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			reset_scmi0: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+
+		sandbox-scmi-agent@1 {
+			compatible = "sandbox,scmi-agent";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clk_scmi1: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			protocol@10 {
+				reg = <0x10>;
+			};
+		};
 	};
 
 	pinctrl-gpio {
@@ -533,7 +574,9 @@
 	};
 
 	cpus {
+		timebase-frequency = <2000000>;
 		cpu-test1 {
+			timebase-frequency = <3000000>;
 			compatible = "sandbox,cpu_sandbox";
 			u-boot,dm-pre-reloc;
 		};
@@ -839,11 +882,16 @@
 			0x58 8>;
 	};
 
-	timer {
+	timer@0 {
 		compatible = "sandbox,timer";
 		clock-frequency = <1000000>;
 	};
 
+	timer@1 {
+		compatible = "sandbox,timer";
+		sandbox,timebase-frequency-fallback;
+	};
+
 	tpm2 {
 		compatible = "sandbox,tpm2";
 	};
@@ -1036,6 +1084,12 @@
 		compatible = "sandbox,virtio2";
 	};
 
+	sandbox_scmi {
+		compatible = "sandbox,scmi-devices";
+		clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
+		resets = <&reset_scmi0 3>;
+	};
+
 	pinctrl {
 		compatible = "sandbox,pinctrl";
 
@@ -1122,6 +1176,19 @@
 		resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
 		reset-names = "valid", "no_mask", "out_of_range";
 	};
+
+	some_regmapped-bus {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+
+		ranges = <0x0 0x0 0x10>;
+		compatible = "simple-bus";
+
+		regmap-test_0 {
+			reg = <0 0x10>;
+			compatible = "sandbox,regmap_test";
+		};
+	};
 };
 
 #include "sandbox_pmic.dtsi"

diff --git a/arch/sandbox/include/asm/cpu.h b/arch/sandbox/include/asm/cpu.h
new file mode 100644
index 0000000..c97ac7b
--- /dev/null
+++ b/arch/sandbox/include/asm/cpu.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#ifndef __SANDBOX_CPU_H
+#define __SANDBOX_CPU_H
+
+void cpu_sandbox_set_current(const char *name);
+
+#endif /* __SANDBOX_CPU_H */

diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
index c4205ea..40d3e61 100644
--- a/arch/sandbox/include/asm/reset.h
+++ b/arch/sandbox/include/asm/reset.h

@@ -11,9 +11,12 @@
 struct udevice;
 
 int sandbox_reset_query(struct udevice *dev, unsigned long id);
+int sandbox_reset_is_requested(struct udevice *dev, unsigned long id);
 
 int sandbox_reset_test_get(struct udevice *dev);
+int sandbox_reset_test_get_devm(struct udevice *dev);
 int sandbox_reset_test_get_bulk(struct udevice *dev);
+int sandbox_reset_test_get_bulk_devm(struct udevice *dev);
 int sandbox_reset_test_assert(struct udevice *dev);
 int sandbox_reset_test_assert_bulk(struct udevice *dev);
 int sandbox_reset_test_deassert(struct udevice *dev);

diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h
new file mode 100644
index 0000000..3e8b006
--- /dev/null
+++ b/arch/sandbox/include/asm/scmi_test.h

@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020, Linaro Limited
+ */
+
+#ifndef __SANDBOX_SCMI_TEST_H
+#define __SANDBOX_SCMI_TEST_H
+
+struct udevice;
+struct sandbox_scmi_agent;
+struct sandbox_scmi_service;
+
+/**
+ * struct sandbox_scmi_clk - Simulated clock exposed by SCMI
+ * @id:		Identifier of the clock used in the SCMI protocol
+ * @enabled:	Clock state: true if enabled, false if disabled
+ * @rate:	Clock rate in Hertz
+ */
+struct sandbox_scmi_clk {
+	uint id;
+	bool enabled;
+	ulong rate;
+};
+
+/**
+ * struct sandbox_scmi_reset - Simulated reset controller exposed by SCMI
+ * @asserted:	Reset control state: true if asserted, false if desasserted
+ */
+struct sandbox_scmi_reset {
+	uint id;
+	bool asserted;
+};
+
+/**
+ * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent
+ * @idx:	Identifier for the SCMI agent, its index
+ * @clk:	Simulated clocks
+ * @clk_count:	Simulated clocks array size
+ * @clk:	Simulated reset domains
+ * @clk_count:	Simulated reset domains array size
+ */
+struct sandbox_scmi_agent {
+	uint idx;
+	struct sandbox_scmi_clk *clk;
+	size_t clk_count;
+	struct sandbox_scmi_reset *reset;
+	size_t reset_count;
+};
+
+/**
+ * struct sandbox_scmi_service - Reference to simutaed SCMI agents/services
+ * @agent:		Pointer to SCMI sandbox agent pointers array
+ * @agent_count:	Number of emulated agents exposed in array @agent.
+ */
+struct sandbox_scmi_service {
+	struct sandbox_scmi_agent **agent;
+	size_t agent_count;
+};
+
+/**
+ * struct sandbox_scmi_devices - Reference to devices probed through SCMI
+ * @clk:		Array the clock devices
+ * @clk_count:		Number of clock devices probed
+ * @reset:		Array the reset controller devices
+ * @reset_count:	Number of reset controller devices probed
+ */
+struct sandbox_scmi_devices {
+	struct clk *clk;
+	size_t clk_count;
+	struct reset_ctl *reset;
+	size_t reset_count;
+};
+
+#ifdef CONFIG_SCMI_FIRMWARE
+/**
+ * sandbox_scmi_service_context - Get the simulated SCMI services context
+ * @return:	Reference to backend simulated resources state
+ */
+struct sandbox_scmi_service *sandbox_scmi_service_ctx(void);
+
+/**
+ * sandbox_scmi_devices_get_ref - Get references to devices accessed through SCMI
+ * @dev:	Reference to the test device used get test resources
+ * @return:	Reference to the devices probed by the SCMI test
+ */
+struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev);
+#else
+static inline struct sandbox_scmi_service *sandbox_scmi_service_ctx(void)
+{
+	return NULL;
+}
+
+static inline
+struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev)
+{
+	return NULL;
+}
+#endif /* CONFIG_SCMI_FIRMWARE */
+#endif /* __SANDBOX_SCMI_TEST_H */

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 76276c6..eddf2a7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig

@@ -788,6 +788,13 @@
 	  by the operating system. It defines platform-independent interfaces
 	  for configuration and power management monitoring.
 
+config ACPI_GNVS_EXTERNAL
+	bool
+	help
+	  Put the GNVS (Global Non-Volatile Sleeping) table separate from the
+	  DSDT and add a pointer to the table from the DSDT. This allows
+	  U-Boot to better control the address of the GNVS.
+
 endmenu
 
 config HAVE_ACPI_RESUME
@@ -976,4 +983,44 @@
 
 	  See https://queue.acm.org/blogposting.cfm?id=18977 for more info
 
+config SA_PCIEX_LENGTH
+	hex
+	default 0x10000000 if (PCIEX_LENGTH_256MB)
+	default 0x8000000 if (PCIEX_LENGTH_128MB)
+	default 0x4000000 if (PCIEX_LENGTH_64MB)
+	default 0x10000000
+	help
+	  This option allows you to select length of PCIEX region.
+
+config PCIEX_LENGTH_256MB
+	bool
+
+config PCIEX_LENGTH_128MB
+	bool
+
+config PCIEX_LENGTH_64MB
+	bool
+
+config INTEL_GMA_ACPI
+	bool "Generate ACPI table for Intel GMA graphics"
+	help
+	  The Intel GMA graphics driver in Linux expects an ACPI table
+	  which describes the layout of the registers and the display
+	  connected to the device. Enable this option to create this
+	  table so that graphics works correctly.
+
+config INTEL_GENERIC_WIFI
+	bool "Enable generation of ACPI tables for Intel WiFi"
+	help
+	  Select this option to provide code to a build generic WiFi ACPI table
+	  for Intel WiFi devices. This is not a WiFi driver and offers no
+	  network functionality. It is only here to generate the ACPI tables
+	  required by Linux.
+
+config INTEL_GMA_SWSMISCI
+	bool
+	help
+	  Select this option for Atom-based platforms which use the SWSMISCI
+	  register (0xe0) rather than the SWSCI register (0xe8).
+
 endmenu

diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 99d4e10..35a425c 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig

@@ -13,9 +13,12 @@
 	select TPL_X86_TSC_TIMER_NATIVE
 	select SPL_PCH_SUPPORT
 	select TPL_PCH_SUPPORT
+	select PCIEX_LENGTH_256MB
 	select PCH_SUPPORT
 	select P2SB
 	select SMP_AP_WORK
+	select INTEL_GMA_SWSMISCI
+	select ACPI_GNVS_EXTERNAL
 	imply ENABLE_MRC_CACHE
 	imply AHCI_PCI
 	imply SCSI
@@ -46,6 +49,7 @@
 	imply CMD_CLK
 	imply CLK_INTEL
 	imply ACPI_GPE
+	imply INTEL_GMA_ACPI
 
 if INTEL_APOLLOLAKE
 

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3aa2a55..2ddf4af 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile

@@ -16,6 +16,7 @@
 endif
 endif
 ifndef CONFIG_SPL_BUILD
+obj-y += acpi.o
 obj-y += fsp_s.o
 endif
 

diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
new file mode 100644
index 0000000..69b544f
--- /dev/null
+++ b/arch/x86/cpu/apollolake/acpi.c

@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2017-2019 Siemens AG
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot apollolake/acpi.c
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <log.h>
+#include <p2sb.h>
+#include <pci.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_s3.h>
+#include <asm/acpi_table.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_acpi.h>
+#include <asm/intel_gnvs.h>
+#include <asm/intel_pinctrl.h>
+#include <asm/intel_pinctrl_defs.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/systemagent.h>
+#include <dm/acpi.h>
+#include <dm/uclass-internal.h>
+#include <power/acpi_pmc.h>
+
+int arch_read_sci_irq_select(void)
+{
+	struct acpi_pmc_upriv *upriv;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev);
+	if (ret)
+		return log_msg_ret("pmc", ret);
+	upriv = dev_get_uclass_priv(dev);
+
+	return readl(upriv->pmc_bar0 + IRQ_REG);
+}
+
+int arch_write_sci_irq_select(uint scis)
+{
+	struct acpi_pmc_upriv *upriv;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev);
+	if (ret)
+		return log_msg_ret("pmc", ret);
+	upriv = dev_get_uclass_priv(dev);
+	writel(scis, upriv->pmc_bar0 + IRQ_REG);
+
+	return 0;
+}
+
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+	struct udevice *cpu;
+	int ret;
+
+	/* Clear out GNV */
+	memset(gnvs, '\0', sizeof(*gnvs));
+
+	/* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */
+
+#ifdef CONFIG_CHROMEOS
+	/* Initialise Verified Boot data */
+	chromeos_init_acpi(&gnvs->chromeos);
+	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+	/* Set unknown wake source */
+	gnvs->pm1i = ~0ULL;
+
+	/* CPU core count */
+	gnvs->pcnt = 1;
+	ret = uclass_find_first_device(UCLASS_CPU, &cpu);
+	if (cpu) {
+		ret = cpu_get_count(cpu);
+		if (ret > 0)
+			gnvs->pcnt = ret;
+	}
+
+	return 0;
+}
+
+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en)
+{
+	/*
+	 * WAK_STS bit is set when the system is in one of the sleep states
+	 * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
+	 * this bit, the PMC will transition the system to the ON state and
+	 * can only be set by hardware and can only be cleared by writing a one
+	 * to this bit position.
+	 */
+	generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
+
+	return generic_pm1_en;
+}
+
+int arch_madt_sci_irq_polarity(int sci)
+{
+	return MP_IRQ_POLARITY_LOW;
+}
+
+void fill_fadt(struct acpi_fadt *fadt)
+{
+	fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
+
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+
+	fadt->pm_tmr_len = 4;
+	fadt->duty_width = 3;
+
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
+}
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &fadt->header;
+
+	acpi_fadt_common(fadt, facs, dsdt);
+	intel_acpi_fill_fadt(fadt);
+	fill_fadt(fadt);
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
+{
+	struct udevice *dev, *sa_dev;
+	u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK;
+	u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK;
+	bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED;
+	bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED;
+	void *tmp;
+	int ret;
+
+	uclass_find_first_device(UCLASS_VIDEO, &dev);
+	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa_dev);
+	if (ret)
+		return log_msg_ret("no sa", ret);
+
+	/* IGD has to be enabled, GFXVTBAR set and enabled */
+	if (dev && device_active(dev) && gfxvtbar && gfxvten) {
+		tmp = ctx->current;
+
+		acpi_create_dmar_drhd(ctx, 0, 0, gfxvtbar);
+		ret = acpi_create_dmar_ds_pci(ctx, PCI_BDF(0, 2, 0));
+		if (ret)
+			return log_msg_ret("ds_pci", ret);
+		acpi_dmar_drhd_fixup(ctx, tmp);
+
+		/* Add RMRR entry */
+		tmp = ctx->current;
+		acpi_create_dmar_rmrr(ctx->current, 0, sa_get_gsm_base(sa_dev),
+				      sa_get_tolud_base(sa_dev) - 1);
+		acpi_create_dmar_ds_pci(ctx->current, PCI_BDF(0, 2, 0));
+		acpi_dmar_rmrr_fixup(ctx, tmp);
+	}
+
+	/* DEFVTBAR has to be set and enabled */
+	if (defvtbar && defvten) {
+		struct udevice *p2sb_dev;
+		u16 ibdf, hbdf;
+		uint ioapic, hpet;
+		int ret;
+
+		tmp = ctx->current;
+		/*
+		 * P2SB may already be hidden. There's no clear rule, when.
+		 * It is needed to get bus, device and function for IOAPIC and
+		 * HPET device which is stored in P2SB device. So unhide it to
+		 * get the info and hide it again when done.
+		 *
+		 * TODO(sjg@chromium.org): p2sb_unhide() ?
+		 */
+		ret = uclass_first_device_err(UCLASS_P2SB, &p2sb_dev);
+		if (ret)
+			return log_msg_ret("p2sb", ret);
+
+		dm_pci_read_config16(p2sb_dev, PCH_P2SB_IBDF, &ibdf);
+		ioapic = PCI_TO_BDF(ibdf);
+		dm_pci_read_config16(p2sb_dev, PCH_P2SB_HBDF, &hbdf);
+		hpet = PCI_TO_BDF(hbdf);
+		/* TODO(sjg@chromium.org): p2sb_hide() ? */
+
+		acpi_create_dmar_drhd(ctx, DRHD_INCLUDE_PCI_ALL, 0, defvtbar);
+		acpi_create_dmar_ds_ioapic(ctx, 2, ioapic);
+		acpi_create_dmar_ds_msi_hpet(ctx, 0, hpet);
+		acpi_dmar_drhd_fixup(tmp, ctx->current);
+	}
+
+	return 0;
+}

diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index 0a6d2ad..8da2e64 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c

@@ -6,14 +6,90 @@
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_table.h>
 #include <asm/cpu_common.h>
 #include <asm/cpu_x86.h>
+#include <asm/intel_acpi.h>
+#include <asm/msr.h>
+#include <dm/acpi.h>
+
+#define CSTATE_RES(address_space, width, offset, address)		\
+	{								\
+	.space_id = address_space,					\
+	.bit_width = width,						\
+	.bit_offset = offset,						\
+	.addrl = address,						\
+	}
+
+static struct acpi_cstate cstate_map[] = {
+	{
+		/* C1 */
+		.ctype = 1,		/* ACPI C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+		},
+	}, {
+		.ctype = 2,		/* ACPI C2 */
+		.latency = 50,
+		.power = 10,
+		.resource = {
+			.space_id = ACPI_ADDRESS_SPACE_IO,
+			.bit_width = 8,
+			.addrl = 0x415,
+		},
+	}, {
+		.ctype = 3,		/* ACPI C3 */
+		.latency = 150,
+		.power = 10,
+		.resource = {
+			.space_id = ACPI_ADDRESS_SPACE_IO,
+			.bit_width = 8,
+			.addrl = 0x419,
+		},
+	},
+};
 
 static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
 {
 	return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
 }
 
+static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+	uint core_id = dev->req_seq;
+	int cores_per_package;
+	int ret;
+
+	cores_per_package = cpu_get_cores_per_package();
+	ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
+				       ARRAY_SIZE(cstate_map));
+
+	/* Generate P-state tables */
+	generate_p_state_entries(ctx, core_id, cores_per_package);
+
+	/* Generate T-state tables */
+	generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
+
+	acpigen_pop_len(ctx);
+
+	if (device_is_last_sibling(dev)) {
+		ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+struct acpi_ops apl_cpu_acpi_ops = {
+	.fill_ssdt	= acpi_cpu_fill_ssdt,
+};
+
 static const struct cpu_ops cpu_x86_apl_ops = {
 	.get_desc	= cpu_x86_get_desc,
 	.get_info	= apl_get_info,
@@ -32,5 +108,6 @@
 	.of_match	= cpu_x86_apl_ids,
 	.bind		= cpu_x86_bind,
 	.ops		= &cpu_x86_apl_ops,
+	ACPI_OPS_PTR(&apl_cpu_acpi_ops)
 	.flags		= DM_FLAG_PRE_RELOC,
 };

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index e54b0ac..715ceab 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c

@@ -157,6 +157,8 @@
 	struct udevice *itss;
 	int ret;
 
+	if (!ll_boot_init())
+		return 0;
 	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
 	if (ret)
 		return log_msg_ret("no itss", ret);

diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c
index cb46ec6..7fd67dc 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c

@@ -1,17 +1,45 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2019 Google LLC
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * Copyright (C) 2017 - 2019 Siemens AG
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * Portions from coreboot soc/intel/apollolake/chip.c
  */
 
+#define LOG_CATEGORY UCLASS_NORTHBRIDGE
+
 #include <common.h>
 #include <dm.h>
 #include <dt-structs.h>
 #include <log.h>
 #include <spl.h>
+#include <tables_csum.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_nhlt.h>
 #include <asm/intel_pinctrl.h>
 #include <asm/intel_regs.h>
+#include <asm/io.h>
 #include <asm/pci.h>
+#include <asm/arch/acpi.h>
 #include <asm/arch/systemagent.h>
+#include <dt-bindings/sound/nhlt.h>
+#include <dm/acpi.h>
+
+enum {
+	PCIEXBAR		= 0x60,
+	PCIEXBAR_LENGTH_256MB	= 0,
+	PCIEXBAR_LENGTH_128MB,
+	PCIEXBAR_LENGTH_64MB,
+
+	PCIEXBAR_PCIEXBAREN	= 1 << 0,
+
+	BGSM			= 0xb4,  /* Base GTT Stolen Memory */
+	TSEG			= 0xb8,  /* TSEG base */
+	TOLUD			= 0xbc,
+};
 
 /**
  * struct apl_hostbridge_platdata - platform data for hostbridge
@@ -32,17 +60,102 @@
 	pci_dev_t bdf;
 };
 
-enum {
-	PCIEXBAR		= 0x60,
-	PCIEXBAR_LENGTH_256MB	= 0,
-	PCIEXBAR_LENGTH_128MB,
-	PCIEXBAR_LENGTH_64MB,
+static const struct nhlt_format_config dmic_1ch_formats[] = {
+	/* 48 KHz 16-bits per sample. */
+	{
+		.num_channels = 1,
+		.sample_freq_khz = 48,
+		.container_bits_per_sample = 16,
+		.valid_bits_per_sample = 16,
+		.settings_file = "dmic-1ch-48khz-16b.dat",
+	},
+};
 
-	PCIEXBAR_PCIEXBAREN	= 1 << 0,
+static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {
+	.tdm_config = {
+		.config_type = NHLT_TDM_MIC_ARRAY,
+	},
+	.array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,
+};
 
-	TSEG			= 0xb8,  /* TSEG base */
+static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {
+	{
+		.link = NHLT_LINK_PDM,
+		.device = NHLT_PDM_DEV,
+		.direction = NHLT_DIR_CAPTURE,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_DMIC,
+		.cfg = &dmic_1ch_mic_config,
+		.cfg_size = sizeof(dmic_1ch_mic_config),
+		.formats = dmic_1ch_formats,
+		.num_formats = ARRAY_SIZE(dmic_1ch_formats),
+	},
+};
+
+static const struct nhlt_format_config dmic_2ch_formats[] = {
+	/* 48 KHz 16-bits per sample. */
+	{
+		.num_channels = 2,
+		.sample_freq_khz = 48,
+		.container_bits_per_sample = 16,
+		.valid_bits_per_sample = 16,
+		.settings_file = "dmic-2ch-48khz-16b.dat",
+	},
+};
+
+static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {
+	.tdm_config = {
+		.config_type = NHLT_TDM_MIC_ARRAY,
+	},
+	.array_type = NHLT_MIC_ARRAY_2CH_SMALL,
+};
+
+static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {
+	{
+		.link = NHLT_LINK_PDM,
+		.device = NHLT_PDM_DEV,
+		.direction = NHLT_DIR_CAPTURE,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_DMIC,
+		.cfg = &dmic_2ch_mic_config,
+		.cfg_size = sizeof(dmic_2ch_mic_config),
+		.formats = dmic_2ch_formats,
+		.num_formats = ARRAY_SIZE(dmic_2ch_formats),
+	},
+};
+
+static const struct nhlt_format_config dmic_4ch_formats[] = {
+	/* 48 KHz 16-bits per sample. */
+	{
+		.num_channels = 4,
+		.sample_freq_khz = 48,
+		.container_bits_per_sample = 16,
+		.valid_bits_per_sample = 16,
+		.settings_file = "dmic-4ch-48khz-16b.dat",
+	},
 };
 
+static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {
+	.tdm_config = {
+		.config_type = NHLT_TDM_MIC_ARRAY,
+	},
+	.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED,
+};
+
+static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
+	{
+		.link = NHLT_LINK_PDM,
+		.device = NHLT_PDM_DEV,
+		.direction = NHLT_DIR_CAPTURE,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_DMIC,
+		.cfg = &dmic_4ch_mic_config,
+		.cfg_size = sizeof(dmic_4ch_mic_config),
+		.formats = dmic_4ch_formats,
+		.num_formats = ARRAY_SIZE(dmic_4ch_formats),
+	},
+};
+
 static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
 {
 	struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
@@ -165,6 +278,119 @@
 	return 0;
 }
 
+static int apl_acpi_hb_get_name(const struct udevice *dev, char *out_name)
+{
+	return acpi_copy_name(out_name, "RHUB");
+}
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static int apl_acpi_hb_write_tables(const struct udevice *dev,
+				    struct acpi_ctx *ctx)
+{
+	struct acpi_table_header *header;
+	struct acpi_dmar *dmar;
+	u32 val;
+
+	/*
+	 * Create DMAR table only if virtualization is enabled. Due to some
+	 * constraints on Apollo Lake SoC (some stepping affected), VTD could
+	 * not be enabled together with IPU. Doing so will override and disable
+	 * VTD while leaving CAPID0_A still reporting that VTD is available.
+	 * As in this case FSP will lock VTD to disabled state, we need to make
+	 * sure that DMAR table generation only happens when at least DEFVTBAR
+	 * is enabled. Otherwise the DMAR header will be generated while the
+	 * content of the table will be missing.
+	 */
+	dm_pci_read_config32(dev, CAPID0_A, &val);
+	if ((val & VTD_DISABLE) ||
+	    !(readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED))
+		return 0;
+
+	log_debug("ACPI:    * DMAR\n");
+	dmar = (struct acpi_dmar *)ctx->current;
+	header = &dmar->header;
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP);
+	ctx->current += sizeof(struct acpi_dmar);
+	apl_acpi_fill_dmar(ctx);
+
+	/* (Re)calculate length and checksum */
+	header->length = ctx->current - (void *)dmar;
+	header->checksum = table_compute_checksum((void *)dmar, header->length);
+
+	acpi_align(ctx);
+	acpi_add_table(ctx, dmar);
+
+	return 0;
+}
+#endif
+
+static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+	struct nhlt *nhlt = ctx->nhlt;
+	u32 channels;
+	ofnode node;
+
+	node = ofnode_find_subnode(dev_ofnode(dev), "nhlt");
+	if (ofnode_read_u32(node, "intel,dmic-channels", &channels))
+		return log_msg_ret("channels", -EINVAL);
+	switch (channels) {
+	case 1:
+		return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,
+					  ARRAY_SIZE(dmic_1ch_descriptors));
+	case 2:
+		return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,
+					  ARRAY_SIZE(dmic_2ch_descriptors));
+	case 4:
+		return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors,
+					  ARRAY_SIZE(dmic_4ch_descriptors));
+	}
+
+	return log_msg_ret("channels", -EINVAL);
+}
+
+static int apl_hostbridge_remove(struct udevice *dev)
+{
+	/*
+	 * TODO(sjg@chromium.org): Consider adding code from coreboot's
+	 * platform_fsp_notify_status()
+	 */
+
+	return 0;
+}
+
+static ulong sa_read_reg(struct udevice *dev, int reg)
+{
+	u32 val;
+
+	/* All regions concerned for have 1 MiB alignment */
+	dm_pci_read_config32(dev, BGSM, &val);
+
+	return ALIGN_DOWN(val, 1 << 20);
+}
+
+ulong sa_get_tolud_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, TOLUD);
+}
+
+ulong sa_get_gsm_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, BGSM);
+}
+
+ulong sa_get_tseg_base(struct udevice *dev)
+{
+	return sa_read_reg(dev, TSEG);
+}
+
+struct acpi_ops apl_hostbridge_acpi_ops = {
+	.get_name	= apl_acpi_hb_get_name,
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+	.write_tables	= apl_acpi_hb_write_tables,
+#endif
+	.setup_nhlt	= apl_acpi_setup_nhlt,
+};
+
 static const struct udevice_id apl_hostbridge_ids[] = {
 	{ .compatible = "intel,apl-hostbridge" },
 	{ }
@@ -176,5 +402,8 @@
 	.of_match	= apl_hostbridge_ids,
 	.ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
 	.probe		= apl_hostbridge_probe,
+	.remove		= apl_hostbridge_remove,
 	.platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
+	ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
+	.flags		= DM_FLAG_OS_PREPARE,
 };

diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
index b81a458..a29832c 100644
--- a/arch/x86/cpu/apollolake/lpc.c
+++ b/arch/x86/cpu/apollolake/lpc.c

@@ -9,10 +9,14 @@
 #include <dm.h>
 #include <log.h>
 #include <spl.h>
+#include <acpi/acpi_table.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_acpi.h>
 #include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/iomap.h>
 #include <asm/arch/lpc.h>
+#include <dm/acpi.h>
 #include <linux/log2.h>
 
 void lpc_enable_fixed_io_ranges(uint io_enables)
@@ -110,6 +114,19 @@
 	lpc_enable_fixed_io_ranges(com_enable);
 }
 
+static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name)
+{
+	return acpi_copy_name(out_name, "LPCB");
+}
+
+struct acpi_ops apl_lpc_acpi_ops = {
+	.get_name	= apl_acpi_lpc_get_name,
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+	.write_tables	= intel_southbridge_write_acpi_tables,
+#endif
+	.inject_dsdt	= southbridge_inject_dsdt,
+};
+
 static const struct udevice_id apl_lpc_ids[] = {
 	{ .compatible = "intel,apl-lpc" },
 	{ }
@@ -120,4 +137,5 @@
 	.name		= "intel_apl_lpc",
 	.id		= UCLASS_LPC,
 	.of_match	= apl_lpc_ids,
+	ACPI_OPS_PTR(&apl_lpc_acpi_ops)
 };

diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index 192dec7..576d018 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c

@@ -118,7 +118,8 @@
 	int size;
 	int ret;
 
-	ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+	ret = dev_read_u32_array(dev, "early-regs", base,
+				 ARRAY_SIZE(base));
 	if (ret)
 		return log_msg_ret("Missing/short early-regs", ret);
 	if (spl_phase() == PHASE_TPL) {
@@ -133,11 +134,6 @@
 	}
 	upriv->acpi_base = base[4];
 
-	/* Since PCI is not enabled, we must get the BDF manually */
-	plat->bdf = pci_get_devfn(dev);
-	if (plat->bdf < 0)
-		return log_msg_ret("Cannot get PMC PCI address", plat->bdf);
-
 	/* Get the dwX values for pmc gpe settings */
 	size = dev_read_size(dev, "gpe0-dw");
 	if (size < 0)

diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c
index 6567d50..4d4cdaf 100644
--- a/arch/x86/cpu/broadwell/cpu_from_spl.c
+++ b/arch/x86/cpu/broadwell/cpu_from_spl.c

@@ -53,14 +53,12 @@
 
 int dram_init_banksize(void)
 {
-#ifdef CONFIG_NR_DRAM_BANKS
 	struct spl_handoff *ho;
 
 	ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
 	if (!ho)
 		return log_msg_ret("Missing SPL hand-off info", -ENOENT);
 	handoff_load_dram_banks(ho);
-#endif
 
 	return 0;
 }

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 69c1418..f869275 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c

@@ -189,6 +189,14 @@
 {
 }
 
+/*
+ * Implement a weak default function for boards that need to do some final
+ * processing before booting the OS.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	struct acpi_fadt __maybe_unused *fadt;
@@ -218,6 +226,13 @@
 		}
 	}
 
+	/*
+	 * TODO(sjg@chromium.org): Move this to bootm_announce_and_cleanup()
+	 * once APL FSP-S at 0x200000 does not overlap with the bzimage at
+	 * 0x100000.
+	 */
+	board_final_cleanup();
+
 	return 0;
 }
 #endif

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 8f342dd..7517b75 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c

@@ -34,6 +34,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CPUID_FEATURE_PAE	BIT(6)
+#define CPUID_FEATURE_PSE36	BIT(17)
+#define CPUID_FEAURE_HTT	BIT(28)
+
 /*
  * Constructor for a conventional segment GDT (or LDT) entry
  * This is a macro so it can be used in initialisers
@@ -388,6 +392,25 @@
 	}
 }
 
+static uint cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+	if (!has_cpuid())
+		return 32;
+
+	if (cpu_cpuid_extended_level() >= 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+
+	return 32;
+}
+
 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
 static void setup_pci_ram_top(void)
 {

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 374803b..4a5cf17 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile

@@ -2,6 +2,8 @@
 #
 # Copyright (c) 2016 Google, Inc
 
+obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o
+
 ifdef CONFIG_HAVE_MRC
 obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
@@ -9,6 +11,10 @@
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
 endif
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
+endif
+
 ifdef CONFIG_INTEL_CAR_CQOS
 obj-$(CONFIG_TPL_BUILD) += car2.o
 ifndef CONFIG_SPL_BUILD
@@ -20,6 +26,7 @@
 obj-y += fast_spi.o
 obj-y += lpc.o
 obj-y += lpss.o
+obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o
 ifndef CONFIG_TARGET_EFI_APP
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
 ifndef CONFIG_$(SPL_)X86_64

diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
new file mode 100644
index 0000000..a4d5fbd3
--- /dev/null
+++ b/arch/x86/cpu/intel_common/acpi.c

@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic Intel ACPI table generation
+ *
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot src/soc/intel/common/block/acpi.c
+ */
+
+#include <common.h>
+#include <bloblist.h>
+#include <cpu.h>
+#include <dm.h>
+#include <acpi/acpigen.h>
+#include <asm/acpigen.h>
+#include <asm/acpi_table.h>
+#include <asm/cpu.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_acpi.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/smm.h>
+#include <asm/turbo.h>
+#include <asm/intel_gnvs.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/systemagent.h>
+#include <dm/acpi.h>
+#include <linux/err.h>
+#include <power/acpi_pmc.h>
+
+u32 acpi_fill_mcfg(u32 current)
+{
+	/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+	current += acpi_create_mcfg_mmconfig((void *)current,
+					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+					     (CONFIG_SA_PCIEX_LENGTH >> 20)
+					     - 1);
+	return current;
+}
+
+static int acpi_sci_irq(void)
+{
+	int sci_irq = 9;
+	uint scis;
+	int ret;
+
+	ret = arch_read_sci_irq_select();
+	if (IS_ERR_VALUE(ret))
+		return log_msg_ret("sci_irq", ret);
+	scis = ret;
+	scis &= SCI_IRQ_MASK;
+	scis >>= SCI_IRQ_SHIFT;
+
+	/* Determine how SCI is routed. */
+	switch (scis) {
+	case SCIS_IRQ9:
+	case SCIS_IRQ10:
+	case SCIS_IRQ11:
+		sci_irq = scis - SCIS_IRQ9 + 9;
+		break;
+	case SCIS_IRQ20:
+	case SCIS_IRQ21:
+	case SCIS_IRQ22:
+	case SCIS_IRQ23:
+		sci_irq = scis - SCIS_IRQ20 + 20;
+		break;
+	default:
+		log_warning("Invalid SCI route! Defaulting to IRQ9\n");
+		sci_irq = 9;
+		break;
+	}
+
+	log_debug("SCI is IRQ%d\n", sci_irq);
+
+	return sci_irq;
+}
+
+static unsigned long acpi_madt_irq_overrides(unsigned long current)
+{
+	int sci = acpi_sci_irq();
+	u16 flags = MP_IRQ_TRIGGER_LEVEL;
+
+	if (sci < 0)
+		return log_msg_ret("sci irq", sci);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
+
+	flags |= arch_madt_sci_irq_polarity(sci);
+
+	/* SCI */
+	current +=
+	    acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
+
+	return current;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	/* Local APICs */
+	current += acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
+
+	return acpi_madt_irq_overrides(current);
+}
+
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+	const u16 pmbase = IOMAP_ACPI_BASE;
+
+	/* Use ACPI 3.0 revision. */
+	fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT);
+
+	fadt->sci_int = acpi_sci_irq();
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0;
+
+	fadt->pm1a_evt_blk = pmbase + PM1_STS;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
+	fadt->pm1b_cnt_blk = 0x0;
+
+	fadt->gpe0_blk = pmbase + GPE0_STS;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+
+	/* GPE0 STS/EN pairs each 32 bits wide. */
+	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
+
+	fadt->flush_size = 0x400;	/* twice of cache size */
+	fadt->flush_stride = 0x10;	/* Cache line width  */
+	fadt->duty_offset = 1;
+	fadt->day_alrm = 0xd;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	    ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+	    ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+	    ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_value = RST_CPU | SYS_RST;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+
+	fadt->x_gpe1_blk.space_id = 1;
+}
+
+int intel_southbridge_write_acpi_tables(const struct udevice *dev,
+					struct acpi_ctx *ctx)
+{
+	int ret;
+
+	ret = acpi_write_dbg2_pci_uart(ctx, gd->cur_serial_dev,
+				       ACPI_ACCESS_SIZE_DWORD_ACCESS);
+	if (ret)
+		return log_msg_ret("dbg2", ret);
+
+	ret = acpi_write_hpet(ctx);
+	if (ret)
+		return log_msg_ret("hpet", ret);
+
+	return 0;
+}
+
+__weak u32 acpi_fill_soc_wake(u32 generic_pm1_en,
+			      const struct chipset_power_state *ps)
+{
+	return generic_pm1_en;
+}
+
+__weak int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+	return 0;
+}
+
+int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+	struct acpi_global_nvs *gnvs;
+	int ret;
+
+	ret = bloblist_ensure_size(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs),
+				   (void **)&gnvs);
+	if (ret)
+		return log_msg_ret("bloblist", ret);
+	memset(gnvs, '\0', sizeof(*gnvs));
+
+	ret = acpi_create_gnvs(gnvs);
+	if (ret)
+		return log_msg_ret("gnvs", ret);
+
+	/*
+	 * TODO(sjg@chromum.org): tell SMI about it
+	 * smm_setup_structures(gnvs, NULL, NULL);
+	 */
+
+	/* Add it to DSDT */
+	acpigen_write_scope(ctx, "\\");
+	acpigen_write_name_dword(ctx, "NVSA", (uintptr_t)gnvs);
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+	u32 m;
+	u32 power;
+
+	/*
+	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+	 *
+	 * Power = (ratio / p1_ratio) * m * tdp
+	 */
+
+	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+	m = (m * m) / 1000;
+
+	power = ((ratio * 100000 / p1_ratio) / 100);
+	power *= (m / 100) * (tdp / 1000);
+	power /= 1000;
+
+	return power;
+}
+
+void generate_p_state_entries(struct acpi_ctx *ctx, int core,
+			      int cores_per_package)
+{
+	int ratio_min, ratio_max, ratio_turbo, ratio_step;
+	int coord_type, power_max, num_entries;
+	int ratio, power, clock, clock_max;
+	bool turbo;
+
+	coord_type = cpu_get_coord_type();
+	ratio_min = cpu_get_min_ratio();
+	ratio_max = cpu_get_max_ratio();
+	clock_max = (ratio_max * cpu_get_bus_clock_khz()) / 1000;
+	turbo = (turbo_get_state() == TURBO_ENABLED);
+
+	/* Calculate CPU TDP in mW */
+	power_max = cpu_get_power_max();
+
+	/* Write _PCT indicating use of FFixedHW */
+	acpigen_write_empty_pct(ctx);
+
+	/* Write _PPC with no limit on supported P-state */
+	acpigen_write_ppc_nvs(ctx);
+	/* Write PSD indicating configured coordination type */
+	acpigen_write_psd_package(ctx, core, 1, coord_type);
+
+	/* Add P-state entries in _PSS table */
+	acpigen_write_name(ctx, "_PSS");
+
+	/* Determine ratio points */
+	ratio_step = PSS_RATIO_STEP;
+	do {
+		num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
+		if (((ratio_max - ratio_min) % ratio_step) > 0)
+			num_entries += 1;
+		if (turbo)
+			num_entries += 1;
+		if (num_entries > PSS_MAX_ENTRIES)
+			ratio_step += 1;
+	} while (num_entries > PSS_MAX_ENTRIES);
+
+	/* _PSS package count depends on Turbo */
+	acpigen_write_package(ctx, num_entries);
+
+	/* P[T] is Turbo state if enabled */
+	if (turbo) {
+		ratio_turbo = cpu_get_max_turbo_ratio();
+
+		/* Add entry for Turbo ratio */
+		acpigen_write_pss_package(ctx, clock_max + 1,	/* MHz */
+					  power_max,		/* mW */
+					  PSS_LATENCY_TRANSITION,/* lat1 */
+					  PSS_LATENCY_BUSMASTER,/* lat2 */
+					  ratio_turbo << 8,	/* control */
+					  ratio_turbo << 8);	/* status */
+		num_entries -= 1;
+	}
+
+	/* First regular entry is max non-turbo ratio */
+	acpigen_write_pss_package(ctx, clock_max,	/* MHz */
+				  power_max,		/* mW */
+				  PSS_LATENCY_TRANSITION,/* lat1 */
+				  PSS_LATENCY_BUSMASTER,/* lat2 */
+				  ratio_max << 8,	/* control */
+				  ratio_max << 8);	/* status */
+	num_entries -= 1;
+
+	/* Generate the remaining entries */
+	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+	     ratio >= ratio_min; ratio -= ratio_step) {
+		/* Calculate power at this ratio */
+		power = calculate_power(power_max, ratio_max, ratio);
+		clock = (ratio * cpu_get_bus_clock_khz()) / 1000;
+
+		acpigen_write_pss_package(ctx, clock,		/* MHz */
+					  power,		/* mW */
+					  PSS_LATENCY_TRANSITION,/* lat1 */
+					  PSS_LATENCY_BUSMASTER,/* lat2 */
+					  ratio << 8,		/* control */
+					  ratio << 8);		/* status */
+	}
+	/* Fix package length */
+	acpigen_pop_len(ctx);
+}
+
+void generate_t_state_entries(struct acpi_ctx *ctx, int core,
+			      int cores_per_package, struct acpi_tstate *entry,
+			      int nentries)
+{
+	if (!nentries)
+		return;
+
+	/* Indicate SW_ALL coordination for T-states */
+	acpigen_write_tsd_package(ctx, core, cores_per_package, SW_ALL);
+
+	/* Indicate FixedHW so OS will use MSR */
+	acpigen_write_empty_ptc(ctx);
+
+	/* Set NVS controlled T-state limit */
+	acpigen_write_tpc(ctx, "\\TLVL");
+
+	/* Write TSS table for MSR access */
+	acpigen_write_tss_package(ctx, entry, nentries);
+}
+
+int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id,
+			     const struct acpi_cstate *c_state_map,
+			     int num_cstates)
+{
+	bool is_first = !core_id;
+
+	/* Generate processor \_PR.CPUx */
+	acpigen_write_processor(ctx, core_id, is_first ? ACPI_BASE_ADDRESS : 0,
+				is_first ? 6 : 0);
+
+	/* Generate C-state tables */
+	acpigen_write_cst_package(ctx, c_state_map, num_cstates);
+
+	return 0;
+}
+
+int acpi_generate_cpu_package_final(struct acpi_ctx *ctx, int cores_per_package)
+{
+	/*
+	 * PPKG is usually used for thermal management of the first and only
+	 * package
+	 */
+	acpigen_write_processor_package(ctx, "PPKG", 0, cores_per_package);
+
+	/* Add a method to notify processor nodes */
+	acpigen_write_processor_cnot(ctx, cores_per_package);
+
+	return 0;
+}

diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 509730a..39aa0f6 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c

@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <log.h>
+#include <acpi/acpigen.h>
 #include <asm/cpu.h>
 #include <asm/cpu_common.h>
 #include <asm/intel_regs.h>
@@ -126,6 +127,7 @@
 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
 	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
 		1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+	info->address_width = cpu_phys_address_size();
 
 	return 0;
 }
@@ -227,3 +229,80 @@
 		msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
 	msr_write(MSR_IA32_MISC_ENABLE, msr);
 }
+
+int cpu_get_coord_type(void)
+{
+	return HW_ALL;
+}
+
+int cpu_get_min_ratio(void)
+{
+	msr_t msr;
+
+	/* Get bus ratio limits and calculate clock speeds */
+	msr = msr_read(MSR_PLATFORM_INFO);
+
+	return (msr.hi >> 8) & 0xff;	/* Max Efficiency Ratio */
+}
+
+int cpu_get_max_ratio(void)
+{
+	u32 ratio_max;
+	msr_t msr;
+
+	if (cpu_config_tdp_levels()) {
+		/* Set max ratio to nominal TDP ratio */
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		ratio_max = msr.lo & 0xff;
+	} else {
+		msr = msr_read(MSR_PLATFORM_INFO);
+		/* Max Non-Turbo Ratio */
+		ratio_max = (msr.lo >> 8) & 0xff;
+	}
+
+	return ratio_max;
+}
+
+int cpu_get_bus_clock_khz(void)
+{
+	/*
+	 * CPU bus clock is set by default here to 100MHz. This function returns
+	 * the bus clock in KHz.
+	 */
+	return INTEL_BCLK_MHZ * 1000;
+}
+
+int cpu_get_power_max(void)
+{
+	int power_unit;
+	msr_t msr;
+
+	msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+	msr = msr_read(MSR_PKG_POWER_SKU);
+
+	return (msr.lo & 0x7fff) * 1000 / power_unit;
+}
+
+int cpu_get_max_turbo_ratio(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_TURBO_RATIO_LIMIT);
+
+	return msr.lo & 0xff;
+}
+
+int cpu_get_cores_per_package(void)
+{
+	struct cpuid_result result;
+	int cores = 1;
+
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 1;
+
+	result = cpuid_ext(0xb, 1);
+	cores = result.ebx & 0xff;
+
+	return cores;
+}

diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c
new file mode 100644
index 0000000..61ec539
--- /dev/null
+++ b/arch/x86/cpu/intel_common/generic_wifi.c

@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic WiFi ACPI info
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/drivers/wifi/generic.c
+ */
+
+#include <common.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <dm.h>
+#include <dm/acpi.h>
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* WGDS Domain type */
+#define WGDS_DOMAIN_TYPE_WIFI 0x7
+
+/*
+ * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
+ * The above representation returns unique and consistent name every time
+ * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
+ * chosen since it contains the bus address of the device.
+ */
+#define WIFI_ACPI_NAME_MAX_LEN 5
+
+/**
+ * struct generic_wifi_config - Data structure to contain common wifi config
+ * @wake: Wake pin for ACPI _PRW
+ * @maxsleep: Maximum sleep state to wake from
+ */
+struct generic_wifi_config {
+	unsigned int wake;
+	unsigned int maxsleep;
+};
+
+static int generic_wifi_fill_ssdt(struct acpi_ctx *ctx,
+				  const struct udevice *dev,
+				  const struct generic_wifi_config *config)
+{
+	char name[ACPI_NAME_MAX];
+	char path[ACPI_PATH_MAX];
+	pci_dev_t bdf;
+	u32 address;
+	int ret;
+
+	ret = acpi_device_path(dev_get_parent(dev), path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+	ret = acpi_get_name(dev, name);
+	if (ret)
+		return log_msg_ret("name", ret);
+
+	/* Device */
+	acpigen_write_scope(ctx, path);
+	acpigen_write_device(ctx, name);
+	acpigen_write_name_integer(ctx, "_UID", 0);
+	acpigen_write_name_string(ctx, "_DDN",
+				  dev_read_string(dev, "acpi,ddn"));
+
+	/* Address */
+	bdf = dm_pci_get_bdf(dev);
+	address = (PCI_DEV(bdf) << 16) | PCI_FUNC(bdf);
+	acpigen_write_name_dword(ctx, "_ADR", address);
+
+	/* Wake capabilities */
+	if (config)
+		acpigen_write_prw(ctx, config->wake, config->maxsleep);
+
+	acpigen_pop_len(ctx); /* Device */
+	acpigen_pop_len(ctx); /* Scope */
+
+	return 0;
+}
+
+static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev,
+				     struct acpi_ctx *ctx)
+{
+	struct generic_wifi_config config;
+	bool have_config;
+	int ret;
+
+	ret = dev_read_u32(dev, "acpi,wake", &config.wake);
+	have_config = !ret;
+	/* By default, all intel wifi chips wake from S3 */
+	config.maxsleep = 3;
+	ret = generic_wifi_fill_ssdt(ctx, dev, have_config ? &config : NULL);
+	if (ret)
+		return log_msg_ret("wifi", ret);
+
+	return 0;
+}
+
+struct acpi_ops wifi_acpi_ops = {
+	.fill_ssdt	= intel_wifi_acpi_fill_ssdt,
+};
+
+static const struct udevice_id intel_wifi_ids[] = {
+	{ .compatible = "intel,generic-wifi" },
+	{ }
+};
+
+U_BOOT_DRIVER(intel_wifi) = {
+	.name		= "intel_wifi",
+	.id		= UCLASS_MISC,
+	.of_match	= intel_wifi_ids,
+	ACPI_OPS_PTR(&wifi_acpi_ops)
+};

diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c
new file mode 100644
index 0000000..4e6c64d
--- /dev/null
+++ b/arch/x86/cpu/intel_common/intel_opregion.c

@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.c
+ */
+
+#include <common.h>
+#include <binman.h>
+#include <bloblist.h>
+#include <dm.h>
+#include <spi_flash.h>
+#include <asm/intel_opregion.h>
+
+static char vbt_data[8 << 10];
+
+static int locate_vbt(char **vbtp, int *sizep)
+{
+	struct binman_entry vbt;
+	struct udevice *dev;
+	u32 vbtsig = 0;
+	int size;
+	int ret;
+
+	ret = binman_entry_find("intel-vbt", &vbt);
+	if (ret)
+		return log_msg_ret("find VBT", ret);
+	ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
+	if (ret)
+		return log_msg_ret("find flash", ret);
+	size = vbt.size;
+	if (size > sizeof(vbt_data))
+		return log_msg_ret("vbt", -E2BIG);
+	ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
+	if (ret)
+		return log_msg_ret("read", ret);
+
+	memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
+	if (vbtsig != VBT_SIGNATURE) {
+		log_err("Missing/invalid signature in VBT data file!\n");
+		return -EINVAL;
+	}
+
+	log_info("Found a VBT of %u bytes\n", size);
+	*sizep = size;
+	*vbtp = vbt_data;
+
+	return 0;
+}
+
+/* Write ASLS PCI register and prepare SWSCI register */
+static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
+{
+	int sci_reg;
+
+	if (!device_active(dev))
+		return -ENOENT;
+
+	/*
+	 * Intel BIOS Specification
+	 * Chapter 5.3.7 "Initialise Hardware State"
+	 */
+	dm_pci_write_config32(dev, ASLS, opregion);
+
+	/*
+	 * Atom-based platforms use a combined SMI/SCI register,
+	 * whereas non-Atom platforms use a separate SCI register
+	 */
+	if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
+		sci_reg = SWSMISCI;
+	else
+		sci_reg = SWSCI;
+
+	/*
+	 * Intel's Windows driver relies on this:
+	 * Intel BIOS Specification
+	 * Chapter 5.4 "ASL Software SCI Handler"
+	 */
+	dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
+
+	return 0;
+}
+
+int intel_gma_init_igd_opregion(struct udevice *dev,
+				struct igd_opregion *opregion)
+{
+	struct optionrom_vbt *vbt = NULL;
+	char *vbt_buf;
+	int vbt_size;
+	int ret;
+
+	ret = locate_vbt(&vbt_buf, &vbt_size);
+	if (ret) {
+		log_err("GMA: VBT couldn't be found\n");
+		return log_msg_ret("find vbt", ret);
+	}
+	vbt = (struct optionrom_vbt *)vbt_buf;
+
+	memset(opregion, '\0', sizeof(struct igd_opregion));
+
+	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+	       sizeof(opregion->header.signature));
+	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
+	       ARRAY_SIZE(vbt->coreblock_biosbuild));
+	/* Extended VBT support */
+	if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
+		struct optionrom_vbt *ext_vbt;
+
+		ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT,
+					   vbt->hdr_vbt_size,
+					   (void **)&ext_vbt);
+		if (ret) {
+			log_err("GMA: Unable to add Ext VBT to bloblist\n");
+			return log_msg_ret("blob", ret);
+		}
+
+		memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
+		opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
+		opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+	} else {
+		/* Raw VBT size which can fit in gvd1 */
+		printf("copy to %p\n", opregion->vbt.gvd1);
+		memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
+	}
+
+	/* 8kb */
+	opregion->header.size = sizeof(struct igd_opregion) / 1024;
+
+	/*
+	 * Left-shift version field to accommodate Intel Windows driver quirk
+	 * when not using a VBIOS.
+	 * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
+	 *
+	 * No adverse effects when using VBIOS or booting Linux.
+	 */
+	opregion->header.version = IGD_OPREGION_VERSION << 24;
+
+	/* We just assume we're mobile for now */
+	opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+	/* Initialise Mailbox 1 */
+	opregion->mailbox1.clid = 1;
+
+	/* Initialise Mailbox 3 */
+	opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+	opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+	opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
+	opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+	opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+	opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+	opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+	opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+	opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+	opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+	opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+	opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+	opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+	opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+	opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+	/* Write ASLS PCI register and prepare SWSCI register */
+	ret = intel_gma_opregion_register(dev, (ulong)opregion);
+	if (ret)
+		return log_msg_ret("write asls", ret);
+
+	return 0;
+}

diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 2468d88..5180eb0 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c

@@ -19,6 +19,7 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <log.h>
+#include <sort.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mp.h>
@@ -66,9 +67,10 @@
 
 void mtrr_read_all(struct mtrr_info *info)
 {
+	int reg_count = mtrr_get_var_count();
 	int i;
 
-	for (i = 0; i < MTRR_COUNT; i++) {
+	for (i = 0; i < reg_count; i++) {
 		info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
 		info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
 	}
@@ -76,10 +78,11 @@
 
 void mtrr_write_all(struct mtrr_info *info)
 {
+	int reg_count = mtrr_get_var_count();
 	struct mtrr_state state;
 	int i;
 
-	for (i = 0; i < MTRR_COUNT; i++) {
+	for (i = 0; i < reg_count; i++) {
 		mtrr_open(&state, true);
 		wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base);
 		wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask);
@@ -124,6 +127,16 @@
 	return 0;
 }
 
+static int h_comp_mtrr(const void *p1, const void *p2)
+{
+	const struct mtrr_request *req1 = p1;
+	const struct mtrr_request *req2 = p2;
+
+	s64 diff = req1->start - req2->start;
+
+	return diff < 0 ? -1 : diff > 0 ? 1 : 0;
+}
+
 int mtrr_commit(bool do_caches)
 {
 	struct mtrr_request *req = gd->arch.mtrr_req;
@@ -139,12 +152,13 @@
 	debug("open\n");
 	mtrr_open(&state, do_caches);
 	debug("open done\n");
+	qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
 	for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
 		set_var_mtrr(i, req->type, req->start, req->size);
 
 	/* Clear the ones that are unused */
 	debug("clear\n");
-	for (; i < MTRR_COUNT; i++)
+	for (; i < MTRR_MAX_COUNT; i++)
 		wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
 	debug("close\n");
 	mtrr_close(&state, do_caches);
@@ -184,7 +198,7 @@
 	return 0;
 }
 
-static int get_var_mtrr_count(void)
+int mtrr_get_var_count(void)
 {
 	return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
 }
@@ -195,7 +209,7 @@
 	int vcnt;
 	int i;
 
-	vcnt = get_var_mtrr_count();
+	vcnt = mtrr_get_var_count();
 
 	/* Identify the first var mtrr which is not valid */
 	for (i = 0; i < vcnt; i++) {

diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig
index d2b7ede..571470c 100644
--- a/arch/x86/cpu/tangier/Kconfig
+++ b/arch/x86/cpu/tangier/Kconfig

@@ -12,6 +12,7 @@
 	imply MMC_SDHCI_TANGIER
 	imply USB
 	imply USB_DWC3
+	imply BINMAN
 
 if INTEL_TANGIER
 

diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 1b4d397..90a766c 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c

@@ -70,3 +70,8 @@
 {
 	return 0;
 }
+
+int cpu_phys_address_size(void)
+{
+	return CONFIG_CPU_ADDR_BITS;
+}

diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index a17a9c2..893a59b 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts

@@ -15,14 +15,20 @@
 #include "flashmap-16mb-rw.dtsi"
 #endif
 
+#include <dt-bindings/clock/intel-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/x86-irq.h>
+#include <asm/e820.h>
 #include <asm/intel_pinctrl_defs.h>
 #include <asm/arch-apollolake/cpu.h>
+#include <asm/arch-apollolake/gpe.h>
 #include <asm/arch-apollolake/gpio.h>
 #include <asm/arch-apollolake/iomap.h>
 #include <asm/arch-apollolake/pm.h>
 #include <dt-bindings/clock/intel-clock.h>
 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
 #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
+#include <dt-bindings/sound/nhlt.h>
 
 / {
 	model = "Google Coral";
@@ -40,6 +46,14 @@
 		i2c5 = &i2c_5;
 		i2c6 = &i2c_6;
 		i2c7 = &i2c_7;
+		mmc1 = &sdmmc;
+	};
+
+	board: board {
+		compatible = "google,coral";
+		recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
+		write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
+		phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
 	};
 
 	config {
@@ -48,6 +62,15 @@
 
 	chosen {
 		stdout-path = &serial;
+		e820-entries = /bits/ 64 <
+			IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
+			MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
+		u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3
+			&i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5
+			&sdmmc &maxim_codec &wifi &da_codec &tpm
+			&elan_touchscreen &raydium_touchscreen
+			&elan_touchpad &synaptics_touchpad &wacom_digitizer>;
+		u-boot,acpi-dsdt-order = <&board &lpc>;
 	};
 
 	clk: clock {
@@ -60,7 +83,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu_0: cpu@0 {
 			u-boot,dm-pre-reloc;
 			device_type = "cpu";
 			compatible = "intel,apl-cpu";
@@ -68,21 +91,21 @@
 			intel,apic-id = <0>;
 		};
 
-		cpu@1 {
+		cpu_1: cpu@1 {
 			device_type = "cpu";
 			compatible = "intel,apl-cpu";
 			reg = <1>;
 			intel,apic-id = <2>;
 		};
 
-		cpu@2 {
+		cpu_2: cpu@2 {
 			device_type = "cpu";
 			compatible = "intel,apl-cpu";
 			reg = <2>;
 			intel,apic-id = <4>;
 		};
 
-		cpu@3 {
+		cpu_3: cpu@3 {
 			device_type = "cpu";
 			compatible = "intel,apl-cpu";
 			reg = <3>;
@@ -128,6 +151,10 @@
 			 */
 			fsp_s: fsp-s {
 			};
+
+			nhlt {
+				intel,dmic-channels = <4>;
+			};
 		};
 
 		punit@0,1 {
@@ -136,21 +163,29 @@
 			compatible = "intel,apl-punit";
 		};
 
+		gma@2,0 {
+			reg = <0x00001000 0 0 0 0>;
+			compatible = "fsp-fb";
+		};
+
 		p2sb: p2sb@d,0 {
 			u-boot,dm-pre-reloc;
 			reg = <0x02006810 0 0 0 0>;
 			compatible = "intel,p2sb";
 			early-regs = <IOMAP_P2SB_BAR 0x100000>;
+			pci,no-autoconfig;
 
 			n {
 				compatible = "intel,apl-pinctrl";
 				u-boot,dm-pre-reloc;
 				intel,p2sb-port-id = <PID_GPIO_N>;
+				acpi,path = "\\_SB.GPO0";
 				gpio_n: gpio-n {
 					compatible = "intel,gpio";
 					u-boot,dm-pre-reloc;
 					gpio-controller;
 					#gpio-cells = <2>;
+					linux-name = "INT3452:00";
 				};
 			};
 
@@ -159,11 +194,13 @@
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_NW>;
 				#gpio-cells = <2>;
+				acpi,path = "\\_SB.GPO1";
 				gpio_nw: gpio-nw {
 					compatible = "intel,gpio";
 					u-boot,dm-pre-reloc;
 					gpio-controller;
 					#gpio-cells = <2>;
+					linux-name = "INT3452:01";
 				};
 			};
 
@@ -172,11 +209,13 @@
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_W>;
 				#gpio-cells = <2>;
+				acpi,path = "\\_SB.GPO2";
 				gpio_w: gpio-w {
 					compatible = "intel,gpio";
 					u-boot,dm-pre-reloc;
 					gpio-controller;
 					#gpio-cells = <2>;
+					linux-name = "INT3452:02";
 				};
 			};
 
@@ -185,11 +224,13 @@
 				compatible = "intel,apl-pinctrl";
 				intel,p2sb-port-id = <PID_GPIO_SW>;
 				#gpio-cells = <2>;
+				acpi,path = "\\_SB.GPO3";
 				gpio_sw: gpio-sw {
 					compatible = "intel,gpio";
 					u-boot,dm-pre-reloc;
 					gpio-controller;
 					#gpio-cells = <2>;
+					linux-name = "INT3452:03";
 				};
 			};
 
@@ -238,6 +279,24 @@
 			gpe0-en = <0x30>;
 		};
 
+		audio@e,0 {
+			reg = <0x7000 0 0 0 0>;
+			compatible = "simple-bus";
+			acpi,name = "HDAS";
+			i2s {
+				compatible = "fred";
+			};
+			maxim_codec: maxim-codec {
+				compatible = "maxim,max98357a";
+				acpi,ddn = "Maxim Integrated 98357A Amplifier";
+				sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>;
+				sdmode-delay = <5>;
+				acpi,name = "MAXM";
+				acpi,hid = "MX98357A";
+				acpi,audio-link = <AUDIO_LINK_SSP5>;
+			};
+		};
+
 		spi: fast-spi@d,2 {
 			u-boot,dm-pre-reloc;
 			reg = <0x02006a10 0 0 0 0>;
@@ -267,19 +326,63 @@
 			};
 		};
 
+		/* WiFi */
+		pcie-a0@14,0 {
+			reg = <0x0000a000 0 0 0 0>;
+			acpi,name = "RP01";
+			wifi: wifi {
+				compatible = "intel,generic-wifi";
+				acpi,ddn = "Intel WiFi";
+				acpi,name = "WF00";
+				acpi,wake = <GPE0_DW3_00>;
+				interrupts-extended = <&acpi_gpe 0x3c 0>;
+			};
+		};
+
 		i2c_0: i2c2@16,0 {
 			compatible = "intel,apl-i2c";
 			reg = <0x0200b010 0 0 0 0>;
 			clocks = <&clk CLK_I2C>;
 			i2c-scl-rising-time-ns = <104>;
 			i2c-scl-falling-time-ns = <52>;
+			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000 1000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			da_codec: da-codec {
+				reg = <0x1a>;
+				compatible = "dlg,da7219";
+				interrupts-extended = <&acpi_gpe GPIO_116_IRQ
+					(IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
+				acpi,name = "DLG7";
+				acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec";
+				acpi,audio-link = <AUDIO_LINK_SSP1>;
+				dlg,micbias-lvl = <2600>;
+				dlg,mic-amp-in-sel = "diff";
+				da7219_aad {
+					dlg,btn-cfg = <50>;
+					dlg,mic-det-thr = <500>;
+					dlg,jack-ins-deb = <20>;
+					dlg,jack-det-rate = "32ms_64ms";
+					dlg,jack-rem-deb = <1>;
+					dlg,a-d-btn-thr = <0xa>;
+					dlg,d-b-btn-thr = <0x16>;
+					dlg,b-c-btn-thr = <0x21>;
+					dlg,c-mic-btn-thr = <0x3e>;
+					dlg,btn-avg = <4>;
+					dlg,adc-1bit-rpt = <1>;
+				};
+			};
 		};
 
 		i2c_1: i2c2@16,1 {
 			compatible = "intel,apl-i2c";
 			reg = <0x0200b110 0 0 0 0>;
 			clocks = <&clk CLK_I2C>;
-			status = "disabled";
+			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000 1000000 3400000>;
+			i2c-scl-rising-time-ns = <52>;
+			i2c-scl-falling-time-ns = <52>;
 		};
 
 		i2c_2: i2c2@16,2 {
@@ -288,53 +391,130 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000 1000000>;
 			clocks = <&clk CLK_I2C>;
 			i2c-scl-rising-time-ns = <57>;
 			i2c-scl-falling-time-ns = <28>;
-			tpm@50 {
+			tpm: tpm@50 {
 				reg = <0x50>;
 				compatible = "google,cr50";
 				u-boot,i2c-offset-len = <0>;
 				ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
-				interrupts-extended = <&acpi_gpe 0x3c 0>;
+				interrupts-extended = <&acpi_gpe GPIO_28_IRQ
+					 IRQ_TYPE_EDGE_FALLING>;
+				acpi,hid = "GOOG0005";
+				acpi,ddn = "I2C TPM";
+				acpi,name = "TPMI";
 			};
 		};
 
 		i2c_3: i2c2@16,3 {
 			compatible = "intel,apl-i2c";
-			reg = <0x0200b110 0 0 0 0>;
+			reg = <0x0200b310 0 0 0 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			clocks = <&clk CLK_I2C>;
 			i2c-scl-rising-time-ns = <76>;
 			i2c-scl-falling-time-ns = <164>;
+			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000>;
+			elan_touchscreen: elan-touchscreen@10 {
+				compatible = "i2c-chip";
+				reg = <0x10>;
+				acpi,hid = "ELAN0001";
+				acpi,ddn = "ELAN Touchscreen";
+				interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+					IRQ_TYPE_EDGE_FALLING>;
+				linux,probed;
+				reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+				reset-delay-ms = <20>;
+				enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+				enable-delay-ms = <1>;
+				acpi,has-power-resource;
+			};
+
+			raydium_touchscreen: raydium-touchscreen@39 {
+				compatible = "i2c-chip";
+				reg = <0x39>;
+				acpi,hid = "RAYD0001";
+				acpi,ddn = "Raydium Touchscreen";
+				interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+					IRQ_TYPE_EDGE_FALLING>;
+				linux,probed;
+				reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+				reset-delay-ms = <1>;
+				enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+				enable-delay-ms = <50>;
+				acpi,has-power-resource;
+			};
 		};
 
 		i2c_4: i2c2@17,0 {
 			compatible = "intel,apl-i2c";
-			reg = <0x0200b110 0 0 0 0>;
+			reg = <0x0200b810 0 0 0 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			clocks = <&clk CLK_I2C>;
 			i2c-sda-hold-time-ns = <350>;
 			i2c-scl-rising-time-ns = <114>;
 			i2c-scl-falling-time-ns = <164>;
+			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000>;
+			elan_touchpad: elan-touchpad@15 {
+				compatible = "i2c-chip";
+				reg = <0x15>;
+				u-boot,i2c-offset-len = <0>;
+				acpi,hid = "ELAN0000";
+				acpi,ddn = "ELAN Touchpad";
+				interrupts-extended = <&acpi_gpe GPIO_18_IRQ
+					 IRQ_TYPE_EDGE_FALLING>;
+				acpi,wake = <GPE0_DW1_15>;
+				linux,probed;
+			};
+			synaptics_touchpad: synaptics-touchpad@2c {
+				compatible = "hid-over-i2c";
+				reg = <0x2c>;
+				acpi,hid = "PNP0C50";
+				acpi,ddn = "Synaptics Touchpad";
+				interrupts-extended = <&acpi_gpe GPIO_18_IRQ
+					 IRQ_TYPE_EDGE_FALLING>;
+				acpi,wake = <GPE0_DW1_15>;
+				linux,probed;
+				hid-descr-addr = <0x20>;
+			};
 		};
 
 		i2c_5: i2c2@17,1 {
 			compatible = "intel,apl-i2c";
-			reg = <0x0200b110 0 0 0 0>;
+			reg = <0x0200b910 0 0 0 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			clocks = <&clk CLK_I2C>;
 			i2c-scl-rising-time-ns = <76>;
 			i2c-scl-falling-time-ns = <164>;
+			clock-frequency = <400000>;
+			i2c,speeds = <100000 400000 1000000>;
+			wacom_digitizer: wacom-digitizer@9 {
+				compatible = "hid-over-i2c";
+				reg = <0x9>;
+				acpi,hid = "WCOM50C1";
+				acpi,ddn = "WCOM Digitizer";
+				interrupts-extended = <&acpi_gpe GPIO_13_IRQ
+					(IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
+				hid-descr-addr = <0x1>;
+			};
 		};
 
 		i2c_6: i2c2@17,2 {
 			compatible = "intel,apl-i2c";
-			reg = <0x0200b110 0 0 0 0>;
+			reg = <0x0200ba10 0 0 0 0>;
 			clocks = <&clk CLK_I2C>;
 			status = "disabled";
 		};
 
 		i2c_7: i2c2@17,3 {
 			compatible = "intel,apl-i2c";
-			reg = <0x0200b110 0 0 0 0>;
+			reg = <0x0200bb10 0 0 0 0>;
 			clocks = <&clk CLK_I2C>;
 			status = "disabled";
 		};
@@ -347,6 +527,15 @@
 			reg-shift = <2>;
 			clock-frequency = <1843200>;
 			current-speed = <115200>;
+			acpi,name = "URT3";
+			pci,no-autoconfig;
+		};
+
+		sdmmc: sdmmc@1b,0 {
+			reg = <0x0000d800 0 0 0 0>;
+			compatible = "intel,apl-sd";
+			cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>;
+			acpi,name = "SDCD";
 		};
 
 		pch: pch@1f,0 {
@@ -356,7 +545,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			lpc {
+			lpc: lpc {
 				compatible = "intel,apl-lpc";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -594,12 +783,17 @@
 	 * [6:0] steps of delay for HS200, each 125ps
 	 */
 	/* Enable DPTF */
-	dptf-enable;
+	fsps,dptf-enabled;
 	fsps,emmc-tx-data-cntl1 = <0x0c16>;
 	fsps,emmc-tx-data-cntl2 = <0x28162828>;
 	fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
 	fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
 
+	/* Enable Audio Clock and Power gating */
+	fsps,hd-audio-clk-gate = <1>;
+	fsps,hd-audio-pwr-gate = <1>;
+	fsps,bios-cfg-lock-down = <1>;
+
 	/* Enable WiFi */
 	fsps,pcie-root-port-en = [01 00 00 00 00 00];
 	fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
@@ -611,6 +805,10 @@
 	fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
 	fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
 
+	fsps,lpss-s0ix-enable = <1>;
+	fsps,usb-otg = <0>;
+	fsps,monitor-mwait-enable = <0>;
+
 	/*
 	 * TODO(sjg@chromium.org): Move this to the I2C nodes
 	 * Intel Common SoC Config

diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index df24aa0..e2f9469 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts

@@ -22,6 +22,10 @@
 		serial2 = &serial2;
 	};
 
+	binman: binman {
+		multiple-images;
+	};
+
 	chosen {
 		stdout-path = &serial2;
 	};
@@ -130,3 +134,33 @@
 		};
 	};
 };
+
+&binman {
+	u-boot-edison {
+		filename = "u-boot-edison.img";
+
+		/* This is the OSIP */
+		blob {
+			filename = "edison-osip.dat";
+		};
+
+		u-boot {
+			offset = <0x200>;
+		};
+
+		u-boot-env {
+			offset = <0x200200>;
+			filename = "edison-environment.txt";
+			size = <0x10000>;
+			fill-byte = [ff];
+		};
+
+		u-boot-env2 {
+			type = "u-boot-env";
+			offset = <0x500200>;
+			filename = "edison-environment.txt";
+			size = <0x10000>;
+			fill-byte = [ff];
+		};
+	};
+};

diff --git a/arch/x86/dts/emulation-u-boot.dtsi b/arch/x86/dts/emulation-u-boot.dtsi
index 6b651a3..7245fe5 100644
--- a/arch/x86/dts/emulation-u-boot.dtsi
+++ b/arch/x86/dts/emulation-u-boot.dtsi

@@ -7,17 +7,15 @@
 #include <u-boot.dtsi>
 
 #ifdef CONFIG_ROM_SIZE
-/ {
-	binman {
+&rom {
 #ifdef CONFIG_SPL
-		u-boot-spl-with-ucode-ptr {
-			optional-ucode;
-		};
+	u-boot-spl-with-ucode-ptr {
+		optional-ucode;
+	};
 #else
-		u-boot-with-ucode-ptr {
-			optional-ucode;
-		};
-#endif
+	u-boot-with-ucode-ptr {
+		optional-ucode;
 	};
+#endif
 };
 #endif

diff --git a/arch/x86/dts/quark-u-boot.dtsi b/arch/x86/dts/quark-u-boot.dtsi
index 7ebc301..60ffffc 100644
--- a/arch/x86/dts/quark-u-boot.dtsi
+++ b/arch/x86/dts/quark-u-boot.dtsi

@@ -6,11 +6,9 @@
 #include <u-boot.dtsi>
 
 #ifdef CONFIG_ROM_SIZE
-/ {
-	binman {
-		u-boot-with-ucode-ptr {
-			optional-ucode;
-		};
+&rom {
+	u-boot-with-ucode-ptr {
+		optional-ucode;
 	};
 };
 #endif

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index fa8106c..90badcc 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi

@@ -6,7 +6,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_CHROMEOS
 / {
 	binman {
 		multiple-images;
@@ -14,12 +13,6 @@
 		};
 	};
 };
-#else
-/ {
-	rom: binman {
-	};
-};
-#endif
 
 #ifdef CONFIG_ROM_SIZE
 &rom {

diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl
new file mode 100644
index 0000000..2a0fd33
--- /dev/null
+++ b/arch/x86/include/asm/acpi/chromeos.asl

@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ */
+
+#ifdef CONFIG_CHROMEOS
+
+#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+
+#include <asm/acpi/vbnv_layout.h>
+
+/* GPIO package generated at run time. */
+External (OIPG)
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBOOT_VBNV_OFFSET,
+			VBOOT_VBNV_BLOCK_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
+
+#include "ramoops.asl"
+
+#endif

diff --git a/arch/x86/include/asm/acpi/cpu.asl b/arch/x86/include/asm/acpi/cpu.asl
new file mode 100644
index 0000000..b20b357
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cpu.asl

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
+
+/* Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+	\_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+	\_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+	\_PR.CNOT (0x82)
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/ac.asl b/arch/x86/include/asm/acpi/cros_ec/ac.asl
new file mode 100644
index 0000000..80e0ebd
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/ac.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003")
+	Name (_PCL, Package () { \_SB })
+
+	Method (_PSR)
+	{
+		Return (ACEX)
+	}
+
+	Method (_STA)
+	{
+		Return (0x0F)
+	}
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/als.asl b/arch/x86/include/asm/acpi/cros_ec/als.asl
new file mode 100644
index 0000000..f3d40f88
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/als.asl

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Device (ALS)
+{
+	Name (_HID, "ACPI0008")
+	Name (_UID, 1)
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+
+	/*
+	 * Returns the current ambient light illuminance reading in lux
+	 *
+	 *  0: Reading is below the range of sensitivity of the sensor
+	 * -1: Reading is above the range or sensitivity of the sensor
+	 */
+	Method (_ALI, 0, NotSerialized)
+	{
+		Return (^^ALS0)
+	}
+
+	/*
+	 * Returns a recommended polling frequency in tenths of seconds
+	 *
+	 *  0: No need to poll, async notifications will indicate changes
+	 */
+	Name (_ALP, 10)
+
+	/*
+	 * Returns a package of packages where each tuple consists of a pair
+	 * of integers mapping ambient light illuminance to display brightness.
+	 *
+	 * {<display luminance adjustment>, <ambient light illuminance>}
+	 *
+	 * Ambient light illuminance values are specified in lux.
+	 *
+	 * Display luminance adjustment values are relative percentages where
+	 * 100 is no (0%) display brightness adjustment.  Values <100 indicate
+	 * negative adjustment (dimming) and values >100 indicate positive
+	 * adjustment (brightening).
+	 *
+	 * This is currently unused by the Linux kernel ACPI ALS driver but
+	 * is required by the ACPI specification so just define a basic two
+	 * point response curve.
+	 */
+	Name (_ALR, Package ()
+	{
+		Package () { 70, 30 },    // Min { -30% adjust at 30 lux }
+		Package () { 150, 1000 }  // Max { +50% adjust at 1000 lux }
+	})
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/battery.asl b/arch/x86/include/asm/acpi/cros_ec/battery.asl
new file mode 100644
index 0000000..f106088
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/battery.asl

@@ -0,0 +1,411 @@
+/*/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+/* Mutex for EC battery index interface */
+Mutex (BATM, 0)
+
+// Wait for desired battery index to be presented in shared memory
+//   Arg0 = battery index
+//   Returns Zero on success, One on error.
+Method (BTSW, 1)
+{
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+	If (LEqual (BTIX, Arg0)) {
+		Return (Zero)
+	}
+	If (LGreaterEqual (Arg0, BTCN)) {
+		Return (One)
+	}
+	Store (Arg0, \_SB.PCI0.LPCB.EC0.BTID)
+	Store (5, Local0)      // Timeout 5 msec
+	While (LNotEqual (BTIX, Arg0))
+	{
+		Sleep (1)
+		Decrement (Local0)
+		If (LEqual (Local0, Zero))
+		{
+			Return (One)
+		}
+	}
+#else
+	If (LNotEqual (0, Arg0)) {
+		Return (One)
+	}
+#endif
+	Return (Zero)
+}
+
+// _STA implementation.
+//   Arg0 = battery index
+Method (BSTA, 1, Serialized)
+{
+	If (Acquire (^BATM, 1000)) {
+		Return (Zero)
+	}
+
+	If (And(Not(BTSW (Arg0)), BTEX)) {
+		Store (0x1F, Local0)
+	} Else {
+		Store (0x0F, Local0)
+	}
+
+	Release (^BATM)
+	Return (Local0)
+}
+
+// _BIF implementation.
+//   Arg0 = battery index
+//   Arg1 = PBIF
+Method (BBIF, 2, Serialized)
+{
+	If (Acquire (^BATM, 1000)) {
+		Return (Arg1)
+	}
+
+	If (BTSW (Arg0)) {
+		Release (^BATM)
+		Return (Arg1)
+	}
+	// Last Full Charge Capacity
+	Store (BTDF, Index (Arg1, 2))
+
+	// Design Voltage
+	Store (BTDV, Index (Arg1, 4))
+
+	// Design Capacity
+	Store (BTDA, Local0)
+	Store (Local0, Index (Arg1, 1))
+
+	// Design Capacity of Warning
+	Divide (Multiply (Local0, DWRN), 100, , Local2)
+	Store (Local2, Index (Arg1, 5))
+
+	// Design Capacity of Low
+	Divide (Multiply (Local0, DLOW), 100, , Local2)
+	Store (Local2, Index (Arg1, 6))
+
+	// Get battery info from mainboard
+	Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 9))
+	Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 10))
+	Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 12))
+
+	Release (^BATM)
+	Return (Arg1)
+}
+
+// _BIX implementation.
+//   Arg0 = battery index
+//   Arg1 = PBIX
+Method (BBIX, 2, Serialized)
+{
+	If (Acquire (^BATM, 1000)) {
+		Return (Arg1)
+	}
+
+	If (BTSW (Arg0)) {
+		Release (^BATM)
+		Return (Arg1)
+	}
+	// Last Full Charge Capacity
+	Store (BTDF, Index (Arg1, 3))
+
+	// Design Voltage
+	Store (BTDV, Index (Arg1, 5))
+
+	// Design Capacity
+	Store (BTDA, Local0)
+	Store (Local0, Index (Arg1, 2))
+
+	// Design Capacity of Warning
+	Divide (Multiply (Local0, DWRN), 100, , Local2)
+	Store (Local2, Index (Arg1, 6))
+
+	// Design Capacity of Low
+	Divide (Multiply (Local0, DLOW), 100, , Local2)
+	Store (Local2, Index (Arg1, 7))
+
+	// Cycle Count
+	Store (BTCC, Index (Arg1, 8))
+
+	// Get battery info from mainboard
+	Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 16))
+	Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 17))
+	Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 19))
+
+	Release (^BATM)
+	Return (Arg1)
+}
+
+// _BST implementation.
+//   Arg0 = battery index
+//   Arg1 = PBST
+//   Arg2 = BSTP
+//   Arg3 = BFWK
+Method (BBST, 4, Serialized)
+{
+	If (Acquire (^BATM, 1000)) {
+		Return (Arg1)
+	}
+
+	If (BTSW (Arg0)) {
+		Release (^BATM)
+		Return (Arg1)
+	}
+	//
+	// 0: BATTERY STATE
+	//
+	// bit 0 = discharging
+	// bit 1 = charging
+	// bit 2 = critical level
+	//
+	Store (Zero, Local1)
+
+	// Check if AC is present
+	If (ACEX) {
+		If (BFCG) {
+			Store (0x02, Local1)
+		} ElseIf (BFDC) {
+			Store (0x01, Local1)
+		}
+	} Else {
+		// Always discharging when on battery power
+		Store (0x01, Local1)
+	}
+
+	// Check for critical battery level
+	If (BFCR) {
+		Or (Local1, 0x04, Local1)
+	}
+	Store (Local1, Index (Arg1, 0))
+
+	// Notify if battery state has changed since last time
+	If (LNotEqual (Local1, DeRefOf (Arg2))) {
+		Store (Local1, Arg2)
+		If (LEqual(Arg0, 0)) {
+			Notify (BAT0, 0x80)
+		}
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+		Else {
+			Notify (BAT1, 0x80)
+		}
+#endif
+	}
+
+	//
+	// 1: BATTERY PRESENT RATE
+	//
+	Store (BTPR, Index (Arg1, 1))
+
+	//
+	// 2: BATTERY REMAINING CAPACITY
+	//
+	Store (BTRA, Local1)
+	If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) {
+		// On AC power and battery is neither charging
+		// nor discharging.  Linux expects a full battery
+		// to report same capacity as last full charge.
+		// https://bugzilla.kernel.org/show_bug.cgi?id=12632
+		Store (BTDF, Local2)
+
+		// See if within ~6% of full
+		ShiftRight (Local2, 4, Local3)
+		If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+		          LLess (Local1, Add (Local2, Local3))))
+		{
+			Store (Local2, Local1)
+		}
+	}
+	Store (Local1, Index (Arg1, 2))
+
+	//
+	// 3: BATTERY PRESENT VOLTAGE
+	//
+	Store (BTVO, Index (Arg1, 3))
+
+	Release (^BATM)
+	Return (Arg1)
+}
+
+Device (BAT0)
+{
+	Name (_HID, EISAID ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Name (PBIF, Package () {
+		0x00000001,  // 0x00: Power Unit: mAh
+		0xFFFFFFFF,  // 0x01: Design Capacity
+		0xFFFFFFFF,  // 0x02: Last Full Charge Capacity
+		0x00000001,  // 0x03: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x04: Design Voltage
+		0x00000003,  // 0x05: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x06: Design Capacity of Low
+		0x00000001,  // 0x07: Capacity Granularity 1
+		0x00000001,  // 0x08: Capacity Granularity 2
+		"",          // 0x09: Model Number
+		"",          // 0x0a: Serial Number
+		"LION",      // 0x0b: Battery Type
+		""           // 0x0c: OEM Information
+	})
+
+	Name (PBIX, Package () {
+		0x00000000,  // 0x00: Revision
+		0x00000001,  // 0x01: Power Unit: mAh
+		0xFFFFFFFF,  // 0x02: Design Capacity
+		0xFFFFFFFF,  // 0x03: Last Full Charge Capacity
+		0x00000001,  // 0x04: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x05: Design Voltage
+		0x00000003,  // 0x06: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x07: Design Capacity of Low
+		0x00000000,  // 0x08: Cycle Count
+		0x00018000,  // 0x09: Measurement Accuracy (98.3%?)
+		0x000001F4,  // 0x0a: Max Sampling Time (500ms)
+		0x0000000a,  // 0x0b: Min Sampling Time (10ms)
+		0xFFFFFFFF,  // 0x0c: Max Averaging Interval
+		0xFFFFFFFF,  // 0x0d: Min Averaging Interval
+		0x00000001,  // 0x0e: Capacity Granularity 1
+		0x00000001,  // 0x0f: Capacity Granularity 2
+		"",          // 0x10 Model Number
+		"",          // 0x11: Serial Number
+		"LION",      // 0x12: Battery Type
+		""           // 0x13: OEM Information
+	})
+
+	Name (PBST, Package () {
+		0x00000000,  // 0x00: Battery State
+		0xFFFFFFFF,  // 0x01: Battery Present Rate
+		0xFFFFFFFF,  // 0x02: Battery Remaining Capacity
+		0xFFFFFFFF,  // 0x03: Battery Present Voltage
+	})
+	Name (BSTP, Zero)
+
+	// Workaround for full battery status, disabled by default
+	Name (BFWK, Zero)
+
+	// Method to enable full battery workaround
+	Method (BFWE)
+	{
+		Store (One, BFWK)
+	}
+
+	// Method to disable full battery workaround
+	Method (BFWD)
+	{
+		Store (Zero, BFWK)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		Return (BSTA (0))
+	}
+
+	Method (_BIF, 0, Serialized)
+	{
+		Return (BBIF (0, PBIF))
+	}
+
+	Method (_BIX, 0, Serialized)
+	{
+		Return (BBIX (0, PBIX))
+	}
+
+	Method (_BST, 0, Serialized)
+	{
+		Return (BBST (0, PBST, RefOf (BSTP), BFWK))
+	}
+}
+
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+Device (BAT1)
+{
+	Name (_HID, EISAID ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Name (PBIF, Package () {
+		0x00000001,  // 0x00: Power Unit: mAh
+		0xFFFFFFFF,  // 0x01: Design Capacity
+		0xFFFFFFFF,  // 0x02: Last Full Charge Capacity
+		0x00000001,  // 0x03: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x04: Design Voltage
+		0x00000003,  // 0x05: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x06: Design Capacity of Low
+		0x00000001,  // 0x07: Capacity Granularity 1
+		0x00000001,  // 0x08: Capacity Granularity 2
+		"",          // 0x09: Model Number
+		"",          // 0x0a: Serial Number
+		"LION",      // 0x0b: Battery Type
+		""           // 0x0c: OEM Information
+	})
+
+	Name (PBIX, Package () {
+		0x00000000,  // 0x00: Revision
+		0x00000001,  // 0x01: Power Unit: mAh
+		0xFFFFFFFF,  // 0x02: Design Capacity
+		0xFFFFFFFF,  // 0x03: Last Full Charge Capacity
+		0x00000001,  // 0x04: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x05: Design Voltage
+		0x00000003,  // 0x06: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x07: Design Capacity of Low
+		0x00000000,  // 0x08: Cycle Count
+		0x00018000,  // 0x09: Measurement Accuracy (98.3%?)
+		0x000001F4,  // 0x0a: Max Sampling Time (500ms)
+		0x0000000a,  // 0x0b: Min Sampling Time (10ms)
+		0xFFFFFFFF,  // 0x0c: Max Averaging Interval
+		0xFFFFFFFF,  // 0x0d: Min Averaging Interval
+		0x00000001,  // 0x0e: Capacity Granularity 1
+		0x00000001,  // 0x0f: Capacity Granularity 2
+		"",          // 0x10 Model Number
+		"",          // 0x11: Serial Number
+		"LION",      // 0x12: Battery Type
+		""           // 0x13: OEM Information
+	})
+
+	Name (PBST, Package () {
+		0x00000000,  // 0x00: Battery State
+		0xFFFFFFFF,  // 0x01: Battery Present Rate
+		0xFFFFFFFF,  // 0x02: Battery Remaining Capacity
+		0xFFFFFFFF,  // 0x03: Battery Present Voltage
+	})
+	Name (BSTP, Zero)
+
+	// Workaround for full battery status, disabled by default
+	Name (BFWK, Zero)
+
+	// Method to enable full battery workaround
+	Method (BFWE)
+	{
+		Store (One, BFWK)
+	}
+
+	// Method to disable full battery workaround
+	Method (BFWD)
+	{
+		Store (Zero, BFWK)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		Return (BSTA (1))
+	}
+
+	Method (_BIF, 0, Serialized)
+	{
+		Return (BBIF (1, PBIF))
+	}
+
+	Method (_BIX, 0, Serialized)
+	{
+		Return (BBIX (1, PBIX))
+	}
+
+	Method (_BST, 0, Serialized)
+	{
+		Return (BBST (1, PBST, RefOf (BSTP), BFWK))
+	}
+}
+#endif

diff --git a/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
new file mode 100644
index 0000000..9f50185
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+Device (CREC)
+{
+	Name (_HID, "GOOG0004")
+	Name (_UID, 1)
+	Name (_DDN, "EC Command Device")
+#ifdef EC_ENABLE_WAKE_PIN
+	Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
+#endif
+
+#ifdef EC_ENABLE_SYNC_IRQ
+	Name (_CRS, ResourceTemplate ()
+	{
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive)
+		{
+			EC_SYNC_IRQ
+		}
+	})
+#endif
+
+#ifdef EC_ENABLE_SYNC_IRQ_GPIO
+	Name (_CRS, ResourceTemplate ()
+	{
+		GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000,
+		         "\\_SB.GPIO", 0x00, ResourceConsumer, ,)
+		{
+			EC_SYNC_IRQ
+		}
+	})
+#endif
+
+#ifdef EC_ENABLE_MKBP_DEVICE
+	Device (CKSC)
+	{
+		Name (_HID, "GOOG0007")
+		Name (_UID, 1)
+		Name (_DDN, "EC MKBP Device")
+	}
+#endif
+
+#ifdef EC_ENABLE_CBAS_DEVICE
+	Device (CBAS)
+	{
+		Name (_HID, "GOOG000B")
+		Name (_UID, 1)
+		Name (_DDN, "EC Base Switch Device")
+	}
+#endif
+	Method(_STA, 0)
+	{
+		Return (0xB)
+	}
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/ec.asl b/arch/x86/include/asm/acpi/cros_ec/ec.asl
new file mode 100644
index 0000000..03f57f2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/ec.asl

@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+// Mainboard specific throttle handler
+#ifdef DPTF_ENABLE_CHARGER
+External (\_SB.DPTF.TCHG, DeviceObj)
+#endif
+
+
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, EC_SCI_GPI)
+	Name (TOFS, EC_TEMP_SENSOR_OFFSET)
+	Name (TNCA, EC_TEMP_SENSOR_NOT_CALIBRATED)
+	Name (TNOP, EC_TEMP_SENSOR_NOT_POWERED)
+	Name (TBAD, EC_TEMP_SENSOR_ERROR)
+	Name (TNPR, EC_TEMP_SENSOR_NOT_PRESENT)
+	Name (DWRN, 15)		// Battery capacity warning at 15%
+	Name (DLOW, 10)		// Battery capacity low at 10%
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x00),
+		RAMV, 8,	// EC RAM Version
+		TSTB, 8,	// Test Byte
+		TSTC, 8,	// Complement of Test Byte
+		KBLV, 8,	// Keyboard Backlight value
+		FAND, 8,	// Set Fan Duty Cycle
+		PATI, 8,	// Programmable Auxiliary Trip Sensor ID
+		PATT, 8,	// Programmable Auxiliary Trip Threshold
+		PATC, 8,	// Programmable Auxiliary Trip Commit
+		CHGL, 8,	// Charger Current Limit
+		TBMD, 1,	// Tablet mode
+		DDPN, 3,	// Device DPTF Profile Number
+		// DFUD must be 0 for the other 31 values to be valid
+		Offset (0x0a),
+		DFUD, 1,	// Device Features Undefined
+		FLSH, 1,	// Flash commands present
+		PFAN, 1,	// PWM Fan control present
+		KBLE, 1,	// Keyboard Backlight present
+		LTBR, 1,	// Lightbar present
+		LEDC, 1,	// LED control
+		MTNS, 1,	// Motion sensors present
+		KEYB, 1,	// EC is keyboard controller
+		PSTR, 1,	// Persistent storage
+		P80P, 1,	// EC serves I/O Port 80h
+		THRM, 1,	// EC supports thermal management
+		SBKL, 1,	// Screen backlight switch present
+		WIFI, 1,	// WIFI switch present
+		HOST, 1,	// EC monitors host events (eg SCI, SMI)
+		GPIO, 1,	// EC provides GPIO commands
+		I2CB, 1,	// EC provides I2C controller access
+		CHRG, 1,	// EC provides commands for charger control
+		BATT, 1,	// Simply Battery support
+		SBAT, 1,	// Smart Battery support
+		HANG, 1,	// EC can detect host hang
+		PMUI, 1,	// Power Information
+		DSEC, 1,	// another EC exists downstream
+		UPDC, 1,	// supports USB Power Delivery
+		UMUX, 1,	// supports USB Mux
+		MSFF, 1,	// Motion Sense has FIFO
+		TVST, 1,	// supports temporary secure vstore
+		TCMV, 1,	// USB Type C Muxing is virtual (host assisted)
+		RTCD, 1,	// EC provides an RTC device
+		FPRD, 1,	// EC provides a fingerprint reader device
+		TPAD, 1,	// EC provides a touchpad device
+		RWSG, 1,	// EC has RWSIG task enabled
+		DEVE, 1,	// EC supports device events
+		// make sure we're within our space envelope
+		Offset (0x0e),
+		Offset (0x12),
+		BTID, 8,	// Battery index that host wants to read
+		USPP, 8,	// USB Port Power
+}
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
+	OperationRegion (EMEM, EmbeddedControl,
+			 EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE)
+	Field (EMEM, ByteAcc, Lock, Preserve)
+#else
+	OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+	Field (EMEM, ByteAcc, NoLock, Preserve)
+#endif
+	{
+		#include "emem.asl"
+	}
+
+#ifdef EC_ENABLE_LID_SWITCH
+	/* LID Switch */
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (^^LIDS)
+		}
+
+#ifdef EC_ENABLE_WAKE_PIN
+		Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
+#endif
+	}
+#endif
+
+	Method (TINS, 1, Serialized)
+	{
+		Switch (ToInteger (Arg0))
+		{
+			Case (0) { Return (TIN0) }
+			Case (1) { Return (TIN1) }
+			Case (2) { Return (TIN2) }
+			Case (3) { Return (TIN3) }
+			Case (4) { Return (TIN4) }
+			Case (5) { Return (TIN5) }
+			Case (6) { Return (TIN6) }
+			Case (7) { Return (TIN7) }
+			Case (8) { Return (TIN8) }
+			Case (9) { Return (TIN9) }
+			Default  { Return (TIN0) }
+		}
+	}
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16,
+			    EC_LPC_ADDR_ACPI_DATA,
+			    EC_LPC_ADDR_ACPI_DATA,
+			    0, 1)
+			IO (Decode16,
+			    EC_LPC_ADDR_ACPI_CMD,
+			    EC_LPC_ADDR_ACPI_CMD,
+			    0, 1)
+		})
+		Return (ECMD)
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		// Initialize AC power state
+		Store (ACEX, \PWRS)
+
+		// Initialize LID switch state
+		Store (LIDS, \LIDS)
+	}
+
+	/* Read requested temperature and check against EC error values */
+	Method (TSRD, 1, Serialized)
+	{
+		Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0)
+
+		/* Check for sensor not calibrated */
+		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
+			Return (Zero)
+		}
+
+		/* Check for sensor not present */
+		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+			Return (Zero)
+		}
+
+		/* Check for sensor not powered */
+		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+			Return (Zero)
+		}
+
+		/* Check for sensor bad reading */
+		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+			Return (Zero)
+		}
+
+		/* Adjust by offset to get Kelvin */
+		Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+		/* Convert to 1/10 Kelvin */
+		Multiply (Local0, 10, Local0)
+
+		Return (Local0)
+	}
+
+	// Lid Closed Event
+	Method (_Q01, 0, NotSerialized)
+	{
+		Store ("EC: LID CLOSE", Debug)
+		Store (LIDS, \LIDS)
+#ifdef EC_ENABLE_LID_SWITCH
+		Notify (LID0, 0x80)
+#endif
+	}
+
+	// Lid Open Event
+	Method (_Q02, 0, NotSerialized)
+	{
+		Store ("EC: LID OPEN", Debug)
+		Store (LIDS, \LIDS)
+		Notify (CREC, 0x2)
+#ifdef EC_ENABLE_LID_SWITCH
+		Notify (LID0, 0x80)
+#endif
+	}
+
+	// Power Button
+	Method (_Q03, 0, NotSerialized)
+	{
+		Store ("EC: POWER BUTTON", Debug)
+	}
+
+	// AC Connected
+	Method (_Q04, 0, NotSerialized)
+	{
+		Store ("EC: AC CONNECTED", Debug)
+		Store (ACEX, \PWRS)
+		Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
+		If (CondRefOf (\_SB.DPTF.TCHG)) {
+			Notify (\_SB.DPTF.TCHG, 0x80)
+		}
+#endif
+		\PNOT ()
+	}
+
+	// AC Disconnected
+	Method (_Q05, 0, NotSerialized)
+	{
+		Store ("EC: AC DISCONNECTED", Debug)
+		Store (ACEX, \PWRS)
+		Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
+		If (CondRefOf (\_SB.DPTF.TCHG)) {
+			Notify (\_SB.DPTF.TCHG, 0x80)
+		}
+#endif
+		\PNOT ()
+	}
+
+	// Battery Low Event
+	Method (_Q06, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY LOW", Debug)
+		Notify (BAT0, 0x80)
+	}
+
+	// Battery Critical Event
+	Method (_Q07, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY CRITICAL", Debug)
+		Notify (BAT0, 0x80)
+	}
+
+	// Battery Info Event
+	Method (_Q08, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY INFO", Debug)
+		Notify (BAT0, 0x81)
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+		If (CondRefOf (BAT1)) {
+			Notify (BAT1, 0x81)
+		}
+#endif
+	}
+
+	// Thermal Overload Event
+	Method (_Q0A, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL OVERLOAD", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// Thermal Event
+	Method (_Q0B, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// USB Charger
+	Method (_Q0C, 0, NotSerialized)
+	{
+		Store ("EC: USB CHARGER", Debug)
+	}
+
+	// Key Pressed
+	Method (_Q0D, 0, NotSerialized)
+	{
+		Store ("EC: KEY PRESSED", Debug)
+		Notify (CREC, 0x2)
+	}
+
+	// Thermal Shutdown Imminent
+	Method (_Q10, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL SHUTDOWN", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// Battery Shutdown Imminent
+	Method (_Q11, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY SHUTDOWN", Debug)
+		Notify (BAT0, 0x80)
+	}
+
+	// Throttle Start
+	Method (_Q12, 0, NotSerialized)
+	{
+#ifdef EC_ENABLE_THROTTLING_HANDLER
+		Store ("EC: THROTTLE START", Debug)
+		\_TZ.THRT (1)
+#endif
+	}
+
+	// Throttle Stop
+	Method (_Q13, 0, NotSerialized)
+	{
+#ifdef EC_ENABLE_THROTTLING_HANDLER
+		Store ("EC: THROTTLE STOP", Debug)
+		\_TZ.THRT (0)
+#endif
+	}
+
+#ifdef EC_ENABLE_PD_MCU_DEVICE
+	// PD event
+	Method (_Q16, 0, NotSerialized)
+	{
+		Store ("EC: GOT PD EVENT", Debug)
+		Notify (ECPD, 0x80)
+	}
+#endif
+
+	// Battery Status
+	Method (_Q17, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY STATUS", Debug)
+		Notify (BAT0, 0x80)
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+		If (CondRefOf (BAT1)) {
+			Notify (BAT1, 0x80)
+		}
+#endif
+	}
+
+	// MKBP interrupt.
+	Method (_Q1B, 0, NotSerialized)
+	{
+		Store ("EC: MKBP", Debug)
+		Notify (CREC, 0x80)
+	}
+
+	// TABLET mode switch Event
+	Method (_Q1D, 0, NotSerialized)
+	{
+		Store ("EC: TABLET mode switch Event", Debug)
+		Notify (CREC, 0x2)
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+		\_SB.DPTF.TPET()
+#endif
+#ifdef EC_ENABLE_TBMC_DEVICE
+		Notify (TBMC, 0x80)
+#endif
+	}
+
+	/*
+	 * Dynamic Platform Thermal Framework support
+	 */
+
+	/* Mutex for EC PAT interface */
+	Mutex (PATM, 1)
+
+	/*
+	 * Set Aux Trip Point 0
+	 *   Arg0 = Temp Sensor ID
+	 *   Arg1 = Value to set
+	 */
+	Method (PAT0, 2, Serialized)
+	{
+		If (Acquire (^PATM, 1000)) {
+			Return (0)
+		}
+
+		/* Set sensor ID */
+		Store (ToInteger (Arg0), ^PATI)
+
+		/* Temperature is passed in 1/10 Kelvin */
+		Divide (ToInteger (Arg1), 10, , Local1)
+
+		/* Adjust by EC temperature offset */
+		Subtract (Local1, ^TOFS, ^PATT)
+
+		/* Set commit value with SELECT=0 and ENABLE=1 */
+		Store (0x02, ^PATC)
+
+		Release (^PATM)
+		Return (1)
+	}
+
+	/*
+	 * Set Aux Trip Point 1
+	 *   Arg0 = Temp Sensor ID
+	 *   Arg1 = Value to set
+	 */
+	Method (PAT1, 2, Serialized)
+	{
+		If (Acquire (^PATM, 1000)) {
+			Return (0)
+		}
+
+		/* Set sensor ID */
+		Store (ToInteger (Arg0), ^PATI)
+
+		/* Temperature is passed in 1/10 Kelvin */
+		Divide (ToInteger (Arg1), 10, , Local1)
+
+		/* Adjust by EC temperature offset */
+		Subtract (Local1, ^TOFS, ^PATT)
+
+		/* Set commit value with SELECT=1 and ENABLE=1 */
+		Store (0x03, ^PATC)
+
+		Release (^PATM)
+		Return (1)
+	}
+
+	/* Disable Aux Trip Points
+	 *   Arg0 = Temp Sensor ID
+	 */
+	Method (PATD, 1, Serialized)
+	{
+		If (Acquire (^PATM, 1000)) {
+			Return (0)
+		}
+
+		Store (ToInteger (Arg0), ^PATI)
+		Store (0x00, ^PATT)
+
+		/* Disable PAT0 */
+		Store (0x00, ^PATC)
+
+		/* Disable PAT1 */
+		Store (0x01, ^PATC)
+
+		Release (^PATM)
+		Return (1)
+	}
+
+	/*
+	 * Thermal Threshold Event
+	 */
+	Method (_Q09, 0, NotSerialized)
+	{
+		If (LNot(Acquire (^PATM, 1000))) {
+			/* Read sensor ID for event */
+			Store (^PATI, Local0)
+
+			/* When sensor ID returns 0xFF then no more events */
+			While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT))
+			{
+#ifdef HAVE_THERM_EVENT_HANDLER
+				\_SB.DPTF.TEVT (Local0)
+#endif
+
+				/* Keep reaading sensor ID for event */
+				Store (^PATI, Local0)
+			}
+
+			Release (^PATM)
+		}
+	}
+
+	/*
+	 * Set Charger Current Limit
+	 *   Arg0 = Current Limit in 64mA steps
+	 */
+	Method (CHGS, 1, Serialized)
+	{
+		Store (ToInteger (Arg0), ^CHGL)
+	}
+
+	/*
+	 * Disable Charger Current Limit
+	 */
+	Method (CHGD, 0, Serialized)
+	{
+		Store (0xFF, ^CHGL)
+	}
+
+	/* Read current Tablet mode */
+	Method (RCTM, 0, NotSerialized)
+	{
+		Return (^TBMD)
+	}
+
+	/* Read current Device DPTF Profile Number */
+	Method (RCDP, 0, NotSerialized)
+	{
+		/*
+		 * DDPN = 0 is reserved for backwards compatibility.
+		 * If DDPN == 0 use TBMD to load appropriate DPTF table.
+		 */
+		If (LEqual (^DDPN, 0)) {
+			Return (^TBMD)
+		} Else {
+			Subtract (^DDPN, 1, Local0)
+			Return (Local0)
+		}
+	}
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
+	/*
+	 * Enable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPS, 1, Serialized)
+	{
+		Or (USPP, ShiftLeft (1, Arg0), USPP)
+	}
+
+	/*
+	 * Disable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPC, 1, Serialized)
+	{
+		And (USPP, Not (ShiftLeft (1, Arg0)), USPP)
+	}
+#endif
+
+	#include "ac.asl"
+	#include "battery.asl"
+	#include "cros_ec.asl"
+
+#ifdef EC_ENABLE_ALS_DEVICE
+	#include "als.asl"
+#endif
+
+#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
+	#include "keyboard_backlight.asl"
+#endif
+
+#ifdef EC_ENABLE_PD_MCU_DEVICE
+	#include "pd.asl"
+#endif
+
+#ifdef EC_ENABLE_TBMC_DEVICE
+	#include "tbmc.asl"
+#endif
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/emem.asl b/arch/x86/include/asm/acpi/cros_ec/emem.asl
new file mode 100644
index 0000000..681ca1c
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/emem.asl

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ */
+
+/*
+ * EMEM data may be accessed through port 62/66 or through LPC at 900h.
+ */
+
+Offset (0x00),
+TIN0, 8,	// Temperature 0
+TIN1, 8,	// Temperature 1
+TIN2, 8,	// Temperature 2
+TIN3, 8,	// Temperature 3
+TIN4, 8,	// Temperature 4
+TIN5, 8,	// Temperature 5
+TIN6, 8,	// Temperature 6
+TIN7, 8,	// Temperature 7
+TIN8, 8,	// Temperature 8
+TIN9, 8,	// Temperature 9
+Offset (0x10),
+FAN0, 16,	// Fan Speed 0
+Offset (0x24),
+BTVR, 8,	// Battery structure version
+Offset (0x30),
+LIDS, 1,	// Lid Switch State
+PBTN, 1,	// Power Button Pressed
+WPDI, 1,	// Write Protect Disabled
+RECK, 1,	// Keyboard Initiated Recovery
+RECD, 1,	// Dedicated Recovery Mode
+Offset (0x40),
+BTVO, 32,	// Battery Present Voltage
+BTPR, 32,	// Battery Present Rate
+BTRA, 32,	// Battery Remaining Capacity
+ACEX, 1,	// AC Present
+BTEX, 1,	// Battery Present
+BFDC, 1,	// Battery Discharging
+BFCG, 1,	// Battery Charging
+BFCR, 1,	// Battery Level Critical
+Offset (0x4d),
+BTCN, 8,	// Battery Count
+BTIX, 8,	// Battery index
+Offset (0x50),
+BTDA, 32,	// Battery Design Capacity
+BTDV, 32,	// Battery Design Voltage
+BTDF, 32,	// Battery Last Full Charge Capacity
+BTCC, 32,	// Battery Cycle Count
+BMFG, 64,	// Battery Manufacturer String
+BMOD, 64,	// Battery Model String
+BSER, 64,	// Battery Serial String
+BTYP, 64,	// Battery Type String
+Offset (0x80),
+ALS0, 16,	// ALS reading 0 in lux

diff --git a/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
new file mode 100644
index 0000000..e6edd96
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Google Inc.
+ */
+
+Scope (\_SB)
+{
+	/*
+	 * Chrome EC Keyboard Backlight interface
+	 */
+	Device (KBLT)
+	{
+		Name (_HID, "GOOG0002")
+		Name (_UID, 1)
+
+		/* Ask EC if we even have a backlight
+		 * Return 0xf (present, enabled, show in UI, functioning) or 0
+		 *
+		 * With older EC codebases that don't support the Device
+		 * Features bitfield, this reports the keyboard backlight as
+		 * enabled since reads to undefined addresses in EC address
+		 * space return 0xff and so KBLE will be 1.
+		 */
+		Method (_STA, 0, NotSerialized)
+		{
+			/* If query is unsupported, but this code is compiled
+			 * in, assume the backlight exists physically.
+			 */
+			If (LEqual (1, \_SB.PCI0.LPCB.EC0.DFUD)) {
+				Return (0xf)
+			}
+			/* If EC reports that backlight exists, trust it */
+			If (LEqual (1, \_SB.PCI0.LPCB.EC0.KBLE)) {
+				Return (0xf)
+			}
+			/* Otherwise: no device -> disable */
+			Return (0)
+		}
+
+		/* Read current backlight value */
+		Method (KBQC, 0, NotSerialized)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.KBLV)
+		}
+
+		/* Write new backlight value */
+		Method (KBCM, 1, NotSerialized)
+		{
+			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+		}
+	}
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/pd.asl b/arch/x86/include/asm/acpi/cros_ec/pd.asl
new file mode 100644
index 0000000..e55fde3
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/pd.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Device (ECPD)
+{
+	Name (_HID, "GOOG0003")
+	Name (_UID, 1)
+	Name (_DDN, "EC PD Device")
+	Method(_STA, 0)
+	{
+		Return (0xB)
+	}
+}

diff --git a/arch/x86/include/asm/acpi/cros_ec/superio.asl b/arch/x86/include/asm/acpi/cros_ec/superio.asl
new file mode 100644
index 0000000..7ddab1e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/superio.asl

@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ */
+
+/*
+ * Chrome OS Embedded Controller interface
+ *
+ * Constants that should be defined:
+ *
+ * SIO_EC_MEMMAP_ENABLE     : Enable EC LPC memory map resources
+ * EC_LPC_ADDR_MEMMAP       : Base address of memory map range
+ * EC_MEMMAP_SIZE           : Size of memory map range
+ *
+ * SIO_EC_HOST_ENABLE       : Enable EC host command interface resources
+ * EC_LPC_ADDR_HOST_DATA    : EC host command interface data port
+ * EC_LPC_ADDR_HOST_CMD     : EC host command interface command port
+ * EC_HOST_CMD_REGION0      : EC host command buffer
+ * EC_HOST_CMD_REGION1      : EC host command buffer
+ * EC_HOST_CMD_REGION_SIZE  : EC host command buffer size
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+	Name (_UID, 0)
+	Name (_ADR, 0)
+
+#ifdef SIO_EC_MEMMAP_ENABLE
+	Device (ECMM) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 4)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP,
+			    0x08, EC_MEMMAP_SIZE)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP,
+			    0x08, EC_MEMMAP_SIZE)
+		})
+	}
+#endif
+
+#ifdef SIO_EC_HOST_ENABLE
+	Device (ECUI) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 3)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+			    EC_LPC_ADDR_HOST_DATA, EC_LPC_ADDR_HOST_DATA,
+			    0x01, 0x01)
+			IO (Decode16,
+			    EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_CMD,
+			    0x01, 0x01)
+			IO (Decode16,
+			    EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, 0x08,
+			    EC_HOST_CMD_REGION_SIZE)
+			IO (Decode16,
+			    EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08,
+			    EC_HOST_CMD_REGION_SIZE)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			StartDependentFn (0, 0) {
+				IO (Decode16, EC_LPC_ADDR_HOST_DATA,
+				    EC_LPC_ADDR_HOST_DATA, 0x01, 0x01)
+				IO (Decode16, EC_LPC_ADDR_HOST_CMD,
+				    EC_LPC_ADDR_HOST_CMD, 0x01, 0x01)
+				IO (Decode16,
+				    EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0,
+				    0x08, EC_HOST_CMD_REGION_SIZE)
+				IO (Decode16,
+				    EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1,
+				    0x08, EC_HOST_CMD_REGION_SIZE)
+			}
+			EndDependentFn ()
+		})
+	}
+#endif
+
+#ifdef SIO_EC_ENABLE_COM1
+	Device (COM1) {
+		Name (_HID, EISAID ("PNP0501"))
+		Name (_UID, 1)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+			IRQNoFlags () {4}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			StartDependentFn (0, 0) {
+				IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+				IRQNoFlags () {4}
+			}
+			EndDependentFn ()
+		})
+	}
+#endif
+}
+
+#ifdef SIO_EC_ENABLE_PS2K
+Device (PS2K)		// Keyboard
+{
+	Name (_UID, 0)
+	Name (_HID, "GOOG000A")
+	Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )
+
+	Method (_STA, 0, NotSerialized) {
+		Return (0x0F)
+	}
+
+	Name (_CRS, ResourceTemplate()
+	{
+		IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+		IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+		SIO_EC_PS2K_IRQ
+#else
+		IRQ (Edge, ActiveHigh, Exclusive) {1}
+#endif
+	})
+
+	Name (_PRS, ResourceTemplate()
+	{
+		StartDependentFn (0, 0) {
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+			SIO_EC_PS2K_IRQ
+#else
+			IRQ (Edge, ActiveHigh, Exclusive) {1}
+#endif
+		}
+		EndDependentFn ()
+	})
+}
+#endif

diff --git a/arch/x86/include/asm/acpi/cros_ec/tbmc.asl b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl
new file mode 100644
index 0000000..bfe38d6
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 Google Inc.
+ */
+
+Device (TBMC)
+{
+	Name (_HID, "GOOG0006")
+	Name (_UID, 1)
+	Name (_DDN, "Tablet Motion Control")
+	Method (TBMC)
+	{
+		If (LEqual (^^RCTM, One)) {
+			Return (0x1)
+		} Else {
+			Return (0x0)
+		}
+	}
+	Method(_STA, 0)
+	{
+		Return (0xB)
+	}
+}

diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl b/arch/x86/include/asm/acpi/cros_gnvs.asl
new file mode 100644
index 0000000..c20b645
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_gnvs.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* This is the ChromeOS specific ACPI information needed by
+ * the mainboard's chromeos.asl
+ */
+
+VBT0,   32,	// 0x000 - Boot Reason
+VBT1,   32,	// 0x004 - Active Main Firmware
+VBT2,   32,	// 0x008 - Active EC Firmware
+VBT3,   16,	// 0x00c - CHSW
+VBT4, 2048,	// 0x00e - HWID
+VBT5,  512,	// 0x10e - FWID
+VBT6,  512,	// 0x14e - FRID
+VBT7,   32,	// 0x18e - active main firmware type
+VBT8,   32,	// 0x192 - Recovery Reason
+VBT9,   32,	// 0x196 - FMAP base address
+CHVD, 24576,	// 0x19a - VDAT space filled by verified boot
+VBTA,	32,	// 0xd9a - pointer to smbios FWID
+MEHH,  256,	// 0xd9e - Management Engine Hash
+RMOB,   32,	// 0xdbe - RAM oops base address
+RMOL,   32,	// 0xdc2 - RAM oops length
+ROVP,	32,	// 0xdc6 - pointer to RO_VPD
+ROVL,	32,	// 0xdca - size of RO_VPD
+RWVP,	32,	// 0xdce - pointer to RW_VPD
+RWVL,	32,	// 0xdd2 - size of RW_VPD
+		// 0xdd6

diff --git a/arch/x86/include/asm/acpi/dptf/charger.asl b/arch/x86/include/asm/acpi/dptf/charger.asl
new file mode 100644
index 0000000..7f4a7ec
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/charger.asl

@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TCHG)
+{
+	Name (_HID, "INT3403")
+	Name (_UID, 0)
+	Name (PTYP, 0x0B)
+	Name (_STR, Unicode("Battery Charger"))
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/* Return charger performance states defined by mainboard */
+	Method (PPSS)
+	{
+		Return (\_SB.CHPS)
+	}
+
+	/* Return maximum charger current limit */
+	Method (PPPC)
+	{
+		/* Convert size of PPSS table to index */
+		Store (SizeOf (\_SB.CHPS), Local0)
+		Decrement (Local0)
+
+		/* Check if charging is disabled (AC removed) */
+		If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {
+			/* Return last power state */
+			Return (Local0)
+		} Else {
+			/* Return highest power state */
+			Return (0)
+		}
+
+		Return (0)
+	}
+
+	/* Set charger current limit */
+	Method (SPPC, 1)
+	{
+		/* Retrieve Control (index 4) for specified PPSS level */
+		Store (DeRefOf (Index (DeRefOf (Index
+			(\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+		/* Pass Control value to EC to limit charging */
+		\_SB.PCI0.LPCB.EC0.CHGS (Local0)
+	}
+
+	/* Initialize charger participant */
+	Method (INIT)
+	{
+		/* Disable charge limit */
+		\_SB.PCI0.LPCB.EC0.CHGD ()
+	}
+}

diff --git a/arch/x86/include/asm/acpi/dptf/cpu.asl b/arch/x86/include/asm/acpi/dptf/cpu.asl
new file mode 100644
index 0000000..f77d353
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/cpu.asl

@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+External (\_PR.CP00._PSS, PkgObj)
+External (\_PR.CP00._TSS, PkgObj)
+External (\_PR.CP00._TPC, MethodObj)
+External (\_PR.CP00._PTC, PkgObj)
+External (\_PR.CP00._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
+
+Device (DPTF_CPU_DEVICE)
+{
+	Name(_ADR, DPTF_CPU_ADDR)
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/*
+	 * Processor Throttling Controls
+	 */
+
+	Method (_TSS)
+	{
+		If (CondRefOf (\_PR.CP00._TSS)) {
+			Return (\_PR.CP00._TSS)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 0, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+	Method (_TPC)
+	{
+		If (CondRefOf (\_PR.CP00._TPC)) {
+			Return (\_PR.CP00._TPC)
+		} Else {
+			Return (0)
+		}
+	}
+
+	Method (_PTC)
+	{
+		If (CondRefOf (\_PR.CP00._PTC)) {
+			Return (\_PR.CP00._PTC)
+		} Else {
+			Return (Package ()
+			{
+				Buffer () { 0 },
+				Buffer () { 0 }
+			})
+		}
+	}
+
+	Method (_TSD)
+	{
+		If (CondRefOf (\_PR.CP00._TSD)) {
+			Return (\_PR.CP00._TSD)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 5, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+	Method (_TDL)
+	{
+		If (CondRefOf (\_PR.CP00._TSS)) {
+			Store (SizeOf (\_PR.CP00._TSS), Local0)
+			Decrement (Local0)
+			Return (Local0)
+		} Else {
+			Return (0)
+		}
+	}
+
+	/*
+	 * Processor Performance Control
+	 */
+
+	Method (_PPC)
+	{
+		Return (0)
+	}
+
+	Method (SPPC, 1)
+	{
+		Store (Arg0, \PPCM)
+
+		/* Notify OS to re-read _PPC limit on each CPU */
+		\PPCN ()
+	}
+
+	Method (_PSS)
+	{
+		If (CondRefOf (\_PR.CP00._PSS)) {
+			Return (\_PR.CP00._PSS)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 0, 0, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+
+	Method (_PDL)
+	{
+		/* Check for mainboard specific _PDL override */
+		If (CondRefOf (\_SB.MPDL)) {
+			Return (\_SB.MPDL)
+		} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
+			Store (SizeOf (\_PR.CP00._PSS), Local0)
+			Decrement (Local0)
+			Return (Local0)
+		} Else {
+			Return (0)
+		}
+	}
+
+	/* Return PPCC table defined by mainboard */
+	Method (PPCC)
+	{
+		Return (\_SB.MPPC)
+	}
+
+#ifdef DPTF_CPU_CRITICAL
+	Method (_CRT)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
+	}
+#endif
+
+#ifdef DPTF_CPU_PASSIVE
+	Method (_PSV)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
+	}
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
+	}
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
+	}
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
+	}
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
+	}
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
+	}
+#endif
+}

diff --git a/arch/x86/include/asm/acpi/dptf/dptf.asl b/arch/x86/include/asm/acpi/dptf/dptf.asl
new file mode 100644
index 0000000..5f958d2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/dptf.asl

@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (DPTF)
+{
+	Name (_HID, EISAID ("INT3400"))
+	Name (_UID, 0)
+
+	Name (IDSP, Package()
+	{
+		/* DPPM Passive Policy 1.0 */
+		ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
+
+		/* DPPM Critical Policy */
+		ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
+
+		/* DPPM Cooling Policy */
+		ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+		/* DPPM Active Policy */
+		ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"),
+#endif
+	})
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/*
+	 * Arg0: Buffer containing UUID
+	 * Arg1: Integer containing Revision ID of buffer format
+	 * Arg2: Integer containing count of entries in Arg3
+	 * Arg3: Buffer containing list of DWORD capabilities
+	 * Return: Buffer containing list of DWORD capabilities
+	 */
+	Method (_OSC, 4, Serialized)
+	{
+		/* Check for Passive Policy UUID */
+		If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {
+			/* Initialize Thermal Devices */
+			^TINI ()
+
+#ifdef DPTF_ENABLE_CHARGER
+			/* Initialize Charger Device */
+			^TCHG.INIT ()
+#endif
+		}
+
+		Return (Arg3)
+	}
+
+	/* Priority based _TRT */
+	Name (TRTR, 1)
+
+	Method (_TRT)
+	{
+		Return (\_SB.DTRT)
+	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+	/* _ART : Active Cooling Relationship Table */
+	Method (_ART)
+	{
+		Return (\_SB.DART)
+	}
+#endif
+
+	/* Convert from Degrees C to 1/10 Kelvin for ACPI */
+	Method (CTOK, 1) {
+		/* 10th of Degrees C */
+		Multiply (Arg0, 10, Local0)
+
+		/* Convert to Kelvin */
+		Add (Local0, 2732, Local0)
+
+		Return (Local0)
+	}
+
+	/* Convert from 1/10 Kelvin to Degrees C for ACPI */
+	Method (KTOC, 1) {
+		If (LLessEqual (Arg0, 2732)) {
+			Return (0)
+		}
+
+		/* Convert to Celsius */
+		Subtract (Arg0, 2732, Local0)
+
+		/* Convert from 10th of degrees */
+		Divide (Local0, 10,, Local0)
+
+		Return (Local0)
+	}
+
+	/* Include Thermal Participants */
+	#include "thermal.asl"
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Include Charger Participant */
+	#include "charger.asl"
+#endif
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+	/* Include Fan Participant */
+	#include "fan.asl"
+#endif
+
+}
+
+Scope (\_SB.PCI0)
+{
+	#include "cpu.asl"
+}

diff --git a/arch/x86/include/asm/acpi/dptf/fan.asl b/arch/x86/include/asm/acpi/dptf/fan.asl
new file mode 100644
index 0000000..aa4aa12
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/fan.asl

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TFN1)
+{
+	Name (_HID, "INT3404")
+	Name (_UID, 0)
+	Name (_STR, Unicode("Fan Control"))
+
+	/* _FIF: Fan Information */
+	Name (_FIF, Package ()
+	{
+		0,	// Revision
+		1,	// Fine Grained Control
+		2,	// Step Size
+		0	// No Low Speed Notification
+	})
+
+	/* Return Fan Performance States defined by mainboard */
+	Method (_FPS)
+	{
+		Return (\_SB.DFPS)
+	}
+
+	Name (TFST, Package ()
+	{
+		0,	// Revision
+		0x00,	// Control
+		0x00	// Speed
+	})
+
+	/* _FST: Fan current Status */
+	Method (_FST, 0, Serialized,,PkgObj)
+	{
+		/* Fill in TFST with current control. */
+		Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1))
+		Return (TFST)
+	}
+
+	/* _FSL: Fan Speed Level */
+	Method (_FSL, 1, Serialized)
+	{
+		Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One))
+		{
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}

diff --git a/arch/x86/include/asm/acpi/dptf/thermal.asl b/arch/x86/include/asm/acpi/dptf/thermal.asl
new file mode 100644
index 0000000..4c3c8db
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/thermal.asl

@@ -0,0 +1,521 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+/* Thermal Threshold Event Handler */
+#define HAVE_THERM_EVENT_HANDLER
+Method (TEVT, 1, NotSerialized)
+{
+	Store (ToInteger (Arg0), Local0)
+
+#ifdef DPTF_TSR0_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) {
+		Notify (^TSR0, 0x90)
+	}
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) {
+		Notify (^TSR1, 0x90)
+	}
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) {
+		Notify (^TSR2, 0x90)
+	}
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) {
+		Notify (^TSR3, 0x90)
+	}
+#endif
+}
+
+/* Thermal device initialization - Disable Aux Trip Points */
+Method (TINI)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+	^TSR0.PATD ()
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+	^TSR1.PATD ()
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+	^TSR2.PATD ()
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+	^TSR3.PATD ()
+#endif
+}
+
+/* Thermal Trip Points Change Event Handler */
+Method (TPET)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+	Notify (^TSR0, 0x81)
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+	Notify (^TSR1, 0x81)
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+	Notify (^TSR2, 0x81)
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+	Notify (^TSR3, 0x81)
+#endif
+}
+
+/*
+ * Method to return trip temperature value depending upon the device mode.
+ * Arg0 --> Value to return when device is in tablet mode
+ * Arg1 --> Value to return when device is not in tablet mode.
+ */
+Method (DTRP, 2, Serialized)
+{
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+	If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) {
+		Return (CTOK (Arg0))
+	} Else {
+#endif
+		Return (CTOK (Arg1))
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+	}
+#endif
+}
+
+#ifdef DPTF_TSR0_SENSOR_ID
+
+#ifndef DPTF_TSR0_TABLET_PASSIVE
+#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE
+#endif
+#ifndef DPTF_TSR0_TABLET_CRITICAL
+#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL
+#endif
+
+Device (TSR0)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 1)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR0_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+	}
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR1_SENSOR_ID
+
+#ifndef DPTF_TSR1_TABLET_PASSIVE
+#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE
+#endif
+#ifndef DPTF_TSR1_TABLET_CRITICAL
+#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL
+#endif
+
+Device (TSR1)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 2)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR1_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6))
+	}
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR2_SENSOR_ID
+
+#ifndef DPTF_TSR2_TABLET_PASSIVE
+#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE
+#endif
+#ifndef DPTF_TSR2_TABLET_CRITICAL
+#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL
+#endif
+
+Device (TSR2)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 3)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR2_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR2_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6))
+	}
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR3_SENSOR_ID
+
+#ifndef DPTF_TSR3_TABLET_PASSIVE
+#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE
+#endif
+#ifndef DPTF_TSR3_TABLET_CRITICAL
+#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL
+#endif
+
+Device (TSR3)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 4)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR3_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR3_ACTIVE_AC0
+	Method (_AC0)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC1
+	Method (_AC1)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC2
+	Method (_AC2)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC3
+	Method (_AC3)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC4
+	Method (_AC4)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC5
+	Method (_AC5)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5))
+	}
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC6
+	Method (_AC6)
+	{
+		Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6))
+	}
+#endif
+#endif
+}
+#endif

diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
index d56d35c..4638362 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h

@@ -11,8 +11,11 @@
  * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
  * to declare the GNVS OperationRegion, as well as write_acpi_tables()
  * for the GNVS address runtime fix up.
+ *
+ * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in
+ * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
  */
 #define ACPI_GNVS_ADDR	0xdeadbeef
-#define ACPI_GNVS_SIZE	0x100
+#define ACPI_GNVS_SIZE	0x1000
 
 #endif /* _ACPI_GNVS_H_ */

diff --git a/arch/x86/include/asm/acpi/lpc.asl b/arch/x86/include/asm/acpi/lpc.asl
new file mode 100644
index 0000000..18cc78b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/lpc.asl

@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+/* Intel LPC/eSPI Bus Device  - 0:1f.0 */
+#include <asm/arch/iomap.h>
+
+Device (LPCB)
+{
+	Name (_ADR, 0x001f0000)
+	Name (_DDN, "LPC Bus Device")
+
+	/* DMA Controller */
+	Device (DMAC)
+	{
+		Name (_HID, EISAID("PNP0200"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+		})
+	}
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name (_HID, EISAID ("INT0800"))
+		Name (_DDN, "Firmware Hub")
+		Name (_CRS, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* High Precision Event Timer */
+	Device (HPET)
+	{
+		Name (_HID, EISAID ("PNP0103"))
+		Name (_CID, 0x010CD041)
+		Name (_DDN, "High Precision Event Timer")
+		Name (_CRS, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+		})
+		Method (_STA, 0)
+		{
+			Return (0xF)
+		}
+	}
+
+	/* FPU */
+	Device(MATH)
+	{
+		Name (_HID, EISAID("PNP0C04"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+			IRQNoFlags() { 13 }
+		})
+	}
+
+	/* AT Interrupt Controller */
+	Device (PIC)
+	{
+		Name (_HID, EISAID ("PNP0000"))
+		Name (_DDN, "8259 Interrupt Controller")
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 2)
+		Name (_DDN, "Legacy Device Resources")
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
+			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
+			    0x1, 0xff)
+		})
+	}
+
+	/* Real Time Clock Device */
+	Device (RTC)
+	{
+		Name (_HID, EISAID ("PNP0B00"))
+		Name (_DDN, "Real Time Clock")
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x70, 0x70, 1, 8)
+		})
+	}
+
+	/* Timer */
+	Device (TIMR)
+	{
+		Name (_HID, EISAID ("PNP0100"))
+		Name (_DDN, "8254 Timer")
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags () {0}
+		})
+	}
+}

diff --git a/arch/x86/include/asm/acpi/pci_osc.asl b/arch/x86/include/asm/acpi/pci_osc.asl
new file mode 100644
index 0000000..864556f
--- /dev/null
+++ b/arch/x86/include/asm/acpi/pci_osc.asl

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ */
+
+#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766"
+
+Scope (\_SB.PCI0) {
+	Method (_OSC, 4) {
+		/* Check for proper GUID */
+		If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField (Arg3, 0, CDW1)
+			Or (CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+}

diff --git a/arch/x86/include/asm/acpi/pcr.asl b/arch/x86/include/asm/acpi/pcr.asl
new file mode 100644
index 0000000..f66737b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/pcr.asl

@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ */
+
+#include <intelblocks/pcr.h>
+
+/*
+ * Calculate PCR register base at specified PID
+ * Arg0 - PCR Port ID
+ */
+Method (PCRB, 1, NotSerialized)
+{
+	Return (Add (IOMAP_P2SB_BAR,
+				ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+}
+
+/*
+ * Read a PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ */
+Method (PCRR, 2, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	Return (DATA)
+}
+
+/*
+ * AND a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to AND
+ */
+Method (PCRA, 3, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	And (DATA, Arg2, DATA)
+
+	/*
+	 * After every write one needs to read an innocuous register
+	 * to ensure the writes are completed for certain ports. This is done
+	 * for all ports so that the callers don't need the per-port knowledge
+	 * for each transaction.
+	 */
+	PCRR (Arg0, Arg1)
+}
+
+/*
+ * OR a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to OR
+ */
+Method (PCRO, 3, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	Or (DATA, Arg2, DATA)
+
+	/*
+	 * After every write one needs to read an innocuous register
+	 * to ensure the writes are completed for certain ports. This is done
+	 * for all ports so that the callers don't need the per-port knowledge
+	 * for each transaction.
+	 */
+	PCRR (Arg0, Arg1)
+}

diff --git a/arch/x86/include/asm/acpi/ramoops.asl b/arch/x86/include/asm/acpi/ramoops.asl
new file mode 100644
index 0000000..55939e1
--- /dev/null
+++ b/arch/x86/include/asm/acpi/ramoops.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Scope (\_SB)
+{
+	Device(RMOP)
+	{
+		Name (_HID, "GOOG9999")
+		Name (_CID, "GOOG9999")
+		Name (_UID, 1)
+
+		Name (RBUF, ResourceTemplate()
+		{
+			Memory32Fixed (ReadWrite, 0, 0, MRES)
+		})
+
+		Method (_CRS)
+		{
+			CreateDwordField (^RBUF, ^MRES._BAS, RBAS)
+			CreateDwordField (^RBUF, ^MRES._LEN, RLEN)
+			Store (\RMOB, RBAS)
+			Store (\RMOL, RLEN)
+			Return (^RBUF)
+		}
+		Method(_STA, 0)
+		{
+			Return (0xB)
+		}
+	}
+}

diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl
index 32e16a2..31aa69a 100644
--- a/arch/x86/include/asm/acpi/sleepstates.asl
+++ b/arch/x86/include/asm/acpi/sleepstates.asl

@@ -6,9 +6,11 @@
  * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
  */
 
-Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
-#ifdef CONFIG_HAVE_ACPI_RESUME
-Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+Name(\_S1, Package(){0x1,0x0,0x0,0x0})
+#else
+Name(\_S3, Package(){0x5,0x0,0x0,0x0})
 #endif
-Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
-Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
+Name(\_S4, Package(){0x6,0x0,0x0,0x0})
+Name(\_S5, Package(){0x7,0x0,0x0,0x0})

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 733085c..1b49cca 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h

@@ -9,6 +9,8 @@
 #ifndef __ASM_ACPI_TABLE_H__
 #define __ASM_ACPI_TABLE_H__
 
+#ifndef __ACPI__
+
 struct acpi_facs;
 struct acpi_fadt;
 struct acpi_global_nvs;
@@ -37,6 +39,27 @@
 u32 acpi_fill_csrt(u32 current);
 
 /**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @ctx: Current ACPI context
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_hpet(struct acpi_ctx *ctx);
+
+/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * @return 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+			     uint access_size);
+
+/**
  * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
  *
  * @gnvs: Table to fill in
@@ -55,4 +78,143 @@
  */
 ulong acpi_get_rsdp_addr(void);
 
+/**
+ * arch_read_sci_irq_select() - Read the system-control interrupt number
+ *
+ * @returns value of IRQ register in the PMC
+ */
+int arch_read_sci_irq_select(void);
+
+/**
+ * arch_write_sci_irq_select() - Set the system-control interrupt number
+ *
+ * @scis: New value for IRQ register in the PMC
+ */
+int arch_write_sci_irq_select(uint scis);
+
+/**
+ * arch_madt_sci_irq_polarity() - Return the priority to use for the MADT
+ *
+ * @sci: System-control interrupt number
+ * @return priority to use (MP_IRQ_POLARITY_...)
+ */
+int arch_madt_sci_irq_polarity(int sci);
+
+/**
+ * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU
+ *
+ * See here for the specification
+ * https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf
+ *
+ * @ctx: ACPI context pointer
+ * @flags: (DRHD_INCLUDE_...)
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of remapping hardware register-set for this unit
+ */
+void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
+			   u64 bar);
+
+/**
+ * acpi_create_dmar_rmrr() - Set up an RMRR
+ *
+ * This sets up a Reserved-Memory Region Reporting structure, used to allow
+ * DMA to regions used by devices that the BIOS controls.
+ *
+ * @ctx: ACPI context pointer
+ * @segment: PCI segment asscociated with this unit
+ * @bar: Base address of mapping
+ * @limit: End address of mapping
+ */
+void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
+			   u64 limit);
+
+/**
+ * acpi_dmar_drhd_fixup() - Set the length of an DRHD
+ *
+ * This sets the DRHD length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the DRHD
+ */
+void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_dmar_rmrr_fixup() - Set the length of an RMRR
+ *
+ * This sets the RMRR length field based on the current ctx->current
+ *
+ * @ctx: ACPI context pointer
+ * @base: Address of the start of the RMRR
+ */
+void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base);
+
+/**
+ * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge
+ *
+ * This is used to provide a mapping for a PCI bridge
+ *
+ * @ctx: ACPI context pointer
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 2)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
+			       pci_dev_t bdf);
+
+/**
+ * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET
+ *
+ * Sets up a scope for a High-Precision Event Timer that supports
+ * Message-Signalled Interrupts
+ *
+ * @ctx: ACPI context pointer
+ * @enumeration_id: Enumeration ID (typically 0)
+ * @bdf: PCI device to add
+ * @return length of mapping in bytes
+ */
+int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
+				 pci_dev_t bdf);
+
+/**
+ * acpi_fadt_common() - Handle common parts of filling out an FADT
+ *
+ * This sets up the Fixed ACPI Description Table
+ *
+ * @fadt: Pointer to place to put FADT
+ * @facs: Pointer to the FACS
+ * @dsdt: Pointer to the DSDT
+ */
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt);
+
+/**
+ * intel_acpi_fill_fadt() - Set up the contents of the FADT
+ *
+ * This sets up parts of the Fixed ACPI Description Table that are common to
+ * Intel chips
+ *
+ * @fadt: Pointer to place to put FADT
+ */
+void intel_acpi_fill_fadt(struct acpi_fadt *fadt);
+
+#endif /* !__ACPI__ */
+
 #endif /* __ASM_ACPI_TABLE_H__ */

diff --git a/arch/x86/include/asm/acpigen.h b/arch/x86/include/asm/acpigen.h
new file mode 100644
index 0000000..c531dd6
--- /dev/null
+++ b/arch/x86/include/asm/acpigen.h

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Generation of x86-specific ACPI tables
+ *
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef __ASM_ACPIGEN_H__
+#define __ASM_ACPIGEN_H__
+
+struct acpi_ctx;
+
+/**
+ * acpigen_write_empty_pct() - Write an empty PCT
+ *
+ * See ACPI v6.3 section 8.4.6.1: _PCT (Performance Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_pct(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_empty_ptc() - Write an empty PTC
+ *
+ * See ACPI v6.3 section 8.4.5.1: _PTC (Processor Throttling Control)
+ *
+ * This writes an empty table so that CPU performance works as expected
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx);
+
+#endif /* __ASM_ACPI_H__ */

diff --git a/arch/x86/include/asm/arch-apollolake/acpi.h b/arch/x86/include/asm/arch-apollolake/acpi.h
new file mode 100644
index 0000000..ed852fe
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_ACPI_H
+#define _ASM_ARCH_ACPI_H
+
+struct acpi_ctx;
+
+/**
+ * apl_acpi_fill_dmar() - Set up the DMAR for APL
+ *
+ * @ctx: ACPI context pointer
+ */
+int apl_acpi_fill_dmar(struct acpi_ctx *ctx);
+
+#endif /* _ASM_ARCH_CPU_H */

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
new file mode 100644
index 0000000..4c50bb4
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+#define DPTF_CPU_DEVICE		TCPU
+#define DPTF_CPU_ADDR		0x00000001
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE	80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1	80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2	70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3	60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4	50
+#endif

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
new file mode 100644
index 0000000..7854f7e
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/intel/apollolake/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	PCNT,	8,      // 0x00 - Processor Count
+	PPCM,	8,      // 0x01 - Max PPC State
+	LIDS,	8,      // 0x02 - LID State
+	PWRS,	8,      // 0x03 - AC Power State
+	DPTE,	8,      // 0x04 - Enable DPTF
+	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
+	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
+	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
+	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
+	NHLL,	32,     // 0x21 - 0x24 - NHLT Length
+	PRT0,	32,     // 0x25 - 0x28 - PERST_0 Address
+	SCDP,	8,      // 0x29 - SD_CD GPIO portid
+	SCDO,	8,      // 0x2A - GPIO pad offset relative to the community
+	UIOR,	8,      // 0x2B - UART debug controller init on S3 resume
+	EPCS,   8,      // 0x2C - SGX Enabled status
+	EMNA,   64,     // 0x2D - 0x34 EPC base address
+	ELNG,   64,     // 0x35 - 0x3C EPC Length
+
+	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
+	Offset (0x100),
+	#include <asm/acpi/cros_gnvs.asl>
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
new file mode 100644
index 0000000..b0f8921
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl

@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+#include <asm/arch/gpio.h>
+#include <asm/intel_pinctrl_defs.h>
+// #include <intelblocks/pcr.h>
+// #include <soc/pcr_ids.h>
+#include <asm/arch/iomap.h>
+#include <p2sb.h>
+#include "gpiolib.asl"
+
+scope (\_SB) {
+
+	Device (GPO0)
+	{
+		Name (_HID, GPIO_COMM_NAME)
+		Name (_CID, GPIO_COMM_NAME)
+		Name (_DDN, GPIO_COMM_0_DESC)
+		Name (_UID, 1)
+
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{
+				GPIO_BANK_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+			ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0)
+			Or (IOMAP_P2SB_BAR, Local0, RBAS)
+			Return (^RBUF)
+		}
+
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return(0xf)
+		}
+	}
+
+	Device (GPO1)
+	{
+		Name (_HID, GPIO_COMM_NAME)
+		Name (_CID, GPIO_COMM_NAME)
+		Name (_DDN, GPIO_COMM_1_DESC)
+		Name (_UID, 2)
+
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{
+				GPIO_BANK_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+			ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0)
+			Or (IOMAP_P2SB_BAR, Local0, RBAS)
+			Return (^RBUF)
+		}
+
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return(0xf)
+		}
+	}
+
+	Device (GPO2)
+	{
+		Name (_HID, GPIO_COMM_NAME)
+		Name (_CID, GPIO_COMM_NAME)
+		Name (_DDN, GPIO_COMM_2_DESC)
+		Name (_UID, 3)
+
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{
+				GPIO_BANK_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+			ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0)
+			Or (IOMAP_P2SB_BAR, Local0, RBAS)
+			Return (^RBUF)
+		}
+
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return(0xf)
+		}
+	}
+
+	Device (GPO3)
+	{
+		Name (_HID, GPIO_COMM_NAME)
+		Name (_CID, GPIO_COMM_NAME)
+		Name (_DDN, GPIO_COMM_3_DESC)
+		Name (_UID, 4)
+
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{
+				GPIO_BANK_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+			ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0)
+			Or (IOMAP_P2SB_BAR, Local0, RBAS)
+			Return (^RBUF)
+		}
+
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return(0xf)
+		}
+	}
+
+	Scope(\_SB.PCI0) {
+		/* PERST Assertion
+		 * Note: PERST is Active High
+		 */
+		Method (PRAS, 0x1, Serialized)
+		{
+			/*
+			 * Assert PERST
+			 * local1 - to toggle Tx pin of Dw0
+			 * local2 - Address of PERST
+			 */
+			Store (Arg0, Local2)
+			Store (\_SB.GPC0 (Local2), Local1)
+			Or (Local1, PAD_CFG0_TX_STATE, Local1)
+			\_SB.SPC0 (Local2, Local1)
+		}
+
+		/* PERST DE-Assertion */
+		Method (PRDA, 0x1, Serialized)
+		{
+			/*
+			 * De-assert PERST
+			 * local1 - to toggle Tx pin of Dw0
+			 * local2 - Address of PERST
+			 */
+			Store (Arg0, Local2)
+			Store (\_SB.GPC0 (Local2), Local1)
+			And (Local1, Not (PAD_CFG0_TX_STATE), Local1)
+			\_SB.SPC0 (Local2, Local1)
+		}
+	}
+
+	/*
+	 * Sleep button device ASL code. We are using this device to
+	 * add the _PRW method for a dummy wake event to kernel so that
+	 * before going to sleep kernel does not clear bit 15 in ACPI
+	 * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
+	 */
+	Device (SLP)
+	{
+		Name (_HID, EisaId ("PNP0C0E"))
+
+		Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
+	}
+}
+
+Scope(\_GPE)
+{
+	/*
+	 * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
+	 * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
+	 * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
+	 * GPE0a_EN at 0x430 is reserved.
+	 */
+	Method(_L0F, 0) {}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
new file mode 100644
index 0000000..0eb808d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl

@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Scope (\_SB)
+{
+	/* Get Pad Configuration DW0 register value */
+	Method (GPC0, 0x1, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		Store (Arg0, Local0)
+		OperationRegion (PDW0, SystemMemory, Local0, 4)
+		Field (PDW0, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Return (TEMP)
+	}
+
+	/* Set Pad Configuration DW0 register value */
+	Method (SPC0, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		/* Arg1 - Value for DW0 register */
+		Store (Arg0, Local0)
+		OperationRegion (PDW0, SystemMemory, Local0, 4)
+		Field (PDW0, AnyAcc, NoLock, Preserve) {
+			TEMP,32
+		}
+		Store (Arg1, TEMP)
+	}
+
+	/* Get Pad Configuration DW1 register value */
+	Method (GPC1, 0x1, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		Store (Add (Arg0, 0x4), Local0)
+		OperationRegion (PDW1, SystemMemory, Local0, 4)
+		Field (PDW1, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Return (TEMP)
+	}
+
+	/* Set Pad Configuration DW1 register value */
+	Method (SPC1, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		/* Arg1 - Value for DW1 register */
+		Store (Add (Arg0, 0x4), Local0)
+		OperationRegion (PDW1, SystemMemory, Local0, 4)
+		Field(PDW1, AnyAcc, NoLock, Preserve) {
+			TEMP,32
+		}
+		Store (Arg1, TEMP)
+	}
+
+	/* Get DW0 address of a given pad */
+	Method (GDW0, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO portid */
+		/* Arg1 - GPIO pad offset relative to the community */
+		Store (0, Local1)
+		Or( Or (ShiftLeft (Arg0, 16), IOMAP_P2SB_BAR),
+					Local1, Local1)
+		Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply (
+			GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1)
+		Return (Local1)
+	}
+
+	/* Calculate HOSTSW_REG address */
+	Method (CHSA, 0x1, Serialized)
+	{
+		/* Arg0 - GPIO pad offset relative to the community */
+		Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1)
+		Return (Local1)
+	}
+
+	/* Get Host ownership register of GPIO Community */
+	Method (GHO, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO portid */
+		/* Arg1 - GPIO pad offset relative to the community */
+		Store (CHSA (Arg1), Local1)
+
+		OperationRegion (SHO0, SystemMemory, Or ( Or
+			(IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
+		Field (SHO0, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Return (TEMP)
+	}
+
+	/* Set Host ownership register of GPIO Community */
+	Method (SHO, 0x3, Serialized)
+	{
+		/* Arg0 - GPIO portid */
+		/* Arg1 - GPIO pad offset relative to the community */
+		/* Arg2 - Value for Host own register */
+		Store (CHSA (Arg1), Local1)
+
+		OperationRegion (SHO0, SystemMemory, Or ( Or
+			(IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
+		Field (SHO0, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Store (Arg2, TEMP)
+	}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
new file mode 100644
index 0000000..bc3eabb
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl

@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+
+scope (\_SB.PCI0) {
+
+	/* LPIO1 PWM */
+	Device(PWM) {
+		Name (_ADR, 0x001A0000)
+		Name (_DDN, "Intel(R) PWM Controller")
+	}
+
+	/* LPIO1 HS-UART #1 */
+	Device(URT1) {
+		Name (_ADR, 0x00180000)
+		Name (_DDN, "Intel(R) HS-UART Controller #1")
+	}
+
+	/* LPIO1 HS-UART #2 */
+	Device(URT2) {
+		Name (_ADR, 0x00180001)
+		Name (_DDN, "Intel(R) HS-UART Controller #2")
+	}
+
+	/* LPIO1 HS-UART #3 */
+	Device(URT3) {
+		Name (_ADR, 0x00180002)
+		Name (_DDN, "Intel(R) HS-UART Controller #3")
+	}
+
+	/* LPIO1 HS-UART #4 */
+	Device(URT4) {
+		Name (_ADR, 0x00180003)
+		Name (_DDN, "Intel(R) HS-UART Controller #4")
+	}
+
+	/* LPIO1 SPI */
+	Device(SPI1) {
+		Name (_ADR, 0x00190000)
+		Name (_DDN, "Intel(R) SPI Controller #1")
+	}
+
+	/* LPIO1 SPI #2 */
+	Device(SPI2) {
+		Name (_ADR, 0x00190001)
+		Name (_DDN, "Intel(R) SPI Controller #2")
+	}
+
+	/* LPIO1 SPI #3 */
+	Device(SPI3) {
+		Name (_ADR, 0x00190002)
+		Name (_DDN, "Intel(R) SPI Controller #3")
+	}
+
+
+	/* LPIO2 I2C #0 */
+	Device(I2C0) {
+		Name (_ADR, 0x00160000)
+		Name (_DDN, "Intel(R) I2C Controller #0")
+	}
+
+	/* LPIO2 I2C #1 */
+	Device(I2C1) {
+		Name (_ADR, 0x00160001)
+		Name (_DDN, "Intel(R) I2C Controller #1")
+	}
+
+	/* LPIO2 I2C #2 */
+	Device(I2C2) {
+		Name (_ADR, 0x00160002)
+		Name (_DDN, "Intel(R) I2C Controller #2")
+	}
+
+	/* LPIO2 I2C #3 */
+	Device(I2C3) {
+		Name (_ADR, 0x00160003)
+		Name (_DDN, "Intel(R) I2C Controller #3")
+	}
+
+	/* LPIO2 I2C #4 */
+	Device(I2C4) {
+		Name (_ADR, 0x00170000)
+		Name (_DDN, "Intel(R) I2C Controller #4")
+	}
+
+	/* LPIO2 I2C #5 */
+	Device(I2C5) {
+		Name (_ADR, 0x00170001)
+		Name (_DDN, "Intel(R) I2C Controller #5")
+	}
+
+	/* LPIO2 I2C #6 */
+	Device(I2C6) {
+		Name (_ADR, 0x00170002)
+		Name (_DDN, "Intel(R) I2C Controller #6")
+	}
+
+	/* LPIO2 I2C #7 */
+	Device(I2C7) {
+		Name (_ADR, 0x00170003)
+		Name (_DDN, "Intel(R) I2C Controller #7")
+	}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
new file mode 100644
index 0000000..ff5657a
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+	Name(_BBN, 0)
+
+Device (MCHC)
+{
+	Name (_ADR, 0x00000000)		/*Dev0 Func0 */
+
+		OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+		Field (MCHP, DWordAcc, NoLock, Preserve)
+		{
+			Offset(0x60),
+			MCNF,	32,	/* PCI MMCONF base */
+			Offset (0xA8),
+			TUUD, 64,	/* Top of Upper Used Memory */
+			Offset(0xB4),
+			BGSM,   32,	/* Base of Graphics Stolen Memory */
+			Offset(0xBC),
+			TLUD,   32,	/* Top of Low Useable DRAM */
+		}
+}
+Name (MCRS, ResourceTemplate()
+{
+	/* Bus Numbers */
+	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+			0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
+
+	/* IO Region 0 */
+	DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+			0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
+
+	/* PCI Config Space */
+	Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+	/* IO Region 1 */
+	DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+			0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
+
+	/* VGA memory (0xa0000-0xbffff) */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+			0x00020000,,,)
+
+	/* Data and GFX stolen memory */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
+			0x04200000,,, STOM)
+
+	/*
+	 * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
+	 * This assumes that MMCONF is placed after PCI config space,
+	 * and that no resources are allocated after the MMCONF region.
+	 * This works, sicne MMCONF is hardcoded to 0xe00000000.
+	 */
+	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			NonCacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+			0x00000000,,, PM01)
+
+	/* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
+	QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			NonCacheable, ReadWrite,
+			0x00000000, 0x10000, 0x1ffff, 0x00000000,
+			0x10000,,, PM02)
+})
+
+/* Current Resource Settings */
+Method (_CRS, 0, Serialized)
+{
+
+	/* Find PCI resource area in MCRS */
+	CreateDwordField (MCRS, ^PM01._MIN, PMIN)
+	CreateDwordField (MCRS, ^PM01._MAX, PMAX)
+	CreateDwordField (MCRS, ^PM01._LEN, PLEN)
+
+	/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
+	And(^MCHC.TLUD, 0xFFF00000, PMIN)
+	/* Read MMCONF base */
+	And(^MCHC.MCNF, 0xF0000000, PMAX)
+
+	/* Calculate PCI MMIO Length */
+	Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+	/* Find GFX resource area in GCRS */
+	CreateDwordField(MCRS, ^STOM._MIN, GMIN)
+	CreateDwordField(MCRS, ^STOM._MAX, GMAX)
+	CreateDwordField(MCRS, ^STOM._LEN, GLEN)
+
+	/* Read BGSM */
+	And(^MCHC.BGSM, 0xFFF00000, GMIN)
+
+	/* Read TOLUD */
+	And(^MCHC.TLUD, 0xFFF00000, GMAX)
+	Decrement(GMAX)
+	Add(Subtract(GMAX, GMIN), 1, GLEN)
+
+	/* Patch PM02 range based on Memory Size */
+	CreateQwordField (MCRS, ^PM02._MIN, MMIN)
+	CreateQwordField (MCRS, ^PM02._MAX, MMAX)
+	CreateQwordField (MCRS, ^PM02._LEN, MLEN)
+
+	Store (^MCHC.TUUD, Local0)
+
+	If (LLessEqual (Local0, 0x1000000000))
+	{
+		Store (0, MMIN)
+		Store (0, MLEN)
+	}
+	Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+	Return (MCRS)
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
new file mode 100644
index 0000000..cc3b7a7
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2016 Google Inc.
+ *
+ */
+
+/* Audio Controller - Device 14, Function 0 */
+
+Device (HDAS)
+{
+	Name (_ADR, 0x000E0000)
+	Name (_DDN, "Audio Controller")
+	Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+	/* Device is D3 wake capable */
+	Name (_S0W, 3)
+
+	/* NHLT Table Address populated from GNVS values */
+	Name (NBUF, ResourceTemplate() {
+		QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+			MaxFixed, Cacheable, ReadOnly,
+			0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+		}
+	)
+
+	/* can wake up from S3 state */
+	Name (_PRW, Package() { GPE0A_AVS_PME_STS, 3 })
+
+	/*
+	 * Device Specific Method
+	 * Arg0 - UUID
+	 * Arg1 - Revision
+	 * Arg2 - Function Index
+	*/
+	Method (_DSM, 4) {
+		If (LEqual (Arg0, ^UUID)) {
+			/*
+			 * Function 0: Function Support Query
+			 * Returns a bitmask of functions supported.
+			 */
+			If (LEqual (Arg2, Zero)) {
+				/*
+				 * NHLT Query only supported for revision 1 and
+				 * if NHLT address and length are set in NVS.
+				 */
+				If (LAnd (LEqual (Arg1, One),
+					LAnd (LNotEqual (NHLA, Zero),
+					     LNotEqual (NHLL, Zero)))) {
+					Return (Buffer (One) { 0x03 })
+				}
+				Else {
+					Return (Buffer (One) { 0x01 })
+				}
+			}
+
+			/*
+			 * Function 1: Query NHLT memory address used by
+			 * Intel Offload Engine Driver to discover any non-HDA
+			 * devices that are supported by the DSP.
+			 *
+			 * Returns a pointer to NHLT table in memory.
+			 */
+			If (LEqual (Arg2, One)) {
+				CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+				CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+				CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+				Store (NHLA, NBAS)
+				Store (NHLA, NMAS)
+				Store (NHLL, NLEN)
+				Return (NBUF)
+			}
+		}
+
+		Return (Buffer (One) { 0x00 })
+	}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
new file mode 100644
index 0000000..21a1ca9
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+
+#include "soc_int.asl"
+
+Method(_PRT)
+{
+	Return(Package() {
+
+		Package(){0x0000FFFF, 0, 0, NPK_INT},
+		Package(){0x0000FFFF, 1, 0, PUNIT_INT},
+		Package(){0x0002FFFF, 0, 0, GEN_INT},
+		Package(){0x0003FFFF, 0, 0, IUNIT_INT},
+		Package(){0x000DFFFF, 1, 0, PMC_INT},
+		Package(){0x000EFFFF, 0, 0, AUDIO_INT},
+		Package(){0x000FFFFF, 0, 0, CSE_INT},
+		Package(){0x0011FFFF, 0, 0, ISH_INT},
+		Package(){0x0012FFFF, 0, 0, SATA_INT},
+		Package(){0x0013FFFF, 0, 0, PIRQA_INT},
+		Package(){0x0013FFFF, 1, 0, PIRQB_INT},
+		Package(){0x0013FFFF, 2, 0, PIRQC_INT},
+		Package(){0x0013FFFF, 3, 0, PIRQD_INT},
+		Package(){0x0014FFFF, 0, 0, PIRQB_INT},
+		Package(){0x0014FFFF, 1, 0, PIRQC_INT},
+		Package(){0x0014FFFF, 2, 0, PIRQD_INT},
+		Package(){0x0014FFFF, 3, 0, PIRQA_INT},
+		Package(){0x0015FFFF, 0, 0, XHCI_INT},
+		Package(){0x0015FFFF, 1, 0, XDCI_INT},
+		Package(){0x0016FFFF, 0, 0, I2C0_INT},
+		Package(){0x0016FFFF, 1, 0, I2C1_INT},
+		Package(){0x0016FFFF, 2, 0, I2C2_INT},
+		Package(){0x0016FFFF, 3, 0, I2C3_INT},
+		Package(){0x0017FFFF, 0, 0, I2C4_INT},
+		Package(){0x0017FFFF, 1, 0, I2C5_INT},
+		Package(){0x0017FFFF, 2, 0, I2C6_INT},
+		Package(){0x0017FFFF, 3, 0, I2C7_INT},
+		Package(){0x0018FFFF, 0, 0, UART0_INT},
+		Package(){0x0018FFFF, 1, 0, UART1_INT},
+		Package(){0x0018FFFF, 2, 0, UART2_INT},
+		Package(){0x0018FFFF, 3, 0, UART3_INT},
+		Package(){0x0019FFFF, 0, 0, SPI0_INT},
+		Package(){0x0019FFFF, 1, 0, SPI1_INT},
+		Package(){0x0019FFFF, 2, 0, SPI2_INT},
+		Package(){0x001BFFFF, 0, 0, SDCARD_INT},
+		Package(){0x001CFFFF, 0, 0, EMMC_INT},
+		Package(){0x001EFFFF, 0, 0, SDIO_INT},
+		Package(){0x001FFFFF, 1, 0, SMBUS_INT},
+	})
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
new file mode 100644
index 0000000..ecff59a
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation
+ */
+
+/* PCIe Ports */
+
+Device (RP01)
+{
+	Name (_ADR, 0x00140000)
+	Name (_DDN, "PCIe-B 0")
+
+	#include "pcie_port.asl"
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x00130000)
+	Name (_DDN, "PCIe-A 0")
+
+	#include "pcie_port.asl"
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
new file mode 100644
index 0000000..12a08b4
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl

@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation
+ */
+
+/* Include in each PCIe Root Port device */
+
+/* lowest D-state supported by
+ * PCIe root port during S0 state
+ */
+Name (_S0W, 4)
+
+Name (PDST, 0) /* present Detect status */
+
+/* Dynamic Opregion needed to access registers
+ * when the controller is in D3 cold
+ */
+OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
+Field (PX01, AnyAcc, NoLock, Preserve)
+{
+	Offset(0x5A),
+	, 6,
+	PDS, 1,		/* 6, Presence detect Change */
+	Offset(0xE2),	/* RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,	/* 2, L23_Rdy Entry Request (L23ER) */
+	L23R, 1,	/* 3, L23_Rdy to Detect Transition (L23R2DT) */
+	Offset(0xF4),	/* BLKPLLEN */
+	, 10,
+	BPLL, 1,
+}
+
+OperationRegion (PX02, PCI_Config, 0x338, 0x4)
+Field (PX02, AnyAcc, NoLock, Preserve)
+{
+	, 26,
+	BDQA, 1		/* BLKDQDA */
+}
+
+PowerResource (PXP, 0, 0)
+{
+	/* Define the PowerResource for PCIe slot */
+	Method (_STA, 0, Serialized)
+	{
+		Store (PDS, PDST)
+		If (LEqual (PDS, 1)) {
+			Return (0xf)
+		} Else {
+			Return (0)
+		}
+	}
+
+	Method (_ON, 0, Serialized)
+	{
+		If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+			/* Enter this condition if device
+			 * is connected
+			 */
+
+			/* De-assert PERST */
+			\_SB.PCI0.PRDA (\PRT0)
+
+			Store (0, BDQA) /* Set BLKDQDA to 0 */
+			Store (0, BPLL) /* Set BLKPLLEN to 0 */
+
+			/* Set L23_Rdy to Detect Transition
+			 * (L23R2DT)
+			 */
+			Store (1, L23R)
+			Sleep (16)
+			Store (0, Local0)
+
+			/* Delay for transition Detect
+			 * and link to train
+			 */
+			While (L23R) {
+				If (Lgreater (Local0, 4)) {
+					Break
+				}
+				Sleep (16)
+				Increment (Local0)
+			}
+		} /* End PDS condition check */
+	}
+
+	Method (_OFF, 0, Serialized)
+	{
+		/* Set L23_Rdy Entry Request (L23ER) */
+		If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+			/* enter this condition if device
+			 * is connected
+			 */
+			Store (1, L23E)
+			Sleep (16)
+			Store (0, Local0)
+			While (L23E) {
+				If (Lgreater (Local0, 4)) {
+					Break
+				}
+				Sleep (16)
+				Increment (Local0)
+			}
+			Store (1, BDQA) /* Set BLKDQDA to 1 */
+			Store (1, BPLL) /* Set BLKPLLEN to 1 */
+
+			/* Assert PERST */
+			\_SB.PCI0.PRAS (\PRT0)
+		} /* End PDS condition check */
+	} /* End of Method_OFF */
+} /* End PXP */
+
+Name(_PR0, Package() { PXP })
+Name(_PR3, Package() { PXP })

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/platform.asl b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl
new file mode 100644
index 0000000..b631a9f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2016 Intel Corp
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <soc/intel/common/acpi/platform.asl>

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..4a59283
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ */
+
+#include <asm/arch/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+#define PMIO_LIMIT 0x480
+
+scope (\_SB) {
+	Device (IPC1)
+	{
+		Name (_HID, "INT34D2")
+		Name (_CID, "INT34D2")
+		Name (_DDN, "Intel(R) IPC1 Controller")
+		Name (RBUF, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
+			Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
+			Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
+			IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT,
+			      0x04, PMIO_LENGTH)
+			Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+			{
+			      PMC_INT
+			}
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+			Store (PMC_BAR0, IBAS)
+
+			CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+			Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
+			CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+			Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
+
+			CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+			Store (SRAM_BASE_0, SBAS)
+
+			Return (^RBUF)
+		}
+	}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/scs.asl b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl
new file mode 100644
index 0000000..7d61861
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl

@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Scope (\_SB.PCI0) {
+	/* 0xD6- is the port address */
+	/* 0x600- is the dynamic clock gating control register offset (GENR) */
+	OperationRegion (SBMM, SystemMemory,
+		Or ( Or (IOMAP_P2SB_BAR,
+			ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
+	Field (SBMM, DWordAcc, NoLock, Preserve)
+	{
+		GENR, 32,
+		Offset (0x08),
+		,  5, /* bit[5] represents Force Card Detect SD Card */
+		GRR3,  1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */
+	}
+
+	/* SCC power gate control method, this method must be serialized as
+	 * multiple device will control the GENR register
+	 *
+	 * Arguments: (2)
+	 * Arg0: 0-AND  1-OR
+	 * Arg1: Value
+	 */
+	Method (SCPG, 2, Serialized)
+	{
+		if (LEqual(Arg0, 0x1)) {
+			Or (^GENR, Arg1, ^GENR)
+		} ElseIf (LEqual(Arg0, 0x0)){
+			And (^GENR, Arg1, ^GENR)
+		}
+	}
+
+	/* eMMC */
+	Device (SDHA) {
+		Name (_ADR, 0x001C0000)
+		Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+		Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+
+		/*
+		 * Device Specific Method
+		 * Arg0 - UUID
+		 * Arg1 - Revision
+		 * Arg2 - Function Index
+		 */
+		Method (_DSM, 4)
+		{
+			If (LEqual (Arg0, ^UUID)) {
+				/*
+				 * Function 9: Device Readiness Durations
+				 * Returns a package of five integers covering
+				 * various device related delays in PCIe Base Spec.
+				 */
+				If (LEqual (Arg2, 9)) {
+					/*
+					 * Function 9 support for revision 3.
+					 * ECN link for function definitions
+					 * [https://pcisig.com/sites/default/files/
+					 * specification_documents/
+					 * ECN_fw_latency_optimization_final.pdf]
+					 */
+					If (LEqual (Arg1, 3)) {
+						/*
+						 * Integer 0: FW reset time.
+						 * Integer 1: FW data link up time.
+						 * Integer 2: FW functional level reset
+						 * time.
+						 * Integer 3: FW D3 hot to D0 time.
+						 * Integer 4: FW VF enable time.
+						 * set ACPI constant Ones for elements
+						 * where overriding the default value
+						 * is not desired.
+						 */
+						Return (Package (5) {0, Ones, Ones,
+									    Ones, Ones})
+					}
+				}
+			}
+			Return (Buffer() { 0x00 })
+		}
+
+		Method (_PS0, 0, NotSerialized)
+		{
+			/* Clear clock gate
+			 * Clear bit 6 and 0
+			 */
+			^^SCPG(0,0xFFFFFFBE)
+			/* Sleep 2 ms */
+			Sleep (2)
+		}
+
+		Method (_PS3, 0, NotSerialized)
+		{
+			/* Enable power gate
+			 * Restore clock gate
+			 * Restore bit 6 and 0
+			 */
+			^^SCPG(1,0x00000041)
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (0)
+			}
+		}
+	} /* Device (SDHA) */
+
+	/* SD CARD */
+	Device (SDCD)
+	{
+		Name (_ADR, 0x001B0000)
+		Name (_S0W, 4) /* _S0W: S0 Device Wake State */
+		Name (SCD0, 0) /* Store SD_CD DW0 address */
+
+		/* Set the host ownership of sdcard cd during kernel boot */
+		Method (_INI, 0)
+		{
+			/* Check SDCard CD port is valid */
+			If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
+			{
+				/* Store DW0 address of SD_CD */
+				Store (GDW0 (\SCDP, \SCDO), SCD0)
+				/* Get the current SD_CD ownership */
+				Store (\_SB.GHO (\SCDP, \SCDO), Local0)
+				/* Set host ownership as GPIO in HOSTSW_OWN reg */
+				Or (Local0, ShiftLeft (1,  Mod (\SCDO, 32)), Local0)
+				\_SB.SHO (\SCDP, \SCDO, Local0)
+			}
+		}
+
+		Method (_PS0, 0, NotSerialized)
+		{
+			/* Check SDCard CD port is valid */
+			If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
+			{
+				/* Store DW0 into local0 to get rxstate of GPIO */
+				Store (\_SB.GPC0 (SCD0), Local0)
+				/* Extract rxstate [bit 1] of sdcard card detect pin */
+				And (Local0, PAD_CFG0_RX_STATE, Local0)
+				/* If the sdcard is present, rxstate is low.
+				 * If sdcard is not present, rxstate is High.
+				 * Write the inverted value of rxstate to GRR3.
+				 */
+				If (LEqual (Local0, 0)) {
+					Store (1, ^^GRR3)
+				} Else {
+					Store (0, ^^GRR3)
+				}
+				Sleep (2)
+			}
+		}
+
+		Method (_PS3, 0, NotSerialized)
+		{
+			/* Clear GRR3 to Power Gate SD Controller */
+			Store (0, ^^GRR3)
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (1)
+			}
+		}
+	} /* Device (SDCD) */
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
new file mode 100644
index 0000000..df2fafb
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+
+#ifndef _SOC_INT_DEFINE_ASL_
+#define _SOC_INT_DEFINE_ASL_
+
+#define SDCARD_INT	3	/* Need to be shared by PMC and SCC only*/
+#define UART0_INT	4	/* Need to be shared by PMC and SCC only*/
+#define UART1_INT	5	/* Need to be shared by PMC and SCC only*/
+#define UART2_INT	6	/* Need to be shared by PMC and SCC only*/
+#define UART3_INT	7	/* Need to be shared by PMC and SCC only*/
+#define XDCI_INT	13	/* Need to be shared by PMC and SCC only*/
+#define GPIO_BANK_INT	14
+#define NPK_INT		16
+#define PIRQA_INT	16
+#define PIRQB_INT	17
+#define PIRQC_INT	18
+#define SATA_INT	19
+#define GEN_INT		19
+#define PIRQD_INT	19
+#define XHCI_INT	17	/* Need to be shared by PMC and SCC only*/
+#define SMBUS_INT	20	/* PIRQE */
+#define CSE_INT		20	/* PIRQE */
+#define IUNIT_INT	21	/* PIRQF */
+#define PIRQF_INT	21
+#define PIRQG_INT	22
+#define PUNIT_INT	24
+#define AUDIO_INT	25
+#define ISH_INT		26
+#define I2C0_INT	27
+#define I2C1_INT	28
+#define I2C2_INT	29
+#define I2C3_INT	30
+#define I2C4_INT	31
+#define I2C5_INT	32
+#define I2C6_INT	33
+#define I2C7_INT	34
+#define SPI0_INT	35
+#define SPI1_INT	36
+#define SPI2_INT	37
+#define UFS_INT		38
+#define EMMC_INT	39
+#define PMC_INT		40
+#define SDIO_INT	42
+#define CNVI_INT	44
+
+#endif	/* _SOC_INT_DEFINE_ASL_ */

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
new file mode 100644
index 0000000..0829019
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ */
+
+#include <p2sb.h>
+#include <asm/arch/gpe.h>
+
+/* PCIE device */
+#include "pcie.asl"
+
+/* LPSS device */
+#include "lpss.asl"
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
+
+#include "xhci.asl"
+
+/* LPC */
+#include <asm/acpi/lpc.asl>
+
+/* eMMC */
+#include "scs.asl"
+
+/* PMC IPC controller */
+#include "pmc_ipc.asl"
+
+/* PCI _OSC */
+#include <asm/acpi/pci_osc.asl>

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
new file mode 100644
index 0000000..6333126
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+/* XHCI Controller 0:15.0 */
+Device (XHCI) {
+	Name (_ADR, 0x00150000)  /* Device 21, Function 0 */
+
+	Name (_S3D, 3)  /* D3 supported in S3 */
+	Name (_S0W, 3)  /* D3 can wake device in S0 */
+	Name (_S3W, 3)  /* D3 can wake system from S3 */
+
+	/* Declare XHCI GPE status and enable bits are bit 13 */
+	Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 })
+
+	Method (_STA, 0)
+	{
+		Return (0xF)
+	}
+
+	Device (RHUB)
+	{
+		/* Root Hub */
+		Name (_ADR, Zero)
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "xhci_glk_ports.asl"
+#else
+#include "xhci_apl_ports.asl"
+#endif
+	}
+}

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
new file mode 100644
index 0000000..3ab7d18
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 9) }
+Device (SS02) { Name (_ADR, 10) }
+Device (SS03) { Name (_ADR, 11) }
+Device (SS04) { Name (_ADR, 12) }
+Device (SS05) { Name (_ADR, 13) }
+Device (SS06) { Name (_ADR, 14) }

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
new file mode 100644
index 0000000..1922672
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+Device (HS09) { Name (_ADR, 9) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 10) }
+Device (SS02) { Name (_ADR, 11) }
+Device (SS03) { Name (_ADR, 12) }
+Device (SS04) { Name (_ADR, 13) }
+Device (SS05) { Name (_ADR, 14) }
+Device (SS06) { Name (_ADR, 15) }

diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h
index fe62194..ef8eb22 100644
--- a/arch/x86/include/asm/arch-apollolake/global_nvs.h
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h

@@ -10,27 +10,6 @@
 #ifndef _GLOBAL_NVS_H_
 #define _GLOBAL_NVS_H_
 
-struct __packed acpi_global_nvs {
-	/* Miscellaneous */
-	u8	pcnt; /* 0x00 - Processor Count */
-	u8	ppcm; /* 0x01 - Max PPC State */
-	u8	lids; /* 0x02 - LID State */
-	u8	pwrs; /* 0x03 - AC Power State */
-	u8	dpte; /* 0x04 - Enable DPTF */
-	u32	cbmc; /* 0x05 - 0x08 - U-Boot Console */
-	u64	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
-	u64	gpei; /* 0x11 - 0x18 - GPE Wake Source */
-	u64	nhla; /* 0x19 - 0x20 - NHLT Address */
-	u32	nhll; /* 0x21 - 0x24 - NHLT Length */
-	u32	prt0; /* 0x25 - 0x28 - PERST_0 Address */
-	u8	scdp; /* 0x29 - SD_CD GPIO portid */
-	u8	scdo; /* 0x2a - GPIO pad offset relative to the community */
-	u8	uior; /* 0x2b - UART debug controller init on S3 resume */
-	u8	ecps; /* 0x2c - SGX Enabled status */
-	u64	emna; /* 0x2d - 0x34 EPC base address */
-	u64	elng; /* 0x35 - 0x3c EPC Length */
-	u8	unused1[0x100 - 0x3d];		/* Pad out to 256 bytes */
-	u8	unused2[0x1000 - 0x100];	/* Pad out to 4096 bytes */
-};
+#include <asm/intel_gnvs.h>
 
 #endif /* _GLOBAL_NVS_H_ */

diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h
new file mode 100644
index 0000000..f579296
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/gpe.h

@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Intel Corporation
+ * Copyright 2020 Google LLC
+ *
+ * Taken from coreboot apl gpe.h
+ */
+
+#ifndef _ASM_ARCH_GPE_H_
+#define _ASM_ARCH_GPE_H_
+
+/* bit position in GPE0a_STS register */
+#define GPE0A_PCIE_SCI_STS		0
+#define GPE0A_SWGPE_STS			2
+#define GPE0A_PCIE_WAKE0_STS		3
+#define GPE0A_PUNIT_SCI_STS		4
+#define GPE0A_PCIE_WAKE1_STS		6
+#define GPE0A_PCIE_WAKE2_STS		7
+#define GPE0A_PCIE_WAKE3_STS		8
+#define GPE0A_PCIE_GPE_STS		9
+#define GPE0A_BATLOW_STS		10
+#define GPE0A_CSE_PME_STS		11
+#define GPE0A_XDCI_PME_STS		12
+#define GPE0A_XHCI_PME_STS		13
+#define GPE0A_AVS_PME_STS		14
+#define GPE0A_GPIO_TIER1_SCI_STS	15
+#define GPE0A_SMB_WAK_STS		16
+#define GPE0A_SATA_PME_STS		17
+#define GPE0A_CNVI_PME_STS	        18
+
+/* Group DW0 is reserved in Apollolake */
+
+/* GPE_63_32 */
+#define GPE0_DW1_00		32
+#define GPE0_DW1_01		33
+#define GPE0_DW1_02		34
+#define GPE0_DW1_03		36
+#define GPE0_DW1_04		36
+#define GPE0_DW1_05		37
+#define GPE0_DW1_06		38
+#define GPE0_DW1_07		39
+#define GPE0_DW1_08		40
+#define GPE0_DW1_09		41
+#define GPE0_DW1_10		42
+#define GPE0_DW1_11		43
+#define GPE0_DW1_12		44
+#define GPE0_DW1_13		45
+#define GPE0_DW1_14		46
+#define GPE0_DW1_15		47
+#define GPE0_DW1_16		48
+#define GPE0_DW1_17		49
+#define GPE0_DW1_18		50
+#define GPE0_DW1_19		51
+#define GPE0_DW1_20		52
+#define GPE0_DW1_21		53
+#define GPE0_DW1_22		54
+#define GPE0_DW1_23		55
+#define GPE0_DW1_24		56
+#define GPE0_DW1_25		57
+#define GPE0_DW1_26		58
+#define GPE0_DW1_27		59
+#define GPE0_DW1_28		60
+#define GPE0_DW1_29		61
+#define GPE0_DW1_30		62
+#define GPE0_DW1_31		63
+/* GPE_95_64 */
+#define GPE0_DW2_00		64
+#define GPE0_DW2_01		65
+#define GPE0_DW2_02		66
+#define GPE0_DW2_03		67
+#define GPE0_DW2_04		68
+#define GPE0_DW2_05		69
+#define GPE0_DW2_06		70
+#define GPE0_DW2_07		71
+#define GPE0_DW2_08		72
+#define GPE0_DW2_09		73
+#define GPE0_DW2_10		74
+#define GPE0_DW2_11		75
+#define GPE0_DW2_12		76
+#define GPE0_DW2_13		77
+#define GPE0_DW2_14		78
+#define GPE0_DW2_15		79
+#define GPE0_DW2_16		80
+#define GPE0_DW2_17		81
+#define GPE0_DW2_18		82
+#define GPE0_DW2_19		83
+#define GPE0_DW2_20		84
+#define GPE0_DW2_21		85
+#define GPE0_DW2_22		86
+#define GPE0_DW2_23		87
+#define GPE0_DW2_24		88
+#define GPE0_DW2_25		89
+#define GPE0_DW2_26		90
+#define GPE0_DW2_27		91
+#define GPE0_DW2_28		92
+#define GPE0_DW2_29		93
+#define GPE0_DW2_30		94
+#define GPE0_DW2_31		95
+/* GPE_127_96 */
+#define GPE0_DW3_00		96
+#define GPE0_DW3_01		97
+#define GPE0_DW3_02		98
+#define GPE0_DW3_03		99
+#define GPE0_DW3_04		100
+#define GPE0_DW3_05		101
+#define GPE0_DW3_06		102
+#define GPE0_DW3_07		103
+#define GPE0_DW3_08		104
+#define GPE0_DW3_09		105
+#define GPE0_DW3_10		106
+#define GPE0_DW3_11		107
+#define GPE0_DW3_12		108
+#define GPE0_DW3_13		109
+#define GPE0_DW3_14		110
+#define GPE0_DW3_15		111
+#define GPE0_DW3_16		112
+#define GPE0_DW3_17		113
+#define GPE0_DW3_18		114
+#define GPE0_DW3_19		115
+#define GPE0_DW3_20		116
+#define GPE0_DW3_21		117
+#define GPE0_DW3_22		118
+#define GPE0_DW3_23		119
+#define GPE0_DW3_24		120
+#define GPE0_DW3_25		121
+#define GPE0_DW3_26		122
+#define GPE0_DW3_27		123
+#define GPE0_DW3_28		124
+#define GPE0_DW3_29		125
+#define GPE0_DW3_30		126
+#define GPE0_DW3_31		127
+
+#define GPE_MAX			GPE0_DW3_31
+
+#endif

diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
index 10879c1..ab5860c 100644
--- a/arch/x86/include/asm/arch-apollolake/gpio.h
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h

@@ -482,4 +482,7 @@
 #define GPIO_72_IRQ			0x65
 #define GPIO_73_IRQ			0x66
 
+/* This is needed by ACPI */
+#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+
 #endif /* _ASM_ARCH_GPIO_H_ */

diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
index 4ce1017..21c5f33 100644
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h

@@ -11,11 +11,27 @@
 
 /* Put p2sb at 0xd0000000 in TPL */
 #define IOMAP_P2SB_BAR		0xd0000000
+#define IOMAP_P2SB_SIZE		0x10000000
 
 #define IOMAP_SPI_BASE		0xfe010000
 
 #define IOMAP_ACPI_BASE		0x400
 #define IOMAP_ACPI_SIZE		0x100
+#define ACPI_BASE_ADDRESS	IOMAP_ACPI_BASE
+
+#define PMC_BAR0		0xfe042000
+
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_SIZE		0x8000
+
+#ifdef __ACPI__
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define SRAM_BASE_0		0xfe900000
+#define SRAM_SIZE_0		(8 * KiB)
+#define SRAM_BASE_2		0xfe902000
+#define SRAM_SIZE_2		(4 * KiB)
+#endif
 
 /*
  * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial

diff --git a/arch/x86/include/asm/arch-apollolake/pm.h b/arch/x86/include/asm/arch-apollolake/pm.h
index 6718290..9a8d971 100644
--- a/arch/x86/include/asm/arch-apollolake/pm.h
+++ b/arch/x86/include/asm/arch-apollolake/pm.h

@@ -1,12 +1,15 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015-2016 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ * Copyright 2019 Google LLC
  */
 
 #ifndef _ASM_ARCH_PM_H
 #define _ASM_ARCH_PM_H
 
+#include <power/acpi_pmc.h>
+
 #define PMC_GPE_SW_31_0	0
 #define PMC_GPE_SW_63_32	1
 #define PMC_GPE_NW_31_0	3
@@ -16,4 +19,39 @@
 #define PMC_GPE_N_63_32	7
 #define PMC_GPE_W_31_0		9
 
+#define IRQ_REG			0x106c
+#define SCI_IRQ_SHIFT		24
+#define SCI_IRQ_MASK		(0xff << SCI_IRQ_SHIFT)
+#define SCIS_IRQ9		9
+#define SCIS_IRQ10		10
+#define SCIS_IRQ11		11
+#define SCIS_IRQ20		20
+#define SCIS_IRQ21		21
+#define SCIS_IRQ22		22
+#define SCIS_IRQ23		23
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES		8
+#define PSS_RATIO_STEP		2
+#define PSS_LATENCY_TRANSITION	10
+#define PSS_LATENCY_BUSMASTER	10
+
+#ifndef __ASSEMBLY__
+/* Track power state from reset to log events */
+struct __packed chipset_power_state {
+	u16 pm1_sts;
+	u16 pm1_en;
+	u32 pm1_cnt;
+	u32 gpe0_sts[GPE0_REG_MAX];
+	u32 gpe0_en[GPE0_REG_MAX];
+	u16 tco1_sts;
+	u16 tco2_sts;
+	u32 prsts;
+	u32 gen_pmcon1;
+	u32 gen_pmcon2;
+	u32 gen_pmcon3;
+	u32 prev_sleep_state;
+};
+#endif /* !__ASSEMBLY__ */
+
 #endif

diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h
index 9e7bd62..788a63d 100644
--- a/arch/x86/include/asm/arch-apollolake/systemagent.h
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h

@@ -35,4 +35,35 @@
  */
 void enable_bios_reset_cpl(void);
 
+/**
+ * sa_get_tolud_base() - Get the TOLUD base address
+ *
+ * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM
+ * below 4GB
+ *
+ * @dev: hostbridge device
+ * @return TOLUD address
+ */
+ulong sa_get_tolud_base(struct udevice *dev);
+
+/**
+ * sa_get_gsm_base() - Get the GSM base address
+ *
+ * This returns the base of GTT Stolen Memory, marking the start of memory used
+ * for Graphics Translation Tables.
+ *
+ * @dev: hostbridge device
+ * @return GSM address
+ */
+ulong sa_get_gsm_base(struct udevice *dev);
+
+/**
+ * sa_get_tseg_base() - Get the TSEG base address
+ *
+ * This returns the top address of DRAM available below 4GB
+ *
+ * @return TSEG base
+ */
+ulong sa_get_tseg_base(struct udevice *dev);
+
 #endif

diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index d961ddd..7a3c1f5 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h

@@ -24,6 +24,11 @@
 	__u8 data[0];
 };
 
+/**
+ * struct setup_header - Information needed by Linux to boot
+ *
+ * See https://www.kernel.org/doc/html/latest/x86/boot.html
+ */
 struct setup_header {
 	__u8	setup_sects;
 	__u16	root_flags;
@@ -43,15 +48,16 @@
 	__u16	kernel_version;
 	__u8	type_of_loader;
 	__u8	loadflags;
-#define LOADED_HIGH	(1<<0)
-#define QUIET_FLAG	(1<<5)
-#define KEEP_SEGMENTS	(1<<6)
-#define CAN_USE_HEAP	(1<<7)
+#define LOADED_HIGH	BIT(0)
+#define KASLR_FLAG	BIT(1)
+#define QUIET_FLAG	BIT(5)
+#define KEEP_SEGMENTS	BIT(6)		/* Obsolete */
+#define CAN_USE_HEAP	BIT(7)
 	__u16	setup_move_size;
 	__u32	code32_start;
 	__u32	ramdisk_image;
 	__u32	ramdisk_size;
-	__u32	bootsect_kludge;
+	__u32	bootsect_kludge;	/* Obsolete */
 	__u16	heap_end_ptr;
 	__u8	ext_loader_ver;
 	__u8	ext_loader_type;
@@ -59,7 +65,13 @@
 	__u32	initrd_addr_max;
 	__u32	kernel_alignment;
 	__u8	relocatable_kernel;
-	__u8	_pad2[3];
+	u8	min_alignment;
+#define XLF_KERNEL_64			BIT(0)
+#define XLF_CAN_BE_LOADED_ABOVE_4G	BIT(1)
+#define XLF_EFI_HANDOVER_32		BIT(2)
+#define XLF_EFI_HANDOVER_64		BIT(3)
+#define XLF_EFI_KEXEC			BIT(4)
+	u16	xloadflags;
 	__u32	cmdline_size;
 	__u32	hardware_subarch;
 	__u64	hardware_subarch_data;
@@ -69,6 +81,7 @@
 	__u64	pref_address;
 	__u32	init_size;
 	__u32	handover_offset;
+	u32	kernel_info_offset;
 } __attribute__((packed));
 
 struct sys_desc_table {

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05da..5b001bb 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h

@@ -288,4 +288,13 @@
  */
 u32 cpu_get_stepping(void);
 
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
 #endif

diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h
index cdd99a9..48f56c2 100644
--- a/arch/x86/include/asm/cpu_common.h
+++ b/arch/x86/include/asm/cpu_common.h

@@ -128,4 +128,60 @@
  */
 void cpu_set_p_state_to_turbo_ratio(void);
 
+/**
+ * cpu_get_coord_type() - Get the type of coordination for P-State transition
+ *
+ * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency)
+ *
+ * @return HW_ALL (always)
+ */
+int cpu_get_coord_type(void);
+
+/**
+ * cpu_get_min_ratio() - get minimum support frequency ratio for CPU
+ *
+ * @return minimum ratio
+ */
+int cpu_get_min_ratio(void);
+
+/**
+ * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio
+ *
+ * If a nominal TDP ratio is available, it is returned. Otherwise this returns
+ * the  maximum non-turbo frequency ratio for this processor
+ *
+ * @return max ratio
+ */
+int cpu_get_max_ratio(void);
+
+/**
+ * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz
+ *
+ * This is the value the clock ratio is multiplied with
+ *
+ * @return bus-block frequency in KHz
+ */
+int cpu_get_bus_clock_khz(void);
+
+/**
+ * cpu_get_power_max() - Get maximum CPU TDP
+ *
+ * @return maximum CPU TDP (Thermal-design power) in mW
+ */
+int cpu_get_power_max(void);
+
+/**
+ * cpu_get_max_turbo_ratio() - Get maximum turbo ratio
+ *
+ * @return maximum ratio
+ */
+int cpu_get_max_turbo_ratio(void);
+
+/**
+ * cpu_get_cores_per_package() - Get the number of CPU cores in each package
+ *
+ * @return number of cores
+ */
+int cpu_get_cores_per_package(void);
+
 #endif

diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 9d29f82..a66c0d2 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h

@@ -8,6 +8,7 @@
 #define E820_ACPI	3
 #define E820_NVS	4
 #define E820_UNUSABLE	5
+#define E820_COUNT	6	/* Number of types */
 
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
@@ -21,10 +22,9 @@
 #define ISA_START_ADDRESS	0xa0000
 #define ISA_END_ADDRESS		0x100000
 
-#endif /* __ASSEMBLY__ */
-
 /* Implementation defined function to install an e820 map */
 unsigned int install_e820_map(unsigned int max_entries,
 			      struct e820_entry *);
+#endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_X86_E820_H */

diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index 4941e2d..3a9b619 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h

@@ -10,9 +10,18 @@
 
 enum fsp_phase {
 	/* Notification code for post PCI enuermation */
-	INIT_PHASE_PCI	= 0x20,
-	/* Notification code before transferring control to the payload */
-	INIT_PHASE_BOOT	= 0x40
+	INIT_PHASE_PCI		= 0x20,
+	/*
+	 * Notification code before transferring control to the payload.
+	 * This is issued at the end of init before starting main(), i.e.
+	 * the command line / boot script.
+	 */
+	INIT_PHASE_BOOT		= 0x40,
+	/*
+	 * Notification code before existing boot services. This is issued
+	 * just before removing devices and booting the kernel.
+	 */
+	INIT_PHASE_END_FIRMWARE	= 0xf0,
 };
 
 struct fsp_notify_params {

diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index d248520..ea3983e 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h

@@ -99,4 +99,29 @@
 	EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
 		0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
 
+/* The following GUIDs are observed with FSP 2.1 / Apollo Lake */
+#define FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID \
+	EFI_GUID(0x6dadf1d1, 0xd4cc, 0x4910, \
+		0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d)
+
+#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1 \
+	EFI_GUID(0xea296d92, 0x0b69, 0x423c, \
+		0x8c, 0x28, 0x33, 0xb4, 0xe0, 0xa9, 0x12, 0x68)
+
+#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2 \
+	EFI_GUID(0x9b3ada4f, 0xae56, 0x4c24, \
+		0x8d, 0xea, 0xf0, 0x3b, 0x75, 0x58, 0xae, 0x50)
+
+#define FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID \
+	EFI_GUID(0x86d70125, 0xbaa3, 0x4296, \
+		0xa6, 0x2f, 0x60, 0x2b, 0xeb, 0xbb, 0x90, 0x81)
+
+#define FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID \
+	EFI_GUID(0x4ed4bf27, 0x4092, 0x42e9, \
+		0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x00, 0xc9, 0xbd)
+
+#define FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID \
+	EFI_GUID(0x01a1108c, 0x9dee, 0x4984, \
+		0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89)
+
 #endif

diff --git a/arch/x86/include/asm/intel_acpi.h b/arch/x86/include/asm/intel_acpi.h
new file mode 100644
index 0000000..a5781f1
--- /dev/null
+++ b/arch/x86/include/asm/intel_acpi.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __ASM_INTEL_ACPI_H__
+#define __ASM_INTEL_ACPI_H__
+
+struct acpi_cstate;
+struct acpi_ctx;
+struct acpi_tstate;
+struct udevice;
+
+/**
+ * acpi_generate_cpu_header() - Start generating an ACPI CPU entry
+ *
+ * Generates the ACPI information for a CPU. After this, the caller should
+ * generate_p_state_entries(), generate_t_state_entries and then
+ * acpigen_pop_len() to close off this package.
+ *
+ * @ctx: ACPI context pointer
+ * @core_id: CPU core number, as numbered by the SoC
+ * @c_state_map: Information about each C state
+ * @num_cstates: Number of entries in @c_state_map
+ * @return 0 if OK, -ve on error
+ */
+int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id,
+			     const struct acpi_cstate *c_state_map,
+			     int num_cstates);
+
+/**
+ * acpi_generate_cpu_package_final() - Write out the CPU PPKG entry
+ *
+ * This writes information about the CPUs in the package
+ *
+ * @ctx: ACPI context pointer
+ * @cores_per_package: Number of CPU cores in each package in the SoC
+ */
+int acpi_generate_cpu_package_final(struct acpi_ctx *ctx,
+				    int cores_per_package);
+
+void generate_p_state_entries(struct acpi_ctx *ctx, int core,
+			      int cores_per_package);
+void generate_t_state_entries(struct acpi_ctx *ctx, int core,
+			      int cores_per_package, struct acpi_tstate *entry,
+			      int nentries);
+int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx);
+
+int intel_southbridge_write_acpi_tables(const struct udevice *dev,
+					struct acpi_ctx *ctx);
+
+#endif /* __ASM_INTEL_ACPI_H__ */

diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
new file mode 100644
index 0000000..c1e9d65
--- /dev/null
+++ b/arch/x86/include/asm/intel_gnvs.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * Taken from coreboot intelblocks/nvs.h
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _INTEL_GNVS_H_
+#define _INTEL_GNVS_H_
+
+struct __packed acpi_global_nvs {
+	/* Miscellaneous */
+	u8	pcnt; /* 0x00 - Processor Count */
+	u8	ppcm; /* 0x01 - Max PPC State */
+	u8	lids; /* 0x02 - LID State */
+	u8	pwrs; /* 0x03 - AC Power State */
+	u8	dpte; /* 0x04 - Enable DPTF */
+	u32	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	u64	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	u64	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	u64	nhla; /* 0x19 - 0x20 - NHLT Address */
+	u32	nhll; /* 0x21 - 0x24 - NHLT Length */
+	u32	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	u8	scdp; /* 0x29 - SD_CD GPIO portid */
+	u8	scdo; /* 0x2a - GPIO pad offset relative to the community */
+	u8	uior; /* 0x2b - UART debug controller init on S3 resume */
+	u8	ecps; /* 0x2c - SGX Enabled status */
+	u64	emna; /* 0x2d - 0x34 EPC base address */
+	u64	elng; /* 0x35 - 0x3C EPC Length */
+	u8	unused1[0x100 - 0x3d];		/* Pad out to 256 bytes */
+#ifdef CONFIG_CHROMEOS
+	/* ChromeOS-specific (0x100 - 0xfff) */
+	struct chromeos_acpi chromeos;
+#else
+	u8	unused2[0x1000 - 0x100];	/* Pad out to 4096 bytes */
+#endif
+};
+
+#ifdef CONFIG_CHROMEOS
+check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+#endif
+
+#endif /* _INTEL_GNVS_H_ */

diff --git a/arch/x86/include/asm/intel_opregion.h b/arch/x86/include/asm/intel_opregion.h
new file mode 100644
index 0000000..fb3e386
--- /dev/null
+++ b/arch/x86/include/asm/intel_opregion.h

@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.h
+ */
+
+#ifndef _ASM_INTEL_OPREGION_H_
+#define _ASM_INTEL_OPREGION_H_
+
+#define VBT_SIGNATURE		0x54425624
+
+/* IGD PCI Configuration register */
+#define ASLS		0xfc		/* OpRegion Base */
+#define SWSCI		0xe8		/* SWSCI Register */
+#define SWSMISCI	0xe0		/* SWSMISCI Register */
+#define GSSCIE		BIT(0)		/* SCI Event trigger */
+#define SMISCISEL	BIT(15)		/* Select SMI or SCI event source */
+
+/* mailbox 0: header */
+struct __packed opregion_header {
+	u8	signature[16];	    /* Offset 0    OpRegion signature */
+	u32	size;		    /* Offset 16   OpRegion size */
+	u32	version;	    /* Offset 20   OpRegion structure version */
+	u8	sbios_version[32];  /* Offset 24   System BIOS build version */
+	u8	vbios_version[16];  /* Offset 56   Video BIOS build version */
+	u8	driver_version[16]; /* Offset 72   Graphic drvr build version */
+	u32	mailboxes;	    /* Offset 88   Mailboxes supported */
+	u32	dmod;		    /* Offset 92   Driver Model */
+	u32	pcon;		    /* Offset 96   Platform Capabilities */
+	u16	dver[16];	    /* Offset 100  GOP Version */
+	u8	reserved[124];	    /* Offset 132  Reserved */
+};
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION  2
+
+#define IGD_MBOX1	BIT(0)
+#define IGD_MBOX2	BIT(1)
+#define IGD_MBOX3	BIT(2)
+#define IGD_MBOX4	BIT(3)
+#define IGD_MBOX5	BIT(4)
+
+#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+			   IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public ACPI methods */
+struct __packed opregion_mailbox1 {
+	u32	drdy;	/* Offset 0    Driver readiness */
+	u32	csts;	/* Offset 4    Status */
+	u32	cevt;	/* Offset 8    Current event */
+	u8	reserved[20];	/* Offset 12   Reserved */
+	u32	didl;	/* Offset 32   Supported display device 1 */
+	u32	ddl2;	/* Offset 36   Supported display device 2 */
+	u32	ddl3;	/* Offset 40   Supported display device 3 */
+	u32	ddl4;	/* Offset 44   Supported display device 4 */
+	u32	ddl5;	/* Offset 48   Supported display device 5 */
+	u32	ddl6;	/* Offset 52   Supported display device 6 */
+	u32	ddl7;	/* Offset 56   Supported display device 7 */
+	u32	ddl8;	/* Offset 60   Supported display device 8 */
+	u32	cpdl;	/* Offset 64   Currently present display device 1 */
+	u32	cpl2;	/* Offset 68   Currently present display device 2 */
+	u32	cpl3;	/* Offset 72   Currently present display device 3 */
+	u32	cpl4;	/* Offset 76   Currently present display device 4 */
+	u32	cpl5;	/* Offset 80   Currently present display device 5 */
+	u32	cpl6;	/* Offset 84   Currently present display device 6 */
+	u32	cpl7;	/* Offset 88   Currently present display device 7 */
+	u32	cpl8;	/* Offset 92   Currently present display device 8 */
+	u32	cadl;	/* Offset 96   Currently active display device 1 */
+	u32	cal2;	/* Offset 100  Currently active display device 2 */
+	u32	cal3;	/* Offset 104  Currently active display device 3 */
+	u32	cal4;	/* Offset 108  Currently active display device 4 */
+	u32	cal5;	/* Offset 112  Currently active display device 5 */
+	u32	cal6;	/* Offset 116  Currently active display device 6 */
+	u32	cal7;	/* Offset 120  Currently active display device 7 */
+	u32	cal8;	/* Offset 124  Currently active display device 8 */
+	u32	nadl;	/* Offset 128  Next active device 1 */
+	u32	ndl2;	/* Offset 132  Next active device 2 */
+	u32	ndl3;	/* Offset 136  Next active device 3 */
+	u32	ndl4;	/* Offset 140  Next active device 4 */
+	u32	ndl5;	/* Offset 144  Next active device 5 */
+	u32	ndl6;	/* Offset 148  Next active device 6 */
+	u32	ndl7;	/* Offset 152  Next active device 7 */
+	u32	ndl8;	/* Offset 156  Next active device 8 */
+	u32	aslp;	/* Offset 160  ASL sleep timeout */
+	u32	tidx;	/* Offset 164  Toggle table index */
+	u32	chpd;	/* Offset 168  Current hot plug enable indicator */
+	u32	clid;	/* Offset 172  Current lid state indicator */
+	u32	cdck;	/* Offset 176  Current docking state indicator */
+	u32	sxsw;	/* Offset 180  Display Switch notification on Sx State
+			 * resume
+			 */
+	u32	evts;	/* Offset 184  Events supported by ASL */
+	u32	cnot;	/* Offset 188  Current OS Notification */
+	u32	nrdy;	/* Offset 192  Reasons for DRDY = 0 */
+	u32	ddl9;	/* Offset 196  Extended Supported display device 1 */
+	u32	dd10;	/* Offset 200  Extended Supported display device 2 */
+	u32	dd11;	/* Offset 204  Extended Supported display device 3 */
+	u32	dd12;	/* Offset 208  Extended Supported display device 4 */
+	u32	dd13;	/* Offset 212  Extended Supported display device 5 */
+	u32	dd14;	/* Offset 216  Extended Supported display device 6 */
+	u32	dd15;	/* Offset 220  Extended Supported display device 7 */
+	u32	cpl9;	/* Offset 224  Extended Currently present device 1 */
+	u32	cp10;	/* Offset 228  Extended Currently present device 2 */
+	u32	cp11;	/* Offset 232  Extended Currently present device 3 */
+	u32	cp12;	/* Offset 236  Extended Currently present device 4 */
+	u32	cp13;	/* Offset 240  Extended Currently present device 5 */
+	u32	cp14;	/* Offset 244  Extended Currently present device 6 */
+	u32	cp15;	/* Offset 248  Extended Currently present device 7 */
+	u8	reserved2[4];	/* Offset 252  Reserved 4 bytes */
+};
+
+/* mailbox 2: software sci interface */
+struct __packed opregion_mailbox2 {
+	u32	scic;	/* Offset 0  Software SCI function number parameters */
+	u32	parm;	/* Offset 4  Software SCI function number parameters */
+	u32	dslp;	/* Offset 8  Driver sleep timeout */
+	u8	reserved[244];	/* Offset 12   Reserved */
+};
+
+/* mailbox 3: power conservation */
+struct __packed opregion_mailbox3 {
+	u32	ardy;		/* Offset 0   Driver readiness */
+	u32	aslc;		/* Offset 4   ASLE interrupt command / status */
+	u32	tche;		/* Offset 8   Technology enabled indicator */
+	u32	alsi;		/* Offset 12  Current ALS illuminance reading */
+	u32	bclp;		/* Offset 16  Backlight britness to set */
+	u32	pfit;		/* Offset 20  Panel fitting Request */
+	u32	cblv;		/* Offset 24  Brightness Current State */
+	/* Offset 28  Backlight Brightness Level Duty Cycle Mapping Table */
+	u16	bclm[20];
+	u32	cpfm;		/* Offset 68  Panel Fitting Current Mode */
+	u32	epfm;		/* Offset 72  Enabled Panel Fitting Modes */
+	u8	plut[74];	/* Offset 76  Panel Look Up Table */
+	/* Offset 150 PWM Frequency and Minimum Brightness */
+	u32	pfmb;
+	u32	ccdv;		/* Offset 154 Color Correction Default Values */
+	u32	pcft;		/* Offset 158 Power Conservation Features */
+	u32	srot;		/* Offset 162 Supported Rotation angle */
+	u32	iuer;		/* Offset 166 Intel Ultrabook Event Register */
+	u64	fdsp;		/* Offset 170 FFS Display Physical address */
+	u32	fdss;		/* Offset 178 FFS Display Size */
+	u32	stat;		/* Offset 182 State Indicator */
+	/*
+	 * Offset 186 (Igd opregion offset 0x3BAh)
+	 * Physical address of Raw VBT data
+	 */
+	u64	rvda;
+	/* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
+	u32	rvds;
+	u8	reserved[58];	/* Offset 198 Reserved */
+};
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID		BIT(31)
+#define IGD_WORD_FIELD_VALID	BIT(15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+struct __packed opregion_vbt {
+	u8 gvd1[6 << 10];
+};
+
+/* Mailbox 5: BIOS to Driver Notification Extension */
+struct __packed opregion_mailbox5 {
+	u32	phed;		/* Offset 7168 Panel Header */
+	u8	bddc[256];	/* Offset 7172 Panel EDID */
+	u8	reserved[764];	/* Offset 7428 764 bytes */
+};
+
+/* IGD OpRegion */
+struct __packed igd_opregion {
+	struct opregion_header header;
+	struct opregion_mailbox1 mailbox1;
+	struct opregion_mailbox2 mailbox2;
+	struct opregion_mailbox3 mailbox3;
+	struct opregion_vbt vbt;
+	struct opregion_mailbox5 mailbox5;
+};
+
+/* Intel Video BIOS (Option ROM) */
+struct __packed optionrom_header {
+	u16	signature;
+	u8	size;
+	u8	reserved[21];
+	u16	pcir_offset;
+	u16	vbt_offset;
+};
+
+#define OPROM_SIGNATURE 0xaa55
+
+struct __packed optionrom_pcir {
+	u32	signature;
+	u16	vendor;
+	u16	device;
+	u16	reserved1;
+	u16	length;
+	u8	revision;
+	u8	classcode[3];
+	u16	imagelength;
+	u16	coderevision;
+	u8	codetype;
+	u8	indicator;
+	u16	reserved2;
+};
+
+struct __packed optionrom_vbt {
+	u8	hdr_signature[20];
+	u16	hdr_version;
+	u16	hdr_size;
+	u16	hdr_vbt_size;
+	u8	hdr_vbt_checksum;
+	u8	hdr_reserved;
+	u32	hdr_vbt_datablock;
+	u32	hdr_aim[4];
+	u8	datahdr_signature[16];
+	u16	datahdr_version;
+	u16	datahdr_size;
+	u16	datahdr_datablocksize;
+	u8	coreblock_id;
+	u16	coreblock_size;
+	u16	coreblock_biossize;
+	u8	coreblock_biostype;
+	u8	coreblock_releasestatus;
+	u8	coreblock_hwsupported;
+	u8	coreblock_integratedhw;
+	u8	coreblock_biosbuild[4];
+	u8	coreblock_biossignon[155];
+};
+
+/**
+ * intel_gma_init_igd_opregion() - Initialise IGD OpRegion
+ *
+ * This is called from ACPI code and OS drivers
+ *
+ * @return 0 if OK, -ve on error
+ */
+int intel_gma_init_igd_opregion(struct udevice *dev,
+				struct igd_opregion *opregion);
+
+#endif /* _ASM_INTEL_OPREGION_H_ */

diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 48db1dd..3a98aac 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h

@@ -36,8 +36,8 @@
 
 #define MTRR_BASE_TYPE_MASK	0x7
 
-/* Number of MTRRs supported */
-#define MTRR_COUNT		8
+/* Maximum number of MTRRs supported - see also mtrr_get_var_count() */
+#define MTRR_MAX_COUNT		10
 
 #define NUM_FIXED_MTRRS		11
 #define RANGES_PER_FIXED_MTRR	8
@@ -87,7 +87,7 @@
  * @mtrr: Information about each mtrr
  */
 struct mtrr_info {
-	struct mtrr mtrr[MTRR_COUNT];
+	struct mtrr mtrr[MTRR_MAX_COUNT];
 };
 
 /**
@@ -180,6 +180,15 @@
  */
 int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
 
+/**
+ * mtrr_get_var_count() - Get the number of variable MTRRs
+ *
+ * Some CPUs have more than 8 MTRRs. This function returns the actual number
+ *
+ * @return number of variable MTRRs
+ */
+int mtrr_get_var_count(void);
+
 #endif
 
 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)

diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h
new file mode 100644
index 0000000..1e539fd
--- /dev/null
+++ b/arch/x86/include/asm/smm.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * SMM definitions (U-Boot does not support SMM itself)
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot smm.h
+ */
+
+#ifndef _ASM_SMM_H
+#define _ASM_SMM_H
+
+#define APM_CNT			0xb2
+#define APM_CNT_CST_CONTROL	0x85
+#define APM_CNT_PST_CONTROL	0x80
+#define APM_CNT_ACPI_DISABLE	0x1e
+#define APM_CNT_ACPI_ENABLE	0xe1
+#define APM_CNT_MBI_UPDATE	0xeb
+#define APM_CNT_GNVS_UPDATE	0xea
+#define APM_CNT_FINALIZE	0xcb
+#define APM_CNT_LEGACY		0xcc
+#define APM_CNT_SMMSTORE	0xed
+#define APM_CNT_ELOG_GSMI	0xef
+#define APM_STS			0xb3
+
+#endif /* _ASM_SMM_H */

diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 80e128c..64c0e6e 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h

@@ -30,10 +30,38 @@
 #define BZIMAGE_LOAD_ADDR  0x100000
 #define ZIMAGE_LOAD_ADDR   0x10000
 
+/**
+ * load_zimage() - Load a zImage or bzImage
+ *
+ * This copies an image into the standard location ready for setup
+ *
+ * @image: Address of image to load
+ * @kernel_size: Size of kernel including setup block (or 0 if the kernel is
+ *	new enough to have a 'syssize' value)
+ * @load_addressp: Returns the address where the kernel has been loaded
+ * @return address of setup block, or NULL if something went wrong
+ */
 struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 				ulong *load_addressp);
+
+/**
+ * setup_zimage() - Set up a loaded zImage or bzImage ready for booting
+ *
+ * @setup_base: Pointer to the boot parameters, typically at address
+ *	DEFAULT_SETUP_BASE
+ * @cmd_line: Place to put the command line, or NULL to use the one in the setup
+ *	block
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @load_address: Address where the bzImage is moved before booting, either
+ *	BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * @cmdline_force: Address of 'override' command line, or 0 to use the one in
+ *	the *	setup block
+ * @return 0 (always)
+ */
 int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
-		 unsigned long initrd_addr, unsigned long initrd_size);
+		 ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
+
 void setup_video(struct screen_info *screen_info);
 void setup_efi_info(struct efi_info *efi_info);
 

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 1185a88..1bcbb49 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile

@@ -38,6 +38,7 @@
 obj-y	+= acpi.o
 obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
 ifndef CONFIG_QEMU
+obj-y += acpigen.o
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index c445aa6..6d405b0 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c

@@ -6,7 +6,10 @@
  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  */
 
+#define LOG_CATEGORY LOGC_ACPI
+
 #include <common.h>
+#include <bloblist.h>
 #include <cpu.h>
 #include <dm.h>
 #include <log.h>
@@ -15,6 +18,7 @@
 #include <serial.h>
 #include <version.h>
 #include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
 #include <acpi/acpi_table.h>
 #include <asm/acpi/global_nvs.h>
 #include <asm/ioapic.h>
@@ -65,14 +69,17 @@
 {
 	struct udevice *dev;
 	int total_length = 0;
+	int cpu_num = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-		int length = acpi_create_madt_lapic(
-				(struct acpi_madt_lapic *)current,
-				plat->cpu_id, plat->cpu_id);
+		int length;
+
+		length = acpi_create_madt_lapic(
+			(struct acpi_madt_lapic *)current, cpu_num++,
+			plat->cpu_id);
 		current += length;
 		total_length += length;
 	}
@@ -210,6 +217,105 @@
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
+/**
+ * acpi_create_tcpa() - Create a TCPA table
+ *
+ * @tcpa: Pointer to place to put table
+ *
+ * Trusted Computing Platform Alliance Capabilities Table
+ * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
+ * Firmware Specification 3.0
+ */
+static int acpi_create_tcpa(struct acpi_tcpa *tcpa)
+{
+	struct acpi_table_header *header = &tcpa->header;
+	u32 current = (u32)tcpa + sizeof(struct acpi_tcpa);
+	int size = 0x10000;	/* Use this as the default size */
+	void *log;
+	int ret;
+
+	if (!CONFIG_IS_ENABLED(BLOBLIST))
+		return -ENXIO;
+	memset(tcpa, '\0', sizeof(struct acpi_tcpa));
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "TCPA");
+	header->length = sizeof(struct acpi_tcpa);
+	header->revision = 1;
+
+	ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
+	if (ret)
+		return log_msg_ret("blob", ret);
+
+	tcpa->platform_class = 0;
+	tcpa->laml = size;
+	tcpa->lasa = (ulong)log;
+
+	/* (Re)calculate length and checksum */
+	header->length = current - (u32)tcpa;
+	header->checksum = table_compute_checksum((void *)tcpa, header->length);
+
+	return 0;
+}
+
+static int get_tpm2_log(void **ptrp, int *sizep)
+{
+	const int tpm2_default_log_len = 0x10000;
+	int size;
+	int ret;
+
+	*sizep = 0;
+	size = tpm2_default_log_len;
+	ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
+	if (ret)
+		return log_msg_ret("blob", ret);
+	*sizep = size;
+
+	return 0;
+}
+
+static int acpi_create_tpm2(struct acpi_tpm2 *tpm2)
+{
+	struct acpi_table_header *header = &tpm2->header;
+	int tpm2_log_len;
+	void *lasa;
+	int ret;
+
+	memset((void *)tpm2, 0, sizeof(struct acpi_tpm2));
+
+	/*
+	 * Some payloads like SeaBIOS depend on log area to use TPM2.
+	 * Get the memory size and address of TPM2 log area or initialize it.
+	 */
+	ret = get_tpm2_log(&lasa, &tpm2_log_len);
+	if (ret)
+		return ret;
+
+	/* Fill out header fields. */
+	acpi_fill_header(header, "TPM2");
+	memcpy(header->aslc_id, ASLC_ID, 4);
+
+	header->length = sizeof(struct acpi_tpm2);
+	header->revision = acpi_get_table_revision(ACPITAB_TPM2);
+
+	/* Hard to detect for coreboot. Just set it to 0 */
+	tpm2->platform_class = 0;
+
+	/* Must be set to 0 for FIFO-interface support */
+	tpm2->control_area = 0;
+	tpm2->start_method = 6;
+	memset(tpm2->msp, 0, sizeof(tpm2->msp));
+
+	/* Fill the log area size and start address fields. */
+	tpm2->laml = tpm2_log_len;
+	tpm2->lasa = (uintptr_t)lasa;
+
+	/* Calculate checksum. */
+	header->checksum = table_compute_checksum((void *)tpm2, header->length);
+
+	return 0;
+}
+
 __weak u32 acpi_fill_csrt(u32 current)
 {
 	return 0;
@@ -394,11 +500,13 @@
 	struct acpi_fadt *fadt;
 	struct acpi_table_header *ssdt;
 	struct acpi_mcfg *mcfg;
+	struct acpi_tcpa *tcpa;
 	struct acpi_madt *madt;
 	struct acpi_csrt *csrt;
 	struct acpi_spcr *spcr;
 	void *start;
 	ulong addr;
+	int ret;
 	int i;
 
 	start = map_sysmem(start_addr, 0);
@@ -430,17 +538,31 @@
 	       dsdt->length - sizeof(struct acpi_table_header));
 
 	acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header));
+	dsdt->length = ctx->current - (void *)dsdt;
+	acpi_align(ctx);
 
-	/* Pack GNVS into the ACPI table area */
-	for (i = 0; i < dsdt->length; i++) {
-		u32 *gnvs = (u32 *)((u32)dsdt + i);
-		if (*gnvs == ACPI_GNVS_ADDR) {
-			ulong addr = (ulong)map_to_sysmem(ctx->current);
+	if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
+		/* Pack GNVS into the ACPI table area */
+		for (i = 0; i < dsdt->length; i++) {
+			u32 *gnvs = (u32 *)((u32)dsdt + i);
 
-			debug("Fix up global NVS in DSDT to %#08lx\n", addr);
-			*gnvs = addr;
-			break;
+			if (*gnvs == ACPI_GNVS_ADDR) {
+				*gnvs = map_to_sysmem(ctx->current);
+				debug("Fix up global NVS in DSDT to %#08x\n",
+				      *gnvs);
+				break;
+			}
 		}
+
+		/*
+		 * Fill in platform-specific global NVS variables. If this fails
+		 * we cannot return the error but this should only happen while
+		 * debugging.
+		 */
+		addr = acpi_create_gnvs(ctx->current);
+		if (IS_ERR_VALUE(addr))
+			printf("Error: Gailed to create GNVS\n");
+		acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
 	}
 
 	/*
@@ -448,12 +570,9 @@
 	 * the GNVS address. Set the checksum to zero since it is part of the
 	 * region being checksummed.
 	 */
-	dsdt->length = ctx->current - (void *)dsdt;
 	dsdt->checksum = 0;
 	dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
 
-	acpi_align(ctx);
-
 	/*
 	 * Fill in platform-specific global NVS variables. If this fails we
 	 * cannot return the error but this should only happen while debugging.
@@ -484,12 +603,36 @@
 	acpi_inc_align(ctx, mcfg->header.length);
 	acpi_add_table(ctx, mcfg);
 
+	if (IS_ENABLED(CONFIG_TPM_V2)) {
+		struct acpi_tpm2 *tpm2;
+
+		debug("ACPI:    * TPM2\n");
+		tpm2 = (struct acpi_tpm2 *)ctx->current;
+		ret = acpi_create_tpm2(tpm2);
+		if (!ret) {
+			acpi_inc_align(ctx, tpm2->header.length);
+			acpi_add_table(ctx, tpm2);
+		} else {
+			log_warning("TPM2 table creation failed\n");
+		}
+	}
+
 	debug("ACPI:    * MADT\n");
 	madt = ctx->current;
 	acpi_create_madt(madt);
 	acpi_inc_align(ctx, madt->header.length);
 	acpi_add_table(ctx, madt);
 
+	debug("ACPI:    * TCPA\n");
+	tcpa = (struct acpi_tcpa *)ctx->current;
+	ret = acpi_create_tcpa(tcpa);
+	if (ret) {
+		log_warning("Failed to create TCPA table (err=%d)\n", ret);
+	} else {
+		acpi_inc_align(ctx, tcpa->header.length);
+		acpi_add_table(ctx, tcpa);
+	}
+
 	debug("ACPI:    * CSRT\n");
 	csrt = ctx->current;
 	if (!acpi_create_csrt(csrt)) {
@@ -518,3 +661,213 @@
 {
 	return acpi_rsdp_addr;
 }
+
+/**
+ * acpi_write_hpet() - Write out a HPET table
+ *
+ * Write out the table for High-Precision Event Timers
+ *
+ * @hpet: Place to put HPET table
+ */
+static int acpi_create_hpet(struct acpi_hpet *hpet)
+{
+	struct acpi_table_header *header = &hpet->header;
+	struct acpi_gen_regaddr *addr = &hpet->addr;
+
+	/*
+	 * See IA-PC HPET (High Precision Event Timers) Specification v1.0a
+	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
+	 */
+	memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
+
+	/* Fill out header fields. */
+	acpi_fill_header(header, "HPET");
+
+	header->aslc_revision = ASL_REVISION;
+	header->length = sizeof(struct acpi_hpet);
+	header->revision = acpi_get_table_revision(ACPITAB_HPET);
+
+	/* Fill out HPET address */
+	addr->space_id = 0;  /* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
+	addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
+
+	hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
+	hpet->number = 0;
+	hpet->min_tick = 0; /* HPET_MIN_TICKS */
+
+	header->checksum = table_compute_checksum(hpet,
+						  sizeof(struct acpi_hpet));
+
+	return 0;
+}
+
+int acpi_write_hpet(struct acpi_ctx *ctx)
+{
+	struct acpi_hpet *hpet;
+	int ret;
+
+	log_debug("ACPI:    * HPET\n");
+
+	hpet = ctx->current;
+	acpi_inc_align(ctx, sizeof(struct acpi_hpet));
+	acpi_create_hpet(hpet);
+	ret = acpi_add_table(ctx, hpet);
+	if (ret)
+		return log_msg_ret("add", ret);
+
+	return 0;
+}
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+			     uint access_size)
+{
+	struct acpi_dbg2_header *dbg2 = ctx->current;
+	char path[ACPI_PATH_MAX];
+	struct acpi_gen_regaddr address;
+	phys_addr_t addr;
+	int ret;
+
+	if (!device_active(dev)) {
+		log_info("Device not enabled\n");
+		return -EACCES;
+	}
+	/*
+	 * PCI devices don't remember their resource allocation information in
+	 * U-Boot at present. We assume that MMIO is used for the UART and that
+	 * the address space is 32 bytes: ns16550 uses 8 registers of up to
+	 * 32-bits each. This is only for debugging so it is not a big deal.
+	 */
+	addr = dm_pci_read_bar32(dev, 0);
+	printf("UART addr %lx\n", (ulong)addr);
+
+	memset(&address, '\0', sizeof(address));
+	address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+	address.addrl = (uint32_t)addr;
+	address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
+	address.access_size = access_size;
+
+	ret = acpi_device_path(dev, path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+	acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+			 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
+
+	acpi_inc_align(ctx, dbg2->header.length);
+	acpi_add_table(ctx, dbg2);
+
+	return 0;
+}
+
+void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &fadt->header;
+
+	memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+	header->aslc_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long)facs;
+	fadt->dsdt = (unsigned long)dsdt;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+
+	/* Use ACPI 3.0 revision */
+	fadt->header.revision = 4;
+}
+
+void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
+			   u64 bar)
+{
+	struct dmar_entry *drhd = ctx->current;
+
+	memset(drhd, '\0', sizeof(*drhd));
+	drhd->type = DMAR_DRHD;
+	drhd->length = sizeof(*drhd); /* will be fixed up later */
+	drhd->flags = flags;
+	drhd->segment = segment;
+	drhd->bar = bar;
+	acpi_inc(ctx, drhd->length);
+}
+
+void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
+			   u64 limit)
+{
+	struct dmar_rmrr_entry *rmrr = ctx->current;
+
+	memset(rmrr, '\0', sizeof(*rmrr));
+	rmrr->type = DMAR_RMRR;
+	rmrr->length = sizeof(*rmrr); /* will be fixed up later */
+	rmrr->segment = segment;
+	rmrr->bar = bar;
+	rmrr->limit = limit;
+	acpi_inc(ctx, rmrr->length);
+}
+
+void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base)
+{
+	struct dmar_entry *drhd = base;
+
+	drhd->length = ctx->current - base;
+}
+
+void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base)
+{
+	struct dmar_rmrr_entry *rmrr = base;
+
+	rmrr->length = ctx->current - base;
+}
+
+static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type,
+			       uint enumeration_id, pci_dev_t bdf)
+{
+	/* we don't support longer paths yet */
+	const size_t dev_scope_length = sizeof(struct dev_scope) + 2;
+	struct dev_scope *ds = ctx->current;
+
+	memset(ds, '\0', dev_scope_length);
+	ds->type = type;
+	ds->length = dev_scope_length;
+	ds->enumeration = enumeration_id;
+	ds->start_bus = PCI_BUS(bdf);
+	ds->path[0].dev = PCI_DEV(bdf);
+	ds->path[0].fn = PCI_FUNC(bdf);
+
+	return ds->length;
+}
+
+int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf)
+{
+	return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf);
+}
+
+int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf)
+{
+	return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf);
+}
+
+int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
+			       pci_dev_t bdf)
+{
+	return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf);
+}
+
+int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
+				 pci_dev_t bdf)
+{
+	return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf);
+}

diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c
new file mode 100644
index 0000000..ea2ec2a
--- /dev/null
+++ b/arch/x86/lib/acpigen.c

@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Google LLC
+ */
+
+#include <common.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpigen.h>
+
+void acpigen_write_empty_pct(struct acpi_ctx *ctx)
+{
+	/*
+	 * Name (_PCT, Package (0x02)
+	 * {
+	 *	ResourceTemplate ()
+	 *	{
+	 *		Register (FFixedHW,
+	 *			0x00,               // Bit Width
+	 *			0x00,               // Bit Offset
+	 *			0x0000000000000000, // Address
+	 *			,)
+	 *	},
+	 *
+	 *	ResourceTemplate ()
+	 *	{
+	 *		Register (FFixedHW,
+	 *			0x00,               // Bit Width
+	 *			0x00,               // Bit Offset
+	 *			0x0000000000000000, // Address
+	 *			,)
+	 *	}
+	 * })
+	 */
+	static char stream[] = {
+		/* 00000030    "0._PCT.," */
+		0x08, 0x5f, 0x50, 0x43, 0x54, 0x12, 0x2c,
+		/* 00000038    "........" */
+		0x02, 0x11, 0x14, 0x0a, 0x11, 0x82, 0x0c, 0x00,
+		/* 00000040    "........" */
+		0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		/* 00000048    "....y..." */
+		0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14,
+		/* 00000050    "........" */
+		0x0a, 0x11, 0x82, 0x0c, 0x00, 0x7f, 0x00, 0x00,
+		/* 00000058    "........" */
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x79, 0x00
+	};
+	acpigen_emit_stream(ctx, stream, ARRAY_SIZE(stream));
+}
+
+void acpigen_write_empty_ptc(struct acpi_ctx *ctx)
+{
+	/*
+	 * Name (_PTC, Package (0x02)
+	 * {
+	 *	ResourceTemplate ()
+	 *	{
+	 *		Register (FFixedHW,
+	 *			0x00,               // Bit Width
+	 *			0x00,               // Bit Offset
+	 *			0x0000000000000000, // Address
+	 *			,)
+	 *	},
+	 *
+	 *	ResourceTemplate ()
+	 *	{
+	 *		Register (FFixedHW,
+	 *			0x00,               // Bit Width
+	 *			0x00,               // Bit Offset
+	 *			0x0000000000000000, // Address
+	 *			,)
+	 *	}
+	 * })
+	 */
+	struct acpi_gen_regaddr addr = {
+		.space_id    = ACPI_ADDRESS_SPACE_FIXED,
+		.bit_width   = 0,
+		.bit_offset  = 0,
+		.access_size = 0,
+		.addrl       = 0,
+		.addrh       = 0,
+	};
+
+	acpigen_write_name(ctx, "_PTC");
+	acpigen_write_package(ctx, 2);
+
+	/* ControlRegister */
+	acpigen_write_register_resource(ctx, &addr);
+
+	/* StatusRegister */
+	acpigen_write_register_resource(ctx, &addr);
+
+	acpigen_pop_len(ctx);
+}

diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 1198a52..da6b8ce 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c

@@ -136,7 +136,7 @@
 	printf("Setup at %#08lx\n", images->ep);
 	ret = setup_zimage((void *)images->ep, cmd_line_dest,
 			0, images->rd_start,
-			images->rd_end - images->rd_start);
+			images->rd_end - images->rd_start, 0);
 
 	if (ret) {
 		printf("## Setting up boot parameters failed ...\n");

diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index ea52954..4061fa2 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c

@@ -60,6 +60,22 @@
 		debug("OK\n");
 }
 
+void board_final_cleanup(void)
+{
+	u32 status;
+
+	/* TODO(sjg@chromium.org): This causes Linux to crash */
+	return;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
+	status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
+	if (status)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+}
+
 int fsp_save_s3_stack(void)
 {
 	struct udevice *dev;

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index faa819f..a76497d 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c

@@ -12,6 +12,7 @@
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
+#include <dm/ofnode.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +93,8 @@
 	unsigned int num_entries = 0;
 	const struct hob_header *hdr;
 	struct hob_res_desc *res_desc;
+	const fdt64_t *prop;
+	int size;
 
 	hdr = gd->arch.hob_list;
 
@@ -133,6 +136,20 @@
 		num_entries++;
 	}
 
+	prop = ofnode_read_chosen_prop("e820-entries", &size);
+	if (prop) {
+		int count = size / (sizeof(u64) * 3);
+		int i;
+
+		if (num_entries + count >= max_entries)
+			return -ENOSPC;
+		for (i = 0; i < count; i++, num_entries++, prop += 3) {
+			entries[num_entries].addr = fdt64_to_cpu(prop[0]);
+			entries[num_entries].size = fdt64_to_cpu(prop[1]);
+			entries[num_entries].type = fdt64_to_cpu(prop[2]);
+		}
+	}
+
 	return num_entries;
 }
 

diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index e8c1e07..858d794 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c

@@ -3,14 +3,19 @@
  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  */
 
+#define LOG_CATEGORY UCLASS_VIDEO
+
 #include <common.h>
 #include <dm.h>
 #include <init.h>
 #include <log.h>
 #include <vbe.h>
 #include <video.h>
+#include <acpi/acpi_table.h>
 #include <asm/fsp/fsp_support.h>
+#include <asm/intel_opregion.h>
 #include <asm/mtrr.h>
+#include <dm/acpi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -127,6 +132,32 @@
 	return 0;
 }
 
+#ifdef CONFIG_INTEL_GMA_ACPI
+static int fsp_video_acpi_write_tables(const struct udevice *dev,
+				       struct acpi_ctx *ctx)
+{
+	struct igd_opregion *opregion;
+	int ret;
+
+	printf("ACPI:    * IGD OpRegion\n");
+	opregion = (struct igd_opregion *)ctx->current;
+
+	ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
+	if (ret)
+		return ret;
+
+	acpi_inc_align(ctx, sizeof(struct igd_opregion));
+
+	return 0;
+}
+#endif
+
+struct acpi_ops fsp_video_acpi_ops = {
+#ifdef CONFIG_INTEL_GMA_ACPI
+	.write_tables	= fsp_video_acpi_write_tables,
+#endif
+};
+
 static const struct udevice_id fsp_video_ids[] = {
 	{ .compatible = "fsp-fb" },
 	{ }
@@ -139,6 +170,7 @@
 	.bind	= fsp_video_bind,
 	.probe	= fsp_video_probe,
 	.flags	= DM_FLAG_PRE_RELOC,
+	ACPI_OPS_PTR(&fsp_video_acpi_ops)
 };
 
 static struct pci_device_id fsp_video_supported[] = {

diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c
index 0f221a8..ead3493 100644
--- a/arch/x86/lib/fsp2/fsp_silicon_init.c
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c

@@ -26,8 +26,10 @@
 	struct binman_entry entry;
 	struct udevice *dev;
 	ulong rom_offset = 0;
+	u32 init_addr;
 	int ret;
 
+	log_debug("Locating FSP\n");
 	ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
 			     &rom_offset);
 	if (ret)
@@ -44,7 +46,7 @@
 	ret = fsps_update_config(dev, rom_offset, &upd);
 	if (ret)
 		return log_msg_ret("Could not setup config", ret);
-	log_debug("Silicon init...");
+	log_debug("Silicon init @ %x...", init_addr);
 	bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
 	func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
 	ret = func(&upd);

diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c
index 3f2ca84..f220ef4 100644
--- a/arch/x86/lib/fsp2/fsp_support.c
+++ b/arch/x86/lib/fsp2/fsp_support.c

@@ -35,7 +35,8 @@
 	 *
 	 * You are in a maze of twisty little headers all alike.
 	 */
-	debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
+	log_debug("offset=%x buf=%x, use_spi_flash=%d\n", (uint)offset,
+		  (uint)buf, use_spi_flash);
 	if (use_spi_flash) {
 		ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
 		if (ret)
@@ -52,16 +53,16 @@
 	fv = ptr;
 
 	/* Check the FV signature, _FVH */
-	debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
+	log_debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
 	if (fv->sign != EFI_FVH_SIGNATURE)
 		return log_msg_ret("Base FV signature", -EINVAL);
 
 	/* Go to the end of the FV header and align the address */
-	debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
+	log_debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
 	ptr += fv->ext_hdr_off;
 	exhdr = ptr;
 	ptr += ALIGN(exhdr->ext_hdr_size, 8);
-	debug("ptr=%x\n", ptr - (void *)buf);
+	log_debug("ptr=%x\n", ptr - (void *)buf);
 
 	/* Check the FFS GUID */
 	file_hdr = ptr;
@@ -71,7 +72,7 @@
 	ptr = file_hdr + 1;
 
 	raw = ptr;
-	debug("raw->type = %x\n", raw->type);
+	log_debug("raw->type = %x\n", raw->type);
 	if (raw->type != EFI_SECTION_RAW)
 		return log_msg_ret("Section type not RAW", -ENOEXEC);
 
@@ -80,13 +81,18 @@
 	fsp = ptr;
 
 	/* Check the FSPH header */
-	debug("fsp %x\n", (uint)fsp);
+	log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf,
+		  (void *)&fsp->fsp_silicon_init - (void *)buf);
 	if (fsp->sign != EFI_FSPH_SIGNATURE)
 		return log_msg_ret("Base FSPH signature", -EACCES);
 
 	base = (void *)fsp->img_base;
-	debug("Image base %x\n", (uint)base);
-	debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
+	log_debug("image base %x\n", (uint)base);
+	if (fsp->fsp_mem_init)
+		log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init);
+	else if (fsp->fsp_silicon_init)
+		log_debug("silicon_init offset %x\n",
+			  (uint)fsp->fsp_silicon_init);
 	if (use_spi_flash) {
 		ret = spi_flash_read_dm(dev, offset, size, base);
 		if (ret)

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index d2b6002..a00964c 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c

@@ -45,6 +45,42 @@
 
 #define COMMAND_LINE_SIZE	2048
 
+/**
+ * struct zboot_state - Current state of the boot
+ *
+ * @bzimage_addr: Address of the bzImage to boot
+ * @bzimage_size: Size of the bzImage, or 0 to detect this
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @load_address: Address where the bzImage is moved before booting, either
+ *	BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ *	DEFAULT_SETUP_BASE
+ * @cmdline: Address of 'override' command line, or 0 to use the one in the
+ *	setup block
+ */
+struct zboot_state {
+	ulong bzimage_addr;
+	ulong bzimage_size;
+	ulong initrd_addr;
+	ulong initrd_size;
+	ulong load_address;
+	struct boot_params *base_ptr;
+	ulong cmdline;
+} state;
+
+enum {
+	ZBOOT_STATE_START	= BIT(0),
+	ZBOOT_STATE_LOAD	= BIT(1),
+	ZBOOT_STATE_SETUP	= BIT(2),
+	ZBOOT_STATE_INFO	= BIT(3),
+	ZBOOT_STATE_GO		= BIT(4),
+
+	/* This one doesn't execute automatically, so stop the count before 5 */
+	ZBOOT_STATE_DUMP	= BIT(5),
+	ZBOOT_STATE_COUNT	= 5,
+};
+
 static void build_command_line(char *command_line, int auto_boot)
 {
 	char *env_command_line;
@@ -85,21 +121,23 @@
 	}
 }
 
-static int get_boot_protocol(struct setup_header *hdr)
+static int get_boot_protocol(struct setup_header *hdr, bool verbose)
 {
 	if (hdr->header == KERNEL_V2_MAGIC) {
-		printf("Magic signature found\n");
+		if (verbose)
+			printf("Magic signature found\n");
 		return hdr->version;
 	} else {
 		/* Very old kernel */
-		printf("Magic signature not found\n");
+		if (verbose)
+			printf("Magic signature not found\n");
 		return 0x0100;
 	}
 }
 
 static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob)
 {
-	int bootproto = get_boot_protocol(hdr);
+	int bootproto = get_boot_protocol(hdr, false);
 	struct setup_data *sd;
 	int size;
 
@@ -129,10 +167,24 @@
 	return 0;
 }
 
+static const char *get_kernel_version(struct boot_params *params,
+				      void *kernel_base)
+{
+	struct setup_header *hdr = &params->hdr;
+	int bootproto;
+
+	bootproto = get_boot_protocol(hdr, false);
+	if (bootproto < 0x0200 || hdr->setup_sects < 15)
+		return NULL;
+
+	return kernel_base + hdr->kernel_version + 0x200;
+}
+
 struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 				ulong *load_addressp)
 {
 	struct boot_params *setup_base;
+	const char *version;
 	int setup_size;
 	int bootproto;
 	int big_image;
@@ -160,21 +212,16 @@
 		printf("Error: Setup is too large (%d bytes)\n", setup_size);
 
 	/* determine boot protocol version */
-	bootproto = get_boot_protocol(hdr);
+	bootproto = get_boot_protocol(hdr, true);
 
 	printf("Using boot protocol version %x.%02x\n",
 	       (bootproto & 0xff00) >> 8, bootproto & 0xff);
 
-	if (bootproto >= 0x0200) {
-		if (hdr->setup_sects >= 15) {
-			printf("Linux kernel version %s\n",
-				(char *)params +
-				hdr->kernel_version + 0x200);
-		} else {
-			printf("Setup Sectors < 15 - "
-				"Cannot print kernel version.\n");
-		}
-	}
+	version = get_kernel_version(params, image);
+	if (version)
+		printf("Linux kernel version %s\n", version);
+	else
+		printf("Setup Sectors < 15 - Cannot print kernel version\n");
 
 	/* Determine image type */
 	big_image = (bootproto >= 0x0200) &&
@@ -240,10 +287,10 @@
 }
 
 int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
-		 unsigned long initrd_addr, unsigned long initrd_size)
+		 ulong initrd_addr, ulong initrd_size, ulong cmdline_force)
 {
 	struct setup_header *hdr = &setup_base->hdr;
-	int bootproto = get_boot_protocol(hdr);
+	int bootproto = get_boot_protocol(hdr, false);
 
 	setup_base->e820_entries = install_e820_map(
 		ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
@@ -253,8 +300,7 @@
 		setup_base->screen_info.cl_offset = COMMAND_LINE_OFFSET;
 	}
 	if (bootproto >= 0x0200) {
-		hdr->type_of_loader = 8;
-
+		hdr->type_of_loader = 0x80;	/* U-Boot version 0 */
 		if (initrd_addr) {
 			printf("Initial RAM disk at linear address "
 			       "0x%08lx, size %ld bytes\n",
@@ -282,40 +328,33 @@
 		}
 
 		/* build command line at COMMAND_LINE_OFFSET */
-		build_command_line(cmd_line, auto_boot);
+		if (cmdline_force)
+			strcpy(cmd_line, (char *)cmdline_force);
+		else
+			build_command_line(cmd_line, auto_boot);
 	}
 
-#ifdef CONFIG_INTEL_MID
-	if (bootproto >= 0x0207)
+	if (IS_ENABLED(CONFIG_INTEL_MID) && bootproto >= 0x0207)
 		hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
-#endif
 
-#ifdef CONFIG_GENERATE_ACPI_TABLE
-	setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr();
-#endif
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr();
 
 	setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0));
 	setup_video(&setup_base->screen_info);
 
-#ifdef CONFIG_EFI_STUB
-	setup_efi_info(&setup_base->efi_info);
-#endif
+	if (IS_ENABLED(CONFIG_EFI_STUB))
+		setup_efi_info(&setup_base->efi_info);
 
 	return 0;
 }
 
-int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
 {
-	struct boot_params *base_ptr;
-	void *bzImage_addr = NULL;
-	ulong load_address;
-	char *s;
-	ulong bzImage_size = 0;
-	ulong initrd_addr = 0;
-	ulong initrd_size = 0;
-
-	disable_interrupts();
+	const char *s;
 
+	memset(&state, '\0', sizeof(state));
 	if (argc >= 2) {
 		/* argv[1] holds the address of the bzImage */
 		s = argv[1];
@@ -324,39 +363,361 @@
 	}
 
 	if (s)
-		bzImage_addr = (void *)simple_strtoul(s, NULL, 16);
+		state.bzimage_addr = simple_strtoul(s, NULL, 16);
 
 	if (argc >= 3) {
 		/* argv[2] holds the size of the bzImage */
-		bzImage_size = simple_strtoul(argv[2], NULL, 16);
+		state.bzimage_size = simple_strtoul(argv[2], NULL, 16);
 	}
 
 	if (argc >= 4)
-		initrd_addr = simple_strtoul(argv[3], NULL, 16);
+		state.initrd_addr = simple_strtoul(argv[3], NULL, 16);
 	if (argc >= 5)
-		initrd_size = simple_strtoul(argv[4], NULL, 16);
+		state.initrd_size = simple_strtoul(argv[4], NULL, 16);
+	if (argc >= 6) {
+		/*
+		 * When the base_ptr is passed in, we assume that the image is
+		 * already loaded at the address given by argv[1] and therefore
+		 * the original bzImage is somewhere else, or not accessible.
+		 * In any case, we don't need access to the bzImage since all
+		 * the processing is assumed to be done.
+		 *
+		 * So set the base_ptr to the given address, use this arg as the
+		 * load address and set bzimage_addr to 0 so we know that it
+		 * cannot be proceesed (or processed again).
+		 */
+		state.base_ptr = (void *)simple_strtoul(argv[5], NULL, 16);
+		state.load_address = state.bzimage_addr;
+		state.bzimage_addr = 0;
+	}
+	if (argc >= 7)
+		state.cmdline = simple_strtoul(argv[6], NULL, 16);
 
-	/* Lets look for */
-	base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
+	return 0;
+}
+
+static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	struct boot_params *base_ptr;
+
+	if (state.base_ptr) {
+		struct boot_params *from = (struct boot_params *)state.base_ptr;
+
+		base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE;
+		printf("Building boot_params at 0x%8.8lx\n", (ulong)base_ptr);
+		memset(base_ptr, '\0', sizeof(*base_ptr));
+		base_ptr->hdr = from->hdr;
+	} else {
+		base_ptr = load_zimage((void *)state.bzimage_addr, state.bzimage_size,
+				       &state.load_address);
+		if (!base_ptr) {
+			puts("## Kernel loading failed ...\n");
+			return CMD_RET_FAILURE;
+		}
+	}
+	state.base_ptr = base_ptr;
+	if (env_set_hex("zbootbase", (ulong)base_ptr) ||
+	    env_set_hex("zbootaddr", state.load_address))
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	struct boot_params *base_ptr = state.base_ptr;
+	int ret;
 
 	if (!base_ptr) {
-		puts("## Kernel loading failed ...\n");
-		return -1;
+		printf("base is not set: use 'zboot load' first\n");
+		return CMD_RET_FAILURE;
 	}
-	if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
-			0, initrd_addr, initrd_size)) {
+	ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
+			   0, state.initrd_addr, state.initrd_size,
+			   state.cmdline);
+	if (ret) {
 		puts("Setting up boot parameters failed ...\n");
-		return -1;
+		return CMD_RET_FAILURE;
 	}
 
+	return 0;
+}
+
+static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	printf("Kernel loaded at %08lx, setup_base=%p\n",
+	       state.load_address, state.base_ptr);
+
+	return 0;
+}
+
+static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int ret;
+
+	disable_interrupts();
+
 	/* we assume that the kernel is in place */
-	return boot_linux_kernel((ulong)base_ptr, load_address, false);
+	ret = boot_linux_kernel((ulong)state.base_ptr, state.load_address,
+				false);
+	printf("Kernel returned! (err=%d)\n", ret);
+
+	return CMD_RET_FAILURE;
+}
+
+static void print_num(const char *name, ulong value)
+{
+	printf("%-20s: %lx\n", name, value);
 }
 
-U_BOOT_CMD(
-	zboot, 5, 0,	do_zboot,
-	"Boot bzImage",
-	"[addr] [size] [initrd addr] [initrd size]\n"
+static void print_num64(const char *name, u64 value)
+{
+	printf("%-20s: %llx\n", name, value);
+}
+
+static const char *const e820_type_name[E820_COUNT] = {
+	[E820_RAM] = "RAM",
+	[E820_RESERVED] = "Reserved",
+	[E820_ACPI] = "ACPI",
+	[E820_NVS] = "ACPI NVS",
+	[E820_UNUSABLE] = "Unusable",
+};
+
+static const char *const bootloader_id[] = {
+	"LILO",
+	"Loadlin",
+	"bootsect-loader",
+	"Syslinux",
+	"Etherboot/gPXE/iPXE",
+	"ELILO",
+	"undefined",
+	"GRUB",
+	"U-Boot",
+	"Xen",
+	"Gujin",
+	"Qemu",
+	"Arcturus Networks uCbootloader",
+	"kexec-tools",
+	"Extended",
+	"Special",
+	"Reserved",
+	"Minimal Linux Bootloader",
+	"OVMF UEFI virtualization stack",
+};
+
+struct flag_info {
+	uint bit;
+	const char *name;
+};
+
+static struct flag_info load_flags[] = {
+	{ LOADED_HIGH, "loaded-high" },
+	{ QUIET_FLAG, "quiet" },
+	{ KEEP_SEGMENTS, "keep-segments" },
+	{ CAN_USE_HEAP, "can-use-heap" },
+};
+
+static struct flag_info xload_flags[] = {
+	{ XLF_KERNEL_64, "64-bit-entry" },
+	{ XLF_CAN_BE_LOADED_ABOVE_4G, "can-load-above-4gb" },
+	{ XLF_EFI_HANDOVER_32, "32-efi-handoff" },
+	{ XLF_EFI_HANDOVER_64, "64-efi-handoff" },
+	{ XLF_EFI_KEXEC, "kexec-efi-runtime" },
+};
+
+static void print_flags(struct flag_info *flags, int count, uint value)
+{
+	int i;
+
+	printf("%-20s:", "");
+	for (i = 0; i < count; i++) {
+		uint mask = flags[i].bit;
+
+		if (value & mask)
+			printf(" %s", flags[i].name);
+	}
+	printf("\n");
+}
+
+static void show_loader(struct setup_header *hdr)
+{
+	bool version_valid = false;
+	int type, version;
+	const char *name;
+
+	type = hdr->type_of_loader >> 4;
+	version = hdr->type_of_loader & 0xf;
+	if (type == 0xe)
+		type = 0x10 + hdr->ext_loader_type;
+	version |= hdr->ext_loader_ver << 4;
+	if (!hdr->type_of_loader) {
+		name = "pre-2.00 bootloader";
+	} else if (hdr->type_of_loader == 0xff) {
+		name = "unknown";
+	} else if (type < ARRAY_SIZE(bootloader_id)) {
+		name = bootloader_id[type];
+		version_valid = true;
+	} else {
+		name = "undefined";
+	}
+	printf("%20s  %s", "", name);
+	if (version_valid)
+		printf(", version %x", version);
+	printf("\n");
+}
+
+int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct boot_params *base_ptr = state.base_ptr;
+	struct setup_header *hdr;
+	const char *version;
+	int i;
+
+	if (argc > 1)
+		base_ptr = (void *)simple_strtoul(argv[1], NULL, 16);
+	if (!base_ptr) {
+		printf("No zboot setup_base\n");
+		return CMD_RET_FAILURE;
+	}
+	printf("Setup located at %p:\n\n", base_ptr);
+	print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
+
+	printf("E820: %d entries\n", base_ptr->e820_entries);
+	if (base_ptr->e820_entries) {
+		printf("%18s  %16s  %s\n", "Addr", "Size", "Type");
+		for (i = 0; i < base_ptr->e820_entries; i++) {
+			struct e820_entry *entry = &base_ptr->e820_map[i];
+
+			printf("%12llx  %10llx  %s\n", entry->addr, entry->size,
+			       entry->type < E820_COUNT ?
+			       e820_type_name[entry->type] :
+			       simple_itoa(entry->type));
+		}
+	}
+
+	hdr = &base_ptr->hdr;
+	print_num("Setup sectors", hdr->setup_sects);
+	print_num("Root flags", hdr->root_flags);
+	print_num("Sys size", hdr->syssize);
+	print_num("RAM size", hdr->ram_size);
+	print_num("Video mode", hdr->vid_mode);
+	print_num("Root dev", hdr->root_dev);
+	print_num("Boot flag", hdr->boot_flag);
+	print_num("Jump", hdr->jump);
+	print_num("Header", hdr->header);
+	if (hdr->header == KERNEL_V2_MAGIC)
+		printf("%-20s  %s\n", "", "Kernel V2");
+	else
+		printf("%-20s  %s\n", "", "Ancient kernel, using version 100");
+	print_num("Version", hdr->version);
+	print_num("Real mode switch", hdr->realmode_swtch);
+	print_num("Start sys", hdr->start_sys);
+	print_num("Kernel version", hdr->kernel_version);
+	version = get_kernel_version(base_ptr, (void *)state.bzimage_addr);
+	if (version)
+		printf("   @%p: %s\n", version, version);
+	print_num("Type of loader", hdr->type_of_loader);
+	show_loader(hdr);
+	print_num("Load flags", hdr->loadflags);
+	print_flags(load_flags, ARRAY_SIZE(load_flags), hdr->loadflags);
+	print_num("Setup move size", hdr->setup_move_size);
+	print_num("Code32 start", hdr->code32_start);
+	print_num("Ramdisk image", hdr->ramdisk_image);
+	print_num("Ramdisk size", hdr->ramdisk_size);
+	print_num("Bootsect kludge", hdr->bootsect_kludge);
+	print_num("Heap end ptr", hdr->heap_end_ptr);
+	print_num("Ext loader ver", hdr->ext_loader_ver);
+	print_num("Ext loader type", hdr->ext_loader_type);
+	print_num("Command line ptr", hdr->cmd_line_ptr);
+	if (hdr->cmd_line_ptr) {
+		printf("   ");
+		/* Use puts() to avoid limits from CONFIG_SYS_PBSIZE */
+		puts((char *)(ulong)hdr->cmd_line_ptr);
+		printf("\n");
+	}
+	print_num("Initrd addr max", hdr->initrd_addr_max);
+	print_num("Kernel alignment", hdr->kernel_alignment);
+	print_num("Relocatable kernel", hdr->relocatable_kernel);
+	print_num("Min alignment", hdr->min_alignment);
+	if (hdr->min_alignment)
+		printf("%-20s: %x\n", "", 1 << hdr->min_alignment);
+	print_num("Xload flags", hdr->xloadflags);
+	print_flags(xload_flags, ARRAY_SIZE(xload_flags), hdr->xloadflags);
+	print_num("Cmdline size", hdr->cmdline_size);
+	print_num("Hardware subarch", hdr->hardware_subarch);
+	print_num64("HW subarch data", hdr->hardware_subarch_data);
+	print_num("Payload offset", hdr->payload_offset);
+	print_num("Payload length", hdr->payload_length);
+	print_num64("Setup data", hdr->setup_data);
+	print_num64("Pref address", hdr->pref_address);
+	print_num("Init size", hdr->init_size);
+	print_num("Handover offset", hdr->handover_offset);
+	if (get_boot_protocol(hdr, false) >= 0x215)
+		print_num("Kernel info offset", hdr->kernel_info_offset);
+
+	return 0;
+}
+
+/* Note: This defines the complete_zboot() function */
+U_BOOT_SUBCMDS(zboot,
+	U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""),
+	U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""),
+	U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""),
+	U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""),
+	U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""),
+	U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""),
+)
+
+int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[], int state_mask)
+{
+	int i;
+
+	for (i = 0; i < ZBOOT_STATE_COUNT; i++) {
+		struct cmd_tbl *cmd = &zboot_subcmds[i];
+		int mask = 1 << i;
+		int ret;
+
+		if (mask & state_mask) {
+			ret = cmd->cmd(cmd, flag, argc, argv);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[], int *repeatable)
+{
+	/* determine if we have a sub command */
+	if (argc > 1) {
+		char *endp;
+
+		simple_strtoul(argv[1], &endp, 16);
+		/*
+		 * endp pointing to nul means that argv[1] was just a valid
+		 * number, so pass it along to the normal processing
+		 */
+		if (*endp)
+			return do_zboot(cmdtp, flag, argc, argv, repeatable);
+	}
+
+	do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START |
+			ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP |
+			ZBOOT_STATE_INFO | ZBOOT_STATE_GO);
+
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMDREP_COMPLETE(
+	zboot, 8, do_zboot_parent, "Boot bzImage",
+	"[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n"
 	"      addr -        The optional starting address of the bzimage.\n"
 	"                    If not set it defaults to the environment\n"
 	"                    variable \"fileaddr\".\n"
@@ -364,4 +725,17 @@
 	"                    zero.\n"
 	"      initrd addr - The address of the initrd image to use, if any.\n"
 	"      initrd size - The size of the initrd image to use, if any.\n"
+	"      setup -       The address of the kernel setup region, if this\n"
+	"                    is not at addr\n"
+	"      cmdline -     The address of the kernel command line, to\n"
+	"                    override U-Boot's normal cmdline generation\n"
+	"\n"
+	"Sub-commands to do part of the zboot sequence:\n"
+	"\tstart [addr [arg ...]] - specify arguments\n"
+	"\tload   - load OS image\n"
+	"\tsetup  - set up table\n"
+	"\tinfo   - show summary info\n"
+	"\tgo     - start OS\n"
+	"\tdump [addr]    - dump info (optional address of boot params)",
+	complete_zboot
 );

diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
index ceee59b..c59df7d 100644
--- a/arch/xtensa/lib/Makefile
+++ b/arch/xtensa/lib/Makefile

@@ -5,4 +5,4 @@
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 
-obj-y 	+= cache.o misc.o relocate.o time.o bdinfo.o
+obj-y 	+= cache.o misc.o relocate.o time.o

diff --git a/arch/xtensa/lib/bdinfo.c b/arch/xtensa/lib/bdinfo.c
deleted file mode 100644
index 4ec8529..0000000
--- a/arch/xtensa/lib/bdinfo.c
+++ /dev/null

@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * XTENSA-specific information for the 'bd' command
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <init.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_setup_bdinfo(void)
-{
-	struct bd_info *bd = gd->bd;
-
-	bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
-	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-
-	return 0;
-}

diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c
index 458eaf9..0e56450 100644
--- a/arch/xtensa/lib/bootm.c
+++ b/arch/xtensa/lib/bootm.c

@@ -41,15 +41,14 @@
 
 static struct bp_tag *setup_memory_tag(struct bp_tag *params)
 {
-	struct bd_info *bd = gd->bd;
 	struct meminfo *mem;
 
 	params->id = BP_TAG_MEMORY;
 	params->size = sizeof(struct meminfo);
 	mem = (struct meminfo *)params->data;
 	mem->type = MEMORY_TYPE_CONVENTIONAL;
-	mem->start = bd->bi_memstart;
-	mem->end = bd->bi_memstart + bd->bi_memsize;
+	mem->start = PHYSADDR(gd->ram_base);
+	mem->end = PHYSADDR(gd->ram_base + gd->ram_size);
 
 	printf("   MEMORY:          tag:0x%04x, type:0X%lx, start:0X%lx, end:0X%lx\n",
 	       BP_TAG_MEMORY, mem->type, mem->start, mem->end);

diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 5416a5b..0fd9532 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c

@@ -83,8 +83,6 @@
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig
index 8ce21f9..cb73f98 100644
--- a/board/broadcom/bcmns3/Kconfig
+++ b/board/broadcom/bcmns3/Kconfig

@@ -12,4 +12,11 @@
 config SYS_CONFIG_NAME
 	default "bcm_ns3"
 
+config CMD_BCM_EXT_UTILS
+	bool "Enable Broadcom-specific U-Boot commands"
+	default y
+	help
+	  Enable Broadcom specific U-Boot commands such as error log setup
+	  command or any other commands specific to NS3 platform.
+
 endif

diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 0357cd0..10ae344 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c

@@ -12,6 +12,7 @@
 #include <asm/armv8/mmu.h>
 #include <asm/arch-bcmns3/bl33_info.h>
 #include <dt-bindings/memory/bcm-ns3-mc.h>
+#include <broadcom/chimp.h>
 
 /* Default reset-level = 3 and strap-val = 0 */
 #define L3_RESET	30
@@ -210,8 +211,24 @@
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *fdt, struct bd_info *bd)
 {
+	u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
+
 	gic_lpi_tables_init();
 
+	/*
+	 * Check for chimp handshake status.
+	 * Zero timeout value will actually fall to default timeout.
+	 *
+	 * System boot is independent of chimp handshake.
+	 * chimp handshake failure is not a catastrophic error.
+	 * Hence continue booting if chimp handshake fails.
+	 */
+	chimp_handshake_status_optee(0, &chimp_hs);
+	if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
+		printf("ChiMP handshake successful\n");
+	else
+		printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
+
 	return mem_info_parse_fixup(fdt);
 }
 #endif /* CONFIG_OF_BOARD_SETUP */

diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 4b49b6e..5811c43 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c

@@ -49,11 +49,6 @@
 	return 0;
 }
 
-int dram_init_banksize(void)
-{
-	return 0;
-}
-
 int board_postclk_init(void)
 {
 	/*

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index b0e109f..04e04a6 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile

@@ -53,7 +53,6 @@
 obj-$(CONFIG_P2020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
-obj-$(CONFIG_TARGET_P5020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o

diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index 98b1add..e92b0d0 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig

@@ -28,21 +28,6 @@
 
 endif
 
-if TARGET_P5020DS
-
-config SYS_BOARD
-	default "corenet_ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P5020DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
 if TARGET_P5040DS
 
 config SYS_BOARD

diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 708e812..e22cf70 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS

@@ -6,22 +6,13 @@
 F:	configs/P3041DS_defconfig
 F:	configs/P3041DS_NAND_defconfig
 F:	configs/P3041DS_SDCARD_defconfig
-F:	configs/P3041DS_SECURE_BOOT_defconfig
 F:	configs/P3041DS_SPIFLASH_defconfig
 F:	configs/P3041DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P4080DS.h
 F:	configs/P4080DS_defconfig
 F:	configs/P4080DS_SDCARD_defconfig
-F:	configs/P4080DS_SECURE_BOOT_defconfig
 F:	configs/P4080DS_SPIFLASH_defconfig
 F:	configs/P4080DS_SRIO_PCIE_BOOT_defconfig
-F:	include/configs/P5020DS.h
-F:	configs/P5020DS_defconfig
-F:	configs/P5020DS_NAND_defconfig
-F:	configs/P5020DS_SDCARD_defconfig
-F:	configs/P5020DS_SECURE_BOOT_defconfig
-F:	configs/P5020DS_SPIFLASH_defconfig
-F:	configs/P5020DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P5040DS.h
 F:	configs/P5040DS_defconfig
 F:	configs/P5040DS_NAND_defconfig
@@ -33,5 +24,4 @@
 M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
-F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
 F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig

diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 98322b2..4d62fc9 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile

@@ -8,9 +8,7 @@
 obj-y	+= ddr.o
 obj-$(CONFIG_TARGET_P3041DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P4080DS)	+= eth_p4080.o
-obj-$(CONFIG_TARGET_P5020DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P5040DS)	+= eth_superhydra.o
 obj-$(CONFIG_TARGET_P3041DS)	+= p3041ds_ddr.o
 obj-$(CONFIG_TARGET_P4080DS)	+= p4080ds_ddr.o
-obj-$(CONFIG_TARGET_P5020DS)	+= p5020ds_ddr.o
 obj-$(CONFIG_TARGET_P5040DS)	+= p5040ds_ddr.o

diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
deleted file mode 100644
index 112733b..0000000
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ /dev/null

@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
-	{0, 0, NULL}
-};

diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
deleted file mode 100644
index b09e409..0000000
--- a/board/freescale/corenet_ds/rcw_p5020ds.cfg
+++ /dev/null

@@ -1,11 +0,0 @@
-#
-# Default RCW for P5020DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0C540000 00000000 1E120000 00000000
-D8984A01 03002000 58000000 41000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000

diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
index c9f7fa3..6e940dd 100644
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ b/board/freescale/p1010rdb/MAINTAINERS

@@ -4,30 +4,18 @@
 F:	board/freescale/p1010rdb/
 F:	include/configs/P1010RDB.h
 F:	configs/P1010RDB-PA_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NAND_defconfig
-F:	configs/P1010RDB-PA_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NOR_defconfig
-F:	configs/P1010RDB-PA_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_SDCARD_defconfig
 F:	configs/P1010RDB-PA_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NAND_defconfig
-F:	configs/P1010RDB-PB_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NOR_defconfig
-F:	configs/P1010RDB-PB_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_SDCARD_defconfig
 F:	configs/P1010RDB-PB_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index accf2f2..4c3a03e 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c

@@ -484,6 +484,7 @@
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@
 
 	return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void fdt_del_flexcan(void *blob)

diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 4ee4573..fbaa6a6 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c

@@ -69,8 +69,6 @@
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig
deleted file mode 100644
index 1e4cd10..0000000
--- a/board/freescale/p1023rdb/Kconfig
+++ /dev/null

@@ -1,12 +0,0 @@
-if TARGET_P1023RDB
-
-config SYS_BOARD
-	default "p1023rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P1023RDB"
-
-endif

diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS
deleted file mode 100644
index c06bac6..0000000
--- a/board/freescale/p1023rdb/MAINTAINERS
+++ /dev/null

@@ -1,6 +0,0 @@
-P1023RDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/p1023rdb/
-F:	include/configs/P1023RDB.h
-F:	configs/P1023RDB_defconfig

diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
deleted file mode 100644
index 78dc5d5..0000000
--- a/board/freescale/p1023rdb/Makefile
+++ /dev/null

@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y	+= p1023rdb.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o

diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
deleted file mode 100644
index dc7a909..0000000
--- a/board/freescale/p1023rdb/ddr.c
+++ /dev/null

@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* CONFIG_SYS_DDR_RAW_TIMING */
-/*
- * Hynix H5TQ1G83TFR-H9C
- */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 536870912u,
-	.capacity = 536870912u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 14,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1875,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 18000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}

diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
deleted file mode 100644
index 405fcd7..0000000
--- a/board/freescale/p1023rdb/law.c
+++ /dev/null

@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
-		LAW_TRGT_IF_DPAA_SWP_SRAM),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
deleted file mode 100644
index b70ff68..0000000
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ /dev/null

@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Authors:  Roy Zang <tie-fei.zang@freescale.com>
- *           Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_portals.h>
-#include <fsl_qbman.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	/* Set ABSWP to implement conversion of addresses in the LBC */
-	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("Board: P1023 RDB\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	setup_qbman_portals();
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-	return gd->mem_clk;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-
-	/*
-	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
-	 * is not correct.
-	 */
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
-
-	fm_info_set_mdio(FM1_DTSEC1,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-	fm_info_set_mdio(FM1_DTSEC2,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
-#ifdef CONFIG_FMAN_ENET
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-#endif
-	return 0;
-}
-#endif

diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
deleted file mode 100644
index 9f0314d..0000000
--- a/board/freescale/p1023rdb/tlb.c
+++ /dev/null

@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_4M, 1),
-
-	/* W**G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_1M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_16K, 1),
-
-#ifdef CONFIG_SYS_RAMBOOT
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
-		      CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 12, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);

diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index 2f9640b..cd36150 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig

@@ -1,10 +1,5 @@
-if TARGET_P1020MBG		|| \
-	TARGET_P1020RDB_PC	|| \
+if	TARGET_P1020RDB_PC	|| \
 	TARGET_P1020RDB_PD	|| \
-	TARGET_P1020UTM		|| \
-	TARGET_P1021RDB		|| \
-	TARGET_P1024RDB		|| \
-	TARGET_P1025RDB		|| \
 	TARGET_P2020RDB
 
 config SYS_BOARD

diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index c2e9247..b737b09 100644
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS

@@ -3,10 +3,6 @@
 S:	Maintained
 F:	board/freescale/p1_p2_rdb_pc/
 F:	include/configs/p1_p2_rdb_pc.h
-F:	configs/P1020MBG-PC_defconfig
-F:	configs/P1020MBG-PC_36BIT_defconfig
-F:	configs/P1020MBG-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020MBG-PC_SDCARD_defconfig
 F:	configs/P1020RDB-PC_defconfig
 F:	configs/P1020RDB-PC_36BIT_defconfig
 F:	configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -19,28 +15,6 @@
 F:	configs/P1020RDB-PD_NAND_defconfig
 F:	configs/P1020RDB-PD_SDCARD_defconfig
 F:	configs/P1020RDB-PD_SPIFLASH_defconfig
-F:	configs/P1020UTM-PC_defconfig
-F:	configs/P1020UTM-PC_36BIT_defconfig
-F:	configs/P1020UTM-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020UTM-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_defconfig
-F:	configs/P1021RDB-PC_36BIT_defconfig
-F:	configs/P1021RDB-PC_36BIT_NAND_defconfig
-F:	configs/P1021RDB-PC_36BIT_SDCARD_defconfig
-F:	configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
-F:	configs/P1021RDB-PC_NAND_defconfig
-F:	configs/P1021RDB-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_SPIFLASH_defconfig
-F:	configs/P1024RDB_defconfig
-F:	configs/P1024RDB_36BIT_defconfig
-F:	configs/P1024RDB_NAND_defconfig
-F:	configs/P1024RDB_SDCARD_defconfig
-F:	configs/P1024RDB_SPIFLASH_defconfig
-F:	configs/P1025RDB_defconfig
-F:	configs/P1025RDB_36BIT_defconfig
-F:	configs/P1025RDB_NAND_defconfig
-F:	configs/P1025RDB_SDCARD_defconfig
-F:	configs/P1025RDB_SPIFLASH_defconfig
 F:	configs/P2020RDB-PC_defconfig
 F:	configs/P2020RDB-PC_36BIT_defconfig
 F:	configs/P2020RDB-PC_36BIT_NAND_defconfig

diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index b85cf02..86ff04e 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README

@@ -4,10 +4,8 @@
     P1020MSBG-PC
     P1020RDB-PC
     P1020RDB-PD
-    P1020UTM-PC
     P1021RDB-PC
     P1024RDB
-    P1025RDB
     P2020RDB-PC
 
 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC

diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 2346f6a..be803dd 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c

@@ -14,9 +14,7 @@
 #include <asm/fsl_law.h>
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if	defined(CONFIG_P1020RDB_PROTO) || \
-	defined(CONFIG_TARGET_P1021RDB) || \
-	defined(CONFIG_TARGET_P1020UTM)
+#if	defined(CONFIG_P1020RDB_PROTO)
 /* Micron MT41J256M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,
@@ -146,8 +144,7 @@
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif	defined(CONFIG_TARGET_P1024RDB) || \
-	defined(CONFIG_TARGET_P1025RDB)
+#elif	defined(CONFIG_TARGET_P1024RDB)
 /*
  * Samsung K4B2G0846C-HCH9
  * The following timing are for "downshift"

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b3..4584f01 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c

@@ -45,68 +45,12 @@
 #define GPIO_SLIC_PIN		30
 #define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-#define GPIO_DDR_RST_PORT	1
-#define GPIO_DDR_RST_PIN	8
-#define GPIO_DDR_RST_DATA	(1 << (31 - GPIO_DDR_RST_PIN))
-
-#define GPIO_2BIT_MASK		(0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-#define PCA_IOPORT_I2C_ADDR		0x23
-#define PCA_IOPORT_OUTPUT_CMD		0x2
-#define PCA_IOPORT_CFG_CMD		0x6
-#define PCA_IOPORT_QE_PIN_ENABLE	0xf8
-#define PCA_IOPORT_QE_TDM_ENABLE	0xf6
-#endif
-
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* GPIO */
 	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
-#endif
 	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
 	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
 	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
-
-#ifdef CONFIG_TARGET_P1025RDB
-	/* QE_MUX_MDC */
-	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
-
-	/* QE_MUX_MDIO */
-	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
-
-	/* UCC_1_MII */
-	{0, 23, 2, 0, 2}, /* CLK12 */
-	{0, 24, 2, 0, 1}, /* CLK9 */
-	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
-	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
-	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
-	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
-	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
-	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
-	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
-	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
-	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
-	{0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
-	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
-	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
-	{0, 17, 2, 0, 2}, /* ENET1_CRS    */
-	{0, 16, 2, 0, 2}, /* ENET1_COL    */
-
-	/* UCC_5_RMII */
-	{1, 11, 2, 0, 1}, /* CLK13 */
-	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
-	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
-	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
-	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
-	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
-	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
-	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
-#endif
-
 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 };
 #endif
@@ -156,16 +100,6 @@
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	/* reset DDR3 */
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	/* disable CE_PB8 */
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
-#endif
 	/* Enable VSC7385 switch */
 	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
 
@@ -316,6 +250,10 @@
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+	unsigned int vscfw_addr;
+	char *tmp;
+#endif
 
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -338,9 +276,24 @@
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+	/* If a VSC7385 microcode image is present, then upload it. */
+	tmp = env_get("vscfw_addr");
+	if (tmp) {
+		vscfw_addr = simple_strtoul(tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *)vscfw_addr,
+					    CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else {
+		puts("No address specified for VSC7385 microcode.\n");
+	}
+#endif
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 	struct fsl_pq_mdio_info mdio_info;
@@ -348,10 +301,6 @@
 	ccsr_gur_t *gur __attribute__((unused)) =
 		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int num = 0;
-#ifdef CONFIG_VSC7385_ENET
-	char *tmp;
-	unsigned int vscfw_addr;
-#endif
 
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +324,6 @@
 		return 0;
 	}
 
-#ifdef CONFIG_VSC7385_ENET
-	/* If a VSC7385 microcode image is present, then upload it. */
-	tmp = env_get("vscfw_addr");
-	if (tmp) {
-		vscfw_addr = simple_strtoul(tmp, NULL, 16);
-		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
-		if (vsc7385_upload_firmware((void *) vscfw_addr,
-					CONFIG_VSC7385_IMAGE_SIZE))
-			puts("Failure uploading VSC7385 microcode.\n");
-	} else
-		puts("No address specified for VSC7385 microcode.\n");
-#endif
-
 	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 	mdio_info.name = DEFAULT_MII_NAME;
 
@@ -405,50 +341,6 @@
 
 	return pci_eth_init(bis);
 }
-
-#if defined(CONFIG_QE) && \
-	(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
-static void fdt_board_fixup_qe_pins(void *blob)
-{
-	unsigned int oldbus;
-	u8 val8;
-	int node;
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	if (hwconfig("qe")) {
-		/* For QE and eLBC pins multiplexing,
-		 * there is a PCA9555 device on P1025RDB.
-		 * It control the multiplex pins' functions,
-		 * and setting the PCA9555 can switch the
-		 * function between QE and eLBC.
-		 */
-		oldbus = i2c_get_bus_num();
-		i2c_set_bus_num(0);
-		if (hwconfig("tdm"))
-			val8 = PCA_IOPORT_QE_TDM_ENABLE;
-		else
-			val8 = PCA_IOPORT_QE_PIN_ENABLE;
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
-				1, &val8, 1);
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
-				1, &val8, 1);
-		i2c_set_bus_num(oldbus);
-		/* if run QE TDM, Set ABSWP to implement
-		 * conversion of addresses in the eLBC.
-		 */
-		if (hwconfig("tdm")) {
-			set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
-			set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
-			setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-		}
-	} else {
-		node = fdt_path_offset(blob, "/qe");
-		if (node >= 0)
-			fdt_del_node(blob, node);
-	}
-
-	return;
-}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -478,9 +370,6 @@
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 			sizeof("okay"), 0);
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-	fdt_board_fixup_qe_pins(blob);
-#endif
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB)

diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index e76c3e8..8aceceb 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c

@@ -75,8 +75,6 @@
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 14971f0..fcd7a55 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c

@@ -84,13 +84,13 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
-#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 	/* 2G DDR on P1020MBG, map the second 1G */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* TARGET_P1020MBG */
+#endif
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR

diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da442fc..09dd88a 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c

@@ -103,8 +103,6 @@
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index f83d69b..e792295 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c

@@ -94,8 +94,6 @@
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index c197884..d8c2bbe 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c

@@ -102,8 +102,6 @@
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 07aab63..c64bd87 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c

@@ -72,8 +72,6 @@
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 64d2753..9aa0a9b 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c

@@ -75,8 +75,6 @@
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();

diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig
index 2767195..53c651c 100644
--- a/board/google/chromebook_coral/Kconfig
+++ b/board/google/chromebook_coral/Kconfig

@@ -23,7 +23,7 @@
 	select BOARD_ROMSIZE_KB_16384
 
 config PCIE_ECAM_BASE
-	default 0xf0000000
+	default 0xe0000000
 
 config EARLY_POST_CROS_EC
 	bool "Enable early post to Chrome OS EC"

diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile
index 6a27ce3..f7a0ca6 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile

@@ -3,3 +3,4 @@
 # Copyright 2019 Google LLC
 
 obj-y	+= coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o

diff --git a/board/google/chromebook_coral/baseboard_dptf.asl b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 0000000..5da963a
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Battery"
+#define DPTF_TSR0_PASSIVE	120
+#define DPTF_TSR0_CRITICAL	125
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Ambient"
+#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Charger"
+#define DPTF_TSR2_PASSIVE	58
+#define DPTF_TSR2_CRITICAL	90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		12000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})

diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 12d4fe6..f5ae482 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c

@@ -4,7 +4,24 @@
  */
 
 #include <common.h>
+#include <bloblist.h>
 #include <command.h>
+#include <dm.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <asm-generic/gpio.h>
+#include <asm/acpi_nhlt.h>
+#include <asm/intel_gnvs.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/acpi.h>
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+	const char *linux_name;
+	enum cros_gpio_t type;
+	int gpio_num;
+	int flags;
+};
 
 int arch_misc_init(void)
 {
@@ -18,3 +35,122 @@
 
 	return 0;
 }
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+		      enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+	struct udevice *pinctrl;
+	struct gpio_desc desc;
+	int ret;
+
+	ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
+	if (ret == -ENOTBLK)
+		info->gpio_num = CROS_GPIO_VIRTUAL;
+	else if (ret)
+		return log_msg_ret("gpio", ret);
+	else
+		info->gpio_num = desc.offset;
+	info->linux_name = dev_read_string(desc.dev, "linux-name");
+	if (!info->linux_name)
+		return log_msg_ret("linux-name", -ENOENT);
+	info->type = type;
+	/* Get ACPI pin from GPIO library if available */
+	if (info->gpio_num != CROS_GPIO_VIRTUAL) {
+		pinctrl = dev_get_parent(desc.dev);
+		info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
+							    info->gpio_num);
+	}
+	info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
+		CROS_GPIO_ACTIVE_HIGH;
+
+	return 0;
+}
+
+static int chromeos_acpi_gpio_generate(const struct udevice *dev,
+				       struct acpi_ctx *ctx)
+{
+	struct cros_gpio_info info[3];
+	int count, i;
+	int ret;
+
+	count = 3;
+	ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
+				&info[1]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
+				&info[2]);
+	if (ret)
+		return log_msg_ret("rec", ret);
+	acpigen_write_scope(ctx, "\\");
+	acpigen_write_name(ctx, "OIPG");
+	acpigen_write_package(ctx, count);
+	for (i = 0; i < count; i++) {
+		acpigen_write_package(ctx, 4);
+		acpigen_write_integer(ctx, info[i].type);
+		acpigen_write_integer(ctx, info[i].flags);
+		acpigen_write_integer(ctx, info[i].gpio_num);
+		acpigen_write_string(ctx, info[i].linux_name);
+		acpigen_pop_len(ctx);
+	}
+
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+static int coral_write_acpi_tables(const struct udevice *dev,
+				   struct acpi_ctx *ctx)
+{
+	struct acpi_global_nvs *gnvs;
+	struct nhlt *nhlt;
+	const char *oem_id = "coral";
+	const char *oem_table_id = "coral";
+	u32 oem_revision = 3;
+	int ret;
+
+	gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs));
+	if (!gnvs)
+		return log_msg_ret("bloblist", -ENOENT);
+
+	nhlt = nhlt_init();
+	if (!nhlt)
+		return -ENOMEM;
+
+	log_debug("Setting up NHLT\n");
+	ret = acpi_setup_nhlt(ctx, nhlt);
+	if (ret)
+		return log_msg_ret("setup", ret);
+
+	/* Update NHLT GNVS Data */
+	gnvs->nhla = (uintptr_t)ctx->current;
+	gnvs->nhll = nhlt_current_size(nhlt);
+
+	ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id,
+					   oem_revision);
+	if (ret)
+		return log_msg_ret("serialise", ret);
+
+	return 0;
+}
+
+struct acpi_ops coral_acpi_ops = {
+	.write_tables	= coral_write_acpi_tables,
+	.inject_dsdt	= chromeos_acpi_gpio_generate,
+};
+
+static const struct udevice_id coral_ids[] = {
+	{ .compatible = "google,coral" },
+	{ }
+};
+
+U_BOOT_DRIVER(coral_drv) = {
+	.name		= "coral",
+	.id		= UCLASS_BOARD,
+	.of_match	= coral_ids,
+	ACPI_OPS_PTR(&coral_acpi_ops)
+};

diff --git a/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index 0000000..46c0efb
--- /dev/null
+++ b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
Binary files differ

diff --git a/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
index 0000000..6a7f2ce
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
Binary files differ

diff --git a/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
index 0000000..71d7648
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
Binary files differ

diff --git a/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index 0000000..142ab35
--- /dev/null
+++ b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
Binary files differ

diff --git a/board/google/chromebook_coral/dsdt.asl b/board/google/chromebook_coral/dsdt.asl
new file mode 100644
index 0000000..b51e0b0
--- /dev/null
+++ b/board/google/chromebook_coral/dsdt.asl

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "variant_ec.h"
+#include "variant_gpio.h"
+#include <acpi/acpi_table.h>
+#include <asm/acpi/global_nvs.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	OEM_TABLE_ID,
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <asm/arch/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <asm/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <asm/arch/acpi/northbridge.asl>
+			#include <asm/arch/acpi/southbridge.asl>
+			#include <asm/arch/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <asm/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <asm/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <asm/acpi/cros_ec/superio.asl>
+		/* ACPI code for EC functions */
+		#include <asm/acpi/cros_ec/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include "variant_dptf.asl"
+		/* Include soc specific DPTF changes */
+		#include <asm/arch/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <asm/acpi/dptf/dptf.asl>
+	}
+}

diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat


diff --git a/board/google/chromebook_coral/variant_dptf.asl b/board/google/chromebook_coral/variant_dptf.asl
new file mode 100644
index 0000000..943ebea
--- /dev/null
+++ b/board/google/chromebook_coral/variant_dptf.asl

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "baseboard_dptf.asl"

diff --git a/board/google/chromebook_coral/variant_ec.h b/board/google/chromebook_coral/variant_ec.h
new file mode 100644
index 0000000..7d5e1a6
--- /dev/null
+++ b/board/google/chromebook_coral/variant_ec.h

@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+/*
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include "variant_gpio.h"
+#include <ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif

diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h
new file mode 100644
index 0000000..f516d88
--- /dev/null
+++ b/board/google/chromebook_coral/variant_gpio.h

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <asm/arch/gpio.h>
+#include <ec_commands.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI	GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI	GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE	GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP	GPIO_75
+#define GPIO_EC_IN_RW	GPIO_41
+/* Determine if board is in final shipping mode. */
+#define GPIO_SHIP_MODE	GPIO_10
+
+/*  Memory SKU GPIOs. */
+#define MEM_CONFIG3	GPIO_45
+#define MEM_CONFIG2	GPIO_38
+#define MEM_CONFIG1	GPIO_102
+#define MEM_CONFIG0	GPIO_101
+
+/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
+#define DMIC_CONFIG_PIN	GPIO_17
+
+#ifndef __ASSEMBLY__
+
+enum cros_gpio_t {
+	CROS_GPIO_REC = 1,	 /* Recovery */
+
+	/* Developer; * deprecated (chromium:942901) */
+	CROS_GPIO_DEPRECATED_DEV = 2,
+	CROS_GPIO_WP = 3,	/* Write Protect */
+	CROS_GPIO_PE = 4,	/* Phase enforcement for final product */
+
+	CROS_GPIO_ACTIVE_LOW = 0,
+	CROS_GPIO_ACTIVE_HIGH = 1,
+
+	CROS_GPIO_VIRTUAL = -1,
+};
+#endif
+
+#endif /* BASEBOARD_GPIO_H */

diff --git a/board/intel/edison/edison-environment.txt b/board/intel/edison/edison-environment.txt
new file mode 100644
index 0000000..afe0092
--- /dev/null
+++ b/board/intel/edison/edison-environment.txt

@@ -0,0 +1,48 @@
+partitions=uuid_disk=${uuid_disk};name=u-boot0,start=1MiB,size=2MiB,uuid=${uuid_uboot0};name=u-boot-env0,size=1MiB,uuid=${uuid_uboot_env0};name=u-boot1,size=2MiB,uuid=${uuid_uboot1};name=u-boot-env1,size=1MiB,uuid=${uuid_uboot_env1};name=factory,size=1MiB,uuid=${uuid_factory};name=panic,size=24MiB,uuid=${uuid_panic};name=boot,size=32MiB,uuid=${uuid_boot};name=rootfs,size=1536MiB,uuid=${uuid_rootfs};name=update,size=768MiB,uuid=${uuid_update};name=home,size=-,uuid=${uuid_home};
+do_dfu_alt_info_mmc=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2;u-boot0 part 0 1;u-boot-env0 part 0 2;u-boot1 part 0 3;u-boot-env1 part 0 4;boot part 0 7;rootfs part 0 8;update part 0 9;home part 0 10;vmlinuz fat 0 7;initrd fat 0 7"
+dfu_alt_info_ram=kernel ram ${loadaddr} 0x800000
+do_dfu_alt_info_ifwi=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2"
+dfu_alt_info_reset=reset ram 0x0 0x0
+bootargs_console=console=ttyMFD2 earlyprintk=ttyMFD2,keep
+bootargs_debug=loglevel=4
+do_bootargs_rootfs=setenv bootargs_rootfs rootwait root=PARTUUID=${uuid_rootfs} rootfstype=ext4
+first_install_retry=0
+first_install_max_retries=3
+ota_update_retry=0
+ota_update_max_retries=3
+audio_codec_name=audio_codec="dummy"
+do_audio_support=setenv audio_support platform_mrfld_audio.${audio_codec_name}
+do_compute_target=if itest.b ${first_install_retry} -gt ${first_install_max_retries} || itest.b ${ota_update_retry} -gt ${ota_update_max_retries}; then echo "Switch to Rescue target"; setenv bootargs_target rescue; saveenv; fi
+mmc-bootargs=run do_bootargs_rootfs; run do_audio_support; setenv bootargs ${bootargs_rootfs} ${bootargs_console} ${bootargs_debug} g_multi.ethernet_config=${bootargs_ethconfig} systemd.unit=${bootargs_target}.target hardware_id=${hardware_id} g_multi.iSerialNumber=${serial#} g_multi.dev_addr=${usb0addr} ${audio_support}
+loadaddr=0x100000
+load_kernel=fatload mmc 0:7 ${loadaddr} vmlinuz
+do_partition_done=0
+do_partition=if itest.b ${do_partition_done} -eq 1; then echo "Partitioning already done..."; else run do_force_partition ; fi
+do_force_partition=echo "Partitioning using GPT"; gpt write mmc 0 ${partitions} ; mmc rescan; setenv do_partition_done 1 ; saveenv
+do_flash_ifwi=run do_dfu_alt_info_ifwi ; dfu 0 mmc 0 $dfu_to_sec
+do_flash_os=if itest.b ${do_flash_os_done} -eq 1 ; then echo "Flashing already done..." ; else run do_force_flash_os; fi
+do_force_flash_os=run do_dfu_alt_info_mmc ; sleep 1 ; setenv do_flash_os_done 1 ; saveenv ; dfu 0 mmc 0 $dfu_to_sec
+do_flashall=run do_partition;run do_flash_ifwi;run do_flash_os
+do_dnx=setenv dfu_alt_info ${dfu_alt_info_ram};dfu 0 ram 0 ram;run bootcmd
+init_dfu=run do_dfu_alt_info_mmc ; saveenv
+bootcmd=echo "Target:${target_name}"; run do_partition; run do_handle_bootargs_mode;
+do_handle_bootargs_mode=run do_preprocess_bootargs_mode; if itest.s $bootargs_mode == "ota" ; then run do_ota; fi; if itest.s $bootargs_mode == "boot" ; then run do_boot; fi; if itest.s $bootargs_mode == "flash"; then run do_flash; fi; run do_fallback; exit;
+do_preprocess_bootargs_mode=if env exists bootargs_mode ; then ; else setenv bootargs_mode "boot" ;fi;
+do_fallback=echo "Unknown boot mode: $bootargs_mode"; env delete -f bootargs_mode; saveenv; echo "Resetting to default boot mode and reboot..."; reset;
+do_boot=run boot_target_cmd;
+do_flash=run do_force_flash_os;
+ota_done=0
+ota_script_addr=0x100000
+do_ota_init=setenv ota_status 1 ; env delete -f bootargs_mode
+do_load_ota_scr=if fatload mmc 0:9 $ota_script_addr ota_update.scr ; then setenv ota_status 0 ; else setenv ota_status 1 ; fi
+do_source_ota_scr=if test $ota_status -eq 0 ; then if source $ota_script_addr ; then setenv ota_status 0 ; else setenv ota_status 2 ; fi ; fi
+do_ota_clean=saveenv ; reset
+do_ota=run do_ota_init ; run do_load_ota_scr ; run do_source_ota_scr ; run do_ota_clean
+target_name=blank
+bootdelay=1
+do_flash_os_done=1
+bootargs_target=multi-user
+bootargs_ethconfig=cdc
+dfu_to_sec=3
+do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec
+boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr}

diff --git a/board/intel/edison/edison-osip.dat b/board/intel/edison/edison-osip.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/board/intel/edison/edison-osip.dat


diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index 94075ce..bbafabd 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig

@@ -1,3 +1,20 @@
+menu "KM 83xx Options"
+	depends on MPC83xx
+
+config KM_ENABLE_FULL_DM_DTS_SUPPORT
+	bool "enable full DM/DTS support for KM 83xx boards"
+	default y
+	select CMD_DM
+	select DM
+	select DM_ETH
+	select DM_MDIO
+	select DM_SERIAL
+	select OF_CONTROL
+	select PINCTRL
+	select PINCTRL_QE
+	select PHYLIB
+endmenu
+
 if TARGET_KMETER1
 
 config SYS_BOARD

diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index d9483c7..9268719 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS

@@ -1,5 +1,6 @@
 KM83XX BOARD
 M:	Holger Brunck <holger.brunck@hitachi-powergrids.com>
+M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/keymile/km83xx/
 F:	include/configs/km8360.h
@@ -7,12 +8,24 @@
 F:	configs/kmeter1_defconfig
 F:	include/configs/tuxx1.h
 F:	configs/kmopti2_defconfig
+F:	configs/kmsupx5_defconfig
 F:	configs/kmtepr2_defconfig
 F:	configs/kmtegr1_defconfig
 F:	configs/tuge1_defconfig
 F:	configs/tuxx1_defconfig
-
-KMSUPX5 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	configs/kmsupx5_defconfig
+F:	arch/powerpc/dts/km8309-uboot.dtsi
+F:	arch/powerpc/dts/km8321-uboot.dtsi
+F:	arch/powerpc/dts/km8321.dtsi
+F:	arch/powerpc/dts/km836x-uboot.dtsi
+F:	arch/powerpc/dts/km836x.dtsi
+F:	arch/powerpc/dts/kmcoge5ne-uboot.dtsi
+F:	arch/powerpc/dts/kmcoge5ne.dts
+F:	arch/powerpc/dts/kmeter1-uboot.dtsi
+F:	arch/powerpc/dts/kmeter1.dts
+F:	arch/powerpc/dts/kmopti2.dts
+F:	arch/powerpc/dts/kmsupc5.dts
+F:	arch/powerpc/dts/kmsupm5.dts
+F:	arch/powerpc/dts/kmtegr1.dts
+F:	arch/powerpc/dts/kmtepr2.dts
+F:	arch/powerpc/dts/kmtuge1.dts
+F:	arch/powerpc/dts/kmtuxa1.dts

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 0aad452..8669715 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c

@@ -36,70 +36,6 @@
 
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-	/* port pin dir open_drain assign */
-#if defined(CONFIG_ARCH_MPC8360)
-	/* MDIO */
-	{0,  1, 3, 0, 2}, /* MDIO */
-	{0,  2, 1, 0, 1}, /* MDC */
-
-	/* UCC4 - UEC */
-	{1, 14, 1, 0, 1}, /* TxD0 */
-	{1, 15, 1, 0, 1}, /* TxD1 */
-	{1, 20, 2, 0, 1}, /* RxD0 */
-	{1, 21, 2, 0, 1}, /* RxD1 */
-	{1, 18, 1, 0, 1}, /* TX_EN */
-	{1, 26, 2, 0, 1}, /* RX_DV */
-	{1, 27, 2, 0, 1}, /* RX_ER */
-	{1, 24, 2, 0, 1}, /* COL */
-	{1, 25, 2, 0, 1}, /* CRS */
-	{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
-	{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
-
-	/* DUART - UART2 */
-	{5,  0, 1, 0, 2}, /* UART2_SOUT */
-	{5,  2, 1, 0, 1}, /* UART2_RTS */
-	{5,  3, 2, 0, 2}, /* UART2_SIN */
-	{5,  1, 2, 0, 3}, /* UART2_CTS */
-#elif !defined(CONFIG_ARCH_MPC8309)
-	/* Local Bus */
-	{0, 16, 1, 0, 3}, /* LA00 */
-	{0, 17, 1, 0, 3}, /* LA01 */
-	{0, 18, 1, 0, 3}, /* LA02 */
-	{0, 19, 1, 0, 3}, /* LA03 */
-	{0, 20, 1, 0, 3}, /* LA04 */
-	{0, 21, 1, 0, 3}, /* LA05 */
-	{0, 22, 1, 0, 3}, /* LA06 */
-	{0, 23, 1, 0, 3}, /* LA07 */
-	{0, 24, 1, 0, 3}, /* LA08 */
-	{0, 25, 1, 0, 3}, /* LA09 */
-	{0, 26, 1, 0, 3}, /* LA10 */
-	{0, 27, 1, 0, 3}, /* LA11 */
-	{0, 28, 1, 0, 3}, /* LA12 */
-	{0, 29, 1, 0, 3}, /* LA13 */
-	{0, 30, 1, 0, 3}, /* LA14 */
-	{0, 31, 1, 0, 3}, /* LA15 */
-
-	/* MDIO */
-	{3,  4, 3, 0, 2}, /* MDIO */
-	{3,  5, 1, 0, 2}, /* MDC */
-
-	/* UCC4 - UEC */
-	{1, 18, 1, 0, 1}, /* TxD0 */
-	{1, 19, 1, 0, 1}, /* TxD1 */
-	{1, 22, 2, 0, 1}, /* RxD0 */
-	{1, 23, 2, 0, 1}, /* RxD1 */
-	{1, 26, 2, 0, 1}, /* RxER */
-	{1, 28, 2, 0, 1}, /* Rx_DV */
-	{1, 30, 1, 0, 1}, /* TxEN */
-	{1, 31, 2, 0, 1}, /* CRS */
-	{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
-#endif
-
-	/* END of table */
-	{0,  0, 0, 0, QE_IOP_TAB_END},
-};
-
 static int piggy_present(void)
 {
 	struct km_bec_fpga __iomem *base =

diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
index 91afcdd..8054511 100644
--- a/board/renesas/condor/condor.c
+++ b/board/renesas/condor/condor.c

@@ -18,15 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */

diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index c8f4b21..9993f5b 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c

@@ -30,10 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define GSX_MSTP112		BIT(12)	/* 3DG */
 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
 #define DVFS_MSTP926		BIT(26)
@@ -75,23 +71,10 @@
 }
 
 #define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
 #define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
 #define RST_CA53_CODE	0x5A5A000F
 
 void reset_cpu(ulong addr)
 {
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
+	writel(RST_CA53_CODE, RST_CA53RESCNT);
 }

diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index d164a36..8d6b8fe 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c

@@ -29,15 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 947bdae..c78c2a4 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c

@@ -31,10 +31,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define DVFS_MSTP926		BIT(26)
 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 07bc1ec..efbffa0 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c

@@ -29,10 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void)
-{
-}
-
 #define DVFS_MSTP926		BIT(26)
 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 71e2b75..a5cf0b6 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c

@@ -711,7 +711,7 @@
 
 	ret = generic_phy_init(&phy);
 	if (ret) {
-		pr_err("failed to init %s USB PHY\n", dev->name);
+		pr_debug("failed to init %s USB PHY\n", dev->name);
 		return ret;
 	}
 

diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh
deleted file mode 100755
index 88ad719..0000000
--- a/board/sunxi/mksunxi_fit_atf.sh
+++ /dev/null

@@ -1,87 +0,0 @@
-#!/bin/sh
-#
-# script to generate FIT image source for 64-bit sunxi boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-
-if [ ! -f $BL31 ]; then
-	echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
-	echo "Please read the section on ARM Trusted Firmware (ATF) in board/sunxi/README.sunxi64" >&2
-	BL31=/dev/null
-fi
-
-if grep -q "^CONFIG_MACH_SUN50I_H6=y" .config; then
-	BL31_ADDR=0x104000
-else
-	BL31_ADDR=0x44000
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
-	description = "Configuration to load ATF before U-Boot";
-	#address-cells = <1>;
-
-	images {
-		uboot {
-			description = "U-Boot (64-bit)";
-			data = /incbin/("u-boot-nodtb.bin");
-			type = "standalone";
-			arch = "arm64";
-			compression = "none";
-			load = <0x4a000000>;
-		};
-		atf {
-			description = "ARM Trusted Firmware";
-			data = /incbin/("$BL31");
-			type = "firmware";
-			arch = "arm64";
-			compression = "none";
-			load = <$BL31_ADDR>;
-			entry = <$BL31_ADDR>;
-		};
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-	cat << __FDT_IMAGE_EOF
-		fdt_$cnt {
-			description = "$(basename $dtname .dtb)";
-			data = /incbin/("$dtname");
-			type = "flat_dt";
-			compression = "none";
-		};
-__FDT_IMAGE_EOF
-	cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
-	};
-	configurations {
-		default = "config_1";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
-	cat << __CONF_SECTION_EOF
-		config_$cnt {
-			description = "$(basename $dtname .dtb)";
-			firmware = "uboot";
-			loadables = "atf";
-			fdt = "fdt_$cnt";
-		};
-__CONF_SECTION_EOF
-	cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
-	};
-};
-__ITS_EOF

diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index e100adf..219c871 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS

@@ -5,3 +5,4 @@
 F:	include/configs/am335x_evm.h
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
+F:	configs/am335x_evm_spiboot_defconfig

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index ebaa6fa..7925b76 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c

@@ -117,6 +117,13 @@
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	detect_enable_hyperflash(spl_image->fdt_addr);
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {

diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 73fc1be..c80d0a8 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig

@@ -41,7 +41,7 @@
 endif
 
 config XILINX_OF_BOARD_DTB_ADDR
-	hex
+	hex "Default DTB pickup address"
 	default 0x1000 if ARCH_VERSAL
 	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
 	depends on OF_BOARD || OF_SEPARATE

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index eab389d..b0f60c4 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c

@@ -44,7 +44,7 @@
 #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
 void *board_fdt_blob_setup(void)
 {
-	static void *fdt_blob;
+	void *fdt_blob;
 
 #if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
 	fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index b4e7301..28f067a 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c

@@ -9,6 +9,7 @@
 #include <cpu_func.h>
 #include <debug_uart.h>
 #include <env.h>
+#include <env_internal.h>
 #include <init.h>
 #include <log.h>
 #include <net.h>
@@ -38,181 +39,156 @@
 
 #include "pm_cfg_obj.h"
 
+#define ZYNQMP_VERSION_SIZE	7
+#define EFUSE_VCU_DIS_MASK     0x100
+#define EFUSE_VCU_DIS_SHIFT    8
+#define EFUSE_GPU_DIS_MASK     0x20
+#define EFUSE_GPU_DIS_SHIFT    5
+#define IDCODE2_PL_INIT_MASK   0x200
+#define IDCODE2_PL_INIT_SHIFT  9
+
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0U),
+	ZYNQMP_VARIANT_EV = BIT(1U),
+	ZYNQMP_VARIANT_CG = BIT(2U),
+	ZYNQMP_VARIANT_DR = BIT(3U),
+};
+
 static const struct {
 	u32 id;
-	u32 ver;
-	char *name;
-	bool evexists;
+	u8 device;
+	u8 variants;
 } zynqmp_devices[] = {
 	{
-		.id = 0x10,
-		.name = "3eg",
-	},
-	{
-		.id = 0x10,
-		.ver = 0x2c,
-		.name = "3cg",
-	},
-	{
-		.id = 0x11,
-		.name = "2eg",
-	},
-	{
-		.id = 0x11,
-		.ver = 0x2c,
-		.name = "2cg",
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.name = "5ev",
-		.evexists = 1,
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x100,
-		.name = "5eg",
-		.evexists = 1,
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x20,
-		.ver = 0x12c,
-		.name = "5cg",
-		.evexists = 1,
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.name = "4ev",
-		.evexists = 1,
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x100,
-		.name = "4eg",
-		.evexists = 1,
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
 	},
 	{
-		.id = 0x21,
-		.ver = 0x12c,
-		.name = "4cg",
-		.evexists = 1,
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.name = "7ev",
-		.evexists = 1,
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x100,
-		.name = "7eg",
-		.evexists = 1,
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x30,
-		.ver = 0x12c,
-		.name = "7cg",
-		.evexists = 1,
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.name = "9eg",
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
 	},
 	{
-		.id = 0x38,
-		.ver = 0x2c,
-		.name = "9cg",
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.name = "6eg",
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x39,
-		.ver = 0x2c,
-		.name = "6cg",
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x40,
-		.name = "11eg",
-	},
-	{ /* For testing purpose only */
-		.id = 0x50,
-		.ver = 0x2c,
-		.name = "15cg",
-	},
-	{
-		.id = 0x50,
-		.name = "15eg",
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x58,
-		.name = "19eg",
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x59,
-		.name = "17eg",
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x61,
-		.name = "21dr",
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x63,
-		.name = "23dr",
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x65,
-		.name = "25dr",
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x64,
-		.name = "27dr",
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x60,
-		.name = "28dr",
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 	{
-		.id = 0x62,
-		.name = "29dr",
-	},
-	{
-		.id = 0x66,
-		.name = "39dr",
-	},
-	{
-		.id = 0x7b,
-		.name = "48dr",
-	},
-	{
-		.id = 0x7e,
-		.name = "49dr",
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
 	},
 };
-#endif
-
-#define ZYNQMP_VERSION_SIZE		9
-#define ZYNQMP_PL_STATUS_BIT		9
-#define ZYNQMP_IPDIS_VCU_BIT		8
-#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
-#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
-#define ZYNQMP_CSU_VCUDIS_VER_MASK	ZYNQMP_CSU_VERSION_MASK & \
-					~BIT(ZYNQMP_IPDIS_VCU_BIT)
-#define MAX_VARIANTS_EV			3
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	u32 i, id, ver, j;
-	char *buf;
-	static char name[ZYNQMP_VERSION_SIZE];
+	u32 i;
+	u32 idcode, idcode2;
+	char name[ZYNQMP_VERSION_SIZE];
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
 	xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
@@ -226,61 +202,71 @@
 	 * payload[2][29] = PL_INIT
 	 */
 
-	/* Get IDCODE field */
-	id = ret_payload[1];
-	id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK;
-	id >>=	ZYNQMP_CSU_IDCODE_SVD_SHIFT;
-
-	/* Shift silicon version info */
-	ver = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
-
-	debug("%s, ID: 0x%0X, Ver: 0x%0X\r\n", __func__, id, ver);
+	idcode  = ret_payload[1];
+	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+	debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
+	      idcode2);
 
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id) {
-			if (zynqmp_devices[i].evexists &&
-			    !(ver & ZYNQMP_PL_STATUS_MASK))
-				break;
-			if (zynqmp_devices[i].ver == (ver &
-			    ZYNQMP_CSU_VERSION_MASK))
-				break;
-		}
+		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
+			break;
 	}
 
 	if (i >= ARRAY_SIZE(zynqmp_devices))
 		return "unknown";
 
-	strncat(name, "zu", 2);
-	if (!zynqmp_devices[i].evexists ||
-	    (ver & ZYNQMP_PL_STATUS_MASK)) {
-		strncat(name, zynqmp_devices[i].name,
-			ZYNQMP_VERSION_SIZE - 3);
-		return name;
-	}
-
-	/*
-	 * Here we are means, PL not powered up and ev variant
-	 * exists. So, we need to ignore VCU disable bit(8) in
-	 * version and findout if its CG or EG/EV variant.
-	 */
-	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
-		if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
-		    (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
-			strncat(name, zynqmp_devices[i].name,
-				ZYNQMP_VERSION_SIZE - 3);
-			break;
-		}
-	}
+	/* Add device prefix to the name */
+	strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
+	strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
 
-	if (j >= MAX_VARIANTS_EV)
-		return "unknown";
+	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
 
-	if (strstr(name, "eg") || strstr(name, "ev")) {
-		buf = strstr(name, "e");
-		*buf = '\0';
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strncat(name, "ev", 2);
+				break;
+			case 0x10:
+				strncat(name, "eg", 2);
+				break;
+			case 0x11:
+				strncat(name, "cg", 2);
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
+				"e", 2);
+		}
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
+		strncat(name, "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
+		strncat(name, "dr", 2);
+	} else {
+		debug("Variant not identified\n");
 	}
 
-	return name;
+	return strdup(name);
 }
 #endif
 
@@ -342,9 +328,7 @@
 	/* Bug in ROM sets wrong value in this register */
 	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
-    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
-    defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 	zynqmppl.name = zynqmp_get_silicon_idcode_name();
 	printf("Chip ID:\t%s\n", zynqmppl.name);
 	fpga_init();
@@ -423,10 +407,8 @@
 #else
 int dram_init_banksize(void)
 {
-#if defined(CONFIG_NR_DRAM_BANKS)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
 
 	mem_map_fill();
 
@@ -446,6 +428,24 @@
 {
 }
 
+static u8 __maybe_unused zynqmp_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
 #if defined(CONFIG_BOARD_LATE_INIT)
 static const struct {
 	u32 bit;
@@ -529,24 +529,6 @@
 	return 0;
 }
 
-static u8 zynqmp_get_bootmode(void)
-{
-	u8 bootmode;
-	u32 reg = 0;
-	int ret;
-
-	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
-	if (ret)
-		return -EINVAL;
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
-
-	return bootmode;
-}
-
 int board_late_init(void)
 {
 	u8 bootmode;
@@ -691,3 +673,37 @@
 	puts("Board: Xilinx ZynqMP\n");
 	return 0;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynqmp_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case NAND_MODE:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 0c984d7..999b6cf 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig

@@ -1645,6 +1645,7 @@
 
 config CMD_SNTP
 	bool "sntp"
+	select PROT_UDP
 	help
 	  Synchronize RTC via network
 
@@ -2235,7 +2236,7 @@
 
 config CMD_IRQ
 	bool "irq - Show information about interrupts"
-	depends on !ARM && !MIPS && !SH
+	depends on !ARM && !MIPS && !RISCV && !SH
 	help
 	  This enables two commands:
 

diff --git a/cmd/Makefile b/cmd/Makefile
index 3a9c974..c7a08ed 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile

@@ -197,6 +197,8 @@
 # core command
 obj-y += nvedit.o
 
+obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
+
 obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
 
 filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9593b34..8d8daa6 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c

@@ -8,9 +8,11 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <env.h>
 #include <lmb.h>
 #include <net.h>
+#include <video.h>
 #include <vsprintf.h>
 #include <asm/cache.h>
 
@@ -49,7 +51,6 @@
 
 static void print_bi_dram(const struct bd_info *bd)
 {
-#ifdef CONFIG_NR_DRAM_BANKS
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
@@ -59,11 +60,30 @@
 			bdinfo_print_num("-> size",	bd->bi_dram[i].size);
 		}
 	}
-#endif
 }
 
 __weak void arch_print_bdinfo(void)
 {
+}
+
+static void show_video_info(void)
+{
+	const struct udevice *dev;
+	struct uclass *uc;
+
+	uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) {
+		printf("%-12s= %s %sactive\n", "Video", dev->name,
+		       device_active(dev) ? "" : "in");
+		if (device_active(dev)) {
+			struct video_priv *upriv = dev_get_uclass_priv(dev);
+
+			print_phys_addr("FB base", (ulong)upriv->fb);
+			if (upriv->copy_fb)
+				print_phys_addr("FB copy", (ulong)upriv->copy_fb);
+			printf("%-12s= %dx%dx%d\n", "FB size", upriv->xsize,
+			       upriv->ysize, 1 << upriv->bpix);
+		}
+	}
 }
 
 int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@@ -75,8 +95,6 @@
 #endif
 	bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
 	print_bi_dram(bd);
-	bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
-	print_phys_addr("memsize", bd->bi_memsize);
 	if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
 		bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
 		bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
@@ -96,7 +114,9 @@
 	bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob);
 	bdinfo_print_num("new_fdt", (ulong)gd->new_fdt);
 	bdinfo_print_num("fdt_size", (ulong)gd->fdt_size);
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+	if (IS_ENABLED(CONFIG_DM_VIDEO))
+		show_video_info();
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
 	bdinfo_print_num("FB base  ", gd->fb_base);
 #endif
 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)

diff --git a/cmd/bedbug.c b/cmd/bedbug.c
index 81ce256..684e4a9 100644
--- a/cmd/bedbug.c
+++ b/cmd/bedbug.c

@@ -348,7 +348,7 @@
 		return 1;
 	}
 
-	top = gd->bd->bi_memstart + gd->bd->bi_memsize;
+	top = gd->ram_start + gd->ram_size;
 	depth = 0;
 
 	printf ("Depth     PC\n");

diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile
new file mode 100644
index 0000000..62268d9
--- /dev/null
+++ b/cmd/broadcom/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2020 Broadcom
+
+obj-y += chimp_boot.o
+obj-y += nitro_image_load.o
+obj-y += chimp_handshake.o

diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c
new file mode 100644
index 0000000..16f2b61
--- /dev/null
+++ b/cmd/broadcom/chimp_boot.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include <common.h>
+#include <command.h>
+#include <broadcom/chimp.h>
+
+static int do_chimp_fastboot_secure(struct cmd_tbl *cmdtp, int flag, int argc,
+				    char *const argv[])
+{
+	u32 health = 0;
+
+	if (chimp_health_status_optee(&health)) {
+		pr_err("Chimp health command fail\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (health == BCM_CHIMP_RUNNIG_GOOD) {
+		printf("skip fastboot...\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	if (chimp_fastboot_optee()) {
+		pr_err("Failed to load secure ChiMP image\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD
+	(chimp_ld_secure, 1, 0, do_chimp_fastboot_secure,
+	 "Invoke chimp fw load via optee",
+	 "chimp_ld_secure\n"
+);

diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c
new file mode 100644
index 0000000..a90a73a
--- /dev/null
+++ b/cmd/broadcom/chimp_handshake.c

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include <common.h>
+#include <command.h>
+#include <broadcom/chimp.h>
+
+/* This command should be called after loading the nitro binaries */
+static int do_chimp_hs(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int ret = CMD_RET_USAGE;
+	u32 hstatus;
+
+	/* Returns 1, if handshake call is success */
+	if (chimp_handshake_status_optee(0, &hstatus))
+		ret = CMD_RET_SUCCESS;
+
+	if (hstatus == CHIMP_HANDSHAKE_SUCCESS)
+		printf("ChiMP Handshake successful\n");
+	else
+		printf("ERROR: ChiMP Handshake status 0x%x\n", hstatus);
+
+	return ret;
+}
+
+U_BOOT_CMD
+	(chimp_hs, 1, 1, do_chimp_hs,
+	 "Verify the Chimp handshake",
+	 "chimp_hs\n"
+);

diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c
new file mode 100644
index 0000000..4a36b30
--- /dev/null
+++ b/cmd/broadcom/nitro_image_load.c

@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom
+ */
+
+#include <common.h>
+#include <command.h>
+
+#define FW_IMAGE_SIG	0xff123456
+#define CFG_IMAGE_SIG	0xcf54321a
+
+/*
+ * structure for bin file
+ *  signature: fw itb file
+ *  size: fw itb file
+ *  signature: NS3 config file
+ *  size: NS3 config file
+ *  Data: fw itb file
+ *  ............................
+ *  ............................
+ *  Data: NS3 config file
+ *  ............................
+ *  ............................
+ */
+
+static struct img_header {
+	u32 bin_sig;
+	u32 bin_size;
+	u32 cfg1_sig;
+	u32 cfg1_size;
+} *img_header;
+
+static int env_set_val(const char *varname, ulong val)
+{
+	int ret;
+
+	ret = env_set_hex(varname, val);
+	if (ret)
+		pr_err("Failed to %s env var\n", varname);
+
+	return ret;
+}
+
+static int do_spi_images_addr(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	uintptr_t images_load_addr;
+	uintptr_t spi_load_addr;
+	u32 len;
+	u32 spi_data_offset = sizeof(struct img_header);
+
+	if (argc != 3)
+		return CMD_RET_USAGE;
+
+	/* convert command parameter to fastboot address (base 16), i.e. hex */
+	images_load_addr = simple_strtoul(argv[1], NULL, 16);
+	if (!images_load_addr) {
+		pr_err("Invalid load address\n");
+		return CMD_RET_USAGE;
+	}
+
+	spi_load_addr = simple_strtoul(argv[2], NULL, 16);
+	if (!spi_load_addr) {
+		pr_err("Invalid spi load address\n");
+		return CMD_RET_USAGE;
+	}
+
+	img_header = (struct img_header *)images_load_addr;
+
+	if (img_header->bin_sig != FW_IMAGE_SIG) {
+		pr_err("Invalid Nitro bin file\n");
+		goto error;
+	}
+
+	if (env_set_val("spi_nitro_fw_itb_start_addr", 0))
+		goto error;
+
+	if (env_set_val("spi_nitro_fw_itb_len", 0))
+		goto error;
+
+	if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr", 0))
+		goto error;
+
+	if (env_set_val("spi_nitro_fw_ns3_cfg_len", 0))
+		goto error;
+
+	len = img_header->bin_size;
+
+	if (env_set_val("spi_nitro_fw_itb_start_addr",
+			(spi_load_addr + spi_data_offset)))
+		goto error;
+
+	if (env_set_val("spi_nitro_fw_itb_len", img_header->bin_size))
+		goto error;
+
+	spi_data_offset += len;
+
+	if (img_header->cfg1_sig == CFG_IMAGE_SIG) {
+		len = img_header->cfg1_size;
+
+		if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr",
+				(spi_load_addr + spi_data_offset)))
+			goto error;
+
+		if (env_set_val("spi_nitro_fw_ns3_cfg_len", len))
+			goto error;
+
+		spi_data_offset += len;
+	}
+
+	/* disable secure boot */
+	if (env_set_val("nitro_fastboot_secure", 0))
+		goto error;
+
+	return CMD_RET_SUCCESS;
+
+error:
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD
+	(spi_nitro_images_addr, 3, 1, do_spi_images_addr,
+	 "Load the bnxt bin header and sets envs ",
+	 "spi_nitro_images_addr <load_addr> <spi_base_addr>\n"
+);

diff --git a/cmd/net.c b/cmd/net.c
index 9bbcdbc..beb2877 100644
--- a/cmd/net.c
+++ b/cmd/net.c

@@ -13,6 +13,8 @@
 #include <env.h>
 #include <image.h>
 #include <net.h>
+#include <net/udp.h>
+#include <net/sntp.h>
 
 static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []);
 
@@ -356,6 +358,12 @@
 #endif
 
 #if defined(CONFIG_CMD_SNTP)
+static struct udp_ops sntp_ops = {
+	.prereq = sntp_prereq,
+	.start = sntp_start,
+	.data = NULL,
+};
+
 int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	char *toff;
@@ -380,7 +388,7 @@
 	else
 		net_ntp_time_offset = simple_strtol(toff, NULL, 10);
 
-	if (net_loop(SNTP) < 0) {
+	if (udp_loop(&sntp_ops) < 0) {
 		printf("SNTP failed: host %pI4 not responding\n",
 		       &net_ntp_server);
 		return CMD_RET_FAILURE;

diff --git a/cmd/pxe.c b/cmd/pxe.c
index 6372fc9..46ac08f 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c

@@ -212,10 +212,24 @@
 	U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "")
 };
 
+static void __maybe_unused pxe_reloc(void)
+{
+	static int relocated_pxe;
+
+	if (!relocated_pxe) {
+		fixup_cmdtable(cmd_pxe_sub, ARRAY_SIZE(cmd_pxe_sub));
+		relocated_pxe = 1;
+	}
+}
+
 static int do_pxe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	struct cmd_tbl *cp;
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	pxe_reloc();
+#endif
+
 	if (argc < 2)
 		return CMD_RET_USAGE;
 

diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
index 6b1f7bd..9e555c7 100644
--- a/cmd/x86/hob.c
+++ b/cmd/x86/hob.c

@@ -8,6 +8,7 @@
 #include <efi.h>
 #include <uuid.h>
 #include <asm/hob.h>
+#include <asm/fsp/fsp_hob.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -26,6 +27,67 @@
 	"Capsule",
 };
 
+static char *res_type[] = {
+	"System",
+	"Memory-mapped I/O",
+	"I/O",
+	"Firmware device",
+	"Memory-mapped I/O port",
+	"Reserved",
+	"I/O reserved",
+};
+
+static struct guid_name {
+	efi_guid_t guid;
+	const char *name;
+} guid_name[] = {
+	{ FSP_HOB_RESOURCE_OWNER_TSEG_GUID, "TSEG" },
+	{ FSP_HOB_RESOURCE_OWNER_FSP_GUID, "FSP" },
+	{ FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID, "SMM PEI SMRAM" },
+	{ FSP_NON_VOLATILE_STORAGE_HOB_GUID, "NVS" },
+	{ FSP_VARIABLE_NV_DATA_HOB_GUID, "Variable NVS" },
+	{ FSP_GRAPHICS_INFO_HOB_GUID, "Graphics info" },
+	{ FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1, "PCD database ea" },
+	{ FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2, "PCD database 9b" },
+	{ FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID, "PEIM Init DXE" },
+	{ FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID, "Alloc stack" },
+	{ FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID, "SMBIOS memory" },
+	{ {}, "zero-guid" },
+	{}
+};
+
+static const char *guid_to_name(const efi_guid_t *guid)
+{
+	struct guid_name *entry;
+
+	for (entry = guid_name; entry->name; entry++) {
+		if (!guidcmp(guid, &entry->guid))
+			return entry->name;
+	}
+
+	return NULL;
+}
+
+static void show_hob_details(const struct hob_header *hdr)
+{
+	const void *ptr = hdr;
+
+	switch (hdr->type) {
+	case HOB_TYPE_RES_DESC: {
+		const struct hob_res_desc *res = ptr;
+		const char *typename;
+
+		typename = res->type > 0 && res->type <= RES_MAX_MEM_TYPE ?
+			res_type[res->type] : "unknown";
+
+		printf("     base = %08llx, len = %08llx, end = %08llx, type = %d (%s)\n\n",
+		       res->phys_start, res->len, res->phys_start + res->len,
+		       res->type, typename);
+		break;
+	}
+	}
+}
+
 static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	const struct hob_header *hdr;
@@ -34,7 +96,20 @@
 	int i = 0;
 	efi_guid_t *guid;
 	char uuid[UUID_STR_LEN + 1];
+	bool verbose = false;
+	int seq = -1;	/* Show all by default */
 
+	argc--;
+	argv++;
+	if (argc) {
+		if (!strcmp("-v", *argv)) {
+			verbose = true;
+			argc--;
+			argv++;
+		}
+		if (argc)
+			seq = simple_strtol(*argv, NULL, 16);
+	}
 	hdr = gd->arch.hob_list;
 
 	printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
@@ -43,7 +118,9 @@
 	printf("%36s\n", "GUID");
 	printf("---|----------|-----------|------|-");
 	printf("------------------------------------\n");
-	while (!end_of_hob(hdr)) {
+	for (i = 0; !end_of_hob(hdr); i++, hdr = get_next_hob(hdr)) {
+		if (seq != -1 && seq != i)
+			continue;
 		printf("%02x | %08x | ", i, (unsigned int)hdr);
 		type = hdr->type;
 		if (type == HOB_TYPE_UNUSED)
@@ -58,21 +135,30 @@
 
 		if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
 		    type == HOB_TYPE_GUID_EXT) {
+			const char *name;
+
 			guid = (efi_guid_t *)(hdr + 1);
-			uuid_bin_to_str(guid->b, uuid, UUID_STR_FORMAT_GUID);
-			printf("%s", uuid);
+			name = guid_to_name(guid);
+			if (!name) {
+				uuid_bin_to_str(guid->b, uuid,
+						UUID_STR_FORMAT_GUID);
+				name = uuid;
+			}
+			printf("%36s", name);
 		} else {
 			printf("%36s", "Not Available");
 		}
 		printf("\n");
-		hdr = get_next_hob(hdr);
-		i++;
+		if (verbose)
+			show_hob_details(hdr);
 	}
 
 	return 0;
 }
 
-U_BOOT_CMD(hob, 1, 1, do_hob,
-	   "Print Hand-Off Block (HOB) information",
+U_BOOT_CMD(hob, 3, 1, do_hob,
+	   "[-v] [seq]  Print Hand-Off Block (HOB) information"
+	   "   -v  - Show detailed HOB information where available"
+	   "   seq - Record # to show (all by default)",
 	   ""
 );

diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index 99efecb..fc61a54 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c

@@ -27,7 +27,7 @@
 	mtrr_read_all(info);
 }
 
-static int do_mtrr_list(int cpu_select)
+static int do_mtrr_list(int reg_count, int cpu_select)
 {
 	struct mtrr_info info;
 	int ret;
@@ -39,7 +39,7 @@
 	ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info);
 	if (ret)
 		return log_msg_ret("run", ret);
-	for (i = 0; i < MTRR_COUNT; i++) {
+	for (i = 0; i < reg_count; i++) {
 		const char *type = "Invalid";
 		uint64_t base, mask, size;
 		bool valid;
@@ -98,6 +98,7 @@
 static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc,
 		   char *const argv[])
 {
+	int reg_count = mtrr_get_var_count();
 	int cmd;
 	int cpu_select;
 	uint reg;
@@ -126,7 +127,7 @@
 		if (argc < 2)
 			return CMD_RET_USAGE;
 		reg = simple_strtoul(argv[1], NULL, 16);
-		if (reg >= MTRR_COUNT) {
+		if (reg >= reg_count) {
 			printf("Invalid register number\n");
 			return CMD_RET_USAGE;
 		}
@@ -145,7 +146,7 @@
 			if (!first)
 				printf("\n");
 			printf("CPU %d:\n", i);
-			ret = do_mtrr_list(i);
+			ret = do_mtrr_list(reg_count, i);
 			if (ret) {
 				printf("Failed to read CPU %d (err=%d)\n", i,
 				       ret);

diff --git a/common/board_f.c b/common/board_f.c
index d3444c7..62473ab 100644
--- a/common/board_f.c
+++ b/common/board_f.c

@@ -215,8 +215,6 @@
 static int show_dram_config(void)
 {
 	unsigned long long size;
-
-#ifdef CONFIG_NR_DRAM_BANKS
 	int i;
 
 	debug("\nRAM Configuration:\n");
@@ -229,9 +227,6 @@
 #endif
 	}
 	debug("\nDRAM:  ");
-#else
-	size = gd->ram_size;
-#endif
 
 	print_size(size, "");
 	board_add_ram_info(0);
@@ -242,10 +237,8 @@
 
 __weak int dram_init_banksize(void)
 {
-#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = gd->ram_base;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
 
 	return 0;
 }
@@ -603,9 +596,6 @@
 {
 	struct bd_info *bd = gd->bd;
 
-	bd->bi_memstart = gd->ram_base;  /* start of memory */
-	bd->bi_memsize = gd->ram_size;   /* size in bytes */
-
 	if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
 		bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
 		bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;  /* size  of SRAM */

diff --git a/common/image.c b/common/image.c
index da8bccd..645bfef 100644
--- a/common/image.c
+++ b/common/image.c

@@ -685,14 +685,8 @@
 		return tmp;
 	}
 
-#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
-     defined(CONFIG_NR_DRAM_BANKS)
-	start = gd->bd->bi_dram[0].start;
-	size = gd->bd->bi_dram[0].size;
-#else
-	start = gd->bd->bi_memstart;
-	size = gd->bd->bi_memsize;
-#endif
+	start = gd->ram_base;
+	size = gd->ram_size;
 
 	if (start + size > gd->ram_top)
 		size = gd->ram_top - start;

diff --git a/common/init/handoff.c b/common/init/handoff.c
index e00b43e..62071bd 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c

@@ -12,18 +12,15 @@
 
 void handoff_save_dram(struct spl_handoff *ho)
 {
+	struct bd_info *bd = gd->bd;
+	int i;
+
 	ho->ram_size = gd->ram_size;
-#ifdef CONFIG_NR_DRAM_BANKS
-	{
-		struct bd_info *bd = gd->bd;
-		int i;
 
-		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-			ho->ram_bank[i].start = bd->bi_dram[i].start;
-			ho->ram_bank[i].size = bd->bi_dram[i].size;
-		}
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		ho->ram_bank[i].start = bd->bi_dram[i].start;
+		ho->ram_bank[i].size = bd->bi_dram[i].size;
 	}
-#endif
 }
 
 void handoff_load_dram_size(struct spl_handoff *ho)
@@ -33,15 +30,11 @@
 
 void handoff_load_dram_banks(struct spl_handoff *ho)
 {
-#ifdef CONFIG_NR_DRAM_BANKS
-	{
-		struct bd_info *bd = gd->bd;
-		int i;
+	struct bd_info *bd = gd->bd;
+	int i;
 
-		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-			bd->bi_dram[i].start = ho->ram_bank[i].start;
-			bd->bi_dram[i].size = ho->ram_bank[i].size;
-		}
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		bd->bi_dram[i].start = ho->ram_bank[i].start;
+		bd->bi_dram[i].size = ho->ram_bank[i].size;
 	}
-#endif
 }

diff --git a/common/log.c b/common/log.c
index 734d26d..9a5f100 100644
--- a/common/log.c
+++ b/common/log.c

@@ -191,12 +191,23 @@
 static int log_dispatch(struct log_rec *rec)
 {
 	struct log_device *ldev;
+	static int processing_msg;
 
+	/*
+	 * When a log driver writes messages (e.g. via the network stack) this
+	 * may result in further generated messages. We cannot process them here
+	 * as this might result in infinite recursion.
+	 */
+	if (processing_msg)
+		return 0;
+
+	/* Emit message */
+	processing_msg = 1;
 	list_for_each_entry(ldev, &gd->log_head, sibling_node) {
 		if (log_passes_filters(ldev, rec))
 			ldev->drv->emit(ldev, rec);
 	}
-
+	processing_msg = 0;
 	return 0;
 }
 

diff --git a/common/log_syslog.c b/common/log_syslog.c
index 149ff5a..2ae703f 100644
--- a/common/log_syslog.c
+++ b/common/log_syslog.c

@@ -35,16 +35,9 @@
 	char *log_msg;
 	int eth_hdr_size;
 	struct in_addr bcast_ip;
-	static int processing_msg;
 	unsigned int log_level;
 	char *log_hostname;
 
-	/* Fend off messages from the network stack while writing a message */
-	if (processing_msg)
-		return 0;
-
-	processing_msg = 1;
-
 	/* Setup packet buffers */
 	net_init();
 	/* Disable hardware and put it into the reset state */
@@ -108,7 +101,6 @@
 	net_send_packet((uchar *)msg, ptr - msg);
 
 out:
-	processing_msg = 0;
 	return ret;
 }
 

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index af8255a8..807b1dc 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig

@@ -602,7 +602,7 @@
 	  Support for the underlying block device (e.g. MMC or USB) must be
 	  enabled separately.
 
-config SPL_FPGA_SUPPORT
+config SPL_FPGA
 	bool "Support FPGAs"
 	help
 	  Enable support for FPGAs in SPL. Field-programmable Gate Arrays
@@ -1271,7 +1271,7 @@
 
 config SPL_ATF
 	bool "Support ARM Trusted Firmware"
-	depends on ARM64
+	depends on ARM64 && SPL_FIT
 	help
 	  ATF(ARM Trusted Firmware) is a component for ARM AArch64 which
 	  is loaded by SPL (which is considered as BL2 in ATF terminology).

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a8bfd38..0e27ad1 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c

@@ -253,7 +253,7 @@
 	const void *data;
 	bool external_data = false;
 
-	if (IS_ENABLED(CONFIG_SPL_FPGA_SUPPORT) ||
+	if (IS_ENABLED(CONFIG_SPL_FPGA) ||
 	    (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
 		if (fit_image_get_type(fit, node, &type))
 			puts("Cannot get image type.\n");
@@ -546,7 +546,7 @@
 		return -1;
 	}
 
-#ifdef CONFIG_SPL_FPGA_SUPPORT
+#ifdef CONFIG_SPL_FPGA
 	node = spl_fit_get_image_node(fit, images, "fpga", 0);
 	if (node >= 0) {
 		/* Load the image and set up the spl_image structure */

diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
deleted file mode 100644
index d0c8732..0000000
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ /dev/null

@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index b77a5d0..dcd13b3 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -73,8 +75,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
deleted file mode 100644
index 8534015..0000000
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ /dev/null

@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 1ea7e3e..b3ee604 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -55,8 +57,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 7b6b70f..cc9e7f5 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig

@@ -44,6 +44,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -67,8 +69,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index 2949654..0000000
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ /dev/null

@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 4bc60f1..6321780 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig

@@ -46,6 +46,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -69,8 +71,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
deleted file mode 100644
index 8c7460f..0000000
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index ea9f905..63d0529 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig

@@ -48,6 +48,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -72,8 +74,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
deleted file mode 100644
index 098c017..0000000
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ /dev/null

@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index f8093c1..82f0cb8 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig

@@ -31,6 +31,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -54,8 +56,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e0a75a1..d5bdc8c 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig

@@ -43,6 +43,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -66,8 +68,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index ac5c31f..0000000
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ /dev/null

@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PA=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index c8212d7..1ab6342 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig

@@ -45,6 +45,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -68,8 +70,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
deleted file mode 100644
index 51057f8..0000000
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ /dev/null

@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index e109e9c..0b418bc 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -73,8 +75,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
deleted file mode 100644
index 0984b3f..0000000
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ /dev/null

@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 0e01e2b..6e3511b 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -55,8 +57,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index c4f052b..58b39f4 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig

@@ -44,6 +44,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -67,8 +69,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index fad3f91..0000000
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ /dev/null

@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 57d0687..0b9ae9c 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig

@@ -46,6 +46,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -69,8 +71,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
deleted file mode 100644
index a0a0b54..0000000
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 37eddf6..96d2dbe 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig

@@ -48,6 +48,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -72,8 +74,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
deleted file mode 100644
index ab2a339..0000000
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ /dev/null

@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 31e5157..4e9acbf 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig

@@ -31,6 +31,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -54,8 +56,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 2cf26ab..a6efea4 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig

@@ -43,6 +43,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -66,8 +68,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
deleted file mode 100644
index c77d8e8..0000000
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ /dev/null

@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB_PB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 5f578bd..f31b3bd 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig

@@ -45,6 +45,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_FSL_ESDHC=y
@@ -68,8 +70,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index b5ef395..0000000
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ /dev/null

@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
deleted file mode 100644
index 39abe1f..0000000
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ /dev/null

@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
deleted file mode 100644
index 12b0175..0000000
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ /dev/null

@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
deleted file mode 100644
index 71ad06c..0000000
--- a/configs/P1020MBG-PC_defconfig
+++ /dev/null

@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020MBG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 6db4bd7..623e6d7 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -62,6 +64,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +76,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -83,5 +88,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index cacce4d..523d308 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig

@@ -45,6 +45,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -57,6 +59,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -68,8 +71,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -78,5 +83,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 3c9e491..092c0db 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -47,6 +47,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -59,6 +61,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -70,8 +73,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -80,5 +85,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 5c68ea0..2aeada2 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig

@@ -34,6 +34,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -46,6 +48,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -57,8 +60,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -67,5 +72,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 9883204..8c099f2 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig

@@ -48,6 +48,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -61,6 +63,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -72,8 +75,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -82,4 +87,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 22ba4f6..e54e662 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig

@@ -44,6 +44,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -56,6 +58,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -67,8 +70,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -77,4 +82,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 250b56d..32ca2b5 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig

@@ -46,6 +46,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -58,6 +60,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -69,8 +72,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -79,4 +84,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 329bd72..f0c9c82 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -45,6 +47,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -56,8 +59,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -66,4 +71,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 5d7f16a..32cf0d6 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig

@@ -51,6 +51,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -65,6 +67,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -76,8 +79,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -86,4 +91,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 12d70e8..e9dd3bd 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig

@@ -47,6 +47,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -60,6 +62,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -71,8 +74,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -81,4 +86,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 6da7157..14c040f 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -62,6 +64,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +76,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -83,4 +88,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index c39509e..4018f3c 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig

@@ -36,6 +36,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -49,6 +51,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -60,8 +63,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -70,4 +75,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index d0b5065..0000000
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ /dev/null

@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
deleted file mode 100644
index 5e3a92d..0000000
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ /dev/null

@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
deleted file mode 100644
index 6c06815..0000000
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ /dev/null

@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
deleted file mode 100644
index 69744a3..0000000
--- a/configs/P1020UTM-PC_defconfig
+++ /dev/null

@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1020UTM=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
deleted file mode 100644
index ca5baae..0000000
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ /dev/null

@@ -1,86 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index 7a64eec..0000000
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ /dev/null

@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index cc0fc1e..0000000
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ /dev/null

@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
deleted file mode 100644
index 58cdba9..0000000
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ /dev/null

@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
deleted file mode 100644
index e8f99f0..0000000
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ /dev/null

@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
deleted file mode 100644
index e285c01..0000000
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ /dev/null

@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
deleted file mode 100644
index 3c1b4c8..0000000
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ /dev/null

@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
deleted file mode 100644
index 4b2083c..0000000
--- a/configs/P1021RDB-PC_defconfig
+++ /dev/null

@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1021RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
deleted file mode 100644
index a8bb576..0000000
--- a/configs/P1023RDB_defconfig
+++ /dev/null

@@ -1,50 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=-1
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_EEPROM is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
deleted file mode 100644
index e74fc7f..0000000
--- a/configs/P1024RDB_36BIT_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
deleted file mode 100644
index d1e91d3..0000000
--- a/configs/P1024RDB_NAND_defconfig
+++ /dev/null

@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
deleted file mode 100644
index e803ed8..0000000
--- a/configs/P1024RDB_SDCARD_defconfig
+++ /dev/null

@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
deleted file mode 100644
index ffabd5e..0000000
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ /dev/null

@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
deleted file mode 100644
index e4adc0f..0000000
--- a/configs/P1024RDB_defconfig
+++ /dev/null

@@ -1,61 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1024RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
deleted file mode 100644
index d0fc144..0000000
--- a/configs/P1025RDB_36BIT_defconfig
+++ /dev/null

@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
deleted file mode 100644
index 58efd11..0000000
--- a/configs/P1025RDB_NAND_defconfig
+++ /dev/null

@@ -1,81 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C_SUPPORT=y
-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
deleted file mode 100644
index dad06be..0000000
--- a/configs/P1025RDB_SDCARD_defconfig
+++ /dev/null

@@ -1,74 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
deleted file mode 100644
index 48e3540..0000000
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ /dev/null

@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xf8f81000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
deleted file mode 100644
index 7164526..0000000
--- a/configs/P1025RDB_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P1025RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 1e0bd20..130b08e 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig

@@ -53,6 +53,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -67,6 +69,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -78,8 +81,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -88,5 +93,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index df57340..31e9528 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -62,6 +64,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +76,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -83,5 +88,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 1b25021..352b35c 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -51,6 +51,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -64,6 +66,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -75,8 +78,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -85,5 +90,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index e5573cd..68ccadb 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig

@@ -38,6 +38,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -51,6 +53,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -62,8 +65,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -72,5 +77,6 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 6232b18..853698d 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig

@@ -52,6 +52,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -66,6 +68,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -77,8 +80,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -87,4 +92,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 4d3b872..919a7a7 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig

@@ -48,6 +48,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -61,6 +63,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -72,8 +75,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y

diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 7b97d91..882bab0 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig

@@ -50,6 +50,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -63,6 +65,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -74,8 +77,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -84,4 +89,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 3a1f668..f0b39b1 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig

@@ -37,6 +37,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -50,6 +52,7 @@
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -61,8 +64,10 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
@@ -71,4 +76,5 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 711b2ce..41f5f1e 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -65,6 +67,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 98432e7..bd1a052 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -64,6 +66,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 6bfc4fa..2149012 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig

@@ -34,6 +34,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -65,6 +67,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 1d6b011..9952f48 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -63,6 +65,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index bfe374d..0000000
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 403eb92..f52f52a 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -62,6 +64,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 316d7e7..edbd4d2 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -61,6 +63,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
deleted file mode 100644
index 893162f..0000000
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 6b5e8c4..1a3342c 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -62,6 +64,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 98c1b95..7fed793 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig

@@ -31,6 +31,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -60,6 +62,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 2f635bd..0f9a472 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -60,6 +62,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
deleted file mode 100644
index e2f5ac2..0000000
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 5908914..ad001f7 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -61,6 +63,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 344ca5f..4cfb5ec 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig

@@ -31,6 +31,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -59,6 +61,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index b781667..0000000
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
deleted file mode 100644
index e5ea166..0000000
--- a/configs/P5020DS_NAND_defconfig
+++ /dev/null

@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
deleted file mode 100644
index 6bf1e9d..0000000
--- a/configs/P5020DS_SDCARD_defconfig
+++ /dev/null

@@ -1,58 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xCF400
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
deleted file mode 100644
index aae9a7d..0000000
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
deleted file mode 100644
index 683751a..0000000
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ /dev/null

@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 631f7ab..0000000
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null

@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
deleted file mode 100644
index 73c3ed6..0000000
--- a/configs/P5020DS_defconfig
+++ /dev/null

@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5020DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index c6d0e68..0000000
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index c8bed42..9964481 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -63,6 +65,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index a7d1122..c3d37df 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig

@@ -32,6 +32,8 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -61,6 +63,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
deleted file mode 100644
index b11a221..0000000
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ /dev/null

@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P5040DS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 8ed9749..498ea8c 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig

@@ -33,6 +33,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -62,6 +64,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 5bb9ace..0c3c28a 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig

@@ -31,6 +31,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -60,6 +62,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index b754817..b1e7d83 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig

@@ -87,6 +87,9 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index bf2895d..55bac9d 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig

@@ -84,6 +84,9 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 55c10ce..95bac27 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig

@@ -69,3 +69,5 @@
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 31cbc7a..a051bda 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig

@@ -87,6 +87,9 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index fb396c0..3822194 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig

@@ -72,6 +72,9 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 90ebc6c..9bf068d 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig

@@ -51,6 +51,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -82,6 +84,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y

diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index ffbaff5..7a5ab27 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -79,6 +81,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y

diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index e670f06..07d24fc 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig

@@ -52,6 +52,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -82,6 +84,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y

diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 9906bf8..ebed19a 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig

@@ -37,6 +37,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -67,6 +69,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 88ae7ac..4e45940 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig

@@ -84,3 +84,5 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index e1ab189..41fb354 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig

@@ -81,3 +81,5 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 14a7b1e..c2d67e3 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig

@@ -71,3 +71,5 @@
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 0e787ea..1c7acd3 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig

@@ -84,3 +84,5 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 4628124..dd91435 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig

@@ -61,3 +61,5 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index cfac994..70ff72e 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig

@@ -69,3 +69,5 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 9809c3c..32eb602 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig

@@ -51,6 +51,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -82,6 +84,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 2cc7ee2..7f8a398 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig

@@ -49,6 +49,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -79,6 +81,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 62cbab1..fc12766 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig

@@ -52,6 +52,8 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -82,6 +84,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index e066e98..9c85e1b 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig

@@ -37,6 +37,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -66,6 +68,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index f39fde6..389b1e6 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig

@@ -42,6 +42,8 @@
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -72,6 +74,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index ae47aeb..c5b2ad6 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig

@@ -30,6 +30,8 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
@@ -60,6 +62,7 @@
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_USB=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64

diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
new file mode 100644
index 0000000..d71a7ce
--- /dev/null
+++ b/configs/am335x_evm_spiboot_defconfig

@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_LOGLEVEL=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+# CONFIG_SPL_FS_EXT4 is not set
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_ENV_OVERWRITE=y
+# CONFIG_ENV_IS_IN_FAT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_RSA=y
+CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set

diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index dd44168..25282ba 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig

@@ -32,7 +32,6 @@
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y

diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index e1d0749..af0397f 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig

@@ -4,6 +4,7 @@
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL_DM_SPI=y
 CONFIG_SPL_TEXT_BASE=0xfef10000
+CONFIG_MAX_CPUS=8
 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -14,10 +15,12 @@
 CONFIG_TARGET_CHROMEBOOK_CORAL=y
 CONFIG_DEBUG_UART=y
 CONFIG_FSP_VERSION2=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_HAVE_ACPI_RESUME=y
 CONFIG_INTEL_CAR_CQOS=y
-CONFIG_X86_OFFSET_U_BOOT=0xffe00000
+CONFIG_X86_OFFSET_U_BOOT=0xffd00000
 CONFIG_X86_OFFSET_SPL=0xffe80000
+CONFIG_INTEL_GENERIC_WIFI=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SPL_BOOTSTAGE=y
 CONFIG_TPL_BOOTSTAGE=y
@@ -25,13 +28,14 @@
 CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200"
+CONFIG_BOOTARGS="console=ttyS2,115200n8 cros_legacy loglevel=9 init=/sbin/init oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw noinitrd vt.global_cursor_default=0 add_efi_memmap boot=local noresume noswap i915.modeset=1 nmi_watchdog=panic,lapic disablevmx=off"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_SPL_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_BLOBLIST=y
 # CONFIG_TPL_BLOBLIST is not set
+CONFIG_BLOBLIST_SIZE=0x30000
 CONFIG_BLOBLIST_ADDR=0x100000
 CONFIG_HANDOFF=y
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
@@ -71,9 +75,12 @@
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_INTEL_ACPIGEN=y
 CONFIG_CPU=y
+CONFIG_BOARD=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
 CONFIG_TPL_MISC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
@@ -85,7 +92,9 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SOUND=y
+CONFIG_SOUND_DA7219=y
 CONFIG_SOUND_I8254=y
+CONFIG_SOUND_MAX98357A=y
 CONFIG_SOUND_RT5677=y
 CONFIG_SPI=y
 CONFIG_ICH_SPI=y

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 82485a5..c59a7f3 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig

@@ -1,5 +1,5 @@
 CONFIG_X86=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_TEXT_BASE=0xFFEF0000
 CONFIG_SYS_MALLOC_F_LEN=0x2400
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x1000

diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index fb5a7b0..8b08b77 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig

@@ -12,6 +12,7 @@
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="ignore_loglevel"
+# CONFIG_BOARD_EARLY_INIT_F is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 2f7f93a..7c900b1 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig

@@ -30,7 +30,7 @@
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
@@ -41,7 +41,9 @@
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -61,6 +63,7 @@
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -87,6 +90,7 @@
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
@@ -140,6 +144,7 @@
 CONFIG_TI_SCI_POWER_DOMAIN=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SCSI=y

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 2908bc3..3820fc5 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig

@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x70000
@@ -37,7 +38,9 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -67,6 +70,8 @@
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
@@ -81,12 +86,21 @@
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y

diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 733e7f3..1be9e1c 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig

@@ -4,8 +4,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMCOGE5NE=y
@@ -156,7 +156,6 @@
 CONFIG_LCRR_DBYP_PLL_BYPASSED=y
 CONFIG_LCRR_EADC_2=y
 CONFIG_LCRR_CLKDIV_4=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -173,6 +172,7 @@
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -186,8 +186,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -197,8 +198,10 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index ecaeb5d..f24b7aa 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig

@@ -4,8 +4,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmeter1"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMETER1=y
@@ -120,7 +120,6 @@
 CONFIG_LCRR_DBYP_PLL_BYPASSED=y
 CONFIG_LCRR_EADC_2=y
 CONFIG_LCRR_CLKDIV_4=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -136,6 +135,7 @@
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_I2C=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -149,8 +149,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -159,7 +160,8 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 302fdef..b74ea4b 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig

@@ -3,8 +3,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmopti2"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMOPTI2=y
@@ -139,7 +139,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -155,6 +154,7 @@
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_I2C=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -168,8 +168,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -178,7 +179,9 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 222a700..bf613a6 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig

@@ -3,8 +3,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmsupm5"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMSUPX5=y
@@ -119,7 +119,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -148,8 +147,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -158,7 +158,9 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 58674c6..8fb4699 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig

@@ -4,8 +4,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmtegr1"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMTEGR1=y
@@ -118,7 +118,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
@@ -150,8 +149,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF0100000
 CONFIG_ENV_ADDR_REDUND=0xF0120000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -161,9 +161,13 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 36d02e1..3f94db6 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig

@@ -3,8 +3,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmtepr2"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_KMTEPR2=y
@@ -139,7 +139,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -168,8 +167,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -178,7 +178,9 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 06a139b..43f9e51 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig

@@ -44,6 +44,7 @@
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y

diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 8046f64..49197ee 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig

@@ -55,6 +55,7 @@
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y

diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 30511dd..d62dcfa 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig

@@ -46,6 +46,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 60622b1..f49a882 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig

@@ -48,6 +48,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index fa0a118..e75c7b4 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig

@@ -50,6 +50,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 30c1079..767c364 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig

@@ -49,6 +49,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 0911b9c..5b3ac2a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig

@@ -61,6 +61,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index eaf5b98..5cc0b90 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig

@@ -63,6 +63,7 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 2743848..e3e64f9 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig

@@ -60,6 +60,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y

diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 55b29b2..160d563 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig

@@ -20,6 +20,7 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SPI=y
@@ -41,6 +42,9 @@
 CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y

diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index 1f72e55..709eb34 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig

@@ -10,6 +10,7 @@
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_CONDOR=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y

diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index efdb8e6..f4499cd 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig

@@ -9,6 +9,7 @@
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_RCAR_GEN3=y
 CONFIG_TARGET_EBISU=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot"
 CONFIG_SMBIOS_PRODUCT_NAME=""
 CONFIG_FIT=y
@@ -17,11 +18,14 @@
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
 CONFIG_VERSION_VARIABLE=y
+CONFIG_UPDATE_TFTP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -41,6 +45,9 @@
 CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
@@ -49,6 +56,13 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_RENESAS_RPC_HF=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -58,6 +72,9 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
 CONFIG_USB=y

diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index b496230..6152bcf 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig

@@ -17,11 +17,14 @@
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
 CONFIG_VERSION_VARIABLE=y
+CONFIG_UPDATE_TFTP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -40,6 +43,9 @@
 CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
@@ -56,6 +62,8 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -65,6 +73,9 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
 CONFIG_USB=y

diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 0fbd1e0..bc6ba7b 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig

@@ -16,12 +16,15 @@
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb"
 CONFIG_VERSION_VARIABLE=y
+CONFIG_UPDATE_TFTP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -44,6 +47,9 @@
 CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
@@ -52,6 +58,13 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_RENESAS_RPC_HF=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -64,6 +77,9 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
 CONFIG_USB=y

diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index 710b2f4..f654f84 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig

@@ -17,11 +17,14 @@
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb"
 CONFIG_VERSION_VARIABLE=y
+CONFIG_UPDATE_TFTP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
@@ -44,6 +47,9 @@
 CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
@@ -52,6 +58,13 @@
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_RENESAS_RPC_HF=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_BITBANGMII=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -61,6 +74,9 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6e9f029..c72e0e2 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig

@@ -102,6 +102,7 @@
 CONFIG_ENV_IS_IN_EXT4=y
 CONFIG_ENV_EXT4_INTERFACE="host"
 CONFIG_ENV_EXT4_DEVICE_AND_PART="0:0"
+CONFIG_PROT_UDP=y
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NETCONSOLE=y
 CONFIG_IP_DEFRAG=y
@@ -122,6 +123,7 @@
 CONFIG_BUTTON_GPIO=y
 CONFIG_CLK=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_SCMI=y
 CONFIG_SANDBOX_CLK_CCF=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -132,6 +134,8 @@
 CONFIG_DMA=y
 CONFIG_DMA_CHANNELS=y
 CONFIG_SANDBOX_DMA=y
+CONFIG_FIRMWARE=y
+CONFIG_SCMI_FIRMWARE=y
 CONFIG_GPIO_HOG=y
 CONFIG_DM_GPIO_LOOKUP_LABEL=y
 CONFIG_PM8916_GPIO=y
@@ -217,6 +221,7 @@
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_RESET_SYSCON=y
+CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 8fdd21c..5d6fe4f 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig

@@ -23,7 +23,7 @@
 CONFIG_VERSION_VARIABLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FPGA=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set

diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 13a4051..7a46f9c 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig

@@ -3,8 +3,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmtuge1"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_TUGE1=y
@@ -119,7 +119,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -148,8 +147,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -158,7 +158,9 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 343e11a..ada9b0c 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig

@@ -3,8 +3,8 @@
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
 CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1"
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
 CONFIG_TARGET_TUXX1=y
@@ -141,7 +141,6 @@
 CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
 CONFIG_LCRR_EADC_1=y
 CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -170,8 +169,9 @@
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_ADDR=0xF00C0000
 CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_BOOTCOUNT_MEM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -180,7 +180,10 @@
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
+# CONFIG_PINCTRL_FULL is not set
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 4c463f4..5175571 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig

@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x100000
@@ -25,12 +26,15 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -64,6 +68,7 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
@@ -71,10 +76,11 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
 CONFIG_PHY_GIGE=y
-CONFIG_MII=y
+CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ARM_DCC=y
 CONFIG_PL01X_SERIAL=y
+CONFIG_XILINX_UARTLITE=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
@@ -93,4 +99,3 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 8acdab2..b127945 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig

@@ -20,7 +20,7 @@
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 # CONFIG_BOOTM_NETBSD is not set

diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 485bc55..4d313e1 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig

@@ -49,7 +49,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y

diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 43a857d..ccd933f 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig

@@ -49,7 +49,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y

diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index a7cd93e..6ada862 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig

@@ -49,6 +49,7 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SYS_NAND_MAX_CHIPS=2

diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index fb657bf..04e1748 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig

@@ -49,6 +49,7 @@
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_ARM_DCC=y

diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 706e798..0fff0db 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig

@@ -8,8 +8,8 @@
 CONFIG_SPL=y
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
-# CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
+# CONFIG_PSCI_RESET is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
 # CONFIG_EXPERT is not set
 # CONFIG_LEGACY_IMAGE_FORMAT is not set
@@ -49,7 +49,6 @@
 CONFIG_OF_EMBED=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_NET is not set
-CONFIG_SPL_DM=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y

diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig
index 713418e..f7433e9 100644
--- a/configs/xilinx_zynqmp_r5_defconfig
+++ b/configs/xilinx_zynqmp_r5_defconfig

@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQMP_R5=y
 CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DEBUG_UART_BASE=0xff010000
@@ -18,3 +19,4 @@
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_TIMER=y
 CONFIG_CADENCE_TTC_TIMER=y
+# CONFIG_EFI_LOADER is not set

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index a0984c8..264b662 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig

@@ -58,10 +58,13 @@
 CONFIG_CMD_UBI=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
-CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
@@ -95,6 +98,7 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SYS_NAND_MAX_CHIPS=2
@@ -107,6 +111,7 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_MARVELL=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
@@ -116,11 +121,12 @@
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
-CONFIG_MII=y
+CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_ARM_DCC=y
+CONFIG_XILINX_UARTLITE=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_SPI=y
 CONFIG_ZYNQ_SPI=y
@@ -146,4 +152,3 @@
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/doc/README.chromium b/doc/README.chromium
index 8f67da6..75f2f24 100644
--- a/doc/README.chromium
+++ b/doc/README.chromium

@@ -23,6 +23,13 @@
         from U-Boot in 2013) and coreboot. See below for more information on
         this.
 
+   - Running U-Boot from coreboot. This allows U-Boot to run on more devices
+        since many of them only support coreboot as the bootloader and have
+        no bare-metal support in U-Boot. For this, use the 'coreboot' target.
+
+   - Running U-Boot and booting into a Chrome OS image, but without verified
+        boot. This can be useful for testing.
+
 
 U-Boot with Chromium OS verified boot
 -------------------------------------
@@ -168,14 +175,42 @@
 The U-Boot tests ('make check') do operate, but at present there are no
 Chromium OS tests available. These will hopefully come together over time. Of
 course the above sandbox feature provides a sort of functional test and can
-detecte problems that affect the flow or particular vboot features.
+detect problems that affect the flow or particular vboot features.
+
+
+U-Boot without Chromium OS verified boot
+----------------------------------------
+
+The following script can be used to boot a Chrome OS image on coral:
+
+   # Read the image header and obtain the address of the kernel
+   # The offset 4f0 is defined by verified boot and may change for other
+   # Chromebooks
+   read mmc 2:2 100000 0 80; setexpr loader *001004f0;
 
+   # Get the kernel size and calculate the number of blocks (0x200 bytes each)
+   setexpr size *00100518; setexpr blocks $size / 200;
+
+   # Read the full kernel and calculate the address of the setup block
+   read mmc 2:2 100000 80 $blocks; setexpr setup $loader - 1000;
+
+   # Locate the command line
+   setexpr cmdline $loader - 2000;
+
+   # Start the zboot process with the loaded kernel, setup block and cmdline
+   zboot start 100000 0 0 0 $setup $cmdline;
+
+   # Load the kernel, fix up the 'setup' block, dump information
+   zboot load; zboot setup; zboot dump
+
+   # Boot into Chrome OS
+   zboot go
+
 
 TO DO
 -----
 
-- Support for booting from coreboot (patches expected March 2019)
-- Support for booting from an ARM board, e.g. bob
+Get the full ACPI tables working with Coral
 
 
 Simon Glass

diff --git a/doc/README.udp b/doc/README.udp
new file mode 100644
index 0000000..da07257
--- /dev/null
+++ b/doc/README.udp

@@ -0,0 +1,35 @@
+Udp framework
+
+The udp framework is build on top of network framework and is designed
+to define new protocol or new command based on udp without modifying
+the network framework.
+
+The udp framework define a function udp_loop that take as argument
+a structure udp_ops (defined in include/net/udp.h) :
+
+struct udp_ops {
+	int (*prereq)(void *data);
+	int (*start)(void *data);
+	void *data;
+};
+
+The callback prereq define if all the requirements are
+valid before running the network/udp loop.
+
+The callback start define the first step in the network/udp loop,
+and it may also be used to configure a timemout and udp handler.
+
+The pointer data is used to store private data that
+could be used by both callback.
+
+A simple example to use this framework:
+
+static struct udp_ops udp_ops = {
+	.prereq = wmp_prereq,
+	.start = wmp_start,
+	.data = NULL,
+};
+
+...
+
+err = udp_loop(&udp_ops);

diff --git a/doc/board/intel/edison.rst b/doc/board/intel/edison.rst
index 1aee2a1..d658fac 100644
--- a/doc/board/intel/edison.rst
+++ b/doc/board/intel/edison.rst

@@ -39,3 +39,123 @@
    reset the board::
 
    => reset
+
+
+Updating U-Boot using xFSTK
+---------------------------
+
+You can also update U-Boot using the xfstk-dldr-solo tool if you can build it.
+One way to do that is to follow the `xFSTK`_ instructions. You may need to use
+a virtual machine running Ubuntu Trusty. Once you have built it and installed
+libboost-all-dev, you can copy xfstk-dldr-solo to /usr/local/bin and
+libboost_program_options.so.1.54.0 to /usr/lib/i386-linux-gnu/ and with luck
+it will work. You might fine this `drive`_ helpful.
+
+If it does, then you can download and unpack the Edison reocovery image,
+install dfu-util, reset your board and flash U-Boot like this::
+
+   $ xfstk-dldr-solo --gpflags 0x80000007 \
+      --osimage u-boot-edison.img \
+      --fwdnx recover/edison_dnx_fwr.bin \
+      --fwimage recover/edison_ifwi-dbg-00.bin \
+      --osdnx recover/edison_dnx_osr.bin
+
+This should show the following
+
+.. code-block:: none
+
+  XFSTK Downloader Solo 0.0.0
+  Copyright (c) 2015 Intel Corporation
+  Build date and time: Aug 15 2020 15:07:13
+
+  .Intel SoC Device Detection Found
+  Parsing Commandline....
+  Registering Status Callback....
+  .Initiating Download Process....
+  .......(lots of dots)........XFSTK-STATUS--Reconnecting to device - Attempt #1
+  .......(even more dots)......................
+
+
+You have about 10 seconds after resetting the board to type the above command.
+If you want to check if the board is ready, type:
+
+.. code-block:: none
+
+  lsusb |egrep "8087|8086"
+  Bus 001 Device 004: ID 8086:e005 Intel Corp.
+
+If you see a device with the same ID as above, the board is waiting for your
+command.
+
+After about 5 seconds you should see some console output from the board:
+
+.. code-block:: none
+
+  ******************************
+  PSH KERNEL VERSION: b0182b2b
+  		WR: 20104000
+  ******************************
+
+  SCU IPC: 0x800000d0  0xfffce92c
+
+  PSH miaHOB version: TNG.B0.VVBD.0000000c
+
+  microkernel built 11:24:08 Feb  5 2015
+
+  ******* PSH loader *******
+  PCM page cache size = 192 KB
+  Cache Constraint = 0 Pages
+  Arming IPC driver ..
+  Adding page store pool ..
+  PagestoreAddr(IMR Start Address) = 0x04899000
+  pageStoreSize(IMR Size)          = 0x00080000
+
+  *** Ready to receive application ***
+
+  After another 10 seconds the xFSTK tool completes and the board resets. About
+  10 seconds after that should see the above message again and then within a
+  few seconds U-Boot should start on your board:
+
+.. code-block:: none
+
+  U-Boot 2020.10-rc3 (Sep 03 2020 - 18:44:28 -0600)
+
+  CPU:   Genuine Intel(R) CPU   4000  @  500MHz
+  DRAM:  980.6 MiB
+  WDT:   Started with servicing (60s timeout)
+  MMC:   mmc@ff3fc000: 0, mmc@ff3fa000: 1
+  Loading Environment from MMC... OK
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Saving Environment to MMC... Writing to redundant MMC(0)... OK
+  Saving Environment to MMC... Writing to MMC(0)... OK
+  Net:   No ethernet found.
+  Hit any key to stop autoboot:  0
+  Target:blank
+  Partitioning using GPT
+  Writing GPT: success!
+  Saving Environment to MMC... Writing to redundant MMC(0)... OK
+  Flashing already done...
+  5442816 bytes read in 238 ms (21.8 MiB/s)
+  Valid Boot Flag
+  Setup Size = 0x00003c00
+  Magic signature found
+  Using boot protocol version 2.0c
+  Linux kernel version 3.10.17-poky-edison+ (ferry@kalamata) #1 SMP PREEMPT Mon Jan 11 14:54:18 CET 2016
+  Building boot_params at 0x00090000
+  Loading bzImage at address 100000 (5427456 bytes)
+  Magic signature found
+  Kernel command line: "rootwait root=PARTUUID=ada722ed-6410-764e-8619-abff6f66e10e rootfstype=ext4 console=ttyMFD2 earlyprintk=ttyMFD2,keep loglevel=4 g_multi.ethernet_config=cdc systemd.unit=multi-user.target hardware_id=00 g_multi.iSerialNumber=2249baf774c675598661a63098c0ad41 g_multi.dev_addr=02:00:86:c0:ad:41 platform_mrfld_audio.audio_codec=dummy"
+  Magic signature found
+
+  Starting kernel ...
+
+  ...
+
+  Poky (Yocto Project Reference Distro) 1.7.2 edison ttyMFD2
+
+  edison login:
+
+.. _xFSTK: https://community.intel.com/t5/Intel-Makers/Building-xFSTK-on-Ubuntu-14-04-32-bit-for-flashing-Edison/td-p/538081
+.. _drive: https://drive.google.com/drive/u/0/folders/1URPHrOk9-UBsh8hjv-7WwC0W6Fy61uAJ

diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
index efcde9a..3f791b4 100644
--- a/doc/board/sipeed/maix.rst
+++ b/doc/board/sipeed/maix.rst

@@ -59,7 +59,7 @@
 Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic    first
 Sipeed MAIXDUINO         sipeed_maix_bitm_defconfig maixduino  first
 Sipeed MAIX GO                                      goE        second
-Sipeed MAIX ONE DOCK                                goD        first
+Sipeed MAIX ONE DOCK                                dan        first
 ======================== ========================== ========== ==========
 
 Flashing causes a reboot of the device. Parameter -t specifies that the serial
@@ -285,11 +285,15 @@
 Boot Sequence
 ^^^^^^^^^^^^^
 
-1. ``RESET`` pin is deasserted.
+1. ``RESET`` pin is deasserted. The pin is connected to the ``RESET`` button. It
+   can also be set to low via either the ``DTR`` or the ``RTS`` line of the
+   serial interface (depending on the board).
 2. Both harts begin executing at ``0x00001000``.
 3. Both harts jump to firmware at ``0x88000000``.
 4. One hart is chosen as a boot hart.
-5. Firmware reads value of pin ``IO_16`` (ISP).
+5. Firmware reads the value of pin ``IO_16`` (ISP). This pin is connected to the
+   ``BOOT`` button. The pin can equally be set to low via either the ``DTR`` or
+   ``RTS`` line of the serial interface (depending on the board).
 
    * If the pin is low, enter ISP mode. This mode allows loading data to ram,
      writing it to flash, and booting from specific addresses.

diff --git a/doc/device-tree-bindings/arm/arm,scmi.txt b/doc/device-tree-bindings/arm/arm,scmi.txt
new file mode 100644
index 0000000..1f293ea
--- /dev/null
+++ b/doc/device-tree-bindings/arm/arm,scmi.txt

@@ -0,0 +1,197 @@
+System Control and Management Interface (SCMI) Message Protocol
+----------------------------------------------------------
+
+The SCMI is intended to allow agents such as OSPM to manage various functions
+that are provided by the hardware platform it is running on, including power
+and performance functions.
+
+This binding is intended to define the interface the firmware implementing
+the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
+and Management Interface Platform Design Document")[0] provide for OSPM in
+the device tree.
+
+Required properties:
+
+The scmi node with the following properties shall be under the /firmware/ node.
+
+- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
+- mboxes: List of phandle and mailbox channel specifiers. It should contain
+	  exactly one or two mailboxes, one for transmitting messages("tx")
+	  and another optional for receiving the notifications("rx") if
+	  supported.
+- shmem : List of phandle pointing to the shared memory(SHM) area as per
+	  generic mailbox client binding.
+- #address-cells : should be '1' if the device has sub-nodes, maps to
+	  protocol identifier for a given sub-node.
+- #size-cells : should be '0' as 'reg' property doesn't have any size
+	  associated with it.
+- arm,smc-id : SMC id required when using smc or hvc transports
+
+Optional properties:
+
+- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
+about the generic mailbox controller and client driver bindings.
+
+The mailbox is the only permitted method of calling the SCMI firmware.
+Mailbox doorbell is used as a mechanism to alert the presence of a
+messages and/or notification.
+
+Each protocol supported shall have a sub-node with corresponding compatible
+as described in the following sections. If the platform supports dedicated
+communication channel for a particular protocol, the 3 properties namely:
+mboxes, mbox-names and shmem shall be present in the sub-node corresponding
+to that protocol.
+
+Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Required properties:
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
+
+Power domain bindings for the power domains based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding for the SCMI power domain providers uses the generic power
+domain binding[2].
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+			 domain ID value used by SCMI commands.
+
+Sensor bindings for the sensors based on SCMI Message Protocol
+--------------------------------------------------------------
+SCMI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- #thermal-sensor-cells: should be set to 1. This property follows the
+			 thermal device tree bindings[3].
+
+			 Valid cell values are raw identifiers (Sensor ID)
+			 as used by the firmware. Refer to  platform details
+			 for your implementation for the IDs to use.
+
+Reset signal bindings for the reset domains based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding for the SCMI reset domain providers uses the generic reset
+signal binding[5].
+
+Required properties:
+ - #reset-cells : Should be 1. Contains the reset domain ID value used
+		  by SCMI commands.
+
+SRAM and Shared Memory for SCMI
+-------------------------------
+
+A small area of SRAM is reserved for SCMI communication between application
+processors and SCP.
+
+The properties should follow the generic mmio-sram description found in [4]
+
+Each sub-node represents the reserved area for SCMI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
+	       shared memory
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/power/power-domain.yaml
+[3] Documentation/devicetree/bindings/thermal/thermal.txt
+[4] Documentation/devicetree/bindings/sram/sram.yaml
+[5] Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+sram@50000000 {
+	compatible = "mmio-sram";
+	reg = <0x0 0x50000000 0x0 0x10000>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0x0 0x50000000 0x10000>;
+
+	cpu_scp_lpri: scp-shmem@0 {
+		compatible = "arm,scmi-shmem";
+		reg = <0x0 0x200>;
+	};
+
+	cpu_scp_hpri: scp-shmem@200 {
+		compatible = "arm,scmi-shmem";
+		reg = <0x200 0x200>;
+	};
+};
+
+mailbox@40000000 {
+	....
+	#mbox-cells = <1>;
+	reg = <0x0 0x40000000 0x0 0x10000>;
+};
+
+firmware {
+
+	...
+
+	scmi {
+		compatible = "arm,scmi";
+		mboxes = <&mailbox 0 &mailbox 1>;
+		mbox-names = "tx", "rx";
+		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi_devpd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi_dvfs: protocol@13 {
+			reg = <0x13>;
+			#clock-cells = <1>;
+		};
+
+		scmi_clk: protocol@14 {
+			reg = <0x14>;
+			#clock-cells = <1>;
+		};
+
+		scmi_sensors0: protocol@15 {
+			reg = <0x15>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		scmi_reset: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+};
+
+cpu@0 {
+	...
+	reg = <0 0>;
+	clocks = <&scmi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+	...
+	reg = <0 0x7ff60000 0 0x1000>;
+	clocks = <&scmi_clk 4>;
+	power-domains = <&scmi_devpd 1>;
+	resets = <&scmi_reset 10>;
+};
+
+thermal-zones {
+	soc_thermal {
+		polling-delay-passive = <100>;
+		polling-delay = <1000>;
+					/* sensor ID */
+		thermal-sensors = <&scmi_sensors0 3>;
+		...
+	};
+};

diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt
index d4dfc05..e5ba672 100644
--- a/doc/device-tree-bindings/chosen.txt
+++ b/doc/device-tree-bindings/chosen.txt

@@ -143,3 +143,21 @@
 node to add. The ACPI information is written in this order.
 
 If the ordering does not include all nodes, an error is generated.
+
+e820-entries
+------------
+
+This provides a way to add entries to the e820 table which tells the OS about
+the memory map. The property contains three sets of 64-bit values:
+
+   address   - Start address of region
+   size      - Size of region
+   flags     - Flags (E820_...)
+
+Example:
+
+chosen {
+	e820-entries = /bits/ 64 <
+		IOMAP_P2SB_BAR IOMAP P2SB_SIZE E820_RESERVED
+		MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
+};

diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt
index 2a5736c..73ce2a3 100644
--- a/doc/device-tree-bindings/device.txt
+++ b/doc/device-tree-bindings/device.txt

@@ -22,6 +22,8 @@
  - acpi,name : Provides the ACPI name for a device, which is a string consisting
    of four alphanumeric character (upper case)
  - acpi,uid : _UID value for device
+ - acpi,wake : Provides the GPE used to detect a request from a device to wake
+   from sleep
  - linux,probed : Tells U-Boot to add 'linux,probed' to the ACPI tables so that
     Linux will only load the driver if the device can be detected (e.g. on I2C
     bus). Note that this is an out-of-tree Linux feature.
@@ -46,6 +48,7 @@
 		compatible = "intel,generic-wifi";
 		acpi,ddn = "Intel WiFi";
 		acpi,name = "WF00";
+		acpi,wake = <GPE0_DW3_00>;
 		interrupts-extended = <&acpi_gpe 0x3c 0>;
 	};
 };

diff --git a/doc/device-tree-bindings/i2c/generic-acpi.txt b/doc/device-tree-bindings/i2c/generic-acpi.txt
new file mode 100644
index 0000000..3510a71
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/generic-acpi.txt

@@ -0,0 +1,42 @@
+I2C generic device
+==================
+
+This is used only to generate ACPI tables for an I2C device.
+
+Required properties :
+
+ - compatible : "i2c-chip";
+ - reg : I2C chip address
+ - acpi,hid : HID name for the device
+
+Optional properies in addition to device.txt:
+
+ - reset-gpios : GPIO used to assert reset to the device
+ - irq-gpios : GPIO used for interrupt (if Interrupt is not used)
+ - stop-gpios : GPIO used to stop the device
+ - interrupts-extended : Interrupt to use for the device
+ - reset-delay-ms : Delay after de-asserting reset, in ms
+ - reset-off-delay-ms : Delay after asserting reset (during power off)
+ - enable-delay-ms : Delay after asserting enable
+ - enable-off-delay-ms : Delay after de-asserting enable (during power off)
+ - stop-delay-ms : Delay after de-aserting stop
+ - stop-off-delay-ms : Delay after asserting stop (during power off)
+ - hid-descr-addr : HID register offset (for Human Interface Devices)
+
+Example
+-------
+
+	elan-touchscreen@10 {
+		compatible = "i2c-chip";
+		reg = <0x10>;
+		acpi,hid = "ELAN0001";
+		acpi,ddn = "ELAN Touchscreen";
+		interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+			IRQ_TYPE_EDGE_FALLING>;
+		linux,probed;
+		reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+		reset-delay-ms = <20>;
+		enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+		enable-delay-ms = <1>;
+		acpi,has-power-resource;
+	};

diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574b..a44c5fd 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt

@@ -2,7 +2,7 @@
 
 Properties:
 
-  - compatible : Should be "fsl,etsec2"
+  - compatible : Should be "fsl,etsec2" or "gianfar"
   - reg : Offset and length of the register set for the device
   - phy-handle : See ethernet.txt file in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory. This

diff --git a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
index c2fa6e8..5708c23 100644
--- a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
+++ b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt

@@ -25,6 +25,8 @@
 			                       K3 AM65x SoCs
 			    "ti,j721e-r5fss" for R5F clusters/subsystems on
 			                       K3 J721E SoCs
+			    "ti,j7200-r5fss" for R5F clusters/subsystems on
+			                       K3 J7200 SoCs
 - power-domains:	Should contain a phandle to a PM domain provider node
 			and an args specifier containing the R5FSS device id
 			value. This property is as per the binding,
@@ -56,6 +58,7 @@
 - compatible:		Should be one of the following,
 			    "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
 			    "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
+			    "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
 - reg:			Should contain an entry for each value in 'reg-names'.
 			Each entry should have the memory region's start address
 			and the size of the region, the representation matching
@@ -79,7 +82,7 @@
 			specifier. Please refer to the following reset bindings
 			for the reset argument specifier,
 			Documentation/devicetree/bindings/reset/ti,sci-reset.txt
-			    for AM65x and J721E SoCs
+			    for AM65x, J721E and J7200 SoCs
 
 Optional properties:
 --------------------

diff --git a/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ucc.txt b/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 0000000..2758f86
--- /dev/null
+++ b/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ucc.txt

@@ -0,0 +1,53 @@
+* UCC (Unified Communications Controllers)
+
+Required properties:
+- compatible : ucc_geth
+- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
+- reg : Offset and length of the register set for the device
+- rx-clock-name: the UCC receive clock source
+  "none": clock source is disabled
+  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+- tx-clock-name: the UCC transmit clock source
+  "none": clock source is disabled
+  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+The following two properties are deprecated.  rx-clock has been replaced
+with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
+Drivers that currently use the deprecated properties should continue to
+do so, in order to support older device trees, but they should be updated
+to check for the new properties first.
+- rx-clock : represents the UCC receive clock source.
+  0x00 : clock source is disabled;
+  0x1~0x10 : clock source is BRG1~BRG16 respectively;
+  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+- tx-clock: represents the UCC transmit clock source;
+  0x00 : clock source is disabled;
+  0x1~0x10 : clock source is BRG1~BRG16 respectively;
+  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+- phy-handle : The phandle for the PHY connected to this controller.
+- phy-connection-type : a string naming the controller/PHY interface type,
+  i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
+  Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
+  "tbi", or "rtbi".
+- pio-handle : The phandle for the Parallel I/O port configuration.
+
+Deprecated properties:
+- device-id : the ucc number(1-8), corresponding to UCCx in UM.
+    you should use cell-index
+
+Example:
+        ucc@2000 {
+                device_type = "network";
+                compatible = "ucc_geth";
+                cell-index = <1>;
+                reg = <2000 200>;
+                interrupts = <a0 0>;
+                interrupt-parent = <700>;
+                mac-address = [ 00 04 9f 00 23 23 ];
+                rx-clock = "none";
+                tx-clock = "clk9";
+                phy-handle = <212000>;
+                phy-connection-type = "gmii";
+                pio-handle = <140001>;
+        };

diff --git a/drivers/Makefile b/drivers/Makefile
index 33126b2..9eb5145 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile

@@ -30,6 +30,7 @@
 obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
 obj-$(CONFIG_$(SPL_)BOARD) += board/
 obj-$(CONFIG_XEN) += xen/
+obj-$(CONFIG_$(SPL_)FPGA) += fpga/
 
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
@@ -60,7 +61,6 @@
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
 obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/
-obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 obj-$(CONFIG_SPL_THERMAL) += thermal/
 
 endif
@@ -85,7 +85,6 @@
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
-obj-$(CONFIG_FPGA) += fpga/
 obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/

diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index 825fe57..ed0527c 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c

@@ -62,13 +62,13 @@
 
 	ret = generic_phy_init(&phy);
 	if (ret) {
-		pr_err("unable to initialize the sata phy\n");
+		pr_debug("unable to initialize the sata phy\n");
 		return ret;
 	}
 
 	ret = generic_phy_power_on(&phy);
 	if (ret) {
-		pr_err("unable to power on the sata phy\n");
+		pr_debug("unable to power on the sata phy\n");
 		return ret;
 	}
 

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6003e14..4dfbad7 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig

@@ -159,6 +159,14 @@
 	   Enable the clock synthesizer driver for CDCE913/925/937/949
 	   series of chips.
 
+config CLK_SCMI
+	bool "Enable SCMI clock driver"
+	depends on SCMI_FIRMWARE
+	help
+	  Enable this option if you want to support clock devices exposed
+	  by a SCMI agent based on SCMI clock protocol communication
+	  with a SCMI server.
+
 source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cda4b4b..d1e295a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile

@@ -32,6 +32,7 @@
 obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
+obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
 obj-$(CONFIG_CLK_SIFIVE) += sifive/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index d1940f1..aab7d14 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c

@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
-#include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/clock/aspeed-clock.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
@@ -122,8 +122,7 @@
 	ulong rate;
 
 	switch (clk->id) {
-	case PLL_HPLL:
-	case ARMCLK:
+	case ASPEED_CLK_HPLL:
 		/*
 		 * This ignores dynamic/static slowdown of ARMCLK and may
 		 * be inaccurate.
@@ -131,11 +130,11 @@
 		rate = ast2500_get_hpll_rate(clkin,
 					     readl(&priv->scu->h_pll_param));
 		break;
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		rate = ast2500_get_mpll_rate(clkin,
 					     readl(&priv->scu->m_pll_param));
 		break;
-	case BCLK_PCLK:
+	case ASPEED_CLK_APB:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@
 			rate = rate / apb_div;
 		}
 		break;
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		{
 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
 						  & SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@
 			rate = rate / apb_div;
 		}
 		break;
-	case PCLK_UART1:
+	case ASPEED_CLK_GATE_UART1CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 1);
 		break;
-	case PCLK_UART2:
+	case ASPEED_CLK_GATE_UART2CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 2);
 		break;
-	case PCLK_UART3:
+	case ASPEED_CLK_GATE_UART3CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 3);
 		break;
-	case PCLK_UART4:
+	case ASPEED_CLK_GATE_UART4CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 4);
 		break;
-	case PCLK_UART5:
+	case ASPEED_CLK_GATE_UART5CLK:
 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
 		break;
 	default:
@@ -431,11 +430,10 @@
 
 	ulong new_rate;
 	switch (clk->id) {
-	case PLL_MPLL:
-	case MCLK_DDR:
+	case ASPEED_CLK_MPLL:
 		new_rate = ast2500_configure_ddr(priv->scu, rate);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		new_rate = ast2500_configure_d2pll(priv->scu, rate);
 		break;
 	default:
@@ -450,7 +448,7 @@
 	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case BCLK_SDCLK:
+	case ASPEED_CLK_SDIO:
 		if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
 			ast_scu_unlock(priv->scu);
 
@@ -471,13 +469,13 @@
 	 * configured based on whether RGMII or RMII mode has been selected
 	 * through hardware strapping.
 	 */
-	case PCLK_MAC1:
+	case ASPEED_CLK_GATE_MAC1CLK:
 		ast2500_configure_mac(priv->scu, 1);
 		break;
-	case PCLK_MAC2:
+	case ASPEED_CLK_GATE_MAC2CLK:
 		ast2500_configure_mac(priv->scu, 2);
 		break;
-	case PLL_D2PLL:
+	case ASPEED_CLK_D2PLL:
 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
 		break;
 	default:
@@ -497,9 +495,9 @@
 {
 	struct ast2500_clk_priv *priv = dev_get_priv(dev);
 
-	priv->scu = dev_read_addr_ptr(dev);
-	if (!priv->scu)
-		return -EINVAL;
+	priv->scu = devfdt_get_addr_ptr(dev);
+	if (IS_ERR(priv->scu))
+		return PTR_ERR(priv->scu);
 
 	return 0;
 }

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 2c20edd..55e1f8c 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c

@@ -53,4 +53,5 @@
 	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
 	.ops = &clk_fixed_rate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };

diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
new file mode 100644
index 0000000..93a4819
--- /dev/null
+++ b/drivers/clk/clk_scmi.c

@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-2020 Linaro Limited
+ */
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <asm/types.h>
+
+static int scmi_clk_gate(struct clk *clk, int enable)
+{
+	struct scmi_clk_state_in in = {
+		.clock_id = clk->id,
+		.attributes = enable,
+	};
+	struct scmi_clk_state_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+					  SCMI_CLOCK_CONFIG_SET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_clk_enable(struct clk *clk)
+{
+	return scmi_clk_gate(clk, 1);
+}
+
+static int scmi_clk_disable(struct clk *clk)
+{
+	return scmi_clk_gate(clk, 0);
+}
+
+static ulong scmi_clk_get_rate(struct clk *clk)
+{
+	struct scmi_clk_rate_get_in in = {
+		.clock_id = clk->id,
+	};
+	struct scmi_clk_rate_get_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+					  SCMI_CLOCK_RATE_GET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+	if (ret < 0)
+		return ret;
+
+	ret = scmi_to_linux_errno(out.status);
+	if (ret < 0)
+		return ret;
+
+	return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);
+}
+
+static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct scmi_clk_rate_set_in in = {
+		.clock_id = clk->id,
+		.flags = SCMI_CLK_RATE_ROUND_CLOSEST,
+		.rate_lsb = (u32)rate,
+		.rate_msb = (u32)((u64)rate >> 32),
+	};
+	struct scmi_clk_rate_set_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+					  SCMI_CLOCK_RATE_SET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(clk->dev->parent, &msg);
+	if (ret < 0)
+		return ret;
+
+	ret = scmi_to_linux_errno(out.status);
+	if (ret < 0)
+		return ret;
+
+	return scmi_clk_get_rate(clk);
+}
+
+static const struct clk_ops scmi_clk_ops = {
+	.enable = scmi_clk_enable,
+	.disable = scmi_clk_disable,
+	.get_rate = scmi_clk_get_rate,
+	.set_rate = scmi_clk_set_rate,
+};
+
+U_BOOT_DRIVER(scmi_clock) = {
+	.name = "scmi_clk",
+	.id = UCLASS_CLK,
+	.ops = &scmi_clk_ops,
+};

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 2313ac0..7795119 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c

@@ -710,7 +710,7 @@
 };
 
 U_BOOT_DRIVER(zynqmp_clk) = {
-	.name = "zynqmp-clk",
+	.name = "zynqmp_clk",
 	.id = UCLASS_CLK,
 	.of_match = zynqmp_clk_ids,
 	.probe = zynqmp_clk_probe,

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 981b3b7..bb19696 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c

@@ -646,6 +646,10 @@
 	REGISTER_GATE(K210_CLK_RTC,   "rtc",   in0);
 #undef REGISTER_GATE
 
+	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
+	clk_dm(K210_CLK_CLINT,
+	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+
 	return 0;
 }
 

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 00d1d80..1ca5d66 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig

@@ -277,4 +277,13 @@
 	  things like generating device-specific tables and returning the ACPI
 	  name of a device.
 
+config INTEL_ACPIGEN
+	bool "Support ACPI table generation for Intel SoCs"
+	depends on ACPIGEN
+	help
+	  This option adds some functions used for programatic generation of
+	  ACPI tables on Intel SoCs. This provides features for writing CPU
+	  information such as P states and T stages. Also included is a way
+	  to create a GNVS table and set it up.
+
 endmenu

diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 922e78f..bcf1644 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c

@@ -745,13 +745,14 @@
 
 int of_parse_phandle_with_args(const struct device_node *np,
 			       const char *list_name, const char *cells_name,
-			       int index, struct of_phandle_args *out_args)
+			       int cell_count, int index,
+			       struct of_phandle_args *out_args)
 {
 	if (index < 0)
 		return -EINVAL;
 
-	return __of_parse_phandle_with_args(np, list_name, cells_name, 0,
-					    index, out_args);
+	return __of_parse_phandle_with_args(np, list_name, cells_name,
+					    cell_count, index, out_args);
 }
 
 int of_count_phandle_with_args(const struct device_node *np,

diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index d02d8d3..79fcdf5 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c

@@ -409,7 +409,8 @@
 		int ret;
 
 		ret = of_parse_phandle_with_args(ofnode_to_np(node),
-						 list_name, cells_name, index,
+						 list_name, cells_name,
+						 cell_count, index,
 						 &args);
 		if (ret)
 			return ret;

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index a67a237..c2bed88 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c

@@ -14,7 +14,24 @@
 #include <regmap.h>
 #include <asm/io.h>
 #include <dm/of_addr.h>
+#include <dm/devres.h>
 #include <linux/ioport.h>
+#include <linux/compat.h>
+#include <linux/err.h>
+#include <linux/bitops.h>
+
+/*
+ * Internal representation of a regmap field. Instead of storing the MSB and
+ * LSB, store the shift and mask. This makes the code a bit cleaner and faster
+ * because the shift and mask don't have to be calculated every time.
+ */
+struct regmap_field {
+	struct regmap *regmap;
+	unsigned int mask;
+	/* lsb */
+	unsigned int shift;
+	unsigned int reg;
+};
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -22,16 +39,22 @@
  * regmap_alloc() - Allocate a regmap with a given number of ranges.
  *
  * @count: Number of ranges to be allocated for the regmap.
+ *
+ * The default regmap width is set to REGMAP_SIZE_32. Callers can override it
+ * if they need.
+ *
  * Return: A pointer to the newly allocated regmap, or NULL on error.
  */
 static struct regmap *regmap_alloc(int count)
 {
 	struct regmap *map;
+	size_t size = sizeof(*map) + sizeof(map->ranges[0]) * count;
 
-	map = malloc(sizeof(*map) + sizeof(map->ranges[0]) * count);
+	map = calloc(1, size);
 	if (!map)
 		return NULL;
 	map->range_count = count;
+	map->width = REGMAP_SIZE_32;
 
 	return map;
 }
@@ -155,6 +178,33 @@
 	return ret;
 }
 
+int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size,
+			  struct regmap **mapp)
+{
+	struct regmap *map;
+	struct regmap_range *range;
+
+	map = regmap_alloc(1);
+	if (!map)
+		return -ENOMEM;
+
+	range = &map->ranges[0];
+	range->start = r_start;
+	range->size = r_size;
+
+	if (ofnode_read_bool(node, "little-endian"))
+		map->endianness = REGMAP_LITTLE_ENDIAN;
+	else if (ofnode_read_bool(node, "big-endian"))
+		map->endianness = REGMAP_BIG_ENDIAN;
+	else if (ofnode_read_bool(node, "native-endian"))
+		map->endianness = REGMAP_NATIVE_ENDIAN;
+	else /* Default: native endianness */
+		map->endianness = REGMAP_NATIVE_ENDIAN;
+
+	*mapp = map;
+	return 0;
+}
+
 int regmap_init_mem(ofnode node, struct regmap **mapp)
 {
 	struct regmap_range *range;
@@ -228,6 +278,42 @@
 
 	return ret;
 }
+
+static void devm_regmap_release(struct udevice *dev, void *res)
+{
+	regmap_uninit(*(struct regmap **)res);
+}
+
+struct regmap *devm_regmap_init(struct udevice *dev,
+				const struct regmap_bus *bus,
+				void *bus_context,
+				const struct regmap_config *config)
+{
+	int rc;
+	struct regmap **mapp, *map;
+
+	mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *),
+			    __GFP_ZERO);
+	if (unlikely(!mapp))
+		return ERR_PTR(-ENOMEM);
+
+	if (config && config->r_size != 0)
+		rc = regmap_init_mem_range(dev_ofnode(dev), config->r_start,
+					   config->r_size, mapp);
+	else
+		rc = regmap_init_mem(dev_ofnode(dev), mapp);
+	if (rc)
+		return ERR_PTR(rc);
+
+	map = *mapp;
+	if (config) {
+		map->width = config->width;
+		map->reg_offset_shift = config->reg_offset_shift;
+	}
+
+	devres_add(dev, mapp);
+	return *mapp;
+}
 #endif
 
 void *regmap_get_range(struct regmap *map, unsigned int range_num)
@@ -310,6 +396,7 @@
 	}
 	range = &map->ranges[range_num];
 
+	offset <<= map->reg_offset_shift;
 	if (offset + val_len > range->size) {
 		debug("%s: offset/size combination invalid\n", __func__);
 		return -ERANGE;
@@ -347,7 +434,7 @@
 
 int regmap_read(struct regmap *map, uint offset, uint *valp)
 {
-	return regmap_raw_read(map, offset, valp, REGMAP_SIZE_32);
+	return regmap_raw_read(map, offset, valp, map->width);
 }
 
 static inline void __write_8(u8 *addr, const u8 *val,
@@ -419,6 +506,7 @@
 	}
 	range = &map->ranges[range_num];
 
+	offset <<= map->reg_offset_shift;
 	if (offset + val_len > range->size) {
 		debug("%s: offset/size combination invalid\n", __func__);
 		return -ERANGE;
@@ -457,7 +545,7 @@
 
 int regmap_write(struct regmap *map, uint offset, uint val)
 {
-	return regmap_raw_write(map, offset, &val, REGMAP_SIZE_32);
+	return regmap_raw_write(map, offset, &val, map->width);
 }
 
 int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
@@ -473,3 +561,72 @@
 
 	return regmap_write(map, offset, reg | (val & mask));
 }
+
+int regmap_field_read(struct regmap_field *field, unsigned int *val)
+{
+	int ret;
+	unsigned int reg_val;
+
+	ret = regmap_read(field->regmap, field->reg, &reg_val);
+	if (ret != 0)
+		return ret;
+
+	reg_val &= field->mask;
+	reg_val >>= field->shift;
+	*val = reg_val;
+
+	return ret;
+}
+
+int regmap_field_write(struct regmap_field *field, unsigned int val)
+{
+	return regmap_update_bits(field->regmap, field->reg, field->mask,
+				  val << field->shift);
+}
+
+static void regmap_field_init(struct regmap_field *rm_field,
+			      struct regmap *regmap,
+			      struct reg_field reg_field)
+{
+	rm_field->regmap = regmap;
+	rm_field->reg = reg_field.reg;
+	rm_field->shift = reg_field.lsb;
+	rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb);
+}
+
+struct regmap_field *devm_regmap_field_alloc(struct udevice *dev,
+					     struct regmap *regmap,
+					     struct reg_field reg_field)
+{
+	struct regmap_field *rm_field = devm_kzalloc(dev, sizeof(*rm_field),
+						     GFP_KERNEL);
+	if (!rm_field)
+		return ERR_PTR(-ENOMEM);
+
+	regmap_field_init(rm_field, regmap, reg_field);
+
+	return rm_field;
+}
+
+void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field)
+{
+	devm_kfree(dev, field);
+}
+
+struct regmap_field *regmap_field_alloc(struct regmap *regmap,
+					struct reg_field reg_field)
+{
+	struct regmap_field *rm_field = kzalloc(sizeof(*rm_field), GFP_KERNEL);
+
+	if (!rm_field)
+		return ERR_PTR(-ENOMEM);
+
+	regmap_field_init(rm_field, regmap, reg_field);
+
+	return rm_field;
+}
+
+void regmap_field_free(struct regmap_field *field)
+{
+	kfree(field);
+}

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index b5cd763..5be1d52 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c

@@ -18,12 +18,16 @@
 
 /*
  * Caution:
- * This API requires the given device has alerady been bound to syscon driver.
- * For example,
+ * This API requires the given device has already been bound to the syscon
+ * driver. For example,
+ *
  *    compatible = "syscon", "simple-mfd";
+ *
  * works, but
+ *
  *    compatible = "simple-mfd", "syscon";
- * does not.  The behavior is different from Linux.
+ *
+ * does not. The behavior is different from Linux.
  */
 struct regmap *syscon_get_regmap(struct udevice *dev)
 {
@@ -66,7 +70,7 @@
 
 	/* found node with "syscon" compatible, not bounded to SYSCON UCLASS */
 	if (!ofnode_device_is_compatible(node, "syscon")) {
-		dev_dbg(dev, "invalid compatible for syscon device\n");
+		log_debug("invalid compatible for syscon device\n");
 		return -EINVAL;
 	}
 

diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c
index caa26e5..4ba0d1b 100644
--- a/drivers/cpu/cpu_sandbox.c
+++ b/drivers/cpu/cpu_sandbox.c

@@ -8,14 +8,15 @@
 #include <dm.h>
 #include <cpu.h>
 
-int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
 {
 	snprintf(buf, size, "LEG Inc. SuperMegaUltraTurbo CPU No. 1");
 
 	return 0;
 }
 
-int cpu_sandbox_get_info(const struct udevice *dev, struct cpu_info *info)
+static int cpu_sandbox_get_info(const struct udevice *dev,
+				struct cpu_info *info)
 {
 	info->cpu_freq = 42 * 42 * 42 * 42 * 42;
 	info->features = 0x42424242;
@@ -24,21 +25,29 @@
 	return 0;
 }
 
-int cpu_sandbox_get_count(const struct udevice *dev)
+static int cpu_sandbox_get_count(const struct udevice *dev)
 {
 	return 42;
 }
 
-int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf,
+				  int size)
 {
 	snprintf(buf, size, "Languid Example Garbage Inc.");
 
 	return 0;
 }
 
-int cpu_sandbox_is_current(struct udevice *dev)
+static const char *cpu_current = "cpu-test1";
+
+void cpu_sandbox_set_current(const char *name)
 {
-	if (!strcmp(dev->name, "cpu-test1"))
+	cpu_current = name;
+}
+
+static int cpu_sandbox_is_current(struct udevice *dev)
+{
+	if (!strcmp(dev->name, cpu_current))
 		return 1;
 
 	return 0;
@@ -52,7 +61,22 @@
 	.is_current = cpu_sandbox_is_current,
 };
 
+static int cpu_sandbox_bind(struct udevice *dev)
+{
+	int ret;
+	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+	/* first examine the property in current cpu node */
+	ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
+	/* if not found, then look at the parent /cpus node */
+	if (ret)
+		ret = dev_read_u32(dev->parent, "timebase-frequency",
+				   &plat->timebase_freq);
+
+	return ret;
+}
+
-int cpu_sandbox_probe(struct udevice *dev)
+static int cpu_sandbox_probe(struct udevice *dev)
 {
 	return 0;
 }
@@ -67,5 +91,6 @@
 	.id             = UCLASS_CPU,
 	.ops		= &cpu_sandbox_ops,
 	.of_match       = cpu_sandbox_ids,
+	.bind		= cpu_sandbox_bind,
 	.probe          = cpu_sandbox_probe,
 };

diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index b70a206..ef958b3 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig

@@ -36,3 +36,5 @@
 	  various platform management services.
 	  Say yes to enable ZynqMP firmware interface driver.
 	  If in doubt, say N.
+
+source "drivers/firmware/scmi/Kconfig"

diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index a0c250a..7ce83d7 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile

@@ -3,3 +3,4 @@
 obj-$(CONFIG_TI_SCI_PROTOCOL)	+= ti_sci.o
 obj-$(CONFIG_SANDBOX)		+= firmware-sandbox.o
 obj-$(CONFIG_ZYNQMP_FIRMWARE)	+= firmware-zynqmp.o
+obj-$(CONFIG_SCMI_FIRMWARE)	+= scmi/

diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 903a8f5..7583f24a 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c

@@ -202,6 +202,6 @@
 
 U_BOOT_DRIVER(zynqmp_firmware) = {
 	.id = UCLASS_FIRMWARE,
-	.name = "zynqmp-firmware",
+	.name = "zynqmp_firmware",
 	.of_match = zynqmp_firmware_ids,
 };

diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig
new file mode 100644
index 0000000..c3a109b
--- /dev/null
+++ b/drivers/firmware/scmi/Kconfig

@@ -0,0 +1,19 @@
+config SCMI_FIRMWARE
+	bool "Enable SCMI support"
+	select FIRMWARE
+	select OF_TRANSLATE
+	depends on SANDBOX || DM_MAILBOX || ARM_SMCCC
+	help
+	  System Control and Management Interface (SCMI) is a communication
+	  protocol that defines standard interfaces for power, performance
+	  and system management. The SCMI specification is available at
+	  https://developer.arm.com/architectures/system-architectures/software-standards/scmi
+
+	  An SCMI agent communicates with a related SCMI server firmware
+	  located in another sub-system, as a companion micro controller
+	  or a companion host in the CPU system.
+
+	  Communications between agent (client) and the SCMI server are
+	  based on message exchange. Messages can be exchange over tranport
+	  channels as a mailbox device or an Arm SMCCC service with some
+	  piece of identified shared memory.

diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile
new file mode 100644
index 0000000..e1e0224
--- /dev/null
+++ b/drivers/firmware/scmi/Makefile

@@ -0,0 +1,5 @@
+obj-y	+= scmi_agent-uclass.o
+obj-y	+= smt.o
+obj-$(CONFIG_ARM_SMCCC) 	+= smccc_agent.o
+obj-$(CONFIG_DM_MAILBOX)	+= mailbox_agent.o
+obj-$(CONFIG_SANDBOX)		+= sandbox-scmi_agent.o sandbox-scmi_devices.o

diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c
new file mode 100644
index 0000000..7d9fb36
--- /dev/null
+++ b/drivers/firmware/scmi/mailbox_agent.c

@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Linaro Limited.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <mailbox.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <dm/devres.h>
+#include <linux/compat.h>
+
+#include "smt.h"
+
+#define TIMEOUT_US_10MS			10000
+
+/**
+ * struct scmi_mbox_channel - Description of an SCMI mailbox transport
+ * @smt:	Shared memory buffer
+ * @mbox:	Mailbox channel description
+ * @timeout_us:	Timeout in microseconds for the mailbox transfer
+ */
+struct scmi_mbox_channel {
+	struct scmi_smt smt;
+	struct mbox_chan mbox;
+	ulong timeout_us;
+};
+
+static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg)
+{
+	struct scmi_mbox_channel *chan = dev_get_priv(dev);
+	int ret;
+
+	ret = scmi_write_msg_to_smt(dev, &chan->smt, msg);
+	if (ret)
+		return ret;
+
+	/* Give shm addr to mbox in case it is meaningful */
+	ret = mbox_send(&chan->mbox, chan->smt.buf);
+	if (ret) {
+		dev_err(dev, "Message send failed: %d\n", ret);
+		goto out;
+	}
+
+	/* Receive the response */
+	ret = mbox_recv(&chan->mbox, chan->smt.buf, chan->timeout_us);
+	if (ret) {
+		dev_err(dev, "Response failed: %d, abort\n", ret);
+		goto out;
+	}
+
+	ret = scmi_read_resp_from_smt(dev, &chan->smt, msg);
+
+out:
+	scmi_clear_smt_channel(&chan->smt);
+
+	return ret;
+}
+
+int scmi_mbox_probe(struct udevice *dev)
+{
+	struct scmi_mbox_channel *chan = dev_get_priv(dev);
+	int ret;
+
+	chan->timeout_us = TIMEOUT_US_10MS;
+
+	ret = mbox_get_by_index(dev, 0, &chan->mbox);
+	if (ret) {
+		dev_err(dev, "Failed to find mailbox: %d\n", ret);
+		goto out;
+	}
+
+	ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
+	if (ret)
+		dev_err(dev, "Failed to get shm resources: %d\n", ret);
+
+out:
+	if (ret)
+		devm_kfree(dev, chan);
+
+	return ret;
+}
+
+static const struct udevice_id scmi_mbox_ids[] = {
+	{ .compatible = "arm,scmi" },
+	{ }
+};
+
+static const struct scmi_agent_ops scmi_mbox_ops = {
+	.process_msg = scmi_mbox_process_msg,
+};
+
+U_BOOT_DRIVER(scmi_mbox) = {
+	.name		= "scmi-over-mailbox",
+	.id		= UCLASS_SCMI_AGENT,
+	.of_match	= scmi_mbox_ids,
+	.priv_auto_alloc_size = sizeof(struct scmi_mbox_channel),
+	.probe		= scmi_mbox_probe,
+	.ops		= &scmi_mbox_ops,
+};

diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
new file mode 100644
index 0000000..5b6a423
--- /dev/null
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c

@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Linaro Limited
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
+#include <asm/io.h>
+#include <asm/scmi_test.h>
+#include <dm/device_compat.h>
+
+/*
+ * The sandbox SCMI agent driver simulates to some extend a SCMI message
+ * processing. It simulates few of the SCMI services for some of the
+ * SCMI protocols embedded in U-Boot. Currently:
+ * - SCMI clock protocol: emulate 2 agents each exposing few clocks
+ * - SCMI reset protocol: emulate 1 agents each exposing a reset
+ *
+ * Agent #0 simulates 2 clocks and 1 reset domain.
+ * See IDs in scmi0_clk[]/scmi0_reset[] and "sandbox-scmi-agent@0" in test.dts.
+ *
+ * Agent #1 simulates 1 clock.
+ * See IDs in scmi1_clk[] and "sandbox-scmi-agent@1" in test.dts.
+ *
+ * All clocks are default disabled and reset levels down.
+ *
+ * This Driver exports sandbox_scmi_service_ct() for the test sequence to
+ * get the state of the simulated services (clock state, rate, ...) and
+ * check back-end device state reflects the request send through the
+ * various uclass devices, as clocks and reset controllers.
+ */
+
+#define SANDBOX_SCMI_AGENT_COUNT	2
+
+static struct sandbox_scmi_clk scmi0_clk[] = {
+	{ .id = 7, .rate = 1000 },
+	{ .id = 3, .rate = 333 },
+};
+
+static struct sandbox_scmi_reset scmi0_reset[] = {
+	{ .id = 3 },
+};
+
+static struct sandbox_scmi_clk scmi1_clk[] = {
+	{ .id = 1, .rate = 44 },
+};
+
+/* The list saves to simulted end devices references for test purpose */
+struct sandbox_scmi_agent *sandbox_scmi_agent_list[SANDBOX_SCMI_AGENT_COUNT];
+
+static struct sandbox_scmi_service sandbox_scmi_service_state = {
+	.agent = sandbox_scmi_agent_list,
+	.agent_count = SANDBOX_SCMI_AGENT_COUNT,
+};
+
+struct sandbox_scmi_service *sandbox_scmi_service_ctx(void)
+{
+	return &sandbox_scmi_service_state;
+}
+
+static void debug_print_agent_state(struct udevice *dev, char *str)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+
+	dev_dbg(dev, "Dump sandbox_scmi_agent %u: %s\n", agent->idx, str);
+	dev_dbg(dev, " scmi%u_clk   (%zu): %d/%ld, %d/%ld, %d/%ld, ...\n",
+		agent->idx,
+		agent->clk_count,
+		agent->clk_count ? agent->clk[0].enabled : -1,
+		agent->clk_count ? agent->clk[0].rate : -1,
+		agent->clk_count > 1 ? agent->clk[1].enabled : -1,
+		agent->clk_count > 1 ? agent->clk[1].rate : -1,
+		agent->clk_count > 2 ? agent->clk[2].enabled : -1,
+		agent->clk_count > 2 ? agent->clk[2].rate : -1);
+	dev_dbg(dev, " scmi%u_reset (%zu): %d, %d, ...\n",
+		agent->idx,
+		agent->reset_count,
+		agent->reset_count ? agent->reset[0].asserted : -1,
+		agent->reset_count > 1 ? agent->reset[1].asserted : -1);
+};
+
+static struct sandbox_scmi_clk *get_scmi_clk_state(uint agent_id, uint clock_id)
+{
+	struct sandbox_scmi_clk *target = NULL;
+	size_t target_count = 0;
+	size_t n;
+
+	switch (agent_id) {
+	case 0:
+		target = scmi0_clk;
+		target_count = ARRAY_SIZE(scmi0_clk);
+		break;
+	case 1:
+		target = scmi1_clk;
+		target_count = ARRAY_SIZE(scmi1_clk);
+		break;
+	default:
+		return NULL;
+	}
+
+	for (n = 0; n < target_count; n++)
+		if (target[n].id == clock_id)
+			return target + n;
+
+	return NULL;
+}
+
+static struct sandbox_scmi_reset *get_scmi_reset_state(uint agent_id,
+						       uint reset_id)
+{
+	size_t n;
+
+	if (agent_id == 0) {
+		for (n = 0; n < ARRAY_SIZE(scmi0_reset); n++)
+			if (scmi0_reset[n].id == reset_id)
+				return scmi0_reset + n;
+	}
+
+	return NULL;
+}
+
+/*
+ * Sandbox SCMI agent ops
+ */
+
+static int sandbox_scmi_clock_rate_set(struct udevice *dev,
+				       struct scmi_msg *msg)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	struct scmi_clk_rate_set_in *in = NULL;
+	struct scmi_clk_rate_set_out *out = NULL;
+	struct sandbox_scmi_clk *clk_state = NULL;
+
+	if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+	    !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+		return -EINVAL;
+
+	in = (struct scmi_clk_rate_set_in *)msg->in_msg;
+	out = (struct scmi_clk_rate_set_out *)msg->out_msg;
+
+	clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+	if (!clk_state) {
+		dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+		out->status = SCMI_NOT_FOUND;
+	} else {
+		u64 rate = ((u64)in->rate_msb << 32) + in->rate_lsb;
+
+		clk_state->rate = (ulong)rate;
+
+		out->status = SCMI_SUCCESS;
+	}
+
+	return 0;
+}
+
+static int sandbox_scmi_clock_rate_get(struct udevice *dev,
+				       struct scmi_msg *msg)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	struct scmi_clk_rate_get_in *in = NULL;
+	struct scmi_clk_rate_get_out *out = NULL;
+	struct sandbox_scmi_clk *clk_state = NULL;
+
+	if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+	    !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+		return -EINVAL;
+
+	in = (struct scmi_clk_rate_get_in *)msg->in_msg;
+	out = (struct scmi_clk_rate_get_out *)msg->out_msg;
+
+	clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+	if (!clk_state) {
+		dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+		out->status = SCMI_NOT_FOUND;
+	} else {
+		out->rate_msb = (u32)((u64)clk_state->rate >> 32);
+		out->rate_lsb = (u32)clk_state->rate;
+
+		out->status = SCMI_SUCCESS;
+	}
+
+	return 0;
+}
+
+static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	struct scmi_clk_state_in *in = NULL;
+	struct scmi_clk_state_out *out = NULL;
+	struct sandbox_scmi_clk *clk_state = NULL;
+
+	if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+	    !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+		return -EINVAL;
+
+	in = (struct scmi_clk_state_in *)msg->in_msg;
+	out = (struct scmi_clk_state_out *)msg->out_msg;
+
+	clk_state = get_scmi_clk_state(agent->idx, in->clock_id);
+	if (!clk_state) {
+		dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+		out->status = SCMI_NOT_FOUND;
+	} else if (in->attributes > 1) {
+		out->status = SCMI_PROTOCOL_ERROR;
+	} else {
+		clk_state->enabled = in->attributes;
+
+		out->status = SCMI_SUCCESS;
+	}
+
+	return 0;
+}
+
+static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	struct scmi_rd_attr_in *in = NULL;
+	struct scmi_rd_attr_out *out = NULL;
+	struct sandbox_scmi_reset *reset_state = NULL;
+
+	if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+	    !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+		return -EINVAL;
+
+	in = (struct scmi_rd_attr_in *)msg->in_msg;
+	out = (struct scmi_rd_attr_out *)msg->out_msg;
+
+	reset_state = get_scmi_reset_state(agent->idx, in->domain_id);
+	if (!reset_state) {
+		dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id);
+
+		out->status = SCMI_NOT_FOUND;
+	} else {
+		memset(out, 0, sizeof(*out));
+		snprintf(out->name, sizeof(out->name), "rd%u", in->domain_id);
+
+		out->status = SCMI_SUCCESS;
+	}
+
+	return 0;
+}
+
+static int sandbox_scmi_rd_reset(struct udevice *dev, struct scmi_msg *msg)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	struct scmi_rd_reset_in *in = NULL;
+	struct scmi_rd_reset_out *out = NULL;
+	struct sandbox_scmi_reset *reset_state = NULL;
+
+	if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+	    !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+		return -EINVAL;
+
+	in = (struct scmi_rd_reset_in *)msg->in_msg;
+	out = (struct scmi_rd_reset_out *)msg->out_msg;
+
+	reset_state = get_scmi_reset_state(agent->idx, in->domain_id);
+	if (!reset_state) {
+		dev_err(dev, "Unexpected reset domain ID %u\n", in->domain_id);
+
+		out->status = SCMI_NOT_FOUND;
+	} else if (in->reset_state > 1) {
+		dev_err(dev, "Invalid reset domain input attribute value\n");
+
+		out->status = SCMI_INVALID_PARAMETERS;
+	} else {
+		if (in->flags & SCMI_RD_RESET_FLAG_CYCLE) {
+			if (in->flags & SCMI_RD_RESET_FLAG_ASYNC) {
+				out->status = SCMI_NOT_SUPPORTED;
+			} else {
+				/* Ends deasserted whatever current state */
+				reset_state->asserted = false;
+				out->status = SCMI_SUCCESS;
+			}
+		} else {
+			reset_state->asserted = in->flags &
+						SCMI_RD_RESET_FLAG_ASSERT;
+
+			out->status = SCMI_SUCCESS;
+		}
+	}
+
+	return 0;
+}
+
+static int sandbox_scmi_test_process_msg(struct udevice *dev,
+					 struct scmi_msg *msg)
+{
+	switch (msg->protocol_id) {
+	case SCMI_PROTOCOL_ID_CLOCK:
+		switch (msg->message_id) {
+		case SCMI_CLOCK_RATE_SET:
+			return sandbox_scmi_clock_rate_set(dev, msg);
+		case SCMI_CLOCK_RATE_GET:
+			return sandbox_scmi_clock_rate_get(dev, msg);
+		case SCMI_CLOCK_CONFIG_SET:
+			return sandbox_scmi_clock_gate(dev, msg);
+		default:
+			break;
+		}
+		break;
+	case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+		switch (msg->message_id) {
+		case SCMI_RESET_DOMAIN_ATTRIBUTES:
+			return sandbox_scmi_rd_attribs(dev, msg);
+		case SCMI_RESET_DOMAIN_RESET:
+			return sandbox_scmi_rd_reset(dev, msg);
+		default:
+			break;
+		}
+		break;
+	case SCMI_PROTOCOL_ID_BASE:
+	case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+	case SCMI_PROTOCOL_ID_SYSTEM:
+	case SCMI_PROTOCOL_ID_PERF:
+	case SCMI_PROTOCOL_ID_SENSOR:
+		*(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED;
+		return 0;
+	default:
+		break;
+	}
+
+	dev_err(dev, "%s(%s): Unhandled protocol_id %#x/message_id %#x\n",
+		__func__, dev->name, msg->protocol_id, msg->message_id);
+
+	if (msg->out_msg_sz < sizeof(u32))
+		return -EINVAL;
+
+	/* Intentionnaly report unhandled IDs through the SCMI return code */
+	*(u32 *)msg->out_msg = SCMI_PROTOCOL_ERROR;
+	return 0;
+}
+
+static int sandbox_scmi_test_remove(struct udevice *dev)
+{
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+
+	debug_print_agent_state(dev, "removed");
+
+	/* We only need to dereference the agent in the context */
+	sandbox_scmi_service_ctx()->agent[agent->idx] = NULL;
+
+	return 0;
+}
+
+static int sandbox_scmi_test_probe(struct udevice *dev)
+{
+	static const char basename[] = "sandbox-scmi-agent@";
+	struct sandbox_scmi_agent *agent = dev_get_priv(dev);
+	const size_t basename_size = sizeof(basename) - 1;
+
+	if (strncmp(basename, dev->name, basename_size))
+		return -ENOENT;
+
+	switch (dev->name[basename_size]) {
+	case '0':
+		*agent = (struct sandbox_scmi_agent){
+			.idx = 0,
+			.clk = scmi0_clk,
+			.clk_count = ARRAY_SIZE(scmi0_clk),
+			.reset = scmi0_reset,
+			.reset_count = ARRAY_SIZE(scmi0_reset),
+		};
+		break;
+	case '1':
+		*agent = (struct sandbox_scmi_agent){
+			.idx = 1,
+			.clk = scmi1_clk,
+			.clk_count = ARRAY_SIZE(scmi1_clk),
+		};
+		break;
+	default:
+		dev_err(dev, "%s(): Unexpected agent ID %s\n",
+			__func__, dev->name + basename_size);
+		return -ENOENT;
+	}
+
+	debug_print_agent_state(dev, "probed");
+
+	/* Save reference for tests purpose */
+	sandbox_scmi_service_ctx()->agent[agent->idx] = agent;
+
+	return 0;
+};
+
+static const struct udevice_id sandbox_scmi_test_ids[] = {
+	{ .compatible = "sandbox,scmi-agent" },
+	{ }
+};
+
+struct scmi_agent_ops sandbox_scmi_test_ops = {
+	.process_msg = sandbox_scmi_test_process_msg,
+};
+
+U_BOOT_DRIVER(sandbox_scmi_agent) = {
+	.name = "sandbox-scmi_agent",
+	.id = UCLASS_SCMI_AGENT,
+	.of_match = sandbox_scmi_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_scmi_agent),
+	.probe = sandbox_scmi_test_probe,
+	.remove = sandbox_scmi_test_remove,
+	.ops = &sandbox_scmi_test_ops,
+};

diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c
new file mode 100644
index 0000000..c69967b
--- /dev/null
+++ b/drivers/firmware/scmi/sandbox-scmi_devices.c

@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Linaro Limited
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/scmi_test.h>
+#include <dm/device_compat.h>
+
+/*
+ * Simulate to some extent a SCMI exchange.
+ * This drivers gets SCMI resources and offers API function to the
+ * SCMI test sequence manipulate the resources, currently clock
+ * and reset controllers.
+ */
+
+#define SCMI_TEST_DEVICES_CLK_COUNT		3
+#define SCMI_TEST_DEVICES_RD_COUNT		1
+
+/*
+ * struct sandbox_scmi_device_priv - Storage for device handles used by test
+ * @clk:		Array of clock instances used by tests
+ * @reset_clt:		Array of the reset controller instances used by tests
+ * @devices:		Resources exposed by sandbox_scmi_devices_ctx()
+ */
+struct sandbox_scmi_device_priv {
+	struct clk clk[SCMI_TEST_DEVICES_CLK_COUNT];
+	struct reset_ctl reset_ctl[SCMI_TEST_DEVICES_RD_COUNT];
+	struct sandbox_scmi_devices devices;
+};
+
+struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev)
+{
+	struct sandbox_scmi_device_priv *priv = dev_get_priv(dev);
+
+	if (priv)
+		return &priv->devices;
+
+	return NULL;
+}
+
+static int sandbox_scmi_devices_remove(struct udevice *dev)
+{
+	struct sandbox_scmi_devices *devices = sandbox_scmi_devices_ctx(dev);
+	int ret = 0;
+	size_t n;
+
+	for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+		int ret2 = reset_free(devices->reset + n);
+
+		if (ret2 && !ret)
+			ret = ret2;
+	}
+
+	return ret;
+}
+
+static int sandbox_scmi_devices_probe(struct udevice *dev)
+{
+	struct sandbox_scmi_device_priv *priv = dev_get_priv(dev);
+	int ret;
+	size_t n;
+
+	priv->devices = (struct sandbox_scmi_devices){
+		.clk = priv->clk,
+		.clk_count = SCMI_TEST_DEVICES_CLK_COUNT,
+		.reset = priv->reset_ctl,
+		.reset_count = SCMI_TEST_DEVICES_RD_COUNT,
+	};
+
+	for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
+		ret = clk_get_by_index(dev, n, priv->devices.clk + n);
+		if (ret) {
+			dev_err(dev, "%s: Failed on clk %zu\n", __func__, n);
+			return ret;
+		}
+	}
+
+	for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+		ret = reset_get_by_index(dev, n, priv->devices.reset + n);
+		if (ret) {
+			dev_err(dev, "%s: Failed on reset %zu\n", __func__, n);
+			goto err_reset;
+		}
+	}
+
+	return 0;
+
+err_reset:
+	for (; n > 0; n--)
+		reset_free(priv->devices.reset + n - 1);
+
+	return ret;
+}
+
+static const struct udevice_id sandbox_scmi_devices_ids[] = {
+	{ .compatible = "sandbox,scmi-devices" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_scmi_devices) = {
+	.name = "sandbox-scmi_devices",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_scmi_devices_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_scmi_device_priv),
+	.remove = sandbox_scmi_devices_remove,
+	.probe = sandbox_scmi_devices_probe,
+};

diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
new file mode 100644
index 0000000..77160b1
--- /dev/null
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Linaro Limited.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
+
+#include <dm/device-internal.h>
+#include <linux/compat.h>
+
+/**
+ * struct error_code - Helper structure for SCMI error code conversion
+ * @scmi:	SCMI error code
+ * @errno:	Related standard error number
+ */
+struct error_code {
+	int scmi;
+	int errno;
+};
+
+static const struct error_code scmi_linux_errmap[] = {
+	{ .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, },
+	{ .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, },
+	{ .scmi = SCMI_DENIED, .errno = -EACCES, },
+	{ .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, },
+	{ .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, },
+	{ .scmi = SCMI_BUSY, .errno = -EBUSY, },
+	{ .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, },
+	{ .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, },
+	{ .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, },
+	{ .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, },
+};
+
+int scmi_to_linux_errno(s32 scmi_code)
+{
+	int n;
+
+	if (!scmi_code)
+		return 0;
+
+	for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++)
+		if (scmi_code == scmi_linux_errmap[n].scmi)
+			return scmi_linux_errmap[1].errno;
+
+	return -EPROTO;
+}
+
+/*
+ * SCMI agent devices binds devices of various uclasses depeding on
+ * the FDT description. scmi_bind_protocol() is a generic bind sequence
+ * called by the uclass at bind stage, that is uclass post_bind.
+ */
+static int scmi_bind_protocols(struct udevice *dev)
+{
+	int ret = 0;
+	ofnode node;
+
+	dev_for_each_subnode(node, dev) {
+		struct driver *drv = NULL;
+		u32 protocol_id;
+
+		if (!ofnode_is_available(node))
+			continue;
+
+		if (ofnode_read_u32(node, "reg", &protocol_id))
+			continue;
+
+		switch (protocol_id) {
+		case SCMI_PROTOCOL_ID_CLOCK:
+			if (IS_ENABLED(CONFIG_CLK_SCMI))
+				drv = DM_GET_DRIVER(scmi_clock);
+			break;
+		case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+			if (IS_ENABLED(CONFIG_RESET_SCMI))
+				drv = DM_GET_DRIVER(scmi_reset_domain);
+			break;
+		default:
+			break;
+		}
+
+		if (!drv) {
+			dev_dbg(dev, "Ignore unsupported SCMI protocol %#x\n",
+				protocol_id);
+			continue;
+		}
+
+		ret = device_bind_ofnode(dev, drv, ofnode_get_name(node),
+					 NULL, node, NULL);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
+{
+	return (const struct scmi_agent_ops *)dev->driver->ops;
+}
+
+int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg)
+{
+	const struct scmi_agent_ops *ops = transport_dev_ops(dev);
+
+	if (ops->process_msg)
+		return ops->process_msg(dev, msg);
+
+	return -EPROTONOSUPPORT;
+}
+
+UCLASS_DRIVER(scmi_agent) = {
+	.id		= UCLASS_SCMI_AGENT,
+	.name		= "scmi_agent",
+	.post_bind	= scmi_bind_protocols,
+};

diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c
new file mode 100644
index 0000000..85dbf91
--- /dev/null
+++ b/drivers/firmware/scmi/smccc_agent.c

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Linaro Limited.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <dm/devres.h>
+#include <dm/device-internal.h>
+#include <linux/arm-smccc.h>
+#include <linux/compat.h>
+
+#include "smt.h"
+
+#define SMCCC_RET_NOT_SUPPORTED         ((unsigned long)-1)
+
+/**
+ * struct scmi_smccc_channel - Description of an SCMI SMCCC transport
+ * @func_id:	SMCCC function ID used by the SCMI transport
+ * @smt:	Shared memory buffer
+ */
+struct scmi_smccc_channel {
+	ulong func_id;
+	struct scmi_smt smt;
+};
+
+static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg)
+{
+	struct scmi_smccc_channel *chan = dev_get_priv(dev);
+	struct arm_smccc_res res;
+	int ret;
+
+	ret = scmi_write_msg_to_smt(dev, &chan->smt, msg);
+	if (ret)
+		return ret;
+
+	arm_smccc_smc(chan->func_id, 0, 0, 0, 0, 0, 0, 0, &res);
+	if (res.a0 == SMCCC_RET_NOT_SUPPORTED)
+		ret = -ENXIO;
+	else
+		ret = scmi_read_resp_from_smt(dev, &chan->smt, msg);
+
+	scmi_clear_smt_channel(&chan->smt);
+
+	return ret;
+}
+
+static int scmi_smccc_probe(struct udevice *dev)
+{
+	struct scmi_smccc_channel *chan = dev_get_priv(dev);
+	u32 func_id;
+	int ret;
+
+	if (dev_read_u32(dev, "arm,smc-id", &func_id)) {
+		dev_err(dev, "Missing property func-id\n");
+		return -EINVAL;
+	}
+
+	chan->func_id = func_id;
+
+	ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
+	if (ret) {
+		dev_err(dev, "Failed to get smt resources: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id scmi_smccc_ids[] = {
+	{ .compatible = "arm,scmi-smc" },
+	{ }
+};
+
+static const struct scmi_agent_ops scmi_smccc_ops = {
+	.process_msg = scmi_smccc_process_msg,
+};
+
+U_BOOT_DRIVER(scmi_smccc) = {
+	.name		= "scmi-over-smccc",
+	.id		= UCLASS_SCMI_AGENT,
+	.of_match	= scmi_smccc_ids,
+	.priv_auto_alloc_size = sizeof(struct scmi_smccc_channel),
+	.probe		= scmi_smccc_probe,
+	.ops		= &scmi_smccc_ops,
+};

diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
new file mode 100644
index 0000000..ce8fe49
--- /dev/null
+++ b/drivers/firmware/scmi/smt.c

@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2019-2020 Linaro Limited.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <scmi_agent.h>
+#include <asm/cache.h>
+#include <asm/system.h>
+#include <dm/ofnode.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include "smt.h"
+
+/**
+ * Get shared memory configuration defined by the referred DT phandle
+ * Return with a errno compliant value.
+ */
+int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt)
+{
+	int ret;
+	struct ofnode_phandle_args args;
+	struct resource resource;
+	fdt32_t faddr;
+	phys_addr_t paddr;
+
+	ret = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args);
+	if (ret)
+		return ret;
+
+	ret = ofnode_read_resource(args.node, 0, &resource);
+	if (ret)
+		return ret;
+
+	faddr = cpu_to_fdt32(resource.start);
+	paddr = ofnode_translate_address(args.node, &faddr);
+
+	smt->size = resource_size(&resource);
+	if (smt->size < sizeof(struct scmi_smt_header)) {
+		dev_err(dev, "Shared memory buffer too small\n");
+		return -EINVAL;
+	}
+
+	smt->buf = devm_ioremap(dev, paddr, smt->size);
+	if (!smt->buf)
+		return -ENOMEM;
+
+#ifdef CONFIG_ARM
+	if (dcache_status())
+		mmu_set_region_dcache_behaviour((uintptr_t)smt->buf,
+						smt->size, DCACHE_OFF);
+#endif
+
+	return 0;
+}
+
+/**
+ * Write SCMI message @msg into a SMT shared buffer @smt.
+ * Return 0 on success and with a negative errno in case of error.
+ */
+int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt,
+			  struct scmi_msg *msg)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	if ((!msg->in_msg && msg->in_msg_sz) ||
+	    (!msg->out_msg && msg->out_msg_sz))
+		return -EINVAL;
+
+	if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) {
+		dev_dbg(dev, "Channel busy\n");
+		return -EBUSY;
+	}
+
+	if (smt->size < (sizeof(*hdr) + msg->in_msg_sz) ||
+	    smt->size < (sizeof(*hdr) + msg->out_msg_sz)) {
+		dev_dbg(dev, "Buffer too small\n");
+		return -ETOOSMALL;
+	}
+
+	/* Load message in shared memory */
+	hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
+	hdr->length = msg->in_msg_sz + sizeof(hdr->msg_header);
+	hdr->msg_header = SMT_HEADER_TOKEN(0) |
+			  SMT_HEADER_MESSAGE_TYPE(0) |
+			  SMT_HEADER_PROTOCOL_ID(msg->protocol_id) |
+			  SMT_HEADER_MESSAGE_ID(msg->message_id);
+
+	memcpy_toio(hdr->msg_payload, msg->in_msg, msg->in_msg_sz);
+
+	return 0;
+}
+
+/**
+ * Read SCMI message from a SMT shared buffer @smt and copy it into @msg.
+ * Return 0 on success and with a negative errno in case of error.
+ */
+int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt,
+			    struct scmi_msg *msg)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	if (!(hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) {
+		dev_err(dev, "Channel unexpectedly busy\n");
+		return -EBUSY;
+	}
+
+	if (hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR) {
+		dev_err(dev, "Channel error reported, reset channel\n");
+		return -ECOMM;
+	}
+
+	if (hdr->length > msg->out_msg_sz + sizeof(hdr->msg_header)) {
+		dev_err(dev, "Buffer to small\n");
+		return -ETOOSMALL;
+	}
+
+	/* Get the data */
+	msg->out_msg_sz = hdr->length - sizeof(hdr->msg_header);
+	memcpy_fromio(msg->out_msg, hdr->msg_payload, msg->out_msg_sz);
+
+	return 0;
+}
+
+/**
+ * Clear SMT flags in shared buffer to allow further message exchange
+ */
+void scmi_clear_smt_channel(struct scmi_smt *smt)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR;
+}

diff --git a/drivers/firmware/scmi/smt.h b/drivers/firmware/scmi/smt.h
new file mode 100644
index 0000000..a8c0987
--- /dev/null
+++ b/drivers/firmware/scmi/smt.h

@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2019-2020 Linaro Limited.
+ */
+#ifndef SCMI_SMT_H
+#define SCMI_SMT_H
+
+#include <asm/types.h>
+
+/**
+ * struct scmi_smt_header - Description of the shared memory message buffer
+ *
+ * SMT stands for Shared Memory based Transport.
+ * SMT uses 28 byte header prior message payload to handle the state of
+ * the communication channel realized by the shared memory area and
+ * to define SCMI protocol information the payload relates to.
+ */
+struct scmi_smt_header {
+	__le32 reserved;
+	__le32 channel_status;
+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR	BIT(1)
+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE	BIT(0)
+	__le32 reserved1[2];
+	__le32 flags;
+#define SCMI_SHMEM_FLAG_INTR_ENABLED		BIT(0)
+	__le32 length;
+	__le32 msg_header;
+	u8 msg_payload[0];
+};
+
+#define SMT_HEADER_TOKEN(token)		(((token) << 18) & GENMASK(31, 18))
+#define SMT_HEADER_PROTOCOL_ID(proto)	(((proto) << 10) & GENMASK(17, 10))
+#define SMT_HEADER_MESSAGE_TYPE(type)	(((type) << 18) & GENMASK(9, 8))
+#define SMT_HEADER_MESSAGE_ID(id)	((id) & GENMASK(7, 0))
+
+/**
+ * struct scmi_smt - Description of a SMT memory buffer
+ * @buf:	Shared memory base address
+ * @size:	Shared memory byte size
+ */
+struct scmi_smt {
+	u8 *buf;
+	size_t size;
+};
+
+static inline bool scmi_smt_channel_is_free(struct scmi_smt *smt)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	return hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
+}
+
+static inline bool scmi_smt_channel_reports_error(struct scmi_smt *smt)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	return hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR;
+}
+
+static inline void scmi_smt_get_channel(struct scmi_smt *smt)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
+}
+
+static inline void scmi_smt_put_channel(struct scmi_smt *smt)
+{
+	struct scmi_smt_header *hdr = (void *)smt->buf;
+
+	hdr->channel_status |= SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
+	hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR;
+}
+
+int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt);
+
+int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt,
+			  struct scmi_msg *msg);
+
+int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt,
+			    struct scmi_msg *msg);
+
+void scmi_clear_smt_channel(struct scmi_smt *smt);
+
+#endif /* SCMI_SMT_H */

diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index e311f55..a2beb00 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c

@@ -619,7 +619,7 @@
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
-		dev_err(dev, "Mbox send fail %d\n", ret);
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
 		return ret;
 	}
 
@@ -1591,7 +1591,7 @@
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
-		dev_err(dev, "Mbox send fail %d\n", ret);
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
 		return ret;
 	}
 
@@ -1639,7 +1639,7 @@
 				     (u32 *)&req, sizeof(req), sizeof(*resp));
 	if (IS_ERR(xfer)) {
 		ret = PTR_ERR(xfer);
-		dev_err(dev, "Message alloc failed(%d)\n", ret);
+		dev_err(info->dev, "Message alloc failed(%d)\n", ret);
 		return ret;
 	}
 
@@ -1649,7 +1649,7 @@
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
-		dev_err(dev, "Mbox send fail %d\n", ret);
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
 		goto fail;
 	}
 
@@ -1745,7 +1745,7 @@
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
-		dev_err(dev, "Mbox send fail %d\n", ret);
+		dev_err(info->dev, "Mbox send fail %d\n", ret);
 		return ret;
 	}
 
@@ -2229,6 +2229,14 @@
 					    u8 proc_id)
 {
 	int ret;
+	struct ti_sci_info *info;
+
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+	if (!handle)
+		return -EINVAL;
+
+	info = handle_to_ti_sci_info(handle);
 
 	/*
 	 * Send the core boot status wait message waiting for either WFE or
@@ -2554,7 +2562,8 @@
 				     (u32 *)&req, sizeof(req), sizeof(*resp));
 	if (IS_ERR(xfer)) {
 		ret = PTR_ERR(xfer);
-		dev_err(dev, "RX_FL_CFG: Message alloc failed(%d)\n", ret);
+		dev_err(info->dev, "RX_FL_CFG: Message alloc failed(%d)\n",
+			ret);
 		return ret;
 	}
 
@@ -2583,7 +2592,7 @@
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
-		dev_err(dev, "RX_FL_CFG: Mbox send fail %d\n", ret);
+		dev_err(info->dev, "RX_FL_CFG: Mbox send fail %d\n", ret);
 		goto fail;
 	}
 

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 5b103cf..8ce140a 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c

@@ -231,11 +231,11 @@
 	buf_hi = upper_32_bits(bin_buf);
 
 	if (xilfpga_old)
-		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 					buf_hi, (u32)(uintptr_t)bsizeptr,
 					bstype, ret_payload);
 	else
-		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 					buf_hi, (u32)bsize, 0, ret_payload);
 
 	if (ret)
@@ -277,7 +277,7 @@
 	buf_lo = lower_32_bits((ulong)buf);
 	buf_hi = upper_32_bits((ulong)buf);
 
-	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+	ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
 				buf_hi,
 			 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 			 flag, ret_payload);
@@ -295,7 +295,7 @@
 	int ret;
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+	ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
 				0, ret_payload);
 	if (!ret)
 		printf("PCAP status\t0x%x\n", ret_payload[1]);
@@ -305,7 +305,7 @@
 
 struct xilinx_fpga_op zynqmp_op = {
 	.load = zynqmp_load,
-#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
 	.loads = zynqmp_loads,
 #endif
 	.info = zynqmp_pcap_info,

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 9c53299..0c01413 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c

@@ -6,6 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <log.h>
+#include <dm/devres.h>
+#include <dm/device_compat.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/uclass-internal.h>
@@ -1209,6 +1211,75 @@
 				 flags, 0, dev);
 }
 
+static void devm_gpiod_release(struct udevice *dev, void *res)
+{
+	dm_gpio_free(dev, res);
+}
+
+static int devm_gpiod_match(struct udevice *dev, void *res, void *data)
+{
+	return res == data;
+}
+
+struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id,
+				       unsigned int index, int flags)
+{
+	int rc;
+	struct gpio_desc *desc;
+	char *propname;
+	static const char suffix[] = "-gpios";
+
+	propname = malloc(strlen(id) + sizeof(suffix));
+	if (!propname) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	strcpy(propname, id);
+	strcat(propname, suffix);
+
+	desc = devres_alloc(devm_gpiod_release, sizeof(struct gpio_desc),
+			    __GFP_ZERO);
+	if (unlikely(!desc)) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = gpio_request_by_name(dev, propname, index, desc, flags);
+
+end:
+	if (propname)
+		free(propname);
+
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, desc);
+
+	return desc;
+}
+
+struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev,
+						const char *id,
+						unsigned int index,
+						int flags)
+{
+	struct gpio_desc *desc = devm_gpiod_get_index(dev, id, index, flags);
+
+	if (IS_ERR(desc))
+		return NULL;
+
+	return desc;
+}
+
+void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc)
+{
+	int rc;
+
+	rc = devres_release(dev, devm_gpiod_release, devm_gpiod_match, desc);
+	WARN_ON(rc);
+}
+
 static int gpio_post_bind(struct udevice *dev)
 {
 	struct udevice *child;

diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 5bff27f..473e364 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c

@@ -273,9 +273,12 @@
 static int gpio_stm32_probe(struct udevice *dev)
 {
 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct ofnode_phandle_args args;
+	const char *name;
 	struct clk clk;
 	fdt_addr_t addr;
-	int ret;
+	int ret, i;
 
 	addr = dev_read_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
@@ -283,11 +286,6 @@
 
 	priv->regs = (struct stm32_gpio_regs *)addr;
 
-	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-	struct ofnode_phandle_args args;
-	const char *name;
-	int i;
-
 	name = dev_read_string(dev, "st,bank-name");
 	if (!name)
 		return -EINVAL;
@@ -297,6 +295,9 @@
 	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
 					 NULL, 3, i, &args);
 
+	if (!ret && args.args_count < 3)
+		return -EINVAL;
+
 	if (ret == -ENOENT) {
 		uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
 		priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
@@ -310,6 +311,8 @@
 
 		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
 						 ++i, &args);
+		if (!ret && args.args_count < 3)
+			return -EINVAL;
 	}
 
 	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f7b2786..bd248cb 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile

@@ -3,6 +3,9 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 obj-$(CONFIG_DM_I2C) += i2c-uclass.o
+ifdef CONFIG_ACPIGEN
+obj-$(CONFIG_DM_I2C) += acpi_i2c.o
+endif
 obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
 obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o

diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c
new file mode 100644
index 0000000..57d2968
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.c

@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_dp.h>
+#ifdef CONFIG_X86
+#include <asm/intel_pinctrl_defs.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm/acpi.h>
+
+static bool acpi_i2c_add_gpios_to_crs(struct acpi_i2c_priv *priv)
+{
+	/*
+	 * Return false if:
+	 * 1. Request to explicitly disable export of GPIOs in CRS, or
+	 * 2. Both reset and enable GPIOs are not provided.
+	 */
+	if (priv->disable_gpio_export_in_crs ||
+	    (!dm_gpio_is_valid(&priv->reset_gpio) &&
+	     !dm_gpio_is_valid(&priv->enable_gpio)))
+		return false;
+
+	return true;
+}
+
+static int acpi_i2c_write_gpio(struct acpi_ctx *ctx, struct gpio_desc *gpio,
+			       int *curindex)
+{
+	int ret;
+
+	if (!dm_gpio_is_valid(gpio))
+		return -ENOENT;
+
+	acpi_device_write_gpio_desc(ctx, gpio);
+	ret = *curindex;
+	(*curindex)++;
+
+	return ret;
+}
+
+int acpi_i2c_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+	int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
+	enum i2c_device_t type = dev_get_driver_data(dev);
+	struct acpi_i2c_priv *priv = dev_get_priv(dev);
+	struct acpi_dp *dsd = NULL;
+	char scope[ACPI_PATH_MAX];
+	char name[ACPI_NAME_MAX];
+	int tx_state_val;
+	int curindex = 0;
+	int ret;
+
+#ifdef CONFIG_X86
+	tx_state_val = PAD_CFG0_TX_STATE;
+#elif defined(CONFIG_SANDBOX)
+	tx_state_val = BIT(7);  /* test value */
+#else
+#error "Not supported on this architecture"
+#endif
+	ret = acpi_get_name(dev, name);
+	if (ret)
+		return log_msg_ret("name", ret);
+	ret = acpi_device_scope(dev, scope, sizeof(scope));
+	if (ret)
+		return log_msg_ret("scope", ret);
+
+	/* Device */
+	acpigen_write_scope(ctx, scope);
+	acpigen_write_device(ctx, name);
+	acpigen_write_name_string(ctx, "_HID", priv->hid);
+	if (type == I2C_DEVICE_HID_OVER_I2C)
+		acpigen_write_name_string(ctx, "_CID", "PNP0C50");
+	acpigen_write_name_integer(ctx, "_UID", priv->uid);
+	acpigen_write_name_string(ctx, "_DDN", priv->desc);
+	acpigen_write_sta(ctx, acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name(ctx, "_CRS");
+	acpigen_write_resourcetemplate_header(ctx);
+	acpi_device_write_i2c_dev(ctx, dev);
+
+	/* Use either Interrupt() or GpioInt() */
+	if (dm_gpio_is_valid(&priv->irq_gpio)) {
+		irq_gpio_index = acpi_i2c_write_gpio(ctx, &priv->irq_gpio,
+						     &curindex);
+	} else {
+		ret = acpi_device_write_interrupt_irq(ctx, &priv->irq);
+		if (ret < 0)
+			return log_msg_ret("irq", ret);
+	}
+
+	if (acpi_i2c_add_gpios_to_crs(priv)) {
+		reset_gpio_index = acpi_i2c_write_gpio(ctx, &priv->reset_gpio,
+						       &curindex);
+		enable_gpio_index = acpi_i2c_write_gpio(ctx, &priv->enable_gpio,
+							&curindex);
+	}
+	acpigen_write_resourcetemplate_footer(ctx);
+
+	/* Wake capabilities */
+	if (priv->wake) {
+		acpigen_write_name_integer(ctx, "_S0W", 4);
+		acpigen_write_prw(ctx, priv->wake, 3);
+	}
+
+	/* DSD */
+	if (priv->probed || priv->property_count || priv->compat_string ||
+	    reset_gpio_index >= 0 || enable_gpio_index >= 0 ||
+	    irq_gpio_index >= 0) {
+		char path[ACPI_PATH_MAX];
+
+		ret = acpi_device_path(dev, path, sizeof(path));
+		if (ret)
+			return log_msg_ret("path", ret);
+
+		dsd = acpi_dp_new_table("_DSD");
+		if (priv->compat_string)
+			acpi_dp_add_string(dsd, "compatible",
+					   priv->compat_string);
+		if (priv->probed)
+			acpi_dp_add_integer(dsd, "linux,probed", 1);
+		if (irq_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "irq-gpios", path,
+					 irq_gpio_index, 0,
+					 priv->irq_gpio.flags &
+					 GPIOD_ACTIVE_LOW ?
+					 ACPI_GPIO_ACTIVE_LOW : 0);
+		if (reset_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "reset-gpios", path,
+					 reset_gpio_index, 0,
+					 priv->reset_gpio.flags &
+					 GPIOD_ACTIVE_LOW ?
+					 ACPI_GPIO_ACTIVE_LOW : 0);
+		if (enable_gpio_index >= 0)
+			acpi_dp_add_gpio(dsd, "enable-gpios", path,
+					 enable_gpio_index, 0,
+					 priv->enable_gpio.flags &
+					 GPIOD_ACTIVE_LOW ?
+					 ACPI_GPIO_ACTIVE_LOW : 0);
+		/* Generic property list is not supported */
+		acpi_dp_write(ctx, dsd);
+	}
+
+	/* Power Resource */
+	if (priv->has_power_resource) {
+		ret = acpi_device_add_power_res(ctx, tx_state_val,
+			"\\_SB.GPC0", "\\_SB.SPC0",
+			&priv->reset_gpio, priv->reset_delay_ms,
+			priv->reset_off_delay_ms, &priv->enable_gpio,
+			priv->enable_delay_ms, priv->enable_off_delay_ms,
+			&priv->stop_gpio, priv->stop_delay_ms,
+			priv->stop_off_delay_ms);
+		if (ret)
+			return log_msg_ret("power", ret);
+	}
+	if (priv->hid_desc_reg_offset) {
+		ret = acpi_device_write_dsm_i2c_hid(ctx,
+						    priv->hid_desc_reg_offset);
+		if (ret)
+			return log_msg_ret("dsm", ret);
+	}
+
+	acpigen_pop_len(ctx); /* Device */
+	acpigen_pop_len(ctx); /* Scope */
+
+	return 0;
+}
+
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+	struct acpi_i2c_priv *priv = dev_get_priv(dev);
+
+	gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+			     GPIOD_IS_OUT);
+	gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable_gpio,
+			     GPIOD_IS_OUT);
+	gpio_request_by_name(dev, "irq-gpios", 0, &priv->irq_gpio, GPIOD_IS_IN);
+	gpio_request_by_name(dev, "stop-gpios", 0, &priv->stop_gpio,
+			     GPIOD_IS_OUT);
+	irq_get_by_index(dev, 0, &priv->irq);
+	priv->hid = dev_read_string(dev, "acpi,hid");
+	if (!priv->hid)
+		return log_msg_ret("hid", -EINVAL);
+	dev_read_u32(dev, "acpi,uid", &priv->uid);
+	priv->desc = dev_read_string(dev, "acpi,ddn");
+	dev_read_u32(dev, "acpi,wake", &priv->wake);
+	priv->probed = dev_read_bool(dev, "linux,probed");
+	priv->compat_string = dev_read_string(dev, "acpi,compatible");
+	priv->has_power_resource = dev_read_bool(dev,
+						 "acpi,has-power-resource");
+	dev_read_u32(dev, "hid-descr-addr", &priv->hid_desc_reg_offset);
+	dev_read_u32(dev, "reset-delay-ms", &priv->reset_delay_ms);
+	dev_read_u32(dev, "reset-off-delay-ms", &priv->reset_off_delay_ms);
+	dev_read_u32(dev, "enable-delay-ms", &priv->enable_delay_ms);
+	dev_read_u32(dev, "enable-off-delay-ms", &priv->enable_off_delay_ms);
+	dev_read_u32(dev, "stop-delay-ms", &priv->stop_delay_ms);
+	dev_read_u32(dev, "stop-off-delay-ms", &priv->stop_off_delay_ms);
+
+	return 0;
+}
+
+/* Use name specified in priv or build one from I2C address */
+static int acpi_i2c_get_name(const struct udevice *dev, char *out_name)
+{
+	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+	struct acpi_i2c_priv *priv = dev_get_priv(dev);
+
+	snprintf(out_name, ACPI_NAME_MAX,
+		 priv->hid_desc_reg_offset ? "H%03X" : "D%03X",
+		 chip->chip_addr);
+
+	return 0;
+}
+
+struct acpi_ops acpi_i2c_ops = {
+	.fill_ssdt	= acpi_i2c_fill_ssdt,
+	.get_name	= acpi_i2c_get_name,
+};

diff --git a/drivers/i2c/acpi_i2c.h b/drivers/i2c/acpi_i2c.h
new file mode 100644
index 0000000..1f4be29
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ACPI_I2C_H
+#define __ACPI_I2C_H
+
+#include <dm/acpi.h>
+
+extern struct acpi_ops acpi_i2c_ops;
+
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+
+#endif

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 024c63c..7144d39 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c

@@ -500,7 +500,7 @@
 };
 
 U_BOOT_DRIVER(cdns_i2c) = {
-	.name = "i2c-cdns",
+	.name = "i2c_cdns",
 	.id = UCLASS_I2C,
 	.of_match = cdns_i2c_of_match,
 	.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 2373aa2..5c4626b 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c

@@ -9,6 +9,8 @@
 #include <i2c.h>
 #include <log.h>
 #include <malloc.h>
+#include <acpi/acpi_device.h>
+#include <dm/acpi.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
@@ -16,6 +18,7 @@
 #include <asm/gpio.h>
 #endif
 #include <linux/delay.h>
+#include "acpi_i2c.h"
 
 #define I2C_MAX_OFFSET_LEN	4
 
@@ -749,7 +752,21 @@
 	.name		= "i2c_generic",
 };
 
+static const struct udevice_id generic_chip_i2c_ids[] = {
+	{ .compatible = "i2c-chip", .data = I2C_DEVICE_GENERIC },
+#if CONFIG_IS_ENABLED(ACPIGEN)
+	{ .compatible = "hid-over-i2c", .data = I2C_DEVICE_HID_OVER_I2C },
+#endif
+	{ }
+};
+
 U_BOOT_DRIVER(i2c_generic_chip_drv) = {
 	.name		= "i2c_generic_chip_drv",
 	.id		= UCLASS_I2C_GENERIC,
+	.of_match	= generic_chip_i2c_ids,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+	.ofdata_to_platdata	= acpi_i2c_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct acpi_i2c_priv),
+#endif
+	ACPI_OPS_PTR(&acpi_i2c_ops)
 };

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index e3d980a..7609594 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c

@@ -941,7 +941,8 @@
 	 */
 	ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
 	if (ret < 0) {
-		debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
+		debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
+		      bus->seq, i2c_bus->base);
 	} else {
 		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
 				"scl-gpios", 0, &i2c_bus->scl_gpio,
@@ -952,7 +953,9 @@
 		if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
 		    !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
 		    ret || ret2) {
-			dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
+			dev_err(bus,
+				"i2c bus %d at %lu, fail to request scl/sda gpio\n",
+				bus->seq, i2c_bus->base);
 			return -EINVAL;
 		}
 	}

diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index 3f9afae..27ccc6e 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c

@@ -212,14 +212,16 @@
 
 	ret = k3_sec_proxy_verify_thread(spt, THREAD_IS_TX);
 	if (ret) {
-		dev_err(dev, "%s: Thread%d verification failed. ret = %d\n",
+		dev_err(chan->dev,
+			"%s: Thread%d verification failed. ret = %d\n",
 			__func__, spt->id, ret);
 		return ret;
 	}
 
 	/* Check the message size. */
 	if (msg->len > spm->desc->max_msg_size) {
-		printf("%s: Thread %ld message length %zu > max msg size %d\n",
+		dev_err(chan->dev,
+			"%s: Thread %ld message length %zu > max msg size %d\n",
 		       __func__, chan->id, msg->len, spm->desc->max_msg_size);
 		return -EINVAL;
 	}

diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
index b8bf356..81a4115 100644
--- a/drivers/mailbox/stm32-ipcc.c
+++ b/drivers/mailbox/stm32-ipcc.c

@@ -101,9 +101,8 @@
 {
 	struct stm32_ipcc *ipcc = dev_get_priv(dev);
 	fdt_addr_t addr;
-	const fdt32_t *cell;
 	struct clk clk;
-	int len, ret;
+	int ret;
 
 	debug("%s(dev=%p)\n", __func__, dev);
 
@@ -114,14 +113,12 @@
 	ipcc->reg_base = (void __iomem *)addr;
 
 	/* proc_id */
-	cell = dev_read_prop(dev, "st,proc_id", &len);
-	if (len < sizeof(fdt32_t)) {
+	ret = dev_read_u32_index(dev, "st,proc_id", 1, &ipcc->proc_id);
+	if (ret) {
 		dev_dbg(dev, "Missing st,proc_id\n");
 		return -EINVAL;
 	}
 
-	ipcc->proc_id = fdtdec_get_number(cell, 1);
-
 	if (ipcc->proc_id >= STM32_MAX_PROCS) {
 		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
 		return -EINVAL;

diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 746377e..9483ed9 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c

@@ -133,7 +133,7 @@
 };
 
 U_BOOT_DRIVER(zynqmp_ipi) = {
-	.name = "zynqmp-ipi",
+	.name = "zynqmp_ipi",
 	.id = UCLASS_MAILBOX,
 	.of_match = zynqmp_ipi_ids,
 	.probe = zynqmp_ipi_probe,

diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c
index b793028..ea8b385 100644
--- a/drivers/mmc/bcm2835_sdhost.c
+++ b/drivers/mmc/bcm2835_sdhost.c

@@ -185,22 +185,22 @@
 
 static void bcm2835_dumpregs(struct bcm2835_host *host)
 {
-	dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
-	dev_dbg(dev, "SDCMD  0x%08x\n", readl(host->ioaddr + SDCMD));
-	dev_dbg(dev, "SDARG  0x%08x\n", readl(host->ioaddr + SDARG));
-	dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
-	dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
-	dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
-	dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
-	dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
-	dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
-	dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
-	dev_dbg(dev, "SDVDD  0x%08x\n", readl(host->ioaddr + SDVDD));
-	dev_dbg(dev, "SDEDM  0x%08x\n", readl(host->ioaddr + SDEDM));
-	dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
-	dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
-	dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
-	dev_dbg(dev, "===========================================\n");
+	dev_dbg(host->dev, "=========== REGISTER DUMP ===========\n");
+	dev_dbg(host->dev, "SDCMD  0x%08x\n", readl(host->ioaddr + SDCMD));
+	dev_dbg(host->dev, "SDARG  0x%08x\n", readl(host->ioaddr + SDARG));
+	dev_dbg(host->dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
+	dev_dbg(host->dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
+	dev_dbg(host->dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
+	dev_dbg(host->dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
+	dev_dbg(host->dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
+	dev_dbg(host->dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
+	dev_dbg(host->dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
+	dev_dbg(host->dev, "SDVDD  0x%08x\n", readl(host->ioaddr + SDVDD));
+	dev_dbg(host->dev, "SDEDM  0x%08x\n", readl(host->ioaddr + SDEDM));
+	dev_dbg(host->dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
+	dev_dbg(host->dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
+	dev_dbg(host->dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
+	dev_dbg(host->dev, "===========================================\n");
 }
 
 static void bcm2835_reset_internal(struct bcm2835_host *host)
@@ -738,7 +738,7 @@
 	cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
 	cfg->b_max = 65535;
 
-	dev_dbg(dev, "f_max %d, f_min %d\n",
+	dev_dbg(host->dev, "f_max %d, f_min %d\n",
 		cfg->f_max, cfg->f_min);
 
 	/* host controller capabilities */

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index bd1fb09..30fe7a0 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c

@@ -774,7 +774,8 @@
 	writel(val, &host->base->sdc_cfg);
 }
 
-static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
+static void msdc_set_mclk(struct udevice *dev,
+			  struct msdc_host *host, enum bus_mode timing, u32 hz)
 {
 	u32 mode;
 	u32 div;
@@ -897,7 +898,7 @@
 		clock = mmc->cfg->f_min;
 
 	if (host->mclk != clock || host->timing != mmc->selected_mode)
-		msdc_set_mclk(host, mmc->selected_mode, clock);
+		msdc_set_mclk(dev, host, mmc->selected_mode, clock);
 
 	return 0;
 }
@@ -957,7 +958,8 @@
 	return PAD_DELAY_MAX - start_bit;
 }
 
-static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
+static struct msdc_delay_phase get_best_delay(struct udevice *dev,
+					      struct msdc_host *host, u32 delay)
 {
 	int start = 0, len = 0;
 	int start_final = 0, len_final = 0;
@@ -1067,7 +1069,7 @@
 		}
 	}
 
-	final_cmd_delay = get_best_delay(host, cmd_delay);
+	final_cmd_delay = get_best_delay(dev, host, cmd_delay);
 	clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
 			final_cmd_delay.final_phase <<
 			PAD_CMD_TUNE_RX_DLY3_S);
@@ -1117,7 +1119,7 @@
 		}
 	}
 
-	final_rise_delay = get_best_delay(host, rise_delay);
+	final_rise_delay = get_best_delay(dev, host, rise_delay);
 	/* if rising edge has enough margin, do not scan falling edge */
 	if (final_rise_delay.maxlen >= 12 ||
 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
@@ -1139,7 +1141,7 @@
 		}
 	}
 
-	final_fall_delay = get_best_delay(host, fall_delay);
+	final_fall_delay = get_best_delay(dev, host, fall_delay);
 
 skip_fall:
 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
@@ -1171,7 +1173,7 @@
 
 	dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
 
-	internal_delay_phase = get_best_delay(host, internal_delay);
+	internal_delay_phase = get_best_delay(dev, host, internal_delay);
 	clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
 			internal_delay_phase.final_phase <<
 			MSDC_PAD_TUNE_CMDRRDLY_S);
@@ -1214,7 +1216,7 @@
 		}
 	}
 
-	final_rise_delay = get_best_delay(host, rise_delay);
+	final_rise_delay = get_best_delay(dev, host, rise_delay);
 	if (final_rise_delay.maxlen >= 12 ||
 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
 		goto skip_fall;
@@ -1237,7 +1239,7 @@
 		}
 	}
 
-	final_fall_delay = get_best_delay(host, fall_delay);
+	final_fall_delay = get_best_delay(dev, host, fall_delay);
 
 skip_fall:
 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
@@ -1293,7 +1295,7 @@
 			rise_delay |= (1 << i);
 	}
 
-	final_rise_delay = get_best_delay(host, rise_delay);
+	final_rise_delay = get_best_delay(dev, host, rise_delay);
 	if (final_rise_delay.maxlen >= 12 ||
 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
 		goto skip_fall;
@@ -1309,7 +1311,7 @@
 			fall_delay |= (1 << i);
 	}
 
-	final_fall_delay = get_best_delay(host, fall_delay);
+	final_fall_delay = get_best_delay(dev, host, fall_delay);
 
 skip_fall:
 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e9381b9..775c17b 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c

@@ -191,7 +191,7 @@
 
 #if defined(CONFIG_ARCH_ZYNQMP)
 const struct sdhci_ops arasan_ops = {
-	.platform_execute_tuning	= &arasan_sdhci_execute_tuning,
+	.platform_execute_tuning = &arasan_sdhci_execute_tuning,
 	.set_delay = &arasan_sdhci_set_tapdelay,
 	.set_control_reg = &arasan_sdhci_set_control_reg,
 };

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 06b2ff9..df4cbd5 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig

@@ -233,7 +233,7 @@
 config NAND_ARASAN
 	bool "Configure Arasan Nand"
 	select SYS_NAND_SELF_INIT
-	select DM_MTD
+	depends on DM_MTD
 	imply CMD_NAND
 	help
 	  This enables Nand driver support for Arasan nand flash

diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 6c1d640..0615e50 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c

@@ -1306,7 +1306,7 @@
 };
 
 U_BOOT_DRIVER(arasan_nand) = {
-	.name = "arasan-nand",
+	.name = "arasan_nand",
 	.id = UCLASS_MTD,
 	.of_match = arasan_nand_dt_ids,
 	.probe = arasan_probe,

diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 5e95901..abc432c 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c

@@ -424,7 +424,8 @@
 	}
 
 	if (!timeout) {
-		dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
+		dev_err(mtd->dev,
+			"Timeout to calculate PMECC error location\n");
 		return -1;
 	}
 
@@ -464,7 +465,8 @@
 			*(buf + byte_pos) ^= (1 << bit_pos);
 
 			pos = sector_num * host->pmecc_sector_size + byte_pos;
-			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(mtd->dev,
+				"Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, *(buf + byte_pos));
 		} else {
 			/* Bit flip in OOB area */
@@ -474,7 +476,8 @@
 			ecc[tmp] ^= (1 << bit_pos);
 
 			pos = tmp + nand_chip->ecc.layout->eccpos[0];
-			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(mtd->dev,
+				"Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, ecc[tmp]);
 		}
 
@@ -516,7 +519,7 @@
 
 			err_nbr = pmecc_err_location(mtd);
 			if (err_nbr == -1) {
-				dev_err(host->dev, "PMECC: Too many errors\n");
+				dev_err(mtd->dev, "PMECC: Too many errors\n");
 				mtd->ecc_stats.failed++;
 				return -EBADMSG;
 			} else {
@@ -560,7 +563,7 @@
 	}
 
 	if (!timeout) {
-		dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
+		dev_err(mtd->dev, "Timeout to read PMECC page\n");
 		return -1;
 	}
 
@@ -600,7 +603,8 @@
 	}
 
 	if (!timeout) {
-		dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
+		dev_err(mtd->dev,
+			"Timeout to read PMECC status, fail to write PMECC in oob\n");
 		goto out;
 	}
 
@@ -713,7 +717,8 @@
 
 	if (*cap == 0 && *sector_size == 0) {
 		/* Non-ONFI compliant */
-		dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
+		dev_info(chip->mtd.dev,
+			 "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 		*cap = 2;
 		*sector_size = 512;
 	}
@@ -835,17 +840,20 @@
 	 * from ONFI.
 	 */
 	if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
-		dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
+		dev_err(mtd->dev,
+			"Required ECC %d bits in %d bytes not supported!\n",
 			cap, sector_size);
 		return -EINVAL;
 	}
 
 	if (cap > host->pmecc_corr_cap)
-		dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
-				host->pmecc_corr_cap, cap);
+		dev_info(mtd->dev,
+			 "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
+			 host->pmecc_corr_cap, cap);
 	if (sector_size < host->pmecc_sector_size)
-		dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
-				host->pmecc_sector_size, sector_size);
+		dev_info(mtd->dev,
+			 "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
+			 host->pmecc_sector_size, sector_size);
 #else	/* CONFIG_SYS_NAND_ONFI_DETECTION */
 	host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 	host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
@@ -877,7 +885,7 @@
 #if defined(NO_GALOIS_TABLE_IN_ROM)
 	pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 	if (!pmecc_galois_table) {
-		dev_err(host->dev, "out of memory\n");
+		dev_err(mtd->dev, "out of memory\n");
 		return -ENOMEM;
 	}
 
@@ -909,13 +917,14 @@
 				       host->pmecc_sector_number;
 
 		if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
-			dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
-					MTD_MAX_ECCPOS_ENTRIES_LARGE);
+			dev_err(mtd->dev,
+				"too large eccpos entries. max support ecc.bytes is %d\n",
+				MTD_MAX_ECCPOS_ENTRIES_LARGE);
 			return -EINVAL;
 		}
 
 		if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
-			dev_err(host->dev, "No room for ECC bytes\n");
+			dev_err(mtd->dev, "No room for ECC bytes\n");
 			return -EINVAL;
 		}
 		pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
@@ -926,7 +935,8 @@
 	case 512:
 	case 1024:
 		/* TODO */
-		dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
+		dev_err(mtd->dev,
+			"Unsupported page size for PMECC, use Software ECC\n");
 	default:
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
@@ -940,7 +950,8 @@
 
 	/* Allocate data for PMECC computation */
 	if (pmecc_data_alloc(host)) {
-		dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
+		dev_err(mtd->dev,
+			"Cannot allocate memory for PMECC computation!\n");
 		return -ENOMEM;
 	}
 
@@ -951,7 +962,7 @@
 
 	/* Check the PMECC ip version */
 	host->pmecc_version = pmecc_readl(host->pmerrloc, version);
-	dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
+	dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 
 	atmel_pmecc_core_init(mtd);
 
@@ -1114,8 +1125,8 @@
 		/* it doesn't seems to be a freshly
 		 * erased block.
 		 * We can't correct so many errors */
-		dev_warn(host->dev, "atmel_nand : multiple errors detected."
-				" Unable to correct.\n");
+		dev_warn(mtd->dev,
+			 "multiple errors detected. Unable to correct.\n");
 		return -EBADMSG;
 	}
 
@@ -1124,15 +1135,14 @@
 		/* there's nothing much to do here.
 		 * the bit error is on the ECC itself.
 		 */
-		dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
-				" Nothing to correct\n");
+		dev_warn(mtd->dev,
+			 "one bit error on ECC code. Nothing to correct\n");
 		return 0;
 	}
 
-	dev_warn(host->dev, "atmel_nand : one bit error on data."
-			" (word offset in the page :"
-			" 0x%x bit offset : 0x%x)\n",
-			ecc_word, ecc_bit);
+	dev_warn(mtd->dev,
+		 "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
+		 ecc_word, ecc_bit);
 	/* correct the error */
 	if (nand_chip->options & NAND_BUSWIDTH_16) {
 		/* 16 bits words */
@@ -1141,7 +1151,7 @@
 		/* 8 bits words */
 		dat[ecc_word] ^= (1 << ecc_bit);
 	}
-	dev_warn(host->dev, "atmel_nand : error corrected\n");
+	dev_warn(mtd->dev, "error corrected\n");
 	return 1;
 }
 
@@ -1511,7 +1521,6 @@
 	int i;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 		if (atmel_nand_chip_init(i, base_addr[i]))
-			dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
-				i);
+			log_err("atmel_nand: Fail to initialize #%d chip", i);
 }
 #endif /* CONFIG_SPL_BUILD */

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 48c0ca6..7349a9b 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c

@@ -956,7 +956,7 @@
 	 */
 	req = DIV_ROUND_UP(ecc_level * 14, 8);
 	if (req >= sas) {
-		dev_err(&host->pdev->dev,
+		dev_err(host->pdev,
 			"error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
 			req, sas);
 		return NULL;
@@ -1012,8 +1012,8 @@
 
 	layout = brcmnand_create_layout(ecc_level, host);
 	if (!layout) {
-		dev_err(&host->pdev->dev,
-				"no proper ecc_layout for this NAND cfg\n");
+		dev_err(host->pdev,
+			"no proper ecc_layout for this NAND cfg\n");
 		return NULL;
 	}
 
@@ -1056,17 +1056,9 @@
 					       NAND_CTRL_RDY |
 					       NAND_STATUS_READY |
 					       (wp ? 0 : NAND_STATUS_WP), 0);
-#ifndef __UBOOT__
-		if (ret)
-			dev_err_ratelimited(&host->pdev->dev,
-					    "nand #WP expected %s\n",
-					    wp ? "on" : "off");
-#else
 		if (ret)
-			dev_err(&host->pdev->dev,
-					    "nand #WP expected %s\n",
-					    wp ? "on" : "off");
-#endif /* __UBOOT__ */
+			dev_err(host->pdev, "nand #WP expected %s\n",
+				wp ? "on" : "off");
 	}
 }
 
@@ -2257,7 +2249,7 @@
 	ret = ofnode_read_s32(dn, "reg", &host->cs);
 #endif
 	if (ret) {
-		dev_err(&pdev->dev, "can't get chip-select\n");
+		dev_err(pdev, "can't get chip-select\n");
 		return -ENXIO;
 	}
 

diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
index a30e821..5fb3081 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c

@@ -512,7 +512,7 @@
 		}
 
 		if (i == ntypes) {
-			dev_err(&info->pdev->dev, "Error: timings not found\n");
+			dev_err(mtd->dev, "Error: timings not found\n");
 			return -EINVAL;
 		}
 
@@ -603,7 +603,7 @@
 			ts = get_timer(0);
 			while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
 				if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
-					dev_err(&info->pdev->dev,
+					dev_err(info->controller.active->mtd.dev,
 						"Timeout on RDDREQ while draining the FIFO\n");
 					return;
 				}
@@ -656,8 +656,8 @@
 				   DIV_ROUND_UP(info->step_spare_size, 4));
 		break;
 	default:
-		dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
-				info->state);
+		dev_err(info->controller.active->mtd.dev,
+			"%s: invalid state %d\n", __func__, info->state);
 		BUG();
 	}
 
@@ -1027,7 +1027,7 @@
 
 	default:
 		exec_cmd = 0;
-		dev_err(&info->pdev->dev, "non-supported command %x\n",
+		dev_err(mtd->dev, "non-supported command %x\n",
 			command);
 		break;
 	}
@@ -1087,7 +1087,7 @@
 				break;
 
 			if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
-				dev_err(&info->pdev->dev, "Wait timeout!!!\n");
+				dev_err(mtd->dev, "Wait timeout!!!\n");
 				return;
 			}
 		}
@@ -1180,7 +1180,7 @@
 				break;
 
 			if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
-				dev_err(&info->pdev->dev, "Wait timeout!!!\n");
+				dev_err(mtd->dev, "Wait timeout!!!\n");
 				return;
 			}
 		}
@@ -1426,7 +1426,7 @@
 				break;
 
 			if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
-				dev_err(&info->pdev->dev, "Ready timeout!!!\n");
+				dev_err(mtd->dev, "Ready timeout!!!\n");
 				return NAND_STATUS_FAIL;
 			}
 		}
@@ -1633,7 +1633,7 @@
 		ecc->strength = 16;
 
 	} else {
-		dev_err(&info->pdev->dev,
+		dev_err(info->controller.active->mtd.dev,
 			"ECC strength %d at page size %d is not supported\n",
 			strength, page_size);
 		return -ENODEV;
@@ -1659,8 +1659,7 @@
 			return ret;
 		ret = pxa3xx_nand_sensing(host);
 		if (ret) {
-			dev_info(&info->pdev->dev,
-				 "There is no chip on cs %d!\n",
+			dev_info(mtd->dev, "There is no chip on cs %d!\n",
 				 info->cs);
 			return ret;
 		}
@@ -1676,7 +1675,7 @@
 	if (!pdata->keep_config) {
 		ret = pxa3xx_nand_init_timings(host);
 		if (ret) {
-			dev_err(&info->pdev->dev,
+			dev_err(mtd->dev,
 				"Failed to set timings: %d\n", ret);
 			return ret;
 		}
@@ -1720,7 +1719,7 @@
 		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
 			chip->cmdfunc = nand_cmdfunc_extended;
 		} else {
-			dev_err(&info->pdev->dev,
+			dev_err(mtd->dev,
 				"unsupported page size on this variant\n");
 			return -ENODEV;
 		}
@@ -1873,6 +1872,7 @@
 
 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
 {
+	struct mtd_info *mtd = &info->controller.active->mtd;
 	struct pxa3xx_nand_platform_data *pdata;
 	int ret, cs, probe_success;
 
@@ -1884,7 +1884,7 @@
 
 	ret = alloc_nand_resource(info);
 	if (ret) {
-		dev_err(&pdev->dev, "alloc nand resource failed\n");
+		dev_err(mtd->dev, "alloc nand resource failed\n");
 		return ret;
 	}
 
@@ -1901,7 +1901,7 @@
 		info->cs = cs;
 		ret = pxa3xx_nand_scan(mtd);
 		if (ret) {
-			dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
+			dev_info(mtd->dev, "failed to scan nand at cs %d\n",
 				 cs);
 			continue;
 		}

diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index 004b6f1..12fc065 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c

@@ -1226,7 +1226,8 @@
 #define sunxi_nand_lookup_timing(l, p, c) \
 			_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
 
-static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
+static int sunxi_nand_chip_set_timings(struct sunxi_nfc *nfc,
+				       struct sunxi_nand_chip *chip,
 				       const struct nand_sdr_timings *timings)
 {
 	u32 min_clk_period = 0;
@@ -1349,7 +1350,8 @@
 	return 0;
 }
 
-static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
+static int sunxi_nand_chip_init_timings(struct sunxi_nfc *nfc,
+					struct sunxi_nand_chip *chip)
 {
 	struct mtd_info *mtd = nand_to_mtd(&chip->nand);
 	const struct nand_sdr_timings *timings;
@@ -1384,7 +1386,7 @@
 	if (IS_ERR(timings))
 		return PTR_ERR(timings);
 
-	return sunxi_nand_chip_set_timings(chip, timings);
+	return sunxi_nand_chip_set_timings(nfc, chip, timings);
 }
 
 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
@@ -1423,7 +1425,7 @@
 	}
 
 	if (i >= ARRAY_SIZE(strengths)) {
-		dev_err(nfc->dev, "unsupported strength\n");
+		dev_err(mtd->dev, "unsupported strength\n");
 		ret = -ENOTSUPP;
 		goto err;
 	}
@@ -1619,7 +1621,7 @@
 
 	nsels /= sizeof(u32);
 	if (!nsels || nsels > 8) {
-		dev_err(dev, "invalid reg property size\n");
+		dev_err(nfc->dev, "invalid reg property size\n");
 		return -EINVAL;
 	}
 
@@ -1627,7 +1629,7 @@
 		       (nsels * sizeof(struct sunxi_nand_chip_sel)),
 		       GFP_KERNEL);
 	if (!chip) {
-		dev_err(dev, "could not allocate chip\n");
+		dev_err(nfc->dev, "could not allocate chip\n");
 		return -ENOMEM;
 	}
 
@@ -1641,14 +1643,14 @@
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
 	if (ret) {
-		dev_err(dev, "could not retrieve reg property: %d\n", ret);
+		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
 		return ret;
 	}
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
 				   nsels);
 	if (ret) {
-		dev_err(dev, "could not retrieve reg property: %d\n", ret);
+		dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
 		return ret;
 	}
 
@@ -1656,14 +1658,13 @@
 		int tmp = cs[i];
 
 		if (tmp > NFC_MAX_CS) {
-			dev_err(dev,
-				"invalid reg value: %u (max CS = 7)\n",
-				tmp);
+			dev_err(nfc->dev,
+				"invalid reg value: %u (max CS = 7)\n", tmp);
 			return -EINVAL;
 		}
 
 		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
-			dev_err(dev, "CS %d already assigned\n", tmp);
+			dev_err(nfc->dev, "CS %d already assigned\n", tmp);
 			return -EINVAL;
 		}
 
@@ -1688,15 +1689,15 @@
 	timings = onfi_async_timing_mode_to_sdr_timings(0);
 	if (IS_ERR(timings)) {
 		ret = PTR_ERR(timings);
-		dev_err(dev,
+		dev_err(nfc->dev,
 			"could not retrieve timings for ONFI mode 0: %d\n",
 			ret);
 		return ret;
 	}
 
-	ret = sunxi_nand_chip_set_timings(chip, timings);
+	ret = sunxi_nand_chip_set_timings(nfc, chip, timings);
 	if (ret) {
-		dev_err(dev, "could not configure chip timings: %d\n", ret);
+		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
 		return ret;
 	}
 
@@ -1729,27 +1730,27 @@
 
 	nand->options |= NAND_SUBPAGE_READ;
 
-	ret = sunxi_nand_chip_init_timings(chip);
+	ret = sunxi_nand_chip_init_timings(nfc, chip);
 	if (ret) {
-		dev_err(dev, "could not configure chip timings: %d\n", ret);
+		dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
 		return ret;
 	}
 
 	ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
 	if (ret) {
-		dev_err(dev, "ECC init failed: %d\n", ret);
+		dev_err(nfc->dev, "ECC init failed: %d\n", ret);
 		return ret;
 	}
 
 	ret = nand_scan_tail(mtd);
 	if (ret) {
-		dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+		dev_err(nfc->dev, "nand_scan_tail failed: %d\n", ret);
 		return ret;
 	}
 
 	ret = nand_register(devnum, mtd);
 	if (ret) {
-		dev_err(dev, "failed to register mtd device: %d\n", ret);
+		dev_err(nfc->dev, "failed to register mtd device: %d\n", ret);
 		return ret;
 	}
 
@@ -1769,7 +1770,7 @@
 		i++;
 
 	if (i > 8) {
-		dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
+		dev_err(nfc->dev, "too many NAND chips: %d (max = 8)\n", i);
 		return -EINVAL;
 	}
 
@@ -1841,7 +1842,7 @@
 
 	ret = sunxi_nand_chips_init(node, nfc);
 	if (ret) {
-		dev_err(dev, "failed to init nand chips\n");
+		dev_err(nfc->dev, "failed to init nand chips\n");
 		goto err;
 	}
 

diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 52c8a94..4e6fdc6 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c

@@ -152,6 +152,8 @@
 
 struct vf610_nfc {
 	struct nand_chip chip;
+	/* NULL without CONFIG_NAND_VF610_NFC_DT */
+	struct udevice *dev;
 	void __iomem *regs;
 	uint buf_offset;
 	int write_sz;
@@ -631,11 +633,10 @@
 	int flash_bbt;
 };
 
-static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
+static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum)
 {
-	struct mtd_info *mtd;
-	struct nand_chip *chip;
-	struct vf610_nfc *nfc;
+	struct nand_chip *chip = &nfc->chip;
+	struct mtd_info *mtd = nand_to_mtd(chip);
 	int err = 0;
 	struct vf610_nfc_config cfg = {
 		.hardware_ecc = 1,
@@ -647,16 +648,6 @@
 		.flash_bbt = 1,
 	};
 
-	nfc = calloc(1, sizeof(*nfc));
-	if (!nfc) {
-		printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
-		return -ENOMEM;
-	}
-
-	chip = &nfc->chip;
-	nfc->regs = addr;
-
-	mtd = nand_to_mtd(chip);
 	nand_set_controller_data(chip, nfc);
 
 	if (cfg.width == 16)
@@ -777,20 +768,23 @@
 static int vf610_nfc_dt_probe(struct udevice *dev)
 {
 	struct resource res;
+	struct vf610_nfc *nfc = dev_get_priv(dev);
 	int ret;
 
 	ret = dev_read_resource(dev, 0, &res);
 	if (ret)
 		return ret;
 
-	return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start,
-						   resource_size(&res)));
+	nfc->regs = devm_ioremap(dev, res.start, resource_size(&res));
+	nfc->dev = dev;
+	return vf610_nfc_nand_init(nfc, 0);
 }
 
 U_BOOT_DRIVER(vf610_nfc_dt) = {
 	.name = "vf610-nfc-dt",
 	.id = UCLASS_MTD,
 	.of_match = vf610_nfc_dt_ids,
+	.priv_auto_alloc_size = sizeof(struct vf610_nfc),
 	.probe = vf610_nfc_dt_probe,
 };
 
@@ -809,7 +803,17 @@
 #else
 void board_nand_init(void)
 {
-	int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
+	int err;
+	struct vf610_nfc *nfc;
+
+	nfc = calloc(1, sizeof(*nfc));
+	if (!nfc) {
+		printf("%s: Out of memory\n", __func__);
+		return;
+	}
+
+	nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	err = vf610_nfc_nand_init(nfc, 0);
 	if (err)
 		printf("VF610 NAND init failed (err %d)\n", err);
 }

diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index fa59455..92db2aa 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c

@@ -1282,7 +1282,7 @@
 };
 
 U_BOOT_DRIVER(zynq_nand) = {
-	.name = "zynq-nand",
+	.name = "zynq_nand",
 	.id = UCLASS_MTD,
 	.of_match = zynq_nand_dt_ids,
 	.probe = zynq_nand_probe,

diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 93371fd..8c7e07d 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c

@@ -984,13 +984,13 @@
 
 	ret = spinand_manufacturer_detect(spinand);
 	if (ret) {
-		dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
-			spinand->id.data);
+		dev_err(spinand->slave->dev, "unknown raw ID %*phN\n",
+			SPINAND_MAX_ID_LEN, spinand->id.data);
 		return ret;
 	}
 
 	if (nand->memorg.ntargets > 1 && !spinand->select_target) {
-		dev_err(dev,
+		dev_err(spinand->slave->dev,
 			"SPI NANDs with more than one die must implement ->select_target()\n");
 		return -EINVAL;
 	}
@@ -1076,7 +1076,7 @@
 
 	ret = spinand_manufacturer_init(spinand);
 	if (ret) {
-		dev_err(dev,
+		dev_err(spinand->slave->dev,
 			"Failed to initialize the SPI NAND chip (err = %d)\n",
 			ret);
 		goto err_free_bufs;

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 0113e70..e16b0e1 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c

@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <log.h>
+#include <dm.h>
 #include <dm/device_compat.h>
 #include <dm/devres.h>
 #include <linux/bitops.h>

diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index fa26ea3..07c8c7b 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c

@@ -55,9 +55,19 @@
 	int ret;
 
 	ret = spi_nor_read_write_reg(nor, &op, val);
-	if (ret < 0)
-		dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
+	if (ret < 0) {
+		/*
+		 * spi_slave does not have a struct udevice member without DM,
+		 * so use the bus and cs instead.
+		 */
+#if CONFIG_IS_ENABLED(DM_SPI)
+		dev_dbg(nor->spi->dev, "error %d reading %x\n", ret,
 			code);
+#else
+		log_debug("spi%u.%u: error %d reading %x\n",
+			  nor->spi->bus, nor->spi->cs, ret, code);
+#endif
+	}
 
 	return ret;
 }
@@ -512,7 +522,8 @@
 	/* Check current Quad Enable bit value. */
 	ret = read_cr(nor);
 	if (ret < 0) {
-		dev_dbg(dev, "error while reading configuration register\n");
+		dev_dbg(nor->dev,
+			"error while reading configuration register\n");
 		return -EINVAL;
 	}
 
@@ -524,7 +535,7 @@
 	/* Keep the current value of the Status Register. */
 	ret = read_sr(nor);
 	if (ret < 0) {
-		dev_dbg(dev, "error while reading status register\n");
+		dev_dbg(nor->dev, "error while reading status register\n");
 		return -EINVAL;
 	}
 	sr_cr[0] = ret;
@@ -785,7 +796,7 @@
 	}
 
 	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
-		dev_dbg(dev, "address width is too large: %u\n",
+		dev_dbg(nor->dev, "address width is too large: %u\n",
 			nor->addr_width);
 		return -EINVAL;
 	}

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 039f9fb..a0d2d21 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig

@@ -432,6 +432,8 @@
 	  This driver supports AMD PCnet series fast ethernet family of
 	  PCI chipsets/adapters.
 
+source "drivers/net/qe/Kconfig"
+
 config RTL8139
 	bool "Realtek 8139 series Ethernet controller driver"
 	help

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 1ecdc40..03f0192 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile

@@ -78,6 +78,7 @@
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_FSL_PFE) += pfe_eth/
+obj-y += qe/
 obj-$(CONFIG_SNI_AVE) += sni_ave.o
 obj-y += ti/
 obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o

diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c
index 648fafd..38a2a30 100644
--- a/drivers/net/bcm6368-eth.c
+++ b/drivers/net/bcm6368-eth.c

@@ -249,8 +249,7 @@
 
 		/* link changed */
 		if (!up) {
-			dev_info(&priv->pdev->dev, "link DOWN on %s\n",
-				 port->name);
+			dev_info(dev, "link DOWN on %s\n", port->name);
 			writeb_be(ETH_PORTOV_ENABLE_MASK,
 				  priv->base + ETH_PORTOV_REG(i));
 			writeb_be(ETH_PTCTRL_RXDIS_MASK |

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 810a2b9..db11025 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c

@@ -26,6 +26,7 @@
  *    supports a single RGMII PHY. This configuration also has SW control over
  *    all clock and reset signals to the HW block.
  */
+
 #include <common.h>
 #include <clk.h>
 #include <cpu_func.h>
@@ -1893,8 +1894,7 @@
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
-	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
-			       NULL);
+	phy_mode = dev_read_prop(dev, "phy-mode", NULL);
 	if (phy_mode)
 		interface = phy_get_interface_by_name(phy_mode);
 
@@ -1931,8 +1931,7 @@
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
-	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
-			       NULL);
+	phy_mode = dev_read_prop(dev, "phy-mode", NULL);
 	if (phy_mode)
 		interface = phy_get_interface_by_name(phy_mode);
 

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d2edd17..77f1a96 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c

@@ -11,6 +11,7 @@
 #include <fsl_mdio.h>
 #include <asm/io.h>
 #include <linux/errno.h>
+#include <tsec.h>
 
 #ifdef CONFIG_DM_MDIO
 struct tsec_mdio_priv {
@@ -190,17 +191,30 @@
 	.reset = tsec_mdio_reset,
 };
 
+static struct fsl_pq_mdio_data etsec2_data = {
+	.mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+	.mdio_regs_off = 0x0,
+};
+
+static struct fsl_pq_mdio_data fman_data = {
+	.mdio_regs_off = 0x0,
+};
+
 static const struct udevice_id tsec_mdio_ids[] = {
-	{ .compatible = "fsl,gianfar-tbi" },
-	{ .compatible = "fsl,gianfar-mdio" },
-	{ .compatible = "fsl,etsec2-tbi" },
-	{ .compatible = "fsl,etsec2-mdio" },
-	{ .compatible = "fsl,fman-mdio" },
+	{ .compatible = "fsl,gianfar-tbi", .data = (ulong)&gianfar_data },
+	{ .compatible = "fsl,gianfar-mdio", .data = (ulong)&gianfar_data },
+	{ .compatible = "fsl,etsec2-tbi", .data = (ulong)&etsec2_data },
+	{ .compatible = "fsl,etsec2-mdio", .data = (ulong)&etsec2_data },
+	{ .compatible = "fsl,fman-mdio", .data = (ulong)&fman_data },
 	{}
 };
 
 static int tsec_mdio_probe(struct udevice *dev)
 {
+	struct fsl_pq_mdio_data *data;
 	struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
 	struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
 						 NULL;
@@ -213,7 +227,9 @@
 		printf("dev_get_priv(dev %p) = NULL\n", dev);
 		return -1;
 	}
-	priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+
+	data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
+	priv->regs = dev_remap_addr(dev) + data->mdio_regs_off;
 	debug("%s priv %p @ regs %p, pdata %p\n", __func__,
 	      priv, priv->regs, pdata);
 

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 5676a5b..00bda24 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c

@@ -551,6 +551,10 @@
 	priv->max_speed = pdata->max_speed;
 	priv->phy_addr = 0;
 
+#ifdef CONFIG_PHY_ADDR
+	priv->phy_addr = CONFIG_PHY_ADDR;
+#endif
+
 	ret = clk_enable_bulk(&priv->clks);
 	if (ret)
 		goto out;

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 4c7d06c..83f99e5 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c

@@ -625,9 +625,9 @@
 	count = 0;
 	do {
 		if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
-			netdev_warn(pp->dev,
-				    "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
-				    val);
+			dev_warn(pp->phydev->dev,
+				 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
+				 val);
 			break;
 		}
 		mdelay(1);
@@ -648,9 +648,9 @@
 	count = 0;
 	do {
 		if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
-			netdev_warn(pp->dev,
-				    "TIMEOUT for TX stopped status=0x%08x\n",
-				    val);
+			dev_warn(pp->phydev->dev,
+				 "TIMEOUT for TX stopped status=0x%08x\n",
+				 val);
 			break;
 		}
 		mdelay(1);
@@ -664,9 +664,9 @@
 	count = 0;
 	do {
 		if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
-			netdev_warn(pp->dev,
-				    "TX FIFO empty timeout status=0x08%x\n",
-				    val);
+			dev_warn(pp->phydev->dev,
+				 "TX FIFO empty timeout status=0x08%x\n",
+				 val);
 			break;
 		}
 		mdelay(1);
@@ -949,28 +949,32 @@
 	u32 status = rx_desc->status;
 
 	if (!mvneta_rxq_desc_is_first_last(status)) {
-		netdev_err(pp->dev,
-			   "bad rx status %08x (buffer oversize), size=%d\n",
-			   status, rx_desc->data_size);
+		dev_err(pp->phydev->dev,
+			"bad rx status %08x (buffer oversize), size=%d\n",
+			status, rx_desc->data_size);
 		return;
 	}
 
 	switch (status & MVNETA_RXD_ERR_CODE_MASK) {
 	case MVNETA_RXD_ERR_CRC:
-		netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
-			   status, rx_desc->data_size);
+		dev_err(pp->phydev->dev,
+			"bad rx status %08x (crc error), size=%d\n", status,
+			rx_desc->data_size);
 		break;
 	case MVNETA_RXD_ERR_OVERRUN:
-		netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
-			   status, rx_desc->data_size);
+		dev_err(pp->phydev->dev,
+			"bad rx status %08x (overrun error), size=%d\n", status,
+			rx_desc->data_size);
 		break;
 	case MVNETA_RXD_ERR_LEN:
-		netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
-			   status, rx_desc->data_size);
+		dev_err(pp->phydev->dev,
+			"bad rx status %08x (max frame length error), size=%d\n",
+			status, rx_desc->data_size);
 		break;
 	case MVNETA_RXD_ERR_RESOURCE:
-		netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
-			   status, rx_desc->data_size);
+		dev_err(pp->phydev->dev,
+			"bad rx status %08x (resource error), size=%d\n",
+			status, rx_desc->data_size);
 		break;
 	}
 }
@@ -1127,8 +1131,8 @@
 	for (queue = 0; queue < rxq_number; queue++) {
 		int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
 		if (err) {
-			netdev_err(pp->dev, "%s: can't create rxq=%d\n",
-				   __func__, queue);
+			dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
+				__func__, queue);
 			mvneta_cleanup_rxqs(pp);
 			return err;
 		}
@@ -1145,8 +1149,8 @@
 	for (queue = 0; queue < txq_number; queue++) {
 		int err = mvneta_txq_init(pp, &pp->txqs[queue]);
 		if (err) {
-			netdev_err(pp->dev, "%s: can't create txq=%d\n",
-				   __func__, queue);
+			dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
+				__func__, queue);
 			mvneta_cleanup_txqs(pp);
 			return err;
 		}
@@ -1402,7 +1406,7 @@
 
 	err = mvneta_init2(pp);
 	if (err < 0) {
-		dev_err(&pdev->dev, "can't init eth hal\n");
+		dev_err(dev, "can't init eth hal\n");
 		return err;
 	}
 
@@ -1410,7 +1414,7 @@
 
 	err = mvneta_port_power_up(pp, pp->phy_interface);
 	if (err < 0) {
-		dev_err(&pdev->dev, "can't power up port\n");
+		dev_err(dev, "can't power up port\n");
 		return err;
 	}
 

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index a5747a2..8f790a8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c

@@ -2568,7 +2568,7 @@
 
 	if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 			MVPP2_BM_POOL_PTR_ALIGN)) {
-		dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
+		dev_err(dev, "BM pool %d is not %d bytes aligned\n",
 			bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 		return -ENOMEM;
 	}
@@ -2659,7 +2659,7 @@
 	return 0;
 
 err_unroll_pools:
-	dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
+	dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
 	for (i = i - 1; i >= 0; i--)
 		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
 	return err;
@@ -2773,9 +2773,9 @@
 
 	if (buf_num < 0 ||
 	    (buf_num + bm_pool->buf_num > bm_pool->size)) {
-		netdev_err(port->dev,
-			   "cannot allocate %d buffers for pool %d\n",
-			   buf_num, bm_pool->id);
+		dev_err(port->phy_dev->dev,
+			"cannot allocate %d buffers for pool %d\n", buf_num,
+			bm_pool->id);
 		return 0;
 	}
 
@@ -2803,7 +2803,7 @@
 	int num;
 
 	if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
-		netdev_err(port->dev, "mixing pool types is forbidden\n");
+		dev_err(port->phy_dev->dev, "mixing pool types is forbidden\n");
 		return NULL;
 	}
 
@@ -2834,8 +2834,9 @@
 		/* Allocate buffers for this pool */
 		num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
 		if (num != pkts_num) {
-			dev_err(dev, "pool %d: %d of %d allocated\n",
-				new_pool->id, num, pkts_num);
+			dev_err(port->phy_dev->dev,
+				"pool %d: %d of %d allocated\n", new_pool->id,
+				num, pkts_num);
 			return NULL;
 		}
 	}
@@ -3344,8 +3345,7 @@
 	int num_of_act_lanes;
 
 	if (mac_num >= MVPP22_GOP_MAC_NUM) {
-		netdev_err(NULL, "%s: illegal port number %d", __func__,
-			   mac_num);
+		log_err("illegal port number %d", mac_num);
 		return -1;
 	}
 
@@ -3399,8 +3399,8 @@
 		break;
 
 	default:
-		netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
-			   __func__, port->phy_interface);
+		log_err("Requested port mode (%d) not supported\n",
+			port->phy_interface);
 		return -1;
 	}
 
@@ -3440,8 +3440,8 @@
 
 		break;
 	default:
-		netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
-			   port->phy_interface);
+		log_err("%s: Wrong port mode (%d)\n", __func__,
+			port->phy_interface);
 		return;
 	}
 }
@@ -3811,9 +3811,9 @@
 	delay = 0;
 	do {
 		if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
-			netdev_warn(port->dev,
-				    "Tx stop timed out, status=0x%08x\n",
-				    reg_data);
+			dev_warn(port->phy_dev->dev,
+				 "Tx stop timed out, status=0x%08x\n",
+				 reg_data);
 			break;
 		}
 		mdelay(1);
@@ -4261,9 +4261,9 @@
 	delay = 0;
 	do {
 		if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
-			netdev_warn(port->dev,
-				    "port %d: cleaning queue %d timed out\n",
-				    port->id, txq->log_id);
+			dev_warn(port->phy_dev->dev,
+				 "port %d: cleaning queue %d timed out\n",
+				 port->id, txq->log_id);
 			break;
 		}
 		mdelay(1);
@@ -4430,16 +4430,19 @@
 
 	switch (status & MVPP2_RXD_ERR_CODE_MASK) {
 	case MVPP2_RXD_ERR_CRC:
-		netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
-			   status, sz);
+		dev_err(port->phy_dev->dev,
+			"bad rx status %08x (crc error), size=%zu\n", status,
+			sz);
 		break;
 	case MVPP2_RXD_ERR_OVERRUN:
-		netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
-			   status, sz);
+		dev_err(port->phy_dev->dev,
+			"bad rx status %08x (overrun error), size=%zu\n",
+			status, sz);
 		break;
 	case MVPP2_RXD_ERR_RESOURCE:
-		netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
-			   status, sz);
+		dev_err(port->phy_dev->dev,
+			"bad rx status %08x (resource error), size=%zu\n",
+			status, sz);
 		break;
 	}
 }
@@ -4507,8 +4510,8 @@
 		 */
 		if (phy_dev &&
 		    phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
-			netdev_warn(port->dev,
-				    "Marking phy as invalid, link will not be checked\n");
+			dev_warn(port->phy_dev->dev,
+				 "Marking phy as invalid, link will not be checked\n");
 			/* set phy_addr to invalid value */
 			port->phyaddr = PHY_MAX_ADDR;
 			mvpp2_egress_enable(port);
@@ -4519,7 +4522,7 @@
 
 		port->phy_dev = phy_dev;
 		if (!phy_dev) {
-			netdev_err(port->dev, "cannot connect to phy\n");
+			dev_err(port->phy_dev->dev, "cannot connect to phy\n");
 			return;
 		}
 		phy_dev->supported &= PHY_GBIT_FEATURES;
@@ -4550,31 +4553,31 @@
 
 	err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
 	if (err) {
-		netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
+		dev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
 		return err;
 	}
 	err = mvpp2_prs_mac_da_accept(port->priv, port->id,
 				      port->dev_addr, true);
 	if (err) {
-		netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
+		dev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
 		return err;
 	}
 	err = mvpp2_prs_def_flow(port);
 	if (err) {
-		netdev_err(dev, "mvpp2_prs_def_flow failed\n");
+		dev_err(dev, "mvpp2_prs_def_flow failed\n");
 		return err;
 	}
 
 	/* Allocate the Rx/Tx queues */
 	err = mvpp2_setup_rxqs(port);
 	if (err) {
-		netdev_err(port->dev, "cannot allocate Rx queues\n");
+		dev_err(port->phy_dev->dev, "cannot allocate Rx queues\n");
 		return err;
 	}
 
 	err = mvpp2_setup_txqs(port);
 	if (err) {
-		netdev_err(port->dev, "cannot allocate Tx queues\n");
+		dev_err(port->phy_dev->dev, "cannot allocate Tx queues\n");
 		return err;
 	}
 
@@ -4725,7 +4728,7 @@
 		int parent;
 		phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 		if (phyaddr < 0) {
-			dev_err(&pdev->dev, "could not find phy address\n");
+			dev_err(dev, "could not find phy address\n");
 			return -1;
 		}
 		parent = fdt_parent_offset(gd->fdt_blob, phy_node);
@@ -4742,13 +4745,13 @@
 	if (phy_mode_str)
 		phy_mode = phy_get_interface_by_name(phy_mode_str);
 	if (phy_mode == -1) {
-		dev_err(&pdev->dev, "incorrect phy mode\n");
+		dev_err(dev, "incorrect phy mode\n");
 		return -EINVAL;
 	}
 
 	id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
 	if (id == -1) {
-		dev_err(&pdev->dev, "missing port-id value\n");
+		dev_err(dev, "missing port-id value\n");
 		return -EINVAL;
 	}
 
@@ -4807,7 +4810,7 @@
 
 	err = mvpp2_port_init(dev, port);
 	if (err < 0) {
-		dev_err(&pdev->dev, "failed to init port %d\n", port->id);
+		dev_err(dev, "failed to init port %d\n", port->id);
 		return err;
 	}
 	mvpp2_port_power_up(port);
@@ -4978,7 +4981,7 @@
 	/* Checks for hardware constraints (U-Boot uses only one rxq) */
 	if ((rxq_number > priv->max_port_rxqs) ||
 	    (txq_number > MVPP2_MAX_TXQ)) {
-		dev_err(&pdev->dev, "invalid queue size parameter\n");
+		dev_err(dev, "invalid queue size parameter\n");
 		return -EINVAL;
 	}
 
@@ -5099,7 +5102,7 @@
 
 	err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
 	if (err) {
-		netdev_err(port->dev, "failed to refill BM pools\n");
+		dev_err(port->phy_dev->dev, "failed to refill BM pools\n");
 		return 0;
 	}
 
@@ -5345,7 +5348,7 @@
 		port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					      "gop-port-id", -1);
 		if (port->id == -1) {
-			dev_err(&pdev->dev, "missing gop-port-id value\n");
+			dev_err(dev, "missing gop-port-id value\n");
 			return -EINVAL;
 		}
 
@@ -5364,7 +5367,7 @@
 		/* Initialize network controller */
 		err = mvpp2_init(dev, priv);
 		if (err < 0) {
-			dev_err(&pdev->dev, "failed to initialize controller\n");
+			dev_err(dev, "failed to initialize controller\n");
 			return err;
 		}
 		priv->num_ports = 0;

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 709979f..d1a643c 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c

@@ -157,6 +157,14 @@
 #define INT_MEM_DATA_M			GENMASK(7, 0)
 #define INT_MEM_DATA(x)			(INT_MEM_DATA_M & (x))
 
+/* Extended page GPIO register 13G */
+#define MSCC_CLKOUT_CNTL		13
+#define CLKOUT_ENABLE			BIT(15)
+#define CLKOUT_FREQ_MASK		GENMASK(14, 13)
+#define CLKOUT_FREQ_25M			(0x0 << 13)
+#define CLKOUT_FREQ_50M			(0x1 << 13)
+#define CLKOUT_FREQ_125M		(0x2 << 13)
+
 /* Extended page GPIO register 18G */
 #define MSCC_PHY_PROC_CMD		  18
 #define PROC_CMD_NCOMPLETED		  BIT(15)
@@ -1168,6 +1176,9 @@
 		rx_clk_out = RX_CLK_OUT_NORMAL;
 		break;
 
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII:
 		/* Set Reg23.12:11=2 */
 		mac_if = MAC_IF_SELECTION_RGMII;
@@ -1210,13 +1221,84 @@
 	return 0;
 }
 
+static int vsc8531_vsc8541_clkout_config(struct phy_device *phydev)
+{
+	struct ofnode_phandle_args phandle_args;
+	u32 clkout_rate = 0;
+	u16 reg_val;
+	int retval;
+
+	retval = dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL,
+					    0, 0, &phandle_args);
+	if (!retval)
+		clkout_rate = ofnode_read_u32_default(phandle_args.node,
+						"vsc8531,clk-out-frequency", 0);
+
+	switch (clkout_rate) {
+	case 0:
+		reg_val = 0;
+		break;
+	case 25000000:
+		reg_val = CLKOUT_FREQ_25M | CLKOUT_ENABLE;
+		break;
+	case 50000000:
+		reg_val = CLKOUT_FREQ_50M | CLKOUT_ENABLE;
+		break;
+	case 125000000:
+		reg_val = CLKOUT_FREQ_125M | CLKOUT_ENABLE;
+		break;
+	default:
+		printf("PHY 8530/31 invalid clkout rate %u\n",
+		       clkout_rate);
+		return -EINVAL;
+	}
+
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+		  MSCC_PHY_PAGE_GPIO);
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_CLKOUT_CNTL, reg_val);
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+		  MSCC_PHY_PAGE_STD);
+
+	return 0;
+}
+
+static int vsc8531_vsc8541_clk_skew_config(struct phy_device *phydev)
+{
+	enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_200_PS;
+	enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_200_PS;
+	u16 reg_val;
+
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		rx_clk_skew = VSC_PHY_RGMII_DELAY_2000_PS;
+
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		tx_clk_skew = VSC_PHY_RGMII_DELAY_2000_PS;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+		  MSCC_PHY_PAGE_EXT2);
+	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
+
+	/* Reg20E2 - Update RGMII RX_Clk Skews. */
+	reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
+				   RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
+	/* Reg20E2 - Update RGMII TX_Clk Skews. */
+	reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
+				   RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
+	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+		  MSCC_PHY_PAGE_STD);
+
+	return 0;
+}
+
 static int vsc8531_config(struct phy_device *phydev)
 {
 	int  retval = -EINVAL;
 	u16  reg_val;
 	u16  rmii_clk_out;
-	enum vsc_phy_rgmii_skew  rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
-	enum vsc_phy_rgmii_skew  tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
 	enum vsc_phy_clk_slew    edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
 
 	/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
@@ -1226,6 +1308,9 @@
 	switch (phydev->interface) {
 	case PHY_INTERFACE_MODE_RMII:
 	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		retval = vsc8531_vsc8541_mac_config(phydev);
 		if (retval != 0)
 			return retval;
@@ -1242,19 +1327,12 @@
 	/* Default RMII Clk Output to 0=OFF/1=ON  */
 	rmii_clk_out = 0;
 
+	retval = vsc8531_vsc8541_clk_skew_config(phydev);
+	if (retval != 0)
+		return retval;
+
 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
 		  MSCC_PHY_PAGE_EXT2);
-	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
-
-	/* Reg20E2 - Update RGMII RX_Clk Skews. */
-	reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
-				   RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
-	/* Reg20E2 - Update RGMII TX_Clk Skews. */
-	reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
-				   RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
-
-	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
-
 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
 	/* Reg27E2 - Update Clk Slew Rate. */
 	reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
@@ -1267,6 +1345,11 @@
 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
 		  MSCC_PHY_PAGE_STD);
 
+	/* Configure the clk output */
+	retval = vsc8531_vsc8541_clkout_config(phydev);
+	if (retval != 0)
+		return retval;
+
 	return genphy_config_aneg(phydev);
 }
 
@@ -1275,8 +1358,6 @@
 	int  retval = -EINVAL;
 	u16  reg_val;
 	u16  rmii_clk_out;
-	enum vsc_phy_rgmii_skew  rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
-	enum vsc_phy_rgmii_skew  tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
 	enum vsc_phy_clk_slew    edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
 
 	/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
@@ -1304,17 +1385,12 @@
 	/* Default RMII Clk Output to 0=OFF/1=ON  */
 	rmii_clk_out = 0;
 
+	retval = vsc8531_vsc8541_clk_skew_config(phydev);
+	if (retval != 0)
+		return retval;
+
 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
 		  MSCC_PHY_PAGE_EXT2);
-	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
-	/* Reg20E2 - Update RGMII RX_Clk Skews. */
-	reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
-				   RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
-	/* Reg20E2 - Update RGMII TX_Clk Skews. */
-	reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
-				   RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
-	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
-
 	reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
 	/* Reg27E2 - Update Clk Slew Rate. */
 	reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
@@ -1327,6 +1403,11 @@
 	phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
 		  MSCC_PHY_PAGE_STD);
 
+	/* Configure the clk output */
+	retval = vsc8531_vsc8541_clkout_config(phydev);
+	if (retval != 0)
+		return retval;
+
 	return genphy_config_aneg(phydev);
 }
 

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 6778989..9587e6b 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c

@@ -664,7 +664,7 @@
 	dev = malloc(sizeof(*dev));
 	if (!dev) {
 		printf("Failed to allocate PHY device for %s:%d\n",
-		       bus->name, addr);
+		       bus ? bus->name : "(null bus)", addr);
 		return NULL;
 	}
 
@@ -692,7 +692,7 @@
 		return NULL;
 	}
 
-	if (addr >= 0 && addr < PHY_MAX_ADDR)
+	if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
 		bus->phymap[addr] = dev;
 
 	return dev;

diff --git a/drivers/net/qe/Kconfig b/drivers/net/qe/Kconfig
new file mode 100644
index 0000000..dec88de
--- /dev/null
+++ b/drivers/net/qe/Kconfig

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+
+config QE_UEC
+	bool "NXP QE UEC Ethernet controller"
+	depends on DM_ETH
+	help
+	  This driver supports the NXP QE UEC ethernet controller

diff --git a/drivers/net/qe/Makefile b/drivers/net/qe/Makefile
new file mode 100644
index 0000000..7d84757
--- /dev/null
+++ b/drivers/net/qe/Makefile

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+
+obj-$(CONFIG_QE_UEC) += dm_qe_uec.o dm_qe_uec_phy.o uccf.o

diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c
new file mode 100644
index 0000000..3482b3f
--- /dev/null
+++ b/drivers/net/qe/dm_qe_uec.c

@@ -0,0 +1,1167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * QE UEC ethernet controller driver
+ *
+ * based on drivers/qe/uec.c from NXP
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <memalign.h>
+#include <miiphy.h>
+#include <asm/io.h>
+
+#include "dm_qe_uec.h"
+
+#define QE_UEC_DRIVER_NAME	"ucc_geth"
+
+/* Default UTBIPAR SMI address */
+#ifndef CONFIG_UTBIPAR_INIT_TBIPA
+#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
+#endif
+
+static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
+{
+	uec_t		*uec_regs;
+	u32		maccfg1;
+
+	uec_regs = uec->uec_regs;
+	maccfg1 = in_be32(&uec_regs->maccfg1);
+
+	if (mode & COMM_DIR_TX)	{
+		maccfg1 |= MACCFG1_ENABLE_TX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_tx_enabled = 1;
+	}
+
+	if (mode & COMM_DIR_RX)	{
+		maccfg1 |= MACCFG1_ENABLE_RX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_rx_enabled = 1;
+	}
+
+	return 0;
+}
+
+static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
+{
+	uec_t		*uec_regs;
+	u32		maccfg1;
+
+	uec_regs = uec->uec_regs;
+	maccfg1 = in_be32(&uec_regs->maccfg1);
+
+	if (mode & COMM_DIR_TX)	{
+		maccfg1 &= ~MACCFG1_ENABLE_TX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_tx_enabled = 0;
+	}
+
+	if (mode & COMM_DIR_RX)	{
+		maccfg1 &= ~MACCFG1_ENABLE_RX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_rx_enabled = 0;
+	}
+
+	return 0;
+}
+
+static int uec_restart_tx(struct uec_priv *uec)
+{
+	struct uec_inf	*ui = uec->uec_info;
+	u32		cecr_subblock;
+
+	cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
+	qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	uec->grace_stopped_tx = 0;
+
+	return 0;
+}
+
+static int uec_restart_rx(struct uec_priv *uec)
+{
+	struct uec_inf	*ui = uec->uec_info;
+	u32		cecr_subblock;
+
+	cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
+	qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	uec->grace_stopped_rx = 0;
+
+	return 0;
+}
+
+static int uec_open(struct uec_priv *uec, comm_dir_e mode)
+{
+	struct ucc_fast_priv	*uccf;
+
+	uccf = uec->uccf;
+
+	/* check if the UCC number is in range. */
+	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
+		printf("%s: ucc_num out of range.\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Enable MAC */
+	uec_mac_enable(uec, mode);
+
+	/* Enable UCC fast */
+	ucc_fast_enable(uccf, mode);
+
+	/* RISC microcode start */
+	if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
+		uec_restart_tx(uec);
+
+	if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
+		uec_restart_rx(uec);
+
+	return 0;
+}
+
+static int uec_set_mac_if_mode(struct uec_priv *uec)
+{
+	struct uec_inf		*uec_info = uec->uec_info;
+	phy_interface_t		enet_if_mode;
+	uec_t			*uec_regs;
+	u32			upsmr;
+	u32			maccfg2;
+
+	uec_regs = uec->uec_regs;
+	enet_if_mode = uec_info->enet_interface_type;
+
+	maccfg2 = in_be32(&uec_regs->maccfg2);
+	maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
+
+	upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
+	upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
+
+	switch (uec_info->speed) {
+	case SPEED_10:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_MII:
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= (UPSMR_RPM | UPSMR_R10M);
+			break;
+		case PHY_INTERFACE_MODE_RMII:
+			upsmr |= (UPSMR_R10M | UPSMR_RMM);
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	case SPEED_100:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_MII:
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= UPSMR_RPM;
+			break;
+		case PHY_INTERFACE_MODE_RMII:
+			upsmr |= UPSMR_RMM;
+			break;
+		default:
+			return -EINVAL;
+	}
+	break;
+	case SPEED_1000:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_GMII:
+			break;
+		case PHY_INTERFACE_MODE_TBI:
+			upsmr |= UPSMR_TBIM;
+			break;
+		case PHY_INTERFACE_MODE_RTBI:
+			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
+			break;
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= UPSMR_RPM;
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			upsmr |= UPSMR_SGMM;
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	out_be32(&uec_regs->maccfg2, maccfg2);
+	out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
+
+	return 0;
+}
+
+static int qe_uec_start(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv		*uec = priv->uec;
+	struct phy_device	*phydev = priv->phydev;
+	struct uec_inf		*uec_info = uec->uec_info;
+	int			err;
+
+	if (!phydev)
+		return -ENODEV;
+
+	/* Setup MAC interface mode */
+	genphy_update_link(phydev);
+	genphy_parse_link(phydev);
+	uec_info->speed = phydev->speed;
+	uec_set_mac_if_mode(uec);
+
+	err = uec_open(uec, COMM_DIR_RX_AND_TX);
+	if (err) {
+		printf("%s: cannot enable UEC device\n", dev->name);
+		return -EINVAL;
+	}
+
+	return (phydev->link ? 0 : -EINVAL);
+}
+
+static int qe_uec_send(struct udevice *dev, void *packet, int length)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv		*uec = priv->uec;
+	struct ucc_fast_priv	*uccf = uec->uccf;
+	struct buffer_descriptor	*bd;
+	u16			status;
+	int			i;
+	int			result = 0;
+
+	uccf = uec->uccf;
+	bd = uec->tx_bd;
+
+	/* Find an empty TxBD */
+	for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
+		if (i > 0x100000) {
+			printf("%s: tx buffer not ready\n", dev->name);
+			return result;
+		}
+	}
+
+	/* Init TxBD */
+	BD_DATA_SET(bd, packet);
+	BD_LENGTH_SET(bd, length);
+	status = BD_STATUS(bd);
+	status &= BD_WRAP;
+	status |= (TX_BD_READY | TX_BD_LAST);
+	BD_STATUS_SET(bd, status);
+
+	/* Tell UCC to transmit the buffer */
+	ucc_fast_transmit_on_demand(uccf);
+
+	/* Wait for buffer to be transmitted */
+	for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
+		if (i > 0x100000) {
+			printf("%s: tx error\n", dev->name);
+			return result;
+		}
+	}
+
+	/* Ok, the buffer be transimitted */
+	BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
+	uec->tx_bd = bd;
+	result = 1;
+
+	return result;
+}
+
+/*
+ * Receive frame:
+ * - wait for the next BD to get ready bit set
+ * - clean up the descriptor
+ * - move on and indicate to HW that the cleaned BD is available for Rx
+ */
+static int qe_uec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv		*uec = priv->uec;
+	struct buffer_descriptor	*bd;
+	u16			status;
+	u16			len = 0;
+	u8			*data;
+
+	*packetp = memalign(ARCH_DMA_MINALIGN, MAX_RXBUF_LEN);
+	if (*packetp == 0) {
+		printf("%s: error allocating packetp\n", __func__);
+		return -ENOMEM;
+	}
+
+	bd = uec->rx_bd;
+	status = BD_STATUS(bd);
+
+	while (!(status & RX_BD_EMPTY)) {
+		if (!(status & RX_BD_ERROR)) {
+			data = BD_DATA(bd);
+			len = BD_LENGTH(bd);
+			memcpy(*packetp, (char *)data, len);
+		} else {
+			printf("%s: Rx error\n", dev->name);
+		}
+		status &= BD_CLEAN;
+		BD_LENGTH_SET(bd, 0);
+		BD_STATUS_SET(bd, status | RX_BD_EMPTY);
+		BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
+		status = BD_STATUS(bd);
+	}
+	uec->rx_bd = bd;
+
+	return len;
+}
+
+static int uec_graceful_stop_tx(struct uec_priv *uec)
+{
+	ucc_fast_t		*uf_regs;
+	u32			cecr_subblock;
+	u32			ucce;
+
+	uf_regs = uec->uccf->uf_regs;
+
+	/* Clear the grace stop event */
+	out_be32(&uf_regs->ucce, UCCE_GRA);
+
+	/* Issue host command */
+	cecr_subblock =
+		 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+	qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	/* Wait for command to complete */
+	do {
+		ucce = in_be32(&uf_regs->ucce);
+	} while (!(ucce & UCCE_GRA));
+
+	uec->grace_stopped_tx = 1;
+
+	return 0;
+}
+
+static int uec_graceful_stop_rx(struct uec_priv *uec)
+{
+	u32		cecr_subblock;
+	u8		ack;
+
+	if (!uec->p_rx_glbl_pram) {
+		printf("%s: No init rx global parameter\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Clear acknowledge bit */
+	ack = uec->p_rx_glbl_pram->rxgstpack;
+	ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
+	uec->p_rx_glbl_pram->rxgstpack = ack;
+
+	/* Keep issuing cmd and checking ack bit until it is asserted */
+	do {
+		/* Issue host command */
+		cecr_subblock =
+		ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+		qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
+			     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+		ack = uec->p_rx_glbl_pram->rxgstpack;
+	} while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
+
+	uec->grace_stopped_rx = 1;
+
+	return 0;
+}
+
+static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
+{
+	/* check if the UCC number is in range. */
+	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
+		printf("%s: ucc_num out of range.\n", __func__);
+		return -EINVAL;
+	}
+	/* Stop any transmissions */
+	if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
+		uec_graceful_stop_tx(uec);
+
+	/* Stop any receptions */
+	if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
+		uec_graceful_stop_rx(uec);
+
+	/* Disable the UCC fast */
+	ucc_fast_disable(uec->uccf, mode);
+
+	/* Disable the MAC */
+	uec_mac_disable(uec, mode);
+
+	return 0;
+}
+
+static void qe_uec_stop(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv		*uec = priv->uec;
+
+	uec_stop(uec, COMM_DIR_RX_AND_TX);
+}
+
+static int qe_uec_set_hwaddr(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct uec_priv *uec = priv->uec;
+	uec_t *uec_regs = uec->uec_regs;
+	uchar *mac = pdata->enetaddr;
+	u32		mac_addr1;
+	u32		mac_addr2;
+
+	/*
+	 * if a station address of 0x12345678ABCD, perform a write to
+	 * MACSTNADDR1 of 0xCDAB7856,
+	 * MACSTNADDR2 of 0x34120000
+	 */
+
+	mac_addr1 = (mac[5] << 24) | (mac[4] << 16) |
+			(mac[3] << 8)  | (mac[2]);
+	out_be32(&uec_regs->macstnaddr1, mac_addr1);
+
+	mac_addr2 = ((mac[1] << 24) | (mac[0] << 16)) & 0xffff0000;
+	out_be32(&uec_regs->macstnaddr2, mac_addr2);
+
+	return 0;
+}
+
+static int qe_uec_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	if (packet)
+		free(packet);
+
+	return 0;
+}
+
+static const struct eth_ops qe_uec_eth_ops = {
+	.start		= qe_uec_start,
+	.send		= qe_uec_send,
+	.recv		= qe_uec_recv,
+	.free_pkt	= qe_uec_free_pkt,
+	.stop		= qe_uec_stop,
+	.write_hwaddr	= qe_uec_set_hwaddr,
+};
+
+static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
+				   int *threads_num_ret)
+{
+	int	num_threads_numerica;
+
+	switch (threads_num) {
+	case UEC_NUM_OF_THREADS_1:
+		num_threads_numerica = 1;
+		break;
+	case UEC_NUM_OF_THREADS_2:
+		num_threads_numerica = 2;
+		break;
+	case UEC_NUM_OF_THREADS_4:
+		num_threads_numerica = 4;
+		break;
+	case UEC_NUM_OF_THREADS_6:
+		num_threads_numerica = 6;
+		break;
+	case UEC_NUM_OF_THREADS_8:
+		num_threads_numerica = 8;
+		break;
+	default:
+		printf("%s: Bad number of threads value.",
+		       __func__);
+		return -EINVAL;
+	}
+
+	*threads_num_ret = num_threads_numerica;
+
+	return 0;
+}
+
+static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
+{
+	struct uec_inf	*uec_info;
+	u32		end_bd;
+	u8		bmrx = 0;
+	int		i;
+
+	uec_info = uec->uec_info;
+
+	/* Alloc global Tx parameter RAM page */
+	uec->tx_glbl_pram_offset =
+		qe_muram_alloc(sizeof(struct uec_tx_global_pram),
+			       UEC_TX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
+				qe_muram_addr(uec->tx_glbl_pram_offset);
+
+	/* Zero the global Tx prameter RAM */
+	memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
+
+	/* Init global Tx parameter RAM */
+
+	/* TEMODER, RMON statistics disable, one Tx queue */
+	out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
+
+	/* SQPTR */
+	uec->send_q_mem_reg_offset =
+		qe_muram_alloc(sizeof(struct uec_send_queue_qd),
+			       UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
+	uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
+				qe_muram_addr(uec->send_q_mem_reg_offset);
+	out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
+
+	/* Setup the table with TxBDs ring */
+	end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
+					 * SIZEOFBD;
+	out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
+		 (u32)(uec->p_tx_bd_ring));
+	out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
+		 end_bd);
+
+	/* Scheduler Base Pointer, we have only one Tx queue, no need it */
+	out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
+
+	/* TxRMON Base Pointer, TxRMON disable, we don't need it */
+	out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
+
+	/* TSTATE, global snooping, big endian, the CSB bus selected */
+	bmrx = BMR_INIT_VALUE;
+	out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
+
+	/* IPH_Offset */
+	for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
+		out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
+
+	/* VTAG table */
+	for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
+		out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
+
+	/* TQPTR */
+	uec->thread_dat_tx_offset =
+		qe_muram_alloc(num_threads_tx *
+			       sizeof(struct uec_thread_data_tx) +
+			       32 * (num_threads_tx == 1),
+			       UEC_THREAD_DATA_ALIGNMENT);
+
+	uec->p_thread_data_tx = (struct uec_thread_data_tx *)
+				qe_muram_addr(uec->thread_dat_tx_offset);
+	out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
+}
+
+static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
+{
+	u8	bmrx = 0;
+	int	i;
+	struct uec_82xx_add_filtering_pram	*p_af_pram;
+
+	/* Allocate global Rx parameter RAM page */
+	uec->rx_glbl_pram_offset =
+		qe_muram_alloc(sizeof(struct uec_rx_global_pram),
+			       UEC_RX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
+				qe_muram_addr(uec->rx_glbl_pram_offset);
+
+	/* Zero Global Rx parameter RAM */
+	memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
+
+	/* Init global Rx parameter RAM */
+	/*
+	 * REMODER, Extended feature mode disable, VLAN disable,
+	 * LossLess flow control disable, Receive firmware statisic disable,
+	 * Extended address parsing mode disable, One Rx queues,
+	 * Dynamic maximum/minimum frame length disable, IP checksum check
+	 * disable, IP address alignment disable
+	 */
+	out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
+
+	/* RQPTR */
+	uec->thread_dat_rx_offset =
+		qe_muram_alloc(num_threads_rx *
+			       sizeof(struct uec_thread_data_rx),
+			       UEC_THREAD_DATA_ALIGNMENT);
+	uec->p_thread_data_rx = (struct uec_thread_data_rx *)
+				qe_muram_addr(uec->thread_dat_rx_offset);
+	out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
+
+	/* Type_or_Len */
+	out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
+
+	/* RxRMON base pointer, we don't need it */
+	out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
+
+	/* IntCoalescingPTR, we don't need it, no interrupt */
+	out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
+
+	/* RSTATE, global snooping, big endian, the CSB bus selected */
+	bmrx = BMR_INIT_VALUE;
+	out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
+
+	/* MRBLR */
+	out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
+
+	/* RBDQPTR */
+	uec->rx_bd_qs_tbl_offset =
+		qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
+			       sizeof(struct uec_rx_pref_bds),
+			       UEC_RX_BD_QUEUES_ALIGNMENT);
+	uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
+				qe_muram_addr(uec->rx_bd_qs_tbl_offset);
+
+	/* Zero it */
+	memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
+	       sizeof(struct uec_rx_pref_bds));
+	out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
+	out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
+		 (u32)uec->p_rx_bd_ring);
+
+	/* MFLR */
+	out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
+	/* MINFLR */
+	out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
+	/* MAXD1 */
+	out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
+	/* MAXD2 */
+	out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
+	/* ECAM_PTR */
+	out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
+	/* L2QT */
+	out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
+	/* L3QT */
+	for (i = 0; i < 8; i++)
+		out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
+
+	/* VLAN_TYPE */
+	out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
+	/* TCI */
+	out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
+
+	/* Clear PQ2 style address filtering hash table */
+	p_af_pram = (struct uec_82xx_add_filtering_pram *)
+			uec->p_rx_glbl_pram->addressfiltering;
+
+	p_af_pram->iaddr_h = 0;
+	p_af_pram->iaddr_l = 0;
+	p_af_pram->gaddr_h = 0;
+	p_af_pram->gaddr_l = 0;
+}
+
+static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
+					int thread_tx, int thread_rx)
+{
+	struct uec_init_cmd_pram		*p_init_enet_param;
+	u32				init_enet_param_offset;
+	struct uec_inf			*uec_info;
+	struct ucc_fast_inf			*uf_info;
+	int				i;
+	int				snum;
+	u32				off;
+	u32				entry_val;
+	u32				command;
+	u32				cecr_subblock;
+
+	uec_info = uec->uec_info;
+	uf_info = &uec_info->uf_info;
+
+	/* Allocate init enet command parameter */
+	uec->init_enet_param_offset =
+		qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
+	init_enet_param_offset = uec->init_enet_param_offset;
+	uec->p_init_enet_param = (struct uec_init_cmd_pram *)
+				qe_muram_addr(uec->init_enet_param_offset);
+
+	/* Zero init enet command struct */
+	memset((void *)uec->p_init_enet_param, 0,
+	       sizeof(struct uec_init_cmd_pram));
+
+	/* Init the command struct */
+	p_init_enet_param = uec->p_init_enet_param;
+	p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
+	p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
+	p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
+	p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
+	p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
+	p_init_enet_param->largestexternallookupkeysize = 0;
+
+	p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
+					 << ENET_INIT_PARAM_RGF_SHIFT;
+	p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
+					 << ENET_INIT_PARAM_TGF_SHIFT;
+
+	/* Init Rx global parameter pointer */
+	p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
+						 (u32)uec_info->risc_rx;
+
+	/* Init Rx threads */
+	for (i = 0; i < (thread_rx + 1); i++) {
+		snum = qe_get_snum();
+		if (snum < 0) {
+			printf("%s can not get snum\n", __func__);
+			return -ENOMEM;
+		}
+
+		if (i == 0) {
+			off = 0;
+		} else {
+			off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
+					     UEC_THREAD_RX_PRAM_ALIGNMENT);
+		}
+
+		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
+				 off | (u32)uec_info->risc_rx;
+		p_init_enet_param->rxthread[i] = entry_val;
+	}
+
+	/* Init Tx global parameter pointer */
+	p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
+					 (u32)uec_info->risc_tx;
+
+	/* Init Tx threads */
+	for (i = 0; i < thread_tx; i++) {
+		snum = qe_get_snum();
+		if (snum  < 0)	{
+			printf("%s can not get snum\n", __func__);
+			return -ENOMEM;
+		}
+
+		off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
+				     UEC_THREAD_TX_PRAM_ALIGNMENT);
+
+		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
+				 off | (u32)uec_info->risc_tx;
+		p_init_enet_param->txthread[i] = entry_val;
+	}
+
+	__asm__ __volatile__("sync");
+
+	/* Issue QE command */
+	command = QE_INIT_TX_RX;
+	cecr_subblock =	ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
+	qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
+		     init_enet_param_offset);
+
+	return 0;
+}
+
+static int uec_startup(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv *uec = priv->uec;
+	struct uec_inf			*uec_info;
+	struct ucc_fast_inf			*uf_info;
+	struct ucc_fast_priv		*uccf;
+	ucc_fast_t			*uf_regs;
+	uec_t				*uec_regs;
+	int				num_threads_tx;
+	int				num_threads_rx;
+	u32				utbipar;
+	u32				length;
+	u32				align;
+	struct buffer_descriptor	*bd;
+	u8				*buf;
+	int				i;
+
+	uec_info = uec->uec_info;
+	uf_info = &uec_info->uf_info;
+
+	/* Check if Rx BD ring len is illegal */
+	if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
+	    uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT) {
+		printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	/* Check if Tx BD ring len is illegal */
+	if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
+		printf("%s: Tx BD ring length must not be smaller than 2.\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	/* Check if MRBLR is illegal */
+	if (MAX_RXBUF_LEN == 0 || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
+		printf("%s: max rx buffer length must be mutliple of 128.\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	/* Both Rx and Tx are stopped */
+	uec->grace_stopped_rx = 1;
+	uec->grace_stopped_tx = 1;
+
+	/* Init UCC fast */
+	if (ucc_fast_init(uf_info, &uccf)) {
+		printf("%s: failed to init ucc fast\n", __func__);
+		return -ENOMEM;
+	}
+
+	/* Save uccf */
+	uec->uccf = uccf;
+
+	/* Convert the Tx threads number */
+	if (uec_convert_threads_num(uec_info->num_threads_tx,
+				    &num_threads_tx))
+		return -EINVAL;
+
+	/* Convert the Rx threads number */
+	if (uec_convert_threads_num(uec_info->num_threads_rx,
+				    &num_threads_rx))
+		return -EINVAL;
+
+	uf_regs = uccf->uf_regs;
+
+	/* UEC register is following UCC fast registers */
+	uec_regs = (uec_t *)(&uf_regs->ucc_eth);
+
+	/* Save the UEC register pointer to UEC private struct */
+	uec->uec_regs = uec_regs;
+
+	/* Init UPSMR, enable hardware statistics (UCC) */
+	out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
+
+	/* Init MACCFG1, flow control disable, disable Tx and Rx */
+	out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
+
+	/* Init MACCFG2, length check, MAC PAD and CRC enable */
+	out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
+
+	/* Setup UTBIPAR */
+	utbipar = in_be32(&uec_regs->utbipar);
+	utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
+
+	/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
+	 * This frees up the remaining SMI addresses for use.
+	 */
+	utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
+	out_be32(&uec_regs->utbipar, utbipar);
+
+	/* Allocate Tx BDs */
+	length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
+		 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
+		 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
+	if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
+	    UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
+		length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
+
+	align = UEC_TX_BD_RING_ALIGNMENT;
+	uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
+	if (uec->tx_bd_ring_offset != 0)
+		uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
+					   & ~(align - 1));
+
+	/* Zero all of Tx BDs */
+	memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
+
+	/* Allocate Rx BDs */
+	length = uec_info->rx_bd_ring_len * SIZEOFBD;
+	align = UEC_RX_BD_RING_ALIGNMENT;
+	uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
+	if (uec->rx_bd_ring_offset != 0)
+		uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
+					   & ~(align - 1));
+
+	/* Zero all of Rx BDs */
+	memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
+
+	/* Allocate Rx buffer */
+	length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
+	align = UEC_RX_DATA_BUF_ALIGNMENT;
+	uec->rx_buf_offset = (u32)malloc(length + align);
+	if (uec->rx_buf_offset != 0)
+		uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
+				       & ~(align - 1));
+
+	/* Zero all of the Rx buffer */
+	memset((void *)(uec->rx_buf_offset), 0, length + align);
+
+	/* Init TxBD ring */
+	bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
+	uec->tx_bd = bd;
+
+	for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
+		BD_DATA_CLEAR(bd);
+		BD_STATUS_SET(bd, 0);
+		BD_LENGTH_SET(bd, 0);
+		bd++;
+	}
+	BD_STATUS_SET((--bd), TX_BD_WRAP);
+
+	/* Init RxBD ring */
+	bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
+	uec->rx_bd = bd;
+	buf = uec->p_rx_buf;
+	for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
+		BD_DATA_SET(bd, buf);
+		BD_LENGTH_SET(bd, 0);
+		BD_STATUS_SET(bd, RX_BD_EMPTY);
+		buf += MAX_RXBUF_LEN;
+		bd++;
+	}
+	BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
+
+	/* Init global Tx parameter RAM */
+	uec_init_tx_parameter(uec, num_threads_tx);
+
+	/* Init global Rx parameter RAM */
+	uec_init_rx_parameter(uec, num_threads_rx);
+
+	/* Init ethernet Tx and Rx parameter command */
+	if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
+					 num_threads_rx)) {
+		printf("%s issue init enet cmd failed\n", __func__);
+		return -ENOMEM;
+	}
+	return 0;
+}
+
+/* Convert a string to a QE clock source enum
+ *
+ * This function takes a string, typically from a property in the device
+ * tree, and returns the corresponding "enum qe_clock" value.
+ */
+enum qe_clock qe_clock_source(const char *source)
+{
+	unsigned int i;
+
+	if (strcasecmp(source, "none") == 0)
+		return QE_CLK_NONE;
+
+	if (strncasecmp(source, "brg", 3) == 0) {
+		i = simple_strtoul(source + 3, NULL, 10);
+		if (i >= 1 && i <= 16)
+			return (QE_BRG1 - 1) + i;
+		else
+			return QE_CLK_DUMMY;
+	}
+
+	if (strncasecmp(source, "clk", 3) == 0) {
+		i = simple_strtoul(source + 3, NULL, 10);
+		if (i >= 1 && i <= 24)
+			return (QE_CLK1 - 1) + i;
+		else
+			return QE_CLK_DUMMY;
+	}
+
+	return QE_CLK_DUMMY;
+}
+
+static void qe_uec_set_eth_type(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct uec_priv		*uec = priv->uec;
+	struct uec_inf *uec_info  = uec->uec_info;
+	struct ucc_fast_inf *uf_info = &uec_info->uf_info;
+
+	switch (uec_info->enet_interface_type) {
+	case PHY_INTERFACE_MODE_GMII:
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_TBI:
+	case PHY_INTERFACE_MODE_RTBI:
+	case PHY_INTERFACE_MODE_SGMII:
+		uf_info->eth_type = GIGA_ETH;
+		break;
+	default:
+		uf_info->eth_type = FAST_ETH;
+		break;
+	}
+}
+
+static int qe_uec_set_uec_info(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct uec_priv *uec = priv->uec;
+	struct uec_inf *uec_info;
+	struct ucc_fast_inf *uf_info;
+	const char *s;
+	int ret;
+	u32 val;
+
+	uec_info = (struct uec_inf *)malloc(sizeof(struct uec_inf));
+	if (!uec_info)
+		return -ENOMEM;
+
+	uf_info = &uec_info->uf_info;
+
+	ret = dev_read_u32(dev, "cell-index", &val);
+	if (ret) {
+		ret = dev_read_u32(dev, "device-id", &val);
+		if (ret) {
+			pr_err("no cell-index nor device-id found!");
+			goto out;
+		}
+	}
+
+	uf_info->ucc_num = val - 1;
+	if (uf_info->ucc_num < 0 || uf_info->ucc_num > 7) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	ret = dev_read_string_index(dev, "rx-clock-name", 0, &s);
+	if (!ret) {
+		uf_info->rx_clock = qe_clock_source(s);
+		if (uf_info->rx_clock < QE_CLK_NONE ||
+		    uf_info->rx_clock > QE_CLK24) {
+			pr_err("invalid rx-clock-name property\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	} else {
+		ret = dev_read_u32(dev, "rx-clock", &val);
+		if (ret) {
+			/*
+			 * If both rx-clock-name and rx-clock are missing,
+			 * we want to tell people to use rx-clock-name.
+			 */
+			pr_err("missing rx-clock-name property\n");
+			goto out;
+		}
+		if (val < QE_CLK_NONE || val > QE_CLK24) {
+			pr_err("invalid rx-clock property\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		uf_info->rx_clock = val;
+	}
+
+	ret = dev_read_string_index(dev, "tx-clock-name", 0, &s);
+	if (!ret) {
+		uf_info->tx_clock = qe_clock_source(s);
+		if (uf_info->tx_clock < QE_CLK_NONE ||
+		    uf_info->tx_clock > QE_CLK24) {
+			pr_err("invalid tx-clock-name property\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	} else {
+		ret = dev_read_u32(dev, "tx-clock", &val);
+		if (ret) {
+			pr_err("missing tx-clock-name property\n");
+			goto out;
+		}
+		if (val < QE_CLK_NONE || val > QE_CLK24) {
+			pr_err("invalid tx-clock property\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		uf_info->tx_clock = val;
+	}
+
+	uec_info->num_threads_tx = UEC_NUM_OF_THREADS_1;
+	uec_info->num_threads_rx = UEC_NUM_OF_THREADS_1;
+	uec_info->risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
+	uec_info->risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
+	uec_info->tx_bd_ring_len = 16;
+	uec_info->rx_bd_ring_len = 16;
+#if (MAX_QE_RISC == 4)
+	uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
+	uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
+#endif
+
+	uec_info->enet_interface_type = pdata->phy_interface;
+
+	uec->uec_info = uec_info;
+	qe_uec_set_eth_type(dev);
+
+	return 0;
+out:
+	free(uec_info);
+	return ret;
+}
+
+static int qe_uec_probe(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct uec_priv		*uec;
+	int ret;
+
+	/* Allocate the UEC private struct */
+	uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
+	if (!uec)
+		return -ENOMEM;
+
+	memset(uec, 0, sizeof(struct uec_priv));
+	priv->uec = uec;
+	uec->uec_regs = (uec_t *)pdata->iobase;
+
+	/* setup uec info struct */
+	ret = qe_uec_set_uec_info(dev);
+	if (ret) {
+		free(uec);
+		return ret;
+	}
+
+	ret = uec_startup(dev);
+	if (ret) {
+		free(uec->uec_info);
+		free(uec);
+		return ret;
+	}
+
+	priv->phydev = dm_eth_phy_connect(dev);
+	return 0;
+}
+
+/*
+ * Remove the driver from an interface:
+ * - free up allocated memory
+ */
+static int qe_uec_remove(struct udevice *dev)
+{
+	struct qe_uec_priv *priv = dev_get_priv(dev);
+
+	free(priv->uec);
+	return 0;
+}
+
+static int qe_uec_ofdata_to_platdata(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	const char *phy_mode;
+
+	pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+
+	pdata->phy_interface = -1;
+	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+			       "phy-connection-type", NULL);
+	if (phy_mode)
+		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+	if (pdata->phy_interface == -1) {
+		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id qe_uec_ids[] = {
+	{ .compatible = QE_UEC_DRIVER_NAME },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_qe_uec) = {
+	.name	= QE_UEC_DRIVER_NAME,
+	.id	= UCLASS_ETH,
+	.of_match = qe_uec_ids,
+	.ofdata_to_platdata = qe_uec_ofdata_to_platdata,
+	.probe	= qe_uec_probe,
+	.remove = qe_uec_remove,
+	.ops	= &qe_uec_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct qe_uec_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};

diff --git a/drivers/net/qe/dm_qe_uec.h b/drivers/net/qe/dm_qe_uec.h
new file mode 100644
index 0000000..690093c
--- /dev/null
+++ b/drivers/net/qe/dm_qe_uec.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * QE UEC ethernet controller driver
+ *
+ * based on drivers/qe/uec.c from NXP
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ */
+
+#ifndef _DM_QE_UEC_H
+#define _DM_QE_UEC_H
+
+#define qe_uec_dbg(dev, fmt, args...)	debug("%s:" fmt, dev->name, ##args)
+
+#include "uec.h"
+
+/* QE UEC private structure */
+struct qe_uec_priv {
+	struct uec_priv *uec;
+	struct phy_device *phydev;
+};
+#endif

diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c
new file mode 100644
index 0000000..02ce08e
--- /dev/null
+++ b/drivers/net/qe/dm_qe_uec_phy.c

@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * QE UEC ethernet phy controller driver
+ *
+ * based on phy parts of drivers/qe/uec.c and drivers/qe/uec_phy.c
+ * from NXP
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+
+#include "dm_qe_uec.h"
+
+struct qe_uec_mdio_priv {
+	struct ucc_mii_mng *base;
+};
+
+static int
+qe_uec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
+	struct ucc_mii_mng *regs = priv->base;
+	u32 tmp_reg;
+	u16 value;
+
+	debug("%s: regs: %p addr: %x devad: %x reg: %x\n", __func__, regs,
+	      addr, devad, reg);
+	/* Setting up the MII management Address Register */
+	tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
+	out_be32(&regs->miimadd, tmp_reg);
+
+	/* clear MII management command cycle */
+	out_be32(&regs->miimcom, 0);
+	sync();
+
+	/* Perform an MII management read cycle */
+	out_be32(&regs->miimcom, MIIMCOM_READ_CYCLE);
+
+	/* Wait till MII management write is complete */
+	while ((in_be32(&regs->miimind)) &
+	       (MIIMIND_NOT_VALID | MIIMIND_BUSY))
+		;
+
+	/* Read MII management status  */
+	value = (u16)in_be32(&regs->miimstat);
+	if (value == 0xffff)
+		return -EINVAL;
+
+	return value;
+};
+
+static int
+qe_uec_mdio_write(struct udevice *dev, int addr, int devad, int reg,
+		  u16 value)
+{
+	struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
+	struct ucc_mii_mng *regs = priv->base;
+	u32 tmp_reg;
+
+	debug("%s: regs: %p addr: %x devad: %x reg: %x val: %x\n", __func__,
+	      regs, addr, devad, reg, value);
+
+	/* Stop the MII management read cycle */
+	out_be32(&regs->miimcom, 0);
+	/* Setting up the MII management Address Register */
+	tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
+	out_be32(&regs->miimadd, tmp_reg);
+
+	/* Setting up the MII management Control Register with the value */
+	out_be32(&regs->miimcon, (u32)value);
+	sync();
+
+	/* Wait till MII management write is complete */
+	while ((in_be32(&regs->miimind)) & MIIMIND_BUSY)
+		;
+
+	return 0;
+};
+
+static const struct mdio_ops qe_uec_mdio_ops = {
+	.read = qe_uec_mdio_read,
+	.write = qe_uec_mdio_write,
+};
+
+static int qe_uec_mdio_probe(struct udevice *dev)
+{
+	struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
+	fdt_size_t base;
+	ofnode node;
+	u32 num = 0;
+	int ret = -ENODEV;
+
+	priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
+	base = (fdt_size_t)priv->base;
+
+	/*
+	 * idea from linux:
+	 * drivers/net/ethernet/freescale/fsl_pq_mdio.c
+	 *
+	 * Find the UCC node that controls the given MDIO node
+	 *
+	 * For some reason, the QE MDIO nodes are not children of the UCC
+	 * devices that control them.  Therefore, we need to scan all UCC
+	 * nodes looking for the one that encompases the given MDIO node.
+	 * We do this by comparing physical addresses.  The 'start' and
+	 * 'end' addresses of the MDIO node are passed, and the correct
+	 * UCC node will cover the entire address range.
+	 */
+	node = ofnode_by_compatible(ofnode_null(), "ucc_geth");
+	while (ofnode_valid(node)) {
+		fdt_size_t size;
+		fdt_addr_t addr;
+
+		addr = ofnode_get_addr_index(node, 0);
+		ret = ofnode_get_addr_size_index(node, 0, &size);
+
+		if (addr == FDT_ADDR_T_NONE) {
+			node = ofnode_by_compatible(node, "ucc_geth");
+			continue;
+		}
+
+		/* check if priv->base in start end */
+		if (base > addr && base < (addr + size)) {
+			ret = ofnode_read_u32(node, "cell-index", &num);
+			if (ret)
+				ret = ofnode_read_u32(node, "device-id",
+						      &num);
+			break;
+		}
+		node = ofnode_by_compatible(node, "ucc_geth");
+	}
+
+	if (ret) {
+		printf("%s: no cell-index nor device-id found!", __func__);
+		return ret;
+	}
+
+	/* Setup MII master clock source */
+	qe_set_mii_clk_src(num - 1);
+
+	return 0;
+}
+
+static const struct udevice_id qe_uec_mdio_ids[] = {
+	{ .compatible = "fsl,ucc-mdio" },
+	{ }
+};
+
+U_BOOT_DRIVER(mvmdio) = {
+	.name			= "qe_uec_mdio",
+	.id			= UCLASS_MDIO,
+	.of_match		= qe_uec_mdio_ids,
+	.probe			= qe_uec_mdio_probe,
+	.ops			= &qe_uec_mdio_ops,
+	.priv_auto_alloc_size	= sizeof(struct qe_uec_mdio_priv),
+};

diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c
new file mode 100644
index 0000000..306f1ea
--- /dev/null
+++ b/drivers/net/qe/uccf.c

@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <linux/immap_qe.h>
+#include "uccf.h"
+#include <fsl_qe.h>
+
+void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
+{
+	out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+}
+
+u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
+{
+	switch (ucc_num) {
+	case 0:
+		return QE_CR_SUBBLOCK_UCCFAST1;
+	case 1:
+		return QE_CR_SUBBLOCK_UCCFAST2;
+	case 2:
+		return QE_CR_SUBBLOCK_UCCFAST3;
+	case 3:
+		return QE_CR_SUBBLOCK_UCCFAST4;
+	case 4:
+		return QE_CR_SUBBLOCK_UCCFAST5;
+	case 5:
+		return QE_CR_SUBBLOCK_UCCFAST6;
+	case 6:
+		return QE_CR_SUBBLOCK_UCCFAST7;
+	case 7:
+		return QE_CR_SUBBLOCK_UCCFAST8;
+	default:
+		return QE_CR_SUBBLOCK_INVALID;
+	}
+}
+
+static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
+			       u8 *reg_num, u8 *shift)
+{
+	switch (ucc_num) {
+	case 0:	/* UCC1 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr1;
+		*reg_num = 1;
+		*shift  = 16;
+		break;
+	case 2:	/* UCC3 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr1;
+		*reg_num = 1;
+		*shift  = 0;
+		break;
+	case 4:	/* UCC5 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr2;
+		*reg_num = 2;
+		*shift  = 16;
+		break;
+	case 6:	/* UCC7 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr2;
+		*reg_num = 2;
+		*shift  = 0;
+		break;
+	case 1:	/* UCC2 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr3;
+		*reg_num = 3;
+		*shift  = 16;
+		break;
+	case 3:	/* UCC4 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr3;
+		*reg_num = 3;
+		*shift  = 0;
+		break;
+	case 5:	/* UCC6 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr4;
+		*reg_num = 4;
+		*shift  = 16;
+		break;
+	case 7:	/* UCC8 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr4;
+		*reg_num = 4;
+		*shift  = 0;
+		break;
+	default:
+		break;
+	}
+}
+
+static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
+{
+	u32	*p_cmxucr = NULL;
+	u8	reg_num = 0;
+	u8	shift = 0;
+	u32	clk_bits;
+	u32	clk_mask;
+	int	source = -1;
+
+	/* check if the UCC number is in range. */
+	if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
+		return -EINVAL;
+
+	if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
+		printf("%s: bad comm mode type passed\n", __func__);
+		return -EINVAL;
+	}
+
+	ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
+
+	switch (reg_num) {
+	case 1:
+		switch (clock) {
+		case QE_BRG1:
+			source = 1;
+			break;
+		case QE_BRG2:
+			source = 2;
+			break;
+		case QE_BRG7:
+			source = 3;
+			break;
+		case QE_BRG8:
+			source = 4;
+			break;
+		case QE_CLK9:
+			source = 5;
+			break;
+		case QE_CLK10:
+			source = 6;
+			break;
+		case QE_CLK11:
+			source = 7;
+			break;
+		case QE_CLK12:
+			source = 8;
+			break;
+		case QE_CLK15:
+			source = 9;
+			break;
+		case QE_CLK16:
+			source = 10;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	case 2:
+		switch (clock) {
+		case QE_BRG5:
+			source = 1;
+			break;
+		case QE_BRG6:
+			source = 2;
+			break;
+		case QE_BRG7:
+			source = 3;
+			break;
+		case QE_BRG8:
+			source = 4;
+			break;
+		case QE_CLK13:
+			source = 5;
+			break;
+		case QE_CLK14:
+			source = 6;
+			break;
+		case QE_CLK19:
+			source = 7;
+			break;
+		case QE_CLK20:
+			source = 8;
+			break;
+		case QE_CLK15:
+			source = 9;
+			break;
+		case QE_CLK16:
+			source = 10;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	case 3:
+		switch (clock) {
+		case QE_BRG9:
+			source = 1;
+			break;
+		case QE_BRG10:
+			source = 2;
+			break;
+		case QE_BRG15:
+			source = 3;
+			break;
+		case QE_BRG16:
+			source = 4;
+			break;
+		case QE_CLK3:
+			source = 5;
+			break;
+		case QE_CLK4:
+			source = 6;
+			break;
+		case QE_CLK17:
+			source = 7;
+			break;
+		case QE_CLK18:
+			source = 8;
+			break;
+		case QE_CLK7:
+			source = 9;
+			break;
+		case QE_CLK8:
+			source = 10;
+			break;
+		case QE_CLK16:
+			source = 11;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	case 4:
+		switch (clock) {
+		case QE_BRG13:
+			source = 1;
+			break;
+		case QE_BRG14:
+			source = 2;
+			break;
+		case QE_BRG15:
+			source = 3;
+			break;
+		case QE_BRG16:
+			source = 4;
+			break;
+		case QE_CLK5:
+			source = 5;
+			break;
+		case QE_CLK6:
+			source = 6;
+			break;
+		case QE_CLK21:
+			source = 7;
+			break;
+		case QE_CLK22:
+			source = 8;
+			break;
+		case QE_CLK7:
+			source = 9;
+			break;
+		case QE_CLK8:
+			source = 10;
+			break;
+		case QE_CLK16:
+			source = 11;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	default:
+		source = -1;
+		break;
+	}
+
+	if (source == -1) {
+		printf("%s: Bad combination of clock and UCC\n", __func__);
+		return -ENOENT;
+	}
+
+	clk_bits = (u32)source;
+	clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
+	if (mode == COMM_DIR_RX) {
+		clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
+		clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
+	}
+	clk_bits <<= shift;
+	clk_mask <<= shift;
+
+	out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
+
+	return 0;
+}
+
+static uint ucc_get_reg_baseaddr(int ucc_num)
+{
+	uint base = 0;
+
+	/* check if the UCC number is in range */
+	if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
+		printf("%s: the UCC num not in ranges\n", __func__);
+		return 0;
+	}
+
+	switch (ucc_num) {
+	case 0:
+		base = 0x00002000;
+		break;
+	case 1:
+		base = 0x00003000;
+		break;
+	case 2:
+		base = 0x00002200;
+		break;
+	case 3:
+		base = 0x00003200;
+		break;
+	case 4:
+		base = 0x00002400;
+		break;
+	case 5:
+		base = 0x00003400;
+		break;
+	case 6:
+		base = 0x00002600;
+		break;
+	case 7:
+		base = 0x00003600;
+		break;
+	default:
+		break;
+	}
+
+	base = (uint)qe_immr + base;
+	return base;
+}
+
+void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
+{
+	ucc_fast_t	*uf_regs;
+	u32		gumr;
+
+	uf_regs = uccf->uf_regs;
+
+	/* Enable reception and/or transmission on this UCC. */
+	gumr = in_be32(&uf_regs->gumr);
+	if (mode & COMM_DIR_TX) {
+		gumr |= UCC_FAST_GUMR_ENT;
+		uccf->enabled_tx = 1;
+	}
+	if (mode & COMM_DIR_RX) {
+		gumr |= UCC_FAST_GUMR_ENR;
+		uccf->enabled_rx = 1;
+	}
+	out_be32(&uf_regs->gumr, gumr);
+}
+
+void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
+{
+	ucc_fast_t	*uf_regs;
+	u32		gumr;
+
+	uf_regs = uccf->uf_regs;
+
+	/* Disable reception and/or transmission on this UCC. */
+	gumr = in_be32(&uf_regs->gumr);
+	if (mode & COMM_DIR_TX) {
+		gumr &= ~UCC_FAST_GUMR_ENT;
+		uccf->enabled_tx = 0;
+	}
+	if (mode & COMM_DIR_RX) {
+		gumr &= ~UCC_FAST_GUMR_ENR;
+		uccf->enabled_rx = 0;
+	}
+	out_be32(&uf_regs->gumr, gumr);
+}
+
+int ucc_fast_init(struct ucc_fast_inf *uf_info,
+		  struct ucc_fast_priv **uccf_ret)
+{
+	struct ucc_fast_priv	*uccf;
+	ucc_fast_t		*uf_regs;
+
+	if (!uf_info)
+		return -EINVAL;
+
+	if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+		printf("%s: Illagal UCC number!\n", __func__);
+		return -EINVAL;
+	}
+
+	uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
+	if (!uccf) {
+		printf("%s: No memory for UCC fast data structure!\n",
+		       __func__);
+		return -ENOMEM;
+	}
+	memset(uccf, 0, sizeof(struct ucc_fast_priv));
+
+	/* Save fast UCC structure */
+	uccf->uf_info	= uf_info;
+	uccf->uf_regs	= (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
+
+	if (!uccf->uf_regs) {
+		printf("%s: No memory map for UCC fast controller!\n",
+		       __func__);
+		return -ENOMEM;
+	}
+
+	uccf->enabled_tx	= 0;
+	uccf->enabled_rx	= 0;
+
+	uf_regs			= uccf->uf_regs;
+	uccf->p_ucce		= (u32 *)&uf_regs->ucce;
+	uccf->p_uccm		= (u32 *)&uf_regs->uccm;
+
+	/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
+	out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
+				 | UCC_GUEMR_MODE_FAST_TX);
+
+	/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
+	out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
+
+	/* Set the Giga ethernet VFIFO stuff */
+	if (uf_info->eth_type == GIGA_ETH) {
+		/* Allocate memory for Tx Virtual Fifo */
+		uccf->ucc_fast_tx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* Allocate memory for Rx Virtual Fifo */
+		uccf->ucc_fast_rx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
+			       UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* utfb, urfb are offsets from MURAM base */
+		out_be32(&uf_regs->utfb,
+			 uccf->ucc_fast_tx_virtual_fifo_base_offset);
+		out_be32(&uf_regs->urfb,
+			 uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+		/* Set Virtual Fifo registers */
+		out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
+		out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
+		out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
+		out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
+		out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
+		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
+	}
+
+	/* Set the Fast ethernet VFIFO stuff */
+	if (uf_info->eth_type == FAST_ETH) {
+		/* Allocate memory for Tx Virtual Fifo */
+		uccf->ucc_fast_tx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_UTFS_INIT,
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* Allocate memory for Rx Virtual Fifo */
+		uccf->ucc_fast_rx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_URFS_INIT +
+				 UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
+				UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* utfb, urfb are offsets from MURAM base */
+		out_be32(&uf_regs->utfb,
+			 uccf->ucc_fast_tx_virtual_fifo_base_offset);
+		out_be32(&uf_regs->urfb,
+			 uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+		/* Set Virtual Fifo registers */
+		out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
+		out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
+		out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
+		out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
+		out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
+		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
+	}
+
+	/* Rx clock routing */
+	if (uf_info->rx_clock != QE_CLK_NONE) {
+		if (ucc_set_clk_src(uf_info->ucc_num,
+				    uf_info->rx_clock, COMM_DIR_RX)) {
+			printf("%s: Illegal value for parameter 'RxClock'.\n",
+			       __func__);
+			return -EINVAL;
+		}
+	}
+
+	/* Tx clock routing */
+	if (uf_info->tx_clock != QE_CLK_NONE) {
+		if (ucc_set_clk_src(uf_info->ucc_num,
+				    uf_info->tx_clock, COMM_DIR_TX)) {
+			printf("%s: Illegal value for parameter 'TxClock'.\n",
+			       __func__);
+			return -EINVAL;
+		}
+	}
+
+	/* Clear interrupt mask register to disable all of interrupts */
+	out_be32(&uf_regs->uccm, 0x0);
+
+	/* Writing '1' to clear all of envents */
+	out_be32(&uf_regs->ucce, 0xffffffff);
+
+	*uccf_ret = uccf;
+	return 0;
+}

diff --git a/drivers/net/qe/uccf.h b/drivers/net/qe/uccf.h
new file mode 100644
index 0000000..99f8458
--- /dev/null
+++ b/drivers/net/qe/uccf.h

@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#ifndef __UCCF_H__
+#define __UCCF_H__
+
+#include "common.h"
+#include "linux/immap_qe.h"
+#include <fsl_qe.h>
+
+/* Fast or Giga ethernet */
+enum enet_type {
+	FAST_ETH,
+	GIGA_ETH,
+};
+
+/* General UCC Extended Mode Register */
+#define UCC_GUEMR_MODE_MASK_RX		0x02
+#define UCC_GUEMR_MODE_MASK_TX		0x01
+#define UCC_GUEMR_MODE_FAST_RX		0x02
+#define UCC_GUEMR_MODE_FAST_TX		0x01
+#define UCC_GUEMR_MODE_SLOW_RX		0x00
+#define UCC_GUEMR_MODE_SLOW_TX		0x00
+/* Bit 3 must be set 1 */
+#define UCC_GUEMR_SET_RESERVED3		0x10
+
+/* General UCC FAST Mode Register */
+#define UCC_FAST_GUMR_TCI		0x20000000
+#define UCC_FAST_GUMR_TRX		0x10000000
+#define UCC_FAST_GUMR_TTX		0x08000000
+#define UCC_FAST_GUMR_CDP		0x04000000
+#define UCC_FAST_GUMR_CTSP		0x02000000
+#define UCC_FAST_GUMR_CDS		0x01000000
+#define UCC_FAST_GUMR_CTSS		0x00800000
+#define UCC_FAST_GUMR_TXSY		0x00020000
+#define UCC_FAST_GUMR_RSYN		0x00010000
+#define UCC_FAST_GUMR_RTSM		0x00002000
+#define UCC_FAST_GUMR_REVD		0x00000400
+#define UCC_FAST_GUMR_ENR		0x00000020
+#define UCC_FAST_GUMR_ENT		0x00000010
+
+/* GUMR [MODE] bit maps */
+#define UCC_FAST_GUMR_HDLC		0x00000000
+#define UCC_FAST_GUMR_QMC		0x00000002
+#define UCC_FAST_GUMR_UART		0x00000004
+#define UCC_FAST_GUMR_BISYNC		0x00000008
+#define UCC_FAST_GUMR_ATM		0x0000000a
+#define UCC_FAST_GUMR_ETH		0x0000000c
+
+/* Transmit On Demand (UTORD) */
+#define UCC_SLOW_TOD			0x8000
+#define UCC_FAST_TOD			0x8000
+
+/* Fast Ethernet (10/100 Mbps) */
+/* Rx virtual FIFO size */
+#define UCC_GETH_URFS_INIT		512
+/* 1/2 urfs */
+#define UCC_GETH_URFET_INIT		256
+/* 3/4 urfs */
+#define UCC_GETH_URFSET_INIT		384
+/* Tx virtual FIFO size */
+#define UCC_GETH_UTFS_INIT		512
+/* 1/2 utfs */
+#define UCC_GETH_UTFET_INIT		256
+#define UCC_GETH_UTFTT_INIT		128
+
+/* Gigabit Ethernet (1000 Mbps) */
+/* Rx virtual FIFO size */
+#define UCC_GETH_URFS_GIGA_INIT		4096/*2048*/
+/* 1/2 urfs */
+#define UCC_GETH_URFET_GIGA_INIT	2048/*1024*/
+/* 3/4 urfs */
+#define UCC_GETH_URFSET_GIGA_INIT	3072/*1536*/
+/* Tx virtual FIFO size */
+#define UCC_GETH_UTFS_GIGA_INIT		8192/*2048*/
+/* 1/2 utfs */
+#define UCC_GETH_UTFET_GIGA_INIT	4096/*1024*/
+#define UCC_GETH_UTFTT_GIGA_INIT	0x400/*0x40*/
+
+/* UCC fast alignment */
+#define UCC_FAST_RX_ALIGN			4
+#define UCC_FAST_MRBLR_ALIGNMENT		4
+#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
+
+/* Sizes */
+#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD	8
+
+/* UCC fast structure. */
+struct ucc_fast_inf {
+	int		ucc_num;
+	qe_clock_e	rx_clock;
+	qe_clock_e	tx_clock;
+	enum enet_type	eth_type;
+};
+
+struct ucc_fast_priv {
+	struct ucc_fast_inf	*uf_info;
+	ucc_fast_t	*uf_regs; /* a pointer to memory map of UCC regs */
+	u32		*p_ucce; /* a pointer to the event register */
+	u32		*p_uccm; /* a pointer to the mask register */
+	int		enabled_tx; /* whether UCC is enabled for Tx (ENT) */
+	int		enabled_rx; /* whether UCC is enabled for Rx (ENR) */
+	u32		ucc_fast_tx_virtual_fifo_base_offset;
+	u32		ucc_fast_rx_virtual_fifo_base_offset;
+};
+
+void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
+u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
+void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
+void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
+int ucc_fast_init(struct ucc_fast_inf *uf_info,
+		  struct ucc_fast_priv **uccf_ret);
+
+#endif /* __UCCF_H__ */

diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h
new file mode 100644
index 0000000..7cd4b87
--- /dev/null
+++ b/drivers/net/qe/uec.h

@@ -0,0 +1,693 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#ifndef __UEC_H__
+#define __UEC_H__
+
+#include "uccf.h"
+#include <fsl_qe.h>
+#include <phy.h>
+
+#define MAX_TX_THREADS				8
+#define MAX_RX_THREADS				8
+#define MAX_TX_QUEUES				8
+#define MAX_RX_QUEUES				8
+#define MAX_PREFETCHED_BDS			4
+#define MAX_IPH_OFFSET_ENTRY			8
+#define MAX_ENET_INIT_PARAM_ENTRIES_RX		9
+#define MAX_ENET_INIT_PARAM_ENTRIES_TX		8
+
+/* UEC UPSMR (Protocol Specific Mode Register)
+ */
+#define UPSMR_ECM	0x04000000 /* Enable CAM Miss               */
+#define UPSMR_HSE	0x02000000 /* Hardware Statistics Enable    */
+#define UPSMR_PRO	0x00400000 /* Promiscuous                   */
+#define UPSMR_CAP	0x00200000 /* CAM polarity                  */
+#define UPSMR_RSH	0x00100000 /* Receive Short Frames          */
+#define UPSMR_RPM	0x00080000 /* Reduced Pin Mode interfaces   */
+#define UPSMR_R10M	0x00040000 /* RGMII/RMII 10 Mode            */
+#define UPSMR_RLPB	0x00020000 /* RMII Loopback Mode            */
+#define UPSMR_TBIM	0x00010000 /* Ten-bit Interface Mode        */
+#define UPSMR_RMM	0x00001000 /* RMII/RGMII Mode               */
+#define UPSMR_CAM	0x00000400 /* CAM Address Matching          */
+#define UPSMR_BRO	0x00000200 /* Broadcast Address             */
+#define UPSMR_RES1	0x00002000 /* Reserved feild - must be 1    */
+#define UPSMR_SGMM	0x00000020 /* SGMII mode    */
+
+#define UPSMR_INIT_VALUE	(UPSMR_HSE | UPSMR_RES1)
+
+/* UEC MACCFG1 (MAC Configuration 1 Register)
+ */
+#define MACCFG1_FLOW_RX			0x00000020 /* Flow Control Rx */
+#define MACCFG1_FLOW_TX			0x00000010 /* Flow Control Tx */
+#define MACCFG1_ENABLE_SYNCHED_RX	0x00000008 /* Enable Rx Sync  */
+#define MACCFG1_ENABLE_RX		0x00000004 /* Enable Rx       */
+#define MACCFG1_ENABLE_SYNCHED_TX	0x00000002 /* Enable Tx Sync  */
+#define MACCFG1_ENABLE_TX		0x00000001 /* Enable Tx       */
+
+#define MACCFG1_INIT_VALUE		(0)
+
+/* UEC MACCFG2 (MAC Configuration 2 Register)
+ */
+#define MACCFG2_PREL				0x00007000
+#define MACCFG2_PREL_SHIFT			(31 - 19)
+#define MACCFG2_PREL_MASK			0x0000f000
+#define MACCFG2_SRP				0x00000080
+#define MACCFG2_STP				0x00000040
+#define MACCFG2_RESERVED_1			0x00000020 /* must be set  */
+#define MACCFG2_LC				0x00000010 /* Length Check */
+#define MACCFG2_MPE				0x00000008
+#define MACCFG2_FDX				0x00000001 /* Full Duplex  */
+#define MACCFG2_FDX_MASK			0x00000001
+#define MACCFG2_PAD_CRC				0x00000004
+#define MACCFG2_CRC_EN				0x00000002
+#define MACCFG2_PAD_AND_CRC_MODE_NONE		0x00000000
+#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY	0x00000002
+#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC	0x00000004
+#define MACCFG2_INTERFACE_MODE_NIBBLE		0x00000100
+#define MACCFG2_INTERFACE_MODE_BYTE		0x00000200
+#define MACCFG2_INTERFACE_MODE_MASK		0x00000300
+
+#define MACCFG2_INIT_VALUE	(MACCFG2_PREL | MACCFG2_RESERVED_1 | \
+				 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
+
+/* UEC Event Register */
+#define UCCE_MPD				0x80000000
+#define UCCE_SCAR				0x40000000
+#define UCCE_GRA				0x20000000
+#define UCCE_CBPR				0x10000000
+#define UCCE_BSY				0x08000000
+#define UCCE_RXC				0x04000000
+#define UCCE_TXC				0x02000000
+#define UCCE_TXE				0x01000000
+#define UCCE_TXB7				0x00800000
+#define UCCE_TXB6				0x00400000
+#define UCCE_TXB5				0x00200000
+#define UCCE_TXB4				0x00100000
+#define UCCE_TXB3				0x00080000
+#define UCCE_TXB2				0x00040000
+#define UCCE_TXB1				0x00020000
+#define UCCE_TXB0				0x00010000
+#define UCCE_RXB7				0x00008000
+#define UCCE_RXB6				0x00004000
+#define UCCE_RXB5				0x00002000
+#define UCCE_RXB4				0x00001000
+#define UCCE_RXB3				0x00000800
+#define UCCE_RXB2				0x00000400
+#define UCCE_RXB1				0x00000200
+#define UCCE_RXB0				0x00000100
+#define UCCE_RXF7				0x00000080
+#define UCCE_RXF6				0x00000040
+#define UCCE_RXF5				0x00000020
+#define UCCE_RXF4				0x00000010
+#define UCCE_RXF3				0x00000008
+#define UCCE_RXF2				0x00000004
+#define UCCE_RXF1				0x00000002
+#define UCCE_RXF0				0x00000001
+
+#define UCCE_TXB	(UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
+			 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
+#define UCCE_RXB	(UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
+			 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
+#define UCCE_RXF	(UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
+			 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
+#define UCCE_OTHER	(UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
+			 UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
+
+/* UEC TEMODR Register */
+#define TEMODER_SCHEDULER_ENABLE		0x2000
+#define TEMODER_IP_CHECKSUM_GENERATE		0x0400
+#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1	0x0200
+#define TEMODER_RMON_STATISTICS			0x0100
+#define TEMODER_NUM_OF_QUEUES_SHIFT		(15 - 15)
+
+#define TEMODER_INIT_VALUE			0xc000
+
+/* UEC REMODR Register */
+#define REMODER_RX_RMON_STATISTICS_ENABLE	0x00001000
+#define REMODER_RX_EXTENDED_FEATURES		0x80000000
+#define REMODER_VLAN_OPERATION_TAGGED_SHIFT	(31 - 9)
+#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT	(31 - 10)
+#define REMODER_RX_QOS_MODE_SHIFT		(31 - 15)
+#define REMODER_RMON_STATISTICS			0x00001000
+#define REMODER_RX_EXTENDED_FILTERING		0x00000800
+#define REMODER_NUM_OF_QUEUES_SHIFT		(31 - 23)
+#define REMODER_DYNAMIC_MAX_FRAME_LENGTH	0x00000008
+#define REMODER_DYNAMIC_MIN_FRAME_LENGTH	0x00000004
+#define REMODER_IP_CHECKSUM_CHECK		0x00000002
+#define REMODER_IP_ADDRESS_ALIGNMENT		0x00000001
+
+#define REMODER_INIT_VALUE			0
+
+/* BMRx - Bus Mode Register */
+#define BMR_GLB					0x20
+#define BMR_BO_BE				0x10
+#define BMR_DTB_SECONDARY_BUS			0x02
+#define BMR_BDB_SECONDARY_BUS			0x01
+
+#define BMR_SHIFT				24
+#define BMR_INIT_VALUE				(BMR_GLB | BMR_BO_BE)
+
+/* UEC UCCS (Ethernet Status Register)
+ */
+#define UCCS_BPR				0x02
+#define UCCS_PAU				0x02
+#define UCCS_MPD				0x01
+
+/* UEC MIIMCFG (MII Management Configuration Register)
+ */
+#define MIIMCFG_RESET_MANAGEMENT		0x80000000
+#define MIIMCFG_NO_PREAMBLE			0x00000010
+#define MIIMCFG_CLOCK_DIVIDE_SHIFT		(31 - 31)
+#define MIIMCFG_CLOCK_DIVIDE_MASK		0x0000000f
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4	0x00000001
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6	0x00000002
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8	0x00000003
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10	0x00000004
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14	0x00000005
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20	0x00000006
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28	0x00000007
+
+#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE	\
+	MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
+
+/* UEC MIIMCOM (MII Management Command Register)
+ */
+#define MIIMCOM_SCAN_CYCLE			0x00000002 /* Scan cycle */
+#define MIIMCOM_READ_CYCLE			0x00000001 /* Read cycle */
+
+/* UEC MIIMADD (MII Management Address Register)
+ */
+#define MIIMADD_PHY_ADDRESS_SHIFT		(31 - 23)
+#define MIIMADD_PHY_REGISTER_SHIFT		(31 - 31)
+
+/* UEC MIIMCON (MII Management Control Register)
+ */
+#define MIIMCON_PHY_CONTROL_SHIFT		(31 - 31)
+#define MIIMCON_PHY_STATUS_SHIFT		(31 - 31)
+
+/* UEC MIIMIND (MII Management Indicator Register)
+ */
+#define MIIMIND_NOT_VALID			0x00000004
+#define MIIMIND_SCAN				0x00000002
+#define MIIMIND_BUSY				0x00000001
+
+/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
+ */
+#define UTBIPAR_PHY_ADDRESS_SHIFT		(31 - 31)
+#define UTBIPAR_PHY_ADDRESS_MASK		0x0000001f
+
+/* UEC UESCR (Ethernet Statistics Control Register)
+ */
+#define UESCR_AUTOZ				0x8000
+#define UESCR_CLRCNT				0x4000
+#define UESCR_MAXCOV_SHIFT			(15 -  7)
+#define UESCR_SCOV_SHIFT			(15 - 15)
+
+/****** Tx data struct collection ******/
+/* Tx thread data, each Tx thread has one this struct. */
+struct uec_thread_data_tx {
+	u8   res0[136];
+} __packed;
+
+/* Tx thread parameter, each Tx thread has one this struct. */
+struct uec_thread_tx_pram {
+	u8   res0[64];
+} __packed;
+
+/* Send queue queue-descriptor, each Tx queue has one this QD */
+struct uec_send_queue_qd {
+	u32    bd_ring_base; /* pointer to BD ring base address */
+	u8     res0[0x8];
+	u32    last_bd_completed_address; /* last entry in BD ring */
+	u8     res1[0x30];
+} __packed;
+
+/* Send queue memory region */
+struct uec_send_queue_mem_region {
+	struct uec_send_queue_qd   sqqd[MAX_TX_QUEUES];
+} __packed;
+
+/* Scheduler struct */
+struct uec_scheduler {
+	u16  cpucount0;        /* CPU packet counter */
+	u16  cpucount1;        /* CPU packet counter */
+	u16  cecount0;         /* QE  packet counter */
+	u16  cecount1;         /* QE  packet counter */
+	u16  cpucount2;        /* CPU packet counter */
+	u16  cpucount3;        /* CPU packet counter */
+	u16  cecount2;         /* QE  packet counter */
+	u16  cecount3;         /* QE  packet counter */
+	u16  cpucount4;        /* CPU packet counter */
+	u16  cpucount5;        /* CPU packet counter */
+	u16  cecount4;         /* QE  packet counter */
+	u16  cecount5;         /* QE  packet counter */
+	u16  cpucount6;        /* CPU packet counter */
+	u16  cpucount7;        /* CPU packet counter */
+	u16  cecount6;         /* QE  packet counter */
+	u16  cecount7;         /* QE  packet counter */
+	u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
+	u32  rtsrshadow;       /* temporary variable handled by QE */
+	u32  time;             /* temporary variable handled by QE */
+	u32  ttl;              /* temporary variable handled by QE */
+	u32  mblinterval;      /* max burst length interval        */
+	u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
+	u8   fracsiz;
+	u8   res0[1];
+	u8   strictpriorityq;  /* Strict Priority Mask register */
+	u8   txasap;           /* Transmit ASAP register        */
+	u8   extrabw;          /* Extra BandWidth register      */
+	u8   oldwfqmask;       /* temporary variable handled by QE */
+	u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
+	u32  minw;             /* temporary variable handled by QE */
+	u8   res1[0x70 - 0x64];
+} __packed;
+
+/* Tx firmware counters */
+struct uec_tx_firmware_statistics_pram {
+	u32  sicoltx;            /* single collision */
+	u32  mulcoltx;           /* multiple collision */
+	u32  latecoltxfr;        /* late collision */
+	u32  frabortduecol;      /* frames aborted due to tx collision */
+	u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
+	u32  carriersenseertx;   /* carrier sense error */
+	u32  frtxok;             /* frames transmitted OK */
+	u32  txfrexcessivedefer;
+	u32  txpkts256;          /* total packets(including bad) 256~511 B */
+	u32  txpkts512;          /* total packets(including bad) 512~1023B */
+	u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
+	u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
+} __packed;
+
+/* Tx global parameter table */
+struct uec_tx_global_pram {
+	u16  temoder;
+	u8   res0[0x38 - 0x02];
+	u32  sqptr;
+	u32  schedulerbasepointer;
+	u32  txrmonbaseptr;
+	u32  tstate;
+	u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
+	u32  vtagtable[0x8];
+	u32  tqptr;
+	u8   res2[0x80 - 0x74];
+} __packed;
+
+/****** Rx data struct collection ******/
+/* Rx thread data, each Rx thread has one this struct. */
+struct uec_thread_data_rx {
+	u8   res0[40];
+} __packed;
+
+/* Rx thread parameter, each Rx thread has one this struct. */
+struct uec_thread_rx_pram {
+	u8   res0[128];
+} __packed;
+
+/* Rx firmware counters */
+struct uec_rx_firmware_statistics_pram {
+	u32   frrxfcser;         /* frames with crc error */
+	u32   fraligner;         /* frames with alignment error */
+	u32   inrangelenrxer;    /* in range length error */
+	u32   outrangelenrxer;   /* out of range length error */
+	u32   frtoolong;         /* frame too long */
+	u32   runt;              /* runt */
+	u32   verylongevent;     /* very long event */
+	u32   symbolerror;       /* symbol error */
+	u32   dropbsy;           /* drop because of BD not ready */
+	u8    res0[0x8];
+	u32   mismatchdrop;      /* drop because of MAC filtering */
+	u32   underpkts;         /* total frames less than 64 octets */
+	u32   pkts256;           /* total frames(including bad)256~511 B */
+	u32   pkts512;           /* total frames(including bad)512~1023 B */
+	u32   pkts1024;          /* total frames(including bad)1024~1518 B */
+	u32   pktsjumbo;         /* total frames(including bad) >1024 B */
+	u32   frlossinmacer;
+	u32   pausefr;           /* pause frames */
+	u8    res1[0x4];
+	u32   removevlan;
+	u32   replacevlan;
+	u32   insertvlan;
+} __packed;
+
+/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
+struct uec_rx_interrupt_coalescing_entry {
+	u32   maxvalue;
+	u32   counter;
+} __packed;
+
+struct uec_rx_interrupt_coalescing_table {
+	struct uec_rx_interrupt_coalescing_entry   entry[MAX_RX_QUEUES];
+} __packed;
+
+/* RxBD queue entry, each Rx queue has one this entry. */
+struct uec_rx_bd_queues_entry {
+	u32   bdbaseptr;         /* BD base pointer          */
+	u32   bdptr;             /* BD pointer               */
+	u32   externalbdbaseptr; /* external BD base pointer */
+	u32   externalbdptr;     /* external BD pointer      */
+} __packed;
+
+/* Rx global parameter table */
+struct uec_rx_global_pram {
+	u32  remoder;             /* ethernet mode reg. */
+	u32  rqptr;               /* base pointer to the Rx Queues */
+	u32  res0[0x1];
+	u8   res1[0x20 - 0xc];
+	u16  typeorlen;
+	u8   res2[0x1];
+	u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
+	u32  rxrmonbaseptr;       /* Rx RMON statistics base */
+	u8   res3[0x30 - 0x28];
+	u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
+	u8   res4[0x36 - 0x34];
+	u8   rstate;
+	u8   res5[0x46 - 0x37];
+	u16  mrblr;               /* max receive buffer length reg. */
+	u32  rbdqptr;             /* RxBD parameter table description */
+	u16  mflr;                /* max frame length reg. */
+	u16  minflr;              /* min frame length reg. */
+	u16  maxd1;               /* max dma1 length reg. */
+	u16  maxd2;               /* max dma2 length reg. */
+	u32  ecamptr;             /* external CAM address */
+	u32  l2qt;                /* VLAN priority mapping table. */
+	u32  l3qt[0x8];           /* IP   priority mapping table. */
+	u16  vlantype;            /* vlan type */
+	u16  vlantci;             /* default vlan tci */
+	u8   addressfiltering[64];/* address filtering data structure */
+	u32  exf_global_param;      /* extended filtering global parameters */
+	u8   res6[0x100 - 0xc4];    /* Initialize to zero */
+} __packed;
+
+#define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
+
+/****** UEC common ******/
+/* UCC statistics - hardware counters */
+struct uec_hardware_statistics {
+	u32 tx64;
+	u32 tx127;
+	u32 tx255;
+	u32 rx64;
+	u32 rx127;
+	u32 rx255;
+	u32 txok;
+	u16 txcf;
+	u32 tmca;
+	u32 tbca;
+	u32 rxfok;
+	u32 rxbok;
+	u32 rbyt;
+	u32 rmca;
+	u32 rbca;
+} __packed;
+
+/* InitEnet command parameter */
+struct uec_init_cmd_pram {
+	u8   resinit0;
+	u8   resinit1;
+	u8   resinit2;
+	u8   resinit3;
+	u16  resinit4;
+	u8   res1[0x1];
+	u8   largestexternallookupkeysize;
+	u32  rgftgfrxglobal;
+	u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
+	u8   res2[0x38 - 0x30];
+	u32  txglobal;				   /* tx global  */
+	u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
+	u8   res3[0x1];
+} __packed;
+
+#define ENET_INIT_PARAM_RGF_SHIFT		(32 - 4)
+#define ENET_INIT_PARAM_TGF_SHIFT		(32 - 8)
+
+#define ENET_INIT_PARAM_RISC_MASK		0x0000003f
+#define ENET_INIT_PARAM_PTR_MASK		0x00ffffc0
+#define ENET_INIT_PARAM_SNUM_MASK		0xff000000
+#define ENET_INIT_PARAM_SNUM_SHIFT		24
+
+#define ENET_INIT_PARAM_MAGIC_RES_INIT0		0x06
+#define ENET_INIT_PARAM_MAGIC_RES_INIT1		0x30
+#define ENET_INIT_PARAM_MAGIC_RES_INIT2		0xff
+#define ENET_INIT_PARAM_MAGIC_RES_INIT3		0x00
+#define ENET_INIT_PARAM_MAGIC_RES_INIT4		0x0400
+
+/* structure representing 82xx Address Filtering Enet Address in PRAM */
+struct uec_82xx_enet_addr {
+	u8   res1[0x2];
+	u16  h;       /* address (MSB) */
+	u16  m;       /* address       */
+	u16  l;       /* address (LSB) */
+} __packed;
+
+/* structure representing 82xx Address Filtering PRAM */
+struct uec_82xx_add_filtering_pram {
+	u32  iaddr_h;        /* individual address filter, high */
+	u32  iaddr_l;        /* individual address filter, low  */
+	u32  gaddr_h;        /* group address filter, high      */
+	u32  gaddr_l;        /* group address filter, low       */
+	struct uec_82xx_enet_addr    taddr;
+	struct uec_82xx_enet_addr    paddr[4];
+	u8                         res0[0x40 - 0x38];
+} __packed;
+
+/* Buffer Descriptor */
+struct buffer_descriptor {
+	u16 status;
+	u16 len;
+	u32 data;
+} __packed;
+
+#define	SIZEOFBD	sizeof(struct buffer_descriptor)
+
+/* Common BD flags */
+#define BD_WRAP			0x2000
+#define BD_INT			0x1000
+#define BD_LAST			0x0800
+#define BD_CLEAN		0x3000
+
+/* TxBD status flags */
+#define TX_BD_READY		0x8000
+#define TX_BD_PADCRC		0x4000
+#define TX_BD_WRAP		BD_WRAP
+#define TX_BD_INT		BD_INT
+#define TX_BD_LAST		BD_LAST
+#define TX_BD_TXCRC		0x0400
+#define TX_BD_DEF		0x0200
+#define TX_BD_PP			0x0100
+#define TX_BD_LC			0x0080
+#define TX_BD_RL			0x0040
+#define TX_BD_RC			0x003C
+#define TX_BD_UNDERRUN		0x0002
+#define TX_BD_TRUNC		0x0001
+
+#define TX_BD_ERROR		(TX_BD_UNDERRUN | TX_BD_TRUNC)
+
+/* RxBD status flags */
+#define RX_BD_EMPTY		0x8000
+#define RX_BD_OWNER		0x4000
+#define RX_BD_WRAP		BD_WRAP
+#define RX_BD_INT		BD_INT
+#define RX_BD_LAST		BD_LAST
+#define RX_BD_FIRST		0x0400
+#define RX_BD_CMR		0x0200
+#define RX_BD_MISS		0x0100
+#define RX_BD_BCAST		0x0080
+#define RX_BD_MCAST		0x0040
+#define RX_BD_LG			0x0020
+#define RX_BD_NO			0x0010
+#define RX_BD_SHORT		0x0008
+#define RX_BD_CRCERR		0x0004
+#define RX_BD_OVERRUN		0x0002
+#define RX_BD_IPCH		0x0001
+
+#define RX_BD_ERROR		(RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
+				 RX_BD_CRCERR | RX_BD_OVERRUN)
+
+/* BD access macros */
+#define BD_STATUS(_bd)		(in_be16(&((_bd)->status)))
+#define BD_STATUS_SET(_bd, _v)	(out_be16(&((_bd)->status), _v))
+#define BD_LENGTH(_bd)		(in_be16(&((_bd)->len)))
+#define BD_LENGTH_SET(_bd, _v)	(out_be16(&((_bd)->len), _v))
+#define BD_DATA_CLEAR(_bd)	(out_be32(&((_bd)->data), 0))
+#define BD_DATA(_bd)		((u8 *)(((_bd)->data)))
+#define BD_DATA_SET(_bd, _data)	(out_be32(&((_bd)->data), (u32)_data))
+#define BD_ADVANCE(_bd, _status, _base)	\
+	(((_status) & BD_WRAP) ? (_bd) = \
+	 ((struct buffer_descriptor *)(_base)) : ++(_bd))
+
+/* Rx Prefetched BDs */
+struct uec_rx_pref_bds {
+	struct buffer_descriptor   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
+} __packed;
+
+/* Alignments */
+#define UEC_RX_GLOBAL_PRAM_ALIGNMENT				64
+#define UEC_TX_GLOBAL_PRAM_ALIGNMENT				64
+#define UEC_THREAD_RX_PRAM_ALIGNMENT				128
+#define UEC_THREAD_TX_PRAM_ALIGNMENT				64
+#define UEC_THREAD_DATA_ALIGNMENT				256
+#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT		32
+#define UEC_SCHEDULER_ALIGNMENT					4
+#define UEC_TX_STATISTICS_ALIGNMENT				4
+#define UEC_RX_STATISTICS_ALIGNMENT				4
+#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT			4
+#define UEC_RX_BD_QUEUES_ALIGNMENT				8
+#define UEC_RX_PREFETCHED_BDS_ALIGNMENT				128
+#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT	4
+#define UEC_RX_BD_RING_ALIGNMENT				32
+#define UEC_TX_BD_RING_ALIGNMENT				32
+#define UEC_MRBLR_ALIGNMENT					128
+#define UEC_RX_BD_RING_SIZE_ALIGNMENT				4
+#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT			32
+#define UEC_RX_DATA_BUF_ALIGNMENT				64
+
+#define UEC_VLAN_PRIORITY_MAX					8
+#define UEC_IP_PRIORITY_MAX					64
+#define UEC_TX_VTAG_TABLE_ENTRY_MAX				8
+#define UEC_RX_BD_RING_SIZE_MIN					8
+#define UEC_TX_BD_RING_SIZE_MIN					2
+
+/* TBI / MII Set Register */
+enum enet_tbi_mii_reg {
+	ENET_TBI_MII_CR        = 0x00,
+	ENET_TBI_MII_SR        = 0x01,
+	ENET_TBI_MII_ANA       = 0x04,
+	ENET_TBI_MII_ANLPBPA   = 0x05,
+	ENET_TBI_MII_ANEX      = 0x06,
+	ENET_TBI_MII_ANNPT     = 0x07,
+	ENET_TBI_MII_ANLPANP   = 0x08,
+	ENET_TBI_MII_EXST      = 0x0F,
+	ENET_TBI_MII_JD        = 0x10,
+	ENET_TBI_MII_TBICON    = 0x11
+};
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE	0x0100
+#define TBIANA_SYMMETRIC_PAUSE	0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+#define TBIANA_SETTINGS ( \
+		TBIANA_ASYMMETRIC_PAUSE \
+		| TBIANA_SYMMETRIC_PAUSE \
+		| TBIANA_FULL_DUPLEX \
+		)
+
+#define TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+/* UEC number of threads */
+enum uec_num_of_threads {
+	UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
+	UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
+	UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
+	UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
+	UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
+};
+
+/* UEC initialization info struct */
+#define STD_UEC_INFO(num) \
+{			\
+	.uf_info		= {	\
+		.ucc_num	= CONFIG_SYS_UEC##num##_UCC_NUM,\
+		.rx_clock	= CONFIG_SYS_UEC##num##_RX_CLK,	\
+		.tx_clock	= CONFIG_SYS_UEC##num##_TX_CLK,	\
+		.eth_type	= CONFIG_SYS_UEC##num##_ETH_TYPE,\
+	},	\
+	.num_threads_tx		= UEC_NUM_OF_THREADS_1,	\
+	.num_threads_rx		= UEC_NUM_OF_THREADS_1,	\
+	.risc_tx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
+	.risc_rx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
+	.tx_bd_ring_len		= 16,	\
+	.rx_bd_ring_len		= 16,	\
+	.phy_address		= CONFIG_SYS_UEC##num##_PHY_ADDR, \
+	.enet_interface_type	= CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
+	.speed			= CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+}
+
+struct uec_inf {
+	struct ucc_fast_inf		uf_info;
+	enum uec_num_of_threads		num_threads_tx;
+	enum uec_num_of_threads		num_threads_rx;
+	unsigned int			risc_tx;
+	unsigned int			risc_rx;
+	u16				rx_bd_ring_len;
+	u16				tx_bd_ring_len;
+	u8				phy_address;
+	phy_interface_t			enet_interface_type;
+	int				speed;
+};
+
+/* UEC driver initialized info */
+#define MAX_RXBUF_LEN			1536
+#define MAX_FRAME_LEN			1518
+#define MIN_FRAME_LEN			64
+#define MAX_DMA1_LEN			1520
+#define MAX_DMA2_LEN			1520
+
+/* UEC driver private struct */
+struct uec_priv {
+	struct uec_inf			*uec_info;
+	struct ucc_fast_priv		*uccf;
+	struct eth_device		*dev;
+	uec_t				*uec_regs;
+	/* enet init command parameter */
+	struct uec_init_cmd_pram		*p_init_enet_param;
+	u32				init_enet_param_offset;
+	/* Rx and Tx parameter */
+	struct uec_rx_global_pram		*p_rx_glbl_pram;
+	u32				rx_glbl_pram_offset;
+	struct uec_tx_global_pram		*p_tx_glbl_pram;
+	u32				tx_glbl_pram_offset;
+	struct uec_send_queue_mem_region	*p_send_q_mem_reg;
+	u32				send_q_mem_reg_offset;
+	struct uec_thread_data_tx		*p_thread_data_tx;
+	u32				thread_dat_tx_offset;
+	struct uec_thread_data_rx		*p_thread_data_rx;
+	u32				thread_dat_rx_offset;
+	struct uec_rx_bd_queues_entry	*p_rx_bd_qs_tbl;
+	u32				rx_bd_qs_tbl_offset;
+	/* BDs specific */
+	u8				*p_tx_bd_ring;
+	u32				tx_bd_ring_offset;
+	u8				*p_rx_bd_ring;
+	u32				rx_bd_ring_offset;
+	u8				*p_rx_buf;
+	u32				rx_buf_offset;
+	struct buffer_descriptor	*tx_bd;
+	struct buffer_descriptor	*rx_bd;
+	/* Status */
+	int				mac_tx_enabled;
+	int				mac_rx_enabled;
+	int				grace_stopped_tx;
+	int				grace_stopped_rx;
+	int				the_first_run;
+#if !defined(COFIG_DM)
+	/* PHY specific */
+	struct uec_mii_info		*mii_info;
+	int				oldspeed;
+	int				oldduplex;
+	int				oldlink;
+#endif
+};
+
+int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
+int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
+int uec_standard_init(struct bd_info *bis);
+#endif /* __UEC_H__ */

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 886f53e..98883cd 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c

@@ -438,8 +438,6 @@
 
 	writel(mask, eth->iobase + RAVB_REG_ECMR);
 
-	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
-
 	return 0;
 }
 

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 546cc6c..1dae81c 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c

@@ -663,7 +663,8 @@
 	return _sun8i_write_hwaddr(priv, pdata->enetaddr);
 }
 
-static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct udevice *dev,
+				  struct emac_eth_dev *priv)
 {
 	int ret;
 
@@ -833,7 +834,7 @@
 
 	priv->mac_reg = (void *)pdata->iobase;
 
-	ret = sun8i_emac_board_setup(priv);
+	ret = sun8i_emac_board_setup(dev, priv);
 	if (ret)
 		return ret;
 
@@ -854,7 +855,7 @@
 	.stop                   = sun8i_emac_eth_stop,
 };
 
-static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
+static int sun8i_get_ephy_nodes(struct udevice *dev, struct emac_eth_dev *priv)
 {
 	int emac_node, ephy_node, ret, ephy_handle;
 
@@ -986,7 +987,7 @@
 	}
 
 	if (priv->variant == H3_EMAC) {
-		ret = sun8i_get_ephy_nodes(priv);
+		ret = sun8i_get_ephy_nodes(dev, priv);
 		if (ret)
 			return ret;
 	}

diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index df18ecc..8e66ce2 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c

@@ -505,7 +505,8 @@
 	return 0;
 }
 
-static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct udevice *dev,
+				  struct emac_eth_dev *priv)
 {
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
@@ -576,7 +577,7 @@
 		return ret;
 	}
 
-	ret = sunxi_emac_board_setup(priv);
+	ret = sunxi_emac_board_setup(dev, priv);
 	if (ret)
 		return ret;
 

diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index d6fefe5..1c11257 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c

@@ -856,8 +856,14 @@
 		ret = phy_set_supported(phydev, slave->data->max_speed);
 		if (ret)
 			return ret;
+#if CONFIG_IS_ENABLED(DM_ETH)
 		dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
 			slave->slave_num + 1, slave->data->max_speed);
+#else
+		log_debug("%s: Port %u speed forced to %uMbit\n",
+			  priv->dev->name, slave->slave_num + 1,
+			  slave->data->max_speed);
+#endif
 	}
 	phydev->advertising = phydev->supported;
 

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 5d12e4b..c436b83 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c

@@ -18,6 +18,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <miiphy.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -681,8 +682,15 @@
 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 		tsec_configure_serdes(priv);
 
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
+	if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link")))
+		phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
+	else
+		phydev = dm_eth_phy_connect(priv->dev);
+#else
 	phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
 			     priv->interface);
+#endif
 	if (!phydev)
 		return 0;
 
@@ -793,43 +801,19 @@
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct tsec_private *priv = dev_get_priv(dev);
-	struct tsec_mii_mng __iomem *ext_phyregs_mii;
 	struct ofnode_phandle_args phandle_args;
 	u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
-	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_data *data;
 	const char *phy_mode;
 	fdt_addr_t reg;
 	ofnode parent;
 	int ret;
 
+	data = (struct tsec_data *)dev_get_driver_data(dev);
+
 	pdata->iobase = (phys_addr_t)dev_read_addr(dev);
 	priv->regs = dev_remap_addr(dev);
 
-	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
-				       &phandle_args)) {
-		printf("phy-handle does not exist under tsec %s\n", dev->name);
-		return -ENOENT;
-	} else {
-		int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
-		priv->phyaddr = reg;
-	}
-
-	parent = ofnode_get_parent(phandle_args.node);
-	if (!ofnode_valid(parent)) {
-		printf("No parent node for PHY?\n");
-		return -ENOENT;
-	}
-
-	reg = ofnode_get_addr_index(parent, 0);
-	if (reg == FDT_ADDR_T_NONE) {
-		printf("No 'reg' property of MII for external PHY\n");
-		return -ENOENT;
-	}
-
-	ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
-				      MAP_NOCACHE);
-
 	ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
 					 &phandle_args);
 	if (ret == 0) {
@@ -847,7 +831,7 @@
 			return -ENOENT;
 		}
 
-		priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+		priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
 						  0, MAP_NOCACHE);
 	}
 
@@ -867,12 +851,6 @@
 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 		priv->flags |= TSEC_SGMII;
 
-	mdio_info.regs = ext_phyregs_mii;
-	mdio_info.name = (char *)dev->name;
-	ret = fsl_pq_mdio_init(NULL, &mdio_info);
-	if (ret)
-		return ret;
-
 	/* Reset the MAC */
 	setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 	udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
@@ -905,8 +883,17 @@
 	.mcast = tsec_mcast_addr,
 };
 
+static struct tsec_data etsec2_data = {
+	.mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+	.mdio_regs_off = 0x0,
+};
+
 static const struct udevice_id tsec_ids[] = {
-	{ .compatible = "fsl,etsec2" },
+	{ .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
+	{ .compatible = "gianfar", .data = (ulong)&gianfar_data },
 	{ }
 };
 

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 99d4d85..8af3711 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c

@@ -101,10 +101,10 @@
 
 /* BD descriptors */
 struct axidma_bd {
-	u32 next;	/* Next descriptor pointer */
-	u32 reserved1;
-	u32 phys;	/* Buffer address */
-	u32 reserved2;
+	u32 next_desc;	/* Next descriptor pointer */
+	u32 next_desc_msb;
+	u32 buf_addr;	/* Buffer address */
+	u32 buf_addr_msb;
 	u32 reserved3;
 	u32 reserved4;
 	u32 cntrl;	/* Control */
@@ -182,7 +182,7 @@
 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
 {
 #if defined(CONFIG_PHYS_64BIT)
-	writeq(bd, desc);
+	writeq((unsigned long)bd, desc);
 #else
 	writel((u32)bd, desc);
 #endif
@@ -492,15 +492,19 @@
 
 	/* Setup the BD. */
 	memset(&rx_bd, 0, sizeof(rx_bd));
-	rx_bd.next = (u32)&rx_bd;
-	rx_bd.phys = (u32)&rxframe;
+	rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+	rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
 	rx_bd.cntrl = sizeof(rxframe);
 	/* Flush the last BD so DMA core could see the updates */
-	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+	flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
 
 	/* It is necessary to flush rxframe because if you don't do it
 	 * then cache can contain uninitialized data */
-	flush_cache((u32)&rxframe, sizeof(rxframe));
+	flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
 
 	/* Start the hardware */
 	temp = readl(&priv->dmarx->control);
@@ -534,19 +538,23 @@
 		len = PKTSIZE_ALIGN;
 
 	/* Flush packet to main memory to be trasfered by DMA */
-	flush_cache((u32)ptr, len);
+	flush_cache((phys_addr_t)ptr, len);
 
 	/* Setup Tx BD */
 	memset(&tx_bd, 0, sizeof(tx_bd));
 	/* At the end of the ring, link the last BD back to the top */
-	tx_bd.next = (u32)&tx_bd;
-	tx_bd.phys = (u32)ptr;
+	tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
+	tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
+#if defined(CONFIG_PHYS_64BIT)
+	tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
+	tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
+#endif
 	/* Save len */
 	tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 						XAXIDMA_BD_CTRL_TXEOF_MASK;
 
 	/* Flush the last BD so DMA core could see the updates */
-	flush_cache((u32)&tx_bd, sizeof(tx_bd));
+	flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
 
 	if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 		u32 temp;
@@ -637,16 +645,20 @@
 	/* Setup RxBD */
 	/* Clear the whole buffer and setup it again - all flags are cleared */
 	memset(&rx_bd, 0, sizeof(rx_bd));
-	rx_bd.next = (u32)&rx_bd;
-	rx_bd.phys = (u32)&rxframe;
+	rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+	rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+	rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
 	rx_bd.cntrl = sizeof(rxframe);
 
 	/* Write bd to HW */
-	flush_cache((u32)&rx_bd, sizeof(rx_bd));
+	flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
 
 	/* It is necessary to flush rxframe because if you don't do it
 	 * then cache will contain previous packet */
-	flush_cache((u32)&rxframe, sizeof(rxframe));
+	flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
 
 	/* Rx BD is ready - start again */
 	axienet_dma_write(&rx_bd, &priv->dmarx->tail);
@@ -738,7 +750,7 @@
 		return -EINVAL;
 	}
 	/* RX channel offset is 0x30 */
-	priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
+	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
 
 	priv->phyaddr = -1;
 

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index da4b6fb..8afec8b 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c

@@ -758,6 +758,9 @@
 
 	if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
 					&phandle_args)) {
+		fdt_addr_t addr;
+		ofnode parent;
+
 		debug("phy-handle does exist %s\n", dev->name);
 		priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
 							"reg", -1);
@@ -765,6 +768,13 @@
 		priv->max_speed = ofnode_read_u32_default(phandle_args.node,
 							  "max-speed",
 							  SPEED_1000);
+
+		parent = ofnode_get_parent(phandle_args.node);
+		addr = ofnode_get_addr(parent);
+		if (addr != FDT_ADDR_T_NONE) {
+			debug("MDIO bus not found %s\n", dev->name);
+			priv->mdiobase = (struct zynq_gem_regs *)addr;
+		}
 	}
 
 	phy_mode = dev_read_prop(dev, "phy-mode", NULL);

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index d8a6647..eb07d25 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c

@@ -911,8 +911,8 @@
 			   ofnode node)
 {
 	int pci_addr_cells, addr_cells, size_cells;
-	struct bd_info *bd = gd->bd;
 	int cells_per_record;
+	struct bd_info *bd;
 	const u32 *prop;
 	int max_regions;
 	int len;
@@ -989,6 +989,7 @@
 	}
 
 	/* Add a region for our local memory */
+	bd = gd->bd;
 	if (!bd)
 		return;
 

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 9c77510..d66aa07 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig

@@ -84,6 +84,13 @@
 	help
 	  Support for the Broadcom MIPS BCM6368 USBH PHY.
 
+config BCM_SR_PCIE_PHY
+	bool "Broadcom Stingray PCIe PHY driver"
+	depends on PHY
+	help
+	  Enable this to support the Broadcom Stingray PCIe PHY
+	  If unsure, say N.
+
 config PHY_DA8XX_USB
 	tristate "TI DA8xx USB PHY Driver"
 	depends on PHY && ARCH_DAVINCI
@@ -125,6 +132,12 @@
 	  used by USB2 and USB3 Host controllers available on
 	  STiH407 SoC families.
 
+config PHY_QCOM_IPQ4019_USB
+	tristate "Qualcomm IPQ4019 USB PHY driver"
+	depends on PHY && ARCH_IPQ40XX
+	help
+	  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
+
 config PHY_RCAR_GEN2
 	tristate "Renesas R-Car Gen2 USB PHY"
 	depends on PHY && RCAR_GEN2

diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 74e8d93..8dabefd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile

@@ -9,10 +9,12 @@
 obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
 obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
 obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
+obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
 obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
 obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index f050645..7b9d3ee 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c

@@ -272,13 +272,15 @@
 
 	ret = clk_enable(&usb_phy->clocks);
 	if (ret) {
-		dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
+		dev_err(phy->dev, "failed to enable usb_%ldphy clock\n",
+			phy->id);
 		return ret;
 	}
 
 	ret = reset_deassert(&usb_phy->resets);
 	if (ret) {
-		dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
+		dev_err(phy->dev, "failed to deassert usb_%ldreset reset\n",
+			phy->id);
 		return ret;
 	}
 
@@ -338,13 +340,15 @@
 
 	ret = clk_disable(&usb_phy->clocks);
 	if (ret) {
-		dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
+		dev_err(phy->dev, "failed to disable usb_%ldphy clock\n",
+			phy->id);
 		return ret;
 	}
 
 	ret = reset_assert(&usb_phy->resets);
 	if (ret) {
-		dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
+		dev_err(phy->dev, "failed to assert usb_%ldreset reset\n",
+			phy->id);
 		return ret;
 	}
 

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 27bff27..5e8ce74 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c

@@ -98,14 +98,14 @@
 	chip_cfg->comphy_lanes_count = fdtdec_get_int(blob, node,
 						      "max-lanes", 0);
 	if (chip_cfg->comphy_lanes_count <= 0) {
-		dev_err(&dev->dev, "comphy max lanes is wrong\n");
+		dev_err(dev, "comphy max lanes is wrong\n");
 		return -EINVAL;
 	}
 
 	chip_cfg->comphy_mux_bitcount = fdtdec_get_int(blob, node,
 						       "mux-bitcount", 0);
 	if (chip_cfg->comphy_mux_bitcount <= 0) {
-		dev_err(&dev->dev, "comphy mux bit count is wrong\n");
+		dev_err(dev, "comphy mux bit count is wrong\n");
 		return -EINVAL;
 	}
 
@@ -124,7 +124,7 @@
 	 * compatible node is found
 	 */
 	if (!chip_cfg->ptr_comphy_chip_init) {
-		dev_err(&dev->dev, "comphy: No compatible DT node found\n");
+		dev_err(dev, "comphy: No compatible DT node found\n");
 		return -ENODEV;
 	}
 

diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c
new file mode 100644
index 0000000..36c77c4
--- /dev/null
+++ b/drivers/phy/phy-bcm-sr-pcie.c

@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Broadcom
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
+#define SR_NR_PCIE_PHYS               8
+
+#define PCIE_PIPEMUX_CFG_OFFSET       0x10c
+#define PCIE_PIPEMUX_SELECT_STRAP     GENMASK(3, 0)
+
+#define CDRU_STRAP_DATA_LSW_OFFSET    0x5c
+#define PCIE_PIPEMUX_SHIFT            19
+#define PCIE_PIPEMUX_MASK             GENMASK(3, 0)
+
+/**
+ * struct sr_pcie_phy_core - Stingray PCIe PHY core control
+ *
+ * @dev: pointer to device
+ * @base: base register of PCIe SS
+ * @cdru: CDRU base address
+ * @pipemux: pipemuex strap
+ */
+struct sr_pcie_phy_core {
+	struct udevice *dev;
+	void __iomem *base;
+	void __iomem *cdru;
+	u32 pipemux;
+};
+
+/*
+ * PCIe PIPEMUX lookup table
+ *
+ * Each array index represents a PIPEMUX strap setting
+ * The array element represents a bitmap where a set bit means the PCIe
+ * core and associated serdes has been enabled as RC and is available for use
+ */
+static const u8 pipemux_table[] = {
+	/* PIPEMUX = 0, EP 1x16 */
+	0x00,
+	/* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
+	0x80,
+	/* PIPEMUX = 2, EP 4x4 */
+	0x00,
+	/* PIPEMUX = 3, RC 2x8, cores 0, 7 */
+	0x81,
+	/* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
+	0xc3,
+	/* PIPEMUX = 5, RC 8x2, all 8 cores */
+	0xff,
+	/* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
+	0xcd,
+	/* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
+	0xfd,
+	/* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
+	0xf0,
+	/* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
+	0xc0,
+	/* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
+	0x42,
+	/* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
+	0x3c,
+	/* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
+	0xfc,
+	/* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
+	0x4c,
+};
+
+/*
+ * Return true if the strap setting is valid
+ */
+static bool pipemux_strap_is_valid(u32 pipemux)
+{
+	return !!(pipemux < ARRAY_SIZE(pipemux_table));
+}
+
+/*
+ * Read the PCIe PIPEMUX from strap
+ */
+static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
+{
+	u32 pipemux;
+
+	/*
+	 * Read PIPEMUX configuration register to determine the pipemux setting
+	 *
+	 * In the case when the value indicates using HW strap, fall back to
+	 * use HW strap
+	 */
+	pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
+	pipemux &= PCIE_PIPEMUX_MASK;
+	if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
+		pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET);
+		pipemux >>= PCIE_PIPEMUX_SHIFT;
+		pipemux &= PCIE_PIPEMUX_MASK;
+	}
+
+	return pipemux;
+}
+
+static int sr_pcie_phy_init(struct phy *phy)
+{
+	struct sr_pcie_phy_core *core = dev_get_priv(phy->dev);
+	unsigned int core_idx = phy->id;
+
+	debug("%s %lx\n", __func__, phy->id);
+	/*
+	 * Check whether this PHY is for root complex or not. If yes, return
+	 * zero so the host driver can proceed to enumeration. If not, return
+	 * an error and that will force the host driver to bail out
+	 */
+	if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1))
+		return 0;
+
+	return -ENODEV;
+}
+
+static int sr_pcie_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
+{
+	debug("%s %d\n", __func__, args->args[0]);
+	if (args->args_count && args->args[0] < SR_NR_PCIE_PHYS)
+		phy->id = args->args[0];
+	else
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct phy_ops sr_pcie_phy_ops = {
+	.of_xlate = sr_pcie_phy_xlate,
+	.init = sr_pcie_phy_init,
+};
+
+static int sr_pcie_phy_probe(struct udevice *dev)
+{
+	struct sr_pcie_phy_core *core = dev_get_priv(dev);
+
+	core->dev = dev;
+
+	core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base");
+	core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base");
+	debug("ip base %p\n", core->base);
+	debug("cdru base %p\n", core->cdru);
+
+	/* read the PCIe PIPEMUX strap setting */
+	core->pipemux = pipemux_strap_read(core);
+	if (!pipemux_strap_is_valid(core->pipemux)) {
+		pr_err("invalid PCIe PIPEMUX strap %u\n", core->pipemux);
+		return -EIO;
+	}
+	debug("%s %#x\n", __func__, core->pipemux);
+
+	pr_info("Stingray PCIe PHY driver initialized\n");
+
+	return 0;
+}
+
+static const struct udevice_id sr_pcie_phy_match_table[] = {
+	{ .compatible = "brcm,sr-pcie-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(sr_pcie_phy) = {
+	.name = "sr-pcie-phy",
+	.id = UCLASS_PHY,
+	.probe = sr_pcie_phy_probe,
+	.of_match = sr_pcie_phy_match_table,
+	.ops = &sr_pcie_phy_ops,
+	.platdata_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
+	.priv_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
+};

diff --git a/drivers/phy/phy-qcom-ipq4019-usb.c b/drivers/phy/phy-qcom-ipq4019-usb.c
new file mode 100644
index 0000000..465f0d3
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq4019-usb.c

@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <log.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+struct ipq4019_usb_phy {
+	phys_addr_t			base;
+	struct reset_ctl	por_rst;
+	struct reset_ctl	srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	reset_assert(&phy->por_rst);
+	mdelay(10);
+
+	return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	ipq4019_ss_phy_power_off(_phy);
+
+	reset_deassert(&phy->por_rst);
+
+	return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+	.power_on = ipq4019_ss_phy_power_on,
+	.power_off = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_usb_ss_phy_probe(struct udevice *dev)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+	int ret;
+
+	phy->base = dev_read_addr(dev);
+	if (phy->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_usb_ss_phy_ids[] = {
+	{ .compatible = "qcom,usb-ss-ipq4019-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_ss_phy) = {
+	.name		= "ipq4019-usb-ss-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= ipq4019_usb_ss_phy_ids,
+	.ops		= &ipq4019_usb_ss_phy_ops,
+	.probe		= ipq4019_usb_ss_phy_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	reset_assert(&phy->por_rst);
+	mdelay(10);
+
+	reset_assert(&phy->srif_rst);
+	mdelay(10);
+
+	return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+	ipq4019_hs_phy_power_off(_phy);
+
+	reset_deassert(&phy->srif_rst);
+	mdelay(10);
+
+	reset_deassert(&phy->por_rst);
+
+	return 0;
+}
+
+static struct phy_ops ipq4019_usb_hs_phy_ops = {
+	.power_on = ipq4019_hs_phy_power_on,
+	.power_off = ipq4019_hs_phy_power_off,
+};
+
+static int ipq4019_usb_hs_phy_probe(struct udevice *dev)
+{
+	struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+	int ret;
+
+	phy->base = dev_read_addr(dev);
+	if (phy->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+	if (ret)
+		return ret;
+
+	ret = reset_get_by_name(dev, "srif_rst", &phy->srif_rst);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_usb_hs_phy_ids[] = {
+	{ .compatible = "qcom,usb-hs-ipq4019-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_hs_phy) = {
+	.name		= "ipq4019-usb-hs-phy",
+	.id		= UCLASS_PHY,
+	.of_match	= ipq4019_usb_hs_phy_ids,
+	.ops		= &ipq4019_usb_hs_phy_ops,
+	.probe		= ipq4019_usb_hs_phy_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};

diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index c6d3048..9d4296d 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c

@@ -311,7 +311,7 @@
 
 	if ((phy->id == 0 && args->args_count != 1) ||
 	    (phy->id == 1 && args->args_count != 2)) {
-		dev_err(dev, "invalid number of cells for phy port%ld\n",
+		dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
 			phy->id);
 		return -EINVAL;
 	}

diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c
index 6907c1a..cc73760 100644
--- a/drivers/phy/phy-ti-am654.c
+++ b/drivers/phy/phy-ti-am654.c

@@ -318,13 +318,13 @@
 	struct serdes_am654 *phy = dev_get_priv(x->dev);
 
 	if (args->args_count != 2) {
-		dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
+		dev_err(x->dev, "Invalid DT PHY argument count: %d\n",
 			args->args_count);
 		return -EINVAL;
 	}
 
 	if (args->args[0] != PHY_TYPE_PCIE) {
-		dev_err(phy->dev, "Unrecognized PHY type: %d\n",
+		dev_err(x->dev, "Unrecognized PHY type: %d\n",
 			args->args[0]);
 		return -EINVAL;
 	}

diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index db7f39c..8f456f3 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c

@@ -117,56 +117,91 @@
 int generic_phy_init(struct phy *phy)
 {
 	struct phy_ops const *ops;
+	int ret;
 
 	if (!generic_phy_valid(phy))
 		return 0;
 	ops = phy_dev_ops(phy->dev);
+	if (!ops->init)
+		return 0;
+	ret = ops->init(phy);
+	if (ret)
+		dev_err(phy->dev, "PHY: Failed to init %s: %d.\n",
+			phy->dev->name, ret);
 
-	return ops->init ? ops->init(phy) : 0;
+	return ret;
 }
 
 int generic_phy_reset(struct phy *phy)
 {
 	struct phy_ops const *ops;
+	int ret;
 
 	if (!generic_phy_valid(phy))
 		return 0;
 	ops = phy_dev_ops(phy->dev);
+	if (!ops->reset)
+		return 0;
+	ret = ops->reset(phy);
+	if (ret)
+		dev_err(phy->dev, "PHY: Failed to reset %s: %d.\n",
+			phy->dev->name, ret);
 
-	return ops->reset ? ops->reset(phy) : 0;
+	return ret;
 }
 
 int generic_phy_exit(struct phy *phy)
 {
 	struct phy_ops const *ops;
+	int ret;
 
 	if (!generic_phy_valid(phy))
 		return 0;
 	ops = phy_dev_ops(phy->dev);
+	if (!ops->exit)
+		return 0;
+	ret = ops->exit(phy);
+	if (ret)
+		dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n",
+			phy->dev->name, ret);
 
-	return ops->exit ? ops->exit(phy) : 0;
+	return ret;
 }
 
 int generic_phy_power_on(struct phy *phy)
 {
 	struct phy_ops const *ops;
+	int ret;
 
 	if (!generic_phy_valid(phy))
 		return 0;
 	ops = phy_dev_ops(phy->dev);
+	if (!ops->power_on)
+		return 0;
+	ret = ops->power_on(phy);
+	if (ret)
+		dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n",
+			phy->dev->name, ret);
 
-	return ops->power_on ? ops->power_on(phy) : 0;
+	return ret;
 }
 
 int generic_phy_power_off(struct phy *phy)
 {
 	struct phy_ops const *ops;
+	int ret;
 
 	if (!generic_phy_valid(phy))
 		return 0;
 	ops = phy_dev_ops(phy->dev);
+	if (!ops->power_off)
+		return 0;
+	ret = ops->power_off(phy);
+	if (ret)
+		dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n",
+			phy->dev->name, ret);
 
-	return ops->power_off ? ops->power_off(phy) : 0;
+	return ret;
 }
 
 int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)

diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
index 83928cf..617943f 100644
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c

@@ -98,7 +98,7 @@
 
 	ret = reset_deassert(&priv->phy_rst);
 	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
+		dev_err(phy->dev, "failed to assert phy reset\n");
 		return ret;
 	}
 
@@ -119,7 +119,7 @@
 				       20 * 1000,
 				       50);
 	if (ret) {
-		dev_err(&priv->dev, "pll lock timeout!\n");
+		dev_err(phy->dev, "pll lock timeout!\n");
 		goto err_pll_lock;
 	}
 
@@ -133,7 +133,7 @@
 				       20 * 1000,
 				       50);
 	if (ret) {
-		dev_err(&priv->dev, "pll output enable timeout!\n");
+		dev_err(phy->dev, "pll output enable timeout!\n");
 		goto err_pll_lock;
 	}
 
@@ -149,7 +149,7 @@
 				       20 * 1000,
 				       50);
 	if (ret) {
-		dev_err(&priv->dev, "pll relock timeout!\n");
+		dev_err(phy->dev, "pll relock timeout!\n");
 		goto err_pll_lock;
 	}
 
@@ -173,7 +173,7 @@
 
 	ret = reset_assert(&priv->phy_rst);
 	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
+		dev_err(phy->dev, "failed to assert phy reset\n");
 		return ret;
 	}
 
@@ -187,13 +187,13 @@
 
 	ret = clk_enable(&priv->refclk);
 	if (ret) {
-		dev_err(dev, "failed to enable refclk clock\n");
+		dev_err(phy->dev, "failed to enable refclk clock\n");
 		return ret;
 	}
 
 	ret = reset_assert(&priv->phy_rst);
 	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
+		dev_err(phy->dev, "failed to assert phy reset\n");
 		goto err_reset;
 	}
 

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index c9c8e1c..da00daa 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c

@@ -448,7 +448,7 @@
 	writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
 }
 
-static int rockchip_tcphy_init(struct rockchip_tcphy *priv)
+static int rockchip_tcphy_init(struct phy *phy, struct rockchip_tcphy *priv)
 {
 	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
 	u32 val;
@@ -559,9 +559,9 @@
 		return 0;
 
 	if (priv->mode == MODE_DISCONNECT) {
-		ret = rockchip_tcphy_init(priv);
+		ret = rockchip_tcphy_init(phy, priv);
 		if (ret) {
-			dev_err(dev, "failed to init tcphy (ret=%d)\n", ret);
+			dev_err(phy->dev, "failed to init tcphy (ret=%d)\n", ret);
 			return ret;
 		}
 	}

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index cdbccfd..048583f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig

@@ -205,6 +205,13 @@
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
+config PINCTRL_QE
+	bool "QE based pinctrl driver, like on mpc83xx"
+	depends on DM
+	help
+	  This option is to enable the QE pinctrl driver for QE based io
+	  controller.
+
 config PINCTRL_ROCKCHIP_RV1108
 	bool "Rockchip rv1108 pin control driver"
 	depends on DM

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 92cff1b..507dd3a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile

@@ -22,6 +22,7 @@
 obj-$(CONFIG_PINCTRL_MSCC)	+= mscc/
 obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
 obj-$(CONFIG_ARCH_NEXELL)	+= nexell/
+obj-$(CONFIG_PINCTRL_QE)	+= pinctrl-qe-io.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_STI)	+= pinctrl-sti.o
 obj-$(CONFIG_PINCTRL_STM32)	+= pinctrl_stm32.o

diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index c22d534..41da814 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c

@@ -63,7 +63,7 @@
 int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 {
 	u32 pin_arr[MAX_PINS_PER_BANK];
-	u32 function;
+	int function;
 	int i, len, pin_count = 0;
 
 	if (!dev_read_prop(config, "brcm,pins", &len) || !len ||
@@ -104,17 +104,11 @@
 	{}
 };
 
-int bcm283x_pinctl_probe(struct udevice *dev)
+int bcm283x_pinctl_ofdata_to_platdata(struct udevice *dev)
 {
 	struct bcm283x_pinctrl_priv *priv;
-	int ret;
-	struct udevice *pdev;
 
 	priv = dev_get_priv(dev);
-	if (!priv) {
-		debug("%s: Failed to get private\n", __func__);
-		return -EINVAL;
-	}
 
 	priv->base_reg = dev_read_addr_ptr(dev);
 	if (!priv->base_reg) {
@@ -122,6 +116,14 @@
 		return -EINVAL;
 	}
 
+	return 0;
+}
+
+int bcm283x_pinctl_probe(struct udevice *dev)
+{
+	int ret;
+	struct udevice *pdev;
+
 	/* Create GPIO device as well */
 	ret = device_bind(dev, lists_driver_lookup_name("gpio_bcm2835"),
 			  "gpio_bcm2835", NULL, dev_of_offset(dev), &pdev);
@@ -147,10 +149,11 @@
 	.name		= "bcm283x_pinctrl",
 	.id		= UCLASS_PINCTRL,
 	.of_match	= of_match_ptr(bcm2835_pinctrl_id),
+	.ofdata_to_platdata = bcm283x_pinctl_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
 	.ops		= &bcm283x_pinctrl_ops,
 	.probe		= bcm283x_pinctl_probe,
-#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
+#if CONFIG_IS_ENABLED(OF_BOARD)
 	.flags		= DM_FLAG_PRE_RELOC,
 #endif
 };

diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c
new file mode 100644
index 0000000..85521ea
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-qe-io.c

@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/immap_83xx.h>
+
+#if defined(CONFIG_PINCTRL)
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/ioport.h>
+
+/**
+ * struct qe_io_platdata
+ *
+ * @base:		Base register address
+ * @num_par_io_ports	number of io ports
+ */
+struct qe_io_platdata {
+	qepio83xx_t *base;
+	u32 num_io_ports;
+};
+#endif
+
+#define	NUM_OF_PINS	32
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io:	pointer to parallel I/O base
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+			 int open_drain, int assign)
+{
+	u32	dbit_mask;
+	u32	dbit_dir;
+	u32	dbit_asgn;
+	u32	bit_mask;
+	u32	tmp_val;
+	int	offset;
+
+	offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
+
+	/* Calculate pin location and 2bit mask and dir */
+	dbit_mask = (u32)(0x3 << offset);
+	dbit_dir = (u32)(dir << offset);
+
+	/* Setup the direction */
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].dir2) :
+		in_be32(&par_io->ioport[port].dir1);
+
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
+	}
+
+	/* Calculate pin location for 1bit mask */
+	bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
+
+	/* Setup the open drain */
+	tmp_val = in_be32(&par_io->ioport[port].podr);
+	if (open_drain)
+		out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+	else
+		out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
+
+	/* Setup the assignment */
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].ppar2) :
+		in_be32(&par_io->ioport[port].ppar1);
+	dbit_asgn = (u32)(assign << offset);
+
+	/* Clear and set 2 bits mask */
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
+	}
+}
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
+	qepio83xx_t    *par_io = (qepio83xx_t *)&im->qepio;
+
+	qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#else
+static int qe_io_ofdata_to_platdata(struct udevice *dev)
+{
+	struct qe_io_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->base = (qepio83xx_t *)addr;
+	if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
+		return -EINVAL;
+
+	return 0;
+}
+
+/**
+ * par_io_of_config_node	config
+ * @dev:	pointer to pinctrl device
+ * @pio:	ofnode of pinconfig property
+ */
+static int par_io_of_config_node(struct udevice *dev, ofnode pio)
+{
+	struct qe_io_platdata *plat = dev->platdata;
+	qepio83xx_t *par_io = plat->base;
+	const unsigned int *pio_map;
+	int pio_map_len;
+
+	pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
+	if (!pio_map)
+		return -ENOENT;
+
+	pio_map_len /= sizeof(unsigned int);
+	if ((pio_map_len % 6) != 0) {
+		dev_err(dev, "%s: pio-map format wrong!\n", __func__);
+		return -EINVAL;
+	}
+
+	while (pio_map_len > 0) {
+		/*
+		 * column pio_map[5] from linux (has_irq) not
+		 * supported in u-boot yet.
+		 */
+		qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
+			     (int)pio_map[2], (int)pio_map[3],
+			     (int)pio_map[4]);
+		pio_map += 6;
+		pio_map_len -= 6;
+	}
+	return 0;
+}
+
+int par_io_of_config(struct udevice *dev)
+{
+	u32 phandle;
+	ofnode pio;
+	int err;
+
+	err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
+	if (err) {
+		dev_err(dev, "%s: pio-handle not available\n", __func__);
+		return err;
+	}
+
+	pio = ofnode_get_by_phandle(phandle);
+	if (!ofnode_valid(pio)) {
+		dev_err(dev, "%s: unable to find node\n", __func__);
+		return -EINVAL;
+	}
+
+	/* To Do: find pinctrl device and pass it */
+	return par_io_of_config_node(NULL, pio);
+}
+
+/*
+ * This is not nice!
+ * pinsettings should work with "pinctrl-" properties.
+ * Unfortunately on mpc83xx powerpc linux device trees
+ * devices handle this with "pio-handle" properties ...
+ *
+ * Even worser, old board code inits all par_io
+ * pins in one step, if U-Boot uses the device
+ * or not. So init all par_io definitions here too
+ * as linux does this also.
+ */
+static void config_qe_ioports(struct udevice *dev)
+{
+	ofnode ofn;
+
+	for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
+	     ofn = dev_read_next_subnode(ofn)) {
+		/*
+		 * ignore errors here, as may the subnode
+		 * has no pio-handle
+		 */
+		par_io_of_config_node(dev, ofn);
+	}
+}
+
+static int par_io_pinctrl_probe(struct udevice *dev)
+{
+	config_qe_ioports(dev);
+
+	return 0;
+}
+
+static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	return 0;
+}
+
+const struct pinctrl_ops par_io_pinctrl_ops = {
+	.set_state = par_io_pinctrl_set_state,
+};
+
+static const struct udevice_id par_io_pinctrl_match[] = {
+	{ .compatible = "fsl,mpc8360-par_io"},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(par_io_pinctrl) = {
+	.name = "par-io-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(par_io_pinctrl_match),
+	.probe = par_io_pinctrl_probe,
+	.ofdata_to_platdata = qe_io_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct qe_io_platdata),
+	.ops = &par_io_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.flags	= DM_FLAG_PRE_RELOC,
+#endif
+};
+#endif

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 71fa29a..dbea995 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c

@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
+ */
+
 #include <common.h>
 #include <dm.h>
 #include <hwspinlock.h>
@@ -13,8 +18,6 @@
 #include <linux/err.h>
 #include <linux/libfdt.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define MAX_PINS_ONE_IP			70
 #define MODE_BITS_MASK			3
 #define OSPEED_MASK			3
@@ -308,7 +311,8 @@
 	return 0;
 }
 
-static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
+static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
+			 ofnode node)
 {
 	gpio_fn &= 0x00FF;
 	gpio_ctl->af = 0;
@@ -329,16 +333,16 @@
 		break;
 	}
 
-	gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
+	gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
 
-	if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
+	if (ofnode_read_bool(node, "drive-open-drain"))
 		gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
 	else
 		gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
 
-	if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
+	if (ofnode_read_bool(node, "bias-pull-up"))
 		gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
-	else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
+	else if (ofnode_read_bool(node, "bias-pull-down"))
 		gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
 	else
 		gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
@@ -350,32 +354,37 @@
 	return 0;
 }
 
-static int stm32_pinctrl_config(int offset)
+static int stm32_pinctrl_config(ofnode node)
 {
 	u32 pin_mux[MAX_PINS_ONE_IP];
 	int rv, len;
+	ofnode subnode;
 
 	/*
 	 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
 	 * usart1) of pin controller phandle "pinctrl-0"
 	 * */
-	fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
+	ofnode_for_each_subnode(subnode, node) {
 		struct stm32_gpio_dsc gpio_dsc;
 		struct stm32_gpio_ctl gpio_ctl;
 		int i;
 
-		len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
-						 "pinmux", pin_mux,
-						 ARRAY_SIZE(pin_mux));
+		rv = ofnode_read_size(subnode, "pinmux");
+		if (rv < 0)
+			return rv;
+		len = rv / sizeof(pin_mux[0]);
 		debug("%s: no of pinmux entries= %d\n", __func__, len);
-		if (len < 0)
+		if (len > MAX_PINS_ONE_IP)
 			return -EINVAL;
+		rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
+		if (rv < 0)
+			return rv;
 		for (i = 0; i < len; i++) {
 			struct gpio_desc desc;
 
 			debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
 			prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
-			prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
+			prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
 			rv = uclass_get_device_by_seq(UCLASS_GPIO,
 						      gpio_dsc.port,
 						      &desc.dev);
@@ -424,19 +433,18 @@
 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 {
-	return stm32_pinctrl_config(dev_of_offset(config));
+	return stm32_pinctrl_config(dev_ofnode(config));
 }
 #else /* PINCTRL_FULL */
 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
 					  struct udevice *periph)
 {
-	const void *fdt = gd->fdt_blob;
 	const fdt32_t *list;
 	uint32_t phandle;
-	int config_node;
+	ofnode config_node;
 	int size, i, ret;
 
-	list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
+	list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
 	if (!list)
 		return -EINVAL;
 
@@ -446,8 +454,8 @@
 	for (i = 0; i < size; i++) {
 		phandle = fdt32_to_cpu(*list++);
 
-		config_node = fdt_node_offset_by_phandle(fdt, phandle);
-		if (config_node < 0) {
+		config_node = ofnode_get_by_phandle(phandle);
+		if (!ofnode_valid(config_node)) {
 			pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
 			return -EINVAL;
 		}

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8327bca..e14294b 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig

@@ -57,6 +57,16 @@
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
+config PINCTRL_PFC_R8A774A1
+        bool "Renesas RZ/G2 R8A774A1 pin control driver"
+        depends on PINCTRL_PFC
+        help
+          Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs.
+
+          The driver is controlled by a device tree node which contains both
+          the GPIO definitions and pin control functions for each available
+          multiplex function.
+
 config PINCTRL_PFC_R8A7795
 	bool "Renesas RCar Gen3 R8A7795 pin control driver"
 	depends on PINCTRL_PFC
@@ -77,16 +87,6 @@
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
-config PINCTRL_PFC_R8A774A1
-        bool "Renesas RCar Gen3 R8A774A1 pin control driver"
-        depends on PINCTRL_PFC
-        help
-          Support pin multiplexing control on Renesas RZG2M R8A774A1 SoCs.
-
-          The driver is controlled by a device tree node which contains both
-          the GPIO definitions and pin control functions for each available
-          multiplex function.
-
 config PINCTRL_PFC_R8A77965
 	bool "Renesas RCar Gen3 R8A77965 pin control driver"
 	depends on PINCTRL_PFC

diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig
index 44c9f01..864b36b 100644
--- a/drivers/qe/Kconfig
+++ b/drivers/qe/Kconfig

@@ -3,7 +3,7 @@
 #
 config QE
 	bool "Enable support for QUICC Engine"
-	depends on PPC && !DM_ETH
+	depends on PPC
 	default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
 		|| ARCH_P1025
 	help

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 61ca476..1a829b5 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c

@@ -26,7 +26,7 @@
 
 #define MPC85xx_DEVDISR_QE_DISABLE	0x1
 
-qe_map_t		*qe_immr = NULL;
+qe_map_t		*qe_immr;
 #ifdef CONFIG_QE
 static qe_snum_t	snums[QE_NUM_OF_SNUM];
 #endif
@@ -38,18 +38,16 @@
 	u32 cecr;
 
 	if (cmd == QE_RESET) {
-		out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
+		out_be32(&qe_immr->cp.cecr, (u32)(cmd | QE_CR_FLG));
 	} else {
 		out_be32(&qe_immr->cp.cecdr, cmd_data);
 		out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
-			 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
+			 ((u32)mcn << QE_CR_PROTOCOL_SHIFT) | cmd));
 	}
 	/* Wait for the QE_CR_FLG to clear */
 	do {
 		cecr = in_be32(&qe_immr->cp.cecr);
 	} while (cecr & QE_CR_FLG);
-
-	return;
 }
 
 #ifdef CONFIG_QE
@@ -66,12 +64,13 @@
 	if (off != 0)
 		gd->arch.mp_alloc_base += (align - off);
 
-	if ((off = size & align_mask) != 0)
+	off = size & align_mask;
+	if (off != 0)
 		size += (align - off);
 
 	if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
 		gd->arch.mp_alloc_base = savebase;
-		printf("%s: ran out of ram.\n",  __FUNCTION__);
+		printf("%s: ran out of ram.\n",  __func__);
 	}
 
 	retloc = gd->arch.mp_alloc_base;
@@ -93,10 +92,10 @@
 #ifdef CONFIG_QE
 static void qe_sdma_init(void)
 {
-	volatile sdma_t	*p;
-	uint		sdma_buffer_base;
+	sdma_t	*p;
+	uint	sdma_buffer_base;
 
-	p = (volatile sdma_t *)&qe_immr->sdma;
+	p = (sdma_t *)&qe_immr->sdma;
 
 	/* All of DMA transaction in bus 1 */
 	out_be32(&p->sdaqr, 0);
@@ -212,7 +211,7 @@
 	qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
 
 	/* enable the microcode in IRAM */
-	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
+	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
 #endif
 
 	gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
@@ -235,10 +234,12 @@
 	void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
 
 	if (src == BOOT_SOURCE_IFC_NOR)
-		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
+				CONFIG_SYS_FSL_IFC_BASE);
 
 	if (src == BOOT_SOURCE_QSPI_NOR)
-		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
+				CONFIG_SYS_FSL_QSPI_BASE);
 
 	if (src == BOOT_SOURCE_SD_MMC) {
 		int dev = CONFIG_SYS_MMC_ENV_DEV;
@@ -320,7 +321,7 @@
 void qe_reset(void)
 {
 	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
-			 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+		     (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 }
 
 #ifdef CONFIG_QE
@@ -329,24 +330,22 @@
 	u32	cecr;
 
 	out_be32(&qe_immr->cp.cecdr, para_ram_base);
-	out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
+	out_be32(&qe_immr->cp.cecr, ((u32)snum << QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
 					 | QE_CR_FLG | QE_ASSIGN_PAGE);
 
 	/* Wait for the QE_CR_FLG to clear */
 	do {
 		cecr = in_be32(&qe_immr->cp.cecr);
-	} while (cecr & QE_CR_FLG );
-
-	return;
+	} while (cecr & QE_CR_FLG);
 }
 #endif
 
 /*
  * brg: 0~15 as BRG1~BRG16
-   rate: baud rate
+ * rate: baud rate
  * BRG input clock comes from the BRGCLK (internal clock generated from
-   the QE clock, it is one-half of the QE clock), If need the clock source
-   from CLKn pin, we have te change the function.
+ * the QE clock, it is one-half of the QE clock), If need the clock source
+ * from CLKn pin, we have te change the function.
  */
 
 #define BRG_CLK		(gd->arch.brg_clk)
@@ -354,12 +353,14 @@
 #ifdef CONFIG_QE
 int qe_set_brg(uint brg, uint rate)
 {
-	volatile uint	*bp;
-	u32		divisor;
-	int		div16 = 0;
+	uint	*bp;
+	u32	divisor;
+	u32	val;
+	int	div16 = 0;
 
 	if (brg >= QE_NUM_OF_BRGS)
 		return -EINVAL;
+
 	bp = (uint *)&qe_immr->brg.brgc1;
 	bp += brg;
 
@@ -369,33 +370,37 @@
 		divisor /= 16;
 	}
 
-	*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
-	__asm__ __volatile__("sync");
+	/* CHECK TODO */
+	/*
+	 * was
+	 * *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+	 * __asm__ __volatile__("sync");
+	 */
 
-	if (div16) {
-		*bp |= QE_BRGC_DIV16;
-		__asm__ __volatile__("sync");
-	}
+	val = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+	if (div16)
+		val |= QE_BRGC_DIV16;
+
+	out_be32(bp, val);
 
 	return 0;
 }
 #endif
 
-/* Set ethernet MII clock master
-*/
+/* Set ethernet MII clock master */
 int qe_set_mii_clk_src(int ucc_num)
 {
 	u32	cmxgcr;
 
 	/* check if the UCC number is in range. */
-	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
-		printf("%s: ucc num not in ranges\n", __FUNCTION__);
+	if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
+		printf("%s: ucc num not in ranges\n", __func__);
 		return -EINVAL;
 	}
 
 	cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
 	cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
-	cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
+	cmxgcr |= (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
 	out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
 
 	return 0;
@@ -417,7 +422,7 @@
  * the actual uploading of the microcode.
  */
 static void qe_upload_microcode(const void *base,
-	const struct qe_microcode *ucode)
+				const struct qe_microcode *ucode)
 {
 	const u32 *code = base + be32_to_cpu(ucode->code_offset);
 	unsigned int i;
@@ -494,7 +499,7 @@
 	}
 
 	/* Validate some of the fields */
-	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+	if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
 		printf("Invalid data\n");
 		return -EINVAL;
 	}
@@ -522,7 +527,7 @@
 	 * function isn't available unless you turn on JFFS support.
 	 */
 	crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
-	if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
+	if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
 		printf("Firmware CRC is invalid\n");
 		return -EIO;
 	}
@@ -532,12 +537,12 @@
 	 */
 	if (!firmware->split) {
 		out_be16(&qe_immr->cp.cercr,
-			in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+			 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
 	}
 
 	if (firmware->soc.model)
 		printf("Firmware '%s' for %u V%u.%u\n",
-			firmware->id, be16_to_cpu(firmware->soc.model),
+		       firmware->id, be16_to_cpu(firmware->soc.model),
 			firmware->soc.major, firmware->soc.minor);
 	else
 		printf("Firmware '%s'\n", firmware->id);
@@ -550,7 +555,7 @@
 	strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
 	qe_firmware_info.extended_modes = firmware->extended_modes;
 	memcpy(qe_firmware_info.vtraps, firmware->vtraps,
-		sizeof(firmware->vtraps));
+	       sizeof(firmware->vtraps));
 	qe_firmware_uploaded = 1;
 
 	/* Loop through each microcode. */
@@ -634,7 +639,7 @@
 	}
 
 	/* Validate some of the fields */
-	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+	if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
 		printf("Invalid data\n");
 		return -EINVAL;
 	}
@@ -803,7 +808,7 @@
 
 		if (argc > 3) {
 			ulong length = simple_strtoul(argv[3], NULL, 16);
-			struct qe_firmware *firmware = (void *) addr;
+			struct qe_firmware *firmware = (void *)addr;
 
 			if (length != be32_to_cpu(firmware->header.length)) {
 				printf("Length mismatch\n");
@@ -811,7 +816,7 @@
 			}
 		}
 
-		return qe_upload_firmware((const struct qe_firmware *) addr);
+		return qe_upload_firmware((const struct qe_firmware *)addr);
 	}
 
 	return cmd_usage(cmdtp);
@@ -820,7 +825,6 @@
 U_BOOT_CMD(
 	qe, 4, 0, qe_cmd,
 	"QUICC Engine commands",
-	"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
-		"the QE,\n"
+	"fw <addr> [<length>] - Upload firmware binary at address <addr> to the QE,\n"
 	"\twith optional length <length> verification."
 );

diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index 9beb5d9..d5d7344 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c

@@ -14,7 +14,8 @@
 #include "uccf.h"
 #include <fsl_qe.h>
 
-void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
+#if !defined(CONFIG_DM_ETH)
+void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
 {
 	out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
 }
@@ -22,170 +23,271 @@
 u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
 {
 	switch (ucc_num) {
-		case 0:	return QE_CR_SUBBLOCK_UCCFAST1;
-		case 1:	return QE_CR_SUBBLOCK_UCCFAST2;
-		case 2:	return QE_CR_SUBBLOCK_UCCFAST3;
-		case 3:	return QE_CR_SUBBLOCK_UCCFAST4;
-		case 4:	return QE_CR_SUBBLOCK_UCCFAST5;
-		case 5:	return QE_CR_SUBBLOCK_UCCFAST6;
-		case 6:	return QE_CR_SUBBLOCK_UCCFAST7;
-		case 7:	return QE_CR_SUBBLOCK_UCCFAST8;
-		default:	return QE_CR_SUBBLOCK_INVALID;
+	case 0:
+		return QE_CR_SUBBLOCK_UCCFAST1;
+	case 1:
+		return QE_CR_SUBBLOCK_UCCFAST2;
+	case 2:
+		return QE_CR_SUBBLOCK_UCCFAST3;
+	case 3:
+		return QE_CR_SUBBLOCK_UCCFAST4;
+	case 4:
+		return QE_CR_SUBBLOCK_UCCFAST5;
+	case 5:
+		return QE_CR_SUBBLOCK_UCCFAST6;
+	case 6:
+		return QE_CR_SUBBLOCK_UCCFAST7;
+	case 7:
+		return QE_CR_SUBBLOCK_UCCFAST8;
+	default:
+		return QE_CR_SUBBLOCK_INVALID;
 	}
 }
 
-static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
-				 u8 *reg_num, u8 *shift)
+static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
+			       u8 *reg_num, u8 *shift)
 {
 	switch (ucc_num) {
-		case 0:	/* UCC1 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr1);
-			*reg_num = 1;
-			*shift  = 16;
-			break;
-		case 2:	/* UCC3 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr1);
-			*reg_num = 1;
-			*shift  = 0;
-			break;
-		case 4:	/* UCC5 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr2);
-			*reg_num = 2;
-			*shift  = 16;
-			break;
-		case 6:	/* UCC7 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr2);
-			*reg_num = 2;
-			*shift  = 0;
-			break;
-		case 1:	/* UCC2 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr3);
-			*reg_num = 3;
-			*shift  = 16;
-			break;
-		case 3:	/* UCC4 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr3);
-			*reg_num = 3;
-			*shift  = 0;
-			break;
-		case 5:	/* UCC6 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr4);
-			*reg_num = 4;
-			*shift  = 16;
-			break;
-		case 7:	/* UCC8 */
-			*p_cmxucr  = &(qe_immr->qmx.cmxucr4);
-			*reg_num = 4;
-			*shift  = 0;
-			break;
-		default:
-			break;
+	case 0:	/* UCC1 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr1;
+		*reg_num = 1;
+		*shift  = 16;
+		break;
+	case 2:	/* UCC3 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr1;
+		*reg_num = 1;
+		*shift  = 0;
+		break;
+	case 4:	/* UCC5 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr2;
+		*reg_num = 2;
+		*shift  = 16;
+		break;
+	case 6:	/* UCC7 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr2;
+		*reg_num = 2;
+		*shift  = 0;
+		break;
+	case 1:	/* UCC2 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr3;
+		*reg_num = 3;
+		*shift  = 16;
+		break;
+	case 3:	/* UCC4 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr3;
+		*reg_num = 3;
+		*shift  = 0;
+		break;
+	case 5:	/* UCC6 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr4;
+		*reg_num = 4;
+		*shift  = 16;
+		break;
+	case 7:	/* UCC8 */
+		*p_cmxucr  = &qe_immr->qmx.cmxucr4;
+		*reg_num = 4;
+		*shift  = 0;
+		break;
+	default:
+		break;
 	}
 }
 
 static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
 {
-	volatile u32	*p_cmxucr = NULL;
-	u8		reg_num = 0;
-	u8		shift = 0;
-	u32		clockBits;
-	u32		clockMask;
-	int		source = -1;
+	u32	*p_cmxucr = NULL;
+	u8	reg_num = 0;
+	u8	shift = 0;
+	u32	clk_bits;
+	u32	clk_mask;
+	int	source = -1;
 
 	/* check if the UCC number is in range. */
-	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+	if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
 		return -EINVAL;
 
-	if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
-		printf("%s: bad comm mode type passed\n", __FUNCTION__);
+	if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
+		printf("%s: bad comm mode type passed\n", __func__);
 		return -EINVAL;
 	}
 
 	ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
 
 	switch (reg_num) {
-		case 1:
-			switch (clock) {
-				case QE_BRG1:	source = 1; break;
-				case QE_BRG2:	source = 2; break;
-				case QE_BRG7:	source = 3; break;
-				case QE_BRG8:	source = 4; break;
-				case QE_CLK9:	source = 5; break;
-				case QE_CLK10:	source = 6; break;
-				case QE_CLK11:	source = 7; break;
-				case QE_CLK12:	source = 8; break;
-				case QE_CLK15:	source = 9; break;
-				case QE_CLK16:	source = 10; break;
-				default:	source = -1; break;
-			}
+	case 1:
+		switch (clock) {
+		case QE_BRG1:
+			source = 1;
+			break;
+		case QE_BRG2:
+			source = 2;
+			break;
+		case QE_BRG7:
+			source = 3;
+			break;
+		case QE_BRG8:
+			source = 4;
+			break;
+		case QE_CLK9:
+			source = 5;
+			break;
+		case QE_CLK10:
+			source = 6;
+			break;
+		case QE_CLK11:
+			source = 7;
 			break;
-		case 2:
-			switch (clock) {
-				case QE_BRG5:	source = 1; break;
-				case QE_BRG6:	source = 2; break;
-				case QE_BRG7:	source = 3; break;
-				case QE_BRG8:	source = 4; break;
-				case QE_CLK13:	source = 5; break;
-				case QE_CLK14:	source = 6; break;
-				case QE_CLK19:	source = 7; break;
-				case QE_CLK20:	source = 8; break;
-				case QE_CLK15:	source = 9; break;
-				case QE_CLK16:	source = 10; break;
-				default:	source = -1; break;
-			}
+		case QE_CLK12:
+			source = 8;
 			break;
-		case 3:
-			switch (clock) {
-				case QE_BRG9:	source = 1; break;
-				case QE_BRG10:	source = 2; break;
-				case QE_BRG15:	source = 3; break;
-				case QE_BRG16:	source = 4; break;
-				case QE_CLK3:	source = 5; break;
-				case QE_CLK4:	source = 6; break;
-				case QE_CLK17:	source = 7; break;
-				case QE_CLK18:	source = 8; break;
-				case QE_CLK7:	source = 9; break;
-				case QE_CLK8:	source = 10; break;
-				case QE_CLK16:	source = 11; break;
-				default:	source = -1; break;
-			}
+		case QE_CLK15:
+			source = 9;
 			break;
-		case 4:
-			switch (clock) {
-				case QE_BRG13:	source = 1; break;
-				case QE_BRG14:	source = 2; break;
-				case QE_BRG15:	source = 3; break;
-				case QE_BRG16:	source = 4; break;
-				case QE_CLK5:	source = 5; break;
-				case QE_CLK6:	source = 6; break;
-				case QE_CLK21:	source = 7; break;
-				case QE_CLK22:	source = 8; break;
-				case QE_CLK7:	source = 9; break;
-				case QE_CLK8:	source = 10; break;
-				case QE_CLK16:	source = 11; break;
-				default:	source = -1; break;
-			}
+		case QE_CLK16:
+			source = 10;
 			break;
 		default:
 			source = -1;
 			break;
+		}
+		break;
+	case 2:
+		switch (clock) {
+		case QE_BRG5:
+			source = 1;
+			break;
+		case QE_BRG6:
+			source = 2;
+			break;
+		case QE_BRG7:
+			source = 3;
+			break;
+		case QE_BRG8:
+			source = 4;
+			break;
+		case QE_CLK13:
+			source = 5;
+			break;
+		case QE_CLK14:
+			source = 6;
+			break;
+		case QE_CLK19:
+			source = 7;
+			break;
+		case QE_CLK20:
+			source = 8;
+			break;
+		case QE_CLK15:
+			source = 9;
+			break;
+		case QE_CLK16:
+			source = 10;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	case 3:
+		switch (clock) {
+		case QE_BRG9:
+			source = 1;
+			break;
+		case QE_BRG10:
+			source = 2;
+			break;
+		case QE_BRG15:
+			source = 3;
+			break;
+		case QE_BRG16:
+			source = 4;
+			break;
+		case QE_CLK3:
+			source = 5;
+			break;
+		case QE_CLK4:
+			source = 6;
+			break;
+		case QE_CLK17:
+			source = 7;
+			break;
+		case QE_CLK18:
+			source = 8;
+			break;
+		case QE_CLK7:
+			source = 9;
+			break;
+		case QE_CLK8:
+			source = 10;
+			break;
+		case QE_CLK16:
+			source = 11;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	case 4:
+		switch (clock) {
+		case QE_BRG13:
+			source = 1;
+			break;
+		case QE_BRG14:
+			source = 2;
+			break;
+		case QE_BRG15:
+			source = 3;
+			break;
+		case QE_BRG16:
+			source = 4;
+			break;
+		case QE_CLK5:
+			source = 5;
+			break;
+		case QE_CLK6:
+			source = 6;
+			break;
+		case QE_CLK21:
+			source = 7;
+			break;
+		case QE_CLK22:
+			source = 8;
+			break;
+		case QE_CLK7:
+			source = 9;
+			break;
+		case QE_CLK8:
+			source = 10;
+			break;
+		case QE_CLK16:
+			source = 11;
+			break;
+		default:
+			source = -1;
+			break;
+		}
+		break;
+	default:
+		source = -1;
+		break;
 	}
 
 	if (source == -1) {
-		printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
+		printf("%s: Bad combination of clock and UCC\n", __func__);
 		return -ENOENT;
 	}
 
-	clockBits = (u32) source;
-	clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
+	clk_bits = (u32)source;
+	clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
 	if (mode == COMM_DIR_RX) {
-		clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
-		clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
+		clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
+		clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
 	}
-	clockBits <<= shift;
-	clockMask <<= shift;
+	clk_bits <<= shift;
+	clk_mask <<= shift;
 
-	out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
+	out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
 
 	return 0;
 }
@@ -195,28 +297,45 @@
 	uint base = 0;
 
 	/* check if the UCC number is in range */
-	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
-		printf("%s: the UCC num not in ranges\n", __FUNCTION__);
+	if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
+		printf("%s: the UCC num not in ranges\n", __func__);
 		return 0;
 	}
 
 	switch (ucc_num) {
-		case 0:	base = 0x00002000; break;
-		case 1:	base = 0x00003000; break;
-		case 2:	base = 0x00002200; break;
-		case 3:	base = 0x00003200; break;
-		case 4:	base = 0x00002400; break;
-		case 5:	base = 0x00003400; break;
-		case 6:	base = 0x00002600; break;
-		case 7:	base = 0x00003600; break;
-		default: break;
+	case 0:
+		base = 0x00002000;
+		break;
+	case 1:
+		base = 0x00003000;
+		break;
+	case 2:
+		base = 0x00002200;
+		break;
+	case 3:
+		base = 0x00003200;
+		break;
+	case 4:
+		base = 0x00002400;
+		break;
+	case 5:
+		base = 0x00003400;
+		break;
+	case 6:
+		base = 0x00002600;
+		break;
+	case 7:
+		base = 0x00003600;
+		break;
+	default:
+		break;
 	}
 
 	base = (uint)qe_immr + base;
 	return base;
 }
 
-void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
+void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
 {
 	ucc_fast_t	*uf_regs;
 	u32		gumr;
@@ -236,7 +355,7 @@
 	out_be32(&uf_regs->gumr, gumr);
 }
 
-void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
+void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
 {
 	ucc_fast_t	*uf_regs;
 	u32		gumr;
@@ -256,34 +375,35 @@
 	out_be32(&uf_regs->gumr, gumr);
 }
 
-int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t  **uccf_ret)
+int ucc_fast_init(struct ucc_fast_inf *uf_info,
+		  struct ucc_fast_priv **uccf_ret)
 {
-	ucc_fast_private_t	*uccf;
+	struct ucc_fast_priv	*uccf;
 	ucc_fast_t		*uf_regs;
 
 	if (!uf_info)
 		return -EINVAL;
 
-	if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
-		printf("%s: Illagal UCC number!\n", __FUNCTION__);
+	if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+		printf("%s: Illagal UCC number!\n", __func__);
 		return -EINVAL;
 	}
 
-	uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
+	uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
 	if (!uccf) {
 		printf("%s: No memory for UCC fast data structure!\n",
-			 __FUNCTION__);
+		       __func__);
 		return -ENOMEM;
 	}
-	memset(uccf, 0, sizeof(ucc_fast_private_t));
+	memset(uccf, 0, sizeof(struct ucc_fast_priv));
 
 	/* Save fast UCC structure */
 	uccf->uf_info	= uf_info;
 	uccf->uf_regs	= (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
 
-	if (uccf->uf_regs == NULL) {
+	if (!uccf->uf_regs) {
 		printf("%s: No memory map for UCC fast controller!\n",
-			 __FUNCTION__);
+		       __func__);
 		return -ENOMEM;
 	}
 
@@ -291,8 +411,8 @@
 	uccf->enabled_rx	= 0;
 
 	uf_regs			= uccf->uf_regs;
-	uccf->p_ucce		= (u32 *) &(uf_regs->ucce);
-	uccf->p_uccm		= (u32 *) &(uf_regs->uccm);
+	uccf->p_ucce		= (u32 *)&uf_regs->ucce;
+	uccf->p_uccm		= (u32 *)&uf_regs->uccm;
 
 	/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
 	out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
@@ -306,13 +426,13 @@
 		/* Allocate memory for Tx Virtual Fifo */
 		uccf->ucc_fast_tx_virtual_fifo_base_offset =
 		qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
-				 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 
 		/* Allocate memory for Rx Virtual Fifo */
 		uccf->ucc_fast_rx_virtual_fifo_base_offset =
 		qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
-				 UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
-				UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+			       UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 
 		/* utfb, urfb are offsets from MURAM base */
 		out_be32(&uf_regs->utfb,
@@ -334,7 +454,7 @@
 		/* Allocate memory for Tx Virtual Fifo */
 		uccf->ucc_fast_tx_virtual_fifo_base_offset =
 		qe_muram_alloc(UCC_GETH_UTFS_INIT,
-				 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+			       UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 
 		/* Allocate memory for Rx Virtual Fifo */
 		uccf->ucc_fast_rx_virtual_fifo_base_offset =
@@ -360,9 +480,9 @@
 	/* Rx clock routing */
 	if (uf_info->rx_clock != QE_CLK_NONE) {
 		if (ucc_set_clk_src(uf_info->ucc_num,
-			 uf_info->rx_clock, COMM_DIR_RX)) {
+				    uf_info->rx_clock, COMM_DIR_RX)) {
 			printf("%s: Illegal value for parameter 'RxClock'.\n",
-				 __FUNCTION__);
+			       __func__);
 			return -EINVAL;
 		}
 	}
@@ -370,9 +490,9 @@
 	/* Tx clock routing */
 	if (uf_info->tx_clock != QE_CLK_NONE) {
 		if (ucc_set_clk_src(uf_info->ucc_num,
-			 uf_info->tx_clock, COMM_DIR_TX)) {
+				    uf_info->tx_clock, COMM_DIR_TX)) {
 			printf("%s: Illegal value for parameter 'TxClock'.\n",
-				 __FUNCTION__);
+			       __func__);
 			return -EINVAL;
 		}
 	}
@@ -386,3 +506,4 @@
 	*uccf_ret = uccf;
 	return 0;
 }
+#endif

diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
index 4098c66..99f8458 100644
--- a/drivers/qe/uccf.h
+++ b/drivers/qe/uccf.h

@@ -13,25 +13,23 @@
 #include "linux/immap_qe.h"
 #include <fsl_qe.h>
 
-/* Fast or Giga ethernet
-*/
-typedef enum enet_type {
+/* Fast or Giga ethernet */
+enum enet_type {
 	FAST_ETH,
 	GIGA_ETH,
-} enet_type_e;
+};
 
-/* General UCC Extended Mode Register
-*/
+/* General UCC Extended Mode Register */
 #define UCC_GUEMR_MODE_MASK_RX		0x02
 #define UCC_GUEMR_MODE_MASK_TX		0x01
 #define UCC_GUEMR_MODE_FAST_RX		0x02
 #define UCC_GUEMR_MODE_FAST_TX		0x01
 #define UCC_GUEMR_MODE_SLOW_RX		0x00
 #define UCC_GUEMR_MODE_SLOW_TX		0x00
-#define UCC_GUEMR_SET_RESERVED3		0x10 /* Bit 3 must be set 1 */
+/* Bit 3 must be set 1 */
+#define UCC_GUEMR_SET_RESERVED3		0x10
 
-/* General UCC FAST Mode Register
-*/
+/* General UCC FAST Mode Register */
 #define UCC_FAST_GUMR_TCI		0x20000000
 #define UCC_FAST_GUMR_TRX		0x10000000
 #define UCC_FAST_GUMR_TTX		0x08000000
@@ -46,8 +44,7 @@
 #define UCC_FAST_GUMR_ENR		0x00000020
 #define UCC_FAST_GUMR_ENT		0x00000010
 
-/* GUMR [MODE] bit maps
-*/
+/* GUMR [MODE] bit maps */
 #define UCC_FAST_GUMR_HDLC		0x00000000
 #define UCC_FAST_GUMR_QMC		0x00000002
 #define UCC_FAST_GUMR_UART		0x00000004
@@ -55,50 +52,54 @@
 #define UCC_FAST_GUMR_ATM		0x0000000a
 #define UCC_FAST_GUMR_ETH		0x0000000c
 
-/* Transmit On Demand (UTORD)
-*/
+/* Transmit On Demand (UTORD) */
 #define UCC_SLOW_TOD			0x8000
 #define UCC_FAST_TOD			0x8000
 
-/* Fast Ethernet (10/100 Mbps)
-*/
-#define UCC_GETH_URFS_INIT		512        /* Rx virtual FIFO size */
-#define UCC_GETH_URFET_INIT		256        /* 1/2 urfs */
-#define UCC_GETH_URFSET_INIT		384        /* 3/4 urfs */
-#define UCC_GETH_UTFS_INIT		512        /* Tx virtual FIFO size */
-#define UCC_GETH_UTFET_INIT		256        /* 1/2 utfs */
+/* Fast Ethernet (10/100 Mbps) */
+/* Rx virtual FIFO size */
+#define UCC_GETH_URFS_INIT		512
+/* 1/2 urfs */
+#define UCC_GETH_URFET_INIT		256
+/* 3/4 urfs */
+#define UCC_GETH_URFSET_INIT		384
+/* Tx virtual FIFO size */
+#define UCC_GETH_UTFS_INIT		512
+/* 1/2 utfs */
+#define UCC_GETH_UTFET_INIT		256
 #define UCC_GETH_UTFTT_INIT		128
 
-/* Gigabit Ethernet (1000 Mbps)
-*/
-#define UCC_GETH_URFS_GIGA_INIT		4096/*2048*/    /* Rx virtual FIFO size */
-#define UCC_GETH_URFET_GIGA_INIT	2048/*1024*/    /* 1/2 urfs */
-#define UCC_GETH_URFSET_GIGA_INIT	3072/*1536*/    /* 3/4 urfs */
-#define UCC_GETH_UTFS_GIGA_INIT		8192/*2048*/    /* Tx virtual FIFO size */
-#define UCC_GETH_UTFET_GIGA_INIT	4096/*1024*/    /* 1/2 utfs */
-#define UCC_GETH_UTFTT_GIGA_INIT	0x400/*0x40*/   /*  */
+/* Gigabit Ethernet (1000 Mbps) */
+/* Rx virtual FIFO size */
+#define UCC_GETH_URFS_GIGA_INIT		4096/*2048*/
+/* 1/2 urfs */
+#define UCC_GETH_URFET_GIGA_INIT	2048/*1024*/
+/* 3/4 urfs */
+#define UCC_GETH_URFSET_GIGA_INIT	3072/*1536*/
+/* Tx virtual FIFO size */
+#define UCC_GETH_UTFS_GIGA_INIT		8192/*2048*/
+/* 1/2 utfs */
+#define UCC_GETH_UTFET_GIGA_INIT	4096/*1024*/
+#define UCC_GETH_UTFTT_GIGA_INIT	0x400/*0x40*/
 
-/* UCC fast alignment
-*/
+/* UCC fast alignment */
 #define UCC_FAST_RX_ALIGN			4
 #define UCC_FAST_MRBLR_ALIGNMENT		4
 #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
 
-/* Sizes
-*/
+/* Sizes */
 #define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD	8
 
-/* UCC fast structure.
-*/
-typedef struct ucc_fast_info {
+/* UCC fast structure. */
+struct ucc_fast_inf {
 	int		ucc_num;
 	qe_clock_e	rx_clock;
 	qe_clock_e	tx_clock;
-	enet_type_e	eth_type;
-} ucc_fast_info_t;
+	enum enet_type	eth_type;
+};
 
-typedef struct ucc_fast_private {
-	ucc_fast_info_t	*uf_info;
+struct ucc_fast_priv {
+	struct ucc_fast_inf	*uf_info;
 	ucc_fast_t	*uf_regs; /* a pointer to memory map of UCC regs */
 	u32		*p_ucce; /* a pointer to the event register */
 	u32		*p_uccm; /* a pointer to the mask register */
@@ -106,12 +107,13 @@
 	int		enabled_rx; /* whether UCC is enabled for Rx (ENR) */
 	u32		ucc_fast_tx_virtual_fifo_base_offset;
 	u32		ucc_fast_rx_virtual_fifo_base_offset;
-} ucc_fast_private_t;
+};
 
-void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf);
+void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
 u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
-void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode);
-void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode);
-int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret);
+void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
+void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
+int ucc_fast_init(struct ucc_fast_inf *uf_info,
+		  struct ucc_fast_priv **uccf_ret);
 
 #endif /* __UCCF_H__ */

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 0143454..5da971d 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c

@@ -20,12 +20,13 @@
 #include <fsl_qe.h>
 #include <phy.h>
 
+#if !defined(CONFIG_DM_ETH)
 /* Default UTBIPAR SMI address */
 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
 #endif
 
-static uec_info_t uec_info[] = {
+static struct uec_inf uec_info[] = {
 #ifdef CONFIG_UEC_ETH1
 	STD_UEC_INFO(1),	/* UEC1 */
 #endif
@@ -56,13 +57,13 @@
 
 static struct eth_device *devlist[MAXCONTROLLERS];
 
-static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
+static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
 {
 	uec_t		*uec_regs;
 	u32		maccfg1;
 
 	if (!uec) {
-		printf("%s: uec not initial\n", __FUNCTION__);
+		printf("%s: uec not initial\n", __func__);
 		return -EINVAL;
 	}
 	uec_regs = uec->uec_regs;
@@ -84,13 +85,13 @@
 	return 0;
 }
 
-static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
+static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
 {
 	uec_t		*uec_regs;
 	u32		maccfg1;
 
 	if (!uec) {
-		printf("%s: uec not initial\n", __FUNCTION__);
+		printf("%s: uec not initial\n", __func__);
 		return -EINVAL;
 	}
 	uec_regs = uec->uec_regs;
@@ -112,14 +113,14 @@
 	return 0;
 }
 
-static int uec_graceful_stop_tx(uec_private_t *uec)
+static int uec_graceful_stop_tx(struct uec_priv *uec)
 {
 	ucc_fast_t		*uf_regs;
 	u32			cecr_subblock;
 	u32			ucce;
 
 	if (!uec || !uec->uccf) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 
@@ -132,30 +133,30 @@
 	cecr_subblock =
 		 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 	qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
-			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 
 	/* Wait for command to complete */
 	do {
 		ucce = in_be32(&uf_regs->ucce);
-	} while (! (ucce & UCCE_GRA));
+	} while (!(ucce & UCCE_GRA));
 
 	uec->grace_stopped_tx = 1;
 
 	return 0;
 }
 
-static int uec_graceful_stop_rx(uec_private_t *uec)
+static int uec_graceful_stop_rx(struct uec_priv *uec)
 {
 	u32		cecr_subblock;
 	u8		ack;
 
 	if (!uec) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 
 	if (!uec->p_rx_glbl_pram) {
-		printf("%s: No init rx global parameter\n", __FUNCTION__);
+		printf("%s: No init rx global parameter\n", __func__);
 		return -EINVAL;
 	}
 
@@ -170,66 +171,66 @@
 		cecr_subblock =
 		 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 		qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
-				 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+			     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 		ack = uec->p_rx_glbl_pram->rxgstpack;
-	} while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
+	} while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
 
 	uec->grace_stopped_rx = 1;
 
 	return 0;
 }
 
-static int uec_restart_tx(uec_private_t *uec)
+static int uec_restart_tx(struct uec_priv *uec)
 {
 	u32		cecr_subblock;
 
 	if (!uec || !uec->uec_info) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 
 	cecr_subblock =
 	 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 	qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
-			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 
 	uec->grace_stopped_tx = 0;
 
 	return 0;
 }
 
-static int uec_restart_rx(uec_private_t *uec)
+static int uec_restart_rx(struct uec_priv *uec)
 {
 	u32		cecr_subblock;
 
 	if (!uec || !uec->uec_info) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 
 	cecr_subblock =
 	 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 	qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
-			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+		     (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 
 	uec->grace_stopped_rx = 0;
 
 	return 0;
 }
 
-static int uec_open(uec_private_t *uec, comm_dir_e mode)
+static int uec_open(struct uec_priv *uec, comm_dir_e mode)
 {
-	ucc_fast_private_t	*uccf;
+	struct ucc_fast_priv	*uccf;
 
 	if (!uec || !uec->uccf) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 	uccf = uec->uccf;
 
 	/* check if the UCC number is in range. */
 	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
-		printf("%s: ucc_num out of range.\n", __FUNCTION__);
+		printf("%s: ucc_num out of range.\n", __func__);
 		return -EINVAL;
 	}
 
@@ -240,36 +241,33 @@
 	ucc_fast_enable(uccf, mode);
 
 	/* RISC microcode start */
-	if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
+	if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
 		uec_restart_tx(uec);
-	}
-	if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
+	if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
 		uec_restart_rx(uec);
-	}
 
 	return 0;
 }
 
-static int uec_stop(uec_private_t *uec, comm_dir_e mode)
+static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
 {
 	if (!uec || !uec->uccf) {
-		printf("%s: No handle passed.\n", __FUNCTION__);
+		printf("%s: No handle passed.\n", __func__);
 		return -EINVAL;
 	}
 
 	/* check if the UCC number is in range. */
 	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
-		printf("%s: ucc_num out of range.\n", __FUNCTION__);
+		printf("%s: ucc_num out of range.\n", __func__);
 		return -EINVAL;
 	}
 	/* Stop any transmissions */
-	if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
+	if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
 		uec_graceful_stop_tx(uec);
-	}
+
 	/* Stop any receptions */
-	if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
+	if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
 		uec_graceful_stop_rx(uec);
-	}
 
 	/* Disable the UCC fast */
 	ucc_fast_disable(uec->uccf, mode);
@@ -280,13 +278,13 @@
 	return 0;
 }
 
-static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
+static int uec_set_mac_duplex(struct uec_priv *uec, int duplex)
 {
 	uec_t		*uec_regs;
 	u32		maccfg2;
 
 	if (!uec) {
-		printf("%s: uec not initial\n", __FUNCTION__);
+		printf("%s: uec not initial\n", __func__);
 		return -EINVAL;
 	}
 	uec_regs = uec->uec_regs;
@@ -306,8 +304,8 @@
 	return 0;
 }
 
-static int uec_set_mac_if_mode(uec_private_t *uec,
-		phy_interface_t if_mode, int speed)
+static int uec_set_mac_if_mode(struct uec_priv *uec,
+			       phy_interface_t if_mode, int speed)
 {
 	phy_interface_t		enet_if_mode;
 	uec_t			*uec_regs;
@@ -315,7 +313,7 @@
 	u32			maccfg2;
 
 	if (!uec) {
-		printf("%s: uec not initial\n", __FUNCTION__);
+		printf("%s: uec not initial\n", __func__);
 		return -EINVAL;
 	}
 
@@ -329,66 +327,62 @@
 	upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 
 	switch (speed) {
-		case SPEED_10:
-			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
-			switch (enet_if_mode) {
-				case PHY_INTERFACE_MODE_MII:
-					break;
-				case PHY_INTERFACE_MODE_RGMII:
-					upsmr |= (UPSMR_RPM | UPSMR_R10M);
-					break;
-				case PHY_INTERFACE_MODE_RMII:
-					upsmr |= (UPSMR_R10M | UPSMR_RMM);
-					break;
-				default:
-					return -EINVAL;
-					break;
-			}
+	case SPEED_10:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_MII:
 			break;
-		case SPEED_100:
-			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
-			switch (enet_if_mode) {
-				case PHY_INTERFACE_MODE_MII:
-					break;
-				case PHY_INTERFACE_MODE_RGMII:
-					upsmr |= UPSMR_RPM;
-					break;
-				case PHY_INTERFACE_MODE_RMII:
-					upsmr |= UPSMR_RMM;
-					break;
-				default:
-					return -EINVAL;
-					break;
-			}
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= (UPSMR_RPM | UPSMR_R10M);
 			break;
-		case SPEED_1000:
-			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
-			switch (enet_if_mode) {
-				case PHY_INTERFACE_MODE_GMII:
-					break;
-				case PHY_INTERFACE_MODE_TBI:
-					upsmr |= UPSMR_TBIM;
-					break;
-				case PHY_INTERFACE_MODE_RTBI:
-					upsmr |= (UPSMR_RPM | UPSMR_TBIM);
-					break;
-				case PHY_INTERFACE_MODE_RGMII_RXID:
-				case PHY_INTERFACE_MODE_RGMII_TXID:
-				case PHY_INTERFACE_MODE_RGMII_ID:
-				case PHY_INTERFACE_MODE_RGMII:
-					upsmr |= UPSMR_RPM;
-					break;
-				case PHY_INTERFACE_MODE_SGMII:
-					upsmr |= UPSMR_SGMM;
-					break;
-				default:
-					return -EINVAL;
-					break;
-			}
+		case PHY_INTERFACE_MODE_RMII:
+			upsmr |= (UPSMR_R10M | UPSMR_RMM);
 			break;
 		default:
 			return -EINVAL;
+		}
+		break;
+	case SPEED_100:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_MII:
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= UPSMR_RPM;
+			break;
+		case PHY_INTERFACE_MODE_RMII:
+			upsmr |= UPSMR_RMM;
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	case SPEED_1000:
+		maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+		switch (enet_if_mode) {
+		case PHY_INTERFACE_MODE_GMII:
+			break;
+		case PHY_INTERFACE_MODE_TBI:
+			upsmr |= UPSMR_TBIM;
+			break;
+		case PHY_INTERFACE_MODE_RTBI:
+			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
+			break;
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
+		case PHY_INTERFACE_MODE_RGMII:
+			upsmr |= UPSMR_RPM;
 			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			upsmr |= UPSMR_SGMM;
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	default:
+		return -EINVAL;
 	}
 
 	out_be32(&uec_regs->maccfg2, maccfg2);
@@ -407,9 +401,10 @@
 	out_be32(&uec_mii_regs->miimcfg, miimcfg);
 
 	/* Wait until the bus is free */
-	while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+	while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--)
+		;
 	if (timeout <= 0) {
-		printf("%s: The MII Bus is stuck!", __FUNCTION__);
+		printf("%s: The MII Bus is stuck!", __func__);
 		return -ETIMEDOUT;
 	}
 
@@ -418,13 +413,13 @@
 
 static int init_phy(struct eth_device *dev)
 {
-	uec_private_t		*uec;
+	struct uec_priv		*uec;
 	uec_mii_t		*umii_regs;
 	struct uec_mii_info	*mii_info;
 	struct phy_info		*curphy;
 	int			err;
 
-	uec = (uec_private_t *)dev->priv;
+	uec = (struct uec_priv *)dev->priv;
 	umii_regs = uec->uec_mii_regs;
 
 	uec->oldlink = 0;
@@ -438,11 +433,10 @@
 	}
 	memset(mii_info, 0, sizeof(*mii_info));
 
-	if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
+	if (uec->uec_info->uf_info.eth_type == GIGA_ETH)
 		mii_info->speed = SPEED_1000;
-	} else {
+	else
 		mii_info->speed = SPEED_100;
-	}
 
 	mii_info->duplex = DUPLEX_FULL;
 	mii_info->pause = 0;
@@ -498,15 +492,14 @@
 
 static void adjust_link(struct eth_device *dev)
 {
-	uec_private_t		*uec = (uec_private_t *)dev->priv;
+	struct uec_priv		*uec = (struct uec_priv *)dev->priv;
 	struct uec_mii_info	*mii_info = uec->mii_info;
 
-	extern void change_phy_interface_mode(struct eth_device *dev,
-				 phy_interface_t mode, int speed);
-
 	if (mii_info->link) {
-		/* Now we make sure that we can be in full duplex mode.
-		* If not, we operate in half-duplex mode. */
+		/*
+		 * Now we make sure that we can be in full duplex mode.
+		 * If not, we operate in half-duplex mode.
+		 */
 		if (mii_info->duplex != uec->oldduplex) {
 			if (!(mii_info->duplex)) {
 				uec_set_mac_duplex(uec, DUPLEX_HALF);
@@ -526,16 +519,16 @@
 				case SPEED_1000:
 					break;
 				case SPEED_100:
-					printf ("switching to rgmii 100\n");
+					printf("switching to rgmii 100\n");
 					mode = PHY_INTERFACE_MODE_RGMII;
 					break;
 				case SPEED_10:
-					printf ("switching to rgmii 10\n");
+					printf("switching to rgmii 10\n");
 					mode = PHY_INTERFACE_MODE_RGMII;
 					break;
 				default:
 					printf("%s: Ack,Speed(%d)is illegal\n",
-						dev->name, mii_info->speed);
+					       dev->name, mii_info->speed);
 					break;
 				}
 			}
@@ -566,12 +559,12 @@
 
 static void phy_change(struct eth_device *dev)
 {
-	uec_private_t	*uec = (uec_private_t *)dev->priv;
+	struct uec_priv	*uec = (struct uec_priv *)dev->priv;
 
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
-	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
+	/* QE9 and QE12 need to be set for enabling QE MII management signals */
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 #endif
@@ -604,14 +597,14 @@
 	int i;
 
 	for (i = 0; i < MAXCONTROLLERS; i++) {
-		if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
+		if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0)
 			break;
-		}
 	}
 
 	/* If device cannot be found, returns -1 */
 	if (i == MAXCONTROLLERS) {
-		debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
+		debug("%s: device %s not found in devlist\n", __func__,
+		      devname);
 		i = -1;
 	}
 
@@ -629,13 +622,12 @@
 	unsigned short value = 0;
 	int devindex = 0;
 
-	if (bus->name == NULL) {
-		debug("%s: NULL pointer given\n", __FUNCTION__);
+	if (!bus->name) {
+		debug("%s: NULL pointer given\n", __func__);
 	} else {
 		devindex = uec_miiphy_find_dev_by_name(bus->name);
-		if (devindex >= 0) {
+		if (devindex >= 0)
 			value = uec_read_phy_reg(devlist[devindex], addr, reg);
-		}
 	}
 	return value;
 }
@@ -651,36 +643,37 @@
 {
 	int devindex = 0;
 
-	if (bus->name == NULL) {
-		debug("%s: NULL pointer given\n", __FUNCTION__);
+	if (!bus->name) {
+		debug("%s: NULL pointer given\n", __func__);
 	} else {
 		devindex = uec_miiphy_find_dev_by_name(bus->name);
-		if (devindex >= 0) {
+		if (devindex >= 0)
 			uec_write_phy_reg(devlist[devindex], addr, reg, value);
-		}
 	}
 	return 0;
 }
 #endif
 
-static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
+static int uec_set_mac_address(struct uec_priv *uec, u8 *mac_addr)
 {
 	uec_t		*uec_regs;
 	u32		mac_addr1;
 	u32		mac_addr2;
 
 	if (!uec) {
-		printf("%s: uec not initial\n", __FUNCTION__);
+		printf("%s: uec not initial\n", __func__);
 		return -EINVAL;
 	}
 
 	uec_regs = uec->uec_regs;
 
-	/* if a station address of 0x12345678ABCD, perform a write to
-	MACSTNADDR1 of 0xCDAB7856,
-	MACSTNADDR2 of 0x34120000 */
+	/*
+	 * if a station address of 0x12345678ABCD, perform a write to
+	 * MACSTNADDR1 of 0xCDAB7856,
+	 * MACSTNADDR2 of 0x34120000
+	 */
 
-	mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
+	mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) |
 			(mac_addr[3] << 8)  | (mac_addr[2]);
 	out_be32(&uec_regs->macstnaddr1, mac_addr1);
 
@@ -690,31 +683,31 @@
 	return 0;
 }
 
-static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
-					 int *threads_num_ret)
+static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
+				   int *threads_num_ret)
 {
 	int	num_threads_numerica;
 
 	switch (threads_num) {
-		case UEC_NUM_OF_THREADS_1:
-			num_threads_numerica = 1;
-			break;
-		case UEC_NUM_OF_THREADS_2:
-			num_threads_numerica = 2;
-			break;
-		case UEC_NUM_OF_THREADS_4:
-			num_threads_numerica = 4;
-			break;
-		case UEC_NUM_OF_THREADS_6:
-			num_threads_numerica = 6;
-			break;
-		case UEC_NUM_OF_THREADS_8:
-			num_threads_numerica = 8;
-			break;
-		default:
-			printf("%s: Bad number of threads value.",
-				 __FUNCTION__);
-			return -EINVAL;
+	case UEC_NUM_OF_THREADS_1:
+		num_threads_numerica = 1;
+		break;
+	case UEC_NUM_OF_THREADS_2:
+		num_threads_numerica = 2;
+		break;
+	case UEC_NUM_OF_THREADS_4:
+		num_threads_numerica = 4;
+		break;
+	case UEC_NUM_OF_THREADS_6:
+		num_threads_numerica = 6;
+		break;
+	case UEC_NUM_OF_THREADS_8:
+		num_threads_numerica = 8;
+		break;
+	default:
+		printf("%s: Bad number of threads value.",
+		       __func__);
+		return -EINVAL;
 	}
 
 	*threads_num_ret = num_threads_numerica;
@@ -722,9 +715,9 @@
 	return 0;
 }
 
-static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
+static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
 {
-	uec_info_t	*uec_info;
+	struct uec_inf	*uec_info;
 	u32		end_bd;
 	u8		bmrx = 0;
 	int		i;
@@ -732,14 +725,14 @@
 	uec_info = uec->uec_info;
 
 	/* Alloc global Tx parameter RAM page */
-	uec->tx_glbl_pram_offset = qe_muram_alloc(
-				sizeof(uec_tx_global_pram_t),
-				 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
-	uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
+	uec->tx_glbl_pram_offset =
+		qe_muram_alloc(sizeof(struct uec_tx_global_pram),
+			       UEC_TX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
 				qe_muram_addr(uec->tx_glbl_pram_offset);
 
 	/* Zero the global Tx prameter RAM */
-	memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
+	memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
 
 	/* Init global Tx parameter RAM */
 
@@ -747,10 +740,10 @@
 	out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 
 	/* SQPTR */
-	uec->send_q_mem_reg_offset = qe_muram_alloc(
-				sizeof(uec_send_queue_qd_t),
-				 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
-	uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
+	uec->send_q_mem_reg_offset =
+		qe_muram_alloc(sizeof(struct uec_send_queue_qd),
+			       UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
+	uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
 				qe_muram_addr(uec->send_q_mem_reg_offset);
 	out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 
@@ -758,9 +751,9 @@
 	end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 					 * SIZEOFBD;
 	out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
-				 (u32)(uec->p_tx_bd_ring));
+		 (u32)(uec->p_tx_bd_ring));
 	out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
-						 end_bd);
+		 end_bd);
 
 	/* Scheduler Base Pointer, we have only one Tx queue, no need it */
 	out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
@@ -773,54 +766,57 @@
 	out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 
 	/* IPH_Offset */
-	for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
+	for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
 		out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
-	}
 
 	/* VTAG table */
-	for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
+	for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
 		out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
-	}
 
 	/* TQPTR */
-	uec->thread_dat_tx_offset = qe_muram_alloc(
-		num_threads_tx * sizeof(uec_thread_data_tx_t) +
-		 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
+	uec->thread_dat_tx_offset =
+		qe_muram_alloc(num_threads_tx *
+			       sizeof(struct uec_thread_data_tx) +
+			       32 * (num_threads_tx == 1),
+			       UEC_THREAD_DATA_ALIGNMENT);
 
-	uec->p_thread_data_tx = (uec_thread_data_tx_t *)
+	uec->p_thread_data_tx = (struct uec_thread_data_tx *)
 				qe_muram_addr(uec->thread_dat_tx_offset);
 	out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 }
 
-static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
+static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
 {
 	u8	bmrx = 0;
 	int	i;
-	uec_82xx_address_filtering_pram_t	*p_af_pram;
+	struct uec_82xx_add_filtering_pram	*p_af_pram;
 
 	/* Allocate global Rx parameter RAM page */
-	uec->rx_glbl_pram_offset = qe_muram_alloc(
-		sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
-	uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
+	uec->rx_glbl_pram_offset =
+		qe_muram_alloc(sizeof(struct uec_rx_global_pram),
+			       UEC_RX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
 				qe_muram_addr(uec->rx_glbl_pram_offset);
 
 	/* Zero Global Rx parameter RAM */
-	memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
+	memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
 
 	/* Init global Rx parameter RAM */
-	/* REMODER, Extended feature mode disable, VLAN disable,
-	 LossLess flow control disable, Receive firmware statisic disable,
-	 Extended address parsing mode disable, One Rx queues,
-	 Dynamic maximum/minimum frame length disable, IP checksum check
-	 disable, IP address alignment disable
-	*/
+	/*
+	 * REMODER, Extended feature mode disable, VLAN disable,
+	 * LossLess flow control disable, Receive firmware statisic disable,
+	 * Extended address parsing mode disable, One Rx queues,
+	 * Dynamic maximum/minimum frame length disable, IP checksum check
+	 * disable, IP address alignment disable
+	 */
 	out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 
 	/* RQPTR */
-	uec->thread_dat_rx_offset = qe_muram_alloc(
-			num_threads_rx * sizeof(uec_thread_data_rx_t),
-			 UEC_THREAD_DATA_ALIGNMENT);
-	uec->p_thread_data_rx = (uec_thread_data_rx_t *)
+	uec->thread_dat_rx_offset =
+		qe_muram_alloc(num_threads_rx *
+			       sizeof(struct uec_thread_data_rx),
+			       UEC_THREAD_DATA_ALIGNMENT);
+	uec->p_thread_data_rx = (struct uec_thread_data_rx *)
 				qe_muram_addr(uec->thread_dat_rx_offset);
 	out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 
@@ -841,16 +837,16 @@
 	out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 
 	/* RBDQPTR */
-	uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
-				sizeof(uec_rx_bd_queues_entry_t) + \
-				sizeof(uec_rx_prefetched_bds_t),
-				 UEC_RX_BD_QUEUES_ALIGNMENT);
-	uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
+	uec->rx_bd_qs_tbl_offset =
+		qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
+			       sizeof(struct uec_rx_pref_bds),
+			       UEC_RX_BD_QUEUES_ALIGNMENT);
+	uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
 				qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 
 	/* Zero it */
-	memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
-					sizeof(uec_rx_prefetched_bds_t));
+	memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
+	       sizeof(struct uec_rx_pref_bds));
 	out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 	out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 		 (u32)uec->p_rx_bd_ring);
@@ -868,9 +864,8 @@
 	/* L2QT */
 	out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 	/* L3QT */
-	for (i = 0; i < 8; i++)	{
+	for (i = 0; i < 8; i++)
 		out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
-	}
 
 	/* VLAN_TYPE */
 	out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
@@ -878,7 +873,7 @@
 	out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 
 	/* Clear PQ2 style address filtering hash table */
-	p_af_pram = (uec_82xx_address_filtering_pram_t *) \
+	p_af_pram = (struct uec_82xx_add_filtering_pram *)
 			uec->p_rx_glbl_pram->addressfiltering;
 
 	p_af_pram->iaddr_h = 0;
@@ -887,30 +882,33 @@
 	p_af_pram->gaddr_l = 0;
 }
 
-static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
-					 int thread_tx, int thread_rx)
+static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
+					int thread_tx, int thread_rx)
 {
-	uec_init_cmd_pram_t		*p_init_enet_param;
+	struct uec_init_cmd_pram		*p_init_enet_param;
 	u32				init_enet_param_offset;
-	uec_info_t			*uec_info;
+	struct uec_inf			*uec_info;
+	struct ucc_fast_inf			*uf_info;
 	int				i;
 	int				snum;
-	u32				init_enet_offset;
+	u32				off;
 	u32				entry_val;
 	u32				command;
 	u32				cecr_subblock;
 
 	uec_info = uec->uec_info;
+	uf_info = &uec_info->uf_info;
 
 	/* Allocate init enet command parameter */
-	uec->init_enet_param_offset = qe_muram_alloc(
-					sizeof(uec_init_cmd_pram_t), 4);
+	uec->init_enet_param_offset =
+		qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
 	init_enet_param_offset = uec->init_enet_param_offset;
-	uec->p_init_enet_param = (uec_init_cmd_pram_t *)
+	uec->p_init_enet_param = (struct uec_init_cmd_pram *)
 				qe_muram_addr(uec->init_enet_param_offset);
 
 	/* Zero init enet command struct */
-	memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
+	memset((void *)uec->p_init_enet_param, 0,
+	       sizeof(struct uec_init_cmd_pram));
 
 	/* Init the command struct */
 	p_init_enet_param = uec->p_init_enet_param;
@@ -932,21 +930,21 @@
 
 	/* Init Rx threads */
 	for (i = 0; i < (thread_rx + 1); i++) {
-		if ((snum = qe_get_snum()) < 0) {
-			printf("%s can not get snum\n", __FUNCTION__);
+		snum = qe_get_snum();
+		if (snum < 0) {
+			printf("%s can not get snum\n", __func__);
 			return -ENOMEM;
 		}
 
-		if (i==0) {
-			init_enet_offset = 0;
+		if (i == 0) {
+			off = 0;
 		} else {
-			init_enet_offset = qe_muram_alloc(
-					sizeof(uec_thread_rx_pram_t),
-					 UEC_THREAD_RX_PRAM_ALIGNMENT);
+			off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
+					     UEC_THREAD_RX_PRAM_ALIGNMENT);
 		}
 
 		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
-				 init_enet_offset | (u32)uec_info->risc_rx;
+				 off | (u32)uec_info->risc_rx;
 		p_init_enet_param->rxthread[i] = entry_val;
 	}
 
@@ -956,16 +954,17 @@
 
 	/* Init Tx threads */
 	for (i = 0; i < thread_tx; i++) {
-		if ((snum = qe_get_snum()) < 0)	{
-			printf("%s can not get snum\n", __FUNCTION__);
+		snum = qe_get_snum();
+		if (snum  < 0)	{
+			printf("%s can not get snum\n", __func__);
 			return -ENOMEM;
 		}
 
-		init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
-						 UEC_THREAD_TX_PRAM_ALIGNMENT);
+		off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
+				     UEC_THREAD_TX_PRAM_ALIGNMENT);
 
 		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
-				 init_enet_offset | (u32)uec_info->risc_tx;
+				 off | (u32)uec_info->risc_tx;
 		p_init_enet_param->txthread[i] = entry_val;
 	}
 
@@ -973,19 +972,18 @@
 
 	/* Issue QE command */
 	command = QE_INIT_TX_RX;
-	cecr_subblock =	ucc_fast_get_qe_cr_subblock(
-				uec->uec_info->uf_info.ucc_num);
-	qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
-						 init_enet_param_offset);
+	cecr_subblock =	ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
+	qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
+		     init_enet_param_offset);
 
 	return 0;
 }
 
-static int uec_startup(uec_private_t *uec)
+static int uec_startup(struct uec_priv *uec)
 {
-	uec_info_t			*uec_info;
-	ucc_fast_info_t			*uf_info;
-	ucc_fast_private_t		*uccf;
+	struct uec_inf			*uec_info;
+	struct ucc_fast_inf		*uf_info;
+	struct ucc_fast_priv		*uccf;
 	ucc_fast_t			*uf_regs;
 	uec_t				*uec_regs;
 	int				num_threads_tx;
@@ -993,37 +991,37 @@
 	u32				utbipar;
 	u32				length;
 	u32				align;
-	qe_bd_t				*bd;
+	struct buffer_descriptor	*bd;
 	u8				*buf;
 	int				i;
 
 	if (!uec || !uec->uec_info) {
-		printf("%s: uec or uec_info not initial\n", __FUNCTION__);
+		printf("%s: uec or uec_info not initial\n", __func__);
 		return -EINVAL;
 	}
 
 	uec_info = uec->uec_info;
-	uf_info = &(uec_info->uf_info);
+	uf_info = &uec_info->uf_info;
 
 	/* Check if Rx BD ring len is illegal */
-	if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
-		(uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
+	if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
+	    (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
 		printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
-			 __FUNCTION__);
+		       __func__);
 		return -EINVAL;
 	}
 
 	/* Check if Tx BD ring len is illegal */
 	if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
 		printf("%s: Tx BD ring length must not be smaller than 2.\n",
-			 __FUNCTION__);
+		       __func__);
 		return -EINVAL;
 	}
 
 	/* Check if MRBLR is illegal */
-	if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
+	if (MAX_RXBUF_LEN == 0 || MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT) {
 		printf("%s: max rx buffer length must be mutliple of 128.\n",
-			 __FUNCTION__);
+		       __func__);
 		return -EINVAL;
 	}
 
@@ -1033,7 +1031,7 @@
 
 	/* Init UCC fast */
 	if (ucc_fast_init(uf_info, &uccf)) {
-		printf("%s: failed to init ucc fast\n", __FUNCTION__);
+		printf("%s: failed to init ucc fast\n", __func__);
 		return -ENOMEM;
 	}
 
@@ -1042,13 +1040,13 @@
 
 	/* Convert the Tx threads number */
 	if (uec_convert_threads_num(uec_info->num_threads_tx,
-					 &num_threads_tx)) {
+				    &num_threads_tx)) {
 		return -EINVAL;
 	}
 
 	/* Convert the Rx threads number */
 	if (uec_convert_threads_num(uec_info->num_threads_rx,
-					 &num_threads_rx)) {
+				    &num_threads_rx)) {
 		return -EINVAL;
 	}
 
@@ -1070,13 +1068,14 @@
 	out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
 
 	/* Setup MAC interface mode */
-	uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
+	uec_set_mac_if_mode(uec, uec_info->enet_interface_type,
+			    uec_info->speed);
 
 	/* Setup MII management base */
 #ifndef CONFIG_eTSEC_MDIO_BUS
 	uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
 #else
-	uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
+	uec->uec_mii_regs = (uec_mii_t *)CONFIG_MIIM_ADDRESS;
 #endif
 
 	/* Setup MII master clock source */
@@ -1093,16 +1092,16 @@
 	out_be32(&uec_regs->utbipar, utbipar);
 
 	/* Configure the TBI for SGMII operation */
-	if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
-	   (uec->uec_info->speed == SPEED_1000)) {
+	if (uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII &&
+	    uec->uec_info->speed == SPEED_1000) {
 		uec_write_phy_reg(uec->dev, uec_regs->utbipar,
-			ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+				  ENET_TBI_MII_ANA, TBIANA_SETTINGS);
 
 		uec_write_phy_reg(uec->dev, uec_regs->utbipar,
-			ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+				  ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
 
 		uec_write_phy_reg(uec->dev, uec_regs->utbipar,
-			ENET_TBI_MII_CR, TBICR_SETTINGS);
+				  ENET_TBI_MII_CR, TBICR_SETTINGS);
 	}
 
 	/* Allocate Tx BDs */
@@ -1149,29 +1148,29 @@
 	memset((void *)(uec->rx_buf_offset), 0, length + align);
 
 	/* Init TxBD ring */
-	bd = (qe_bd_t *)uec->p_tx_bd_ring;
-	uec->txBd = bd;
+	bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
+	uec->tx_bd = bd;
 
 	for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
 		BD_DATA_CLEAR(bd);
 		BD_STATUS_SET(bd, 0);
 		BD_LENGTH_SET(bd, 0);
-		bd ++;
+		bd++;
 	}
-	BD_STATUS_SET((--bd), TxBD_WRAP);
+	BD_STATUS_SET((--bd), TX_BD_WRAP);
 
 	/* Init RxBD ring */
-	bd = (qe_bd_t *)uec->p_rx_bd_ring;
-	uec->rxBd = bd;
+	bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
+	uec->rx_bd = bd;
 	buf = uec->p_rx_buf;
 	for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
 		BD_DATA_SET(bd, buf);
 		BD_LENGTH_SET(bd, 0);
-		BD_STATUS_SET(bd, RxBD_EMPTY);
+		BD_STATUS_SET(bd, RX_BD_EMPTY);
 		buf += MAX_RXBUF_LEN;
-		bd ++;
+		bd++;
 	}
-	BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
+	BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
 
 	/* Init global Tx parameter RAM */
 	uec_init_tx_parameter(uec, num_threads_tx);
@@ -1182,29 +1181,32 @@
 	/* Init ethernet Tx and Rx parameter command */
 	if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
 					 num_threads_rx)) {
-		printf("%s issue init enet cmd failed\n", __FUNCTION__);
+		printf("%s issue init enet cmd failed\n", __func__);
 		return -ENOMEM;
 	}
 
 	return 0;
 }
 
-static int uec_init(struct eth_device* dev, struct bd_info *bd)
+static int uec_init(struct eth_device *dev, struct bd_info *bd)
 {
-	uec_private_t		*uec;
+	struct uec_priv		*uec;
 	int			err, i;
 	struct phy_info         *curphy;
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
-	uec = (uec_private_t *)dev->priv;
+	uec = (struct uec_priv *)dev->priv;
 
-	if (uec->the_first_run == 0) {
+	if (!uec->the_first_run) {
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
-	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+		/*
+		 * QE9 and QE12 need to be set for enabling QE MII
+		 * management signals
+		 */
+		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 #endif
 
 		err = init_phy(dev);
@@ -1230,7 +1232,7 @@
 			err = curphy->read_status(uec->mii_info);
 			if (!(((i-- > 0) && !uec->mii_info->link) || err))
 				break;
-			udelay(100000);
+			mdelay(100);
 		} while (1);
 
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
@@ -1248,12 +1250,11 @@
 	/* Set up the MAC address */
 	if (dev->enetaddr[0] & 0x01) {
 		printf("%s: MacAddress is multcast address\n",
-			 __FUNCTION__);
+		       __func__);
 		return -1;
 	}
 	uec_set_mac_address(uec, dev->enetaddr);
 
-
 	err = uec_open(uec, COMM_DIR_RX_AND_TX);
 	if (err) {
 		printf("%s: cannot enable UEC device\n", dev->name);
@@ -1262,30 +1263,31 @@
 
 	phy_change(dev);
 
-	return (uec->mii_info->link ? 0 : -1);
+	return uec->mii_info->link ? 0 : -1;
 }
 
-static void uec_halt(struct eth_device* dev)
+static void uec_halt(struct eth_device *dev)
 {
-	uec_private_t	*uec = (uec_private_t *)dev->priv;
+	struct uec_priv	*uec = (struct uec_priv *)dev->priv;
+
 	uec_stop(uec, COMM_DIR_RX_AND_TX);
 }
 
 static int uec_send(struct eth_device *dev, void *buf, int len)
 {
-	uec_private_t		*uec;
-	ucc_fast_private_t	*uccf;
-	volatile qe_bd_t	*bd;
+	struct uec_priv		*uec;
+	struct ucc_fast_priv	*uccf;
+	struct buffer_descriptor	*bd;
 	u16			status;
 	int			i;
 	int			result = 0;
 
-	uec = (uec_private_t *)dev->priv;
+	uec = (struct uec_priv *)dev->priv;
 	uccf = uec->uccf;
-	bd = uec->txBd;
+	bd = uec->tx_bd;
 
 	/* Find an empty TxBD */
-	for (i = 0; bd->status & TxBD_READY; i++) {
+	for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
 		if (i > 0x100000) {
 			printf("%s: tx buffer not ready\n", dev->name);
 			return result;
@@ -1295,16 +1297,16 @@
 	/* Init TxBD */
 	BD_DATA_SET(bd, buf);
 	BD_LENGTH_SET(bd, len);
-	status = bd->status;
+	status = BD_STATUS(bd);
 	status &= BD_WRAP;
-	status |= (TxBD_READY | TxBD_LAST);
+	status |= (TX_BD_READY | TX_BD_LAST);
 	BD_STATUS_SET(bd, status);
 
 	/* Tell UCC to transmit the buffer */
 	ucc_fast_transmit_on_demand(uccf);
 
 	/* Wait for buffer to be transmitted */
-	for (i = 0; bd->status & TxBD_READY; i++) {
+	for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
 		if (i > 0x100000) {
 			printf("%s: tx error\n", dev->name);
 			return result;
@@ -1313,25 +1315,25 @@
 
 	/* Ok, the buffer be transimitted */
 	BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
-	uec->txBd = bd;
+	uec->tx_bd = bd;
 	result = 1;
 
 	return result;
 }
 
-static int uec_recv(struct eth_device* dev)
+static int uec_recv(struct eth_device *dev)
 {
-	uec_private_t		*uec = dev->priv;
-	volatile qe_bd_t	*bd;
+	struct uec_priv		*uec = dev->priv;
+	struct buffer_descriptor	*bd;
 	u16			status;
 	u16			len;
 	u8			*data;
 
-	bd = uec->rxBd;
-	status = bd->status;
+	bd = uec->rx_bd;
+	status = BD_STATUS(bd);
 
-	while (!(status & RxBD_EMPTY)) {
-		if (!(status & RxBD_ERROR)) {
+	while (!(status & RX_BD_EMPTY)) {
+		if (!(status & RX_BD_ERROR)) {
 			data = BD_DATA(bd);
 			len = BD_LENGTH(bd);
 			net_process_received_packet(data, len);
@@ -1340,20 +1342,20 @@
 		}
 		status &= BD_CLEAN;
 		BD_LENGTH_SET(bd, 0);
-		BD_STATUS_SET(bd, status | RxBD_EMPTY);
+		BD_STATUS_SET(bd, status | RX_BD_EMPTY);
 		BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
-		status = bd->status;
+		status = BD_STATUS(bd);
 	}
-	uec->rxBd = bd;
+	uec->rx_bd = bd;
 
 	return 1;
 }
 
-int uec_initialize(struct bd_info *bis, uec_info_t *uec_info)
+int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info)
 {
 	struct eth_device	*dev;
 	int			i;
-	uec_private_t		*uec;
+	struct uec_priv		*uec;
 	int			err;
 
 	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
@@ -1362,11 +1364,11 @@
 	memset(dev, 0, sizeof(struct eth_device));
 
 	/* Allocate the UEC private struct */
-	uec = (uec_private_t *)malloc(sizeof(uec_private_t));
-	if (!uec) {
+	uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
+	if (!uec)
 		return -ENOMEM;
-	}
-	memset(uec, 0, sizeof(uec_private_t));
+
+	memset(uec, 0, sizeof(struct uec_priv));
 
 	/* Adjust uec_info */
 #if (MAX_QE_RISC == 4)
@@ -1395,13 +1397,14 @@
 
 	err = uec_startup(uec);
 	if (err) {
-		printf("%s: Cannot configure net device, aborting.",dev->name);
+		printf("%s: Cannot configure net device, aborting.", dev->name);
 		return err;
 	}
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 	int retval;
 	struct mii_dev *mdiodev = mdio_alloc();
+
 	if (!mdiodev)
 		return -ENOMEM;
 	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
@@ -1416,7 +1419,7 @@
 	return 1;
 }
 
-int uec_eth_init(struct bd_info *bis, uec_info_t *uecs, int num)
+int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num)
 {
 	int i;
 
@@ -1430,3 +1433,4 @@
 {
 	return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
 }
+#endif

diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 6de2ac4..83461c0 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h

@@ -76,8 +76,7 @@
 #define MACCFG2_INIT_VALUE	(MACCFG2_PREL | MACCFG2_RESERVED_1 | \
 				 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
 
-/* UEC Event Register
-*/
+/* UEC Event Register */
 #define UCCE_MPD				0x80000000
 #define UCCE_SCAR				0x40000000
 #define UCCE_GRA				0x20000000
@@ -120,26 +119,24 @@
 #define UCCE_OTHER	(UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
 			 UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 
-/* UEC TEMODR Register
-*/
+/* UEC TEMODR Register */
 #define TEMODER_SCHEDULER_ENABLE		0x2000
 #define TEMODER_IP_CHECKSUM_GENERATE		0x0400
 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1	0x0200
 #define TEMODER_RMON_STATISTICS			0x0100
-#define TEMODER_NUM_OF_QUEUES_SHIFT		(15-15)
+#define TEMODER_NUM_OF_QUEUES_SHIFT		(15 - 15)
 
 #define TEMODER_INIT_VALUE			0xc000
 
-/* UEC REMODR Register
-*/
+/* UEC REMODR Register */
 #define REMODER_RX_RMON_STATISTICS_ENABLE	0x00001000
 #define REMODER_RX_EXTENDED_FEATURES		0x80000000
-#define REMODER_VLAN_OPERATION_TAGGED_SHIFT	(31-9 )
-#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT	(31-10)
-#define REMODER_RX_QOS_MODE_SHIFT		(31-15)
+#define REMODER_VLAN_OPERATION_TAGGED_SHIFT	(31 - 9)
+#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT	(31 - 10)
+#define REMODER_RX_QOS_MODE_SHIFT		(31 - 15)
 #define REMODER_RMON_STATISTICS			0x00001000
 #define REMODER_RX_EXTENDED_FILTERING		0x00000800
-#define REMODER_NUM_OF_QUEUES_SHIFT		(31-23)
+#define REMODER_NUM_OF_QUEUES_SHIFT		(31 - 23)
 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH	0x00000008
 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH	0x00000004
 #define REMODER_IP_CHECKSUM_CHECK		0x00000002
@@ -213,35 +210,31 @@
 #define UESCR_SCOV_SHIFT			(15 - 15)
 
 /****** Tx data struct collection ******/
-/* Tx thread data, each Tx thread has one this struct.
-*/
-typedef struct uec_thread_data_tx {
+/* Tx thread data, each Tx thread has one this struct. */
+struct uec_thread_data_tx {
 	u8   res0[136];
-} __attribute__ ((packed)) uec_thread_data_tx_t;
+} __packed;
 
-/* Tx thread parameter, each Tx thread has one this struct.
-*/
-typedef struct uec_thread_tx_pram {
+/* Tx thread parameter, each Tx thread has one this struct. */
+struct uec_thread_tx_pram {
 	u8   res0[64];
-} __attribute__ ((packed)) uec_thread_tx_pram_t;
+} __packed;
 
-/* Send queue queue-descriptor, each Tx queue has one this QD
-*/
-typedef struct uec_send_queue_qd {
+/* Send queue queue-descriptor, each Tx queue has one this QD */
+struct uec_send_queue_qd {
 	u32    bd_ring_base; /* pointer to BD ring base address */
 	u8     res0[0x8];
 	u32    last_bd_completed_address; /* last entry in BD ring */
 	u8     res1[0x30];
-} __attribute__ ((packed)) uec_send_queue_qd_t;
+} __packed;
 
 /* Send queue memory region */
-typedef struct uec_send_queue_mem_region {
-	uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
-} __attribute__ ((packed)) uec_send_queue_mem_region_t;
+struct uec_send_queue_mem_region {
+	struct uec_send_queue_qd   sqqd[MAX_TX_QUEUES];
+} __packed;
 
-/* Scheduler struct
-*/
-typedef struct uec_scheduler {
+/* Scheduler struct */
+struct uec_scheduler {
 	u16  cpucount0;        /* CPU packet counter */
 	u16  cpucount1;        /* CPU packet counter */
 	u16  cecount0;         /* QE  packet counter */
@@ -272,12 +265,11 @@
 	u8   oldwfqmask;       /* temporary variable handled by QE */
 	u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
 	u32  minw;             /* temporary variable handled by QE */
-	u8   res1[0x70-0x64];
-} __attribute__ ((packed)) uec_scheduler_t;
+	u8   res1[0x70 - 0x64];
+} __packed;
 
-/* Tx firmware counters
-*/
-typedef struct uec_tx_firmware_statistics_pram {
+/* Tx firmware counters */
+struct uec_tx_firmware_statistics_pram {
 	u32  sicoltx;            /* single collision */
 	u32  mulcoltx;           /* multiple collision */
 	u32  latecoltxfr;        /* late collision */
@@ -290,13 +282,12 @@
 	u32  txpkts512;          /* total packets(including bad) 512~1023B */
 	u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
 	u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
-} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
+} __packed;
 
-/* Tx global parameter table
-*/
-typedef struct uec_tx_global_pram {
+/* Tx global parameter table */
+struct uec_tx_global_pram {
 	u16  temoder;
-	u8   res0[0x38-0x02];
+	u8   res0[0x38 - 0x02];
 	u32  sqptr;
 	u32  schedulerbasepointer;
 	u32  txrmonbaseptr;
@@ -304,26 +295,22 @@
 	u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
 	u32  vtagtable[0x8];
 	u32  tqptr;
-	u8   res2[0x80-0x74];
-} __attribute__ ((packed)) uec_tx_global_pram_t;
-
+	u8   res2[0x80 - 0x74];
+} __packed;
 
 /****** Rx data struct collection ******/
-/* Rx thread data, each Rx thread has one this struct.
-*/
-typedef struct uec_thread_data_rx {
+/* Rx thread data, each Rx thread has one this struct. */
+struct uec_thread_data_rx {
 	u8   res0[40];
-} __attribute__ ((packed)) uec_thread_data_rx_t;
+} __packed;
 
-/* Rx thread parameter, each Rx thread has one this struct.
-*/
-typedef struct uec_thread_rx_pram {
+/* Rx thread parameter, each Rx thread has one this struct. */
+struct uec_thread_rx_pram {
 	u8   res0[128];
-} __attribute__ ((packed)) uec_thread_rx_pram_t;
+} __packed;
 
-/* Rx firmware counters
-*/
-typedef struct uec_rx_firmware_statistics_pram {
+/* Rx firmware counters */
+struct uec_rx_firmware_statistics_pram {
 	u32   frrxfcser;         /* frames with crc error */
 	u32   fraligner;         /* frames with alignment error */
 	u32   inrangelenrxer;    /* in range length error */
@@ -346,44 +333,41 @@
 	u32   removevlan;
 	u32   replacevlan;
 	u32   insertvlan;
-} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
+} __packed;
 
-/* Rx interrupt coalescing entry, each Rx queue has one this entry.
-*/
-typedef struct uec_rx_interrupt_coalescing_entry {
+/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
+struct uec_rx_interrupt_coalescing_entry {
 	u32   maxvalue;
 	u32   counter;
-} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
+} __packed;
 
-typedef struct uec_rx_interrupt_coalescing_table {
-	uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
-} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
+struct uec_rx_interrupt_coalescing_table {
+	struct uec_rx_interrupt_coalescing_entry   entry[MAX_RX_QUEUES];
+} __packed;
 
-/* RxBD queue entry, each Rx queue has one this entry.
-*/
-typedef struct uec_rx_bd_queues_entry {
+/* RxBD queue entry, each Rx queue has one this entry. */
+struct uec_rx_bd_queues_entry {
 	u32   bdbaseptr;         /* BD base pointer          */
 	u32   bdptr;             /* BD pointer               */
 	u32   externalbdbaseptr; /* external BD base pointer */
 	u32   externalbdptr;     /* external BD pointer      */
-} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
+} __packed;
 
-/* Rx global paramter table
-*/
-typedef struct uec_rx_global_pram {
+/* Rx global parameter table */
+struct uec_rx_global_pram {
 	u32  remoder;             /* ethernet mode reg. */
 	u32  rqptr;               /* base pointer to the Rx Queues */
 	u32  res0[0x1];
-	u8   res1[0x20-0xC];
+	u8   res1[0x20 - 0xc];
 	u16  typeorlen;
 	u8   res2[0x1];
 	u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
 	u32  rxrmonbaseptr;       /* Rx RMON statistics base */
-	u8   res3[0x30-0x28];
+	u8   res3[0x30 - 0x28];
 	u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
-	u8   res4[0x36-0x34];
+	u8   res4[0x36 - 0x34];
 	u8   rstate;
-	u8   res5[0x46-0x37];
+	u8   res5[0x46 - 0x37];
 	u16  mrblr;               /* max receive buffer length reg. */
 	u32  rbdqptr;             /* RxBD parameter table description */
 	u16  mflr;                /* max frame length reg. */
@@ -396,17 +380,15 @@
 	u16  vlantype;            /* vlan type */
 	u16  vlantci;             /* default vlan tci */
 	u8   addressfiltering[64];/* address filtering data structure */
-	u32  exfGlobalParam;      /* extended filtering global parameters */
-	u8   res6[0x100-0xC4];    /* Initialize to zero */
-} __attribute__ ((packed)) uec_rx_global_pram_t;
+	u32  exf_global_param;      /* extended filtering global parameters */
+	u8   res6[0x100 - 0xc4];    /* Initialize to zero */
+} __packed;
 
 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 
-
 /****** UEC common ******/
-/* UCC statistics - hardware counters
-*/
-typedef struct uec_hardware_statistics {
+/* UCC statistics - hardware counters */
+struct uec_hardware_statistics {
 	u32 tx64;
 	u32 tx127;
 	u32 tx255;
@@ -422,11 +404,10 @@
 	u32 rbyt;
 	u32 rmca;
 	u32 rbca;
-} __attribute__ ((packed)) uec_hardware_statistics_t;
+} __packed;
 
-/* InitEnet command parameter
-*/
-typedef struct uec_init_cmd_pram {
+/* InitEnet command parameter */
+struct uec_init_cmd_pram {
 	u8   resinit0;
 	u8   resinit1;
 	u8   resinit2;
@@ -440,7 +421,7 @@
 	u32  txglobal;				   /* tx global  */
 	u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
 	u8   res3[0x1];
-} __attribute__ ((packed)) uec_init_cmd_pram_t;
+} __packed;
 
 #define ENET_INIT_PARAM_RGF_SHIFT		(32 - 4)
 #define ENET_INIT_PARAM_TGF_SHIFT		(32 - 8)
@@ -456,105 +437,96 @@
 #define ENET_INIT_PARAM_MAGIC_RES_INIT3		0x00
 #define ENET_INIT_PARAM_MAGIC_RES_INIT4		0x0400
 
-/* structure representing 82xx Address Filtering Enet Address in PRAM
-*/
-typedef struct uec_82xx_enet_address {
+/* structure representing 82xx Address Filtering Enet Address in PRAM */
+struct uec_82xx_enet_addr {
 	u8   res1[0x2];
 	u16  h;       /* address (MSB) */
 	u16  m;       /* address       */
 	u16  l;       /* address (LSB) */
-} __attribute__ ((packed)) uec_82xx_enet_address_t;
+} __packed;
 
-/* structure representing 82xx Address Filtering PRAM
-*/
-typedef struct uec_82xx_address_filtering_pram {
+/* structure representing 82xx Address Filtering PRAM */
+struct uec_82xx_add_filtering_pram {
 	u32  iaddr_h;        /* individual address filter, high */
 	u32  iaddr_l;        /* individual address filter, low  */
 	u32  gaddr_h;        /* group address filter, high      */
 	u32  gaddr_l;        /* group address filter, low       */
-	uec_82xx_enet_address_t    taddr;
-	uec_82xx_enet_address_t    paddr[4];
-	u8                         res0[0x40-0x38];
-} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
+	struct uec_82xx_enet_addr    taddr;
+	struct uec_82xx_enet_addr    paddr[4];
+	u8                         res0[0x40 - 0x38];
+} __packed;
 
-/* Buffer Descriptor
-*/
-typedef struct buffer_descriptor {
+/* Buffer Descriptor */
+struct buffer_descriptor {
 	u16 status;
 	u16 len;
 	u32 data;
-} __attribute__ ((packed)) qe_bd_t, *p_bd_t;
+} __packed;
 
-#define	SIZEOFBD		sizeof(qe_bd_t)
+#define	SIZEOFBD	sizeof(struct buffer_descriptor)
 
-/* Common BD flags
-*/
+/* Common BD flags */
 #define BD_WRAP			0x2000
 #define BD_INT			0x1000
 #define BD_LAST			0x0800
 #define BD_CLEAN		0x3000
 
-/* TxBD status flags
-*/
-#define TxBD_READY		0x8000
-#define TxBD_PADCRC		0x4000
-#define TxBD_WRAP		BD_WRAP
-#define TxBD_INT		BD_INT
-#define TxBD_LAST		BD_LAST
-#define TxBD_TXCRC		0x0400
-#define TxBD_DEF		0x0200
-#define TxBD_PP			0x0100
-#define TxBD_LC			0x0080
-#define TxBD_RL			0x0040
-#define TxBD_RC			0x003C
-#define TxBD_UNDERRUN		0x0002
-#define TxBD_TRUNC		0x0001
+/* TxBD status flags */
+#define TX_BD_READY		0x8000
+#define TX_BD_PADCRC		0x4000
+#define TX_BD_WRAP		BD_WRAP
+#define TX_BD_INT		BD_INT
+#define TX_BD_LAST		BD_LAST
+#define TX_BD_TXCRC		0x0400
+#define TX_BD_DEF		0x0200
+#define TX_BD_PP			0x0100
+#define TX_BD_LC			0x0080
+#define TX_BD_RL			0x0040
+#define TX_BD_RC			0x003C
+#define TX_BD_UNDERRUN		0x0002
+#define TX_BD_TRUNC		0x0001
 
-#define TxBD_ERROR		(TxBD_UNDERRUN | TxBD_TRUNC)
+#define TX_BD_ERROR		(TX_BD_UNDERRUN | TX_BD_TRUNC)
 
-/* RxBD status flags
-*/
-#define RxBD_EMPTY		0x8000
-#define RxBD_OWNER		0x4000
-#define RxBD_WRAP		BD_WRAP
-#define RxBD_INT		BD_INT
-#define RxBD_LAST		BD_LAST
-#define RxBD_FIRST		0x0400
-#define RxBD_CMR		0x0200
-#define RxBD_MISS		0x0100
-#define RxBD_BCAST		0x0080
-#define RxBD_MCAST		0x0040
-#define RxBD_LG			0x0020
-#define RxBD_NO			0x0010
-#define RxBD_SHORT		0x0008
-#define RxBD_CRCERR		0x0004
-#define RxBD_OVERRUN		0x0002
-#define RxBD_IPCH		0x0001
+/* RxBD status flags */
+#define RX_BD_EMPTY		0x8000
+#define RX_BD_OWNER		0x4000
+#define RX_BD_WRAP		BD_WRAP
+#define RX_BD_INT		BD_INT
+#define RX_BD_LAST		BD_LAST
+#define RX_BD_FIRST		0x0400
+#define RX_BD_CMR		0x0200
+#define RX_BD_MISS		0x0100
+#define RX_BD_BCAST		0x0080
+#define RX_BD_MCAST		0x0040
+#define RX_BD_LG			0x0020
+#define RX_BD_NO			0x0010
+#define RX_BD_SHORT		0x0008
+#define RX_BD_CRCERR		0x0004
+#define RX_BD_OVERRUN		0x0002
+#define RX_BD_IPCH		0x0001
 
-#define RxBD_ERROR		(RxBD_LG | RxBD_NO | RxBD_SHORT | \
-				 RxBD_CRCERR | RxBD_OVERRUN)
+#define RX_BD_ERROR		(RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
+				 RX_BD_CRCERR | RX_BD_OVERRUN)
 
-/* BD access macros
-*/
-#define BD_STATUS(_bd)			(((p_bd_t)(_bd))->status)
-#define BD_STATUS_SET(_bd, _val)	(((p_bd_t)(_bd))->status = _val)
-#define BD_LENGTH(_bd)			(((p_bd_t)(_bd))->len)
-#define BD_LENGTH_SET(_bd, _val)	(((p_bd_t)(_bd))->len = _val)
-#define BD_DATA_CLEAR(_bd)		(((p_bd_t)(_bd))->data = 0)
-#define BD_IS_DATA(_bd)			(((p_bd_t)(_bd))->data)
-#define BD_DATA(_bd)			((u8 *)(((p_bd_t)(_bd))->data))
-#define BD_DATA_SET(_bd, _data)		(((p_bd_t)(_bd))->data = (u32)(_data))
-#define BD_ADVANCE(_bd,_status,_base)	\
-	(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
+/* BD access macros */
+#define BD_STATUS(_bd)		(in_be16(&((_bd)->status)))
+#define BD_STATUS_SET(_bd, _v)	(out_be16(&((_bd)->status), _v))
+#define BD_LENGTH(_bd)		(in_be16(&((_bd)->len)))
+#define BD_LENGTH_SET(_bd, _v)	(out_be16(&((_bd)->len), _v))
+#define BD_DATA_CLEAR(_bd)	(out_be32(&((_bd)->data), 0))
+#define BD_DATA(_bd)		((u8 *)(((_bd)->data)))
+#define BD_DATA_SET(_bd, _data)	(out_be32(&((_bd)->data), (u32)_data))
+#define BD_ADVANCE(_bd, _status, _base)	\
+	(((_status) & BD_WRAP) ? (_bd) = \
+	 ((struct buffer_descriptor *)(_base)) : ++(_bd))
 
-/* Rx Prefetched BDs
-*/
-typedef struct uec_rx_prefetched_bds {
-    qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
-} __attribute__ ((packed)) uec_rx_prefetched_bds_t;
+/* Rx Prefetched BDs */
+struct uec_rx_pref_bds {
+	struct buffer_descriptor   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
+} __packed;
 
-/* Alignments
- */
+/* Alignments */
 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT				64
 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT				64
 #define UEC_THREAD_RX_PRAM_ALIGNMENT				128
@@ -581,25 +553,8 @@
 #define UEC_RX_BD_RING_SIZE_MIN					8
 #define UEC_TX_BD_RING_SIZE_MIN					2
 
-/* Ethernet speed
-*/
-typedef enum enet_speed {
-	ENET_SPEED_10BT,   /* 10 Base T */
-	ENET_SPEED_100BT,  /* 100 Base T */
-	ENET_SPEED_1000BT  /* 1000 Base T */
-} enet_speed_e;
-
-/* Ethernet Address Type.
-*/
-typedef enum enet_addr_type {
-	ENET_ADDR_TYPE_INDIVIDUAL,
-	ENET_ADDR_TYPE_GROUP,
-	ENET_ADDR_TYPE_BROADCAST
-} enet_addr_type_e;
-
-/* TBI / MII Set Register
-*/
-typedef enum enet_tbi_mii_reg {
+/* TBI / MII Set Register */
+enum enet_tbi_mii_reg {
 	ENET_TBI_MII_CR        = 0x00,
 	ENET_TBI_MII_SR        = 0x01,
 	ENET_TBI_MII_ANA       = 0x04,
@@ -610,7 +565,7 @@
 	ENET_TBI_MII_EXST      = 0x0F,
 	ENET_TBI_MII_JD        = 0x10,
 	ENET_TBI_MII_TBICON    = 0x11
-} enet_tbi_mii_reg_e;
+};
 
 /* TBI MDIO register bit fields*/
 #define TBICON_CLK_SELECT	0x0020
@@ -637,18 +592,16 @@
 		| TBICR_SPEED1_SET \
 		)
 
-/* UEC number of threads
-*/
-typedef enum uec_num_of_threads {
+/* UEC number of threads */
+enum uec_num_of_threads {
 	UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
 	UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
 	UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
 	UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
 	UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
-} uec_num_of_threads_e;
+};
 
-/* UEC initialization info struct
-*/
+/* UEC initialization info struct */
 #define STD_UEC_INFO(num) \
 {			\
 	.uf_info		= {	\
@@ -668,10 +621,10 @@
 	.speed			= CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
 }
 
-typedef struct uec_info {
-	ucc_fast_info_t			uf_info;
-	uec_num_of_threads_e		num_threads_tx;
-	uec_num_of_threads_e		num_threads_rx;
+struct uec_inf {
+	struct ucc_fast_inf		uf_info;
+	enum uec_num_of_threads		num_threads_tx;
+	enum uec_num_of_threads		num_threads_rx;
 	unsigned int			risc_tx;
 	unsigned int			risc_rx;
 	u16				rx_bd_ring_len;
@@ -679,39 +632,37 @@
 	u8				phy_address;
 	phy_interface_t			enet_interface_type;
 	int				speed;
-} uec_info_t;
+};
 
-/* UEC driver initialized info
-*/
+/* UEC driver initialized info */
 #define MAX_RXBUF_LEN			1536
 #define MAX_FRAME_LEN			1518
 #define MIN_FRAME_LEN			64
 #define MAX_DMA1_LEN			1520
 #define MAX_DMA2_LEN			1520
 
-/* UEC driver private struct
-*/
-typedef struct uec_private {
-	uec_info_t			*uec_info;
-	ucc_fast_private_t		*uccf;
+/* UEC driver private struct */
+struct uec_priv {
+	struct uec_inf			*uec_info;
+	struct ucc_fast_priv		*uccf;
 	struct eth_device		*dev;
 	uec_t				*uec_regs;
 	uec_mii_t			*uec_mii_regs;
 	/* enet init command parameter */
-	uec_init_cmd_pram_t		*p_init_enet_param;
+	struct uec_init_cmd_pram		*p_init_enet_param;
 	u32				init_enet_param_offset;
-	/* Rx and Tx paramter */
-	uec_rx_global_pram_t		*p_rx_glbl_pram;
+	/* Rx and Tx parameter */
+	struct uec_rx_global_pram		*p_rx_glbl_pram;
 	u32				rx_glbl_pram_offset;
-	uec_tx_global_pram_t		*p_tx_glbl_pram;
+	struct uec_tx_global_pram		*p_tx_glbl_pram;
 	u32				tx_glbl_pram_offset;
-	uec_send_queue_mem_region_t	*p_send_q_mem_reg;
+	struct uec_send_queue_mem_region	*p_send_q_mem_reg;
 	u32				send_q_mem_reg_offset;
-	uec_thread_data_tx_t		*p_thread_data_tx;
+	struct uec_thread_data_tx		*p_thread_data_tx;
 	u32				thread_dat_tx_offset;
-	uec_thread_data_rx_t		*p_thread_data_rx;
+	struct uec_thread_data_rx		*p_thread_data_rx;
 	u32				thread_dat_rx_offset;
-	uec_rx_bd_queues_entry_t	*p_rx_bd_qs_tbl;
+	struct uec_rx_bd_queues_entry	*p_rx_bd_qs_tbl;
 	u32				rx_bd_qs_tbl_offset;
 	/* BDs specific */
 	u8				*p_tx_bd_ring;
@@ -720,8 +671,8 @@
 	u32				rx_bd_ring_offset;
 	u8				*p_rx_buf;
 	u32				rx_buf_offset;
-	volatile qe_bd_t		*txBd;
-	volatile qe_bd_t		*rxBd;
+	struct buffer_descriptor	*tx_bd;
+	struct buffer_descriptor	*rx_bd;
 	/* Status */
 	int				mac_tx_enabled;
 	int				mac_rx_enabled;
@@ -733,9 +684,9 @@
 	int				oldspeed;
 	int				oldduplex;
 	int				oldlink;
-} uec_private_t;
+};
 
-int uec_initialize(struct bd_info *bis, uec_info_t *uec_info);
-int uec_eth_init(struct bd_info *bis, uec_info_t *uecs, int num);
+int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
+int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
 int uec_standard_init(struct bd_info *bis);
 #endif /* __UEC_H__ */

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 69c22dd..9d429c8 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c

@@ -23,17 +23,19 @@
 #include <fsl_qe.h>
 #include <phy.h>
 
+#if !defined(CONFIG_DM_ETH)
+
 #define ugphy_printk(format, arg...)  \
 	printf(format "\n", ## arg)
 
 #define ugphy_dbg(format, arg...)	     \
-	ugphy_printk(format , ## arg)
+	ugphy_printk(format, ## arg)
 #define ugphy_err(format, arg...)	     \
-	ugphy_printk(format , ## arg)
+	ugphy_printk(format, ## arg)
 #define ugphy_info(format, arg...)	     \
-	ugphy_printk(format , ## arg)
+	ugphy_printk(format, ## arg)
 #define ugphy_warn(format, arg...)	     \
-	ugphy_printk(format , ## arg)
+	ugphy_printk(format, ## arg)
 
 #ifdef UEC_VERBOSE_DEBUG
 #define ugphy_vdbg ugphy_dbg
@@ -41,13 +43,13 @@
 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
 #endif /* UEC_VERBOSE_DEBUG */
 
-/*--------------------------------------------------------------------+
+/*
+ * --------------------------------------------------------------------
  * Fixed PHY (PHY-less) support for Ethernet Ports.
  *
  * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
- *--------------------------------------------------------------------*/
-
-/*
+ *--------------------------------------------------------------------
+ *
  * Some boards do not have a PHY for each ethernet port. These ports are known
  * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
  * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
@@ -90,54 +92,58 @@
 	CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
 };
 
-/*--------------------------------------------------------------------+
+/*
+ * -------------------------------------------------------------------
  * BitBang MII support for ethernet ports
  *
  * Based from MPC8560ADS implementation
- *--------------------------------------------------------------------*/
-/*
+ *--------------------------------------------------------------------
+ *
  * Example board header file to define bitbang ethernet ports:
  *
  * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
  * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
-*/
+ */
 #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
 #define CONFIG_SYS_BITBANG_PHY_PORTS	/* default is an empty array */
 #endif
 
 #if defined(CONFIG_BITBANGMII)
-static const char *bitbang_phy_port[] = {
+static const char * const bitbang_phy_port[] = {
 	CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
 };
 #endif /* CONFIG_BITBANGMII */
 
-static void config_genmii_advert (struct uec_mii_info *mii_info);
-static void genmii_setup_forced (struct uec_mii_info *mii_info);
-static void genmii_restart_aneg (struct uec_mii_info *mii_info);
-static int gbit_config_aneg (struct uec_mii_info *mii_info);
-static int genmii_config_aneg (struct uec_mii_info *mii_info);
-static int genmii_update_link (struct uec_mii_info *mii_info);
-static int genmii_read_status (struct uec_mii_info *mii_info);
-u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
-void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
+static void config_genmii_advert(struct uec_mii_info *mii_info);
+static void genmii_setup_forced(struct uec_mii_info *mii_info);
+static void genmii_restart_aneg(struct uec_mii_info *mii_info);
+static int gbit_config_aneg(struct uec_mii_info *mii_info);
+static int genmii_config_aneg(struct uec_mii_info *mii_info);
+static int genmii_update_link(struct uec_mii_info *mii_info);
+static int genmii_read_status(struct uec_mii_info *mii_info);
+static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
+static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
+			  u16 val);
 
-/* Write value to the PHY for this device to the register at regnum, */
-/* waiting until the write is done before it returns.  All PHY */
-/* configuration has to be done through the TSEC1 MIIM regs */
-void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+/*
+ * Write value to the PHY for this device to the register at regnum,
+ * waiting until the write is done before it returns.  All PHY
+ * configuration has to be done through the TSEC1 MIIM regs
+ */
+void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
+		       int value)
 {
-	uec_private_t *ugeth = (uec_private_t *) dev->priv;
+	struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
 	uec_mii_t *ug_regs;
-	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+	enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
 	u32 tmp_reg;
 
-
 #if defined(CONFIG_BITBANGMII)
 	u32 i = 0;
 
 	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
 		if (strncmp(dev->name, bitbang_phy_port[i],
-			sizeof(dev->name)) == 0) {
+			    sizeof(dev->name)) == 0) {
 			(void)bb_miiphy_write(NULL, mii_id, regnum, value);
 			return;
 		}
@@ -148,46 +154,48 @@
 
 	/* Stop the MII management read cycle */
 	out_be32 (&ug_regs->miimcom, 0);
-	/* Setting up the MII Mangement Address Register */
-	tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
+	/* Setting up the MII Management Address Register */
+	tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 	out_be32 (&ug_regs->miimadd, tmp_reg);
 
-	/* Setting up the MII Mangement Control Register with the value */
-	out_be32 (&ug_regs->miimcon, (u32) value);
+	/* Setting up the MII Management Control Register with the value */
+	out_be32 (&ug_regs->miimcon, (u32)value);
 	sync();
 
 	/* Wait till MII management write is complete */
-	while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
+	while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
+		;
 }
 
-/* Reads from register regnum in the PHY for device dev, */
-/* returning the value.  Clears miimcom first.  All PHY */
-/* configuration has to be done through the TSEC1 MIIM regs */
-int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+/*
+ * Reads from register regnum in the PHY for device dev,
+ * returning the value.  Clears miimcom first.  All PHY
+ * configuration has to be done through the TSEC1 MIIM regs
+ */
+int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
 {
-	uec_private_t *ugeth = (uec_private_t *) dev->priv;
+	struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
 	uec_mii_t *ug_regs;
-	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+	enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
 	u32 tmp_reg;
 	u16 value;
 
-
 #if defined(CONFIG_BITBANGMII)
 	u32 i = 0;
 
 	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
 		if (strncmp(dev->name, bitbang_phy_port[i],
-			sizeof(dev->name)) == 0) {
+			    sizeof(dev->name)) == 0) {
 			(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
-			return (value);
+			return value;
 		}
 	}
 #endif /* CONFIG_BITBANGMII */
 
 	ug_regs = ugeth->uec_mii_regs;
 
-	/* Setting up the MII Mangement Address Register */
-	tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
+	/* Setting up the MII Management Address Register */
+	tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 	out_be32 (&ug_regs->miimadd, tmp_reg);
 
 	/* clear MII management command cycle */
@@ -199,37 +207,38 @@
 
 	/* Wait till MII management write is complete */
 	while ((in_be32 (&ug_regs->miimind)) &
-	       (MIIMIND_NOT_VALID | MIIMIND_BUSY));
+	       (MIIMIND_NOT_VALID | MIIMIND_BUSY))
+		;
 
 	/* Read MII management status  */
-	value = (u16) in_be32 (&ug_regs->miimstat);
+	value = (u16)in_be32 (&ug_regs->miimstat);
 	if (value == 0xffff)
 		ugphy_vdbg
 			("read wrong value : mii_id %d,mii_reg %d, base %08x",
-			 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
+			 mii_id, mii_reg, (u32)&ug_regs->miimcfg);
 
-	return (value);
+	return value;
 }
 
-void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
+void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
 {
 	if (mii_info->phyinfo->ack_interrupt)
-		mii_info->phyinfo->ack_interrupt (mii_info);
+		mii_info->phyinfo->ack_interrupt(mii_info);
 }
 
-void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
-				  u32 interrupts)
+void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
+				 u32 interrupts)
 {
 	mii_info->interrupts = interrupts;
 	if (mii_info->phyinfo->config_intr)
-		mii_info->phyinfo->config_intr (mii_info);
+		mii_info->phyinfo->config_intr(mii_info);
 }
 
 /* Writes MII_ADVERTISE with the appropriate values, after
  * sanitizing advertise to make sure only supported features
  * are advertised
  */
-static void config_genmii_advert (struct uec_mii_info *mii_info)
+static void config_genmii_advert(struct uec_mii_info *mii_info)
 {
 	u32 advertise;
 	u16 adv;
@@ -252,7 +261,7 @@
 	uec_phy_write(mii_info, MII_ADVERTISE, adv);
 }
 
-static void genmii_setup_forced (struct uec_mii_info *mii_info)
+static void genmii_setup_forced(struct uec_mii_info *mii_info)
 {
 	u16 ctrl;
 	u32 features = mii_info->phyinfo->features;
@@ -283,7 +292,7 @@
 				| SUPPORTED_10baseT_Full))
 			break;
 	default:		/* Unsupported speed! */
-		ugphy_err ("%s: Bad speed!", mii_info->dev->name);
+		ugphy_err("%s: Bad speed!", mii_info->dev->name);
 		break;
 	}
 
@@ -291,7 +300,7 @@
 }
 
 /* Enable and Restart Autonegotiation */
-static void genmii_restart_aneg (struct uec_mii_info *mii_info)
+static void genmii_restart_aneg(struct uec_mii_info *mii_info)
 {
 	u16 ctl;
 
@@ -300,14 +309,14 @@
 	uec_phy_write(mii_info, MII_BMCR, ctl);
 }
 
-static int gbit_config_aneg (struct uec_mii_info *mii_info)
+static int gbit_config_aneg(struct uec_mii_info *mii_info)
 {
 	u16 adv;
 	u32 advertise;
 
 	if (mii_info->autoneg) {
 		/* Configure the ADVERTISE register */
-		config_genmii_advert (mii_info);
+		config_genmii_advert(mii_info);
 		advertise = mii_info->advertising;
 
 		adv = uec_phy_read(mii_info, MII_CTRL1000);
@@ -320,18 +329,21 @@
 		uec_phy_write(mii_info, MII_CTRL1000, adv);
 
 		/* Start/Restart aneg */
-		genmii_restart_aneg (mii_info);
-	} else
-		genmii_setup_forced (mii_info);
+		genmii_restart_aneg(mii_info);
+	} else {
+		genmii_setup_forced(mii_info);
+	}
 
 	return 0;
 }
 
-static int marvell_config_aneg (struct uec_mii_info *mii_info)
+static int marvell_config_aneg(struct uec_mii_info *mii_info)
 {
-	/* The Marvell PHY has an errata which requires
+	/*
+	 * The Marvell PHY has an errata which requires
 	 * that certain registers get written in order
-	 * to restart autonegotiation */
+	 * to restart autonegotiation
+	 */
 	uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
 
 	uec_phy_write(mii_info, 0x1d, 0x1f);
@@ -340,16 +352,18 @@
 	uec_phy_write(mii_info, 0x1e, 0);
 	uec_phy_write(mii_info, 0x1e, 0x100);
 
-	gbit_config_aneg (mii_info);
+	gbit_config_aneg(mii_info);
 
 	return 0;
 }
 
-static int genmii_config_aneg (struct uec_mii_info *mii_info)
+static int genmii_config_aneg(struct uec_mii_info *mii_info)
 {
 	if (mii_info->autoneg) {
-		/* Speed up the common case, if link is already up, speed and
-		   duplex match, skip auto neg as it already matches */
+		/*
+		 * Speed up the common case, if link is already up, speed and
+		 * duplex match, skip auto neg as it already matches
+		 */
 		if (!genmii_read_status(mii_info) && mii_info->link)
 			if (mii_info->duplex == DUPLEX_FULL &&
 			    mii_info->speed == SPEED_100)
@@ -357,15 +371,16 @@
 				    ADVERTISED_100baseT_Full)
 					return 0;
 
-		config_genmii_advert (mii_info);
-		genmii_restart_aneg (mii_info);
-	} else
-		genmii_setup_forced (mii_info);
+		config_genmii_advert(mii_info);
+		genmii_restart_aneg(mii_info);
+	} else {
+		genmii_setup_forced(mii_info);
+	}
 
 	return 0;
 }
 
-static int genmii_update_link (struct uec_mii_info *mii_info)
+static int genmii_update_link(struct uec_mii_info *mii_info)
 {
 	u16 status;
 
@@ -377,8 +392,8 @@
 	 * (ie - we're capable and it's not done)
 	 */
 	status = uec_phy_read(mii_info, MII_BMSR);
-	if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
-	    && !(status & BMSR_ANEGCOMPLETE)) {
+	if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
+	    !(status & BMSR_ANEGCOMPLETE)) {
 		int i = 0;
 
 		while (!(status & BMSR_ANEGCOMPLETE)) {
@@ -405,14 +420,13 @@
 	return 0;
 }
 
-static int genmii_read_status (struct uec_mii_info *mii_info)
+static int genmii_read_status(struct uec_mii_info *mii_info)
 {
 	u16 status;
 	int err;
 
-	/* Update the link, but return if there
-	 * was an error */
-	err = genmii_update_link (mii_info);
+	/* Update the link, but return if there was an error */
+	err = genmii_update_link(mii_info);
 	if (err)
 		return err;
 
@@ -449,13 +463,13 @@
 static int bcm_init(struct uec_mii_info *mii_info)
 {
 	struct eth_device *edev = mii_info->dev;
-	uec_private_t *uec = edev->priv;
+	struct uec_priv *uec = edev->priv;
 
 	gbit_config_aneg(mii_info);
 
-	if ((uec->uec_info->enet_interface_type ==
-				PHY_INTERFACE_MODE_RGMII_RXID) &&
-			(uec->uec_info->speed == SPEED_1000)) {
+	if (uec->uec_info->enet_interface_type ==
+				PHY_INTERFACE_MODE_RGMII_RXID &&
+			uec->uec_info->speed == SPEED_1000) {
 		u16 val;
 		int cnt = 50;
 
@@ -476,18 +490,18 @@
 		uec_phy_write(mii_info, 0x18, val);
 	}
 
-	 return 0;
+	return 0;
 }
 
 static int uec_marvell_init(struct uec_mii_info *mii_info)
 {
 	struct eth_device *edev = mii_info->dev;
-	uec_private_t *uec = edev->priv;
+	struct uec_priv *uec = edev->priv;
 	phy_interface_t iface = uec->uec_info->enet_interface_type;
 	int	speed = uec->uec_info->speed;
 
-	if ((speed == SPEED_1000) &&
-	   (iface == PHY_INTERFACE_MODE_RGMII_ID ||
+	if (speed == SPEED_1000 &&
+	    (iface == PHY_INTERFACE_MODE_RGMII_ID ||
 	    iface == PHY_INTERFACE_MODE_RGMII_RXID ||
 	    iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 		int temp;
@@ -515,20 +529,21 @@
 	return 0;
 }
 
-static int marvell_read_status (struct uec_mii_info *mii_info)
+static int marvell_read_status(struct uec_mii_info *mii_info)
 {
 	u16 status;
 	int err;
 
-	/* Update the link, but return if there
-	 * was an error */
-	err = genmii_update_link (mii_info);
+	/* Update the link, but return if there was an error */
+	err = genmii_update_link(mii_info);
 	if (err)
 		return err;
 
-	/* If the link is up, read the speed and duplex */
-	/* If we aren't autonegotiating, assume speeds
-	 * are as set */
+	/*
+	 * If the link is up, read the speed and duplex
+	 * If we aren't autonegotiating, assume speeds
+	 * are as set
+	 */
 	if (mii_info->autoneg && mii_info->link) {
 		int speed;
 
@@ -559,7 +574,7 @@
 	return 0;
 }
 
-static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
+static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
 {
 	/* Clear the interrupts by reading the reg */
 	uec_phy_read(mii_info, MII_M1011_IEVENT);
@@ -567,18 +582,18 @@
 	return 0;
 }
 
-static int marvell_config_intr (struct uec_mii_info *mii_info)
+static int marvell_config_intr(struct uec_mii_info *mii_info)
 {
 	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 		uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 	else
 		uec_phy_write(mii_info, MII_M1011_IMASK,
-				MII_M1011_IMASK_CLEAR);
+			      MII_M1011_IMASK_CLEAR);
 
 	return 0;
 }
 
-static int dm9161_init (struct uec_mii_info *mii_info)
+static int dm9161_init(struct uec_mii_info *mii_info)
 {
 	/* Reset the PHY */
 	uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
@@ -589,29 +604,31 @@
 
 	uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
 
-	config_genmii_advert (mii_info);
+	config_genmii_advert(mii_info);
 	/* Start/restart aneg */
-	genmii_config_aneg (mii_info);
+	genmii_config_aneg(mii_info);
 
 	return 0;
 }
 
-static int dm9161_config_aneg (struct uec_mii_info *mii_info)
+static int dm9161_config_aneg(struct uec_mii_info *mii_info)
 {
 	return 0;
 }
 
-static int dm9161_read_status (struct uec_mii_info *mii_info)
+static int dm9161_read_status(struct uec_mii_info *mii_info)
 {
 	u16 status;
 	int err;
 
 	/* Update the link, but return if there was an error */
-	err = genmii_update_link (mii_info);
+	err = genmii_update_link(mii_info);
 	if (err)
 		return err;
-	/* If the link is up, read the speed and duplex
-	   If we aren't autonegotiating assume speeds are as set */
+	/*
+	 * If the link is up, read the speed and duplex
+	 * If we aren't autonegotiating assume speeds are as set
+	 */
 	if (mii_info->autoneg && mii_info->link) {
 		status = uec_phy_read(mii_info, MII_DM9161_SCSR);
 		if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
@@ -628,7 +645,7 @@
 	return 0;
 }
 
-static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
+static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
 {
 	/* Clear the interrupt by reading the reg */
 	uec_phy_read(mii_info, MII_DM9161_INTR);
@@ -636,7 +653,7 @@
 	return 0;
 }
 
-static int dm9161_config_intr (struct uec_mii_info *mii_info)
+static int dm9161_config_intr(struct uec_mii_info *mii_info)
 {
 	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 		uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
@@ -646,23 +663,23 @@
 	return 0;
 }
 
-static void dm9161_close (struct uec_mii_info *mii_info)
+static void dm9161_close(struct uec_mii_info *mii_info)
 {
 }
 
-static int fixed_phy_aneg (struct uec_mii_info *mii_info)
+static int fixed_phy_aneg(struct uec_mii_info *mii_info)
 {
 	mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
 	return 0;
 }
 
-static int fixed_phy_read_status (struct uec_mii_info *mii_info)
+static int fixed_phy_read_status(struct uec_mii_info *mii_info)
 {
 	int i = 0;
 
 	for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
 		if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
-				strlen(mii_info->dev->name)) == 0) {
+			    strlen(mii_info->dev->name)) == 0) {
 			mii_info->speed = fixed_phy_port[i].speed;
 			mii_info->duplex = fixed_phy_port[i].duplex;
 			mii_info->link = 1; /* Link is always UP */
@@ -673,25 +690,26 @@
 	return 0;
 }
 
-static int smsc_config_aneg (struct uec_mii_info *mii_info)
+static int smsc_config_aneg(struct uec_mii_info *mii_info)
 {
 	return 0;
 }
 
-static int smsc_read_status (struct uec_mii_info *mii_info)
+static int smsc_read_status(struct uec_mii_info *mii_info)
 {
 	u16 status;
 	int err;
 
-	/* Update the link, but return if there
-	 * was an error */
-	err = genmii_update_link (mii_info);
+	/* Update the link, but return if there was an error */
+	err = genmii_update_link(mii_info);
 	if (err)
 		return err;
 
-	/* If the link is up, read the speed and duplex */
-	/* If we aren't autonegotiating, assume speeds
-	 * are as set */
+	/*
+	 * If the link is up, read the speed and duplex
+	 * If we aren't autonegotiating, assume speeds
+	 * are as set
+	 */
 	if (mii_info->autoneg && mii_info->link) {
 		int	val;
 
@@ -699,22 +717,22 @@
 		val = (status & 0x1c) >> 2;
 
 		switch (val) {
-			case 1:
-				mii_info->duplex = DUPLEX_HALF;
-				mii_info->speed = SPEED_10;
-				break;
-			case 5:
-				mii_info->duplex = DUPLEX_FULL;
-				mii_info->speed = SPEED_10;
-				break;
-			case 2:
-				mii_info->duplex = DUPLEX_HALF;
-				mii_info->speed = SPEED_100;
-				break;
-			case 6:
-				mii_info->duplex = DUPLEX_FULL;
-				mii_info->speed = SPEED_100;
-				break;
+		case 1:
+			mii_info->duplex = DUPLEX_HALF;
+			mii_info->speed = SPEED_10;
+			break;
+		case 5:
+			mii_info->duplex = DUPLEX_FULL;
+			mii_info->speed = SPEED_10;
+			break;
+		case 2:
+			mii_info->duplex = DUPLEX_HALF;
+			mii_info->speed = SPEED_100;
+			break;
+		case 6:
+			mii_info->duplex = DUPLEX_FULL;
+			mii_info->speed = SPEED_100;
+			break;
 		}
 		mii_info->pause = 0;
 	}
@@ -803,25 +821,25 @@
 	NULL
 };
 
-u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
+static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
 {
-	return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
+	return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
 }
 
-void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
+static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
 {
-	mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
+	mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
 }
 
 /* Use the PHY ID registers to determine what type of PHY is attached
  * to device dev.  return a struct phy_info structure describing that PHY
  */
-struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
+struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
 {
 	u16 phy_reg;
 	u32 phy_ID;
 	int i;
-	struct phy_info *theInfo = NULL;
+	struct phy_info *info = NULL;
 
 	/* Grab the bits from PHYIR1, and put them in the upper half */
 	phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
@@ -836,30 +854,29 @@
 	for (i = 0; phy_info[i]; i++)
 		if (phy_info[i]->phy_id ==
 		    (phy_ID & phy_info[i]->phy_id_mask)) {
-			theInfo = phy_info[i];
+			info = phy_info[i];
 			break;
 		}
 
 	/* This shouldn't happen, as we have generic PHY support */
-	if (theInfo == NULL) {
-		ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
+	if (!info) {
+		ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
 		return NULL;
-	} else {
-		ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
 	}
+	ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
 
-	return theInfo;
+	return info;
 }
 
 void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
-		int speed)
+				int speed)
 {
-	uec_private_t *uec = (uec_private_t *) dev->priv;
+	struct uec_priv *uec = (struct uec_priv *)dev->priv;
 	struct uec_mii_info *mii_info;
 	u16 status;
 
 	if (!uec->mii_info) {
-		printf ("%s: the PHY not initialized\n", __FUNCTION__);
+		printf("%s: the PHY not initialized\n", __func__);
 		return;
 	}
 	mii_info = uec->mii_info;
@@ -903,10 +920,11 @@
 	/* now the B2 will correctly report autoneg completion status */
 }
 
-void change_phy_interface_mode (struct eth_device *dev,
-				phy_interface_t type, int speed)
+void change_phy_interface_mode(struct eth_device *dev,
+			       phy_interface_t type, int speed)
 {
 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
-	marvell_phy_interface_mode (dev, type, speed);
+	marvell_phy_interface_mode(dev, type, speed);
 #endif
 }
+#endif

diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 83a7ccd..7fd0e2c 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h

@@ -11,6 +11,8 @@
 #ifndef __UEC_PHY_H__
 #define __UEC_PHY_H__
 
+#include <linux/bitops.h>
+
 #define MII_end ((u32)-2)
 #define MII_read ((u32)-1)
 
@@ -93,8 +95,8 @@
 #define MII_DM9161_INTR_LINK_CHANGE	0x0004
 #define MII_DM9161_INTR_INIT		0x0000
 #define MII_DM9161_INTR_STOP	\
-(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
- | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
+		(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
+		 MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
 
 /* DM9161 10BT Configuration/Status */
 #define MII_DM9161_10BTCSR		0x12
@@ -125,35 +127,6 @@
 #define DUPLEX_HALF		0x00
 #define DUPLEX_FULL		0x01
 
-/* Indicates what features are supported by the interface. */
-#define SUPPORTED_10baseT_Half		(1 << 0)
-#define SUPPORTED_10baseT_Full		(1 << 1)
-#define SUPPORTED_100baseT_Half		(1 << 2)
-#define SUPPORTED_100baseT_Full		(1 << 3)
-#define SUPPORTED_1000baseT_Half	(1 << 4)
-#define SUPPORTED_1000baseT_Full	(1 << 5)
-#define SUPPORTED_Autoneg		(1 << 6)
-#define SUPPORTED_TP			(1 << 7)
-#define SUPPORTED_AUI			(1 << 8)
-#define SUPPORTED_MII			(1 << 9)
-#define SUPPORTED_FIBRE			(1 << 10)
-#define SUPPORTED_BNC			(1 << 11)
-#define SUPPORTED_10000baseT_Full	(1 << 12)
-
-#define ADVERTISED_10baseT_Half		(1 << 0)
-#define ADVERTISED_10baseT_Full		(1 << 1)
-#define ADVERTISED_100baseT_Half	(1 << 2)
-#define ADVERTISED_100baseT_Full	(1 << 3)
-#define ADVERTISED_1000baseT_Half	(1 << 4)
-#define ADVERTISED_1000baseT_Full	(1 << 5)
-#define ADVERTISED_Autoneg		(1 << 6)
-#define ADVERTISED_TP			(1 << 7)
-#define ADVERTISED_AUI			(1 << 8)
-#define ADVERTISED_MII			(1 << 9)
-#define ADVERTISED_FIBRE		(1 << 10)
-#define ADVERTISED_BNC			(1 << 11)
-#define ADVERTISED_10000baseT_Full	(1 << 12)
-
 /* Taken from mii_if_info and sungem_phy.h */
 struct uec_mii_info {
 	/* Information about the PHY type */
@@ -184,9 +157,9 @@
 	void *priv;
 
 	/* Provided by ethernet driver */
-	int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
-	void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
-			    int val);
+	int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
+	void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
+			   int val);
 };
 
 /* struct phy_info: a structure which defines attributes for a PHY
@@ -208,32 +181,34 @@
 	u32 features;
 
 	/* Called to initialize the PHY */
-	int (*init) (struct uec_mii_info * mii_info);
+	int (*init)(struct uec_mii_info *mii_info);
 
 	/* Called to suspend the PHY for power */
-	int (*suspend) (struct uec_mii_info * mii_info);
+	int (*suspend)(struct uec_mii_info *mii_info);
 
 	/* Reconfigures autonegotiation (or disables it) */
-	int (*config_aneg) (struct uec_mii_info * mii_info);
+	int (*config_aneg)(struct uec_mii_info *mii_info);
 
 	/* Determines the negotiated speed and duplex */
-	int (*read_status) (struct uec_mii_info * mii_info);
+	int (*read_status)(struct uec_mii_info *mii_info);
 
 	/* Clears any pending interrupts */
-	int (*ack_interrupt) (struct uec_mii_info * mii_info);
+	int (*ack_interrupt)(struct uec_mii_info *mii_info);
 
 	/* Enables or disables interrupts */
-	int (*config_intr) (struct uec_mii_info * mii_info);
+	int (*config_intr)(struct uec_mii_info *mii_info);
 
 	/* Clears up any memory if needed */
-	void (*close) (struct uec_mii_info * mii_info);
+	void (*close)(struct uec_mii_info *mii_info);
 };
 
-struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
-void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
-		    int value);
-int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
-void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
-void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
-				  u32 interrupts);
+struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
+void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
+		       int value);
+int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
+void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
+void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
+				 u32 interrupts);
+void change_phy_interface_mode(struct eth_device *dev,
+			       phy_interface_t type, int speed);
 #endif /* __UEC_PHY_H__ */

diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
index 5ff8869..60d4945 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/fu540_ddr.c

@@ -11,7 +11,6 @@
 #include <fdtdec.h>
 #include <init.h>
 #include <ram.h>
-#include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <clk.h>
@@ -339,17 +338,12 @@
 	priv->info.size = gd->ram_size;
 
 #if defined(CONFIG_SPL_BUILD)
-	struct regmap *map;
 	int ret;
 	u32 clock = 0;
 
 	debug("FU540 DDR probe\n");
 	priv->dev = dev;
 
-	ret = regmap_init_mem(dev_ofnode(dev), &map);
-	if (ret)
-		return ret;
-
 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
 	if (ret) {
 		debug("clk get failed %d\n", ret);
@@ -369,9 +363,14 @@
 	}
 
 	ret = clk_enable(&priv->ddr_clk);
-	priv->ctl = regmap_get_range(map, 0);
-	priv->phy = regmap_get_range(map, 1);
-	priv->physical_filter_ctrl = regmap_get_range(map, 2);
+	if (ret < 0) {
+		debug("Could not enable DDR clock\n");
+		return ret;
+	}
+
+	priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0);
+	priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1);
+	priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
 
 	return fu540_ddr_setup(dev);
 #endif

diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c
index 54209fc..702d98d 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c

@@ -100,7 +100,7 @@
 	fw->buffer_size = size;
 }
 
-static int k3_sysctrler_load_response(u32 *buf)
+static int k3_sysctrler_load_response(struct udevice *dev, u32 *buf)
 {
 	struct k3_sysctrler_load_msg *fw;
 
@@ -129,7 +129,8 @@
 	return 0;
 }
 
-static int k3_sysctrler_boot_notification_response(u32 *buf)
+static int k3_sysctrler_boot_notification_response(struct udevice *dev,
+						   u32 *buf)
 {
 	struct k3_sysctrler_boot_notification_msg *boot;
 
@@ -193,7 +194,7 @@
 	}
 
 	/* Process the response */
-	ret = k3_sysctrler_load_response(msg.buf);
+	ret = k3_sysctrler_load_response(dev, msg.buf);
 	if (ret)
 		return ret;
 
@@ -230,7 +231,7 @@
 	}
 
 	/* Process the response */
-	ret = k3_sysctrler_boot_notification_response(msg.buf);
+	ret = k3_sysctrler_boot_notification_response(dev, msg.buf);
 	if (ret)
 		return ret;
 

diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
index c464ece..b185a6c 100644
--- a/drivers/remoteproc/rproc-elf-loader.c
+++ b/drivers/remoteproc/rproc-elf-loader.c

@@ -158,22 +158,6 @@
 	return 0;
 }
 
-/* Basic function to verify ELF image format */
-int rproc_elf_sanity_check(ulong addr, ulong size)
-{
-	Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr;
-
-	if (!addr) {
-		dev_err(dev, "Invalid firmware address\n");
-		return -EFAULT;
-	}
-
-	if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
-		return rproc_elf64_sanity_check(addr, size);
-	else
-		return rproc_elf32_sanity_check(addr, size);
-}
-
 int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size)
 {
 	Elf32_Ehdr *ehdr; /* Elf header structure pointer */

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 1a7f1f8..9332a63d 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c

@@ -2,8 +2,9 @@
 /*
  * Texas Instruments' K3 R5 Remoteproc driver
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  */
 
 #include <common.h>
@@ -37,6 +38,8 @@
 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN			0x00001000
 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN			0x00002000
 #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR		0x10000000
+/* Available from J7200 SoCs onwards */
+#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS		0x00004000
 
 /* R5 TI-SCI Processor Control Flags */
 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT		0x00000001
@@ -55,6 +58,16 @@
 };
 
 /**
+ * struct k3_r5f_ip_data - internal data structure used for IP variations
+ * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
+ * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
+ */
+struct k3_r5f_ip_data {
+	bool tcm_is_double;
+	bool tcm_ecc_autoinit;
+};
+
+/**
  * struct k3_r5_mem - internal memory structure
  * @cpu_addr: MPU virtual address of the memory region
  * @bus_addr: Bus address used to access the memory region
@@ -74,6 +87,7 @@
  * @cluster: pointer to the parent cluster.
  * @reset: reset control handle
  * @tsp: TI-SCI processor control handle
+ * @ipdata: cached pointer to R5F IP specific feature data
  * @mem: Array of available internal memories
  * @num_mem: Number of available memories
  * @atcm_enable: flag to control ATCM enablement
@@ -86,6 +100,7 @@
 	struct k3_r5f_cluster *cluster;
 	struct reset_ctl reset;
 	struct ti_sci_proc tsp;
+	struct k3_r5f_ip_data *ipdata;
 	struct k3_r5f_mem *mem;
 	int num_mems;
 	u32 atcm_enable;
@@ -150,7 +165,7 @@
 {
 	int ret, c;
 
-	dev_dbg(dev, "%s\n", __func__);
+	debug("%s\n", __func__);
 
 	for (c = NR_CORES - 1; c >= 0; c--) {
 		ret = ti_sci_proc_power_domain_on(&cluster->cores[c]->tsp);
@@ -186,7 +201,7 @@
 {
 	int ret;
 
-	dev_dbg(dev, "%s\n", __func__);
+	dev_dbg(core->dev, "%s\n", __func__);
 
 	ret = ti_sci_proc_power_domain_on(&core->tsp);
 	if (ret) {
@@ -231,25 +246,29 @@
 	struct k3_r5f_cluster *cluster = core->cluster;
 
 	if (core->in_use) {
-		dev_err(dev, "Invalid op: Trying to load/start on already running core %d\n",
+		dev_err(core->dev,
+			"Invalid op: Trying to load/start on already running core %d\n",
 			core->tsp.proc_id);
 		return -EINVAL;
 	}
 
 	if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !cluster->cores[1]) {
-		printf("Secondary core is not probed in this cluster\n");
+		dev_err(core->dev,
+			"Secondary core is not probed in this cluster\n");
 		return -EAGAIN;
 	}
 
 	if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !is_primary_core(core)) {
-		dev_err(dev, "Invalid op: Trying to start secondary core %d in lockstep mode\n",
+		dev_err(core->dev,
+			"Invalid op: Trying to start secondary core %d in lockstep mode\n",
 			core->tsp.proc_id);
 		return -EINVAL;
 	}
 
 	if (cluster->mode == CLUSTER_MODE_SPLIT && !is_primary_core(core)) {
 		if (!core->cluster->cores[0]->in_use) {
-			dev_err(dev, "Invalid seq: Enable primary core before loading secondary core\n");
+			dev_err(core->dev,
+				"Invalid seq: Enable primary core before loading secondary core\n");
 			return -EINVAL;
 		}
 	}
@@ -257,6 +276,18 @@
 	return 0;
 }
 
+/* Zero out TCMs so that ECC can be effective on all TCM addresses */
+void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited)
+{
+	if (core->ipdata->tcm_ecc_autoinit && auto_inited)
+		return;
+
+	if (core->atcm_enable)
+		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
+	if (core->btcm_enable)
+		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+}
+
 /**
  * k3_r5f_load() - Load up the Remote processor image
  * @dev:	rproc device pointer
@@ -268,7 +299,9 @@
 static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 {
 	struct k3_r5f_core *core = dev_get_priv(dev);
-	u32 boot_vector;
+	u64 boot_vector;
+	u32 ctrl, sts, cfg = 0;
+	bool mem_auto_init;
 	int ret;
 
 	dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -281,6 +314,12 @@
 	if (ret)
 		return ret;
 
+	ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl,
+				     &sts);
+	if (ret)
+		return ret;
+	mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
+
 	ret = k3_r5f_prepare(dev);
 	if (ret) {
 		dev_err(dev, "R5f prepare failed for core %d\n",
@@ -288,11 +327,7 @@
 		goto proc_release;
 	}
 
-	/* Zero out TCMs so that ECC can be effective on all TCM addresses */
-	if (core->atcm_enable)
-		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
-	if (core->btcm_enable)
-		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+	k3_r5f_init_tcm_memories(core, mem_auto_init);
 
 	ret = rproc_elf_load_image(dev, addr, size);
 	if (ret < 0) {
@@ -302,7 +337,7 @@
 
 	boot_vector = rproc_elf_get_boot_addr(dev, addr);
 
-	dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+	dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector);
 
 	ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
 
@@ -401,7 +436,7 @@
 {
 	int ret;
 
-	dev_dbg(dev, "%s\n", __func__);
+	dev_dbg(core->dev, "%s\n", __func__);
 
 	if (reset_assert(&core->reset))
 		ret = -EINVAL;
@@ -416,7 +451,7 @@
 {
 	int ret = 0, c;
 
-	dev_dbg(dev, "%s\n", __func__);
+	debug("%s\n", __func__);
 
 	for (c = 0; c < NR_CORES; c++)
 		if (reset_assert(&cluster->cores[c]->reset))
@@ -548,7 +583,7 @@
 	u64 boot_vec = 0;
 	int ret;
 
-	dev_dbg(dev, "%s\n", __func__);
+	dev_dbg(core->dev, "%s\n", __func__);
 
 	ret = ti_sci_proc_request(&core->tsp);
 	if (ret < 0)
@@ -641,7 +676,7 @@
 {
 	int ret;
 
-	dev_dbg(dev, "%s\n", __func__);
+	dev_dbg(core->dev, "%s\n", __func__);
 
 	core->atcm_enable = dev_read_u32_default(core->dev, "atcm-enable", 0);
 	core->btcm_enable = dev_read_u32_default(core->dev, "btcm-enable", 1);
@@ -657,6 +692,8 @@
 		return ret;
 	}
 
+	core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev);
+
 	return 0;
 }
 
@@ -702,6 +739,38 @@
 	return 0;
 }
 
+/*
+ * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
+ * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
+ * cores are usable in Split-mode, but only the Core0 TCMs can be used in
+ * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
+ * leveraging the Core1 TCMs as well in certain modes where they would have
+ * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by
+ * making a Core1 TCM visible immediately after the corresponding Core0 TCM.
+ * The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the
+ * dts representation reflects this increased size on supported SoCs. The Core0
+ * TCM sizes therefore have to be adjusted to only half the original size in
+ * Split mode.
+ */
+static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core)
+{
+	struct k3_r5f_cluster *cluster = core->cluster;
+
+	if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+		return;
+
+	if (!core->ipdata->tcm_is_double)
+		return;
+
+	if (core == cluster->cores[0]) {
+		core->mem[0].size /= 2;
+		core->mem[1].size /= 2;
+
+		dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
+			core->mem[0].size, core->mem[1].size);
+	}
+}
+
 /**
  * k3_r5f_probe() - Basic probe
  * @dev:	corresponding k3 remote processor device
@@ -755,6 +824,8 @@
 		return ret;
 	}
 
+	k3_r5f_core_adjust_tcm_sizes(core);
+
 	dev_dbg(dev, "Remoteproc successfully probed\n");
 
 	return 0;
@@ -771,9 +842,20 @@
 	return 0;
 }
 
+static const struct k3_r5f_ip_data k3_data = {
+	.tcm_is_double = false,
+	.tcm_ecc_autoinit = false,
+};
+
+static const struct k3_r5f_ip_data j7200_data = {
+	.tcm_is_double = true,
+	.tcm_ecc_autoinit = true,
+};
+
 static const struct udevice_id k3_r5f_rproc_ids[] = {
-	{ .compatible = "ti,am654-r5f"},
-	{ .compatible = "ti,j721e-r5f"},
+	{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
 	{}
 };
 
@@ -810,6 +892,7 @@
 static const struct udevice_id k3_r5fss_ids[] = {
 	{ .compatible = "ti,am654-r5fss"},
 	{ .compatible = "ti,j721e-r5fss"},
+	{ .compatible = "ti,j7200-r5fss"},
 	{}
 };
 

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 253902f..b60e11f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig

@@ -148,6 +148,14 @@
 	help
 	  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_IPQ419
+	bool "Reset driver for Qualcomm IPQ40xx SoCs"
+	depends on DM_RESET && ARCH_IPQ40XX
+	default y
+	help
+	  Support for reset controller on Qualcomm
+	  IPQ40xx SoCs.
+
 config RESET_SIFIVE
 	bool "Reset Driver for SiFive SoC's"
 	depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
@@ -173,4 +181,12 @@
 	  relevant. This driver provides a reset controller capable of
 	  interfacing with RPi4's co-processor and model these firmware
 	  initialization routines as reset lines.
+
+config RESET_SCMI
+	bool "Enable SCMI reset domain driver"
+	select SCMI_FIRMWARE
+	help
+	  Enable this option if you want to support reset controller
+	  devices exposed by a SCMI agent based on SCMI reset domain
+	  protocol communication with a SCMI server.
 endmenu

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3c7f066..10a7973 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile

@@ -23,6 +23,8 @@
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
 obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
 obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
+obj-$(CONFIG_RESET_SCMI) += reset-scmi.o

diff --git a/drivers/reset/reset-ipq4019.c b/drivers/reset/reset-ipq4019.c
new file mode 100644
index 0000000..f216db4
--- /dev/null
+++ b/drivers/reset/reset-ipq4019.c

@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <malloc.h>
+
+struct ipq4019_reset_priv {
+	phys_addr_t base;
+};
+
+struct qcom_reset_map {
+	unsigned int reg;
+	u8 bit;
+};
+
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
+	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
+	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
+	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
+	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
+	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
+	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
+	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
+	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
+	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
+	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
+	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
+	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
+	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
+	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
+	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
+	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
+	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
+	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
+	[PCIE_AHB_ARES] = { 0x1d010, 10 },
+	[PCIE_PWR_ARES] = { 0x1d010, 9 },
+	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
+	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
+	[PCIE_PHY_ARES] = { 0x1d010, 6 },
+	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
+	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
+	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
+	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
+	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
+	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
+	[ESS_RESET] = { 0x12008, 0},
+	[GCC_BLSP1_BCR] = {0x01000, 0},
+	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
+	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
+	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
+	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
+	[GCC_BIMC_BCR] = {0x04000, 0},
+	[GCC_TLMM_BCR] = {0x05000, 0},
+	[GCC_IMEM_BCR] = {0x0E000, 0},
+	[GCC_ESS_BCR] = {0x12008, 0},
+	[GCC_PRNG_BCR] = {0x13000, 0},
+	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
+	[GCC_CRYPTO_BCR] = {0x16000, 0},
+	[GCC_SDCC1_BCR] = {0x18000, 0},
+	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
+	[GCC_AUDIO_BCR] = {0x1B008, 0},
+	[GCC_QPIC_BCR] = {0x1C000, 0},
+	[GCC_PCIE_BCR] = {0x1D000, 0},
+	[GCC_USB2_BCR] = {0x1E008, 0},
+	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
+	[GCC_USB3_BCR] = {0x1E024, 0},
+	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
+	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
+	[GCC_PCNOC_BCR] = {0x2102C, 0},
+	[GCC_DCD_BCR] = {0x21038, 0},
+	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
+	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
+	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
+	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
+	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
+	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
+	[GCC_TCSR_BCR] = {0x22000, 0},
+	[GCC_MPM_BCR] = {0x24000, 0},
+	[GCC_SPDM_BCR] = {0x25000, 0},
+};
+
+static int ipq4019_reset_assert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value |= BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_deassert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value &= ~BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int ipq4019_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops ipq4019_reset_ops = {
+	.request = ipq4019_reset_request,
+	.rfree = ipq4019_reset_free,
+	.rst_assert = ipq4019_reset_assert,
+	.rst_deassert = ipq4019_reset_deassert,
+};
+
+static const struct udevice_id ipq4019_reset_ids[] = {
+	{ .compatible = "qcom,gcc-reset-ipq4019" },
+	{ }
+};
+
+static int ipq4019_reset_probe(struct udevice *dev)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(ipq4019_reset) = {
+	.name = "ipq4019_reset",
+	.id = UCLASS_RESET,
+	.of_match = ipq4019_reset_ids,
+	.ops = &ipq4019_reset_ops,
+	.probe = ipq4019_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
+};

diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
new file mode 100644
index 0000000..1bff807
--- /dev/null
+++ b/drivers/reset/reset-scmi.c

@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-2020 Linaro Limited
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <asm/types.h>
+
+static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
+{
+	struct scmi_rd_reset_in in = {
+		.domain_id = rst->id,
+		.flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0,
+		.reset_state = 0,
+	};
+	struct scmi_rd_reset_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN,
+					  SCMI_RESET_DOMAIN_RESET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_reset_assert(struct reset_ctl *rst)
+{
+	return scmi_reset_set_level(rst, true);
+}
+
+static int scmi_reset_deassert(struct reset_ctl *rst)
+{
+	return scmi_reset_set_level(rst, false);
+}
+
+static int scmi_reset_request(struct reset_ctl *rst)
+{
+	struct scmi_rd_attr_in in = {
+		.domain_id = rst->id,
+	};
+	struct scmi_rd_attr_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN,
+					  SCMI_RESET_DOMAIN_ATTRIBUTES,
+					  in, out);
+	int ret;
+
+	/*
+	 * We don't really care about the attribute, just check
+	 * the reset domain exists.
+	 */
+	ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_reset_rfree(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops scmi_reset_domain_ops = {
+	.request	= scmi_reset_request,
+	.rfree		= scmi_reset_rfree,
+	.rst_assert	= scmi_reset_assert,
+	.rst_deassert	= scmi_reset_deassert,
+};
+
+U_BOOT_DRIVER(scmi_reset_domain) = {
+	.name = "scmi_reset_domain",
+	.id = UCLASS_RESET,
+	.ops = &scmi_reset_domain_ops,
+};

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 5e38ce5..e7e407c 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c

@@ -11,6 +11,7 @@
 #include <reset.h>
 #include <reset-uclass.h>
 #include <dm/devres.h>
+#include <dm/lists.h>
 
 static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
 {
@@ -100,13 +101,14 @@
 				       index > 0, reset_ctl);
 }
 
-int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
+static int __reset_get_bulk(struct udevice *dev, ofnode node,
+			    struct reset_ctl_bulk *bulk)
 {
 	int i, ret, err, count;
-	
+
 	bulk->count = 0;
 
-	count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
+	count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells");
 	if (count < 1)
 		return count;
 
@@ -116,7 +118,7 @@
 		return -ENOMEM;
 
 	for (i = 0; i < count; i++) {
-		ret = reset_get_by_index(dev, i, &bulk->resets[i]);
+		ret = reset_get_by_index_nodev(node, i, &bulk->resets[i]);
 		if (ret < 0)
 			goto bulk_get_err;
 
@@ -134,6 +136,11 @@
 	return ret;
 }
 
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
+{
+	return __reset_get_bulk(dev, dev_ofnode(dev), bulk);
+}
+
 int reset_get_by_name(struct udevice *dev, const char *name,
 		     struct reset_ctl *reset_ctl)
 {
@@ -246,6 +253,109 @@
 	return 0;
 }
 
+static void devm_reset_release(struct udevice *dev, void *res)
+{
+	reset_free(res);
+}
+
+struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev,
+						  int index)
+{
+	int rc;
+	struct reset_ctl *reset_ctl;
+
+	reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl),
+				 __GFP_ZERO);
+	if (unlikely(!reset_ctl))
+		return ERR_PTR(-ENOMEM);
+
+	rc = reset_get_by_index(dev, index, reset_ctl);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, reset_ctl);
+	return reset_ctl;
+}
+
+struct reset_ctl *devm_reset_control_get(struct udevice *dev, const char *id)
+{
+	int rc;
+	struct reset_ctl *reset_ctl;
+
+	reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl),
+				 __GFP_ZERO);
+	if (unlikely(!reset_ctl))
+		return ERR_PTR(-ENOMEM);
+
+	rc = reset_get_by_name(dev, id, reset_ctl);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, reset_ctl);
+	return reset_ctl;
+}
+
+struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev,
+						  const char *id)
+{
+	struct reset_ctl *r = devm_reset_control_get(dev, id);
+
+	if (IS_ERR(r))
+		return NULL;
+
+	return r;
+}
+
+static void devm_reset_bulk_release(struct udevice *dev, void *res)
+{
+	struct reset_ctl_bulk *bulk = res;
+
+	reset_release_all(bulk->resets, bulk->count);
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev,
+						   ofnode node)
+{
+	int rc;
+	struct reset_ctl_bulk *bulk;
+
+	bulk = devres_alloc(devm_reset_bulk_release,
+			    sizeof(struct reset_ctl_bulk),
+			    __GFP_ZERO);
+	if (unlikely(!bulk))
+		return ERR_PTR(-ENOMEM);
+
+	rc = __reset_get_bulk(dev, node, bulk);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, bulk);
+	return bulk;
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev,
+							    ofnode node)
+{
+	struct reset_ctl_bulk *bulk;
+
+	bulk = devm_reset_bulk_get_by_node(dev, node);
+
+	if (IS_ERR(bulk))
+		return NULL;
+
+	return bulk;
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev)
+{
+	return devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev)
+{
+	return devm_reset_bulk_get_optional_by_node(dev, dev_ofnode(dev));
+}
+
 UCLASS_DRIVER(reset) = {
 	.id		= UCLASS_RESET,
 	.name		= "reset",

diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c
index 9bc4a7e..10e02f1 100644
--- a/drivers/reset/sandbox-reset-test.c
+++ b/drivers/reset/sandbox-reset-test.c

@@ -10,66 +10,105 @@
 #include <reset.h>
 #include <asm/io.h>
 #include <asm/reset.h>
+#include <linux/err.h>
 
 struct sandbox_reset_test {
 	struct reset_ctl ctl;
 	struct reset_ctl_bulk bulk;
+
+	struct reset_ctl *ctlp;
+	struct reset_ctl_bulk *bulkp;
 };
 
 int sandbox_reset_test_get(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
+	sbrt->ctlp = &sbrt->ctl;
 	return reset_get_by_name(dev, "test", &sbrt->ctl);
 }
 
+int sandbox_reset_test_get_devm(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+	struct reset_ctl *r;
+
+	r = devm_reset_control_get(dev, "not-a-valid-reset-ctl");
+	if (!IS_ERR(r))
+		return -EINVAL;
+
+	r = devm_reset_control_get_optional(dev, "not-a-valid-reset-ctl");
+	if (r)
+		return -EINVAL;
+
+	sbrt->ctlp = devm_reset_control_get(dev, "test");
+	if (IS_ERR(sbrt->ctlp))
+		return PTR_ERR(sbrt->ctlp);
+
+	return 0;
+}
+
 int sandbox_reset_test_get_bulk(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
+	sbrt->bulkp = &sbrt->bulk;
 	return reset_get_bulk(dev, &sbrt->bulk);
 }
 
+int sandbox_reset_test_get_bulk_devm(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+	struct reset_ctl_bulk *r;
+
+	r = devm_reset_bulk_get_optional(dev);
+	if (IS_ERR(r))
+		return PTR_ERR(r);
+
+	sbrt->bulkp = r;
+	return 0;
+}
+
 int sandbox_reset_test_assert(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_assert(&sbrt->ctl);
+	return reset_assert(sbrt->ctlp);
 }
 
 int sandbox_reset_test_assert_bulk(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_assert_bulk(&sbrt->bulk);
+	return reset_assert_bulk(sbrt->bulkp);
 }
 
 int sandbox_reset_test_deassert(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_deassert(&sbrt->ctl);
+	return reset_deassert(sbrt->ctlp);
 }
 
 int sandbox_reset_test_deassert_bulk(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_deassert_bulk(&sbrt->bulk);
+	return reset_deassert_bulk(sbrt->bulkp);
 }
 
 int sandbox_reset_test_free(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_free(&sbrt->ctl);
+	return reset_free(sbrt->ctlp);
 }
 
 int sandbox_reset_test_release_bulk(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
 
-	return reset_release_bulk(&sbrt->bulk);
+	return reset_release_bulk(sbrt->bulkp);
 }
 
 static const struct udevice_id sandbox_reset_test_ids[] = {

diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
index 7a6f7f6..08008d8 100644
--- a/drivers/reset/sandbox-reset.c
+++ b/drivers/reset/sandbox-reset.c

@@ -15,6 +15,7 @@
 
 struct sandbox_reset_signal {
 	bool asserted;
+	bool requested;
 };
 
 struct sandbox_reset {
@@ -23,18 +24,24 @@
 
 static int sandbox_reset_request(struct reset_ctl *reset_ctl)
 {
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
 	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
 
 	if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
 		return -EINVAL;
 
+	sbr->signals[reset_ctl->id].requested = true;
 	return 0;
 }
 
 static int sandbox_reset_free(struct reset_ctl *reset_ctl)
 {
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
 	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
 
+	sbr->signals[reset_ctl->id].requested = false;
 	return 0;
 }
 
@@ -107,3 +114,15 @@
 
 	return sbr->signals[id].asserted;
 }
+
+int sandbox_reset_is_requested(struct udevice *dev, unsigned long id)
+{
+	struct sandbox_reset *sbr = dev_get_priv(dev);
+
+	debug("%s(dev=%p, id=%ld)\n", __func__, dev, id);
+
+	if (id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	return sbr->signals[id].requested;
+}

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e344677..b4805a2 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig

@@ -734,7 +734,7 @@
 
 config XILINX_UARTLITE
 	bool "Xilinx Uarlite support"
-	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
+	depends on DM_SERIAL
 	help
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
@@ -802,7 +802,7 @@
 
 config ZYNQ_SERIAL
 	bool "Cadence (Xilinx Zynq) UART support"
-	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5)
+	depends on DM_SERIAL
 	help
 	  This driver supports the Cadence UART. It is found e.g. in Xilinx
 	  Zynq/ZynqMP.

diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 5116d13..236ab86 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c

@@ -23,6 +23,8 @@
 #define ULITE_CONTROL_RST_TX	0x01
 #define ULITE_CONTROL_RST_RX	0x02
 
+static bool little_endian;
+
 struct uartlite {
 	unsigned int rx_fifo;
 	unsigned int tx_fifo;
@@ -34,15 +36,31 @@
 	struct uartlite *regs;
 };
 
+static u32 uart_in32(void __iomem *addr)
+{
+	if (little_endian)
+		return in_le32(addr);
+	else
+		return in_be32(addr);
+}
+
+static void uart_out32(void __iomem *addr, u32 val)
+{
+	if (little_endian)
+		out_le32(addr, val);
+	else
+		out_be32(addr, val);
+}
+
 static int uartlite_serial_putc(struct udevice *dev, const char ch)
 {
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
 
-	if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+	if (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
 		return -EAGAIN;
 
-	out_be32(&regs->tx_fifo, ch & 0xff);
+	uart_out32(&regs->tx_fifo, ch & 0xff);
 
 	return 0;
 }
@@ -52,10 +70,10 @@
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
 
-	if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
+	if (!(uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA))
 		return -EAGAIN;
 
-	return in_be32(&regs->rx_fifo) & 0xff;
+	return uart_in32(&regs->rx_fifo) & 0xff;
 }
 
 static int uartlite_serial_pending(struct udevice *dev, bool input)
@@ -64,19 +82,26 @@
 	struct uartlite *regs = plat->regs;
 
 	if (input)
-		return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
+		return uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA;
 
-	return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
+	return !(uart_in32(&regs->status) & SR_TX_FIFO_EMPTY);
 }
 
 static int uartlite_serial_probe(struct udevice *dev)
 {
 	struct uartlite_platdata *plat = dev_get_platdata(dev);
 	struct uartlite *regs = plat->regs;
+	int ret;
 
-	out_be32(&regs->control, 0);
-	out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
-	in_be32(&regs->control);
+	uart_out32(&regs->control, 0);
+	uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	ret = uart_in32(&regs->status);
+	/* Endianness detection */
+	if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+		little_endian = true;
+		uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+			   ULITE_CONTROL_RST_TX);
+	}
 
 	return 0;
 }
@@ -119,20 +144,27 @@
 static inline void _debug_uart_init(void)
 {
 	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+	int ret;
 
-	out_be32(&regs->control, 0);
-	out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
-	in_be32(&regs->control);
+	uart_out32(&regs->control, 0);
+	uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	uart_in32(&regs->status);
+	/* Endianness detection */
+	if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+		little_endian = true;
+		uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+			   ULITE_CONTROL_RST_TX);
+	}
 }
 
 static inline void _debug_uart_putc(int ch)
 {
 	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
 
-	while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+	while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
 		;
 
-	out_be32(&regs->tx_fifo, ch & 0xff);
+	uart_out32(&regs->tx_fifo, ch & 0xff);
 }
 
 DEBUG_UART_FUNCS

diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig
index 7169d0f..73d51b3 100644
--- a/drivers/smem/Kconfig
+++ b/drivers/smem/Kconfig

@@ -15,7 +15,7 @@
 config MSM_SMEM
     bool "Qualcomm Shared Memory Manager (SMEM)"
     depends on DM
-    depends on ARCH_SNAPDRAGON
+    depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX
     help
       Enable support for the Qualcomm Shared Memory Manager.
       The driver provides an interface to items in a heap shared among all

diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c
index 2557269..597d425 100644
--- a/drivers/smem/msm_smem.c
+++ b/drivers/smem/msm_smem.c

@@ -879,7 +879,7 @@
 	header = smem->regions[0].virt_base;
 	if (le32_to_cpu(header->initialized) != 1 ||
 	    le32_to_cpu(header->reserved)) {
-		dev_err(&pdev->dev, "SMEM is not initialized by SBL\n");
+		dev_err(dev, "SMEM is not initialized by SBL\n");
 		return -EINVAL;
 	}
 

diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
index 841bc6e..827262d 100644
--- a/drivers/sound/max98357a.c
+++ b/drivers/sound/max98357a.c

@@ -81,7 +81,7 @@
 	dp = acpi_dp_new_table("_DSD");
 	acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0,
 			 priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ?
-			 ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH);
+			 ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH);
 	acpi_dp_add_integer(dp, "sdmode-delay",
 			    dev_read_u32_default(dev, "sdmode-delay", 0));
 	acpi_dp_write(ctx, dp);

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3fc2d06..5df97c8 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig

@@ -407,7 +407,6 @@
 
 config ZYNQ_SPI
 	bool "Zynq SPI driver"
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  Enable the Zynq SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Zynq
@@ -415,7 +414,6 @@
 
 config ZYNQ_QSPI
 	bool "Zynq QSPI driver"
-	depends on ARCH_ZYNQ
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
@@ -425,7 +423,6 @@
 
 config ZYNQMP_GQSPI
 	bool "Configure ZynqMP Generic QSPI"
-	depends on ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  This option is used to enable ZynqMP QSPI controller driver which
 	  is used to communicate with qspi flash devices.

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fbf9575..56cb217 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c

@@ -22,82 +22,14 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <omap3_spi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define OMAP4_MCSPI_REG_OFFSET	0x100
-
 struct omap2_mcspi_platform_config {
 	unsigned int regs_offset;
 };
 
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
-#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT	0
-#define MCSPI_PINDIR_D0_OUT_D1_IN	1
-
-#define OMAP3_MCSPI_MAX_FREQ		48000000
-#define SPI_WAIT_TIMEOUT		10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
-	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
-	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
-	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
-	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
-	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned int irqstatus;		/* 0x18 */
-	unsigned int irqenable;		/* 0x1C */
-	unsigned int wakeupenable;	/* 0x20 */
-	unsigned int syst;		/* 0x24 */
-	unsigned int modulctrl;		/* 0x28 */
-	struct mcspi_channel channel[4];
-	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
-	/* channel1: 0x40 - 0x50, bus 0 & 1 */
-	/* channel2: 0x54 - 0x64, bus 0 & 1 */
-	/* channel3: 0x68 - 0x78, bus 0 */
-};
-
 struct omap3_spi_priv {
 	struct mcspi *regs;
 	unsigned int cs;
@@ -482,17 +414,10 @@
 static int omap3_spi_probe(struct udevice *dev)
 {
 	struct omap3_spi_priv *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
+	struct omap3_spi_plat *plat = dev_get_platdata(dev);
 
-	struct omap2_mcspi_platform_config* data =
-		(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
-
-	priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
-	if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
-		priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
-	else
-		priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+	priv->regs = plat->regs;
+	priv->pin_dir = plat->pin_dir;
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
 
 	spi_reset(priv->regs);
@@ -544,6 +469,7 @@
 	 */
 };
 
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 static struct omap2_mcspi_platform_config omap2_pdata = {
 	.regs_offset = 0,
 };
@@ -552,16 +478,37 @@
 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
 };
 
+static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct omap2_mcspi_platform_config *data =
+		(struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
+	struct omap3_spi_plat *plat = dev_get_platdata(dev);
+
+	plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
+
+	if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
+		plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+	else
+		plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+
+	return 0;
+}
+
 static const struct udevice_id omap3_spi_ids[] = {
 	{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
 	{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
 	{ }
 };
-
+#endif
 U_BOOT_DRIVER(omap3_spi) = {
 	.name   = "omap3_spi",
 	.id     = UCLASS_SPI,
+	.flags	= DM_FLAG_PRE_RELOC,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 	.of_match = omap3_spi_ids,
+	.ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
+#endif
 	.probe = omap3_spi_probe,
 	.ops    = &omap3_spi_ops,
 	.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),

diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index cd2e17b..0844a5a 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c

@@ -489,19 +489,19 @@
 
 	ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
 	if (ret) {
-		dev_err(dev, "failed to get ahb clock\n");
+		dev_err(bus, "failed to get ahb clock\n");
 		return ret;
 	}
 
 	ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
 	if (ret) {
-		dev_err(dev, "failed to get mod clock\n");
+		dev_err(bus, "failed to get mod clock\n");
 		return ret;
 	}
 
 	ret = reset_get_by_index(bus, 0, &priv->reset);
 	if (ret && ret != -ENOENT) {
-		dev_err(dev, "failed to get reset\n");
+		dev_err(bus, "failed to get reset\n");
 		return ret;
 	}
 

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index cffd9cf..55a8eed 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c

@@ -497,7 +497,7 @@
 	.id		= UCLASS_SPI,
 	.name		= "spi",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 	.post_bind	= dm_scan_fdt_dev,
 #endif
 	.post_probe	= spi_post_probe,

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index a72986b..e0e6687 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c

@@ -346,20 +346,20 @@
 
 	ret = clk_get_by_index(bus, 0, &clk);
 	if (ret < 0) {
-		dev_err(dev, "failed to get clock\n");
+		dev_err(bus, "failed to get clock\n");
 		return ret;
 	}
 
 	clock = clk_get_rate(&clk);
 	if (IS_ERR_VALUE(clock)) {
-		dev_err(dev, "failed to get rate\n");
+		dev_err(bus, "failed to get rate\n");
 		return clock;
 	}
 	debug("%s: CLK %ld\n", __func__, clock);
 
 	ret = clk_enable(&clk);
 	if (ret && ret != -ENOSYS) {
-		dev_err(dev, "failed to enable clock\n");
+		dev_err(bus, "failed to enable clock\n");
 		return ret;
 	}
 	plat->frequency = clock;

diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c
index 3877b9b..7707c72 100644
--- a/drivers/sysreset/sysreset-ti-sci.c
+++ b/drivers/sysreset/sysreset-ti-sci.c

@@ -51,8 +51,7 @@
 
 	ret = cops->reboot_device(sci);
 	if (ret)
-		dev_err(rst->dev, "%s: reboot_device failed (%d)\n",
-			__func__, ret);
+		dev_err(dev, "%s: reboot_device failed (%d)\n", __func__, ret);
 
 	return ret;
 }

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 12020e4..f8fa4aa 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig

@@ -146,8 +146,8 @@
 	bool "RISC-V timer support"
 	depends on TIMER && RISCV
 	help
-	  Select this to enable support for the timer as defined
-	  by the RISC-V privileged architecture spec.
+	  Select this to enable support for a generic RISC-V S-Mode timer
+	  driver.
 
 config ROCKCHIP_TIMER
 	bool "Rockchip timer support"

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 9f9f070..449fcfc 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c

@@ -1,36 +1,37 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
+ * Copyright (C) 2012 Regents of the University of California
  *
- * RISC-V privileged architecture defined generic timer driver
+ * RISC-V architecturally-defined generic timer driver
  *
- * This driver relies on RISC-V platform codes to provide the essential API
- * riscv_get_time() which is supposed to return the timer counter as defined
- * by the RISC-V privileged architecture spec.
- *
- * This driver can be used in both M-mode and S-mode U-Boot.
+ * This driver provides generic timer support for S-mode U-Boot.
  */
 
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <timer.h>
-#include <asm/io.h>
-
-/**
- * riscv_get_time() - get the timer counter
- *
- * Platform codes should provide this API in order to make this driver function.
- *
- * @time:	the 64-bit timer count  as defined by the RISC-V privileged
- *		architecture spec.
- * @return:	0 on success, -ve on error.
- */
-extern int riscv_get_time(u64 *time);
+#include <asm/csr.h>
 
 static int riscv_timer_get_count(struct udevice *dev, u64 *count)
 {
-	return riscv_get_time(count);
+	if (IS_ENABLED(CONFIG_64BIT)) {
+		*count = csr_read(CSR_TIME);
+	} else {
+		u32 hi, lo;
+
+		do {
+			hi = csr_read(CSR_TIMEH);
+			lo = csr_read(CSR_TIME);
+		} while (hi != csr_read(CSR_TIMEH));
+
+		*count = ((u64)hi << 32) | lo;
+	}
+
+	return 0;
 }
 
 static int riscv_timer_probe(struct udevice *dev)

diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 5228486..6a503c2 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c

@@ -40,7 +40,9 @@
 {
 	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
-	if (!uc_priv->clock_rate)
+	if (dev_read_bool(dev, "sandbox,timebase-frequency-fallback"))
+		return timer_timebase_fallback(dev);
+	else if (!uc_priv->clock_rate)
 		uc_priv->clock_rate = SANDBOX_TIMER_RATE;
 
 	return 0;

diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 14dde95..e9802c8 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <cpu.h>
 #include <dm.h>
 #include <init.h>
 #include <dm/lists.h>
@@ -79,6 +80,36 @@
 	return 0;
 }
 
+/*
+ * TODO: should be CONFIG_IS_ENABLED(CPU), but the SPL config has _SUPPORT on
+ * the end...
+ */
+#if defined(CONFIG_CPU) || defined(CONFIG_SPL_CPU_SUPPORT)
+int timer_timebase_fallback(struct udevice *dev)
+{
+	struct udevice *cpu;
+	struct cpu_platdata *cpu_plat;
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	/* Did we get our clock rate from the device tree? */
+	if (uc_priv->clock_rate)
+		return 0;
+
+	/* Fall back to timebase-frequency */
+	dev_dbg(dev, "missing clocks or clock-frequency property; falling back on timebase-frequency\n");
+	cpu = cpu_get_current_dev();
+	if (!cpu)
+		return -ENODEV;
+
+	cpu_plat = dev_get_parent_platdata(cpu);
+	if (!cpu_plat)
+		return -ENODEV;
+
+	uc_priv->clock_rate = cpu_plat->timebase_freq;
+	return 0;
+}
+#endif
+
 u64 timer_conv_64(u32 count)
 {
 	/* increment tbh if tbl has rolled over */

diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 1942c07..64831a4 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c

@@ -14,11 +14,14 @@
 #include <log.h>
 #include <spl.h>
 #include <tpm-v2.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/iomap.h>
 #include <asm/arch/pm.h>
 #include <linux/delay.h>
+#include <dm/acpi.h>
 
 enum {
 	TIMEOUT_INIT_MS		= 30000, /* Very long timeout for TPM init */
@@ -581,6 +584,53 @@
 	return 0;
 }
 
+static int cr50_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+	char scope[ACPI_PATH_MAX];
+	char name[ACPI_NAME_MAX];
+	const char *hid;
+	int ret;
+
+	ret = acpi_device_scope(dev, scope, sizeof(scope));
+	if (ret)
+		return log_msg_ret("scope", ret);
+	ret = acpi_get_name(dev, name);
+	if (ret)
+		return log_msg_ret("name", ret);
+
+	hid = dev_read_string(dev, "acpi,hid");
+	if (!hid)
+		return log_msg_ret("hid", ret);
+
+	/* Device */
+	acpigen_write_scope(ctx, scope);
+	acpigen_write_device(ctx, name);
+	acpigen_write_name_string(ctx, "_HID", hid);
+	acpigen_write_name_integer(ctx, "_UID",
+				   dev_read_u32_default(dev, "acpi,uid", 0));
+	acpigen_write_name_string(ctx, "_DDN",
+				  dev_read_string(dev, "acpi,ddn"));
+	acpigen_write_sta(ctx, acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name(ctx, "_CRS");
+	acpigen_write_resourcetemplate_header(ctx);
+	ret = acpi_device_write_i2c_dev(ctx, dev);
+	if (ret < 0)
+		return log_msg_ret("i2c", ret);
+	ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
+						  "ready-gpios");
+	if (ret < 0)
+		return log_msg_ret("irq_gpio", ret);
+
+	acpigen_write_resourcetemplate_footer(ctx);
+
+	acpigen_pop_len(ctx); /* Device */
+	acpigen_pop_len(ctx); /* Scope */
+
+	return 0;
+}
+
 enum {
 	TPM_TIMEOUT_MS		= 5,
 	SHORT_TIMEOUT_MS	= 750,
@@ -653,6 +703,10 @@
 	return 0;
 }
 
+struct acpi_ops cr50_acpi_ops = {
+	.fill_ssdt	= cr50_acpi_fill_ssdt,
+};
+
 static const struct tpm_ops cr50_i2c_ops = {
 	.open		= cr50_i2c_open,
 	.get_desc	= cr50_i2c_get_desc,
@@ -675,5 +729,6 @@
 	.probe	= cr50_i2c_probe,
 	.remove	= cr50_i2c_cleanup,
 	.priv_auto_alloc_size = sizeof(struct cr50_priv),
+	ACPI_OPS_PTR(&cr50_acpi_ops)
 	.flags		= DM_FLAG_OS_PREPARE,
 };

diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
index a08c6945..acff79a 100644
--- a/drivers/usb/cdns3/ep0.c
+++ b/drivers/usb/cdns3/ep0.c

@@ -11,8 +11,9 @@
  */
 
 #include <cpu_func.h>
-#include <asm/cache.h>
+#include <dm.h>
 #include <dm/device_compat.h>
+#include <asm/cache.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/usb/composite.h>
@@ -810,7 +811,7 @@
 {
 	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
 
-	dev_dbg(priv_dev->dev, "Wedge for %s\n", ep->name);
+	dev_dbg(priv_ep->cdns3_dev->dev, "Wedge for %s\n", ep->name);
 	cdns3_gadget_ep_set_halt(ep, 1);
 	priv_ep->flags |= EP_WEDGE;
 

diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index 8f81d17..83dbb5a 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c

@@ -2399,8 +2399,7 @@
 	case USB_SPEED_SUPER:
 		break;
 	default:
-		dev_err(cdns->dev, "invalid speed parameter %d\n",
-			speed);
+		dev_err(priv_dev->dev, "invalid speed parameter %d\n", speed);
 	}
 
 	priv_dev->gadget.speed = speed;

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 8682556..2e00353 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c

@@ -592,7 +592,7 @@
 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 		ret = dwc3_gadget_init(dwc);
 		if (ret) {
-			dev_err(dev, "failed to initialize gadget\n");
+			dev_err(dwc->dev, "failed to initialize gadget\n");
 			return ret;
 		}
 		break;
@@ -600,7 +600,7 @@
 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 		ret = dwc3_host_init(dwc);
 		if (ret) {
-			dev_err(dev, "failed to initialize host\n");
+			dev_err(dwc->dev, "failed to initialize host\n");
 			return ret;
 		}
 		break;
@@ -608,18 +608,19 @@
 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 		ret = dwc3_host_init(dwc);
 		if (ret) {
-			dev_err(dev, "failed to initialize host\n");
+			dev_err(dwc->dev, "failed to initialize host\n");
 			return ret;
 		}
 
 		ret = dwc3_gadget_init(dwc);
 		if (ret) {
-			dev_err(dev, "failed to initialize gadget\n");
+			dev_err(dwc->dev, "failed to initialize gadget\n");
 			return ret;
 		}
 		break;
 	default:
-		dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
+		dev_err(dwc->dev,
+			"Unsupported mode of operation %d\n", dwc->dr_mode);
 		return -EINVAL;
 	}
 
@@ -768,7 +769,7 @@
 
 	ret = dwc3_core_init(dwc);
 	if (ret) {
-		dev_err(dev, "failed to initialize core\n");
+		dev_err(dwc->dev, "failed to initialize core\n");
 		goto err0;
 	}
 
@@ -974,7 +975,7 @@
 
 	ret = dwc3_core_init(dwc);
 	if (ret) {
-		dev_err(dev, "failed to initialize core\n");
+		dev_err(dwc->dev, "failed to initialize core\n");
 		goto core_fail;
 	}
 

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 551f682..36fa16a 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c

@@ -10,7 +10,6 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <log.h>
-#include <asm-generic/io.h>
 #include <dm.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
@@ -449,6 +448,7 @@
 	{ .compatible = "ti,am654-dwc3" },
 	{ .compatible = "rockchip,rk3328-dwc3" },
 	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "qcom,dwc3" },
 	{ }
 };
 

diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 385bed3..75ac993 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c

@@ -14,6 +14,7 @@
  */
 #include <common.h>
 #include <cpu_func.h>
+#include <dm.h>
 #include <dm/device_compat.h>
 #include <linux/bug.h>
 #include <linux/kernel.h>

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 2aec874..4e68fb0 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c

@@ -17,6 +17,7 @@
 #include <cpu_func.h>
 #include <log.h>
 #include <malloc.h>
+#include <dm.h>
 #include <dm/device_compat.h>
 #include <dm/devres.h>
 #include <linux/bug.h>
@@ -633,7 +634,7 @@
 		strlcat(dep->name, "-int", sizeof(dep->name));
 		break;
 	default:
-		dev_err(dwc->dev, "invalid endpoint transfer type\n");
+		dev_err(dep->dwc->dev, "invalid endpoint transfer type\n");
 	}
 
 	spin_lock_irqsave(&dwc->lock, flags);
@@ -708,10 +709,9 @@
 {
 	struct dwc3_trb		*trb;
 
-	dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
-			dep->name, req, (unsigned long long) dma,
-			length, last ? " last" : "",
-			chain ? " chain" : "");
+	dev_vdbg(dep->dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
+		 dep->name, req, (unsigned long long)dma,
+		 length, last ? " last" : "", chain ? " chain" : "");
 
 
 	trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
@@ -1074,21 +1074,22 @@
 
 	spin_lock_irqsave(&dwc->lock, flags);
 	if (!dep->endpoint.desc) {
-		dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
-				request, ep->name);
+		dev_dbg(dep->dwc->dev,
+			"trying to queue request %p to disabled %s\n", request,
+			ep->name);
 		ret = -ESHUTDOWN;
 		goto out;
 	}
 
 	if (req->dep != dep) {
-		WARN(true, "request %p belongs to '%s'\n",
-				request, req->dep->name);
+		WARN(true, "request %p belongs to '%s'\n", request,
+		     req->dep->name);
 		ret = -EINVAL;
 		goto out;
 	}
 
-	dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
-			request, ep->name, request->length);
+	dev_vdbg(dep->dwc->dev, "queing request %p to %s length %d\n",
+		 request, ep->name, request->length);
 
 	ret = __dwc3_gadget_ep_queue(dep, req);
 

diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c
index f8ab064..f476810 100644
--- a/drivers/usb/dwc3/ti_usb_phy.c
+++ b/drivers/usb/dwc3/ti_usb_phy.c

@@ -129,7 +129,7 @@
 			return &dpll_map->params;
 	}
 
-	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+	log_err("No DPLL configuration for %lu Hz SYS CLK\n", rate);
 
 	return NULL;
 }
@@ -269,7 +269,7 @@
 
 	phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
 	if (!phy) {
-		dev_err(NULL, "unable to alloc mem for TI USB3 PHY\n");
+		log_err("unable to alloc mem for TI USB3 PHY\n");
 		return -ENOMEM;
 	}
 

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7..4eb7b34 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig

@@ -200,8 +200,7 @@
 
 config USB_EHCI_ZYNQ
 	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
-	depends on ARCH_ZYNQ
-	default y
+	default y if ARCH_ZYNQ
 	---help---
 	  Enable support for Zynq on-chip EHCI USB controller
 

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index cefe9d8..f1d13b1 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c

@@ -114,7 +114,8 @@
  * @param regs Programming view of DWC_otg controller.
  * @param num Tx FIFO to flush.
  */
-static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
+static void dwc_otg_flush_tx_fifo(struct udevice *dev,
+				  struct dwc2_core_regs *regs, const int num)
 {
 	int ret;
 
@@ -134,7 +135,8 @@
  *
  * @param regs Programming view of DWC_otg controller.
  */
-static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
+static void dwc_otg_flush_rx_fifo(struct udevice *dev,
+				  struct dwc2_core_regs *regs)
 {
 	int ret;
 
@@ -152,7 +154,8 @@
  * Do core a soft reset of the core.  Be careful with this because it
  * resets all the internal state machines of the core.
  */
-static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
+static void dwc_otg_core_reset(struct udevice *dev,
+			       struct dwc2_core_regs *regs)
 {
 	int ret;
 
@@ -284,8 +287,8 @@
 	clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 
 	/* Make sure the FIFOs are flushed. */
-	dwc_otg_flush_tx_fifo(regs, 0x10);	/* All Tx FIFOs */
-	dwc_otg_flush_rx_fifo(regs);
+	dwc_otg_flush_tx_fifo(dev, regs, 0x10);	/* All Tx FIFOs */
+	dwc_otg_flush_rx_fifo(dev, regs);
 
 	/* Flush out any leftover queued requests. */
 	num_channels = readl(&regs->ghwcfg2);
@@ -306,7 +309,7 @@
 		ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 					DWC2_HCCHAR_CHEN, false, 1000, false);
 		if (ret)
-			dev_info("%s: Timeout!\n", __func__);
+			dev_info(dev, "%s: Timeout!\n", __func__);
 	}
 
 	/* Turn on the vbus power. */
@@ -330,8 +333,9 @@
  *
  * @param regs Programming view of the DWC_otg controller
  */
-static void dwc_otg_core_init(struct dwc2_priv *priv)
+static void dwc_otg_core_init(struct udevice *dev)
 {
+	struct dwc2_priv *priv = dev_get_priv(dev);
 	struct dwc2_core_regs *regs = priv->regs;
 	uint32_t ahbcfg = 0;
 	uint32_t usbcfg = 0;
@@ -360,7 +364,7 @@
 	writel(usbcfg, &regs->gusbcfg);
 
 	/* Reset the Controller */
-	dwc_otg_core_reset(regs);
+	dwc_otg_core_reset(dev, regs);
 
 	/*
 	 * This programming sequence needs to happen in FS mode before
@@ -372,7 +376,7 @@
 	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 
 	/* Reset after a PHY select */
-	dwc_otg_core_reset(regs);
+	dwc_otg_core_reset(dev, regs);
 
 	/*
 	 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
@@ -419,7 +423,7 @@
 	writel(usbcfg, &regs->gusbcfg);
 
 	/* Reset after setting the PHY parameters */
-	dwc_otg_core_reset(regs);
+	dwc_otg_core_reset(dev, regs);
 #endif
 
 	usbcfg = readl(&regs->gusbcfg);
@@ -1128,7 +1132,12 @@
 	timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 	for (;;) {
 		if (get_timer(0) > timeout) {
-			dev_err(dev, "Timeout poll on interrupt endpoint\n");
+#if CONFIG_IS_ENABLED(DM_USB)
+			dev_err(dev->dev,
+				"Timeout poll on interrupt endpoint\n");
+#else
+			log_err("Timeout poll on interrupt endpoint\n");
+#endif
 			return -ETIMEDOUT;
 		}
 		ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
@@ -1194,7 +1203,7 @@
 	priv->ext_vbus = 0;
 #endif
 
-	dwc_otg_core_init(priv);
+	dwc_otg_core_init(dev);
 	dwc_otg_core_host_init(dev, regs);
 
 	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
@@ -1320,12 +1329,10 @@
 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 {
 	struct dwc2_priv *priv = dev_get_priv(dev);
-	fdt_addr_t addr;
 
-	addr = dev_read_addr(dev);
-	if (addr == FDT_ADDR_T_NONE)
+	priv->regs = dev_read_addr_ptr(dev);
+	if (!priv->regs)
 		return -EINVAL;
-	priv->regs = (struct dwc2_core_regs *)addr;
 
 	priv->oc_disable = dev_read_bool(dev, "disable-over-current");
 	priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f79f063..8933f60 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c

@@ -1762,13 +1762,13 @@
 	} else {
 		ret = generic_phy_init(phy);
 		if (ret) {
-			dev_err(dev, "failed to init usb phy\n");
+			dev_dbg(dev, "failed to init usb phy\n");
 			return ret;
 		}
 
 		ret = generic_phy_power_on(phy);
 		if (ret) {
-			dev_err(dev, "failed to power on usb phy\n");
+			dev_dbg(dev, "failed to power on usb phy\n");
 			return generic_phy_exit(phy);
 		}
 	}
@@ -1786,13 +1786,13 @@
 	if (generic_phy_valid(phy)) {
 		ret = generic_phy_power_off(phy);
 		if (ret) {
-			dev_err(dev, "failed to power off usb phy\n");
+			dev_dbg(dev, "failed to power off usb phy\n");
 			return ret;
 		}
 
 		ret = generic_phy_exit(phy);
 		if (ret) {
-			dev_err(dev, "failed to power off usb phy\n");
+			dev_dbg(dev, "failed to power off usb phy\n");
 			return ret;
 		}
 	}

diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index b84bf8a..ed5e500 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c

@@ -41,13 +41,13 @@
 	} else {
 		ret = generic_phy_init(&priv->phy);
 		if (ret) {
-			dev_err(dev, "failed to init usb phy\n");
+			dev_dbg(dev, "failed to init usb phy\n");
 			return ret;
 		}
 
 		ret = generic_phy_power_on(&priv->phy);
 		if (ret) {
-			dev_err(dev, "failed to power on usb phy\n");
+			dev_dbg(dev, "failed to power on usb phy\n");
 			return generic_phy_exit(&priv->phy);
 		}
 	}
@@ -63,13 +63,13 @@
 	if (generic_phy_valid(&priv->phy)) {
 		ret = generic_phy_power_off(&priv->phy);
 		if (ret) {
-			dev_err(dev, "failed to power off usb phy\n");
+			dev_dbg(dev, "failed to power off usb phy\n");
 			return ret;
 		}
 
 		ret = generic_phy_exit(&priv->phy);
 		if (ret) {
-			dev_err(dev, "failed to power off usb phy\n");
+			dev_dbg(dev, "failed to power off usb phy\n");
 			return ret;
 		}
 	}

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 1da0524..0b49614 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c

@@ -236,8 +236,7 @@
 		 */
 		val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 		val &= ~TRB_TYPE_BITMASK;
-		val |= (TRB_LINK << TRB_TYPE_SHIFT);
-
+		val |= TRB_TYPE(TRB_LINK);
 		prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 	}
 }
@@ -826,25 +825,22 @@
 
 	/* Step 4 - ring already allocated */
 	/* Step 5 */
-	ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
+	ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
 	debug("SPEED = %d\n", speed);
 
 	switch (speed) {
 	case USB_SPEED_SUPER:
-		ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
-					MAX_PACKET_SHIFT));
+		ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
 		debug("Setting Packet size = 512bytes\n");
 		break;
 	case USB_SPEED_HIGH:
 	/* USB core guesses at a 64-byte max packet first for FS devices */
 	case USB_SPEED_FULL:
-		ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
-					MAX_PACKET_SHIFT));
+		ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
 		debug("Setting Packet size = 64bytes\n");
 		break;
 	case USB_SPEED_LOW:
-		ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
-					MAX_PACKET_SHIFT));
+		ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
 		debug("Setting Packet size = 8bytes\n");
 		break;
 	default:
@@ -853,9 +849,7 @@
 	}
 
 	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
-	ep0_ctx->ep_info2 |=
-			cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
-			((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+	ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
 
 	trb_64 = virt_to_phys(virt_dev->eps[0].ring->first_seg->trbs);
 	ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);

diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 8ff7185..f3f181d 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c

@@ -258,6 +258,7 @@
 	if (ret)
 		goto ssusb_init_err;
 
+	mtk->ctrl.quirks = XHCI_MTK_HOST;
 	hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
 			HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
 

diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 8fc51df..5379dba 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c

@@ -146,6 +146,7 @@
 }
 
 static const struct udevice_id xhci_rcar_ids[] = {
+	{ .compatible = "renesas,rcar-gen3-xhci" },
 	{ .compatible = "renesas,xhci-r8a7795" },
 	{ .compatible = "renesas,xhci-r8a7796" },
 	{ .compatible = "renesas,xhci-r8a77965" },

diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 092ed6e..b118207 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c

@@ -298,55 +298,57 @@
 	xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST);
 }
 
-/**
- * The TD size is the number of bytes remaining in the TD (including this TRB),
- * right shifted by 10.
- * It must fit in bits 21:17, so it can't be bigger than 31.
+/*
+ * For xHCI 1.0 host controllers, TD size is the number of max packet sized
+ * packets remaining in the TD (*not* including this TRB).
  *
- * @param remainder	remaining packets to be sent
- * @return remainder if remainder is less than max else max
- */
-static u32 xhci_td_remainder(unsigned int remainder)
-{
-	u32 max = (1 << (21 - 17 + 1)) - 1;
-
-	if ((remainder >> 10) >= max)
-		return max << 17;
-	else
-		return (remainder >> 10) << 17;
-}
-
-/**
- * Finds out the remanining packets to be sent
+ * Total TD packet count = total_packet_count =
+ *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
  *
- * @param running_total	total size sent so far
+ * Packets transferred up to and including this TRB = packets_transferred =
+ *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
+ *
+ * TD size = total_packet_count - packets_transferred
+ *
+ * For xHCI 0.96 and older, TD size field should be the remaining bytes
+ * including this TRB, right shifted by 10
+ *
+ * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
+ * This is taken care of in the TRB_TD_SIZE() macro
+ *
+ * The last TRB in a TD must have the TD size set to zero.
+ *
+ * @param ctrl	host controller data structure
+ * @param transferred	total size sent so far
  * @param trb_buff_len	length of the TRB Buffer
- * @param total_packet_count	total packet count
- * @param maxpacketsize		max packet size of current pipe
- * @param num_trbs_left		number of TRBs left to be processed
- * @return 0 if running_total or trb_buff_len is 0, else remainder
+ * @param td_total_len	total packet count
+ * @param maxp	max packet size of current pipe
+ * @param more_trbs_coming	indicate last trb in TD
+ * @return remainder
  */
-static u32 xhci_v1_0_td_remainder(int running_total,
-				int trb_buff_len,
-				unsigned int total_packet_count,
-				int maxpacketsize,
-				unsigned int num_trbs_left)
+static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred,
+			     int trb_buff_len, unsigned int td_total_len,
+			     int maxp, bool more_trbs_coming)
 {
-	int packets_transferred;
+	u32 total_packet_count;
+
+	/* MTK xHCI 0.96 contains some features from 1.0 */
+	if (ctrl->hci_version < 0x100 && !(ctrl->quirks & XHCI_MTK_HOST))
+		return ((td_total_len - transferred) >> 10);
 
 	/* One TRB with a zero-length data packet. */
-	if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
+	if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
+	    trb_buff_len == td_total_len)
 		return 0;
 
-	/*
-	 * All the TRB queueing functions don't count the current TRB in
-	 * running_total.
-	 */
-	packets_transferred = (running_total + trb_buff_len) / maxpacketsize;
+	/* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
+	if ((ctrl->quirks & XHCI_MTK_HOST) && (ctrl->hci_version < 0x100))
+		trb_buff_len = 0;
 
-	if ((total_packet_count - packets_transferred) > 31)
-		return 31 << 17;
-	return (total_packet_count - packets_transferred) << 17;
+	total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
+
+	/* Queueing functions don't count the current TRB into transferred */
+	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
 }
 
 /**
@@ -572,7 +574,7 @@
 	union xhci_trb *event;
 
 	int running_total, trb_buff_len;
-	unsigned int total_packet_count;
+	bool more_trbs_coming = true;
 	int maxpacketsize;
 	u64 addr;
 	int ret;
@@ -636,8 +638,6 @@
 	running_total = 0;
 	maxpacketsize = usb_maxpacket(udev, pipe);
 
-	total_packet_count = DIV_ROUND_UP(length, maxpacketsize);
-
 	/* How much data is in the first TRB? */
 	/*
 	 * How much data is (potentially) left before the 64KB boundary?
@@ -672,34 +672,30 @@
 		 * Chain all the TRBs together; clear the chain bit in the last
 		 * TRB to indicate it's the last TRB in the chain.
 		 */
-		if (num_trbs > 1)
+		if (num_trbs > 1) {
 			field |= TRB_CHAIN;
-		else
+		} else {
 			field |= TRB_IOC;
+			more_trbs_coming = false;
+		}
 
 		/* Only set interrupt on short packet for IN endpoints */
 		if (usb_pipein(pipe))
 			field |= TRB_ISP;
 
 		/* Set the TRB length, TD size, and interrupter fields. */
-		if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100)
-			remainder = xhci_td_remainder(length - running_total);
-		else
-			remainder = xhci_v1_0_td_remainder(running_total,
-							   trb_buff_len,
-							   total_packet_count,
-							   maxpacketsize,
-							   num_trbs - 1);
+		remainder = xhci_td_remainder(ctrl, running_total, trb_buff_len,
+					      length, maxpacketsize,
+					      more_trbs_coming);
 
-		length_field = ((trb_buff_len & TRB_LEN_MASK) |
-				remainder |
-				((0 & TRB_INTR_TARGET_MASK) <<
-				TRB_INTR_TARGET_SHIFT));
+		length_field = (TRB_LEN(trb_buff_len) |
+				TRB_TD_SIZE(remainder) |
+				TRB_INTR_TARGET(0));
 
 		trb_fields[0] = lower_32_bits(addr);
 		trb_fields[1] = upper_32_bits(addr);
 		trb_fields[2] = length_field;
-		trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
+		trb_fields[3] = field | TRB_TYPE(TRB_NORMAL);
 
 		queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
 
@@ -764,6 +760,7 @@
 	struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
 	struct xhci_ring *ep_ring;
 	union xhci_trb *event;
+	u32 remainder;
 
 	debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
 		req->request, req->request,
@@ -825,17 +822,17 @@
 	/* Queue setup TRB - see section 6.4.1.2.1 */
 	/* FIXME better way to translate setup_packet into two u32 fields? */
 	field = 0;
-	field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT);
+	field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
 	if (start_cycle == 0)
 		field |= 0x1;
 
 	/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
-	if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) >= 0x100) {
+	if (ctrl->hci_version >= 0x100 || ctrl->quirks & XHCI_MTK_HOST) {
 		if (length > 0) {
 			if (req->requesttype & USB_DIR_IN)
-				field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
+				field |= TRB_TX_TYPE(TRB_DATA_IN);
 			else
-				field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT);
+				field |= TRB_TX_TYPE(TRB_DATA_OUT);
 		}
 	}
 
@@ -851,8 +848,7 @@
 	trb_fields[1] = le16_to_cpu(req->index) |
 			le16_to_cpu(req->length) << 16;
 	/* TRB_LEN | (TRB_INTR_TARGET) */
-	trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) <<
-			TRB_INTR_TARGET_SHIFT));
+	trb_fields[2] = (TRB_LEN(8) | TRB_INTR_TARGET(0));
 	/* Immediate data in pointer */
 	trb_fields[3] = field;
 	queue_trb(ctrl, ep_ring, true, trb_fields);
@@ -862,16 +858,18 @@
 	/* If there's data, queue data TRBs */
 	/* Only set interrupt on short packet for IN endpoints */
 	if (usb_pipein(pipe))
-		field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT);
+		field = TRB_ISP | TRB_TYPE(TRB_DATA);
 	else
-		field = (TRB_DATA << TRB_TYPE_SHIFT);
+		field = TRB_TYPE(TRB_DATA);
 
-	length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) |
-			((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+	remainder = xhci_td_remainder(ctrl, 0, length, length,
+				      usb_maxpacket(udev, pipe), true);
+	length_field = TRB_LEN(length) | TRB_TD_SIZE(remainder) |
+		       TRB_INTR_TARGET(0);
 	debug("length_field = %d, length = %d,"
 		"xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n",
-		length_field, (length & TRB_LEN_MASK),
-		xhci_td_remainder(length), 0);
+		length_field, TRB_LEN(length),
+		TRB_TD_SIZE(remainder), 0);
 
 	if (length > 0) {
 		if (req->requesttype & USB_DIR_IN)
@@ -901,11 +899,10 @@
 
 	trb_fields[0] = 0;
 	trb_fields[1] = 0;
-	trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+	trb_fields[2] = TRB_INTR_TARGET(0);
 		/* Event on completion */
 	trb_fields[3] = field | TRB_IOC |
-			(TRB_STATUS << TRB_TYPE_SHIFT) |
-			ep_ring->cycle_state;
+			TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state;
 
 	queue_trb(ctrl, ep_ring, false, trb_fields);
 

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 126dabc..3547a9b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c

@@ -33,6 +33,7 @@
 #include <linux/bug.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/iopoll.h>
 #include <usb/xhci.h>
 
 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
@@ -143,23 +144,19 @@
  * @param usec	time to wait till
  * @return 0 if handshake is success else < 0 on failure
  */
-static int handshake(uint32_t volatile *ptr, uint32_t mask,
-					uint32_t done, int usec)
+static int
+handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec)
 {
 	uint32_t result;
+	int ret;
 
-	do {
-		result = xhci_readl(ptr);
-		if (result == ~(uint32_t)0)
-			return -ENODEV;
-		result &= mask;
-		if (result == done)
-			return 0;
-		usec--;
-		udelay(1);
-	} while (usec > 0);
+	ret = readx_poll_sleep_timeout(xhci_readl, ptr, result,
+				 (result & mask) == done || result == U32_MAX,
+				 1, usec);
+	if (result == U32_MAX)		/* card removed */
+		return -ENODEV;
 
-	return -ETIMEDOUT;
+	return ret;
 }
 
 /**
@@ -618,8 +615,7 @@
 			cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
 			EP_INTERVAL(interval) | EP_MULT(mult));
 
-		ep_ctx[ep_index]->ep_info2 =
-			cpu_to_le32(ep_type << EP_TYPE_SHIFT);
+		ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
 		ep_ctx[ep_index]->ep_info2 |=
 			cpu_to_le32(MAX_PACKET
 			(get_unaligned(&endpt_desc->wMaxPacketSize)));
@@ -650,7 +646,7 @@
 		 * are put into reserved DWs in Slot and Endpoint Contexts
 		 * for synchronous endpoints.
 		 */
-		if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) {
+		if (ctrl->quirks & XHCI_MTK_HOST) {
 			ep_ctx[ep_index]->reserved[0] =
 				cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
 		}
@@ -832,8 +828,7 @@
 				ctrl->devs[slot_id]->out_ctx, ep_index);
 		in_ctx = ctrl->devs[slot_id]->in_ctx;
 		ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
-		ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
-						<< MAX_PACKET_SHIFT));
+		ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
 		ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
 
 		/*
@@ -1257,8 +1252,7 @@
 		return -ENOMEM;
 
 	reg = xhci_readl(&hccr->cr_hcsparams1);
-	descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
-						HCS_MAX_PORTS_SHIFT);
+	descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg);
 	printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
 
 	/* Port Indicators */
@@ -1283,6 +1277,7 @@
 
 	reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
 	printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
+	ctrl->hci_version = reg;
 
 	return 0;
 }

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 53c336f..187db77 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c

@@ -257,7 +257,7 @@
 
 		ret = generic_phy_power_on(&glue->phy);
 		if (ret) {
-			pr_err("failed to power on USB PHY\n");
+			pr_debug("failed to power on USB PHY\n");
 			return ret;
 		}
 	}
@@ -281,7 +281,7 @@
 	if (is_host_enabled(musb)) {
 		ret = generic_phy_power_off(&glue->phy);
 		if (ret) {
-			pr_err("failed to power off USB PHY\n");
+			pr_debug("failed to power off USB PHY\n");
 			return;
 		}
 	}
@@ -301,21 +301,21 @@
 
 	ret = clk_enable(&glue->clk);
 	if (ret) {
-		dev_err(dev, "failed to enable clock\n");
+		dev_err(musb->controller, "failed to enable clock\n");
 		return ret;
 	}
 
 	if (reset_valid(&glue->rst)) {
 		ret = reset_deassert(&glue->rst);
 		if (ret) {
-			dev_err(dev, "failed to deassert reset\n");
+			dev_err(musb->controller, "failed to deassert reset\n");
 			goto err_clk;
 		}
 	}
 
 	ret = generic_phy_init(&glue->phy);
 	if (ret) {
-		dev_err(dev, "failed to init USB PHY\n");
+		dev_dbg(musb->controller, "failed to init USB PHY\n");
 		goto err_rst;
 	}
 
@@ -352,7 +352,8 @@
 	if (generic_phy_valid(&glue->phy)) {
 		ret = generic_phy_exit(&glue->phy);
 		if (ret) {
-			dev_err(dev, "failed to power off usb phy\n");
+			dev_dbg(musb->controller,
+				"failed to power off usb phy\n");
 			return ret;
 		}
 	}

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index badade3..3f07f4e 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c

@@ -1983,8 +1983,6 @@
 static int cfb_fb_is_in_dram(void)
 {
 	struct bd_info *bd = gd->bd;
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || \
-defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
 	ulong start, end;
 	int i;
 
@@ -1995,11 +1993,7 @@
 		    (ulong)video_fb_address < end)
 			return 1;
 	}
-#else
-	if ((ulong)video_fb_address >= bd->bi_memstart &&
-	    (ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize)
-		return 1;
-#endif
+
 	return 0;
 }
 

diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index b7bfbb5..2743836 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c

@@ -314,7 +314,8 @@
 				 val, !(val & GEN_CMD_FULL),
 				 CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
-		dev_err(dsi->dev, "failed to get available command FIFO\n");
+		dev_err(dsi->dsi_host.dev,
+			"failed to get available command FIFO\n");
 		return ret;
 	}
 
@@ -325,7 +326,7 @@
 				 val, (val & mask) == mask,
 				 CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
-		dev_err(dsi->dev, "failed to write command FIFO\n");
+		dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n");
 		return ret;
 	}
 
@@ -357,7 +358,7 @@
 					 val, !(val & GEN_PLD_W_FULL),
 					 CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
-			dev_err(dsi->dev,
+			dev_err(dsi->dsi_host.dev,
 				"failed to get available write payload FIFO\n");
 			return ret;
 		}
@@ -380,7 +381,7 @@
 				 val, !(val & GEN_RD_CMD_BUSY),
 				 CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret) {
-		dev_err(dsi->dev, "Timeout during read operation\n");
+		dev_err(dsi->dsi_host.dev, "Timeout during read operation\n");
 		return ret;
 	}
 
@@ -390,7 +391,8 @@
 					 val, !(val & GEN_PLD_R_EMPTY),
 					 CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret) {
-			dev_err(dsi->dev, "Read payload FIFO is empty\n");
+			dev_err(dsi->dsi_host.dev,
+				"Read payload FIFO is empty\n");
 			return ret;
 		}
 
@@ -411,7 +413,7 @@
 
 	ret = mipi_dsi_create_packet(&packet, msg);
 	if (ret) {
-		dev_err(dsi->dev, "failed to create packet: %d\n", ret);
+		dev_err(host->dev, "failed to create packet: %d\n", ret);
 		return ret;
 	}
 
@@ -702,13 +704,15 @@
 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 				 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
 	if (ret)
-		dev_warn(dsi->dev, "failed to wait phy lock state\n");
+		dev_warn(dsi->dsi_host.dev,
+			 "failed to wait phy lock state\n");
 
 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 				 val, val & PHY_STOP_STATE_CLK_LANE,
 				 PHY_STATUS_TIMEOUT_US);
 	if (ret)
-		dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
+		dev_warn(dsi->dsi_host.dev,
+			 "failed to wait phy clk lane stop state\n");
 }
 
 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
@@ -729,7 +733,7 @@
 	ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
 				     device->format, &dsi->lane_mbps);
 	if (ret)
-		dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
+		dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n");
 
 	dw_mipi_dsi_init_pll(dsi);
 	dw_mipi_dsi_dpi_config(dsi, timings);
@@ -748,7 +752,7 @@
 
 	ret = phy_ops->init(dsi->device);
 	if (ret)
-		dev_warn(dsi->dev, "Phy init() failed\n");
+		dev_warn(dsi->dsi_host.dev, "Phy init() failed\n");
 
 	dw_mipi_dsi_dphy_enable(dsi);
 

diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 2831513..9d5abac 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c

@@ -359,8 +359,7 @@
 
 	ret = panel_get_display_timing(priv->panel, &timings);
 	if (ret) {
-		ret = fdtdec_decode_display_timing(gd->fdt_blob,
-						   dev_of_offset(priv->panel),
+		ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
 						   0, &timings);
 		if (ret) {
 			dev_err(dev, "decode display timing error %d\n", ret);

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 2f3427a..7fff735 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c

@@ -366,8 +366,7 @@
 
 	ret = panel_get_display_timing(panel, &timings);
 	if (ret) {
-		ret = fdtdec_decode_display_timing(gd->fdt_blob,
-						   dev_of_offset(panel),
+		ret = ofnode_decode_display_timing(dev_ofnode(panel),
 						   0, &timings);
 		if (ret) {
 			dev_err(dev, "decode display timing error %d\n", ret);

diff --git a/env/Kconfig b/env/Kconfig
index b59ba31..f3a9925 100644
--- a/env/Kconfig
+++ b/env/Kconfig

@@ -422,7 +422,7 @@
 	string "Device and partition for where to store the environemt in FAT"
 	depends on ENV_IS_IN_FAT
 	default "0:1" if TI_COMMON_CMD_OPTIONS
-	default "0:auto" if ARCH_ZYNQMP
+	default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP
 	default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
 	default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
 	default "0" if ARCH_AT91

diff --git a/fs/btrfs/Makefile b/fs/btrfs/Makefile
index 9b31592..fc074c8 100644
--- a/fs/btrfs/Makefile
+++ b/fs/btrfs/Makefile

@@ -2,5 +2,6 @@
 #
 # 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
 
-obj-y := btrfs.o chunk-map.o compression.o ctree.o dev.o dir-item.o \
-	extent-io.o hash.o inode.o root.o subvolume.o super.o
+obj-y := btrfs.o compression.o ctree.o dev.o dir-item.o \
+	extent-io.o inode.o subvolume.o crypto/hash.o disk-io.o \
+	common/rbtree-utils.o extent-cache.o volumes.o root-tree.o

diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index de16217..cbf9dcf 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c

@@ -5,219 +5,280 @@
  * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
  */
 
-#include "btrfs.h"
 #include <config.h>
 #include <malloc.h>
 #include <uuid.h>
 #include <linux/time.h>
+#include "btrfs.h"
+#include "crypto/hash.h"
+#include "disk-io.h"
 
-struct btrfs_info btrfs_info;
+struct btrfs_fs_info *current_fs_info;
 
-static int readdir_callback(const struct btrfs_root *root,
-			    struct btrfs_dir_item *item)
+static int show_dir(struct btrfs_root *root, struct extent_buffer *eb,
+		    struct btrfs_dir_item *di)
 {
-	static const char typestr[BTRFS_FT_MAX][4] = {
-		[BTRFS_FT_UNKNOWN]  = " ? ",
-		[BTRFS_FT_REG_FILE] = "   ",
-		[BTRFS_FT_DIR]      = "DIR",
-		[BTRFS_FT_CHRDEV]   = "CHR",
-		[BTRFS_FT_BLKDEV]   = "BLK",
-		[BTRFS_FT_FIFO]     = "FIF",
-		[BTRFS_FT_SOCK]     = "SCK",
-		[BTRFS_FT_SYMLINK]  = "SYM",
-		[BTRFS_FT_XATTR]    = " ? ",
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	struct btrfs_inode_item ii;
+	struct btrfs_key key;
+	static const char* dir_item_str[] = {
+		[BTRFS_FT_REG_FILE]	= "FILE",
+		[BTRFS_FT_DIR] 		= "DIR",
+		[BTRFS_FT_CHRDEV]	= "CHRDEV",
+		[BTRFS_FT_BLKDEV]	= "BLKDEV",
+		[BTRFS_FT_FIFO]		= "FIFO",
+		[BTRFS_FT_SOCK]		= "SOCK",
+		[BTRFS_FT_SYMLINK]	= "SYMLINK",
+		[BTRFS_FT_XATTR]	= "XATTR"
 	};
-	struct btrfs_inode_item inode;
-	const char *name = (const char *) (item + 1);
-	char filetime[32], *target = NULL;
+	u8 type = btrfs_dir_type(eb, di);
+	char namebuf[BTRFS_NAME_LEN];
+	char *target = NULL;
+	char filetime[32];
 	time_t mtime;
+	int ret;
 
-	if (btrfs_lookup_inode(root, &item->location, &inode, NULL)) {
-		printf("%s: Cannot find inode item for directory entry %.*s!\n",
-		       __func__, item->name_len, name);
-		return 0;
-	}
+	btrfs_dir_item_key_to_cpu(eb, di, &key);
 
-	mtime = inode.mtime.sec;
-	ctime_r(&mtime, filetime);
+	if (key.type == BTRFS_ROOT_ITEM_KEY) {
+		struct btrfs_root *subvol;
 
-	if (item->type == BTRFS_FT_SYMLINK) {
-		target = malloc(min(inode.size + 1,
-				    (u64) btrfs_info.sb.sectorsize));
+		/* It's a subvolume, get its mtime from root item */
+		subvol = btrfs_read_fs_root(fs_info, &key);
+		if (IS_ERR(subvol)) {
+			ret = PTR_ERR(subvol);
+			error("Can't find root %llu", key.objectid);
+			return ret;
+		}
+		mtime = btrfs_stack_timespec_sec(&subvol->root_item.otime);
+	} else {
+		struct btrfs_path path;
 
-		if (target && btrfs_readlink(root, item->location.objectid,
-					     target)) {
-			free(target);
-			target = NULL;
+		/* It's regular inode, get its mtime from inode item */
+		btrfs_init_path(&path);
+		ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+		if (ret > 0)
+			ret = -ENOENT;
+		if (ret < 0) {
+			error("Can't find inode %llu", key.objectid);
+			btrfs_release_path(&path);
+			return ret;
 		}
+		read_extent_buffer(path.nodes[0], &ii,
+			btrfs_item_ptr_offset(path.nodes[0], path.slots[0]),
+			sizeof(ii));
+		btrfs_release_path(&path);
+		mtime = btrfs_stack_timespec_sec(&ii.mtime);
+	}
+	ctime_r(&mtime, filetime);
 
-		if (!target)
-			printf("%s: Cannot read symlink target!\n", __func__);
+	if (type == BTRFS_FT_SYMLINK) {
+		target = malloc(fs_info->sectorsize);
+		if (!target) {
+			error("Can't alloc memory for symlink %llu",
+				key.objectid);
+			return -ENOMEM;
+		}
+		ret = btrfs_readlink(root, key.objectid, target);
+		if (ret < 0) {
+			error("Failed to read symlink %llu", key.objectid);
+			goto out;
+		}
+		target[ret] = '\0';
 	}
 
-	printf("<%s> ", typestr[item->type]);
-	if (item->type == BTRFS_FT_CHRDEV || item->type == BTRFS_FT_BLKDEV)
-		printf("%4u,%5u  ", (unsigned int) (inode.rdev >> 20),
-			(unsigned int) (inode.rdev & 0xfffff));
+	if (type < ARRAY_SIZE(dir_item_str) && dir_item_str[type])
+		printf("<%s> ", dir_item_str[type]);
 	else
-		printf("%10llu  ", inode.size);
-
-	printf("%24.24s  %.*s", filetime, item->name_len, name);
-
-	if (item->type == BTRFS_FT_SYMLINK) {
-		printf(" -> %s", target ? target : "?");
-		if (target)
-			free(target);
+		printf("DIR_ITEM.%u", type);
+	if (type == BTRFS_FT_CHRDEV || type == BTRFS_FT_BLKDEV) {
+		ASSERT(key.type == BTRFS_INODE_ITEM_KEY);
+		printf("%4llu,%5llu  ", btrfs_stack_inode_rdev(&ii) >> 20,
+				btrfs_stack_inode_rdev(&ii) & 0xfffff);
+	} else {
+		if (key.type == BTRFS_INODE_ITEM_KEY)
+			printf("%10llu  ", btrfs_stack_inode_size(&ii));
+		else
+			printf("%10llu  ", 0ULL);
 	}
 
+	read_extent_buffer(eb, namebuf, (unsigned long)(di + 1),
+			   btrfs_dir_name_len(eb, di));
+	printf("%24.24s  %.*s", filetime, btrfs_dir_name_len(eb, di), namebuf);
+	if (type == BTRFS_FT_SYMLINK)
+		printf(" -> %s", target ? target : "?");
 	printf("\n");
-
-	return 0;
+out:
+	free(target);
+	return ret;
 }
 
 int btrfs_probe(struct blk_desc *fs_dev_desc,
 		struct disk_partition *fs_partition)
 {
-	btrfs_blk_desc = fs_dev_desc;
-	btrfs_part_info = fs_partition;
-
-	memset(&btrfs_info, 0, sizeof(btrfs_info));
+	struct btrfs_fs_info *fs_info;
+	int ret = -1;
 
 	btrfs_hash_init();
-	if (btrfs_read_superblock())
-		return -1;
-
-	if (btrfs_chunk_map_init()) {
-		printf("%s: failed to init chunk map\n", __func__);
-		return -1;
-	}
-
-	btrfs_info.tree_root.objectid = 0;
-	btrfs_info.tree_root.bytenr = btrfs_info.sb.root;
-	btrfs_info.chunk_root.objectid = 0;
-	btrfs_info.chunk_root.bytenr = btrfs_info.sb.chunk_root;
-
-	if (btrfs_read_chunk_tree()) {
-		printf("%s: failed to read chunk tree\n", __func__);
-		return -1;
+	fs_info = open_ctree_fs_info(fs_dev_desc, fs_partition);
+	if (fs_info) {
+		current_fs_info = fs_info;
+		ret = 0;
 	}
-
-	if (btrfs_find_root(btrfs_get_default_subvol_objectid(),
-			    &btrfs_info.fs_root, NULL)) {
-		printf("%s: failed to find default subvolume\n", __func__);
-		return -1;
-	}
-
-	return 0;
+	return ret;
 }
 
 int btrfs_ls(const char *path)
 {
-	struct btrfs_root root = btrfs_info.fs_root;
-	u64 inr;
+	struct btrfs_fs_info *fs_info = current_fs_info;
+	struct btrfs_root *root = fs_info->fs_root;
+	u64 ino = BTRFS_FIRST_FREE_OBJECTID;
 	u8 type;
+	int ret;
 
-	inr = btrfs_lookup_path(&root, root.root_dirid, path, &type, NULL, 40);
-
-	if (inr == -1ULL) {
+	ASSERT(fs_info);
+	ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
+				path, &root, &ino, &type, 40);
+	if (ret < 0) {
 		printf("Cannot lookup path %s\n", path);
-		return -1;
+		return ret;
 	}
 
 	if (type != BTRFS_FT_DIR) {
-		printf("Not a directory: %s\n", path);
-		return -1;
+		error("Not a directory: %s", path);
+		return -ENOENT;
 	}
-
-	if (btrfs_readdir(&root, inr, readdir_callback)) {
-		printf("An error occured while listing directory %s\n", path);
-		return -1;
+	ret = btrfs_iter_dir(root, ino, show_dir);
+	if (ret < 0) {
+		error("An error occured while listing directory %s", path);
+		return ret;
 	}
-
 	return 0;
 }
 
 int btrfs_exists(const char *file)
 {
-	struct btrfs_root root = btrfs_info.fs_root;
-	u64 inr;
+	struct btrfs_fs_info *fs_info = current_fs_info;
+	struct btrfs_root *root;
+	u64 ino;
 	u8 type;
+	int ret;
 
-	inr = btrfs_lookup_path(&root, root.root_dirid, file, &type, NULL, 40);
+	ASSERT(fs_info);
+
+	ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
+				file, &root, &ino, &type, 40);
+	if (ret < 0)
+		return 0;
 
-	return (inr != -1ULL && type == BTRFS_FT_REG_FILE);
+	if (type == BTRFS_FT_REG_FILE)
+		return 1;
+	return 0;
 }
 
 int btrfs_size(const char *file, loff_t *size)
 {
-	struct btrfs_root root = btrfs_info.fs_root;
-	struct btrfs_inode_item inode;
-	u64 inr;
+	struct btrfs_fs_info *fs_info = current_fs_info;
+	struct btrfs_inode_item *ii;
+	struct btrfs_root *root;
+	struct btrfs_path path;
+	struct btrfs_key key;
+	u64 ino;
 	u8 type;
+	int ret;
 
-	inr = btrfs_lookup_path(&root, root.root_dirid, file, &type, &inode,
-				40);
-
-	if (inr == -1ULL) {
+	ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
+				file, &root, &ino, &type, 40);
+	if (ret < 0) {
 		printf("Cannot lookup file %s\n", file);
-		return -1;
+		return ret;
 	}
-
 	if (type != BTRFS_FT_REG_FILE) {
 		printf("Not a regular file: %s\n", file);
-		return -1;
+		return -ENOENT;
 	}
+	btrfs_init_path(&path);
+	key.objectid = ino;
+	key.type = BTRFS_INODE_ITEM_KEY;
+	key.offset = 0;
 
-	*size = inode.size;
-	return 0;
+	ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+	if (ret < 0) {
+		printf("Cannot lookup ino %llu\n", ino);
+		return ret;
+	}
+	if (ret > 0) {
+		printf("Ino %llu does not exist\n", ino);
+		ret = -ENOENT;
+		goto out;
+	}
+	ii = btrfs_item_ptr(path.nodes[0], path.slots[0],
+			    struct btrfs_inode_item);
+	*size = btrfs_inode_size(path.nodes[0], ii);
+out:
+	btrfs_release_path(&path);
+	return ret;
 }
 
 int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len,
 	       loff_t *actread)
 {
-	struct btrfs_root root = btrfs_info.fs_root;
-	struct btrfs_inode_item inode;
-	u64 inr, rd;
+	struct btrfs_fs_info *fs_info = current_fs_info;
+	struct btrfs_root *root;
+	loff_t real_size = 0;
+	u64 ino;
 	u8 type;
-
-	inr = btrfs_lookup_path(&root, root.root_dirid, file, &type, &inode,
-				40);
+	int ret;
 
-	if (inr == -1ULL) {
-		printf("Cannot lookup file %s\n", file);
-		return -1;
+	ASSERT(fs_info);
+	ret = btrfs_lookup_path(fs_info->fs_root, BTRFS_FIRST_FREE_OBJECTID,
+				file, &root, &ino, &type, 40);
+	if (ret < 0) {
+		error("Cannot lookup file %s", file);
+		return ret;
 	}
 
 	if (type != BTRFS_FT_REG_FILE) {
-		printf("Not a regular file: %s\n", file);
-		return -1;
+		error("Not a regular file: %s", file);
+		return -EINVAL;
 	}
 
-	if (!len)
-		len = inode.size;
+	if (!len) {
+		ret = btrfs_size(file, &real_size);
+		if (ret < 0) {
+			error("Failed to get inode size: %s", file);
+			return ret;
+		}
+		len = real_size;
+	}
 
-	if (len > inode.size - offset)
-		len = inode.size - offset;
+	if (len > real_size - offset)
+		len = real_size - offset;
 
-	rd = btrfs_file_read(&root, inr, offset, len, buf);
-	if (rd == -1ULL) {
-		printf("An error occured while reading file %s\n", file);
-		return -1;
+	ret = btrfs_file_read(root, ino, offset, len, buf);
+	if (ret < 0) {
+		error("An error occured while reading file %s", file);
+		return ret;
 	}
 
-	*actread = rd;
+	*actread = len;
 	return 0;
 }
 
 void btrfs_close(void)
 {
-	btrfs_chunk_map_exit();
+	if (current_fs_info) {
+		close_ctree_fs_info(current_fs_info);
+		current_fs_info = NULL;
+	}
 }
 
 int btrfs_uuid(char *uuid_str)
 {
 #ifdef CONFIG_LIB_UUID
-	uuid_bin_to_str(btrfs_info.sb.fsid, uuid_str, UUID_STR_FORMAT_STD);
+	if (current_fs_info)
+		uuid_bin_to_str(current_fs_info->super_copy->fsid, uuid_str,
+				UUID_STR_FORMAT_STD);
 	return 0;
 #endif
 	return -ENOSYS;

diff --git a/fs/btrfs/btrfs.h b/fs/btrfs/btrfs.h
index 25a8cf6..7d8b395 100644
--- a/fs/btrfs/btrfs.h
+++ b/fs/btrfs/btrfs.h

@@ -11,77 +11,18 @@
 #include <linux/rbtree.h>
 #include "conv-funcs.h"
 
-struct btrfs_info {
-	struct btrfs_super_block sb;
-
-	struct btrfs_root tree_root;
-	struct btrfs_root fs_root;
-	struct btrfs_root chunk_root;
-
-	struct rb_root chunks_root;
-};
-
 extern struct btrfs_info btrfs_info;
-
-/* hash.c */
-void btrfs_hash_init(void);
-u32 btrfs_crc32c(u32, const void *, size_t);
-u32 btrfs_csum_data(char *, u32, size_t);
-void btrfs_csum_final(u32, void *);
-
-static inline u64 btrfs_name_hash(const char *name, int len)
-{
-	return btrfs_crc32c((u32) ~1, name, len);
-}
-
-/* dev.c */
-extern struct blk_desc *btrfs_blk_desc;
-extern struct disk_partition *btrfs_part_info;
-
-int btrfs_devread(u64, int, void *);
-
-/* chunk-map.c */
-u64 btrfs_map_logical_to_physical(u64);
-int btrfs_chunk_map_init(void);
-void btrfs_chunk_map_exit(void);
-int btrfs_read_chunk_tree(void);
+extern struct btrfs_fs_info *current_fs_info;
 
 /* compression.c */
 u32 btrfs_decompress(u8 type, const char *, u32, char *, u32);
 
-/* super.c */
-int btrfs_read_superblock(void);
-
-/* dir-item.c */
-typedef int (*btrfs_readdir_callback_t)(const struct btrfs_root *,
-					struct btrfs_dir_item *);
-
-int btrfs_lookup_dir_item(const struct btrfs_root *, u64, const char *, int,
-			   struct btrfs_dir_item *);
-int btrfs_readdir(const struct btrfs_root *, u64, btrfs_readdir_callback_t);
-
-/* root.c */
-int btrfs_find_root(u64, struct btrfs_root *, struct btrfs_root_item *);
-u64 btrfs_lookup_root_ref(u64, struct btrfs_root_ref *, char *);
-
 /* inode.c */
-u64 btrfs_lookup_inode_ref(struct btrfs_root *, u64, struct btrfs_inode_ref *,
-			    char *);
-int btrfs_lookup_inode(const struct btrfs_root *, struct btrfs_key *,
-		        struct btrfs_inode_item *, struct btrfs_root *);
-int btrfs_readlink(const struct btrfs_root *, u64, char *);
-u64 btrfs_lookup_path(struct btrfs_root *, u64, const char *, u8 *,
-		       struct btrfs_inode_item *, int);
-u64 btrfs_file_read(const struct btrfs_root *, u64, u64, u64, char *);
+int btrfs_readlink(struct btrfs_root *root, u64 ino, char *target);
+int btrfs_file_read(struct btrfs_root *root, u64 ino, u64 file_offset, u64 len,
+		    char *dest);
 
 /* subvolume.c */
 u64 btrfs_get_default_subvol_objectid(void);
 
-/* extent-io.c */
-u64 btrfs_read_extent_inline(struct btrfs_path *,
-			      struct btrfs_file_extent_item *, u64, u64,
-			      char *);
-u64 btrfs_read_extent_reg(struct btrfs_path *, struct btrfs_file_extent_item *,
-			   u64, u64, char *);
-
 #endif /* !__BTRFS_BTRFS_H__ */

diff --git a/fs/btrfs/btrfs_tree.h b/fs/btrfs/btrfs_tree.h
deleted file mode 100644
index aa0f3d6..0000000
--- a/fs/btrfs/btrfs_tree.h
+++ /dev/null

@@ -1,766 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * From linux/include/uapi/linux/btrfs_tree.h
- */
-
-#ifndef __BTRFS_BTRFS_TREE_H__
-#define __BTRFS_BTRFS_TREE_H__
-
-#include <common.h>
-
-#define BTRFS_VOL_NAME_MAX 255
-#define BTRFS_NAME_MAX 255
-#define BTRFS_LABEL_SIZE 256
-#define BTRFS_FSID_SIZE 16
-#define BTRFS_UUID_SIZE 16
-
-/*
- * This header contains the structure definitions and constants used
- * by file system objects that can be retrieved using
- * the BTRFS_IOC_SEARCH_TREE ioctl.  That means basically anything that
- * is needed to describe a leaf node's key or item contents.
- */
-
-/* holds pointers to all of the tree roots */
-#define BTRFS_ROOT_TREE_OBJECTID 1ULL
-
-/* stores information about which extents are in use, and reference counts */
-#define BTRFS_EXTENT_TREE_OBJECTID 2ULL
-
-/*
- * chunk tree stores translations from logical -> physical block numbering
- * the super block points to the chunk tree
- */
-#define BTRFS_CHUNK_TREE_OBJECTID 3ULL
-
-/*
- * stores information about which areas of a given device are in use.
- * one per device.  The tree of tree roots points to the device tree
- */
-#define BTRFS_DEV_TREE_OBJECTID 4ULL
-
-/* one per subvolume, storing files and directories */
-#define BTRFS_FS_TREE_OBJECTID 5ULL
-
-/* directory objectid inside the root tree */
-#define BTRFS_ROOT_TREE_DIR_OBJECTID 6ULL
-
-/* holds checksums of all the data extents */
-#define BTRFS_CSUM_TREE_OBJECTID 7ULL
-
-/* holds quota configuration and tracking */
-#define BTRFS_QUOTA_TREE_OBJECTID 8ULL
-
-/* for storing items that use the BTRFS_UUID_KEY* types */
-#define BTRFS_UUID_TREE_OBJECTID 9ULL
-
-/* tracks free space in block groups. */
-#define BTRFS_FREE_SPACE_TREE_OBJECTID 10ULL
-
-/* device stats in the device tree */
-#define BTRFS_DEV_STATS_OBJECTID 0ULL
-
-/* for storing balance parameters in the root tree */
-#define BTRFS_BALANCE_OBJECTID -4ULL
-
-/* orhpan objectid for tracking unlinked/truncated files */
-#define BTRFS_ORPHAN_OBJECTID -5ULL
-
-/* does write ahead logging to speed up fsyncs */
-#define BTRFS_TREE_LOG_OBJECTID -6ULL
-#define BTRFS_TREE_LOG_FIXUP_OBJECTID -7ULL
-
-/* for space balancing */
-#define BTRFS_TREE_RELOC_OBJECTID -8ULL
-#define BTRFS_DATA_RELOC_TREE_OBJECTID -9ULL
-
-/*
- * extent checksums all have this objectid
- * this allows them to share the logging tree
- * for fsyncs
- */
-#define BTRFS_EXTENT_CSUM_OBJECTID -10ULL
-
-/* For storing free space cache */
-#define BTRFS_FREE_SPACE_OBJECTID -11ULL
-
-/*
- * The inode number assigned to the special inode for storing
- * free ino cache
- */
-#define BTRFS_FREE_INO_OBJECTID -12ULL
-
-/* dummy objectid represents multiple objectids */
-#define BTRFS_MULTIPLE_OBJECTIDS -255ULL
-
-/*
- * All files have objectids in this range.
- */
-#define BTRFS_FIRST_FREE_OBJECTID 256ULL
-#define BTRFS_LAST_FREE_OBJECTID -256ULL
-#define BTRFS_FIRST_CHUNK_TREE_OBJECTID 256ULL
-
-
-/*
- * the device items go into the chunk tree.  The key is in the form
- * [ 1 BTRFS_DEV_ITEM_KEY device_id ]
- */
-#define BTRFS_DEV_ITEMS_OBJECTID 1ULL
-
-#define BTRFS_BTREE_INODE_OBJECTID 1
-
-#define BTRFS_EMPTY_SUBVOL_DIR_OBJECTID 2
-
-#define BTRFS_DEV_REPLACE_DEVID 0ULL
-
-/*
- * inode items have the data typically returned from stat and store other
- * info about object characteristics.  There is one for every file and dir in
- * the FS
- */
-#define BTRFS_INODE_ITEM_KEY		1
-#define BTRFS_INODE_REF_KEY		12
-#define BTRFS_INODE_EXTREF_KEY		13
-#define BTRFS_XATTR_ITEM_KEY		24
-#define BTRFS_ORPHAN_ITEM_KEY		48
-/* reserve 2-15 close to the inode for later flexibility */
-
-/*
- * dir items are the name -> inode pointers in a directory.  There is one
- * for every name in a directory.
- */
-#define BTRFS_DIR_LOG_ITEM_KEY  60
-#define BTRFS_DIR_LOG_INDEX_KEY 72
-#define BTRFS_DIR_ITEM_KEY	84
-#define BTRFS_DIR_INDEX_KEY	96
-/*
- * extent data is for file data
- */
-#define BTRFS_EXTENT_DATA_KEY	108
-
-/*
- * extent csums are stored in a separate tree and hold csums for
- * an entire extent on disk.
- */
-#define BTRFS_EXTENT_CSUM_KEY	128
-
-/*
- * root items point to tree roots.  They are typically in the root
- * tree used by the super block to find all the other trees
- */
-#define BTRFS_ROOT_ITEM_KEY	132
-
-/*
- * root backrefs tie subvols and snapshots to the directory entries that
- * reference them
- */
-#define BTRFS_ROOT_BACKREF_KEY	144
-
-/*
- * root refs make a fast index for listing all of the snapshots and
- * subvolumes referenced by a given root.  They point directly to the
- * directory item in the root that references the subvol
- */
-#define BTRFS_ROOT_REF_KEY	156
-
-/*
- * extent items are in the extent map tree.  These record which blocks
- * are used, and how many references there are to each block
- */
-#define BTRFS_EXTENT_ITEM_KEY	168
-
-/*
- * The same as the BTRFS_EXTENT_ITEM_KEY, except it's metadata we already know
- * the length, so we save the level in key->offset instead of the length.
- */
-#define BTRFS_METADATA_ITEM_KEY	169
-
-#define BTRFS_TREE_BLOCK_REF_KEY	176
-
-#define BTRFS_EXTENT_DATA_REF_KEY	178
-
-#define BTRFS_EXTENT_REF_V0_KEY		180
-
-#define BTRFS_SHARED_BLOCK_REF_KEY	182
-
-#define BTRFS_SHARED_DATA_REF_KEY	184
-
-/*
- * block groups give us hints into the extent allocation trees.  Which
- * blocks are free etc etc
- */
-#define BTRFS_BLOCK_GROUP_ITEM_KEY 192
-
-/*
- * Every block group is represented in the free space tree by a free space info
- * item, which stores some accounting information. It is keyed on
- * (block_group_start, FREE_SPACE_INFO, block_group_length).
- */
-#define BTRFS_FREE_SPACE_INFO_KEY 198
-
-/*
- * A free space extent tracks an extent of space that is free in a block group.
- * It is keyed on (start, FREE_SPACE_EXTENT, length).
- */
-#define BTRFS_FREE_SPACE_EXTENT_KEY 199
-
-/*
- * When a block group becomes very fragmented, we convert it to use bitmaps
- * instead of extents. A free space bitmap is keyed on
- * (start, FREE_SPACE_BITMAP, length); the corresponding item is a bitmap with
- * (length / sectorsize) bits.
- */
-#define BTRFS_FREE_SPACE_BITMAP_KEY 200
-
-#define BTRFS_DEV_EXTENT_KEY	204
-#define BTRFS_DEV_ITEM_KEY	216
-#define BTRFS_CHUNK_ITEM_KEY	228
-
-/*
- * Records the overall state of the qgroups.
- * There's only one instance of this key present,
- * (0, BTRFS_QGROUP_STATUS_KEY, 0)
- */
-#define BTRFS_QGROUP_STATUS_KEY         240
-/*
- * Records the currently used space of the qgroup.
- * One key per qgroup, (0, BTRFS_QGROUP_INFO_KEY, qgroupid).
- */
-#define BTRFS_QGROUP_INFO_KEY           242
-/*
- * Contains the user configured limits for the qgroup.
- * One key per qgroup, (0, BTRFS_QGROUP_LIMIT_KEY, qgroupid).
- */
-#define BTRFS_QGROUP_LIMIT_KEY          244
-/*
- * Records the child-parent relationship of qgroups. For
- * each relation, 2 keys are present:
- * (childid, BTRFS_QGROUP_RELATION_KEY, parentid)
- * (parentid, BTRFS_QGROUP_RELATION_KEY, childid)
- */
-#define BTRFS_QGROUP_RELATION_KEY       246
-
-/*
- * Obsolete name, see BTRFS_TEMPORARY_ITEM_KEY.
- */
-#define BTRFS_BALANCE_ITEM_KEY	248
-
-/*
- * The key type for tree items that are stored persistently, but do not need to
- * exist for extended period of time. The items can exist in any tree.
- *
- * [subtype, BTRFS_TEMPORARY_ITEM_KEY, data]
- *
- * Existing items:
- *
- * - balance status item
- *   (BTRFS_BALANCE_OBJECTID, BTRFS_TEMPORARY_ITEM_KEY, 0)
- */
-#define BTRFS_TEMPORARY_ITEM_KEY	248
-
-/*
- * Obsolete name, see BTRFS_PERSISTENT_ITEM_KEY
- */
-#define BTRFS_DEV_STATS_KEY		249
-
-/*
- * The key type for tree items that are stored persistently and usually exist
- * for a long period, eg. filesystem lifetime. The item kinds can be status
- * information, stats or preference values. The item can exist in any tree.
- *
- * [subtype, BTRFS_PERSISTENT_ITEM_KEY, data]
- *
- * Existing items:
- *
- * - device statistics, store IO stats in the device tree, one key for all
- *   stats
- *   (BTRFS_DEV_STATS_OBJECTID, BTRFS_DEV_STATS_KEY, 0)
- */
-#define BTRFS_PERSISTENT_ITEM_KEY	249
-
-/*
- * Persistantly stores the device replace state in the device tree.
- * The key is built like this: (0, BTRFS_DEV_REPLACE_KEY, 0).
- */
-#define BTRFS_DEV_REPLACE_KEY	250
-
-/*
- * Stores items that allow to quickly map UUIDs to something else.
- * These items are part of the filesystem UUID tree.
- * The key is built like this:
- * (UUID_upper_64_bits, BTRFS_UUID_KEY*, UUID_lower_64_bits).
- */
-#if BTRFS_UUID_SIZE != 16
-#error "UUID items require BTRFS_UUID_SIZE == 16!"
-#endif
-#define BTRFS_UUID_KEY_SUBVOL	251	/* for UUIDs assigned to subvols */
-#define BTRFS_UUID_KEY_RECEIVED_SUBVOL	252	/* for UUIDs assigned to
-						 * received subvols */
-
-/*
- * string items are for debugging.  They just store a short string of
- * data in the FS
- */
-#define BTRFS_STRING_ITEM_KEY	253
-
-
-
-/* 32 bytes in various csum fields */
-#define BTRFS_CSUM_SIZE 32
-
-/* csum types */
-#define BTRFS_CSUM_TYPE_CRC32	0
-
-/*
- * flags definitions for directory entry item type
- *
- * Used by:
- * struct btrfs_dir_item.type
- */
-#define BTRFS_FT_UNKNOWN	0
-#define BTRFS_FT_REG_FILE	1
-#define BTRFS_FT_DIR		2
-#define BTRFS_FT_CHRDEV		3
-#define BTRFS_FT_BLKDEV		4
-#define BTRFS_FT_FIFO		5
-#define BTRFS_FT_SOCK		6
-#define BTRFS_FT_SYMLINK	7
-#define BTRFS_FT_XATTR		8
-#define BTRFS_FT_MAX		9
-
-/*
- * The key defines the order in the tree, and so it also defines (optimal)
- * block layout.
- *
- * objectid corresponds to the inode number.
- *
- * type tells us things about the object, and is a kind of stream selector.
- * so for a given inode, keys with type of 1 might refer to the inode data,
- * type of 2 may point to file data in the btree and type == 3 may point to
- * extents.
- *
- * offset is the starting byte offset for this key in the stream.
- */
-
-struct btrfs_key {
-	__u64 objectid;
-	__u8 type;
-	__u64 offset;
-} __attribute__ ((__packed__));
-
-struct btrfs_dev_item {
-	/* the internal btrfs device id */
-	__u64 devid;
-
-	/* size of the device */
-	__u64 total_bytes;
-
-	/* bytes used */
-	__u64 bytes_used;
-
-	/* optimal io alignment for this device */
-	__u32 io_align;
-
-	/* optimal io width for this device */
-	__u32 io_width;
-
-	/* minimal io size for this device */
-	__u32 sector_size;
-
-	/* type and info about this device */
-	__u64 type;
-
-	/* expected generation for this device */
-	__u64 generation;
-
-	/*
-	 * starting byte of this partition on the device,
-	 * to allow for stripe alignment in the future
-	 */
-	__u64 start_offset;
-
-	/* grouping information for allocation decisions */
-	__u32 dev_group;
-
-	/* seek speed 0-100 where 100 is fastest */
-	__u8 seek_speed;
-
-	/* bandwidth 0-100 where 100 is fastest */
-	__u8 bandwidth;
-
-	/* btrfs generated uuid for this device */
-	__u8 uuid[BTRFS_UUID_SIZE];
-
-	/* uuid of FS who owns this device */
-	__u8 fsid[BTRFS_UUID_SIZE];
-} __attribute__ ((__packed__));
-
-struct btrfs_stripe {
-	__u64 devid;
-	__u64 offset;
-	__u8 dev_uuid[BTRFS_UUID_SIZE];
-} __attribute__ ((__packed__));
-
-struct btrfs_chunk {
-	/* size of this chunk in bytes */
-	__u64 length;
-
-	/* objectid of the root referencing this chunk */
-	__u64 owner;
-
-	__u64 stripe_len;
-	__u64 type;
-
-	/* optimal io alignment for this chunk */
-	__u32 io_align;
-
-	/* optimal io width for this chunk */
-	__u32 io_width;
-
-	/* minimal io size for this chunk */
-	__u32 sector_size;
-
-	/* 2^16 stripes is quite a lot, a second limit is the size of a single
-	 * item in the btree
-	 */
-	__u16 num_stripes;
-
-	/* sub stripes only matter for raid10 */
-	__u16 sub_stripes;
-	struct btrfs_stripe stripe;
-	/* additional stripes go here */
-} __attribute__ ((__packed__));
-
-#define BTRFS_FREE_SPACE_EXTENT	1
-#define BTRFS_FREE_SPACE_BITMAP	2
-
-struct btrfs_free_space_entry {
-	__u64 offset;
-	__u64 bytes;
-	__u8 type;
-} __attribute__ ((__packed__));
-
-struct btrfs_free_space_header {
-	struct btrfs_key location;
-	__u64 generation;
-	__u64 num_entries;
-	__u64 num_bitmaps;
-} __attribute__ ((__packed__));
-
-#define BTRFS_HEADER_FLAG_WRITTEN	(1ULL << 0)
-#define BTRFS_HEADER_FLAG_RELOC		(1ULL << 1)
-
-/* Super block flags */
-/* Errors detected */
-#define BTRFS_SUPER_FLAG_ERROR		(1ULL << 2)
-
-#define BTRFS_SUPER_FLAG_SEEDING	(1ULL << 32)
-#define BTRFS_SUPER_FLAG_METADUMP	(1ULL << 33)
-
-
-/*
- * items in the extent btree are used to record the objectid of the
- * owner of the block and the number of references
- */
-
-struct btrfs_extent_item {
-	__u64 refs;
-	__u64 generation;
-	__u64 flags;
-} __attribute__ ((__packed__));
-
-
-#define BTRFS_EXTENT_FLAG_DATA		(1ULL << 0)
-#define BTRFS_EXTENT_FLAG_TREE_BLOCK	(1ULL << 1)
-
-/* following flags only apply to tree blocks */
-
-/* use full backrefs for extent pointers in the block */
-#define BTRFS_BLOCK_FLAG_FULL_BACKREF	(1ULL << 8)
-
-/*
- * this flag is only used internally by scrub and may be changed at any time
- * it is only declared here to avoid collisions
- */
-#define BTRFS_EXTENT_FLAG_SUPER		(1ULL << 48)
-
-struct btrfs_tree_block_info {
-	struct btrfs_key key;
-	__u8 level;
-} __attribute__ ((__packed__));
-
-struct btrfs_extent_data_ref {
-	__u64 root;
-	__u64 objectid;
-	__u64 offset;
-	__u32 count;
-} __attribute__ ((__packed__));
-
-struct btrfs_shared_data_ref {
-	__u32 count;
-} __attribute__ ((__packed__));
-
-struct btrfs_extent_inline_ref {
-	__u8 type;
-	__u64 offset;
-} __attribute__ ((__packed__));
-
-/* dev extents record free space on individual devices.  The owner
- * field points back to the chunk allocation mapping tree that allocated
- * the extent.  The chunk tree uuid field is a way to double check the owner
- */
-struct btrfs_dev_extent {
-	__u64 chunk_tree;
-	__u64 chunk_objectid;
-	__u64 chunk_offset;
-	__u64 length;
-	__u8 chunk_tree_uuid[BTRFS_UUID_SIZE];
-} __attribute__ ((__packed__));
-
-struct btrfs_inode_ref {
-	__u64 index;
-	__u16 name_len;
-	/* name goes here */
-} __attribute__ ((__packed__));
-
-struct btrfs_inode_extref {
-	__u64 parent_objectid;
-	__u64 index;
-	__u16 name_len;
-	__u8   name[0];
-	/* name goes here */
-} __attribute__ ((__packed__));
-
-struct btrfs_timespec {
-	__u64 sec;
-	__u32 nsec;
-} __attribute__ ((__packed__));
-
-struct btrfs_inode_item {
-	/* nfs style generation number */
-	__u64 generation;
-	/* transid that last touched this inode */
-	__u64 transid;
-	__u64 size;
-	__u64 nbytes;
-	__u64 block_group;
-	__u32 nlink;
-	__u32 uid;
-	__u32 gid;
-	__u32 mode;
-	__u64 rdev;
-	__u64 flags;
-
-	/* modification sequence number for NFS */
-	__u64 sequence;
-
-	/*
-	 * a little future expansion, for more than this we can
-	 * just grow the inode item and version it
-	 */
-	__u64 reserved[4];
-	struct btrfs_timespec atime;
-	struct btrfs_timespec ctime;
-	struct btrfs_timespec mtime;
-	struct btrfs_timespec otime;
-} __attribute__ ((__packed__));
-
-struct btrfs_dir_log_item {
-	__u64 end;
-} __attribute__ ((__packed__));
-
-struct btrfs_dir_item {
-	struct btrfs_key location;
-	__u64 transid;
-	__u16 data_len;
-	__u16 name_len;
-	__u8 type;
-} __attribute__ ((__packed__));
-
-#define BTRFS_ROOT_SUBVOL_RDONLY	(1ULL << 0)
-
-/*
- * Internal in-memory flag that a subvolume has been marked for deletion but
- * still visible as a directory
- */
-#define BTRFS_ROOT_SUBVOL_DEAD		(1ULL << 48)
-
-struct btrfs_root_item {
-	struct btrfs_inode_item inode;
-	__u64 generation;
-	__u64 root_dirid;
-	__u64 bytenr;
-	__u64 byte_limit;
-	__u64 bytes_used;
-	__u64 last_snapshot;
-	__u64 flags;
-	__u32 refs;
-	struct btrfs_key drop_progress;
-	__u8 drop_level;
-	__u8 level;
-
-	/*
-	 * The following fields appear after subvol_uuids+subvol_times
-	 * were introduced.
-	 */
-
-	/*
-	 * This generation number is used to test if the new fields are valid
-	 * and up to date while reading the root item. Every time the root item
-	 * is written out, the "generation" field is copied into this field. If
-	 * anyone ever mounted the fs with an older kernel, we will have
-	 * mismatching generation values here and thus must invalidate the
-	 * new fields. See btrfs_update_root and btrfs_find_last_root for
-	 * details.
-	 * the offset of generation_v2 is also used as the start for the memset
-	 * when invalidating the fields.
-	 */
-	__u64 generation_v2;
-	__u8 uuid[BTRFS_UUID_SIZE];
-	__u8 parent_uuid[BTRFS_UUID_SIZE];
-	__u8 received_uuid[BTRFS_UUID_SIZE];
-	__u64 ctransid; /* updated when an inode changes */
-	__u64 otransid; /* trans when created */
-	__u64 stransid; /* trans when sent. non-zero for received subvol */
-	__u64 rtransid; /* trans when received. non-zero for received subvol */
-	struct btrfs_timespec ctime;
-	struct btrfs_timespec otime;
-	struct btrfs_timespec stime;
-	struct btrfs_timespec rtime;
-	__u64 reserved[8]; /* for future */
-} __attribute__ ((__packed__));
-
-/*
- * this is used for both forward and backward root refs
- */
-struct btrfs_root_ref {
-	__u64 dirid;
-	__u64 sequence;
-	__u16 name_len;
-} __attribute__ ((__packed__));
-
-#define BTRFS_FILE_EXTENT_INLINE 0
-#define BTRFS_FILE_EXTENT_REG 1
-#define BTRFS_FILE_EXTENT_PREALLOC 2
-
-enum btrfs_compression_type {
-	BTRFS_COMPRESS_NONE  = 0,
-	BTRFS_COMPRESS_ZLIB  = 1,
-	BTRFS_COMPRESS_LZO   = 2,
-	BTRFS_COMPRESS_ZSTD  = 3,
-	BTRFS_COMPRESS_TYPES = 3,
-	BTRFS_COMPRESS_LAST  = 4,
-};
-
-struct btrfs_file_extent_item {
-	/*
-	 * transaction id that created this extent
-	 */
-	__u64 generation;
-	/*
-	 * max number of bytes to hold this extent in ram
-	 * when we split a compressed extent we can't know how big
-	 * each of the resulting pieces will be.  So, this is
-	 * an upper limit on the size of the extent in ram instead of
-	 * an exact limit.
-	 */
-	__u64 ram_bytes;
-
-	/*
-	 * 32 bits for the various ways we might encode the data,
-	 * including compression and encryption.  If any of these
-	 * are set to something a given disk format doesn't understand
-	 * it is treated like an incompat flag for reading and writing,
-	 * but not for stat.
-	 */
-	__u8 compression;
-	__u8 encryption;
-	__u16 other_encoding; /* spare for later use */
-
-	/* are we inline data or a real extent? */
-	__u8 type;
-
-	/*
-	 * disk space consumed by the extent, checksum blocks are included
-	 * in these numbers
-	 *
-	 * At this offset in the structure, the inline extent data start.
-	 */
-	__u64 disk_bytenr;
-	__u64 disk_num_bytes;
-	/*
-	 * the logical offset in file blocks (no csums)
-	 * this extent record is for.  This allows a file extent to point
-	 * into the middle of an existing extent on disk, sharing it
-	 * between two snapshots (useful if some bytes in the middle of the
-	 * extent have changed
-	 */
-	__u64 offset;
-	/*
-	 * the logical number of file blocks (no csums included).  This
-	 * always reflects the size uncompressed and without encoding.
-	 */
-	__u64 num_bytes;
-
-} __attribute__ ((__packed__));
-
-struct btrfs_csum_item {
-	__u8 csum;
-} __attribute__ ((__packed__));
-
-/* different types of block groups (and chunks) */
-#define BTRFS_BLOCK_GROUP_DATA		(1ULL << 0)
-#define BTRFS_BLOCK_GROUP_SYSTEM	(1ULL << 1)
-#define BTRFS_BLOCK_GROUP_METADATA	(1ULL << 2)
-#define BTRFS_BLOCK_GROUP_RAID0		(1ULL << 3)
-#define BTRFS_BLOCK_GROUP_RAID1		(1ULL << 4)
-#define BTRFS_BLOCK_GROUP_DUP		(1ULL << 5)
-#define BTRFS_BLOCK_GROUP_RAID10	(1ULL << 6)
-#define BTRFS_BLOCK_GROUP_RAID5         (1ULL << 7)
-#define BTRFS_BLOCK_GROUP_RAID6         (1ULL << 8)
-#define BTRFS_BLOCK_GROUP_RESERVED	(BTRFS_AVAIL_ALLOC_BIT_SINGLE | \
-					 BTRFS_SPACE_INFO_GLOBAL_RSV)
-
-enum btrfs_raid_types {
-	BTRFS_RAID_RAID10,
-	BTRFS_RAID_RAID1,
-	BTRFS_RAID_DUP,
-	BTRFS_RAID_RAID0,
-	BTRFS_RAID_SINGLE,
-	BTRFS_RAID_RAID5,
-	BTRFS_RAID_RAID6,
-	BTRFS_NR_RAID_TYPES
-};
-
-#define BTRFS_BLOCK_GROUP_TYPE_MASK	(BTRFS_BLOCK_GROUP_DATA |    \
-					 BTRFS_BLOCK_GROUP_SYSTEM |  \
-					 BTRFS_BLOCK_GROUP_METADATA)
-
-#define BTRFS_BLOCK_GROUP_PROFILE_MASK	(BTRFS_BLOCK_GROUP_RAID0 |   \
-					 BTRFS_BLOCK_GROUP_RAID1 |   \
-					 BTRFS_BLOCK_GROUP_RAID5 |   \
-					 BTRFS_BLOCK_GROUP_RAID6 |   \
-					 BTRFS_BLOCK_GROUP_DUP |     \
-					 BTRFS_BLOCK_GROUP_RAID10)
-#define BTRFS_BLOCK_GROUP_RAID56_MASK	(BTRFS_BLOCK_GROUP_RAID5 |   \
-					 BTRFS_BLOCK_GROUP_RAID6)
-
-/*
- * We need a bit for restriper to be able to tell when chunks of type
- * SINGLE are available.  This "extended" profile format is used in
- * fs_info->avail_*_alloc_bits (in-memory) and balance item fields
- * (on-disk).  The corresponding on-disk bit in chunk.type is reserved
- * to avoid remappings between two formats in future.
- */
-#define BTRFS_AVAIL_ALLOC_BIT_SINGLE	(1ULL << 48)
-
-/*
- * A fake block group type that is used to communicate global block reserve
- * size to userspace via the SPACE_INFO ioctl.
- */
-#define BTRFS_SPACE_INFO_GLOBAL_RSV	(1ULL << 49)
-
-#define BTRFS_EXTENDED_PROFILE_MASK	(BTRFS_BLOCK_GROUP_PROFILE_MASK | \
-					 BTRFS_AVAIL_ALLOC_BIT_SINGLE)
-
-#endif /* __BTRFS_BTRFS_TREE_H__ */

diff --git a/fs/btrfs/chunk-map.c b/fs/btrfs/chunk-map.c
deleted file mode 100644
index 2e5be65..0000000
--- a/fs/btrfs/chunk-map.c
+++ /dev/null

@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * BTRFS filesystem implementation for U-Boot
- *
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
- */
-
-#include "btrfs.h"
-#include <log.h>
-#include <malloc.h>
-
-struct chunk_map_item {
-	struct rb_node node;
-	u64 logical;
-	u64 length;
-	u64 physical;
-};
-
-static int add_chunk_mapping(struct btrfs_key *key, struct btrfs_chunk *chunk)
-{
-	struct btrfs_stripe *stripe;
-	u64 block_profile = chunk->type & BTRFS_BLOCK_GROUP_PROFILE_MASK;
-	struct rb_node **new = &(btrfs_info.chunks_root.rb_node), *prnt = NULL;
-	struct chunk_map_item *map_item;
-
-	if (block_profile && block_profile != BTRFS_BLOCK_GROUP_DUP) {
-		printf("%s: unsupported chunk profile %llu\n", __func__,
-		       block_profile);
-		return -1;
-	} else if (!chunk->length) {
-		printf("%s: zero length chunk\n", __func__);
-		return -1;
-	}
-
-	stripe = &chunk->stripe;
-	btrfs_stripe_to_cpu(stripe);
-
-	while (*new) {
-		struct chunk_map_item *this;
-
-		this = rb_entry(*new, struct chunk_map_item, node);
-
-		prnt = *new;
-		if (key->offset < this->logical) {
-			new = &((*new)->rb_left);
-		} else if (key->offset > this->logical) {
-			new = &((*new)->rb_right);
-		} else {
-			debug("%s: Logical address %llu already in map!\n",
-			      __func__, key->offset);
-			return 0;
-		}
-	}
-
-	map_item = malloc(sizeof(struct chunk_map_item));
-	if (!map_item)
-		return -1;
-
-	map_item->logical = key->offset;
-	map_item->length = chunk->length;
-	map_item->physical = le64_to_cpu(chunk->stripe.offset);
-	rb_link_node(&map_item->node, prnt, new);
-	rb_insert_color(&map_item->node, &btrfs_info.chunks_root);
-
-	debug("%s: Mapping %llu to %llu\n", __func__, map_item->logical,
-	      map_item->physical);
-
-	return 0;
-}
-
-u64 btrfs_map_logical_to_physical(u64 logical)
-{
-	struct rb_node *node = btrfs_info.chunks_root.rb_node;
-
-	while (node) {
-		struct chunk_map_item *item;
-
-		item = rb_entry(node, struct chunk_map_item, node);
-
-		if (item->logical > logical)
-			node = node->rb_left;
-		else if (logical >= item->logical + item->length)
-			node = node->rb_right;
-		else
-			return item->physical + logical - item->logical;
-	}
-
-	printf("%s: Cannot map logical address %llu to physical\n", __func__,
-	       logical);
-
-	return -1ULL;
-}
-
-void btrfs_chunk_map_exit(void)
-{
-	struct rb_node *now, *next;
-	struct chunk_map_item *item;
-
-	for (now = rb_first_postorder(&btrfs_info.chunks_root); now; now = next)
-	{
-		item = rb_entry(now, struct chunk_map_item, node);
-		next = rb_next_postorder(now);
-		free(item);
-	}
-}
-
-int btrfs_chunk_map_init(void)
-{
-	u8 sys_chunk_array_copy[sizeof(btrfs_info.sb.sys_chunk_array)];
-	u8 * const start = sys_chunk_array_copy;
-	u8 * const end = start + btrfs_info.sb.sys_chunk_array_size;
-	u8 *cur;
-	struct btrfs_key *key;
-	struct btrfs_chunk *chunk;
-
-	btrfs_info.chunks_root = RB_ROOT;
-
-	memcpy(sys_chunk_array_copy, btrfs_info.sb.sys_chunk_array,
-	       sizeof(sys_chunk_array_copy));
-
-	for (cur = start; cur < end;) {
-		key = (struct btrfs_key *) cur;
-		cur += sizeof(struct btrfs_key);
-		chunk = (struct btrfs_chunk *) cur;
-
-		btrfs_key_to_cpu(key);
-		btrfs_chunk_to_cpu(chunk);
-
-		if (key->type != BTRFS_CHUNK_ITEM_KEY) {
-			printf("%s: invalid key type %u\n", __func__,
-			       key->type);
-			return -1;
-		}
-
-		if (add_chunk_mapping(key, chunk))
-			return -1;
-
-		cur += sizeof(struct btrfs_chunk);
-		cur += sizeof(struct btrfs_stripe) * (chunk->num_stripes - 1);
-	}
-
-	return 0;
-}
-
-int btrfs_read_chunk_tree(void)
-{
-	struct btrfs_path path;
-	struct btrfs_key key, *found_key;
-	struct btrfs_chunk *chunk;
-	int res = 0;
-
-	key.objectid = BTRFS_FIRST_CHUNK_TREE_OBJECTID;
-	key.type = BTRFS_CHUNK_ITEM_KEY;
-	key.offset = 0;
-
-	if (btrfs_search_tree(&btrfs_info.chunk_root, &key, &path))
-		return -1;
-
-	do {
-		found_key = btrfs_path_leaf_key(&path);
-		if (btrfs_comp_keys_type(&key, found_key))
-			continue;
-
-		chunk = btrfs_path_item_ptr(&path, struct btrfs_chunk);
-		btrfs_chunk_to_cpu(chunk);
-		if (add_chunk_mapping(found_key, chunk)) {
-			res = -1;
-			break;
-		}
-	} while (!(res = btrfs_next_slot(&path)));
-
-	btrfs_free_path(&path);
-
-	if (res < 0)
-		return -1;
-
-	return 0;
-}

diff --git a/fs/btrfs/common/rbtree-utils.c b/fs/btrfs/common/rbtree-utils.c
new file mode 100644
index 0000000..7a7d7e8
--- /dev/null
+++ b/fs/btrfs/common/rbtree-utils.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2014 Facebook.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public
+ * License v2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the
+ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * Boston, MA 021110-1307, USA.
+ */
+
+#include <linux/errno.h>
+#include "rbtree-utils.h"
+
+int rb_insert(struct rb_root *root, struct rb_node *node,
+	      rb_compare_nodes comp)
+{
+	struct rb_node **p = &root->rb_node;
+	struct rb_node *parent = NULL;
+	int ret;
+
+	while(*p) {
+		parent = *p;
+
+		ret = comp(parent, node);
+		if (ret < 0)
+			p = &(*p)->rb_left;
+		else if (ret > 0)
+			p = &(*p)->rb_right;
+		else
+			return -EEXIST;
+	}
+
+	rb_link_node(node, parent, p);
+	rb_insert_color(node, root);
+	return 0;
+}
+
+struct rb_node *rb_search(struct rb_root *root, void *key, rb_compare_keys comp,
+			  struct rb_node **next_ret)
+{
+	struct rb_node *n = root->rb_node;
+	struct rb_node *parent = NULL;
+	int ret = 0;
+
+	while(n) {
+		parent = n;
+
+		ret = comp(n, key);
+		if (ret < 0)
+			n = n->rb_left;
+		else if (ret > 0)
+			n = n->rb_right;
+		else
+			return n;
+	}
+
+	if (!next_ret)
+		return NULL;
+
+	if (parent && ret > 0)
+		parent = rb_next(parent);
+
+	*next_ret = parent;
+	return NULL;
+}
+
+void rb_free_nodes(struct rb_root *root, rb_free_node free_node)
+{
+	struct rb_node *node;
+
+	while ((node = rb_first(root))) {
+		rb_erase(node, root);
+		free_node(node);
+	}
+}

diff --git a/fs/btrfs/common/rbtree-utils.h b/fs/btrfs/common/rbtree-utils.h
new file mode 100644
index 0000000..d977cfd
--- /dev/null
+++ b/fs/btrfs/common/rbtree-utils.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014 Facebook.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public
+ * License v2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the
+ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * Boston, MA 021110-1307, USA.
+ */
+
+#ifndef __RBTREE_UTILS__
+#define __RBTREE_UTILS__
+
+#include <linux/rbtree.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The common insert/search/free functions */
+typedef int (*rb_compare_nodes)(struct rb_node *node1, struct rb_node *node2);
+typedef int (*rb_compare_keys)(struct rb_node *node, void *key);
+typedef void (*rb_free_node)(struct rb_node *node);
+
+int rb_insert(struct rb_root *root, struct rb_node *node,
+	      rb_compare_nodes comp);
+/*
+ * In some cases, we need return the next node if we don't find the node we
+ * specify. At this time, we can use next_ret.
+ */
+struct rb_node *rb_search(struct rb_root *root, void *key, rb_compare_keys comp,
+			  struct rb_node **next_ret);
+void rb_free_nodes(struct rb_root *root, rb_free_node free_node);
+
+#define FREE_RB_BASED_TREE(name, free_func)		\
+static void free_##name##_tree(struct rb_root *root)	\
+{							\
+	rb_free_nodes(root, free_func);			\
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h
new file mode 100644
index 0000000..9cf8a10
--- /dev/null
+++ b/fs/btrfs/compat.h

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#ifndef __BTRFS_COMPAT_H__
+#define __BTRFS_COMPAT_H__
+
+#include <linux/errno.h>
+#include <fs_internal.h>
+#include <uuid.h>
+
+/* Provide a compatibility layer to make code syncing easier */
+
+/* A simple wraper to for error() used in btrfs-progs */
+#define error(fmt, ...)		pr_err("BTRFS: " fmt "\n", ##__VA_ARGS__)
+
+#define ASSERT(c) assert(c)
+
+#define BTRFS_UUID_UNPARSED_SIZE	37
+
+/* No <linux/limits.h> so have to define it here */
+#define XATTR_NAME_MAX		255
+#define PATH_MAX		4096
+
+/*
+ * Macros to generate set/get funcs for the struct fields
+ * assume there is a lefoo_to_cpu for every type, so lets make a simple
+ * one for u8:
+ */
+#define le8_to_cpu(v) (v)
+#define cpu_to_le8(v) (v)
+#define __le8 u8
+
+/*
+ * Macros to generate set/get funcs for the struct fields
+ * assume there is a lefoo_to_cpu for every type, so lets make a simple
+ * one for u8:
+ */
+#define le8_to_cpu(v) (v)
+#define cpu_to_le8(v) (v)
+#define __le8 u8
+
+#define get_unaligned_le8(p) (*((u8 *)(p)))
+#define get_unaligned_8(p) (*((u8 *)(p)))
+#define put_unaligned_le8(val,p) ((*((u8 *)(p))) = (val))
+#define put_unaligned_8(val,p) ((*((u8 *)(p))) = (val))
+
+/*
+ * Read data from device specified by @desc and @part
+ *
+ * U-boot equivalent of pread().
+ *
+ * Return the bytes of data read.
+ * Return <0 for error.
+ */
+static inline int __btrfs_devread(struct blk_desc *desc,
+				  struct disk_partition *part,
+				  void *buf, size_t size, u64 offset)
+{
+	lbaint_t sector;
+	int byte_offset;
+	int ret;
+
+	sector = offset >> desc->log2blksz;
+	byte_offset = offset % desc->blksz;
+
+	/* fs_devread() return 0 for error, >0 for success */
+	ret = fs_devread(desc, part, sector, byte_offset, size, buf);
+	if (!ret)
+		return -EIO;
+	return size;
+}
+
+static inline void uuid_unparse(const u8 *uuid, char *out)
+{
+	return uuid_bin_to_str((unsigned char *)uuid, out, 0);
+}
+
+static inline int is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
+#endif

diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
index 59e4a94..23efefa 100644
--- a/fs/btrfs/compression.c
+++ b/fs/btrfs/compression.c

@@ -115,7 +115,7 @@
 	while (stream.total_in < clen) {
 		stream.next_in = cbuf + stream.total_in;
 		stream.avail_in = min((u32) (clen - stream.total_in),
-				      (u32) btrfs_info.sb.sectorsize);
+					current_fs_info->sectorsize);
 
 		ret = inflate(&stream, Z_NO_FLUSH);
 		if (ret != Z_OK)

diff --git a/fs/btrfs/crypto/hash.c b/fs/btrfs/crypto/hash.c
new file mode 100644
index 0000000..fb51f63
--- /dev/null
+++ b/fs/btrfs/crypto/hash.c

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/xxhash.h>
+#include <linux/unaligned/access_ok.h>
+#include <linux/types.h>
+#include <u-boot/sha256.h>
+#include <u-boot/crc.h>
+
+static u32 btrfs_crc32c_table[256];
+
+void btrfs_hash_init(void)
+{
+	static int inited = 0;
+
+	if (!inited) {
+		crc32c_init(btrfs_crc32c_table, 0x82F63B78);
+		inited = 1;
+	}
+}
+
+int hash_sha256(const u8 *buf, size_t length, u8 *out)
+{
+	sha256_context ctx;
+
+	sha256_starts(&ctx);
+	sha256_update(&ctx, buf, length);
+	sha256_finish(&ctx, out);
+
+	return 0;
+}
+
+int hash_xxhash(const u8 *buf, size_t length, u8 *out)
+{
+	u64 hash;
+
+	hash = xxh64(buf, length, 0);
+	put_unaligned_le64(hash, out);
+
+	return 0;
+}
+
+int hash_crc32c(const u8 *buf, size_t length, u8 *out)
+{
+	u32 crc;
+
+	crc = crc32c_cal((u32)~0, (char *)buf, length, btrfs_crc32c_table);
+	put_unaligned_le32(~crc, out);
+
+	return 0;
+}
+
+u32 crc32c(u32 seed, const void * data, size_t len)
+{
+	return crc32c_cal(seed, data, len, btrfs_crc32c_table);
+}

diff --git a/fs/btrfs/crypto/hash.h b/fs/btrfs/crypto/hash.h
new file mode 100644
index 0000000..d1ba1fa
--- /dev/null
+++ b/fs/btrfs/crypto/hash.h

@@ -0,0 +1,17 @@
+#ifndef CRYPTO_HASH_H
+#define CRYPTO_HASH_H
+
+#include <linux/types.h>
+
+#define CRYPTO_HASH_SIZE_MAX	32
+
+void btrfs_hash_init(void);
+int hash_crc32c(const u8 *buf, size_t length, u8 *out);
+int hash_xxhash(const u8 *buf, size_t length, u8 *out);
+int hash_sha256(const u8 *buf, size_t length, u8 *out);
+
+u32 crc32c(u32 seed, const void * data, size_t len);
+
+/* Blake2B is not yet supported due to lack of library */
+
+#endif

diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c
index 28f98d4..5ffced9 100644
--- a/fs/btrfs/ctree.c
+++ b/fs/btrfs/ctree.c

@@ -5,287 +5,738 @@
  * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
  */
 
-#include "btrfs.h"
+#include <linux/kernel.h>
 #include <log.h>
 #include <malloc.h>
 #include <memalign.h>
+#include "btrfs.h"
+#include "disk-io.h"
+
+static const struct btrfs_csum {
+	u16 size;
+	const char name[14];
+} btrfs_csums[] = {
+	[BTRFS_CSUM_TYPE_CRC32]		= {  4, "crc32c" },
+	[BTRFS_CSUM_TYPE_XXHASH]	= {  8, "xxhash64" },
+	[BTRFS_CSUM_TYPE_SHA256]	= { 32, "sha256" },
+	[BTRFS_CSUM_TYPE_BLAKE2]	= { 32, "blake2" },
+};
+
+u16 btrfs_super_csum_size(const struct btrfs_super_block *sb)
+{
+	const u16 csum_type = btrfs_super_csum_type(sb);
+
+	return btrfs_csums[csum_type].size;
+}
+
+const char *btrfs_super_csum_name(u16 csum_type)
+{
+	return btrfs_csums[csum_type].name;
+}
+
+size_t btrfs_super_num_csums(void)
+{
+	return ARRAY_SIZE(btrfs_csums);
+}
+
+u16 btrfs_csum_type_size(u16 csum_type)
+{
+	return btrfs_csums[csum_type].size;
+}
+
+struct btrfs_path *btrfs_alloc_path(void)
+{
+	struct btrfs_path *path;
+	path = kzalloc(sizeof(struct btrfs_path), GFP_NOFS);
+	return path;
+}
 
-int btrfs_comp_keys(struct btrfs_key *a, struct btrfs_key *b)
+void btrfs_free_path(struct btrfs_path *p)
+{
+	if (!p)
+		return;
+	btrfs_release_path(p);
+	kfree(p);
+}
+
+void btrfs_release_path(struct btrfs_path *p)
+{
+	int i;
+	for (i = 0; i < BTRFS_MAX_LEVEL; i++) {
+		if (!p->nodes[i])
+			continue;
+		free_extent_buffer(p->nodes[i]);
+	}
+	memset(p, 0, sizeof(*p));
+}
+
+int btrfs_comp_cpu_keys(const struct btrfs_key *k1, const struct btrfs_key *k2)
 {
-	if (a->objectid > b->objectid)
+	if (k1->objectid > k2->objectid)
 		return 1;
-	if (a->objectid < b->objectid)
+	if (k1->objectid < k2->objectid)
 		return -1;
-	if (a->type > b->type)
+	if (k1->type > k2->type)
 		return 1;
-	if (a->type < b->type)
+	if (k1->type < k2->type)
 		return -1;
-	if (a->offset > b->offset)
+	if (k1->offset > k2->offset)
 		return 1;
-	if (a->offset < b->offset)
+	if (k1->offset < k2->offset)
 		return -1;
 	return 0;
 }
 
-int btrfs_comp_keys_type(struct btrfs_key *a, struct btrfs_key *b)
+static int btrfs_comp_keys(struct btrfs_disk_key *disk,
+			     const struct btrfs_key *k2)
 {
-	if (a->objectid > b->objectid)
-		return 1;
-	if (a->objectid < b->objectid)
-		return -1;
-	if (a->type > b->type)
-		return 1;
-	if (a->type < b->type)
-		return -1;
-	return 0;
+	struct btrfs_key k1;
+
+	btrfs_disk_key_to_cpu(&k1, disk);
+	return btrfs_comp_cpu_keys(&k1, k2);
 }
 
-static int generic_bin_search(void *addr, int item_size, struct btrfs_key *key,
+enum btrfs_tree_block_status
+btrfs_check_node(struct btrfs_fs_info *fs_info,
+		 struct btrfs_disk_key *parent_key, struct extent_buffer *buf)
+{
+	int i;
+	struct btrfs_key cpukey;
+	struct btrfs_disk_key key;
+	u32 nritems = btrfs_header_nritems(buf);
+	enum btrfs_tree_block_status ret = BTRFS_TREE_BLOCK_INVALID_NRITEMS;
+
+	if (nritems == 0 || nritems > BTRFS_NODEPTRS_PER_BLOCK(fs_info))
+		goto fail;
+
+	ret = BTRFS_TREE_BLOCK_INVALID_PARENT_KEY;
+	if (parent_key && parent_key->type) {
+		btrfs_node_key(buf, &key, 0);
+		if (memcmp(parent_key, &key, sizeof(key)))
+			goto fail;
+	}
+	ret = BTRFS_TREE_BLOCK_BAD_KEY_ORDER;
+	for (i = 0; nritems > 1 && i < nritems - 2; i++) {
+		btrfs_node_key(buf, &key, i);
+		btrfs_node_key_to_cpu(buf, &cpukey, i + 1);
+		if (btrfs_comp_keys(&key, &cpukey) >= 0)
+			goto fail;
+	}
+	return BTRFS_TREE_BLOCK_CLEAN;
+fail:
+	return ret;
+}
+
+enum btrfs_tree_block_status
+btrfs_check_leaf(struct btrfs_fs_info *fs_info,
+		 struct btrfs_disk_key *parent_key, struct extent_buffer *buf)
+{
+	int i;
+	struct btrfs_key cpukey;
+	struct btrfs_disk_key key;
+	u32 nritems = btrfs_header_nritems(buf);
+	enum btrfs_tree_block_status ret = BTRFS_TREE_BLOCK_INVALID_NRITEMS;
+
+	if (nritems * sizeof(struct btrfs_item) > buf->len)  {
+		fprintf(stderr, "invalid number of items %llu\n",
+			(unsigned long long)buf->start);
+		goto fail;
+	}
+
+	if (btrfs_header_level(buf) != 0) {
+		ret = BTRFS_TREE_BLOCK_INVALID_LEVEL;
+		fprintf(stderr, "leaf is not a leaf %llu\n",
+		       (unsigned long long)btrfs_header_bytenr(buf));
+		goto fail;
+	}
+	if (btrfs_leaf_free_space(buf) < 0) {
+		ret = BTRFS_TREE_BLOCK_INVALID_FREE_SPACE;
+		fprintf(stderr, "leaf free space incorrect %llu %d\n",
+			(unsigned long long)btrfs_header_bytenr(buf),
+			btrfs_leaf_free_space(buf));
+		goto fail;
+	}
+
+	if (nritems == 0)
+		return BTRFS_TREE_BLOCK_CLEAN;
+
+	btrfs_item_key(buf, &key, 0);
+	if (parent_key && parent_key->type &&
+	    memcmp(parent_key, &key, sizeof(key))) {
+		ret = BTRFS_TREE_BLOCK_INVALID_PARENT_KEY;
+		fprintf(stderr, "leaf parent key incorrect %llu\n",
+		       (unsigned long long)btrfs_header_bytenr(buf));
+		goto fail;
+	}
+	for (i = 0; nritems > 1 && i < nritems - 1; i++) {
+		btrfs_item_key(buf, &key, i);
+		btrfs_item_key_to_cpu(buf, &cpukey, i + 1);
+		if (btrfs_comp_keys(&key, &cpukey) >= 0) {
+			ret = BTRFS_TREE_BLOCK_BAD_KEY_ORDER;
+			fprintf(stderr, "bad key ordering %d %d\n", i, i+1);
+			goto fail;
+		}
+		if (btrfs_item_offset_nr(buf, i) !=
+			btrfs_item_end_nr(buf, i + 1)) {
+			ret = BTRFS_TREE_BLOCK_INVALID_OFFSETS;
+			fprintf(stderr, "incorrect offsets %u %u\n",
+				btrfs_item_offset_nr(buf, i),
+				btrfs_item_end_nr(buf, i + 1));
+			goto fail;
+		}
+		if (i == 0 && btrfs_item_end_nr(buf, i) !=
+		    BTRFS_LEAF_DATA_SIZE(fs_info)) {
+			ret = BTRFS_TREE_BLOCK_INVALID_OFFSETS;
+			fprintf(stderr, "bad item end %u wanted %u\n",
+				btrfs_item_end_nr(buf, i),
+				(unsigned)BTRFS_LEAF_DATA_SIZE(fs_info));
+			goto fail;
+		}
+	}
+
+	for (i = 0; i < nritems; i++) {
+		if (btrfs_item_end_nr(buf, i) >
+				BTRFS_LEAF_DATA_SIZE(fs_info)) {
+			btrfs_item_key(buf, &key, 0);
+			ret = BTRFS_TREE_BLOCK_INVALID_OFFSETS;
+			fprintf(stderr, "slot end outside of leaf %llu > %llu\n",
+				(unsigned long long)btrfs_item_end_nr(buf, i),
+				(unsigned long long)BTRFS_LEAF_DATA_SIZE(
+					fs_info));
+			goto fail;
+		}
+	}
+
+	return BTRFS_TREE_BLOCK_CLEAN;
+fail:
+	return ret;
+}
+
+static int noinline check_block(struct btrfs_fs_info *fs_info,
+				struct btrfs_path *path, int level)
+{
+	struct btrfs_disk_key key;
+	struct btrfs_disk_key *key_ptr = NULL;
+	struct extent_buffer *parent;
+	enum btrfs_tree_block_status ret;
+
+	if (path->nodes[level + 1]) {
+		parent = path->nodes[level + 1];
+		btrfs_node_key(parent, &key, path->slots[level + 1]);
+		key_ptr = &key;
+	}
+	if (level == 0)
+		ret = btrfs_check_leaf(fs_info, key_ptr, path->nodes[0]);
+	else
+		ret = btrfs_check_node(fs_info, key_ptr, path->nodes[level]);
+	if (ret == BTRFS_TREE_BLOCK_CLEAN)
+		return 0;
+	return -EIO;
+}
+
+/*
+ * search for key in the extent_buffer.  The items start at offset p,
+ * and they are item_size apart.  There are 'max' items in p.
+ *
+ * the slot in the array is returned via slot, and it points to
+ * the place where you would insert key if it is not found in
+ * the array.
+ *
+ * slot may point to max if the key is bigger than all of the keys
+ */
+static int generic_bin_search(struct extent_buffer *eb, unsigned long p,
+			      int item_size, const struct btrfs_key *key,
 			      int max, int *slot)
 {
-	int low = 0, high = max, mid, ret;
-	struct btrfs_key *tmp;
+	int low = 0;
+	int high = max;
+	int mid;
+	int ret;
+	unsigned long offset;
+	struct btrfs_disk_key *tmp;
 
-	while (low < high) {
+	while(low < high) {
 		mid = (low + high) / 2;
+		offset = p + mid * item_size;
 
-		tmp = (struct btrfs_key *) ((u8 *) addr + mid*item_size);
+		tmp = (struct btrfs_disk_key *)(eb->data + offset);
 		ret = btrfs_comp_keys(tmp, key);
 
-		if (ret < 0) {
+		if (ret < 0)
 			low = mid + 1;
-		} else if (ret > 0) {
+		else if (ret > 0)
 			high = mid;
-		} else {
+		else {
 			*slot = mid;
 			return 0;
 		}
 	}
-
 	*slot = low;
 	return 1;
 }
 
-int btrfs_bin_search(union btrfs_tree_node *p, struct btrfs_key *key,
+/*
+ * simple bin_search frontend that does the right thing for
+ * leaves vs nodes
+ */
+int btrfs_bin_search(struct extent_buffer *eb, const struct btrfs_key *key,
 		     int *slot)
 {
-	void *addr;
-	unsigned long size;
-
-	if (p->header.level) {
-		addr = p->node.ptrs;
-		size = sizeof(struct btrfs_key_ptr);
-	} else {
-		addr = p->leaf.items;
-		size = sizeof(struct btrfs_item);
-	}
-
-	return generic_bin_search(addr, size, key, p->header.nritems, slot);
+	if (btrfs_header_level(eb) == 0)
+		return generic_bin_search(eb,
+					  offsetof(struct btrfs_leaf, items),
+					  sizeof(struct btrfs_item),
+					  key, btrfs_header_nritems(eb),
+					  slot);
+	else
+		return generic_bin_search(eb,
+					  offsetof(struct btrfs_node, ptrs),
+					  sizeof(struct btrfs_key_ptr),
+					  key, btrfs_header_nritems(eb),
+					  slot);
 }
 
-static void clear_path(struct btrfs_path *p)
+struct extent_buffer *read_node_slot(struct btrfs_fs_info *fs_info,
+				   struct extent_buffer *parent, int slot)
 {
-	int i;
+	struct extent_buffer *ret;
+	int level = btrfs_header_level(parent);
 
-	for (i = 0; i < BTRFS_MAX_LEVEL; ++i) {
-		p->nodes[i] = NULL;
-		p->slots[i] = 0;
-	}
-}
+	if (slot < 0)
+		return NULL;
+	if (slot >= btrfs_header_nritems(parent))
+		return NULL;
 
-void btrfs_free_path(struct btrfs_path *p)
-{
-	int i;
+	if (level == 0)
+		return NULL;
 
-	for (i = 0; i < BTRFS_MAX_LEVEL; ++i) {
-		if (p->nodes[i])
-			free(p->nodes[i]);
-	}
+	ret = read_tree_block(fs_info, btrfs_node_blockptr(parent, slot),
+		       btrfs_node_ptr_generation(parent, slot));
+	if (!extent_buffer_uptodate(ret))
+		return ERR_PTR(-EIO);
 
-	clear_path(p);
+	if (btrfs_header_level(ret) != level - 1) {
+		error("child eb corrupted: parent bytenr=%llu item=%d parent level=%d child level=%d",
+		      btrfs_header_bytenr(parent), slot,
+		      btrfs_header_level(parent), btrfs_header_level(ret));
+		free_extent_buffer(ret);
+		return ERR_PTR(-EIO);
+	}
+	return ret;
 }
 
-static int read_tree_node(u64 physical, union btrfs_tree_node **buf)
+int btrfs_find_item(struct btrfs_root *fs_root, struct btrfs_path *found_path,
+		u64 iobjectid, u64 ioff, u8 key_type,
+		struct btrfs_key *found_key)
 {
-	ALLOC_CACHE_ALIGN_BUFFER(struct btrfs_header, hdr,
-				 sizeof(struct btrfs_header));
-	unsigned long size, offset = sizeof(*hdr);
-	union btrfs_tree_node *res;
-	u32 i;
+	int ret;
+	struct btrfs_key key;
+	struct extent_buffer *eb;
+	struct btrfs_path *path;
 
-	if (!btrfs_devread(physical, sizeof(*hdr), hdr))
-		return -1;
+	key.type = key_type;
+	key.objectid = iobjectid;
+	key.offset = ioff;
 
-	btrfs_header_to_cpu(hdr);
+	if (found_path == NULL) {
+		path = btrfs_alloc_path();
+		if (!path)
+			return -ENOMEM;
+	} else
+		path = found_path;
 
-	if (hdr->level)
-		size = sizeof(struct btrfs_node)
-		       + hdr->nritems * sizeof(struct btrfs_key_ptr);
-	else
-		size = btrfs_info.sb.nodesize;
+	ret = btrfs_search_slot(NULL, fs_root, &key, path, 0, 0);
+	if ((ret < 0) || (found_key == NULL))
+		goto out;
 
-	res = malloc_cache_aligned(size);
-	if (!res) {
-		debug("%s: malloc failed\n", __func__);
-		return -1;
+	eb = path->nodes[0];
+	if (ret && path->slots[0] >= btrfs_header_nritems(eb)) {
+		ret = btrfs_next_leaf(fs_root, path);
+		if (ret)
+			goto out;
+		eb = path->nodes[0];
 	}
 
-	if (!btrfs_devread(physical + offset, size - offset,
-			   ((u8 *) res) + offset)) {
-		free(res);
-		return -1;
+	btrfs_item_key_to_cpu(eb, found_key, path->slots[0]);
+	if (found_key->type != key.type ||
+			found_key->objectid != key.objectid) {
+		ret = 1;
+		goto out;
 	}
 
-	memcpy(&res->header, hdr, sizeof(*hdr));
-	if (hdr->level)
-		for (i = 0; i < hdr->nritems; ++i)
-			btrfs_key_ptr_to_cpu(&res->node.ptrs[i]);
-	else
-		for (i = 0; i < hdr->nritems; ++i)
-			btrfs_item_to_cpu(&res->leaf.items[i]);
-
-	*buf = res;
-
-	return 0;
+out:
+	if (path != found_path)
+		btrfs_free_path(path);
+	return ret;
 }
 
-int btrfs_search_tree(const struct btrfs_root *root, struct btrfs_key *key,
-		      struct btrfs_path *p)
+/*
+ * look for key in the tree.  path is filled in with nodes along the way
+ * if key is found, we return zero and you can find the item in the leaf
+ * level of the path (level 0)
+ *
+ * If the key isn't found, the path points to the slot where it should
+ * be inserted, and 1 is returned.  If there are other errors during the
+ * search a negative error number is returned.
+ *
+ * if ins_len > 0, nodes and leaves will be split as we walk down the
+ * tree.  if ins_len < 0, nodes will be merged as we walk down the tree (if
+ * possible)
+ *
+ * NOTE: This version has no COW ability, thus we expect trans == NULL,
+ * ins_len == 0 and cow == 0.
+ */
+int btrfs_search_slot(struct btrfs_trans_handle *trans,
+		struct btrfs_root *root, const struct btrfs_key *key,
+		struct btrfs_path *p, int ins_len, int cow)
 {
-	u8 lvl, prev_lvl;
-	int i, slot, ret;
-	u64 logical, physical;
-	union btrfs_tree_node *buf;
+	struct extent_buffer *b;
+	int slot;
+	int ret;
+	int level;
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	u8 lowest_level = 0;
 
-	clear_path(p);
+	assert(trans == NULL && ins_len == 0 && cow == 0);
+	lowest_level = p->lowest_level;
+	WARN_ON(lowest_level && ins_len > 0);
+	WARN_ON(p->nodes[0] != NULL);
 
-	logical = root->bytenr;
-
-	for (i = 0; i < BTRFS_MAX_LEVEL; ++i) {
-		physical = btrfs_map_logical_to_physical(logical);
-		if (physical == -1ULL)
-			goto err;
-
-		if (read_tree_node(physical, &buf))
-			goto err;
+	b = root->node;
+	extent_buffer_get(b);
+	while (b) {
+		level = btrfs_header_level(b);
+		/*
+		if (cow) {
+			int wret;
+			wret = btrfs_cow_block(trans, root, b,
+					       p->nodes[level + 1],
+					       p->slots[level + 1],
+					       &b);
+			if (wret) {
+				free_extent_buffer(b);
+				return wret;
+			}
+		}
+		*/
+		BUG_ON(!cow && ins_len);
+		if (level != btrfs_header_level(b))
+			WARN_ON(1);
+		level = btrfs_header_level(b);
+		p->nodes[level] = b;
+		ret = check_block(fs_info, p, level);
+		if (ret)
+			return -1;
+		ret = btrfs_bin_search(b, key, &slot);
+		if (level != 0) {
+			if (ret && slot > 0)
+				slot -= 1;
+			p->slots[level] = slot;
+			/*
+			if ((p->search_for_split || ins_len > 0) &&
+			    btrfs_header_nritems(b) >=
+			    BTRFS_NODEPTRS_PER_BLOCK(fs_info) - 3) {
+				int sret = split_node(trans, root, p, level);
+				BUG_ON(sret > 0);
+				if (sret)
+					return sret;
+				b = p->nodes[level];
+				slot = p->slots[level];
+			} else if (ins_len < 0) {
+				int sret = balance_level(trans, root, p,
+							 level);
+				if (sret)
+					return sret;
+				b = p->nodes[level];
+				if (!b) {
+					btrfs_release_path(p);
+					goto again;
+				}
+				slot = p->slots[level];
+				BUG_ON(btrfs_header_nritems(b) == 1);
+			}
+			*/
+			/* this is only true while dropping a snapshot */
+			if (level == lowest_level)
+				break;
 
-		lvl = buf->header.level;
-		if (i && prev_lvl != lvl + 1) {
-			printf("%s: invalid level in header at %llu\n",
-			       __func__, logical);
-			goto err;
+			b = read_node_slot(fs_info, b, slot);
+			if (!extent_buffer_uptodate(b))
+				return -EIO;
+		} else {
+			p->slots[level] = slot;
+			/*
+			if (ins_len > 0 &&
+			    ins_len > btrfs_leaf_free_space(b)) {
+				int sret = split_leaf(trans, root, key,
+						      p, ins_len, ret == 0);
+				BUG_ON(sret > 0);
+				if (sret)
+					return sret;
+			}
+			*/
+			return ret;
 		}
-		prev_lvl = lvl;
+	}
+	return 1;
+}
 
-		ret = btrfs_bin_search(buf, key, &slot);
-		if (ret < 0)
-			goto err;
-		if (ret && slot > 0 && lvl)
-			slot -= 1;
+/*
+ * Helper to use instead of search slot if no exact match is needed but
+ * instead the next or previous item should be returned.
+ * When find_higher is true, the next higher item is returned, the next lower
+ * otherwise.
+ * When return_any and find_higher are both true, and no higher item is found,
+ * return the next lower instead.
+ * When return_any is true and find_higher is false, and no lower item is found,
+ * return the next higher instead.
+ * It returns 0 if any item is found, 1 if none is found (tree empty), and
+ * < 0 on error
+ */
+int btrfs_search_slot_for_read(struct btrfs_root *root,
+			       const struct btrfs_key *key,
+			       struct btrfs_path *p, int find_higher,
+			       int return_any)
+{
+	int ret;
+	struct extent_buffer *leaf;
 
-		p->slots[lvl] = slot;
-		p->nodes[lvl] = buf;
+again:
+	ret = btrfs_search_slot(NULL, root, key, p, 0, 0);
+	if (ret <= 0)
+		 return ret;
+	/*
+	 * A return value of 1 means the path is at the position where the item
+	 * should be inserted. Normally this is the next bigger item, but in
+	 * case the previous item is the last in a leaf, path points to the
+	 * first free slot in the previous leaf, i.e. at an invalid item.
+	 */
+	leaf = p->nodes[0];
 
-		if (lvl) {
-			logical = buf->node.ptrs[slot].blockptr;
-		} else {
+	if (find_higher) {
+		if (p->slots[0] >= btrfs_header_nritems(leaf)) {
+			ret = btrfs_next_leaf(root, p);
+			if (ret <= 0)
+				return ret;
+			if (!return_any)
+				return 1;
 			/*
-			 * The path might be invalid if:
-			 *   cur leaf max < searched value < next leaf min
-			 *
-			 * Jump to the next valid element if it exists.
+			 * No higher item found, return the next lower instead
 			 */
-			if (slot >= buf->header.nritems)
-				if (btrfs_next_slot(p) < 0)
-					goto err;
-			break;
+			return_any = 0;
+			find_higher = 0;
+			btrfs_release_path(p);
+			goto again;
+		}
+	} else {
+		if (p->slots[0] == 0) {
+			ret = btrfs_prev_leaf(root, p);
+			if (ret < 0)
+				return ret;
+			if (!ret) {
+				leaf = p->nodes[0];
+				if (p->slots[0] == btrfs_header_nritems(leaf))
+					p->slots[0]--;
+				return 0;
+			}
+			if (!return_any)
+				return 1;
+			/*
+			 * No lower item found, return the next higher instead
+			 */
+			return_any = 0;
+			find_higher = 1;
+			btrfs_release_path(p);
+			goto again;
+		} else {
+			--p->slots[0];
 		}
 	}
-
 	return 0;
-err:
-	btrfs_free_path(p);
-	return -1;
 }
 
-static int jump_leaf(struct btrfs_path *path, int dir)
+/*
+ * how many bytes are required to store the items in a leaf.  start
+ * and nr indicate which items in the leaf to check.  This totals up the
+ * space used both by the item structs and the item data
+ */
+static int leaf_space_used(struct extent_buffer *l, int start, int nr)
 {
-	struct btrfs_path p;
-	u32 slot;
-	int level = 1, from_level, i;
-
-	dir = dir >= 0 ? 1 : -1;
+	int data_len;
+	int nritems = btrfs_header_nritems(l);
+	int end = min(nritems, start + nr) - 1;
 
-	p = *path;
+	if (!nr)
+		return 0;
+	data_len = btrfs_item_end_nr(l, start);
+	data_len = data_len - btrfs_item_offset_nr(l, end);
+	data_len += sizeof(struct btrfs_item) * nr;
+	WARN_ON(data_len < 0);
+	return data_len;
+}
 
-	while (level < BTRFS_MAX_LEVEL) {
-		if (!p.nodes[level])
-			return 1;
+/*
+ * The space between the end of the leaf items and
+ * the start of the leaf data.  IOW, how much room
+ * the leaf has left for both items and data
+ */
+int btrfs_leaf_free_space(struct extent_buffer *leaf)
+{
+	int nritems = btrfs_header_nritems(leaf);
+	u32 leaf_data_size;
+	int ret;
 
-		slot = p.slots[level];
-		if ((dir > 0 && slot + dir >= p.nodes[level]->header.nritems)
-		    || (dir < 0 && !slot))
-			level++;
-		else
-			break;
+	BUG_ON(leaf->fs_info && leaf->fs_info->nodesize != leaf->len);
+	leaf_data_size = __BTRFS_LEAF_DATA_SIZE(leaf->len);
+	ret = leaf_data_size - leaf_space_used(leaf, 0 ,nritems);
+	if (ret < 0) {
+		printk("leaf free space ret %d, leaf data size %u, used %d nritems %d\n",
+		       ret, leaf_data_size, leaf_space_used(leaf, 0, nritems),
+		       nritems);
 	}
-
-	if (level == BTRFS_MAX_LEVEL)
-		return 1;
-
-	p.slots[level] = slot + dir;
-	level--;
-	from_level = level;
+	return ret;
+}
 
-	while (level >= 0) {
-		u64 logical, physical;
+/*
+ * walk up the tree as far as required to find the previous leaf.
+ * returns 0 if it found something or 1 if there are no lesser leaves.
+ * returns < 0 on io errors.
+ */
+int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path)
+{
+	int slot;
+	int level = 1;
+	struct extent_buffer *c;
+	struct extent_buffer *next = NULL;
+	struct btrfs_fs_info *fs_info = root->fs_info;
 
-		slot = p.slots[level + 1];
-		logical = p.nodes[level + 1]->node.ptrs[slot].blockptr;
-		physical = btrfs_map_logical_to_physical(logical);
-		if (physical == -1ULL)
-			goto err;
+	while(level < BTRFS_MAX_LEVEL) {
+		if (!path->nodes[level])
+			return 1;
 
-		if (read_tree_node(physical, &p.nodes[level]))
-			goto err;
+		slot = path->slots[level];
+		c = path->nodes[level];
+		if (slot == 0) {
+			level++;
+			if (level == BTRFS_MAX_LEVEL)
+				return 1;
+			continue;
+		}
+		slot--;
 
-		if (dir > 0)
-			p.slots[level] = 0;
-		else
-			p.slots[level] = p.nodes[level]->header.nritems - 1;
+		next = read_node_slot(fs_info, c, slot);
+		if (!extent_buffer_uptodate(next)) {
+			if (IS_ERR(next))
+				return PTR_ERR(next);
+			return -EIO;
+		}
+		break;
+	}
+	path->slots[level] = slot;
+	while(1) {
 		level--;
+		c = path->nodes[level];
+		free_extent_buffer(c);
+		slot = btrfs_header_nritems(next);
+		if (slot != 0)
+			slot--;
+		path->nodes[level] = next;
+		path->slots[level] = slot;
+		if (!level)
+			break;
+		next = read_node_slot(fs_info, next, slot);
+		if (!extent_buffer_uptodate(next)) {
+			if (IS_ERR(next))
+				return PTR_ERR(next);
+			return -EIO;
+		}
 	}
-
-	/* Free rewritten nodes in path */
-	for (i = 0; i <= from_level; ++i)
-		free(path->nodes[i]);
-
-	*path = p;
 	return 0;
-
-err:
-	/* Free rewritten nodes in p */
-	for (i = level + 1; i <= from_level; ++i)
-		free(p.nodes[i]);
-	return -1;
 }
 
-int btrfs_prev_slot(struct btrfs_path *p)
+/*
+ * Walk up the tree as far as necessary to find the next sibling tree block.
+ * More generic version of btrfs_next_leaf(), as it could find sibling nodes
+ * if @path->lowest_level is not 0.
+ *
+ * returns 0 if it found something or 1 if there are no greater leaves.
+ * returns < 0 on io errors.
+ */
+int btrfs_next_sibling_tree_block(struct btrfs_fs_info *fs_info,
+				  struct btrfs_path *path)
 {
-	if (!p->slots[0])
-		return jump_leaf(p, -1);
+	int slot;
+	int level = path->lowest_level + 1;
+	struct extent_buffer *c;
+	struct extent_buffer *next = NULL;
+
+	BUG_ON(path->lowest_level + 1 >= BTRFS_MAX_LEVEL);
+	do {
+		if (!path->nodes[level])
+			return 1;
 
-	p->slots[0]--;
+		slot = path->slots[level] + 1;
+		c = path->nodes[level];
+		if (slot >= btrfs_header_nritems(c)) {
+			level++;
+			if (level == BTRFS_MAX_LEVEL)
+				return 1;
+			continue;
+		}
+
+		next = read_node_slot(fs_info, c, slot);
+		if (!extent_buffer_uptodate(next))
+			return -EIO;
+		break;
+	} while (level < BTRFS_MAX_LEVEL);
+	path->slots[level] = slot;
+	while(1) {
+		level--;
+		c = path->nodes[level];
+		free_extent_buffer(c);
+		path->nodes[level] = next;
+		path->slots[level] = 0;
+		if (level == path->lowest_level)
+			break;
+		next = read_node_slot(fs_info, next, 0);
+		if (!extent_buffer_uptodate(next))
+			return -EIO;
+	}
 	return 0;
 }
 
-int btrfs_next_slot(struct btrfs_path *p)
+int btrfs_previous_item(struct btrfs_root *root,
+			struct btrfs_path *path, u64 min_objectid,
+			int type)
 {
-	struct btrfs_leaf *leaf = &p->nodes[0]->leaf;
+	struct btrfs_key found_key;
+	struct extent_buffer *leaf;
+	u32 nritems;
+	int ret;
 
-	if (p->slots[0] + 1 >= leaf->header.nritems)
-		return jump_leaf(p, 1);
+	while(1) {
+		if (path->slots[0] == 0) {
+			ret = btrfs_prev_leaf(root, path);
+			if (ret != 0)
+				return ret;
+		} else {
+			path->slots[0]--;
+		}
+		leaf = path->nodes[0];
+		nritems = btrfs_header_nritems(leaf);
+		if (nritems == 0)
+			return 1;
+		if (path->slots[0] == nritems)
+			path->slots[0]--;
 
-	p->slots[0]++;
-	return 0;
+		btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
+		if (found_key.objectid < min_objectid)
+			break;
+		if (found_key.type == type)
+			return 0;
+		if (found_key.objectid == min_objectid &&
+		    found_key.type < type)
+			break;
+	}
+	return 1;
 }

diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 65c152a..219c410 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h

@@ -11,16 +11,17 @@
 
 #include <common.h>
 #include <compiler.h>
-#include "btrfs_tree.h"
-
-#define BTRFS_MAGIC 0x4D5F53665248425FULL /* ascii _BHRfS_M, no null */
+#include <linux/rbtree.h>
+#include <linux/bug.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <u-boot/crc.h>
+#include "kernel-shared/btrfs_tree.h"
+#include "crypto/hash.h"
+#include "compat.h"
+#include "extent-io.h"
 
 #define BTRFS_MAX_MIRRORS 3
 
-#define BTRFS_MAX_LEVEL 8
-
-#define BTRFS_COMPAT_EXTENT_TREE_V0
-
 /*
  * the max metadata block size.  This limit is somewhat artificial,
  * but the memmove costs go through the roof for larger blocks.
@@ -28,23 +29,38 @@
 #define BTRFS_MAX_METADATA_BLOCKSIZE 65536
 
 /*
- * we can actually store much bigger names, but lets not confuse the rest
- * of linux
- */
-#define BTRFS_NAME_LEN 255
-
-/*
  * Theoretical limit is larger, but we keep this down to a sane
  * value. That should limit greatly the possibility of collisions on
  * inode ref items.
  */
 #define BTRFS_LINK_MAX 65535U
 
-static const int btrfs_csum_sizes[] = { 4 };
-
 /* four bytes for CRC32 */
 #define BTRFS_EMPTY_DIR_SIZE 0
 
+struct btrfs_mapping_tree {
+	struct cache_tree cache_tree;
+};
+
+static inline unsigned long btrfs_chunk_item_size(int num_stripes)
+{
+	BUG_ON(num_stripes == 0);
+	return sizeof(struct btrfs_chunk) +
+		sizeof(struct btrfs_stripe) * (num_stripes - 1);
+}
+
+#define __BTRFS_LEAF_DATA_SIZE(bs) ((bs) - sizeof(struct btrfs_header))
+#define BTRFS_LEAF_DATA_SIZE(fs_info) \
+				(__BTRFS_LEAF_DATA_SIZE(fs_info->nodesize))
+
+struct btrfs_path {
+	struct extent_buffer *nodes[BTRFS_MAX_LEVEL];
+	int slots[BTRFS_MAX_LEVEL];
+
+	/* keep some upper locks as we walk down */
+	u8 lowest_level;
+};
+
 /* ioprio of readahead is set to idle */
 #define BTRFS_IOPRIO_READA (IOPRIO_PRIO_VALUE(IOPRIO_CLASS_IDLE, 0))
 
@@ -52,6 +68,92 @@
 
 #define BTRFS_MAX_EXTENT_SIZE SZ_128M
 
+enum btrfs_tree_block_status {
+	BTRFS_TREE_BLOCK_CLEAN,
+	BTRFS_TREE_BLOCK_INVALID_NRITEMS,
+	BTRFS_TREE_BLOCK_INVALID_PARENT_KEY,
+	BTRFS_TREE_BLOCK_BAD_KEY_ORDER,
+	BTRFS_TREE_BLOCK_INVALID_LEVEL,
+	BTRFS_TREE_BLOCK_INVALID_FREE_SPACE,
+	BTRFS_TREE_BLOCK_INVALID_OFFSETS,
+};
+
+struct btrfs_root {
+	struct extent_buffer *node;
+	struct btrfs_root_item root_item;
+	struct btrfs_key root_key;
+	struct btrfs_fs_info *fs_info;
+	u64 objectid;
+	u64 last_trans;
+
+	int ref_cows;
+	int track_dirty;
+
+	u32 type;
+	u64 last_inode_alloc;
+
+	struct rb_node rb_node;
+};
+
+struct btrfs_trans_handle;
+struct btrfs_device;
+struct btrfs_fs_devices;
+struct btrfs_fs_info {
+	u8 chunk_tree_uuid[BTRFS_UUID_SIZE];
+	u8 *new_chunk_tree_uuid;
+	struct btrfs_root *fs_root;
+	struct btrfs_root *tree_root;
+	struct btrfs_root *chunk_root;
+	struct btrfs_root *csum_root;
+
+	struct rb_root fs_root_tree;
+
+	struct extent_io_tree extent_cache;
+
+	/* logical->physical extent mapping */
+	struct btrfs_mapping_tree mapping_tree;
+
+	u64 last_trans_committed;
+
+	struct btrfs_super_block *super_copy;
+
+	struct btrfs_fs_devices *fs_devices;
+
+	/* Cached block sizes */
+	u32 nodesize;
+	u32 sectorsize;
+	u32 stripesize;
+};
+
+static inline u32 BTRFS_MAX_ITEM_SIZE(const struct btrfs_fs_info *info)
+{
+	return BTRFS_LEAF_DATA_SIZE(info) - sizeof(struct btrfs_item);
+}
+
+static inline u32 BTRFS_NODEPTRS_PER_BLOCK(const struct btrfs_fs_info *info)
+{
+	return BTRFS_LEAF_DATA_SIZE(info) / sizeof(struct btrfs_key_ptr);
+}
+
+static inline u32 BTRFS_NODEPTRS_PER_EXTENT_BUFFER(const struct extent_buffer *eb)
+{
+	BUG_ON(eb->fs_info && eb->fs_info->nodesize != eb->len);
+	return __BTRFS_LEAF_DATA_SIZE(eb->len) / sizeof(struct btrfs_key_ptr);
+}
+
+#define BTRFS_FILE_EXTENT_INLINE_DATA_START		\
+	(offsetof(struct btrfs_file_extent_item, disk_bytenr))
+static inline u32 BTRFS_MAX_INLINE_DATA_SIZE(const struct btrfs_fs_info *info)
+{
+	return BTRFS_MAX_ITEM_SIZE(info) -
+		BTRFS_FILE_EXTENT_INLINE_DATA_START;
+}
+
+static inline u32 BTRFS_MAX_XATTR_SIZE(const struct btrfs_fs_info *info)
+{
+	return BTRFS_MAX_ITEM_SIZE(info) - sizeof(struct btrfs_dir_item);
+}
+
 /*
  * File system states
  */
@@ -61,273 +163,1136 @@
 #define BTRFS_FS_STATE_DEV_REPLACING	3
 #define BTRFS_FS_STATE_DUMMY_FS_INFO	4
 
-#define BTRFS_BACKREF_REV_MAX		256
-#define BTRFS_BACKREF_REV_SHIFT		56
-#define BTRFS_BACKREF_REV_MASK		(((u64)BTRFS_BACKREF_REV_MAX - 1) << \
-					 BTRFS_BACKREF_REV_SHIFT)
+#define read_eb_member(eb, ptr, type, member, result) (			\
+	read_extent_buffer(eb, (char *)(result),			\
+			   ((unsigned long)(ptr)) +			\
+			    offsetof(type, member),			\
+			   sizeof(((type *)0)->member)))
 
-#define BTRFS_OLD_BACKREF_REV		0
-#define BTRFS_MIXED_BACKREF_REV		1
+#define write_eb_member(eb, ptr, type, member, result) (		\
+	write_extent_buffer(eb, (char *)(result),			\
+			   ((unsigned long)(ptr)) +			\
+			    offsetof(type, member),			\
+			   sizeof(((type *)0)->member)))
 
-/*
- * every tree block (leaf or node) starts with this header.
- */
-struct btrfs_header {
-	/* these first four must match the super block */
-	__u8 csum[BTRFS_CSUM_SIZE];
-	__u8 fsid[BTRFS_FSID_SIZE]; /* FS specific uuid */
-	__u64 bytenr; /* which block this node is supposed to live in */
-	__u64 flags;
+#define BTRFS_SETGET_HEADER_FUNCS(name, type, member, bits)		\
+static inline u##bits btrfs_##name(const struct extent_buffer *eb)	\
+{									\
+	const struct btrfs_header *h = (struct btrfs_header *)eb->data;	\
+	return le##bits##_to_cpu(h->member);				\
+}									\
+static inline void btrfs_set_##name(struct extent_buffer *eb,		\
+				    u##bits val)			\
+{									\
+	struct btrfs_header *h = (struct btrfs_header *)eb->data;	\
+	h->member = cpu_to_le##bits(val);				\
+}
 
-	/* allowed to be different from the super from here on down */
-	__u8 chunk_tree_uuid[BTRFS_UUID_SIZE];
-	__u64 generation;
-	__u64 owner;
-	__u32 nritems;
-	__u8 level;
-} __attribute__ ((__packed__));
+#define BTRFS_SETGET_FUNCS(name, type, member, bits)			\
+static inline u##bits btrfs_##name(const struct extent_buffer *eb,	\
+				   const type *s)			\
+{									\
+	unsigned long offset = (unsigned long)s;			\
+	const type *p = (type *) (eb->data + offset);			\
+	return get_unaligned_le##bits(&p->member);			\
+}									\
+static inline void btrfs_set_##name(struct extent_buffer *eb,		\
+				    type *s, u##bits val)		\
+{									\
+	unsigned long offset = (unsigned long)s;			\
+	type *p = (type *) (eb->data + offset);				\
+	put_unaligned_le##bits(val, &p->member);			\
+}
 
-/*
- * this is a very generous portion of the super block, giving us
- * room to translate 14 chunks with 3 stripes each.
- */
-#define BTRFS_SYSTEM_CHUNK_ARRAY_SIZE 2048
+#define BTRFS_SETGET_STACK_FUNCS(name, type, member, bits)		\
+static inline u##bits btrfs_##name(const type *s)			\
+{									\
+	return le##bits##_to_cpu(s->member);				\
+}									\
+static inline void btrfs_set_##name(type *s, u##bits val)		\
+{									\
+	s->member = cpu_to_le##bits(val);				\
+}
 
-/*
- * just in case we somehow lose the roots and are not able to mount,
- * we store an array of the roots from previous transactions
- * in the super.
- */
-#define BTRFS_NUM_BACKUP_ROOTS 4
-struct btrfs_root_backup {
-	__u64 tree_root;
-	__u64 tree_root_gen;
+BTRFS_SETGET_FUNCS(device_type, struct btrfs_dev_item, type, 64);
+BTRFS_SETGET_FUNCS(device_total_bytes, struct btrfs_dev_item, total_bytes, 64);
+BTRFS_SETGET_FUNCS(device_bytes_used, struct btrfs_dev_item, bytes_used, 64);
+BTRFS_SETGET_FUNCS(device_io_align, struct btrfs_dev_item, io_align, 32);
+BTRFS_SETGET_FUNCS(device_io_width, struct btrfs_dev_item, io_width, 32);
+BTRFS_SETGET_FUNCS(device_start_offset, struct btrfs_dev_item,
+		   start_offset, 64);
+BTRFS_SETGET_FUNCS(device_sector_size, struct btrfs_dev_item, sector_size, 32);
+BTRFS_SETGET_FUNCS(device_id, struct btrfs_dev_item, devid, 64);
+BTRFS_SETGET_FUNCS(device_group, struct btrfs_dev_item, dev_group, 32);
+BTRFS_SETGET_FUNCS(device_seek_speed, struct btrfs_dev_item, seek_speed, 8);
+BTRFS_SETGET_FUNCS(device_bandwidth, struct btrfs_dev_item, bandwidth, 8);
+BTRFS_SETGET_FUNCS(device_generation, struct btrfs_dev_item, generation, 64);
 
-	__u64 chunk_root;
-	__u64 chunk_root_gen;
+BTRFS_SETGET_STACK_FUNCS(stack_device_type, struct btrfs_dev_item, type, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_device_total_bytes, struct btrfs_dev_item,
+			 total_bytes, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_device_bytes_used, struct btrfs_dev_item,
+			 bytes_used, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_device_io_align, struct btrfs_dev_item,
+			 io_align, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_device_io_width, struct btrfs_dev_item,
+			 io_width, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_device_sector_size, struct btrfs_dev_item,
+			 sector_size, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_device_id, struct btrfs_dev_item, devid, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_device_group, struct btrfs_dev_item,
+			 dev_group, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_device_seek_speed, struct btrfs_dev_item,
+			 seek_speed, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_device_bandwidth, struct btrfs_dev_item,
+			 bandwidth, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_device_generation, struct btrfs_dev_item,
+			 generation, 64);
 
-	__u64 extent_root;
-	__u64 extent_root_gen;
+static inline char *btrfs_device_uuid(struct btrfs_dev_item *d)
+{
+	return (char *)d + offsetof(struct btrfs_dev_item, uuid);
+}
 
-	__u64 fs_root;
-	__u64 fs_root_gen;
+static inline char *btrfs_device_fsid(struct btrfs_dev_item *d)
+{
+	return (char *)d + offsetof(struct btrfs_dev_item, fsid);
+}
 
-	__u64 dev_root;
-	__u64 dev_root_gen;
+BTRFS_SETGET_FUNCS(chunk_length, struct btrfs_chunk, length, 64);
+BTRFS_SETGET_FUNCS(chunk_owner, struct btrfs_chunk, owner, 64);
+BTRFS_SETGET_FUNCS(chunk_stripe_len, struct btrfs_chunk, stripe_len, 64);
+BTRFS_SETGET_FUNCS(chunk_io_align, struct btrfs_chunk, io_align, 32);
+BTRFS_SETGET_FUNCS(chunk_io_width, struct btrfs_chunk, io_width, 32);
+BTRFS_SETGET_FUNCS(chunk_sector_size, struct btrfs_chunk, sector_size, 32);
+BTRFS_SETGET_FUNCS(chunk_type, struct btrfs_chunk, type, 64);
+BTRFS_SETGET_FUNCS(chunk_num_stripes, struct btrfs_chunk, num_stripes, 16);
+BTRFS_SETGET_FUNCS(chunk_sub_stripes, struct btrfs_chunk, sub_stripes, 16);
+BTRFS_SETGET_FUNCS(stripe_devid, struct btrfs_stripe, devid, 64);
+BTRFS_SETGET_FUNCS(stripe_offset, struct btrfs_stripe, offset, 64);
 
-	__u64 csum_root;
-	__u64 csum_root_gen;
+static inline char *btrfs_stripe_dev_uuid(struct btrfs_stripe *s)
+{
+	return (char *)s + offsetof(struct btrfs_stripe, dev_uuid);
+}
 
-	__u64 total_bytes;
-	__u64 bytes_used;
-	__u64 num_devices;
-	/* future */
-	__u64 unused_64[4];
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_length, struct btrfs_chunk, length, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_owner, struct btrfs_chunk, owner, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_stripe_len, struct btrfs_chunk,
+			 stripe_len, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_io_align, struct btrfs_chunk,
+			 io_align, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_io_width, struct btrfs_chunk,
+			 io_width, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_sector_size, struct btrfs_chunk,
+			 sector_size, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_type, struct btrfs_chunk, type, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_num_stripes, struct btrfs_chunk,
+			 num_stripes, 16);
+BTRFS_SETGET_STACK_FUNCS(stack_chunk_sub_stripes, struct btrfs_chunk,
+			 sub_stripes, 16);
+BTRFS_SETGET_STACK_FUNCS(stack_stripe_devid, struct btrfs_stripe, devid, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_stripe_offset, struct btrfs_stripe, offset, 64);
 
-	__u8 tree_root_level;
-	__u8 chunk_root_level;
-	__u8 extent_root_level;
-	__u8 fs_root_level;
-	__u8 dev_root_level;
-	__u8 csum_root_level;
-	/* future and to align */
-	__u8 unused_8[10];
-} __attribute__ ((__packed__));
+static inline struct btrfs_stripe *btrfs_stripe_nr(struct btrfs_chunk *c,
+						   int nr)
+{
+	unsigned long offset = (unsigned long)c;
+	offset += offsetof(struct btrfs_chunk, stripe);
+	offset += nr * sizeof(struct btrfs_stripe);
+	return (struct btrfs_stripe *)offset;
+}
 
-/*
- * the super block basically lists the main trees of the FS
- * it currently lacks any block count etc etc
- */
-struct btrfs_super_block {
-	__u8 csum[BTRFS_CSUM_SIZE];
-	/* the first 4 fields must match struct btrfs_header */
-	__u8 fsid[BTRFS_FSID_SIZE];    /* FS specific uuid */
-	__u64 bytenr; /* this block number */
-	__u64 flags;
+static inline char *btrfs_stripe_dev_uuid_nr(struct btrfs_chunk *c, int nr)
+{
+	return btrfs_stripe_dev_uuid(btrfs_stripe_nr(c, nr));
+}
+
+static inline u64 btrfs_stripe_offset_nr(struct extent_buffer *eb,
+					 struct btrfs_chunk *c, int nr)
+{
+	return btrfs_stripe_offset(eb, btrfs_stripe_nr(c, nr));
+}
+
+static inline void btrfs_set_stripe_offset_nr(struct extent_buffer *eb,
+					     struct btrfs_chunk *c, int nr,
+					     u64 val)
+{
+	btrfs_set_stripe_offset(eb, btrfs_stripe_nr(c, nr), val);
+}
+
+static inline u64 btrfs_stripe_devid_nr(struct extent_buffer *eb,
+					 struct btrfs_chunk *c, int nr)
+{
+	return btrfs_stripe_devid(eb, btrfs_stripe_nr(c, nr));
+}
 
-	/* allowed to be different from the btrfs_header from here own down */
-	__u64 magic;
-	__u64 generation;
-	__u64 root;
-	__u64 chunk_root;
-	__u64 log_root;
+static inline void btrfs_set_stripe_devid_nr(struct extent_buffer *eb,
+					     struct btrfs_chunk *c, int nr,
+					     u64 val)
+{
+	btrfs_set_stripe_devid(eb, btrfs_stripe_nr(c, nr), val);
+}
 
-	/* this will help find the new super based on the log root */
-	__u64 log_root_transid;
-	__u64 total_bytes;
-	__u64 bytes_used;
-	__u64 root_dir_objectid;
-	__u64 num_devices;
-	__u32 sectorsize;
-	__u32 nodesize;
-	__u32 __unused_leafsize;
-	__u32 stripesize;
-	__u32 sys_chunk_array_size;
-	__u64 chunk_root_generation;
-	__u64 compat_flags;
-	__u64 compat_ro_flags;
-	__u64 incompat_flags;
-	__u16 csum_type;
-	__u8 root_level;
-	__u8 chunk_root_level;
-	__u8 log_root_level;
-	struct btrfs_dev_item dev_item;
+/* struct btrfs_block_group_item */
+BTRFS_SETGET_STACK_FUNCS(block_group_used, struct btrfs_block_group_item,
+			 used, 64);
+BTRFS_SETGET_FUNCS(disk_block_group_used, struct btrfs_block_group_item,
+			 used, 64);
+BTRFS_SETGET_STACK_FUNCS(block_group_chunk_objectid,
+			struct btrfs_block_group_item, chunk_objectid, 64);
 
-	char label[BTRFS_LABEL_SIZE];
+BTRFS_SETGET_FUNCS(disk_block_group_chunk_objectid,
+		   struct btrfs_block_group_item, chunk_objectid, 64);
+BTRFS_SETGET_FUNCS(disk_block_group_flags,
+		   struct btrfs_block_group_item, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(block_group_flags,
+			struct btrfs_block_group_item, flags, 64);
 
-	__u64 cache_generation;
-	__u64 uuid_tree_generation;
+/* struct btrfs_free_space_info */
+BTRFS_SETGET_FUNCS(free_space_extent_count, struct btrfs_free_space_info,
+		   extent_count, 32);
+BTRFS_SETGET_FUNCS(free_space_flags, struct btrfs_free_space_info, flags, 32);
 
-	/* future expansion */
-	__u64 reserved[30];
-	__u8 sys_chunk_array[BTRFS_SYSTEM_CHUNK_ARRAY_SIZE];
-	struct btrfs_root_backup super_roots[BTRFS_NUM_BACKUP_ROOTS];
-} __attribute__ ((__packed__));
+/* struct btrfs_inode_ref */
+BTRFS_SETGET_FUNCS(inode_ref_name_len, struct btrfs_inode_ref, name_len, 16);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_ref_name_len, struct btrfs_inode_ref, name_len, 16);
+BTRFS_SETGET_FUNCS(inode_ref_index, struct btrfs_inode_ref, index, 64);
 
-/*
- * Compat flags that we support.  If any incompat flags are set other than the
- * ones specified below then we will fail to mount
- */
-#define BTRFS_FEATURE_COMPAT_SUPP		0ULL
-#define BTRFS_FEATURE_COMPAT_SAFE_SET		0ULL
-#define BTRFS_FEATURE_COMPAT_SAFE_CLEAR		0ULL
+/* struct btrfs_inode_extref */
+BTRFS_SETGET_FUNCS(inode_extref_parent, struct btrfs_inode_extref,
+		   parent_objectid, 64);
+BTRFS_SETGET_FUNCS(inode_extref_name_len, struct btrfs_inode_extref,
+		   name_len, 16);
+BTRFS_SETGET_FUNCS(inode_extref_index, struct btrfs_inode_extref, index, 64);
 
-#define BTRFS_FEATURE_COMPAT_RO_SUPP			\
-	(BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE |	\
-	 BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE_VALID)
+/* struct btrfs_inode_item */
+BTRFS_SETGET_FUNCS(inode_generation, struct btrfs_inode_item, generation, 64);
+BTRFS_SETGET_FUNCS(inode_sequence, struct btrfs_inode_item, sequence, 64);
+BTRFS_SETGET_FUNCS(inode_transid, struct btrfs_inode_item, transid, 64);
+BTRFS_SETGET_FUNCS(inode_size, struct btrfs_inode_item, size, 64);
+BTRFS_SETGET_FUNCS(inode_nbytes, struct btrfs_inode_item, nbytes, 64);
+BTRFS_SETGET_FUNCS(inode_block_group, struct btrfs_inode_item, block_group, 64);
+BTRFS_SETGET_FUNCS(inode_nlink, struct btrfs_inode_item, nlink, 32);
+BTRFS_SETGET_FUNCS(inode_uid, struct btrfs_inode_item, uid, 32);
+BTRFS_SETGET_FUNCS(inode_gid, struct btrfs_inode_item, gid, 32);
+BTRFS_SETGET_FUNCS(inode_mode, struct btrfs_inode_item, mode, 32);
+BTRFS_SETGET_FUNCS(inode_rdev, struct btrfs_inode_item, rdev, 64);
+BTRFS_SETGET_FUNCS(inode_flags, struct btrfs_inode_item, flags, 64);
 
-#define BTRFS_FEATURE_COMPAT_RO_SAFE_SET	0ULL
-#define BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR	0ULL
+BTRFS_SETGET_STACK_FUNCS(stack_inode_generation,
+			 struct btrfs_inode_item, generation, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_sequence,
+			 struct btrfs_inode_item, sequence, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_transid,
+			 struct btrfs_inode_item, transid, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_size,
+			 struct btrfs_inode_item, size, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_nbytes,
+			 struct btrfs_inode_item, nbytes, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_block_group,
+			 struct btrfs_inode_item, block_group, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_nlink,
+			 struct btrfs_inode_item, nlink, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_uid,
+			 struct btrfs_inode_item, uid, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_gid,
+			 struct btrfs_inode_item, gid, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_mode,
+			 struct btrfs_inode_item, mode, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_rdev,
+			 struct btrfs_inode_item, rdev, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_inode_flags,
+			 struct btrfs_inode_item, flags, 64);
 
-#define BTRFS_FEATURE_INCOMPAT_SUPP			\
-	(BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF |		\
-	 BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL |	\
-	 BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS |		\
-	 BTRFS_FEATURE_INCOMPAT_BIG_METADATA |		\
-	 BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO |		\
-	 BTRFS_FEATURE_INCOMPAT_RAID56 |		\
-	 BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF |		\
-	 BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA |	\
-	 BTRFS_FEATURE_INCOMPAT_NO_HOLES)
+static inline struct btrfs_timespec *
+btrfs_inode_atime(struct btrfs_inode_item *inode_item)
+{
+	unsigned long ptr = (unsigned long)inode_item;
+	ptr += offsetof(struct btrfs_inode_item, atime);
+	return (struct btrfs_timespec *)ptr;
+}
 
-#define BTRFS_FEATURE_INCOMPAT_SAFE_SET			\
-	(BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF)
-#define BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR		0ULL
+static inline struct btrfs_timespec *
+btrfs_inode_mtime(struct btrfs_inode_item *inode_item)
+{
+	unsigned long ptr = (unsigned long)inode_item;
+	ptr += offsetof(struct btrfs_inode_item, mtime);
+	return (struct btrfs_timespec *)ptr;
+}
 
-/*
- * A leaf is full of items. offset and size tell us where to find
- * the item in the leaf (relative to the start of the data area)
- */
-struct btrfs_item {
-	struct btrfs_key key;
-	__u32 offset;
-	__u32 size;
-} __attribute__ ((__packed__));
+static inline struct btrfs_timespec *
+btrfs_inode_ctime(struct btrfs_inode_item *inode_item)
+{
+	unsigned long ptr = (unsigned long)inode_item;
+	ptr += offsetof(struct btrfs_inode_item, ctime);
+	return (struct btrfs_timespec *)ptr;
+}
 
-/*
- * leaves have an item area and a data area:
- * [item0, item1....itemN] [free space] [dataN...data1, data0]
- *
- * The data is separate from the items to get the keys closer together
- * during searches.
- */
-struct btrfs_leaf {
-	struct btrfs_header header;
-	struct btrfs_item items[];
-} __attribute__ ((__packed__));
+static inline struct btrfs_timespec *
+btrfs_inode_otime(struct btrfs_inode_item *inode_item)
+{
+	unsigned long ptr = (unsigned long)inode_item;
+	ptr += offsetof(struct btrfs_inode_item, otime);
+	return (struct btrfs_timespec *)ptr;
+}
+
+BTRFS_SETGET_FUNCS(timespec_sec, struct btrfs_timespec, sec, 64);
+BTRFS_SETGET_FUNCS(timespec_nsec, struct btrfs_timespec, nsec, 32);
+BTRFS_SETGET_STACK_FUNCS(stack_timespec_sec, struct btrfs_timespec,
+			 sec, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_timespec_nsec, struct btrfs_timespec,
+			 nsec, 32);
+
+/* struct btrfs_dev_extent */
+BTRFS_SETGET_FUNCS(dev_extent_chunk_tree, struct btrfs_dev_extent,
+		   chunk_tree, 64);
+BTRFS_SETGET_FUNCS(dev_extent_chunk_objectid, struct btrfs_dev_extent,
+		   chunk_objectid, 64);
+BTRFS_SETGET_FUNCS(dev_extent_chunk_offset, struct btrfs_dev_extent,
+		   chunk_offset, 64);
+BTRFS_SETGET_FUNCS(dev_extent_length, struct btrfs_dev_extent, length, 64);
+
+BTRFS_SETGET_STACK_FUNCS(stack_dev_extent_length, struct btrfs_dev_extent,
+			 length, 64);
+
+static inline u8 *btrfs_dev_extent_chunk_tree_uuid(struct btrfs_dev_extent *dev)
+{
+	unsigned long ptr = offsetof(struct btrfs_dev_extent, chunk_tree_uuid);
+	return (u8 *)((unsigned long)dev + ptr);
+}
+
+
+/* struct btrfs_extent_item */
+BTRFS_SETGET_FUNCS(extent_refs, struct btrfs_extent_item, refs, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_extent_refs, struct btrfs_extent_item, refs, 64);
+BTRFS_SETGET_FUNCS(extent_generation, struct btrfs_extent_item,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(extent_flags, struct btrfs_extent_item, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_extent_flags, struct btrfs_extent_item, flags, 64);
+
+BTRFS_SETGET_FUNCS(extent_refs_v0, struct btrfs_extent_item_v0, refs, 32);
+
+BTRFS_SETGET_FUNCS(tree_block_level, struct btrfs_tree_block_info, level, 8);
+
+static inline void btrfs_tree_block_key(struct extent_buffer *eb,
+					struct btrfs_tree_block_info *item,
+					struct btrfs_disk_key *key)
+{
+	read_eb_member(eb, item, struct btrfs_tree_block_info, key, key);
+}
+
+static inline void btrfs_set_tree_block_key(struct extent_buffer *eb,
+					    struct btrfs_tree_block_info *item,
+					    struct btrfs_disk_key *key)
+{
+	write_eb_member(eb, item, struct btrfs_tree_block_info, key, key);
+}
+
+BTRFS_SETGET_FUNCS(extent_data_ref_root, struct btrfs_extent_data_ref,
+		   root, 64);
+BTRFS_SETGET_FUNCS(extent_data_ref_objectid, struct btrfs_extent_data_ref,
+		   objectid, 64);
+BTRFS_SETGET_FUNCS(extent_data_ref_offset, struct btrfs_extent_data_ref,
+		   offset, 64);
+BTRFS_SETGET_FUNCS(extent_data_ref_count, struct btrfs_extent_data_ref,
+		   count, 32);
+
+BTRFS_SETGET_FUNCS(shared_data_ref_count, struct btrfs_shared_data_ref,
+		   count, 32);
+
+BTRFS_SETGET_FUNCS(extent_inline_ref_type, struct btrfs_extent_inline_ref,
+		   type, 8);
+BTRFS_SETGET_FUNCS(extent_inline_ref_offset, struct btrfs_extent_inline_ref,
+		   offset, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_extent_inline_ref_type,
+			 struct btrfs_extent_inline_ref, type, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_extent_inline_ref_offset,
+			 struct btrfs_extent_inline_ref, offset, 64);
+
+static inline u32 btrfs_extent_inline_ref_size(int type)
+{
+	if (type == BTRFS_TREE_BLOCK_REF_KEY ||
+	    type == BTRFS_SHARED_BLOCK_REF_KEY)
+		return sizeof(struct btrfs_extent_inline_ref);
+	if (type == BTRFS_SHARED_DATA_REF_KEY)
+		return sizeof(struct btrfs_shared_data_ref) +
+		       sizeof(struct btrfs_extent_inline_ref);
+	if (type == BTRFS_EXTENT_DATA_REF_KEY)
+		return sizeof(struct btrfs_extent_data_ref) +
+		       offsetof(struct btrfs_extent_inline_ref, offset);
+	BUG();
+	return 0;
+}
+
+BTRFS_SETGET_FUNCS(ref_root_v0, struct btrfs_extent_ref_v0, root, 64);
+BTRFS_SETGET_FUNCS(ref_generation_v0, struct btrfs_extent_ref_v0,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(ref_objectid_v0, struct btrfs_extent_ref_v0, objectid, 64);
+BTRFS_SETGET_FUNCS(ref_count_v0, struct btrfs_extent_ref_v0, count, 32);
+
+/* struct btrfs_node */
+BTRFS_SETGET_FUNCS(key_blockptr, struct btrfs_key_ptr, blockptr, 64);
+BTRFS_SETGET_FUNCS(key_generation, struct btrfs_key_ptr, generation, 64);
+
+static inline u64 btrfs_node_blockptr(struct extent_buffer *eb, int nr)
+{
+	unsigned long ptr;
+	ptr = offsetof(struct btrfs_node, ptrs) +
+		sizeof(struct btrfs_key_ptr) * nr;
+	return btrfs_key_blockptr(eb, (struct btrfs_key_ptr *)ptr);
+}
+
+static inline void btrfs_set_node_blockptr(struct extent_buffer *eb,
+					   int nr, u64 val)
+{
+	unsigned long ptr;
+	ptr = offsetof(struct btrfs_node, ptrs) +
+		sizeof(struct btrfs_key_ptr) * nr;
+	btrfs_set_key_blockptr(eb, (struct btrfs_key_ptr *)ptr, val);
+}
+
+static inline u64 btrfs_node_ptr_generation(struct extent_buffer *eb, int nr)
+{
+	unsigned long ptr;
+	ptr = offsetof(struct btrfs_node, ptrs) +
+		sizeof(struct btrfs_key_ptr) * nr;
+	return btrfs_key_generation(eb, (struct btrfs_key_ptr *)ptr);
+}
+
+static inline void btrfs_set_node_ptr_generation(struct extent_buffer *eb,
+						 int nr, u64 val)
+{
+	unsigned long ptr;
+	ptr = offsetof(struct btrfs_node, ptrs) +
+		sizeof(struct btrfs_key_ptr) * nr;
+	btrfs_set_key_generation(eb, (struct btrfs_key_ptr *)ptr, val);
+}
+
+static inline unsigned long btrfs_node_key_ptr_offset(int nr)
+{
+	return offsetof(struct btrfs_node, ptrs) +
+		sizeof(struct btrfs_key_ptr) * nr;
+}
+
+static inline void btrfs_node_key(struct extent_buffer *eb,
+				  struct btrfs_disk_key *disk_key, int nr)
+{
+	unsigned long ptr;
+	ptr = btrfs_node_key_ptr_offset(nr);
+	read_eb_member(eb, (struct btrfs_key_ptr *)ptr,
+		       struct btrfs_key_ptr, key, disk_key);
+}
+
+static inline void btrfs_set_node_key(struct extent_buffer *eb,
+				      struct btrfs_disk_key *disk_key, int nr)
+{
+	unsigned long ptr;
+	ptr = btrfs_node_key_ptr_offset(nr);
+	write_eb_member(eb, (struct btrfs_key_ptr *)ptr,
+		       struct btrfs_key_ptr, key, disk_key);
+}
+
+/* struct btrfs_item */
+BTRFS_SETGET_FUNCS(item_offset, struct btrfs_item, offset, 32);
+BTRFS_SETGET_FUNCS(item_size, struct btrfs_item, size, 32);
+
+static inline unsigned long btrfs_item_nr_offset(int nr)
+{
+	return offsetof(struct btrfs_leaf, items) +
+		sizeof(struct btrfs_item) * nr;
+}
+
+static inline struct btrfs_item *btrfs_item_nr(int nr)
+{
+	return (struct btrfs_item *)btrfs_item_nr_offset(nr);
+}
+
+static inline u32 btrfs_item_end(struct extent_buffer *eb,
+				 struct btrfs_item *item)
+{
+	return btrfs_item_offset(eb, item) + btrfs_item_size(eb, item);
+}
+
+static inline u32 btrfs_item_end_nr(struct extent_buffer *eb, int nr)
+{
+	return btrfs_item_end(eb, btrfs_item_nr(nr));
+}
+
+static inline u32 btrfs_item_offset_nr(const struct extent_buffer *eb, int nr)
+{
+	return btrfs_item_offset(eb, btrfs_item_nr(nr));
+}
+
+static inline u32 btrfs_item_size_nr(struct extent_buffer *eb, int nr)
+{
+	return btrfs_item_size(eb, btrfs_item_nr(nr));
+}
+
+static inline void btrfs_item_key(struct extent_buffer *eb,
+			   struct btrfs_disk_key *disk_key, int nr)
+{
+	struct btrfs_item *item = btrfs_item_nr(nr);
+	read_eb_member(eb, item, struct btrfs_item, key, disk_key);
+}
+
+static inline void btrfs_set_item_key(struct extent_buffer *eb,
+			       struct btrfs_disk_key *disk_key, int nr)
+{
+	struct btrfs_item *item = btrfs_item_nr(nr);
+	write_eb_member(eb, item, struct btrfs_item, key, disk_key);
+}
+
+BTRFS_SETGET_FUNCS(dir_log_end, struct btrfs_dir_log_item, end, 64);
 
 /*
- * all non-leaf blocks are nodes, they hold only keys and pointers to
- * other blocks
+ * struct btrfs_root_ref
  */
-struct btrfs_key_ptr {
-	struct btrfs_key key;
-	__u64 blockptr;
-	__u64 generation;
-} __attribute__ ((__packed__));
+BTRFS_SETGET_FUNCS(root_ref_dirid, struct btrfs_root_ref, dirid, 64);
+BTRFS_SETGET_FUNCS(root_ref_sequence, struct btrfs_root_ref, sequence, 64);
+BTRFS_SETGET_FUNCS(root_ref_name_len, struct btrfs_root_ref, name_len, 16);
 
-struct btrfs_node {
-	struct btrfs_header header;
-	struct btrfs_key_ptr ptrs[];
-} __attribute__ ((__packed__));
+BTRFS_SETGET_STACK_FUNCS(stack_root_ref_dirid, struct btrfs_root_ref, dirid, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_root_ref_sequence, struct btrfs_root_ref, sequence, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_root_ref_name_len, struct btrfs_root_ref, name_len, 16);
 
-union btrfs_tree_node {
-	struct btrfs_header header;
-	struct btrfs_leaf leaf;
-	struct btrfs_node node;
-};
+/* struct btrfs_dir_item */
+BTRFS_SETGET_FUNCS(dir_data_len, struct btrfs_dir_item, data_len, 16);
+BTRFS_SETGET_FUNCS(dir_type, struct btrfs_dir_item, type, 8);
+BTRFS_SETGET_FUNCS(dir_name_len, struct btrfs_dir_item, name_len, 16);
+BTRFS_SETGET_FUNCS(dir_transid, struct btrfs_dir_item, transid, 64);
 
-typedef __u8 u8;
-typedef __u16 u16;
-typedef __u32 u32;
-typedef __u64 u64;
+BTRFS_SETGET_STACK_FUNCS(stack_dir_data_len, struct btrfs_dir_item, data_len, 16);
+BTRFS_SETGET_STACK_FUNCS(stack_dir_type, struct btrfs_dir_item, type, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_dir_name_len, struct btrfs_dir_item, name_len, 16);
+BTRFS_SETGET_STACK_FUNCS(stack_dir_transid, struct btrfs_dir_item, transid, 64);
 
-struct btrfs_path {
-	union btrfs_tree_node *nodes[BTRFS_MAX_LEVEL];
-	u32 slots[BTRFS_MAX_LEVEL];
-};
+static inline void btrfs_dir_item_key(struct extent_buffer *eb,
+				      struct btrfs_dir_item *item,
+				      struct btrfs_disk_key *key)
+{
+	read_eb_member(eb, item, struct btrfs_dir_item, location, key);
+}
 
-struct btrfs_root {
-	u64 objectid;
-	u64 bytenr;
-	u64 root_dirid;
-};
+static inline void btrfs_set_dir_item_key(struct extent_buffer *eb,
+					  struct btrfs_dir_item *item,
+					  struct btrfs_disk_key *key)
+{
+	write_eb_member(eb, item, struct btrfs_dir_item, location, key);
+}
+
+/* struct btrfs_free_space_header */
+BTRFS_SETGET_FUNCS(free_space_entries, struct btrfs_free_space_header,
+		   num_entries, 64);
+BTRFS_SETGET_FUNCS(free_space_bitmaps, struct btrfs_free_space_header,
+		   num_bitmaps, 64);
+BTRFS_SETGET_FUNCS(free_space_generation, struct btrfs_free_space_header,
+		   generation, 64);
+
+static inline void btrfs_free_space_key(struct extent_buffer *eb,
+					struct btrfs_free_space_header *h,
+					struct btrfs_disk_key *key)
+{
+	read_eb_member(eb, h, struct btrfs_free_space_header, location, key);
+}
+
+static inline void btrfs_set_free_space_key(struct extent_buffer *eb,
+					    struct btrfs_free_space_header *h,
+					    struct btrfs_disk_key *key)
+{
+	write_eb_member(eb, h, struct btrfs_free_space_header, location, key);
+}
+
+/* struct btrfs_disk_key */
+BTRFS_SETGET_STACK_FUNCS(disk_key_objectid, struct btrfs_disk_key,
+			 objectid, 64);
+BTRFS_SETGET_STACK_FUNCS(disk_key_offset, struct btrfs_disk_key, offset, 64);
+BTRFS_SETGET_STACK_FUNCS(disk_key_type, struct btrfs_disk_key, type, 8);
+
+static inline void btrfs_disk_key_to_cpu(struct btrfs_key *cpu,
+					 struct btrfs_disk_key *disk)
+{
+	cpu->offset = le64_to_cpu(disk->offset);
+	cpu->type = disk->type;
+	cpu->objectid = le64_to_cpu(disk->objectid);
+}
 
-int btrfs_comp_keys(struct btrfs_key *, struct btrfs_key *);
-int btrfs_comp_keys_type(struct btrfs_key *, struct btrfs_key *);
-int btrfs_bin_search(union btrfs_tree_node *, struct btrfs_key *, int *);
-void btrfs_free_path(struct btrfs_path *);
-int btrfs_search_tree(const struct btrfs_root *, struct btrfs_key *,
-		      struct btrfs_path *);
-int btrfs_prev_slot(struct btrfs_path *);
-int btrfs_next_slot(struct btrfs_path *);
+static inline void btrfs_cpu_key_to_disk(struct btrfs_disk_key *disk,
+					 const struct btrfs_key *cpu)
+{
+	disk->offset = cpu_to_le64(cpu->offset);
+	disk->type = cpu->type;
+	disk->objectid = cpu_to_le64(cpu->objectid);
+}
+
+static inline void btrfs_node_key_to_cpu(struct extent_buffer *eb,
+				  struct btrfs_key *key, int nr)
+{
+	struct btrfs_disk_key disk_key;
+	btrfs_node_key(eb, &disk_key, nr);
+	btrfs_disk_key_to_cpu(key, &disk_key);
+}
 
-static inline struct btrfs_key *btrfs_path_leaf_key(struct btrfs_path *p) {
-	return &p->nodes[0]->leaf.items[p->slots[0]].key;
+static inline void btrfs_item_key_to_cpu(struct extent_buffer *eb,
+				  struct btrfs_key *key, int nr)
+{
+	struct btrfs_disk_key disk_key;
+	btrfs_item_key(eb, &disk_key, nr);
+	btrfs_disk_key_to_cpu(key, &disk_key);
 }
 
+static inline void btrfs_dir_item_key_to_cpu(struct extent_buffer *eb,
+				      struct btrfs_dir_item *item,
+				      struct btrfs_key *key)
+{
+	struct btrfs_disk_key disk_key;
+	btrfs_dir_item_key(eb, item, &disk_key);
+	btrfs_disk_key_to_cpu(key, &disk_key);
+}
+
+/* struct btrfs_header */
+BTRFS_SETGET_HEADER_FUNCS(header_bytenr, struct btrfs_header, bytenr, 64);
+BTRFS_SETGET_HEADER_FUNCS(header_generation, struct btrfs_header,
+			  generation, 64);
+BTRFS_SETGET_HEADER_FUNCS(header_owner, struct btrfs_header, owner, 64);
+BTRFS_SETGET_HEADER_FUNCS(header_nritems, struct btrfs_header, nritems, 32);
+BTRFS_SETGET_HEADER_FUNCS(header_flags, struct btrfs_header, flags, 64);
+BTRFS_SETGET_HEADER_FUNCS(header_level, struct btrfs_header, level, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_header_bytenr, struct btrfs_header, bytenr, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_header_nritems, struct btrfs_header, nritems,
+			 32);
+BTRFS_SETGET_STACK_FUNCS(stack_header_owner, struct btrfs_header, owner, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_header_generation, struct btrfs_header,
+			 generation, 64);
+
-static inline struct btrfs_key *
-btrfs_search_tree_key_type(const struct btrfs_root *root, u64 objectid,
-			   u8 type, struct btrfs_path *path)
+static inline int btrfs_header_flag(struct extent_buffer *eb, u64 flag)
 {
-	struct btrfs_key key, *res;
+	return (btrfs_header_flags(eb) & flag) == flag;
+}
 
-	key.objectid = objectid;
-	key.type = type;
-	key.offset = 0;
+static inline int btrfs_set_header_flag(struct extent_buffer *eb, u64 flag)
+{
+	u64 flags = btrfs_header_flags(eb);
+	btrfs_set_header_flags(eb, flags | flag);
+	return (flags & flag) == flag;
+}
 
-	if (btrfs_search_tree(root, &key, path))
-		return NULL;
+static inline int btrfs_clear_header_flag(struct extent_buffer *eb, u64 flag)
+{
+	u64 flags = btrfs_header_flags(eb);
+	btrfs_set_header_flags(eb, flags & ~flag);
+	return (flags & flag) == flag;
+}
 
-	res = btrfs_path_leaf_key(path);
-	if (btrfs_comp_keys_type(&key, res)) {
-		btrfs_free_path(path);
-		return NULL;
-	}
+static inline int btrfs_header_backref_rev(struct extent_buffer *eb)
+{
+	u64 flags = btrfs_header_flags(eb);
+	return flags >> BTRFS_BACKREF_REV_SHIFT;
+}
 
-	return res;
+static inline void btrfs_set_header_backref_rev(struct extent_buffer *eb,
+						int rev)
+{
+	u64 flags = btrfs_header_flags(eb);
+	flags &= ~BTRFS_BACKREF_REV_MASK;
+	flags |= (u64)rev << BTRFS_BACKREF_REV_SHIFT;
+	btrfs_set_header_flags(eb, flags);
 }
 
-static inline u32 btrfs_path_item_size(struct btrfs_path *p)
+static inline unsigned long btrfs_header_fsid(void)
 {
-	return p->nodes[0]->leaf.items[p->slots[0]].size;
+	return offsetof(struct btrfs_header, fsid);
 }
 
-static inline void *btrfs_leaf_data(struct btrfs_leaf *leaf, u32 slot)
+static inline unsigned long btrfs_header_chunk_tree_uuid(struct extent_buffer *eb)
 {
-	return ((u8 *) leaf) + sizeof(struct btrfs_header)
-	       + leaf->items[slot].offset;
+	return offsetof(struct btrfs_header, chunk_tree_uuid);
 }
 
-static inline void *btrfs_path_leaf_data(struct btrfs_path *p)
+static inline u8 *btrfs_header_csum(struct extent_buffer *eb)
 {
-	return btrfs_leaf_data(&p->nodes[0]->leaf, p->slots[0]);
+	unsigned long ptr = offsetof(struct btrfs_header, csum);
+	return (u8 *)ptr;
 }
 
+static inline int btrfs_is_leaf(struct extent_buffer *eb)
+{
+	return (btrfs_header_level(eb) == 0);
+}
+
+/* struct btrfs_root_item */
+BTRFS_SETGET_FUNCS(disk_root_generation, struct btrfs_root_item,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(disk_root_refs, struct btrfs_root_item, refs, 32);
+BTRFS_SETGET_FUNCS(disk_root_bytenr, struct btrfs_root_item, bytenr, 64);
+BTRFS_SETGET_FUNCS(disk_root_level, struct btrfs_root_item, level, 8);
+
+BTRFS_SETGET_STACK_FUNCS(root_generation, struct btrfs_root_item,
+			 generation, 64);
+BTRFS_SETGET_STACK_FUNCS(root_bytenr, struct btrfs_root_item, bytenr, 64);
+BTRFS_SETGET_STACK_FUNCS(root_level, struct btrfs_root_item, level, 8);
+BTRFS_SETGET_STACK_FUNCS(root_dirid, struct btrfs_root_item, root_dirid, 64);
+BTRFS_SETGET_STACK_FUNCS(root_refs, struct btrfs_root_item, refs, 32);
+BTRFS_SETGET_STACK_FUNCS(root_flags, struct btrfs_root_item, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(root_used, struct btrfs_root_item, bytes_used, 64);
+BTRFS_SETGET_STACK_FUNCS(root_limit, struct btrfs_root_item, byte_limit, 64);
+BTRFS_SETGET_STACK_FUNCS(root_last_snapshot, struct btrfs_root_item,
+			 last_snapshot, 64);
+BTRFS_SETGET_STACK_FUNCS(root_generation_v2, struct btrfs_root_item,
+			 generation_v2, 64);
+BTRFS_SETGET_STACK_FUNCS(root_ctransid, struct btrfs_root_item,
+			 ctransid, 64);
+BTRFS_SETGET_STACK_FUNCS(root_otransid, struct btrfs_root_item,
+			 otransid, 64);
+BTRFS_SETGET_STACK_FUNCS(root_stransid, struct btrfs_root_item,
+			 stransid, 64);
+BTRFS_SETGET_STACK_FUNCS(root_rtransid, struct btrfs_root_item,
+			 rtransid, 64);
+
+static inline struct btrfs_timespec* btrfs_root_ctime(
+		struct btrfs_root_item *root_item)
+{
+	unsigned long ptr = (unsigned long)root_item;
+	ptr += offsetof(struct btrfs_root_item, ctime);
+	return (struct btrfs_timespec *)ptr;
+}
+
+static inline struct btrfs_timespec* btrfs_root_otime(
+		struct btrfs_root_item *root_item)
+{
+	unsigned long ptr = (unsigned long)root_item;
+	ptr += offsetof(struct btrfs_root_item, otime);
+	return (struct btrfs_timespec *)ptr;
+}
+
+static inline struct btrfs_timespec* btrfs_root_stime(
+		struct btrfs_root_item *root_item)
+{
+	unsigned long ptr = (unsigned long)root_item;
+	ptr += offsetof(struct btrfs_root_item, stime);
+	return (struct btrfs_timespec *)ptr;
+}
+
+static inline struct btrfs_timespec* btrfs_root_rtime(
+		struct btrfs_root_item *root_item)
+{
+	unsigned long ptr = (unsigned long)root_item;
+	ptr += offsetof(struct btrfs_root_item, rtime);
+	return (struct btrfs_timespec *)ptr;
+}
+
+/* struct btrfs_root_backup */
+BTRFS_SETGET_STACK_FUNCS(backup_tree_root, struct btrfs_root_backup,
+		   tree_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_tree_root_gen, struct btrfs_root_backup,
+		   tree_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_tree_root_level, struct btrfs_root_backup,
+		   tree_root_level, 8);
+
+BTRFS_SETGET_STACK_FUNCS(backup_chunk_root, struct btrfs_root_backup,
+		   chunk_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_chunk_root_gen, struct btrfs_root_backup,
+		   chunk_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_chunk_root_level, struct btrfs_root_backup,
+		   chunk_root_level, 8);
+
+BTRFS_SETGET_STACK_FUNCS(backup_extent_root, struct btrfs_root_backup,
+		   extent_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_extent_root_gen, struct btrfs_root_backup,
+		   extent_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_extent_root_level, struct btrfs_root_backup,
+		   extent_root_level, 8);
+
+BTRFS_SETGET_STACK_FUNCS(backup_fs_root, struct btrfs_root_backup,
+		   fs_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_fs_root_gen, struct btrfs_root_backup,
+		   fs_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_fs_root_level, struct btrfs_root_backup,
+		   fs_root_level, 8);
+
-#define btrfs_item_ptr(l,s,t)			\
-	((t *) btrfs_leaf_data((l),(s)))
+BTRFS_SETGET_STACK_FUNCS(backup_dev_root, struct btrfs_root_backup,
+		   dev_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_dev_root_gen, struct btrfs_root_backup,
+		   dev_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_dev_root_level, struct btrfs_root_backup,
+		   dev_root_level, 8);
+
+BTRFS_SETGET_STACK_FUNCS(backup_csum_root, struct btrfs_root_backup,
+		   csum_root, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_csum_root_gen, struct btrfs_root_backup,
+		   csum_root_gen, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_csum_root_level, struct btrfs_root_backup,
+		   csum_root_level, 8);
+BTRFS_SETGET_STACK_FUNCS(backup_total_bytes, struct btrfs_root_backup,
+		   total_bytes, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_bytes_used, struct btrfs_root_backup,
+		   bytes_used, 64);
+BTRFS_SETGET_STACK_FUNCS(backup_num_devices, struct btrfs_root_backup,
+		   num_devices, 64);
+
+/* struct btrfs_super_block */
+
+BTRFS_SETGET_STACK_FUNCS(super_bytenr, struct btrfs_super_block, bytenr, 64);
+BTRFS_SETGET_STACK_FUNCS(super_flags, struct btrfs_super_block, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(super_generation, struct btrfs_super_block,
+			 generation, 64);
+BTRFS_SETGET_STACK_FUNCS(super_root, struct btrfs_super_block, root, 64);
+BTRFS_SETGET_STACK_FUNCS(super_sys_array_size,
+			 struct btrfs_super_block, sys_chunk_array_size, 32);
+BTRFS_SETGET_STACK_FUNCS(super_chunk_root_generation,
+			 struct btrfs_super_block, chunk_root_generation, 64);
+BTRFS_SETGET_STACK_FUNCS(super_root_level, struct btrfs_super_block,
+			 root_level, 8);
+BTRFS_SETGET_STACK_FUNCS(super_chunk_root, struct btrfs_super_block,
+			 chunk_root, 64);
+BTRFS_SETGET_STACK_FUNCS(super_chunk_root_level, struct btrfs_super_block,
+			 chunk_root_level, 8);
+BTRFS_SETGET_STACK_FUNCS(super_log_root, struct btrfs_super_block,
+			 log_root, 64);
+BTRFS_SETGET_STACK_FUNCS(super_log_root_transid, struct btrfs_super_block,
+			 log_root_transid, 64);
+BTRFS_SETGET_STACK_FUNCS(super_log_root_level, struct btrfs_super_block,
+			 log_root_level, 8);
+BTRFS_SETGET_STACK_FUNCS(super_total_bytes, struct btrfs_super_block,
+			 total_bytes, 64);
+BTRFS_SETGET_STACK_FUNCS(super_bytes_used, struct btrfs_super_block,
+			 bytes_used, 64);
+BTRFS_SETGET_STACK_FUNCS(super_sectorsize, struct btrfs_super_block,
+			 sectorsize, 32);
+BTRFS_SETGET_STACK_FUNCS(super_nodesize, struct btrfs_super_block,
+			 nodesize, 32);
+BTRFS_SETGET_STACK_FUNCS(super_stripesize, struct btrfs_super_block,
+			 stripesize, 32);
+BTRFS_SETGET_STACK_FUNCS(super_root_dir, struct btrfs_super_block,
+			 root_dir_objectid, 64);
+BTRFS_SETGET_STACK_FUNCS(super_num_devices, struct btrfs_super_block,
+			 num_devices, 64);
+BTRFS_SETGET_STACK_FUNCS(super_compat_flags, struct btrfs_super_block,
+			 compat_flags, 64);
+BTRFS_SETGET_STACK_FUNCS(super_compat_ro_flags, struct btrfs_super_block,
+			 compat_ro_flags, 64);
+BTRFS_SETGET_STACK_FUNCS(super_incompat_flags, struct btrfs_super_block,
+			 incompat_flags, 64);
+BTRFS_SETGET_STACK_FUNCS(super_csum_type, struct btrfs_super_block,
+			 csum_type, 16);
+BTRFS_SETGET_STACK_FUNCS(super_cache_generation, struct btrfs_super_block,
+			 cache_generation, 64);
+BTRFS_SETGET_STACK_FUNCS(super_uuid_tree_generation, struct btrfs_super_block,
+			 uuid_tree_generation, 64);
+BTRFS_SETGET_STACK_FUNCS(super_magic, struct btrfs_super_block, magic, 64);
+
+static inline unsigned long btrfs_leaf_data(struct extent_buffer *l)
+{
+	return offsetof(struct btrfs_leaf, items);
+}
+
+/* struct btrfs_file_extent_item */
+BTRFS_SETGET_FUNCS(file_extent_type, struct btrfs_file_extent_item, type, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_type, struct btrfs_file_extent_item, type, 8);
+
+static inline unsigned long btrfs_file_extent_inline_start(struct
+						   btrfs_file_extent_item *e)
+{
+	unsigned long offset = (unsigned long)e;
+	offset += offsetof(struct btrfs_file_extent_item, disk_bytenr);
+	return offset;
+}
+
+static inline u32 btrfs_file_extent_calc_inline_size(u32 datasize)
+{
+	return offsetof(struct btrfs_file_extent_item, disk_bytenr) + datasize;
+}
+
+BTRFS_SETGET_FUNCS(file_extent_disk_bytenr, struct btrfs_file_extent_item,
+		   disk_bytenr, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_disk_bytenr, struct btrfs_file_extent_item,
+		   disk_bytenr, 64);
+BTRFS_SETGET_FUNCS(file_extent_generation, struct btrfs_file_extent_item,
+		   generation, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_generation, struct btrfs_file_extent_item,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(file_extent_disk_num_bytes, struct btrfs_file_extent_item,
+		   disk_num_bytes, 64);
+BTRFS_SETGET_FUNCS(file_extent_offset, struct btrfs_file_extent_item,
+		  offset, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_offset, struct btrfs_file_extent_item,
+		  offset, 64);
+BTRFS_SETGET_FUNCS(file_extent_num_bytes, struct btrfs_file_extent_item,
+		   num_bytes, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_num_bytes, struct btrfs_file_extent_item,
+		   num_bytes, 64);
+BTRFS_SETGET_FUNCS(file_extent_ram_bytes, struct btrfs_file_extent_item,
+		   ram_bytes, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_ram_bytes, struct btrfs_file_extent_item,
+		   ram_bytes, 64);
+BTRFS_SETGET_FUNCS(file_extent_compression, struct btrfs_file_extent_item,
+		   compression, 8);
+BTRFS_SETGET_STACK_FUNCS(stack_file_extent_compression, struct btrfs_file_extent_item,
+		   compression, 8);
+BTRFS_SETGET_FUNCS(file_extent_encryption, struct btrfs_file_extent_item,
+		   encryption, 8);
+BTRFS_SETGET_FUNCS(file_extent_other_encoding, struct btrfs_file_extent_item,
+		   other_encoding, 16);
+
+/* btrfs_qgroup_status_item */
+BTRFS_SETGET_FUNCS(qgroup_status_version, struct btrfs_qgroup_status_item,
+		   version, 64);
+BTRFS_SETGET_FUNCS(qgroup_status_generation, struct btrfs_qgroup_status_item,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(qgroup_status_flags, struct btrfs_qgroup_status_item,
+		   flags, 64);
+BTRFS_SETGET_FUNCS(qgroup_status_rescan, struct btrfs_qgroup_status_item,
+		   rescan, 64);
+
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_status_version,
+			 struct btrfs_qgroup_status_item, version, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_status_generation,
+			 struct btrfs_qgroup_status_item, generation, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_status_flags,
+			 struct btrfs_qgroup_status_item, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_status_rescan,
+			 struct btrfs_qgroup_status_item, rescan, 64);
+
+/* btrfs_qgroup_info_item */
+BTRFS_SETGET_FUNCS(qgroup_info_generation, struct btrfs_qgroup_info_item,
+		   generation, 64);
+BTRFS_SETGET_FUNCS(qgroup_info_referenced, struct btrfs_qgroup_info_item,
+		   rfer, 64);
+BTRFS_SETGET_FUNCS(qgroup_info_referenced_compressed,
+		   struct btrfs_qgroup_info_item, rfer_cmpr, 64);
+BTRFS_SETGET_FUNCS(qgroup_info_exclusive, struct btrfs_qgroup_info_item,
+		   excl, 64);
+BTRFS_SETGET_FUNCS(qgroup_info_exclusive_compressed,
+		   struct btrfs_qgroup_info_item, excl_cmpr, 64);
+
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_info_generation,
+			 struct btrfs_qgroup_info_item, generation, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_info_referenced,
+			 struct btrfs_qgroup_info_item, rfer, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_info_referenced_compressed,
+		   struct btrfs_qgroup_info_item, rfer_cmpr, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_info_exclusive,
+			 struct btrfs_qgroup_info_item, excl, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_info_exclusive_compressed,
+		   struct btrfs_qgroup_info_item, excl_cmpr, 64);
+
+/* btrfs_qgroup_limit_item */
+BTRFS_SETGET_FUNCS(qgroup_limit_flags, struct btrfs_qgroup_limit_item,
+		   flags, 64);
+BTRFS_SETGET_FUNCS(qgroup_limit_max_referenced, struct btrfs_qgroup_limit_item,
+		   max_rfer, 64);
+BTRFS_SETGET_FUNCS(qgroup_limit_max_exclusive, struct btrfs_qgroup_limit_item,
+		   max_excl, 64);
+BTRFS_SETGET_FUNCS(qgroup_limit_rsv_referenced, struct btrfs_qgroup_limit_item,
+		   rsv_rfer, 64);
+BTRFS_SETGET_FUNCS(qgroup_limit_rsv_exclusive, struct btrfs_qgroup_limit_item,
+		   rsv_excl, 64);
+
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_limit_flags,
+			 struct btrfs_qgroup_limit_item, flags, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_limit_max_referenced,
+			 struct btrfs_qgroup_limit_item, max_rfer, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_limit_max_exclusive,
+			 struct btrfs_qgroup_limit_item, max_excl, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_limit_rsv_referenced,
+			 struct btrfs_qgroup_limit_item, rsv_rfer, 64);
+BTRFS_SETGET_STACK_FUNCS(stack_qgroup_limit_rsv_exclusive,
+			 struct btrfs_qgroup_limit_item, rsv_excl, 64);
+
+/* btrfs_balance_item */
+BTRFS_SETGET_FUNCS(balance_item_flags, struct btrfs_balance_item, flags, 64);
+
+static inline struct btrfs_disk_balance_args* btrfs_balance_item_data(
+		struct extent_buffer *eb, struct btrfs_balance_item *bi)
+{
+	unsigned long offset = (unsigned long)bi;
+	struct btrfs_balance_item *p;
+	p = (struct btrfs_balance_item *)(eb->data + offset);
+	return &p->data;
+}
+
+static inline struct btrfs_disk_balance_args* btrfs_balance_item_meta(
+		struct extent_buffer *eb, struct btrfs_balance_item *bi)
+{
+	unsigned long offset = (unsigned long)bi;
+	struct btrfs_balance_item *p;
+	p = (struct btrfs_balance_item *)(eb->data + offset);
+	return &p->meta;
+}
+
+static inline struct btrfs_disk_balance_args* btrfs_balance_item_sys(
+		struct extent_buffer *eb, struct btrfs_balance_item *bi)
+{
+	unsigned long offset = (unsigned long)bi;
+	struct btrfs_balance_item *p;
+	p = (struct btrfs_balance_item *)(eb->data + offset);
+	return &p->sys;
+}
+
+static inline u64 btrfs_dev_stats_value(const struct extent_buffer *eb,
+					const struct btrfs_dev_stats_item *ptr,
+					int index)
+{
+	u64 val;
+
+	read_extent_buffer(eb, &val,
+			   offsetof(struct btrfs_dev_stats_item, values) +
+			    ((unsigned long)ptr) + (index * sizeof(u64)),
+			   sizeof(val));
+	return val;
+}
+
+/*
+ * this returns the number of bytes used by the item on disk, minus the
+ * size of any extent headers.  If a file is compressed on disk, this is
+ * the compressed size
+ */
+static inline u32 btrfs_file_extent_inline_item_len(struct extent_buffer *eb,
+						    struct btrfs_item *e)
+{
+	unsigned long offset;
+	offset = offsetof(struct btrfs_file_extent_item, disk_bytenr);
+	return btrfs_item_size(eb, e) - offset;
+}
+
+#define btrfs_fs_incompat(fs_info, opt) \
+	__btrfs_fs_incompat((fs_info), BTRFS_FEATURE_INCOMPAT_##opt)
+
+static inline bool __btrfs_fs_incompat(struct btrfs_fs_info *fs_info, u64 flag)
+{
+	struct btrfs_super_block *disk_super;
+	disk_super = fs_info->super_copy;
+	return !!(btrfs_super_incompat_flags(disk_super) & flag);
+}
+
+#define btrfs_fs_compat_ro(fs_info, opt) \
+	__btrfs_fs_compat_ro((fs_info), BTRFS_FEATURE_COMPAT_RO_##opt)
+
+static inline int __btrfs_fs_compat_ro(struct btrfs_fs_info *fs_info, u64 flag)
+{
+	struct btrfs_super_block *disk_super;
+	disk_super = fs_info->super_copy;
+	return !!(btrfs_super_compat_ro_flags(disk_super) & flag);
+}
+
+/* helper function to cast into the data area of the leaf. */
+#define btrfs_item_ptr(leaf, slot, type) \
+	((type *)(btrfs_leaf_data(leaf) + \
+	btrfs_item_offset_nr(leaf, slot)))
+
+#define btrfs_item_ptr_offset(leaf, slot) \
+	((unsigned long)(btrfs_leaf_data(leaf) + \
+	btrfs_item_offset_nr(leaf, slot)))
+
+static inline u64 btrfs_name_hash(const char *name, int len)
+{
+	return (u64)crc32c((u32)~1, (u8 *)name, len);
+}
+
+/*
+ * Figure the key offset of an extended inode ref
+ */
+static inline u64 btrfs_extref_hash(u64 parent_objectid, const char *name,
+				    int len)
+{
+	return crc32(parent_objectid, (u8 *)name, len);
+}
+
+union btrfs_tree_node {
+	struct btrfs_header header;
+	struct btrfs_leaf leaf;
+	struct btrfs_node node;
+};
 
 #define btrfs_path_item_ptr(p,t)		\
 	((t *) btrfs_path_leaf_data((p)))
 
+u16 btrfs_super_csum_size(const struct btrfs_super_block *s);
+const char *btrfs_super_csum_name(u16 csum_type);
+u16 btrfs_csum_type_size(u16 csum_type);
+size_t btrfs_super_num_csums(void);
+
+/* root-tree.c */
+int btrfs_find_last_root(struct btrfs_root *root, u64 objectid,
+			struct btrfs_root_item *item, struct btrfs_key *key);
+
+/* dir-item.c */
+struct btrfs_dir_item *btrfs_lookup_dir_item(struct btrfs_trans_handle *trans,
+					     struct btrfs_root *root,
+					     struct btrfs_path *path, u64 dir,
+					     const char *name, int name_len,
+					     int mod);
+typedef int (*btrfs_iter_dir_callback_t)(struct btrfs_root *root,
+					 struct extent_buffer *eb,
+					 struct btrfs_dir_item *di);
+int btrfs_iter_dir(struct btrfs_root *root, u64 ino,
+		   btrfs_iter_dir_callback_t callback);
+/* inode.c */
+int btrfs_lookup_path(struct btrfs_root *root, u64 ino, const char *filename,
+			struct btrfs_root **root_ret, u64 *ino_ret,
+			u8 *type_ret, int symlink_limit);
+int btrfs_read_extent_inline(struct btrfs_path *path,
+			     struct btrfs_file_extent_item *fi, char *dest);
+int btrfs_read_extent_reg(struct btrfs_path *path,
+			  struct btrfs_file_extent_item *fi, u64 offset,
+			  int len, char *dest);
+
+/* ctree.c */
+int btrfs_comp_cpu_keys(const struct btrfs_key *k1, const struct btrfs_key *k2);
+enum btrfs_tree_block_status
+btrfs_check_node(struct btrfs_fs_info *fs_info,
+		 struct btrfs_disk_key *parent_key, struct extent_buffer *buf);
+enum btrfs_tree_block_status
+btrfs_check_leaf(struct btrfs_fs_info *fs_info,
+		 struct btrfs_disk_key *parent_key, struct extent_buffer *buf);
+struct extent_buffer *read_node_slot(struct btrfs_fs_info *fs_info,
+				   struct extent_buffer *parent, int slot);
+int btrfs_previous_item(struct btrfs_root *root,
+			struct btrfs_path *path, u64 min_objectid,
+			int type);
+int btrfs_next_sibling_tree_block(struct btrfs_fs_info *fs_info,
+				  struct btrfs_path *path);
+/*
+ * Walk up the tree as far as necessary to find the next leaf.
+ *
+ * returns 0 if it found something or 1 if there are no greater leaves.
+ * returns < 0 on io errors.
+ */
+static inline int btrfs_next_leaf(struct btrfs_root *root,
+				  struct btrfs_path *path)
+{
+	path->lowest_level = 0;
+	return btrfs_next_sibling_tree_block(root->fs_info, path);
+}
+
+static inline int btrfs_next_item(struct btrfs_root *root,
+				  struct btrfs_path *p)
+{
+	++p->slots[0];
+	if (p->slots[0] >= btrfs_header_nritems(p->nodes[0]))
+		return btrfs_next_leaf(root, p);
+	return 0;
+}
+
+int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path);
+int btrfs_leaf_free_space(struct extent_buffer *leaf);
+int btrfs_search_slot(struct btrfs_trans_handle *trans,
+		struct btrfs_root *root, const struct btrfs_key *key,
+		struct btrfs_path *p, int ins_len, int cow);
+int btrfs_search_slot_for_read(struct btrfs_root *root,
+			       const struct btrfs_key *key,
+			       struct btrfs_path *p, int find_higher,
+			       int return_any);
+void btrfs_release_path(struct btrfs_path *p);
+struct btrfs_path *btrfs_alloc_path(void);
+void btrfs_free_path(struct btrfs_path *p);
+static inline void btrfs_init_path(struct btrfs_path *p)
+{
+	memset(p, 0, sizeof(*p));
+}
+int btrfs_bin_search(struct extent_buffer *eb, const struct btrfs_key *key,
+		     int *slot);
+int btrfs_find_item(struct btrfs_root *fs_root, struct btrfs_path *found_path,
+		u64 iobjectid, u64 ioff, u8 key_type,
+		struct btrfs_key *found_key);
 #endif /* __BTRFS_CTREE_H__ */

diff --git a/fs/btrfs/dir-item.c b/fs/btrfs/dir-item.c
index 63b5bf0..aab197a 100644
--- a/fs/btrfs/dir-item.c
+++ b/fs/btrfs/dir-item.c

@@ -6,119 +6,163 @@
  */
 
 #include "btrfs.h"
+#include "disk-io.h"
 
-static int verify_dir_item(struct btrfs_dir_item *item, u32 start, u32 total)
+static int verify_dir_item(struct btrfs_root *root,
+		    struct extent_buffer *leaf,
+		    struct btrfs_dir_item *dir_item)
 {
-	u16 max_len = BTRFS_NAME_LEN;
-	u32 end;
+	u16 namelen = BTRFS_NAME_LEN;
+	u8 type = btrfs_dir_type(leaf, dir_item);
 
-	if (item->type >= BTRFS_FT_MAX) {
-		printf("%s: invalid dir item type: %i\n", __func__, item->type);
+	if (type == BTRFS_FT_XATTR)
+		namelen = XATTR_NAME_MAX;
+
+	if (btrfs_dir_name_len(leaf, dir_item) > namelen) {
+		fprintf(stderr, "invalid dir item name len: %u\n",
+			(unsigned)btrfs_dir_data_len(leaf, dir_item));
 		return 1;
 	}
 
-	if (item->type == BTRFS_FT_XATTR)
-		max_len = 255; /* XATTR_NAME_MAX */
-
-	end = start + sizeof(*item) + item->name_len;
-	if (item->name_len > max_len || end > total) {
-		printf("%s: invalid dir item name len: %u\n", __func__,
-		       item->name_len);
+	/* BTRFS_MAX_XATTR_SIZE is the same for all dir items */
+	if ((btrfs_dir_data_len(leaf, dir_item) +
+	     btrfs_dir_name_len(leaf, dir_item)) >
+			BTRFS_MAX_XATTR_SIZE(root->fs_info)) {
+		fprintf(stderr, "invalid dir item name + data len: %u + %u\n",
+			(unsigned)btrfs_dir_name_len(leaf, dir_item),
+			(unsigned)btrfs_dir_data_len(leaf, dir_item));
 		return 1;
 	}
 
 	return 0;
 }
 
-static struct btrfs_dir_item *
-btrfs_match_dir_item_name(struct btrfs_path *path, const char *name,
-			  int name_len)
+struct btrfs_dir_item *btrfs_match_dir_item_name(struct btrfs_root *root,
+			      struct btrfs_path *path,
+			      const char *name, int name_len)
 {
-	struct btrfs_dir_item *item;
-	u32 total_len, cur = 0, this_len;
-	const char *name_ptr;
+	struct btrfs_dir_item *dir_item;
+	unsigned long name_ptr;
+	u32 total_len;
+	u32 cur = 0;
+	u32 this_len;
+	struct extent_buffer *leaf;
 
-	item = btrfs_path_item_ptr(path, struct btrfs_dir_item);
+	leaf = path->nodes[0];
+	dir_item = btrfs_item_ptr(leaf, path->slots[0], struct btrfs_dir_item);
+	total_len = btrfs_item_size_nr(leaf, path->slots[0]);
+	if (verify_dir_item(root, leaf, dir_item))
+		return NULL;
 
-	total_len = btrfs_path_item_size(path);
+	while(cur < total_len) {
+		this_len = sizeof(*dir_item) +
+			btrfs_dir_name_len(leaf, dir_item) +
+			btrfs_dir_data_len(leaf, dir_item);
+		if (this_len > (total_len - cur)) {
+			fprintf(stderr, "invalid dir item size\n");
+			return NULL;
+		}
 
-	while (cur < total_len) {
-		btrfs_dir_item_to_cpu(item);
-		this_len = sizeof(*item) + item->name_len + item->data_len;
-		name_ptr = (const char *) (item + 1);
+		name_ptr = (unsigned long)(dir_item + 1);
 
-		if (verify_dir_item(item, cur, total_len))
-			return NULL;
-		if (item->name_len == name_len && !memcmp(name_ptr, name,
-							  name_len))
-			return item;
+		if (btrfs_dir_name_len(leaf, dir_item) == name_len &&
+		    memcmp_extent_buffer(leaf, name, name_ptr, name_len) == 0)
+			return dir_item;
 
 		cur += this_len;
-		item = (struct btrfs_dir_item *) ((u8 *) item + this_len);
+		dir_item = (struct btrfs_dir_item *)((char *)dir_item +
+						     this_len);
 	}
-
 	return NULL;
 }
 
-int btrfs_lookup_dir_item(const struct btrfs_root *root, u64 dir,
-			  const char *name, int name_len,
-			  struct btrfs_dir_item *item)
+struct btrfs_dir_item *btrfs_lookup_dir_item(struct btrfs_trans_handle *trans,
+					     struct btrfs_root *root,
+					     struct btrfs_path *path, u64 dir,
+					     const char *name, int name_len,
+					     int mod)
 {
-	struct btrfs_path path;
+	int ret;
 	struct btrfs_key key;
-	struct btrfs_dir_item *res = NULL;
+	int ins_len = mod < 0 ? -1 : 0;
+	int cow = mod != 0;
+	struct btrfs_key found_key;
+	struct extent_buffer *leaf;
 
 	key.objectid = dir;
 	key.type = BTRFS_DIR_ITEM_KEY;
+
 	key.offset = btrfs_name_hash(name, name_len);
 
+	ret = btrfs_search_slot(trans, root, &key, path, ins_len, cow);
+	if (ret < 0)
+		return ERR_PTR(ret);
+	if (ret > 0) {
+		if (path->slots[0] == 0)
+			return NULL;
+		path->slots[0]--;
+	}
+
-	if (btrfs_search_tree(root, &key, &path))
-		return -1;
+	leaf = path->nodes[0];
+	btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
 
-	if (btrfs_comp_keys_type(&key, btrfs_path_leaf_key(&path)))
-		goto out;
+	if (found_key.objectid != dir ||
+	    found_key.type != BTRFS_DIR_ITEM_KEY ||
+	    found_key.offset != key.offset)
+		return NULL;
 
-	res = btrfs_match_dir_item_name(&path, name, name_len);
-	if (res)
-		*item = *res;
-out:
-	btrfs_free_path(&path);
-	return res ? 0 : -1;
+	return btrfs_match_dir_item_name(root, path, name, name_len);
 }
 
-int btrfs_readdir(const struct btrfs_root *root, u64 dir,
-		  btrfs_readdir_callback_t callback)
+int btrfs_iter_dir(struct btrfs_root *root, u64 ino,
+		   btrfs_iter_dir_callback_t callback)
 {
 	struct btrfs_path path;
-	struct btrfs_key key, *found_key;
-	struct btrfs_dir_item *item;
-	int res = 0;
+	struct btrfs_key key;
+	int ret;
 
-	key.objectid = dir;
+	btrfs_init_path(&path);
+	key.objectid = ino;
 	key.type = BTRFS_DIR_INDEX_KEY;
 	key.offset = 0;
 
-	if (btrfs_search_tree(root, &key, &path))
-		return -1;
-
+	ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+	if (ret < 0)
+		return ret;
+	/* Should not happen */
+	if (ret == 0) {
+		ret = -EUCLEAN;
+		goto out;
+	}
+	if (path.slots[0] >= btrfs_header_nritems(path.nodes[0])) {
+		ret = btrfs_next_leaf(root, &path);
+		if (ret < 0)
+			goto out;
+		if (ret > 0) {
+			ret = 0;
+			goto out;
+		}
+	}
 	do {
-		found_key = btrfs_path_leaf_key(&path);
-		if (btrfs_comp_keys_type(&key, found_key))
-			break;
-
-		item = btrfs_path_item_ptr(&path, struct btrfs_dir_item);
-		btrfs_dir_item_to_cpu(item);
-
-		if (verify_dir_item(item, 0, sizeof(*item) + item->name_len))
-			continue;
-		if (item->type == BTRFS_FT_XATTR)
-			continue;
+		struct btrfs_dir_item *di;
 
-		if (callback(root, item))
+		btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+		if (key.objectid != ino || key.type != BTRFS_DIR_INDEX_KEY)
 			break;
-	} while (!(res = btrfs_next_slot(&path)));
+		di = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				    struct btrfs_dir_item);
+		if (verify_dir_item(root, path.nodes[0], di)) {
+			ret = -EUCLEAN;
+			goto out;
+		}
+		ret = callback(root, path.nodes[0], di);
+		if (ret < 0)
+			goto out;
+	} while (!(ret = btrfs_next_item(root, &path)));
 
-	btrfs_free_path(&path);
-
-	return res < 0 ? -1 : 0;
+	if (ret > 0)
+		ret = 0;
+out:
+	btrfs_release_path(&path);
+	return ret;
 }

diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
new file mode 100644
index 0000000..01e7cee
--- /dev/null
+++ b/fs/btrfs/disk-io.c

@@ -0,0 +1,1062 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <fs_internal.h>
+#include <uuid.h>
+#include <memalign.h>
+#include "kernel-shared/btrfs_tree.h"
+#include "common/rbtree-utils.h"
+#include "disk-io.h"
+#include "ctree.h"
+#include "btrfs.h"
+#include "volumes.h"
+#include "extent-io.h"
+#include "crypto/hash.h"
+
+/* specified errno for check_tree_block */
+#define BTRFS_BAD_BYTENR		(-1)
+#define BTRFS_BAD_FSID			(-2)
+#define BTRFS_BAD_LEVEL			(-3)
+#define BTRFS_BAD_NRITEMS		(-4)
+
+/* Calculate max possible nritems for a leaf/node */
+static u32 max_nritems(u8 level, u32 nodesize)
+{
+
+	if (level == 0)
+		return ((nodesize - sizeof(struct btrfs_header)) /
+			sizeof(struct btrfs_item));
+	return ((nodesize - sizeof(struct btrfs_header)) /
+		sizeof(struct btrfs_key_ptr));
+}
+
+static int check_tree_block(struct btrfs_fs_info *fs_info,
+			    struct extent_buffer *buf)
+{
+
+	struct btrfs_fs_devices *fs_devices = fs_info->fs_devices;
+	u32 nodesize = fs_info->nodesize;
+	bool fsid_match = false;
+	int ret = BTRFS_BAD_FSID;
+
+	if (buf->start != btrfs_header_bytenr(buf))
+		return BTRFS_BAD_BYTENR;
+	if (btrfs_header_level(buf) >= BTRFS_MAX_LEVEL)
+		return BTRFS_BAD_LEVEL;
+	if (btrfs_header_nritems(buf) > max_nritems(btrfs_header_level(buf),
+						    nodesize))
+		return BTRFS_BAD_NRITEMS;
+
+	/* Only leaf can be empty */
+	if (btrfs_header_nritems(buf) == 0 &&
+	    btrfs_header_level(buf) != 0)
+		return BTRFS_BAD_NRITEMS;
+
+	while (fs_devices) {
+		/*
+		 * Checking the incompat flag is only valid for the current
+		 * fs. For seed devices it's forbidden to have their uuid
+		 * changed so reading ->fsid in this case is fine
+		 */
+		if (fs_devices == fs_info->fs_devices &&
+		    btrfs_fs_incompat(fs_info, METADATA_UUID))
+			fsid_match = !memcmp_extent_buffer(buf,
+						   fs_devices->metadata_uuid,
+						   btrfs_header_fsid(),
+						   BTRFS_FSID_SIZE);
+		else
+			fsid_match = !memcmp_extent_buffer(buf,
+						    fs_devices->fsid,
+						    btrfs_header_fsid(),
+						    BTRFS_FSID_SIZE);
+
+
+		if (fsid_match) {
+			ret = 0;
+			break;
+		}
+		fs_devices = fs_devices->seed;
+	}
+	return ret;
+}
+
+static void print_tree_block_error(struct btrfs_fs_info *fs_info,
+				struct extent_buffer *eb,
+				int err)
+{
+	char fs_uuid[BTRFS_UUID_UNPARSED_SIZE] = {'\0'};
+	char found_uuid[BTRFS_UUID_UNPARSED_SIZE] = {'\0'};
+	u8 buf[BTRFS_UUID_SIZE];
+
+	if (!err)
+		return;
+
+	fprintf(stderr, "bad tree block %llu, ", eb->start);
+	switch (err) {
+	case BTRFS_BAD_FSID:
+		read_extent_buffer(eb, buf, btrfs_header_fsid(),
+				   BTRFS_UUID_SIZE);
+		uuid_unparse(buf, found_uuid);
+		uuid_unparse(fs_info->fs_devices->metadata_uuid, fs_uuid);
+		fprintf(stderr, "fsid mismatch, want=%s, have=%s\n",
+			fs_uuid, found_uuid);
+		break;
+	case BTRFS_BAD_BYTENR:
+		fprintf(stderr, "bytenr mismatch, want=%llu, have=%llu\n",
+			eb->start, btrfs_header_bytenr(eb));
+		break;
+	case BTRFS_BAD_LEVEL:
+		fprintf(stderr, "bad level, %u > %d\n",
+			btrfs_header_level(eb), BTRFS_MAX_LEVEL);
+		break;
+	case BTRFS_BAD_NRITEMS:
+		fprintf(stderr, "invalid nr_items: %u\n",
+			btrfs_header_nritems(eb));
+		break;
+	}
+}
+
+int btrfs_csum_data(u16 csum_type, const u8 *data, u8 *out, size_t len)
+{
+	memset(out, 0, BTRFS_CSUM_SIZE);
+
+	switch (csum_type) {
+	case BTRFS_CSUM_TYPE_CRC32:
+		return hash_crc32c(data, len, out);
+	case BTRFS_CSUM_TYPE_XXHASH:
+		return hash_xxhash(data, len, out);
+	case BTRFS_CSUM_TYPE_SHA256:
+		return hash_sha256(data, len, out);
+	default:
+		printf("Unknown csum type %d\n", csum_type);
+		return -EINVAL;
+	}
+}
+
+/*
+ * Check if the super is valid:
+ * - nodesize/sectorsize - minimum, maximum, alignment
+ * - tree block starts   - alignment
+ * - number of devices   - something sane
+ * - sys array size      - maximum
+ */
+static int btrfs_check_super(struct btrfs_super_block *sb)
+{
+	u8 result[BTRFS_CSUM_SIZE];
+	u16 csum_type;
+	int csum_size;
+	u8 *metadata_uuid;
+
+	if (btrfs_super_magic(sb) != BTRFS_MAGIC)
+		return -EIO;
+
+	csum_type = btrfs_super_csum_type(sb);
+	if (csum_type >= btrfs_super_num_csums()) {
+		error("unsupported checksum algorithm %u", csum_type);
+		return -EIO;
+	}
+	csum_size = btrfs_super_csum_size(sb);
+
+	btrfs_csum_data(csum_type, (u8 *)sb + BTRFS_CSUM_SIZE,
+			result, BTRFS_SUPER_INFO_SIZE - BTRFS_CSUM_SIZE);
+
+	if (memcmp(result, sb->csum, csum_size)) {
+		error("superblock checksum mismatch");
+		return -EIO;
+	}
+	if (btrfs_super_root_level(sb) >= BTRFS_MAX_LEVEL) {
+		error("tree_root level too big: %d >= %d",
+			btrfs_super_root_level(sb), BTRFS_MAX_LEVEL);
+		goto error_out;
+	}
+	if (btrfs_super_chunk_root_level(sb) >= BTRFS_MAX_LEVEL) {
+		error("chunk_root level too big: %d >= %d",
+			btrfs_super_chunk_root_level(sb), BTRFS_MAX_LEVEL);
+		goto error_out;
+	}
+	if (btrfs_super_log_root_level(sb) >= BTRFS_MAX_LEVEL) {
+		error("log_root level too big: %d >= %d",
+			btrfs_super_log_root_level(sb), BTRFS_MAX_LEVEL);
+		goto error_out;
+	}
+
+	if (!IS_ALIGNED(btrfs_super_root(sb), 4096)) {
+		error("tree_root block unaligned: %llu", btrfs_super_root(sb));
+		goto error_out;
+	}
+	if (!IS_ALIGNED(btrfs_super_chunk_root(sb), 4096)) {
+		error("chunk_root block unaligned: %llu",
+			btrfs_super_chunk_root(sb));
+		goto error_out;
+	}
+	if (!IS_ALIGNED(btrfs_super_log_root(sb), 4096)) {
+		error("log_root block unaligned: %llu",
+			btrfs_super_log_root(sb));
+		goto error_out;
+	}
+	if (btrfs_super_nodesize(sb) < 4096) {
+		error("nodesize too small: %u < 4096",
+			btrfs_super_nodesize(sb));
+		goto error_out;
+	}
+	if (!IS_ALIGNED(btrfs_super_nodesize(sb), 4096)) {
+		error("nodesize unaligned: %u", btrfs_super_nodesize(sb));
+		goto error_out;
+	}
+	if (btrfs_super_sectorsize(sb) < 4096) {
+		error("sectorsize too small: %u < 4096",
+			btrfs_super_sectorsize(sb));
+		goto error_out;
+	}
+	if (!IS_ALIGNED(btrfs_super_sectorsize(sb), 4096)) {
+		error("sectorsize unaligned: %u", btrfs_super_sectorsize(sb));
+		goto error_out;
+	}
+	if (btrfs_super_total_bytes(sb) == 0) {
+		error("invalid total_bytes 0");
+		goto error_out;
+	}
+	if (btrfs_super_bytes_used(sb) < 6 * btrfs_super_nodesize(sb)) {
+		error("invalid bytes_used %llu", btrfs_super_bytes_used(sb));
+		goto error_out;
+	}
+	if ((btrfs_super_stripesize(sb) != 4096)
+		&& (btrfs_super_stripesize(sb) != btrfs_super_sectorsize(sb))) {
+		error("invalid stripesize %u", btrfs_super_stripesize(sb));
+		goto error_out;
+	}
+
+	if (btrfs_super_incompat_flags(sb) & BTRFS_FEATURE_INCOMPAT_METADATA_UUID)
+		metadata_uuid = sb->metadata_uuid;
+	else
+		metadata_uuid = sb->fsid;
+
+	if (memcmp(metadata_uuid, sb->dev_item.fsid, BTRFS_FSID_SIZE) != 0) {
+		char fsid[BTRFS_UUID_UNPARSED_SIZE];
+		char dev_fsid[BTRFS_UUID_UNPARSED_SIZE];
+
+		uuid_unparse(sb->metadata_uuid, fsid);
+		uuid_unparse(sb->dev_item.fsid, dev_fsid);
+		error("dev_item UUID does not match fsid: %s != %s",
+			dev_fsid, fsid);
+		goto error_out;
+	}
+
+	/*
+	 * Hint to catch really bogus numbers, bitflips or so
+	 */
+	if (btrfs_super_num_devices(sb) > (1UL << 31)) {
+		error("suspicious number of devices: %llu",
+			btrfs_super_num_devices(sb));
+	}
+
+	if (btrfs_super_num_devices(sb) == 0) {
+		error("number of devices is 0");
+		goto error_out;
+	}
+
+	/*
+	 * Obvious sys_chunk_array corruptions, it must hold at least one key
+	 * and one chunk
+	 */
+	if (btrfs_super_sys_array_size(sb) > BTRFS_SYSTEM_CHUNK_ARRAY_SIZE) {
+		error("system chunk array too big %u > %u",
+		      btrfs_super_sys_array_size(sb),
+		      BTRFS_SYSTEM_CHUNK_ARRAY_SIZE);
+		goto error_out;
+	}
+	if (btrfs_super_sys_array_size(sb) < sizeof(struct btrfs_disk_key)
+			+ sizeof(struct btrfs_chunk)) {
+		error("system chunk array too small %u < %zu",
+		      btrfs_super_sys_array_size(sb),
+		      sizeof(struct btrfs_disk_key) +
+		      sizeof(struct btrfs_chunk));
+		goto error_out;
+	}
+
+	return 0;
+
+error_out:
+	error("superblock checksum matches but it has invalid members");
+	return -EIO;
+}
+
+/*
+ * btrfs_read_dev_super - read a valid primary superblock from a block device
+ * @desc,@part:	file descriptor of the device
+ * @sb:		buffer where the superblock is going to be read in
+ *
+ * Unlike the btrfs-progs/kernel version, here we ony care about the first
+ * super block, thus it's much simpler.
+ */
+int btrfs_read_dev_super(struct blk_desc *desc, struct disk_partition *part,
+			 struct btrfs_super_block *sb)
+{
+	char tmp[BTRFS_SUPER_INFO_SIZE];
+	struct btrfs_super_block *buf = (struct btrfs_super_block *)tmp;
+	int ret;
+
+	ret = __btrfs_devread(desc, part, tmp, BTRFS_SUPER_INFO_SIZE,
+			      BTRFS_SUPER_INFO_OFFSET);
+	if (ret < BTRFS_SUPER_INFO_SIZE)
+		return -EIO;
+
+	if (btrfs_super_bytenr(buf) != BTRFS_SUPER_INFO_OFFSET)
+		return -EIO;
+
+	if (btrfs_check_super(buf))
+		return -EIO;
+
+	memcpy(sb, buf, BTRFS_SUPER_INFO_SIZE);
+	return 0;
+}
+
+static int __csum_tree_block_size(struct extent_buffer *buf, u16 csum_size,
+				  int verify, int silent, u16 csum_type)
+{
+	u8 result[BTRFS_CSUM_SIZE];
+	u32 len;
+
+	len = buf->len - BTRFS_CSUM_SIZE;
+	btrfs_csum_data(csum_type, (u8 *)buf->data + BTRFS_CSUM_SIZE,
+			result, len);
+
+	if (verify) {
+		if (memcmp_extent_buffer(buf, result, 0, csum_size)) {
+			/* FIXME: format */
+			if (!silent)
+				printk("checksum verify failed on %llu found %08X wanted %08X\n",
+				       (unsigned long long)buf->start,
+				       result[0],
+				       buf->data[0]);
+			return 1;
+		}
+	} else {
+		write_extent_buffer(buf, result, 0, csum_size);
+	}
+	return 0;
+}
+
+int csum_tree_block_size(struct extent_buffer *buf, u16 csum_size, int verify,
+			 u16 csum_type)
+{
+	return __csum_tree_block_size(buf, csum_size, verify, 0, csum_type);
+}
+
+static int csum_tree_block(struct btrfs_fs_info *fs_info,
+			   struct extent_buffer *buf, int verify)
+{
+	u16 csum_size = btrfs_super_csum_size(fs_info->super_copy);
+	u16 csum_type = btrfs_super_csum_type(fs_info->super_copy);
+
+	return csum_tree_block_size(buf, csum_size, verify, csum_type);
+}
+
+struct extent_buffer *btrfs_find_tree_block(struct btrfs_fs_info *fs_info,
+					    u64 bytenr, u32 blocksize)
+{
+	return find_extent_buffer(&fs_info->extent_cache,
+				  bytenr, blocksize);
+}
+
+struct extent_buffer* btrfs_find_create_tree_block(
+		struct btrfs_fs_info *fs_info, u64 bytenr)
+{
+	return alloc_extent_buffer(fs_info, bytenr, fs_info->nodesize);
+}
+
+static int verify_parent_transid(struct extent_io_tree *io_tree,
+				 struct extent_buffer *eb, u64 parent_transid,
+				 int ignore)
+{
+	int ret;
+
+	if (!parent_transid || btrfs_header_generation(eb) == parent_transid)
+		return 0;
+
+	if (extent_buffer_uptodate(eb) &&
+	    btrfs_header_generation(eb) == parent_transid) {
+		ret = 0;
+		goto out;
+	}
+	printk("parent transid verify failed on %llu wanted %llu found %llu\n",
+	       (unsigned long long)eb->start,
+	       (unsigned long long)parent_transid,
+	       (unsigned long long)btrfs_header_generation(eb));
+	if (ignore) {
+		eb->flags |= EXTENT_BAD_TRANSID;
+		printk("Ignoring transid failure\n");
+		return 0;
+	}
+
+	ret = 1;
+out:
+	clear_extent_buffer_uptodate(eb);
+	return ret;
+
+}
+
+int read_whole_eb(struct btrfs_fs_info *info, struct extent_buffer *eb, int mirror)
+{
+	unsigned long offset = 0;
+	struct btrfs_multi_bio *multi = NULL;
+	struct btrfs_device *device;
+	int ret = 0;
+	u64 read_len;
+	unsigned long bytes_left = eb->len;
+
+	while (bytes_left) {
+		read_len = bytes_left;
+		device = NULL;
+
+		ret = btrfs_map_block(info, READ, eb->start + offset,
+				      &read_len, &multi, mirror, NULL);
+		if (ret) {
+			printk("Couldn't map the block %Lu\n", eb->start + offset);
+			kfree(multi);
+			return -EIO;
+		}
+		device = multi->stripes[0].dev;
+
+		if (!device->desc || !device->part) {
+			kfree(multi);
+			return -EIO;
+		}
+
+		if (read_len > bytes_left)
+			read_len = bytes_left;
+
+		ret = read_extent_from_disk(device->desc, device->part,
+					    multi->stripes[0].physical, eb,
+					    offset, read_len);
+		kfree(multi);
+		multi = NULL;
+
+		if (ret)
+			return -EIO;
+		offset += read_len;
+		bytes_left -= read_len;
+	}
+	return 0;
+}
+
+struct extent_buffer* read_tree_block(struct btrfs_fs_info *fs_info, u64 bytenr,
+		u64 parent_transid)
+{
+	int ret;
+	struct extent_buffer *eb;
+	u64 best_transid = 0;
+	u32 sectorsize = fs_info->sectorsize;
+	int mirror_num = 1;
+	int good_mirror = 0;
+	int candidate_mirror = 0;
+	int num_copies;
+	int ignore = 0;
+
+	/*
+	 * Don't even try to create tree block for unaligned tree block
+	 * bytenr.
+	 * Such unaligned tree block will free overlapping extent buffer,
+	 * causing use-after-free bugs for fuzzed images.
+	 */
+	if (bytenr < sectorsize || !IS_ALIGNED(bytenr, sectorsize)) {
+		error("tree block bytenr %llu is not aligned to sectorsize %u",
+		      bytenr, sectorsize);
+		return ERR_PTR(-EIO);
+	}
+
+	eb = btrfs_find_create_tree_block(fs_info, bytenr);
+	if (!eb)
+		return ERR_PTR(-ENOMEM);
+
+	if (btrfs_buffer_uptodate(eb, parent_transid))
+		return eb;
+
+	num_copies = btrfs_num_copies(fs_info, eb->start, eb->len);
+	while (1) {
+		ret = read_whole_eb(fs_info, eb, mirror_num);
+		if (ret == 0 && csum_tree_block(fs_info, eb, 1) == 0 &&
+		    check_tree_block(fs_info, eb) == 0 &&
+		    verify_parent_transid(&fs_info->extent_cache, eb,
+					  parent_transid, ignore) == 0) {
+			/*
+			 * check_tree_block() is less strict to allow btrfs
+			 * check to get raw eb with bad key order and fix it.
+			 * But we still need to try to get a good copy if
+			 * possible, or bad key order can go into tools like
+			 * btrfs ins dump-tree.
+			 */
+			if (btrfs_header_level(eb))
+				ret = btrfs_check_node(fs_info, NULL, eb);
+			else
+				ret = btrfs_check_leaf(fs_info, NULL, eb);
+			if (!ret || candidate_mirror == mirror_num) {
+				btrfs_set_buffer_uptodate(eb);
+				return eb;
+			}
+			if (candidate_mirror <= 0)
+				candidate_mirror = mirror_num;
+		}
+		if (ignore) {
+			if (candidate_mirror > 0) {
+				mirror_num = candidate_mirror;
+				continue;
+			}
+			if (check_tree_block(fs_info, eb))
+				print_tree_block_error(fs_info, eb,
+						check_tree_block(fs_info, eb));
+			else
+				fprintf(stderr, "Csum didn't match\n");
+			ret = -EIO;
+			break;
+		}
+		if (num_copies == 1) {
+			ignore = 1;
+			continue;
+		}
+		if (btrfs_header_generation(eb) > best_transid) {
+			best_transid = btrfs_header_generation(eb);
+			good_mirror = mirror_num;
+		}
+		mirror_num++;
+		if (mirror_num > num_copies) {
+			if (candidate_mirror > 0)
+				mirror_num = candidate_mirror;
+			else
+				mirror_num = good_mirror;
+			ignore = 1;
+			continue;
+		}
+	}
+	/*
+	 * We failed to read this tree block, it be should deleted right now
+	 * to avoid stale cache populate the cache.
+	 */
+	free_extent_buffer(eb);
+	return ERR_PTR(ret);
+}
+
+int read_extent_data(struct btrfs_fs_info *fs_info, char *data, u64 logical,
+		     u64 *len, int mirror)
+{
+	u64 offset = 0;
+	struct btrfs_multi_bio *multi = NULL;
+	struct btrfs_device *device;
+	int ret = 0;
+	u64 max_len = *len;
+
+	ret = btrfs_map_block(fs_info, READ, logical, len, &multi, mirror,
+			      NULL);
+	if (ret) {
+		fprintf(stderr, "Couldn't map the block %llu\n",
+				logical + offset);
+		goto err;
+	}
+	device = multi->stripes[0].dev;
+
+	if (*len > max_len)
+		*len = max_len;
+	if (!device->desc || !device->part) {
+		ret = -EIO;
+		goto err;
+	}
+
+	ret = __btrfs_devread(device->desc, device->part, data, *len,
+			      multi->stripes[0].physical);
+	if (ret != *len)
+		ret = -EIO;
+	else
+		ret = 0;
+err:
+	kfree(multi);
+	return ret;
+}
+
+void btrfs_setup_root(struct btrfs_root *root, struct btrfs_fs_info *fs_info,
+		      u64 objectid)
+{
+	root->node = NULL;
+	root->track_dirty = 0;
+
+	root->fs_info = fs_info;
+	root->objectid = objectid;
+	root->last_trans = 0;
+	root->last_inode_alloc = 0;
+
+	memset(&root->root_key, 0, sizeof(root->root_key));
+	memset(&root->root_item, 0, sizeof(root->root_item));
+	root->root_key.objectid = objectid;
+}
+
+static int find_and_setup_root(struct btrfs_root *tree_root,
+			       struct btrfs_fs_info *fs_info,
+			       u64 objectid, struct btrfs_root *root)
+{
+	int ret;
+	u64 generation;
+
+	btrfs_setup_root(root, fs_info, objectid);
+	ret = btrfs_find_last_root(tree_root, objectid,
+				   &root->root_item, &root->root_key);
+	if (ret)
+		return ret;
+
+	generation = btrfs_root_generation(&root->root_item);
+	root->node = read_tree_block(fs_info,
+			btrfs_root_bytenr(&root->root_item), generation);
+	if (!extent_buffer_uptodate(root->node))
+		return -EIO;
+
+	return 0;
+}
+
+int btrfs_free_fs_root(struct btrfs_root *root)
+{
+	if (root->node)
+		free_extent_buffer(root->node);
+	kfree(root);
+	return 0;
+}
+
+static void __free_fs_root(struct rb_node *node)
+{
+	struct btrfs_root *root;
+
+	root = container_of(node, struct btrfs_root, rb_node);
+	btrfs_free_fs_root(root);
+}
+
+FREE_RB_BASED_TREE(fs_roots, __free_fs_root);
+
+struct btrfs_root *btrfs_read_fs_root_no_cache(struct btrfs_fs_info *fs_info,
+					       struct btrfs_key *location)
+{
+	struct btrfs_root *root;
+	struct btrfs_root *tree_root = fs_info->tree_root;
+	struct btrfs_path *path;
+	struct extent_buffer *l;
+	u64 generation;
+	int ret = 0;
+
+	root = calloc(1, sizeof(*root));
+	if (!root)
+		return ERR_PTR(-ENOMEM);
+	if (location->offset == (u64)-1) {
+		ret = find_and_setup_root(tree_root, fs_info,
+					  location->objectid, root);
+		if (ret) {
+			free(root);
+			return ERR_PTR(ret);
+		}
+		goto insert;
+	}
+
+	btrfs_setup_root(root, fs_info,
+			 location->objectid);
+
+	path = btrfs_alloc_path();
+	if (!path) {
+		free(root);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	ret = btrfs_search_slot(NULL, tree_root, location, path, 0, 0);
+	if (ret != 0) {
+		if (ret > 0)
+			ret = -ENOENT;
+		goto out;
+	}
+	l = path->nodes[0];
+	read_extent_buffer(l, &root->root_item,
+	       btrfs_item_ptr_offset(l, path->slots[0]),
+	       sizeof(root->root_item));
+	memcpy(&root->root_key, location, sizeof(*location));
+
+	/* If this root is already an orphan, no need to read */
+	if (btrfs_root_refs(&root->root_item) == 0) {
+		ret = -ENOENT;
+		goto out;
+	}
+	ret = 0;
+out:
+	btrfs_free_path(path);
+	if (ret) {
+		free(root);
+		return ERR_PTR(ret);
+	}
+	generation = btrfs_root_generation(&root->root_item);
+	root->node = read_tree_block(fs_info,
+			btrfs_root_bytenr(&root->root_item), generation);
+	if (!extent_buffer_uptodate(root->node)) {
+		free(root);
+		return ERR_PTR(-EIO);
+	}
+insert:
+	root->ref_cows = 1;
+	return root;
+}
+
+static int btrfs_fs_roots_compare_objectids(struct rb_node *node,
+					    void *data)
+{
+	u64 objectid = *((u64 *)data);
+	struct btrfs_root *root;
+
+	root = rb_entry(node, struct btrfs_root, rb_node);
+	if (objectid > root->objectid)
+		return 1;
+	else if (objectid < root->objectid)
+		return -1;
+	else
+		return 0;
+}
+
+int btrfs_fs_roots_compare_roots(struct rb_node *node1, struct rb_node *node2)
+{
+	struct btrfs_root *root;
+
+	root = rb_entry(node2, struct btrfs_root, rb_node);
+	return btrfs_fs_roots_compare_objectids(node1, (void *)&root->objectid);
+}
+
+struct btrfs_root *btrfs_read_fs_root(struct btrfs_fs_info *fs_info,
+				      struct btrfs_key *location)
+{
+	struct btrfs_root *root;
+	struct rb_node *node;
+	int ret;
+	u64 objectid = location->objectid;
+
+	if (location->objectid == BTRFS_ROOT_TREE_OBJECTID)
+		return fs_info->tree_root;
+	if (location->objectid == BTRFS_CHUNK_TREE_OBJECTID)
+		return fs_info->chunk_root;
+	if (location->objectid == BTRFS_CSUM_TREE_OBJECTID)
+		return fs_info->csum_root;
+	BUG_ON(location->objectid == BTRFS_TREE_RELOC_OBJECTID ||
+	       location->offset != (u64)-1);
+
+	node = rb_search(&fs_info->fs_root_tree, (void *)&objectid,
+			 btrfs_fs_roots_compare_objectids, NULL);
+	if (node)
+		return container_of(node, struct btrfs_root, rb_node);
+
+	root = btrfs_read_fs_root_no_cache(fs_info, location);
+	if (IS_ERR(root))
+		return root;
+
+	ret = rb_insert(&fs_info->fs_root_tree, &root->rb_node,
+			btrfs_fs_roots_compare_roots);
+	BUG_ON(ret);
+	return root;
+}
+
+void btrfs_free_fs_info(struct btrfs_fs_info *fs_info)
+{
+	free(fs_info->tree_root);
+	free(fs_info->chunk_root);
+	free(fs_info->csum_root);
+	free(fs_info->super_copy);
+	free(fs_info);
+}
+
+struct btrfs_fs_info *btrfs_new_fs_info(void)
+{
+	struct btrfs_fs_info *fs_info;
+
+	fs_info = calloc(1, sizeof(struct btrfs_fs_info));
+	if (!fs_info)
+		return NULL;
+
+	fs_info->tree_root = calloc(1, sizeof(struct btrfs_root));
+	fs_info->chunk_root = calloc(1, sizeof(struct btrfs_root));
+	fs_info->csum_root = calloc(1, sizeof(struct btrfs_root));
+	fs_info->super_copy = calloc(1, BTRFS_SUPER_INFO_SIZE);
+
+	if (!fs_info->tree_root || !fs_info->chunk_root ||
+	    !fs_info->csum_root || !fs_info->super_copy)
+		goto free_all;
+
+	extent_io_tree_init(&fs_info->extent_cache);
+
+	fs_info->fs_root_tree = RB_ROOT;
+	cache_tree_init(&fs_info->mapping_tree.cache_tree);
+
+	mutex_init(&fs_info->fs_mutex);
+
+	return fs_info;
+free_all:
+	btrfs_free_fs_info(fs_info);
+	return NULL;
+}
+
+static int setup_root_or_create_block(struct btrfs_fs_info *fs_info,
+				      struct btrfs_root *info_root,
+				      u64 objectid, char *str)
+{
+	struct btrfs_root *root = fs_info->tree_root;
+	int ret;
+
+	ret = find_and_setup_root(root, fs_info, objectid, info_root);
+	if (ret) {
+		error("could not setup %s tree", str);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int btrfs_setup_all_roots(struct btrfs_fs_info *fs_info)
+{
+	struct btrfs_super_block *sb = fs_info->super_copy;
+	struct btrfs_root *root;
+	struct btrfs_key key;
+	u64 root_tree_bytenr;
+	u64 generation;
+	int ret;
+
+	root = fs_info->tree_root;
+	btrfs_setup_root(root, fs_info, BTRFS_ROOT_TREE_OBJECTID);
+	generation = btrfs_super_generation(sb);
+
+	root_tree_bytenr = btrfs_super_root(sb);
+
+	root->node = read_tree_block(fs_info, root_tree_bytenr, generation);
+	if (!extent_buffer_uptodate(root->node)) {
+		fprintf(stderr, "Couldn't read tree root\n");
+		return -EIO;
+	}
+
+	ret = setup_root_or_create_block(fs_info, fs_info->csum_root,
+					 BTRFS_CSUM_TREE_OBJECTID, "csum");
+	if (ret)
+		return ret;
+	fs_info->csum_root->track_dirty = 1;
+
+	fs_info->last_trans_committed = generation;
+
+	key.objectid = BTRFS_FS_TREE_OBJECTID;
+	key.type = BTRFS_ROOT_ITEM_KEY;
+	key.offset = (u64)-1;
+	fs_info->fs_root = btrfs_read_fs_root(fs_info, &key);
+
+	if (IS_ERR(fs_info->fs_root))
+		return -EIO;
+	return 0;
+}
+
+void btrfs_release_all_roots(struct btrfs_fs_info *fs_info)
+{
+	if (fs_info->csum_root)
+		free_extent_buffer(fs_info->csum_root->node);
+	if (fs_info->tree_root)
+		free_extent_buffer(fs_info->tree_root->node);
+	if (fs_info->chunk_root)
+		free_extent_buffer(fs_info->chunk_root->node);
+}
+
+static void free_map_lookup(struct cache_extent *ce)
+{
+	struct map_lookup *map;
+
+	map = container_of(ce, struct map_lookup, ce);
+	kfree(map);
+}
+
+FREE_EXTENT_CACHE_BASED_TREE(mapping_cache, free_map_lookup);
+
+void btrfs_cleanup_all_caches(struct btrfs_fs_info *fs_info)
+{
+	free_mapping_cache_tree(&fs_info->mapping_tree.cache_tree);
+	extent_io_tree_cleanup(&fs_info->extent_cache);
+}
+
+static int btrfs_scan_fs_devices(struct blk_desc *desc,
+				 struct disk_partition *part,
+				 struct btrfs_fs_devices **fs_devices)
+{
+	u64 total_devs;
+	int ret;
+
+	if (round_up(BTRFS_SUPER_INFO_SIZE + BTRFS_SUPER_INFO_OFFSET,
+		     desc->blksz) > (part->size << desc->log2blksz)) {
+		error("superblock end %u is larger than device size " LBAFU,
+				BTRFS_SUPER_INFO_SIZE + BTRFS_SUPER_INFO_OFFSET,
+				part->size << desc->log2blksz);
+		return -EINVAL;
+	}
+
+	ret = btrfs_scan_one_device(desc, part, fs_devices, &total_devs);
+	if (ret) {
+		fprintf(stderr, "No valid Btrfs found\n");
+		return ret;
+	}
+	return 0;
+}
+
+int btrfs_check_fs_compatibility(struct btrfs_super_block *sb)
+{
+	u64 features;
+
+	features = btrfs_super_incompat_flags(sb) &
+		   ~BTRFS_FEATURE_INCOMPAT_SUPP;
+	if (features) {
+		printk("couldn't open because of unsupported "
+		       "option features (%llx).\n",
+		       (unsigned long long)features);
+		return -ENOTSUPP;
+	}
+
+	features = btrfs_super_incompat_flags(sb);
+	if (!(features & BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF)) {
+		features |= BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF;
+		btrfs_set_super_incompat_flags(sb, features);
+	}
+
+	return 0;
+}
+
+static int btrfs_setup_chunk_tree_and_device_map(struct btrfs_fs_info *fs_info)
+{
+	struct btrfs_super_block *sb = fs_info->super_copy;
+	u64 chunk_root_bytenr;
+	u64 generation;
+	int ret;
+
+	btrfs_setup_root(fs_info->chunk_root, fs_info,
+			BTRFS_CHUNK_TREE_OBJECTID);
+
+	ret = btrfs_read_sys_array(fs_info);
+	if (ret)
+		return ret;
+
+	generation = btrfs_super_chunk_root_generation(sb);
+	chunk_root_bytenr = btrfs_super_chunk_root(sb);
+
+	fs_info->chunk_root->node = read_tree_block(fs_info,
+						    chunk_root_bytenr,
+						    generation);
+	if (!extent_buffer_uptodate(fs_info->chunk_root->node)) {
+		error("cannot read chunk root");
+		return -EIO;
+	}
+
+	ret = btrfs_read_chunk_tree(fs_info);
+	if (ret) {
+		fprintf(stderr, "Couldn't read chunk tree\n");
+		return ret;
+	}
+	return 0;
+}
+
+struct btrfs_fs_info *open_ctree_fs_info(struct blk_desc *desc,
+					 struct disk_partition *part)
+{
+	struct btrfs_fs_info *fs_info;
+	struct btrfs_super_block *disk_super;
+	struct btrfs_fs_devices *fs_devices = NULL;
+	struct extent_buffer *eb;
+	int ret;
+
+	fs_info = btrfs_new_fs_info();
+	if (!fs_info) {
+		fprintf(stderr, "Failed to allocate memory for fs_info\n");
+		return NULL;
+	}
+
+	ret = btrfs_scan_fs_devices(desc, part, &fs_devices);
+	if (ret)
+		goto out;
+
+	fs_info->fs_devices = fs_devices;
+
+	ret = btrfs_open_devices(fs_devices);
+	if (ret)
+		goto out;
+
+	disk_super = fs_info->super_copy;
+	ret = btrfs_read_dev_super(desc, part, disk_super);
+	if (ret) {
+		printk("No valid btrfs found\n");
+		goto out_devices;
+	}
+
+	if (btrfs_super_flags(disk_super) & BTRFS_SUPER_FLAG_CHANGING_FSID) {
+		fprintf(stderr, "ERROR: Filesystem UUID change in progress\n");
+		goto out_devices;
+	}
+
+	ASSERT(!memcmp(disk_super->fsid, fs_devices->fsid, BTRFS_FSID_SIZE));
+	if (btrfs_fs_incompat(fs_info, METADATA_UUID))
+		ASSERT(!memcmp(disk_super->metadata_uuid,
+			       fs_devices->metadata_uuid, BTRFS_FSID_SIZE));
+
+	fs_info->sectorsize = btrfs_super_sectorsize(disk_super);
+	fs_info->nodesize = btrfs_super_nodesize(disk_super);
+	fs_info->stripesize = btrfs_super_stripesize(disk_super);
+
+	ret = btrfs_check_fs_compatibility(fs_info->super_copy);
+	if (ret)
+		goto out_devices;
+
+	ret = btrfs_setup_chunk_tree_and_device_map(fs_info);
+	if (ret)
+		goto out_chunk;
+
+	/* Chunk tree root is unable to read, return directly */
+	if (!fs_info->chunk_root)
+		return fs_info;
+
+	eb = fs_info->chunk_root->node;
+	read_extent_buffer(eb, fs_info->chunk_tree_uuid,
+			   btrfs_header_chunk_tree_uuid(eb),
+			   BTRFS_UUID_SIZE);
+
+	ret = btrfs_setup_all_roots(fs_info);
+	if (ret)
+		goto out_chunk;
+
+	return fs_info;
+
+out_chunk:
+	btrfs_release_all_roots(fs_info);
+	btrfs_cleanup_all_caches(fs_info);
+out_devices:
+	btrfs_close_devices(fs_devices);
+out:
+	btrfs_free_fs_info(fs_info);
+	return NULL;
+}
+
+int close_ctree_fs_info(struct btrfs_fs_info *fs_info)
+{
+	int ret;
+	int err = 0;
+
+	free_fs_roots_tree(&fs_info->fs_root_tree);
+
+	btrfs_release_all_roots(fs_info);
+	ret = btrfs_close_devices(fs_info->fs_devices);
+	btrfs_cleanup_all_caches(fs_info);
+	btrfs_free_fs_info(fs_info);
+	if (!err)
+		err = ret;
+	return err;
+}
+
+int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid)
+{
+	int ret;
+
+	ret = extent_buffer_uptodate(buf);
+	if (!ret)
+		return ret;
+
+	ret = verify_parent_transid(&buf->fs_info->extent_cache, buf,
+				    parent_transid, 1);
+	return !ret;
+}
+
+int btrfs_set_buffer_uptodate(struct extent_buffer *eb)
+{
+	return set_extent_buffer_uptodate(eb);
+}

diff --git a/fs/btrfs/disk-io.h b/fs/btrfs/disk-io.h
new file mode 100644
index 0000000..a3479120
--- /dev/null
+++ b/fs/btrfs/disk-io.h

@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifndef __BTRFS_DISK_IO_H__
+#define __BTRFS_DISK_IO_H__
+
+#include <linux/sizes.h>
+#include <fs_internal.h>
+#include "ctree.h"
+#include "disk-io.h"
+
+#define BTRFS_SUPER_INFO_OFFSET SZ_64K
+#define BTRFS_SUPER_INFO_SIZE	SZ_4K
+
+/* From btrfs-progs */
+int read_whole_eb(struct btrfs_fs_info *info, struct extent_buffer *eb, int mirror);
+struct extent_buffer* read_tree_block(struct btrfs_fs_info *fs_info, u64 bytenr,
+		u64 parent_transid);
+
+int read_extent_data(struct btrfs_fs_info *fs_info, char *data, u64 logical,
+		     u64 *len, int mirror);
+struct extent_buffer* btrfs_find_create_tree_block(
+		struct btrfs_fs_info *fs_info, u64 bytenr);
+struct extent_buffer *btrfs_find_tree_block(struct btrfs_fs_info *fs_info,
+					    u64 bytenr, u32 blocksize);
+struct btrfs_root *btrfs_read_fs_root_no_cache(struct btrfs_fs_info *fs_info,
+					       struct btrfs_key *location);
+struct btrfs_root *btrfs_read_fs_root(struct btrfs_fs_info *fs_info,
+				      struct btrfs_key *location);
+
+void btrfs_setup_root(struct btrfs_root *root, struct btrfs_fs_info *fs_info,
+		      u64 objectid);
+
+void btrfs_free_fs_info(struct btrfs_fs_info *fs_info);
+struct btrfs_fs_info *btrfs_new_fs_info(void);
+int btrfs_check_fs_compatibility(struct btrfs_super_block *sb);
+int btrfs_setup_all_roots(struct btrfs_fs_info *fs_info);
+void btrfs_release_all_roots(struct btrfs_fs_info *fs_info);
+void btrfs_cleanup_all_caches(struct btrfs_fs_info *fs_info);
+
+struct btrfs_fs_info *open_ctree_fs_info(struct blk_desc *desc,
+					 struct disk_partition *part);
+int close_ctree_fs_info(struct btrfs_fs_info *fs_info);
+
+int btrfs_read_dev_super(struct blk_desc *desc, struct disk_partition *part,
+			 struct btrfs_super_block *sb);
+int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid);
+int btrfs_set_buffer_uptodate(struct extent_buffer *buf);
+int btrfs_csum_data(u16 csum_type, const u8 *data, u8 *out, size_t len);
+int csum_tree_block_size(struct extent_buffer *buf, u16 csum_sectorsize,
+			 int verify, u16 csum_type);
+#endif

diff --git a/fs/btrfs/extent-cache.c b/fs/btrfs/extent-cache.c
new file mode 100644
index 0000000..bc8cf3a
--- /dev/null
+++ b/fs/btrfs/extent-cache.c

@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Crossported from the same named file of btrfs-progs.
+ *
+ * Minor modification to include headers.
+ */
+#include <linux/kernel.h>
+#include <linux/rbtree.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <stdlib.h>
+#include "extent-cache.h"
+#include "common/rbtree-utils.h"
+
+struct cache_extent_search_range {
+	u64 objectid;
+	u64 start;
+	u64 size;
+};
+
+static int cache_tree_comp_range(struct rb_node *node, void *data)
+{
+	struct cache_extent *entry;
+	struct cache_extent_search_range *range;
+
+	range = (struct cache_extent_search_range *)data;
+	entry = rb_entry(node, struct cache_extent, rb_node);
+
+	if (entry->start + entry->size <= range->start)
+		return 1;
+	else if (range->start + range->size <= entry->start)
+		return -1;
+	else
+		return 0;
+}
+
+static int cache_tree_comp_nodes(struct rb_node *node1, struct rb_node *node2)
+{
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	entry = rb_entry(node2, struct cache_extent, rb_node);
+	range.start = entry->start;
+	range.size = entry->size;
+
+	return cache_tree_comp_range(node1, (void *)&range);
+}
+
+static int cache_tree_comp_range2(struct rb_node *node, void *data)
+{
+	struct cache_extent *entry;
+	struct cache_extent_search_range *range;
+
+	range = (struct cache_extent_search_range *)data;
+	entry = rb_entry(node, struct cache_extent, rb_node);
+
+	if (entry->objectid < range->objectid)
+		return 1;
+	else if (entry->objectid > range->objectid)
+		return -1;
+	else if (entry->start + entry->size <= range->start)
+		return 1;
+	else if (range->start + range->size <= entry->start)
+		return -1;
+	else
+		return 0;
+}
+
+static int cache_tree_comp_nodes2(struct rb_node *node1, struct rb_node *node2)
+{
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	entry = rb_entry(node2, struct cache_extent, rb_node);
+	range.objectid = entry->objectid;
+	range.start = entry->start;
+	range.size = entry->size;
+
+	return cache_tree_comp_range2(node1, (void *)&range);
+}
+
+void cache_tree_init(struct cache_tree *tree)
+{
+	tree->root = RB_ROOT;
+}
+
+static struct cache_extent *alloc_cache_extent(u64 start, u64 size)
+{
+	struct cache_extent *pe = malloc(sizeof(*pe));
+
+	if (!pe)
+		return pe;
+
+	pe->objectid = 0;
+	pe->start = start;
+	pe->size = size;
+	return pe;
+}
+
+int add_cache_extent(struct cache_tree *tree, u64 start, u64 size)
+{
+	struct cache_extent *pe = alloc_cache_extent(start, size);
+	int ret;
+
+	if (!pe)
+		return -ENOMEM;
+
+	ret = insert_cache_extent(tree, pe);
+	if (ret)
+		free(pe);
+
+	return ret;
+}
+
+int insert_cache_extent(struct cache_tree *tree, struct cache_extent *pe)
+{
+	return rb_insert(&tree->root, &pe->rb_node, cache_tree_comp_nodes);
+}
+
+int insert_cache_extent2(struct cache_tree *tree, struct cache_extent *pe)
+{
+	return rb_insert(&tree->root, &pe->rb_node, cache_tree_comp_nodes2);
+}
+
+struct cache_extent *lookup_cache_extent(struct cache_tree *tree,
+					 u64 start, u64 size)
+{
+	struct rb_node *node;
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	range.start = start;
+	range.size = size;
+	node = rb_search(&tree->root, &range, cache_tree_comp_range, NULL);
+	if (!node)
+		return NULL;
+
+	entry = rb_entry(node, struct cache_extent, rb_node);
+	return entry;
+}
+
+struct cache_extent *lookup_cache_extent2(struct cache_tree *tree,
+					 u64 objectid, u64 start, u64 size)
+{
+	struct rb_node *node;
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	range.objectid = objectid;
+	range.start = start;
+	range.size = size;
+	node = rb_search(&tree->root, &range, cache_tree_comp_range2, NULL);
+	if (!node)
+		return NULL;
+
+	entry = rb_entry(node, struct cache_extent, rb_node);
+	return entry;
+}
+
+struct cache_extent *search_cache_extent(struct cache_tree *tree, u64 start)
+{
+	struct rb_node *next;
+	struct rb_node *node;
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	range.start = start;
+	range.size = 1;
+	node = rb_search(&tree->root, &range, cache_tree_comp_range, &next);
+	if (!node)
+		node = next;
+	if (!node)
+		return NULL;
+
+	entry = rb_entry(node, struct cache_extent, rb_node);
+	return entry;
+}
+
+struct cache_extent *search_cache_extent2(struct cache_tree *tree,
+					 u64 objectid, u64 start)
+{
+	struct rb_node *next;
+	struct rb_node *node;
+	struct cache_extent *entry;
+	struct cache_extent_search_range range;
+
+	range.objectid = objectid;
+	range.start = start;
+	range.size = 1;
+	node = rb_search(&tree->root, &range, cache_tree_comp_range2, &next);
+	if (!node)
+		node = next;
+	if (!node)
+		return NULL;
+
+	entry = rb_entry(node, struct cache_extent, rb_node);
+	return entry;
+}
+
+struct cache_extent *first_cache_extent(struct cache_tree *tree)
+{
+	struct rb_node *node = rb_first(&tree->root);
+
+	if (!node)
+		return NULL;
+	return rb_entry(node, struct cache_extent, rb_node);
+}
+
+struct cache_extent *last_cache_extent(struct cache_tree *tree)
+{
+	struct rb_node *node = rb_last(&tree->root);
+
+	if (!node)
+		return NULL;
+	return rb_entry(node, struct cache_extent, rb_node);
+}
+
+struct cache_extent *prev_cache_extent(struct cache_extent *pe)
+{
+	struct rb_node *node = rb_prev(&pe->rb_node);
+
+	if (!node)
+		return NULL;
+	return rb_entry(node, struct cache_extent, rb_node);
+}
+
+struct cache_extent *next_cache_extent(struct cache_extent *pe)
+{
+	struct rb_node *node = rb_next(&pe->rb_node);
+
+	if (!node)
+		return NULL;
+	return rb_entry(node, struct cache_extent, rb_node);
+}
+
+void remove_cache_extent(struct cache_tree *tree, struct cache_extent *pe)
+{
+	rb_erase(&pe->rb_node, &tree->root);
+}
+
+void cache_tree_free_extents(struct cache_tree *tree,
+			     free_cache_extent free_func)
+{
+	struct cache_extent *ce;
+
+	while ((ce = first_cache_extent(tree))) {
+		remove_cache_extent(tree, ce);
+		free_func(ce);
+	}
+}
+
+static void free_extent_cache(struct cache_extent *pe)
+{
+	free(pe);
+}
+
+void free_extent_cache_tree(struct cache_tree *tree)
+{
+	cache_tree_free_extents(tree, free_extent_cache);
+}
+
+int add_merge_cache_extent(struct cache_tree *tree, u64 start, u64 size)
+{
+	struct cache_extent *cache;
+	struct cache_extent *next = NULL;
+	struct cache_extent *prev = NULL;
+	int next_merged = 0;
+	int prev_merged = 0;
+	int ret = 0;
+
+	if (cache_tree_empty(tree))
+		goto insert;
+
+	cache = search_cache_extent(tree, start);
+	if (!cache) {
+		/*
+		 * Either the tree is completely empty, or the no range after
+		 * start.
+		 * Either way, the last cache_extent should be prev.
+		 */
+		prev = last_cache_extent(tree);
+	} else if (start <= cache->start) {
+		next = cache;
+		prev = prev_cache_extent(cache);
+	} else {
+		prev = cache;
+		next = next_cache_extent(cache);
+	}
+
+	/*
+	 * Ensure the range to be inserted won't cover with existings
+	 * Or we will need extra loop to do merge
+	 */
+	BUG_ON(next && start + size > next->start);
+	BUG_ON(prev && prev->start + prev->size > start);
+
+	if (next && start + size == next->start) {
+		next_merged = 1;
+		next->size = next->start + next->size - start;
+		next->start = start;
+	}
+	if (prev && prev->start + prev->size == start) {
+		prev_merged = 1;
+		if (next_merged) {
+			next->size = next->start + next->size - prev->start;
+			next->start = prev->start;
+			remove_cache_extent(tree, prev);
+			free(prev);
+		} else {
+			prev->size = start + size - prev->start;
+		}
+	}
+insert:
+	if (!prev_merged && !next_merged)
+		ret = add_cache_extent(tree, start, size);
+	return ret;
+}

diff --git a/fs/btrfs/extent-cache.h b/fs/btrfs/extent-cache.h
new file mode 100644
index 0000000..2fee81a
--- /dev/null
+++ b/fs/btrfs/extent-cache.h

@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Crossported from the same named file of btrfs-progs.
+ *
+ * Minor modification to include headers.
+ */
+#ifndef __BTRFS_EXTENT_CACHE_H__
+#define __BTRFS_EXTENT_CACHE_H__
+
+#include <linux/rbtree.h>
+#include <linux/types.h>
+
+struct cache_tree {
+	struct rb_root root;
+};
+
+struct cache_extent {
+	struct rb_node rb_node;
+	u64 objectid;
+	u64 start;
+	u64 size;
+};
+
+void cache_tree_init(struct cache_tree *tree);
+
+struct cache_extent *first_cache_extent(struct cache_tree *tree);
+struct cache_extent *last_cache_extent(struct cache_tree *tree);
+struct cache_extent *prev_cache_extent(struct cache_extent *pe);
+struct cache_extent *next_cache_extent(struct cache_extent *pe);
+
+/*
+ * Find a cache_extent which covers start.
+ *
+ * If not found, return next cache_extent if possible.
+ */
+struct cache_extent *search_cache_extent(struct cache_tree *tree, u64 start);
+
+/*
+ * Find a cache_extent which restrictly covers start.
+ *
+ * If not found, return NULL.
+ */
+struct cache_extent *lookup_cache_extent(struct cache_tree *tree,
+					 u64 start, u64 size);
+
+/*
+ * Add an non-overlap extent into cache tree
+ *
+ * If [start, start+size) overlap with existing one, it will return -EEXIST.
+ */
+int add_cache_extent(struct cache_tree *tree, u64 start, u64 size);
+
+/*
+ * Same with add_cache_extent, but with cache_extent strcut.
+ */
+int insert_cache_extent(struct cache_tree *tree, struct cache_extent *pe);
+void remove_cache_extent(struct cache_tree *tree, struct cache_extent *pe);
+
+static inline int cache_tree_empty(struct cache_tree *tree)
+{
+	return RB_EMPTY_ROOT(&tree->root);
+}
+
+typedef void (*free_cache_extent)(struct cache_extent *pe);
+
+void cache_tree_free_extents(struct cache_tree *tree,
+			     free_cache_extent free_func);
+
+#define FREE_EXTENT_CACHE_BASED_TREE(name, free_func)		\
+static void free_##name##_tree(struct cache_tree *tree)		\
+{								\
+	cache_tree_free_extents(tree, free_func);		\
+}
+
+void free_extent_cache_tree(struct cache_tree *tree);
+
+/*
+ * Search a cache_extent with same objectid, and covers start.
+ *
+ * If not found, return next if possible.
+ */
+struct cache_extent *search_cache_extent2(struct cache_tree *tree,
+					  u64 objectid, u64 start);
+/*
+ * Search a cache_extent with same objectid, and covers the range
+ * [start, start + size)
+ *
+ * If not found, return next cache_extent if possible.
+ */
+struct cache_extent *lookup_cache_extent2(struct cache_tree *tree,
+					  u64 objectid, u64 start, u64 size);
+int insert_cache_extent2(struct cache_tree *tree, struct cache_extent *pe);
+
+/*
+ * Insert a cache_extent range [start, start + size).
+ *
+ * This function may merge with existing cache_extent.
+ * NOTE: caller must ensure the inserted range won't cover with any existing
+ * range.
+ */
+int add_merge_cache_extent(struct cache_tree *tree, u64 start, u64 size);
+
+#endif

diff --git a/fs/btrfs/extent-io.c b/fs/btrfs/extent-io.c
index 2e4599c..774e29e 100644
--- a/fs/btrfs/extent-io.c
+++ b/fs/btrfs/extent-io.c

@@ -5,122 +5,805 @@
  * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
  */
 
-#include "btrfs.h"
+#include <linux/kernel.h>
+#include <linux/bug.h>
 #include <malloc.h>
 #include <memalign.h>
+#include "btrfs.h"
+#include "ctree.h"
+#include "extent-io.h"
+#include "disk-io.h"
+
+void extent_io_tree_init(struct extent_io_tree *tree)
+{
+	cache_tree_init(&tree->state);
+	cache_tree_init(&tree->cache);
+	tree->cache_size = 0;
+}
+
+static struct extent_state *alloc_extent_state(void)
+{
+	struct extent_state *state;
+
+	state = malloc(sizeof(*state));
+	if (!state)
+		return NULL;
+	state->cache_node.objectid = 0;
+	state->refs = 1;
+	state->state = 0;
+	state->xprivate = 0;
+	return state;
+}
+
+static void btrfs_free_extent_state(struct extent_state *state)
+{
+	state->refs--;
+	BUG_ON(state->refs < 0);
+	if (state->refs == 0)
+		free(state);
+}
+
+static void free_extent_state_func(struct cache_extent *cache)
+{
+	struct extent_state *es;
+
+	es = container_of(cache, struct extent_state, cache_node);
+	btrfs_free_extent_state(es);
+}
 
-u64 btrfs_read_extent_inline(struct btrfs_path *path,
-			     struct btrfs_file_extent_item *extent, u64 offset,
-			     u64 size, char *out)
+static void free_extent_buffer_final(struct extent_buffer *eb);
+void extent_io_tree_cleanup(struct extent_io_tree *tree)
 {
-	u32 clen, dlen, orig_size = size, res;
-	const char *cbuf;
-	char *dbuf;
-	const int data_off = offsetof(struct btrfs_file_extent_item,
-				      disk_bytenr);
+	cache_tree_free_extents(&tree->state, free_extent_state_func);
+}
 
-	clen = btrfs_path_item_size(path) - data_off;
-	cbuf = (const char *) extent + data_off;
-	dlen = extent->ram_bytes;
+static inline void update_extent_state(struct extent_state *state)
+{
+	state->cache_node.start = state->start;
+	state->cache_node.size = state->end + 1 - state->start;
+}
 
-	if (offset > dlen)
-		return -1ULL;
+/*
+ * Utility function to look for merge candidates inside a given range.
+ * Any extents with matching state are merged together into a single
+ * extent in the tree. Extents with EXTENT_IO in their state field are
+ * not merged
+ */
+static int merge_state(struct extent_io_tree *tree,
+		       struct extent_state *state)
+{
+	struct extent_state *other;
+	struct cache_extent *other_node;
 
-	if (size > dlen - offset)
-		size = dlen - offset;
+	if (state->state & EXTENT_IOBITS)
+		return 0;
 
-	if (extent->compression == BTRFS_COMPRESS_NONE) {
-		memcpy(out, cbuf + offset, size);
-		return size;
+	other_node = prev_cache_extent(&state->cache_node);
+	if (other_node) {
+		other = container_of(other_node, struct extent_state,
+				     cache_node);
+		if (other->end == state->start - 1 &&
+		    other->state == state->state) {
+			state->start = other->start;
+			update_extent_state(state);
+			remove_cache_extent(&tree->state, &other->cache_node);
+			btrfs_free_extent_state(other);
+		}
 	}
+	other_node = next_cache_extent(&state->cache_node);
+	if (other_node) {
+		other = container_of(other_node, struct extent_state,
+				     cache_node);
+		if (other->start == state->end + 1 &&
+		    other->state == state->state) {
+			other->start = state->start;
+			update_extent_state(other);
+			remove_cache_extent(&tree->state, &state->cache_node);
+			btrfs_free_extent_state(state);
+		}
+	}
+	return 0;
+}
+
+/*
+ * insert an extent_state struct into the tree.  'bits' are set on the
+ * struct before it is inserted.
+ */
+static int insert_state(struct extent_io_tree *tree,
+			struct extent_state *state, u64 start, u64 end,
+			int bits)
+{
+	int ret;
+
+	BUG_ON(end < start);
+	state->state |= bits;
+	state->start = start;
+	state->end = end;
+	update_extent_state(state);
+	ret = insert_cache_extent(&tree->state, &state->cache_node);
+	BUG_ON(ret);
+	merge_state(tree, state);
+	return 0;
+}
 
-	if (dlen > orig_size) {
-		dbuf = malloc(dlen);
-		if (!dbuf)
-			return -1ULL;
+/*
+ * split a given extent state struct in two, inserting the preallocated
+ * struct 'prealloc' as the newly created second half.  'split' indicates an
+ * offset inside 'orig' where it should be split.
+ */
+static int split_state(struct extent_io_tree *tree, struct extent_state *orig,
+		       struct extent_state *prealloc, u64 split)
+{
+	int ret;
+	prealloc->start = orig->start;
+	prealloc->end = split - 1;
+	prealloc->state = orig->state;
+	update_extent_state(prealloc);
+	orig->start = split;
+	update_extent_state(orig);
+	ret = insert_cache_extent(&tree->state, &prealloc->cache_node);
+	BUG_ON(ret);
+	return 0;
+}
+
+/*
+ * clear some bits on a range in the tree.
+ */
+static int clear_state_bit(struct extent_io_tree *tree,
+			    struct extent_state *state, int bits)
+{
+	int ret = state->state & bits;
+
+	state->state &= ~bits;
+	if (state->state == 0) {
+		remove_cache_extent(&tree->state, &state->cache_node);
+		btrfs_free_extent_state(state);
 	} else {
-		dbuf = out;
+		merge_state(tree, state);
+	}
+	return ret;
+}
+
+/*
+ * extent_buffer_bitmap_set - set an area of a bitmap
+ * @eb: the extent buffer
+ * @start: offset of the bitmap item in the extent buffer
+ * @pos: bit number of the first bit
+ * @len: number of bits to set
+ */
+void extent_buffer_bitmap_set(struct extent_buffer *eb, unsigned long start,
+			      unsigned long pos, unsigned long len)
+{
+	u8 *p = (u8 *)eb->data + start + BIT_BYTE(pos);
+	const unsigned int size = pos + len;
+	int bits_to_set = BITS_PER_BYTE - (pos % BITS_PER_BYTE);
+	u8 mask_to_set = BITMAP_FIRST_BYTE_MASK(pos);
+
+	while (len >= bits_to_set) {
+		*p |= mask_to_set;
+		len -= bits_to_set;
+		bits_to_set = BITS_PER_BYTE;
+		mask_to_set = ~0;
+		p++;
+	}
+	if (len) {
+		mask_to_set &= BITMAP_LAST_BYTE_MASK(size);
+		*p |= mask_to_set;
+	}
+}
+
+/*
+ * extent_buffer_bitmap_clear - clear an area of a bitmap
+ * @eb: the extent buffer
+ * @start: offset of the bitmap item in the extent buffer
+ * @pos: bit number of the first bit
+ * @len: number of bits to clear
+ */
+void extent_buffer_bitmap_clear(struct extent_buffer *eb, unsigned long start,
+				unsigned long pos, unsigned long len)
+{
+	u8 *p = (u8 *)eb->data + start + BIT_BYTE(pos);
+	const unsigned int size = pos + len;
+	int bits_to_clear = BITS_PER_BYTE - (pos % BITS_PER_BYTE);
+	u8 mask_to_clear = BITMAP_FIRST_BYTE_MASK(pos);
+
+	while (len >= bits_to_clear) {
+		*p &= ~mask_to_clear;
+		len -= bits_to_clear;
+		bits_to_clear = BITS_PER_BYTE;
+		mask_to_clear = ~0;
+		p++;
+	}
+	if (len) {
+		mask_to_clear &= BITMAP_LAST_BYTE_MASK(size);
+		*p &= ~mask_to_clear;
+	}
+}
+
+/*
+ * clear some bits on a range in the tree.
+ */
+int clear_extent_bits(struct extent_io_tree *tree, u64 start, u64 end, int bits)
+{
+	struct extent_state *state;
+	struct extent_state *prealloc = NULL;
+	struct cache_extent *node;
+	u64 last_end;
+	int err;
+	int set = 0;
+
+again:
+	if (!prealloc) {
+		prealloc = alloc_extent_state();
+		if (!prealloc)
+			return -ENOMEM;
+	}
+
+	/*
+	 * this search will find the extents that end after
+	 * our range starts
+	 */
+	node = search_cache_extent(&tree->state, start);
+	if (!node)
+		goto out;
+	state = container_of(node, struct extent_state, cache_node);
+	if (state->start > end)
+		goto out;
+	last_end = state->end;
+
+	/*
+	 *     | ---- desired range ---- |
+	 *  | state | or
+	 *  | ------------- state -------------- |
+	 *
+	 * We need to split the extent we found, and may flip
+	 * bits on second half.
+	 *
+	 * If the extent we found extends past our range, we
+	 * just split and search again.  It'll get split again
+	 * the next time though.
+	 *
+	 * If the extent we found is inside our range, we clear
+	 * the desired bit on it.
+	 */
+	if (state->start < start) {
+		err = split_state(tree, state, prealloc, start);
+		BUG_ON(err == -EEXIST);
+		prealloc = NULL;
+		if (err)
+			goto out;
+		if (state->end <= end) {
+			set |= clear_state_bit(tree, state, bits);
+			if (last_end == (u64)-1)
+				goto out;
+			start = last_end + 1;
+		} else {
+			start = state->start;
+		}
+		goto search_again;
+	}
+	/*
+	 * | ---- desired range ---- |
+	 *                        | state |
+	 * We need to split the extent, and clear the bit
+	 * on the first half
+	 */
+	if (state->start <= end && state->end > end) {
+		err = split_state(tree, state, prealloc, end + 1);
+		BUG_ON(err == -EEXIST);
+
+		set |= clear_state_bit(tree, prealloc, bits);
+		prealloc = NULL;
+		goto out;
+	}
+
+	start = state->end + 1;
+	set |= clear_state_bit(tree, state, bits);
+	if (last_end == (u64)-1)
+		goto out;
+	start = last_end + 1;
+	goto search_again;
+out:
+	if (prealloc)
+		btrfs_free_extent_state(prealloc);
+	return set;
+
+search_again:
+	if (start > end)
+		goto out;
+	goto again;
+}
+
+/*
+ * set some bits on a range in the tree.
+ */
+int set_extent_bits(struct extent_io_tree *tree, u64 start, u64 end, int bits)
+{
+	struct extent_state *state;
+	struct extent_state *prealloc = NULL;
+	struct cache_extent *node;
+	int err = 0;
+	u64 last_start;
+	u64 last_end;
+again:
+	if (!prealloc) {
+		prealloc = alloc_extent_state();
+		if (!prealloc)
+			return -ENOMEM;
+	}
+
+	/*
+	 * this search will find the extents that end after
+	 * our range starts
+	 */
+	node = search_cache_extent(&tree->state, start);
+	if (!node) {
+		err = insert_state(tree, prealloc, start, end, bits);
+		BUG_ON(err == -EEXIST);
+		prealloc = NULL;
+		goto out;
+	}
+
+	state = container_of(node, struct extent_state, cache_node);
+	last_start = state->start;
+	last_end = state->end;
+
+	/*
+	 * | ---- desired range ---- |
+	 * | state |
+	 *
+	 * Just lock what we found and keep going
+	 */
+	if (state->start == start && state->end <= end) {
+		state->state |= bits;
+		merge_state(tree, state);
+		if (last_end == (u64)-1)
+			goto out;
+		start = last_end + 1;
+		goto search_again;
+	}
+	/*
+	 *     | ---- desired range ---- |
+	 * | state |
+	 *   or
+	 * | ------------- state -------------- |
+	 *
+	 * We need to split the extent we found, and may flip bits on
+	 * second half.
+	 *
+	 * If the extent we found extends past our
+	 * range, we just split and search again.  It'll get split
+	 * again the next time though.
+	 *
+	 * If the extent we found is inside our range, we set the
+	 * desired bit on it.
+	 */
+	if (state->start < start) {
+		err = split_state(tree, state, prealloc, start);
+		BUG_ON(err == -EEXIST);
+		prealloc = NULL;
+		if (err)
+			goto out;
+		if (state->end <= end) {
+			state->state |= bits;
+			start = state->end + 1;
+			merge_state(tree, state);
+			if (last_end == (u64)-1)
+				goto out;
+			start = last_end + 1;
+		} else {
+			start = state->start;
+		}
+		goto search_again;
+	}
+	/*
+	 * | ---- desired range ---- |
+	 *     | state | or               | state |
+	 *
+	 * There's a hole, we need to insert something in it and
+	 * ignore the extent we found.
+	 */
+	if (state->start > start) {
+		u64 this_end;
+		if (end < last_start)
+			this_end = end;
+		else
+			this_end = last_start -1;
+		err = insert_state(tree, prealloc, start, this_end,
+				bits);
+		BUG_ON(err == -EEXIST);
+		prealloc = NULL;
+		if (err)
+			goto out;
+		start = this_end + 1;
+		goto search_again;
+	}
+	/*
+	 * | ---- desired range ---- |
+	 * | ---------- state ---------- |
+	 * We need to split the extent, and set the bit
+	 * on the first half
+	 */
+	err = split_state(tree, state, prealloc, end + 1);
+	BUG_ON(err == -EEXIST);
+
+	state->state |= bits;
+	merge_state(tree, prealloc);
+	prealloc = NULL;
+out:
+	if (prealloc)
+		btrfs_free_extent_state(prealloc);
+	return err;
+search_again:
+	if (start > end)
+		goto out;
+	goto again;
+}
+
+int set_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end)
+{
+	return set_extent_bits(tree, start, end, EXTENT_DIRTY);
+}
+
+int clear_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end)
+{
+	return clear_extent_bits(tree, start, end, EXTENT_DIRTY);
+}
+
+int find_first_extent_bit(struct extent_io_tree *tree, u64 start,
+			  u64 *start_ret, u64 *end_ret, int bits)
+{
+	struct cache_extent *node;
+	struct extent_state *state;
+	int ret = 1;
+
+	/*
+	 * this search will find all the extents that end after
+	 * our range starts.
+	 */
+	node = search_cache_extent(&tree->state, start);
+	if (!node)
+		goto out;
+
+	while(1) {
+		state = container_of(node, struct extent_state, cache_node);
+		if (state->end >= start && (state->state & bits)) {
+			*start_ret = state->start;
+			*end_ret = state->end;
+			ret = 0;
+			break;
+		}
+		node = next_cache_extent(node);
+		if (!node)
+			break;
+	}
+out:
+	return ret;
+}
+
+int test_range_bit(struct extent_io_tree *tree, u64 start, u64 end,
+		   int bits, int filled)
+{
+	struct extent_state *state = NULL;
+	struct cache_extent *node;
+	int bitset = 0;
+
+	node = search_cache_extent(&tree->state, start);
+	while (node && start <= end) {
+		state = container_of(node, struct extent_state, cache_node);
+
+		if (filled && state->start > start) {
+			bitset = 0;
+			break;
+		}
+		if (state->start > end)
+			break;
+		if (state->state & bits) {
+			bitset = 1;
+			if (!filled)
+				break;
+		} else if (filled) {
+			bitset = 0;
+			break;
+		}
+		start = state->end + 1;
+		if (start > end)
+			break;
+		node = next_cache_extent(node);
+		if (!node) {
+			if (filled)
+				bitset = 0;
+			break;
+		}
+	}
+	return bitset;
+}
+
+int set_state_private(struct extent_io_tree *tree, u64 start, u64 private)
+{
+	struct cache_extent *node;
+	struct extent_state *state;
+	int ret = 0;
+
+	node = search_cache_extent(&tree->state, start);
+	if (!node) {
+		ret = -ENOENT;
+		goto out;
+	}
+	state = container_of(node, struct extent_state, cache_node);
+	if (state->start != start) {
+		ret = -ENOENT;
+		goto out;
+	}
+	state->xprivate = private;
+out:
+	return ret;
+}
+
+int get_state_private(struct extent_io_tree *tree, u64 start, u64 *private)
+{
+	struct cache_extent *node;
+	struct extent_state *state;
+	int ret = 0;
+
+	node = search_cache_extent(&tree->state, start);
+	if (!node) {
+		ret = -ENOENT;
+		goto out;
 	}
+	state = container_of(node, struct extent_state, cache_node);
+	if (state->start != start) {
+		ret = -ENOENT;
+		goto out;
+	}
+	*private = state->xprivate;
+out:
+	return ret;
+}
 
-	res = btrfs_decompress(extent->compression, cbuf, clen, dbuf, dlen);
-	if (res == -1 || res != dlen)
-		goto err;
+static struct extent_buffer *__alloc_extent_buffer(struct btrfs_fs_info *info,
+						   u64 bytenr, u32 blocksize)
+{
+	struct extent_buffer *eb;
+
+	eb = calloc(1, sizeof(struct extent_buffer));
+	if (!eb)
+		return NULL;
+	eb->data = malloc_cache_aligned(blocksize);
+	if (!eb->data) {
+		free(eb);
+		return NULL;
+	}
+
+	eb->start = bytenr;
+	eb->len = blocksize;
+	eb->refs = 1;
+	eb->flags = 0;
+	eb->cache_node.start = bytenr;
+	eb->cache_node.size = blocksize;
+	eb->fs_info = info;
+	memset_extent_buffer(eb, 0, 0, blocksize);
+
+	return eb;
+}
+
+struct extent_buffer *btrfs_clone_extent_buffer(struct extent_buffer *src)
+{
+	struct extent_buffer *new;
+
+	new = __alloc_extent_buffer(src->fs_info, src->start, src->len);
+	if (!new)
+		return NULL;
+
+	copy_extent_buffer(new, src, 0, 0, src->len);
+	new->flags |= EXTENT_BUFFER_DUMMY;
+
+	return new;
+}
+
+static void free_extent_buffer_final(struct extent_buffer *eb)
+{
+	BUG_ON(eb->refs);
+	if (!(eb->flags & EXTENT_BUFFER_DUMMY)) {
+		struct extent_io_tree *tree = &eb->fs_info->extent_cache;
+
+		remove_cache_extent(&tree->cache, &eb->cache_node);
+		BUG_ON(tree->cache_size < eb->len);
+		tree->cache_size -= eb->len;
+	}
+	free(eb->data);
+	free(eb);
+}
+
+static void free_extent_buffer_internal(struct extent_buffer *eb, bool free_now)
+{
+	if (!eb || IS_ERR(eb))
+		return;
 
-	if (dlen > orig_size) {
-		memcpy(out, dbuf + offset, size);
-		free(dbuf);
-	} else if (offset) {
-		memmove(out, dbuf + offset, size);
+	eb->refs--;
+	BUG_ON(eb->refs < 0);
+	if (eb->refs == 0) {
+		if (eb->flags & EXTENT_DIRTY) {
+			error(
+			"dirty eb leak (aborted trans): start %llu len %u",
+				eb->start, eb->len);
+		}
+		if (eb->flags & EXTENT_BUFFER_DUMMY || free_now)
+			free_extent_buffer_final(eb);
 	}
+}
 
-	return size;
+void free_extent_buffer(struct extent_buffer *eb)
+{
+	free_extent_buffer_internal(eb, 1);
+}
+
+struct extent_buffer *find_extent_buffer(struct extent_io_tree *tree,
+					 u64 bytenr, u32 blocksize)
+{
+	struct extent_buffer *eb = NULL;
+	struct cache_extent *cache;
 
-err:
-	if (dlen > orig_size)
-		free(dbuf);
-	return -1ULL;
+	cache = lookup_cache_extent(&tree->cache, bytenr, blocksize);
+	if (cache && cache->start == bytenr &&
+	    cache->size == blocksize) {
+		eb = container_of(cache, struct extent_buffer, cache_node);
+		eb->refs++;
+	}
+	return eb;
 }
 
-u64 btrfs_read_extent_reg(struct btrfs_path *path,
-			  struct btrfs_file_extent_item *extent, u64 offset,
-			  u64 size, char *out)
+struct extent_buffer *find_first_extent_buffer(struct extent_io_tree *tree,
+					       u64 start)
 {
-	u64 physical, clen, dlen, orig_size = size;
-	u32 res;
-	char *cbuf, *dbuf;
+	struct extent_buffer *eb = NULL;
+	struct cache_extent *cache;
 
-	clen = extent->disk_num_bytes;
-	dlen = extent->num_bytes;
+	cache = search_cache_extent(&tree->cache, start);
+	if (cache) {
+		eb = container_of(cache, struct extent_buffer, cache_node);
+		eb->refs++;
+	}
+	return eb;
+}
 
-	if (offset > dlen)
-		return -1ULL;
+struct extent_buffer *alloc_extent_buffer(struct btrfs_fs_info *fs_info,
+					  u64 bytenr, u32 blocksize)
+{
+	struct extent_buffer *eb;
+	struct extent_io_tree *tree = &fs_info->extent_cache;
+	struct cache_extent *cache;
 
-	if (size > dlen - offset)
-		size = dlen - offset;
+	cache = lookup_cache_extent(&tree->cache, bytenr, blocksize);
+	if (cache && cache->start == bytenr &&
+	    cache->size == blocksize) {
+		eb = container_of(cache, struct extent_buffer, cache_node);
+		eb->refs++;
+	} else {
+		int ret;
 
-	/* sparse extent */
-	if (extent->disk_bytenr == 0) {
-		memset(out, 0, size);
-		return size;
+		if (cache) {
+			eb = container_of(cache, struct extent_buffer,
+					  cache_node);
+			free_extent_buffer(eb);
+		}
+		eb = __alloc_extent_buffer(fs_info, bytenr, blocksize);
+		if (!eb)
+			return NULL;
+		ret = insert_cache_extent(&tree->cache, &eb->cache_node);
+		if (ret) {
+			free(eb);
+			return NULL;
+		}
+		tree->cache_size += blocksize;
 	}
+	return eb;
+}
+
+/*
+ * Allocate a dummy extent buffer which won't be inserted into extent buffer
+ * cache.
+ *
+ * This mostly allows super block read write using existing eb infrastructure
+ * without pulluting the eb cache.
+ *
+ * This is especially important to avoid injecting eb->start == SZ_64K, as
+ * fuzzed image could have invalid tree bytenr covers super block range,
+ * and cause ref count underflow.
+ */
+struct extent_buffer *alloc_dummy_extent_buffer(struct btrfs_fs_info *fs_info,
+						u64 bytenr, u32 blocksize)
+{
+	struct extent_buffer *ret;
+
+	ret = __alloc_extent_buffer(fs_info, bytenr, blocksize);
+	if (!ret)
+		return NULL;
+
+	ret->flags |= EXTENT_BUFFER_DUMMY;
 
-	physical = btrfs_map_logical_to_physical(extent->disk_bytenr);
-	if (physical == -1ULL)
-		return -1ULL;
+	return ret;
+}
 
-	if (extent->compression == BTRFS_COMPRESS_NONE) {
-		physical += extent->offset + offset;
-		if (!btrfs_devread(physical, size, out))
-			return -1ULL;
+int read_extent_from_disk(struct blk_desc *desc, struct disk_partition *part,
+			  u64 physical, struct extent_buffer *eb,
+			  unsigned long offset, unsigned long len)
+{
+	int ret;
 
-		return size;
+	ret = __btrfs_devread(desc, part, eb->data + offset, len, physical);
+	if (ret < 0)
+		goto out;
+	if (ret != len) {
+		ret = -EIO;
+		goto out;
 	}
+	ret = 0;
+out:
+	return ret;
+}
 
-	cbuf = malloc_cache_aligned(dlen > size ? clen + dlen : clen);
-	if (!cbuf)
-		return -1ULL;
+int memcmp_extent_buffer(const struct extent_buffer *eb, const void *ptrv,
+			 unsigned long start, unsigned long len)
+{
+	return memcmp(eb->data + start, ptrv, len);
+}
 
-	if (dlen > orig_size)
-		dbuf = cbuf + clen;
-	else
-		dbuf = out;
+void read_extent_buffer(const struct extent_buffer *eb, void *dst,
+			unsigned long start, unsigned long len)
+{
+	memcpy(dst, eb->data + start, len);
+}
 
-	if (!btrfs_devread(physical, clen, cbuf))
-		goto err;
+void write_extent_buffer(struct extent_buffer *eb, const void *src,
+			 unsigned long start, unsigned long len)
+{
+	memcpy(eb->data + start, src, len);
+}
 
-	res = btrfs_decompress(extent->compression, cbuf, clen, dbuf, dlen);
-	if (res == -1)
-		goto err;
+void copy_extent_buffer(struct extent_buffer *dst, struct extent_buffer *src,
+			unsigned long dst_offset, unsigned long src_offset,
+			unsigned long len)
+{
+	memcpy(dst->data + dst_offset, src->data + src_offset, len);
+}
 
-	if (dlen > orig_size)
-		memcpy(out, dbuf + offset, size);
-	else
-		memmove(out, dbuf + offset, size);
+void memmove_extent_buffer(struct extent_buffer *dst, unsigned long dst_offset,
+			   unsigned long src_offset, unsigned long len)
+{
+	memmove(dst->data + dst_offset, dst->data + src_offset, len);
+}
 
-	free(cbuf);
-	return res;
+void memset_extent_buffer(struct extent_buffer *eb, char c,
+			  unsigned long start, unsigned long len)
+{
+	memset(eb->data + start, c, len);
+}
 
-err:
-	free(cbuf);
-	return -1ULL;
+int extent_buffer_test_bit(struct extent_buffer *eb, unsigned long start,
+			   unsigned long nr)
+{
+	return le_test_bit(nr, (u8 *)eb->data + start);
+}
+
+int set_extent_buffer_dirty(struct extent_buffer *eb)
+{
+	struct extent_io_tree *tree = &eb->fs_info->extent_cache;
+	if (!(eb->flags & EXTENT_DIRTY)) {
+		eb->flags |= EXTENT_DIRTY;
+		set_extent_dirty(tree, eb->start, eb->start + eb->len - 1);
+		extent_buffer_get(eb);
+	}
+	return 0;
+}
+
+int clear_extent_buffer_dirty(struct extent_buffer *eb)
+{
+	struct extent_io_tree *tree = &eb->fs_info->extent_cache;
+	if (eb->flags & EXTENT_DIRTY) {
+		eb->flags &= ~EXTENT_DIRTY;
+		clear_extent_dirty(tree, eb->start, eb->start + eb->len - 1);
+		free_extent_buffer(eb);
+	}
+	return 0;
 }

diff --git a/fs/btrfs/extent-io.h b/fs/btrfs/extent-io.h
new file mode 100644
index 0000000..6b0c87d
--- /dev/null
+++ b/fs/btrfs/extent-io.h

@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Crossported from btrfs-progs/extent_io.h
+ *
+ * Modification includes:
+ * - extent_buffer:data
+ *   Use pointer to provide better alignment.
+ * - Remove max_cache_size related interfaces
+ *   Includes free_extent_buffer_nocache()
+ *   As we don't cache eb in U-boot.
+ * - Include headers
+ *
+ * Write related functions are kept as we still need to modify dummy extent
+ * buffers even in RO environment.
+ */
+#ifndef __BTRFS_EXTENT_IO_H__
+#define __BTRFS_EXTENT_IO_H__
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/bitops.h>
+#include <fs_internal.h>
+#include "extent-cache.h"
+
+#define EXTENT_DIRTY		(1U << 0)
+#define EXTENT_WRITEBACK	(1U << 1)
+#define EXTENT_UPTODATE		(1U << 2)
+#define EXTENT_LOCKED		(1U << 3)
+#define EXTENT_NEW		(1U << 4)
+#define EXTENT_DELALLOC		(1U << 5)
+#define EXTENT_DEFRAG		(1U << 6)
+#define EXTENT_DEFRAG_DONE	(1U << 7)
+#define EXTENT_BUFFER_FILLED	(1U << 8)
+#define EXTENT_CSUM		(1U << 9)
+#define EXTENT_BAD_TRANSID	(1U << 10)
+#define EXTENT_BUFFER_DUMMY	(1U << 11)
+#define EXTENT_IOBITS (EXTENT_LOCKED | EXTENT_WRITEBACK)
+
+#define BLOCK_GROUP_DATA	(1U << 1)
+#define BLOCK_GROUP_METADATA	(1U << 2)
+#define BLOCK_GROUP_SYSTEM	(1U << 4)
+
+/*
+ * The extent buffer bitmap operations are done with byte granularity instead of
+ * word granularity for two reasons:
+ * 1. The bitmaps must be little-endian on disk.
+ * 2. Bitmap items are not guaranteed to be aligned to a word and therefore a
+ *    single word in a bitmap may straddle two pages in the extent buffer.
+ */
+#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE)
+#define BYTE_MASK ((1 << BITS_PER_BYTE) - 1)
+#define BITMAP_FIRST_BYTE_MASK(start) \
+	((BYTE_MASK << ((start) & (BITS_PER_BYTE - 1))) & BYTE_MASK)
+#define BITMAP_LAST_BYTE_MASK(nbits) \
+	(BYTE_MASK >> (-(nbits) & (BITS_PER_BYTE - 1)))
+
+static inline int le_test_bit(int nr, const u8 *addr)
+{
+	return 1U & (addr[BIT_BYTE(nr)] >> (nr & (BITS_PER_BYTE-1)));
+}
+
+struct btrfs_fs_info;
+
+struct extent_io_tree {
+	struct cache_tree state;
+	struct cache_tree cache;
+	u64 cache_size;
+};
+
+struct extent_state {
+	struct cache_extent cache_node;
+	u64 start;
+	u64 end;
+	int refs;
+	unsigned long state;
+	u64 xprivate;
+};
+
+struct extent_buffer {
+	struct cache_extent cache_node;
+	u64 start;
+	u32 len;
+	int refs;
+	u32 flags;
+	struct btrfs_fs_info *fs_info;
+	char *data;
+};
+
+static inline void extent_buffer_get(struct extent_buffer *eb)
+{
+	eb->refs++;
+}
+
+void extent_io_tree_init(struct extent_io_tree *tree);
+void extent_io_tree_cleanup(struct extent_io_tree *tree);
+int set_extent_bits(struct extent_io_tree *tree, u64 start, u64 end, int bits);
+int clear_extent_bits(struct extent_io_tree *tree, u64 start, u64 end, int bits);
+int find_first_extent_bit(struct extent_io_tree *tree, u64 start,
+			  u64 *start_ret, u64 *end_ret, int bits);
+int test_range_bit(struct extent_io_tree *tree, u64 start, u64 end,
+		   int bits, int filled);
+int set_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end);
+int clear_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end);
+static inline int set_extent_buffer_uptodate(struct extent_buffer *eb)
+{
+	eb->flags |= EXTENT_UPTODATE;
+	return 0;
+}
+
+static inline int clear_extent_buffer_uptodate(struct extent_buffer *eb)
+{
+	eb->flags &= ~EXTENT_UPTODATE;
+	return 0;
+}
+
+static inline int extent_buffer_uptodate(struct extent_buffer *eb)
+{
+	if (!eb || IS_ERR(eb))
+		return 0;
+	if (eb->flags & EXTENT_UPTODATE)
+		return 1;
+	return 0;
+}
+
+int set_state_private(struct extent_io_tree *tree, u64 start, u64 xprivate);
+int get_state_private(struct extent_io_tree *tree, u64 start, u64 *xprivate);
+struct extent_buffer *find_extent_buffer(struct extent_io_tree *tree,
+					 u64 bytenr, u32 blocksize);
+struct extent_buffer *find_first_extent_buffer(struct extent_io_tree *tree,
+					       u64 start);
+struct extent_buffer *alloc_extent_buffer(struct btrfs_fs_info *fs_info,
+					  u64 bytenr, u32 blocksize);
+struct extent_buffer *btrfs_clone_extent_buffer(struct extent_buffer *src);
+struct extent_buffer *alloc_dummy_extent_buffer(struct btrfs_fs_info *fs_info,
+						u64 bytenr, u32 blocksize);
+void free_extent_buffer(struct extent_buffer *eb);
+int read_extent_from_disk(struct blk_desc *desc, struct disk_partition *part,
+			  u64 physical, struct extent_buffer *eb,
+			  unsigned long offset, unsigned long len);
+int memcmp_extent_buffer(const struct extent_buffer *eb, const void *ptrv,
+			 unsigned long start, unsigned long len);
+void read_extent_buffer(const struct extent_buffer *eb, void *dst,
+			unsigned long start, unsigned long len);
+void write_extent_buffer(struct extent_buffer *eb, const void *src,
+			 unsigned long start, unsigned long len);
+void copy_extent_buffer(struct extent_buffer *dst, struct extent_buffer *src,
+			unsigned long dst_offset, unsigned long src_offset,
+			unsigned long len);
+void memmove_extent_buffer(struct extent_buffer *dst, unsigned long dst_offset,
+			   unsigned long src_offset, unsigned long len);
+void memset_extent_buffer(struct extent_buffer *eb, char c,
+			  unsigned long start, unsigned long len);
+int extent_buffer_test_bit(struct extent_buffer *eb, unsigned long start,
+			   unsigned long nr);
+int set_extent_buffer_dirty(struct extent_buffer *eb);
+int clear_extent_buffer_dirty(struct extent_buffer *eb);
+void extent_buffer_bitmap_clear(struct extent_buffer *eb, unsigned long start,
+				unsigned long pos, unsigned long len);
+void extent_buffer_bitmap_set(struct extent_buffer *eb, unsigned long start,
+			      unsigned long pos, unsigned long len);
+
+#endif

diff --git a/fs/btrfs/hash.c b/fs/btrfs/hash.c
deleted file mode 100644
index 52a8cea..0000000
--- a/fs/btrfs/hash.c
+++ /dev/null

@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * BTRFS filesystem implementation for U-Boot
- *
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
- */
-
-#include "btrfs.h"
-#include <u-boot/crc.h>
-#include <asm/unaligned.h>
-
-static u32 btrfs_crc32c_table[256];
-
-void btrfs_hash_init(void)
-{
-	static int inited = 0;
-
-	if (!inited) {
-		crc32c_init(btrfs_crc32c_table, 0x82F63B78);
-		inited = 1;
-	}
-}
-
-u32 btrfs_crc32c(u32 crc, const void *data, size_t length)
-{
-	return crc32c_cal(crc, (const char *) data, length,
-			  btrfs_crc32c_table);
-}
-
-u32 btrfs_csum_data(char *data, u32 seed, size_t len)
-{
-	return btrfs_crc32c(seed, data, len);
-}
-
-void btrfs_csum_final(u32 crc, void *result)
-{
-	put_unaligned(cpu_to_le32(~crc), (u32 *)result);
-}

diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 991c2f6..ff33028 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c

@@ -5,193 +5,187 @@
  * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
  */
 
-#include "btrfs.h"
+#include <linux/kernel.h>
 #include <malloc.h>
+#include <memalign.h>
+#include "btrfs.h"
+#include "disk-io.h"
+#include "volumes.h"
 
-u64 btrfs_lookup_inode_ref(struct btrfs_root *root, u64 inr,
-			   struct btrfs_inode_ref *refp, char *name)
+/*
+ * Read the content of symlink inode @ino of @root, into @target.
+ * NOTE: @target will not be \0 termiated, caller should handle it properly.
+ *
+ * Return the number of read data.
+ * Return <0 for error.
+ */
+int btrfs_readlink(struct btrfs_root *root, u64 ino, char *target)
 {
 	struct btrfs_path path;
-	struct btrfs_key *key;
-	struct btrfs_inode_ref *ref;
-	u64 res = -1ULL;
-
-	key = btrfs_search_tree_key_type(root, inr, BTRFS_INODE_REF_KEY,
-					       &path);
-
-	if (!key)
-		return -1ULL;
-
-	ref = btrfs_path_item_ptr(&path, struct btrfs_inode_ref);
-	btrfs_inode_ref_to_cpu(ref);
-
-	if (refp)
-		*refp = *ref;
+	struct btrfs_key key;
+	struct btrfs_file_extent_item *fi;
+	int ret;
 
-	if (name) {
-		if (ref->name_len > BTRFS_NAME_MAX) {
-			printf("%s: inode name too long: %u\n", __func__,
-			        ref->name_len);
-			goto out;
-		}
+	key.objectid = ino;
+	key.type = BTRFS_EXTENT_DATA_KEY;
+	key.offset = 0;
+	btrfs_init_path(&path);
 
-		memcpy(name, ref + 1, ref->name_len);
+	ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+	if (ret < 0)
+		return ret;
+	if (ret > 0) {
+		ret = -ENOENT;
+		goto out;
 	}
-
-	res = key->offset;
-out:
-	btrfs_free_path(&path);
-	return res;
-}
-
-int btrfs_lookup_inode(const struct btrfs_root *root,
-		       struct btrfs_key *location,
-		       struct btrfs_inode_item *item,
-		       struct btrfs_root *new_root)
-{
-	struct btrfs_root tmp_root = *root;
-	struct btrfs_path path;
-	int res = -1;
-
-	if (location->type == BTRFS_ROOT_ITEM_KEY) {
-		if (btrfs_find_root(location->objectid, &tmp_root, NULL))
-			return -1;
-
-		location->objectid = tmp_root.root_dirid;
-		location->type = BTRFS_INODE_ITEM_KEY;
-		location->offset = 0;
+	fi = btrfs_item_ptr(path.nodes[0], path.slots[0],
+			    struct btrfs_file_extent_item);
+	if (btrfs_file_extent_type(path.nodes[0], fi) !=
+	    BTRFS_FILE_EXTENT_INLINE) {
+		ret = -EUCLEAN;
+		error("Extent for symlink %llu must be INLINE type!", ino);
+		goto out;
 	}
-
-	if (btrfs_search_tree(&tmp_root, location, &path))
-		return res;
-
-	if (btrfs_comp_keys(location, btrfs_path_leaf_key(&path)))
+	if (btrfs_file_extent_compression(path.nodes[0], fi) !=
+	    BTRFS_COMPRESS_NONE) {
+		ret = -EUCLEAN;
+		error("Extent for symlink %llu must not be compressed!", ino);
 		goto out;
-
-	if (item) {
-		*item = *btrfs_path_item_ptr(&path, struct btrfs_inode_item);
-		btrfs_inode_item_to_cpu(item);
 	}
-
-	if (new_root)
-		*new_root = tmp_root;
-
-	res = 0;
-
+	if (btrfs_file_extent_ram_bytes(path.nodes[0], fi) >=
+	    root->fs_info->sectorsize) {
+		ret = -EUCLEAN;
+		error("Symlink %llu extent data too large (%llu)!\n",
+			ino, btrfs_file_extent_ram_bytes(path.nodes[0], fi));
+		goto out;
+	}
+	read_extent_buffer(path.nodes[0], target,
+			btrfs_file_extent_inline_start(fi),
+			btrfs_file_extent_ram_bytes(path.nodes[0], fi));
+	ret = btrfs_file_extent_ram_bytes(path.nodes[0], fi);
 out:
-	btrfs_free_path(&path);
-	return res;
+	btrfs_release_path(&path);
+	return ret;
 }
 
-int btrfs_readlink(const struct btrfs_root *root, u64 inr, char *target)
+static int lookup_root_ref(struct btrfs_fs_info *fs_info,
+			   u64 rootid, u64 *root_ret, u64 *dir_ret)
 {
+	struct btrfs_root *root = fs_info->tree_root;
+	struct btrfs_root_ref *root_ref;
 	struct btrfs_path path;
 	struct btrfs_key key;
-	struct btrfs_file_extent_item *extent;
-	const char *data_ptr;
-	int res = -1;
-
-	key.objectid = inr;
-	key.type = BTRFS_EXTENT_DATA_KEY;
-	key.offset = 0;
+	int ret;
 
-	if (btrfs_search_tree(root, &key, &path))
-		return -1;
+	btrfs_init_path(&path);
+	key.objectid = rootid;
+	key.type = BTRFS_ROOT_BACKREF_KEY;
+	key.offset = (u64)-1;
 
-	if (btrfs_comp_keys(&key, btrfs_path_leaf_key(&path)))
-		goto out;
-
-	extent = btrfs_path_item_ptr(&path, struct btrfs_file_extent_item);
-	if (extent->type != BTRFS_FILE_EXTENT_INLINE) {
-		printf("%s: Extent for symlink %llu not of INLINE type\n",
-		       __func__, inr);
+	ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+	if (ret < 0)
+		return ret;
+	/* Should not happen */
+	if (ret == 0) {
+		ret = -EUCLEAN;
 		goto out;
 	}
-
-	btrfs_file_extent_item_to_cpu_inl(extent);
-
-	if (extent->compression != BTRFS_COMPRESS_NONE) {
-		printf("%s: Symlink %llu extent data compressed!\n", __func__,
-		       inr);
+	ret = btrfs_previous_item(root, &path, rootid, BTRFS_ROOT_BACKREF_KEY);
+	if (ret < 0)
 		goto out;
-	} else if (extent->encryption != 0) {
-		printf("%s: Symlink %llu extent data encrypted!\n", __func__,
-		       inr);
-		goto out;
-	} else if (extent->ram_bytes >= btrfs_info.sb.sectorsize) {
-		printf("%s: Symlink %llu extent data too long (%llu)!\n",
-		       __func__, inr, extent->ram_bytes);
+	if (ret > 0) {
+		ret = -ENOENT;
 		goto out;
 	}
-
-	data_ptr = (const char *) extent
-		   + offsetof(struct btrfs_file_extent_item, disk_bytenr);
-
-	memcpy(target, data_ptr, extent->ram_bytes);
-	target[extent->ram_bytes] = '\0';
-	res = 0;
+	btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+	root_ref = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				  struct btrfs_root_ref);
+	*root_ret = key.offset;
+	*dir_ret = btrfs_root_ref_dirid(path.nodes[0], root_ref);
 out:
-	btrfs_free_path(&path);
-	return res;
+	btrfs_release_path(&path);
+	return ret;
 }
 
-/* inr must be a directory (for regular files with multiple hard links this
-   function returns only one of the parents of the file) */
-static u64 get_parent_inode(struct btrfs_root *root, u64 inr,
-			    struct btrfs_inode_item *inode_item)
+/*
+ * To get the parent inode of @ino of @root.
+ *
+ * @root_ret and @ino_ret will be filled.
+ *
+ * NOTE: This function is not reliable. It can only get one parent inode.
+ * The get the proper parent inode, we need a full VFS inodes stack to
+ * resolve properly.
+ */
+static int get_parent_inode(struct btrfs_root *root, u64 ino,
+			    struct btrfs_root **root_ret, u64 *ino_ret)
 {
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	struct btrfs_path path;
 	struct btrfs_key key;
-	u64 res;
+	int ret;
 
-	if (inr == BTRFS_FIRST_FREE_OBJECTID) {
-		if (root->objectid != btrfs_info.fs_root.objectid) {
-			u64 parent;
-			struct btrfs_root_ref ref;
+	if (ino == BTRFS_FIRST_FREE_OBJECTID) {
+		u64 parent_root = -1;
 
-			parent = btrfs_lookup_root_ref(root->objectid, &ref,
-						       NULL);
-			if (parent == -1ULL)
-				return -1ULL;
-
-			if (btrfs_find_root(parent, root, NULL))
-				return -1ULL;
-
-			inr = ref.dirid;
+		/* It's top level already, no more parent */
+		if (root->root_key.objectid == BTRFS_FS_TREE_OBJECTID) {
+			*root_ret = fs_info->fs_root;
+			*ino_ret = BTRFS_FIRST_FREE_OBJECTID;
+			return 0;
 		}
 
-		if (inode_item) {
-			key.objectid = inr;
-			key.type = BTRFS_INODE_ITEM_KEY;
-			key.offset = 0;
+		ret = lookup_root_ref(fs_info, root->root_key.objectid,
+				      &parent_root, ino_ret);
+		if (ret < 0)
+			return ret;
 
-			if (btrfs_lookup_inode(root, &key, inode_item, NULL))
-				return -1ULL;
-		}
+		key.objectid = parent_root;
+		key.type = BTRFS_ROOT_ITEM_KEY;
+		key.offset = (u64)-1;
+		*root_ret = btrfs_read_fs_root(fs_info, &key);
+		if (IS_ERR(*root_ret))
+			return PTR_ERR(*root_ret);
 
-		return inr;
+		return 0;
 	}
 
-	res = btrfs_lookup_inode_ref(root, inr, NULL, NULL);
-	if (res == -1ULL)
-		return -1ULL;
+	btrfs_init_path(&path);
+	key.objectid = ino;
+	key.type = BTRFS_INODE_REF_KEY;
+	key.offset = (u64)-1;
 
-	if (inode_item) {
-		key.objectid = res;
-		key.type = BTRFS_INODE_ITEM_KEY;
-		key.offset = 0;
-
-		if (btrfs_lookup_inode(root, &key, inode_item, NULL))
-			return -1ULL;
+	ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+	if (ret < 0)
+		return ret;
+	/* Should not happen */
+	if (ret == 0) {
+		ret = -EUCLEAN;
+		goto out;
 	}
-
-	return res;
+	ret = btrfs_previous_item(root, &path, ino, BTRFS_INODE_REF_KEY);
+	if (ret < 0)
+		goto out;
+	if (ret > 0) {
+		ret = -ENOENT;
+		goto out;
+	}
+	btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+	*root_ret = root;
+	*ino_ret = key.offset;
+out:
+	btrfs_release_path(&path);
+	return ret;
 }
 
 static inline int next_length(const char *path)
 {
 	int res = 0;
-	while (*path != '\0' && *path != '/' && res <= BTRFS_NAME_LEN)
-		++res, ++path;
+	while (*path != '\0' && *path != '/') {
+		++res;
+		++path;
+		if (res > BTRFS_NAME_LEN)
+			break;
+	}
 	return res;
 }
 
@@ -209,175 +203,549 @@
 	return cur;
 }
 
-u64 btrfs_lookup_path(struct btrfs_root *root, u64 inr, const char *path,
-		      u8 *type_p, struct btrfs_inode_item *inode_item_p,
-		      int symlink_limit)
+/*
+ * Resolve one filename of @ino of @root.
+ *
+ * key_ret:	The child key (either INODE_ITEM or ROOT_ITEM type)
+ * type_ret:	BTRFS_FT_* of the child inode.
+ *
+ * Return 0 with above members filled.
+ * Return <0 for error.
+ */
+static int resolve_one_filename(struct btrfs_root *root, u64 ino,
+				const char *name, int namelen,
+				struct btrfs_key *key_ret, u8 *type_ret)
 {
-	struct btrfs_dir_item item;
-	struct btrfs_inode_item inode_item;
-	u8 type = BTRFS_FT_DIR;
-	int len, have_inode = 0;
-	const char *cur = path;
+	struct btrfs_dir_item *dir_item;
+	struct btrfs_path path;
+	int ret = 0;
 
+	btrfs_init_path(&path);
+
+	dir_item = btrfs_lookup_dir_item(NULL, root, &path, ino, name,
+					 namelen, 0);
+	if (IS_ERR(dir_item)) {
+		ret = PTR_ERR(dir_item);
+		goto out;
+	}
+
+	btrfs_dir_item_key_to_cpu(path.nodes[0], dir_item, key_ret);
+	*type_ret = btrfs_dir_type(path.nodes[0], dir_item);
+out:
+	btrfs_release_path(&path);
+	return ret;
+}
+
+/*
+ * Resolve a full path @filename. The start point is @ino of @root.
+ *
+ * The result will be filled into @root_ret, @ino_ret and @type_ret.
+ */
+int btrfs_lookup_path(struct btrfs_root *root, u64 ino, const char *filename,
+			struct btrfs_root **root_ret, u64 *ino_ret,
+			u8 *type_ret, int symlink_limit)
+{
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	struct btrfs_root *next_root;
+	struct btrfs_key key;
+	const char *cur = filename;
+	u64 next_ino;
+	u8 next_type;
+	u8 type;
+	int len;
+	int ret = 0;
+
+	/* If the path is absolute path, also search from fs root */
 	if (*cur == '/') {
-		++cur;
-		inr = root->root_dirid;
+		root = fs_info->fs_root;
+		ino = btrfs_root_dirid(&root->root_item);
+		type = BTRFS_FT_DIR;
 	}
 
-	do {
+	while (*cur != '\0') {
 		cur = skip_current_directories(cur);
 
 		len = next_length(cur);
 		if (len > BTRFS_NAME_LEN) {
-			printf("%s: Name too long at \"%.*s\"\n", __func__,
+			error("%s: Name too long at \"%.*s\"", __func__,
 			       BTRFS_NAME_LEN, cur);
-			return -1ULL;
+			return -ENAMETOOLONG;
 		}
 
 		if (len == 1 && cur[0] == '.')
 			break;
 
 		if (len == 2 && cur[0] == '.' && cur[1] == '.') {
-			cur += 2;
-			inr = get_parent_inode(root, inr, &inode_item);
-			if (inr == -1ULL)
-				return -1ULL;
-
-			type = BTRFS_FT_DIR;
-			continue;
+			/* Go one level up */
+			ret = get_parent_inode(root, ino, &next_root, &next_ino);
+			if (ret < 0)
+				return ret;
+			root = next_root;
+			ino = next_ino;
+			goto next;
 		}
 
 		if (!*cur)
 			break;
-		
-		if (btrfs_lookup_dir_item(root, inr, cur, len, &item))
-			return -1ULL;
 
-		type = item.type;
-		have_inode = 1;
-		if (btrfs_lookup_inode(root, &item.location, &inode_item, root))
-			return -1ULL;
+		ret = resolve_one_filename(root, ino, cur, len, &key, &type);
+		if (ret < 0)
+			return ret;
 
-		if (item.type == BTRFS_FT_SYMLINK && symlink_limit >= 0) {
+		if (key.type == BTRFS_ROOT_ITEM_KEY) {
+			/* Child inode is a subvolume */
+
+			next_root = btrfs_read_fs_root(fs_info, &key);
+			if (IS_ERR(next_root))
+				return PTR_ERR(next_root);
+			root = next_root;
+			ino = btrfs_root_dirid(&root->root_item);
+		} else if (type == BTRFS_FT_SYMLINK && symlink_limit >= 0) {
+			/* Child inode is a symlink */
+
 			char *target;
 
-			if (!symlink_limit) {
-				printf("%s: Too much symlinks!\n", __func__);
-				return -1ULL;
+			if (symlink_limit == 0) {
+				error("%s: Too much symlinks!", __func__);
+				return -EMLINK;
 			}
-
-			target = malloc(min(inode_item.size + 1,
-					    (u64) btrfs_info.sb.sectorsize));
+			target = malloc(fs_info->sectorsize);
 			if (!target)
-				return -1ULL;
-
-			if (btrfs_readlink(root, item.location.objectid,
-					   target)) {
+				return -ENOMEM;
+			ret = btrfs_readlink(root, key.objectid, target);
+			if (ret < 0) {
 				free(target);
-				return -1ULL;
+				return ret;
 			}
+			target[ret] = '\0';
 
-			inr = btrfs_lookup_path(root, inr, target, &type,
-						&inode_item, symlink_limit - 1);
-
-			free(target);
-
-			if (inr == -1ULL)
-				return -1ULL;
-		} else if (item.type != BTRFS_FT_DIR && cur[len]) {
-			printf("%s: \"%.*s\" not a directory\n", __func__,
-			       (int) (cur - path + len), path);
-			return -1ULL;
+			ret = btrfs_lookup_path(root, ino, target, &next_root,
+						&next_ino, &next_type,
+						symlink_limit);
+			if (ret < 0)
+				return ret;
+			root = next_root;
+			ino = next_ino;
+			type = next_type;
 		} else {
-			inr = item.location.objectid;
+			/* Child inode is an inode */
+			ino = key.objectid;
 		}
-
+next:
 		cur += len;
-	} while (*cur);
+	}
+
+	if (!ret) {
+		*root_ret = root;
+		*ino_ret = ino;
+		*type_ret = type;
+	}
 
-	if (type_p)
-		*type_p = type;
+	return ret;
+}
+
+/*
+ * Read out inline extent.
+ *
+ * Since inline extent should only exist for offset 0, no need for extra
+ * parameters.
+ * Truncating should be handled by the caller.
+ *
+ * Return the number of bytes read.
+ * Return <0 for error.
+ */
+int btrfs_read_extent_inline(struct btrfs_path *path,
+			     struct btrfs_file_extent_item *fi, char *dest)
+{
+	struct extent_buffer *leaf = path->nodes[0];
+	int slot = path->slots[0];
+	char *cbuf = NULL;
+	char *dbuf = NULL;
+	u32 csize;
+	u32 dsize;
+	int ret;
+
+	csize = btrfs_file_extent_inline_item_len(leaf, btrfs_item_nr(slot));
+	if (btrfs_file_extent_compression(leaf, fi) == BTRFS_COMPRESS_NONE) {
+		/* Uncompressed, just read it out */
+		read_extent_buffer(leaf, dest,
+				btrfs_file_extent_inline_start(fi),
+				csize);
+		return csize;
+	}
 
-	if (inode_item_p) {
-		if (!have_inode) {
-			struct btrfs_key key;
+	/* Compressed extent, prepare the compressed and data buffer */
+	dsize = btrfs_file_extent_ram_bytes(leaf, fi);
+	cbuf = malloc(csize);
+	dbuf = malloc(dsize);
+	if (!cbuf || !dbuf) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	read_extent_buffer(leaf, cbuf, btrfs_file_extent_inline_start(fi),
+			   csize);
+	ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi),
+			       cbuf, csize, dbuf, dsize);
+	if (ret < 0 || ret != dsize) {
+		ret = -EIO;
+		goto out;
+	}
+	memcpy(dest, dbuf, dsize);
+	ret = dsize;
+out:
+	free(cbuf);
+	free(dbuf);
+	return ret;
+}
+
+/*
+ * Read out regular extent.
+ *
+ * Truncating should be handled by the caller.
+ *
+ * @offset and @len should not cross the extent boundary.
+ * Return the number of bytes read.
+ * Return <0 for error.
+ */
+int btrfs_read_extent_reg(struct btrfs_path *path,
+			  struct btrfs_file_extent_item *fi, u64 offset,
+			  int len, char *dest)
+{
+	struct extent_buffer *leaf = path->nodes[0];
+	struct btrfs_fs_info *fs_info = leaf->fs_info;
+	struct btrfs_key key;
+	u64 extent_num_bytes;
+	u64 disk_bytenr;
+	u64 read;
+	char *cbuf = NULL;
+	char *dbuf = NULL;
+	u32 csize;
+	u32 dsize;
+	bool finished = false;
+	int num_copies;
+	int i;
+	int slot = path->slots[0];
+	int ret;
 
-			key.objectid = inr;
-			key.type = BTRFS_INODE_ITEM_KEY;
-			key.offset = 0;
+	btrfs_item_key_to_cpu(leaf, &key, slot);
+	extent_num_bytes = btrfs_file_extent_num_bytes(leaf, fi);
+	ASSERT(IS_ALIGNED(offset, fs_info->sectorsize) &&
+	       IS_ALIGNED(len, fs_info->sectorsize));
+	ASSERT(offset >= key.offset &&
+	       offset + len <= key.offset + extent_num_bytes);
 
-			if (btrfs_lookup_inode(root, &key, &inode_item, NULL))
-				return -1ULL;
+	/* Preallocated or hole , fill @dest with zero */
+	if (btrfs_file_extent_type(leaf, fi) == BTRFS_FILE_EXTENT_PREALLOC ||
+	    btrfs_file_extent_disk_bytenr(leaf, fi) == 0) {
+		memset(dest, 0, len);
+		return len;
+	}
+
+	if (btrfs_file_extent_compression(leaf, fi) == BTRFS_COMPRESS_NONE) {
+		u64 logical;
+
+		logical = btrfs_file_extent_disk_bytenr(leaf, fi) +
+			  btrfs_file_extent_offset(leaf, fi) +
+			  offset - key.offset;
+		read = len;
+
+		num_copies = btrfs_num_copies(fs_info, logical, len);
+		for (i = 1; i <= num_copies; i++) {
+			ret = read_extent_data(fs_info, dest, logical, &read, i);
+			if (ret < 0 || read != len)
+				continue;
+			finished = true;
+			break;
 		}
+		if (!finished)
+			return -EIO;
+		return len;
+	}
+
+	csize = btrfs_file_extent_disk_num_bytes(leaf, fi);
+	dsize = btrfs_file_extent_ram_bytes(leaf, fi);
+	disk_bytenr = btrfs_file_extent_disk_bytenr(leaf, fi);
+	num_copies = btrfs_num_copies(fs_info, disk_bytenr, csize);
 
-		*inode_item_p = inode_item;
+	cbuf = malloc_cache_aligned(csize);
+	dbuf = malloc_cache_aligned(dsize);
+	if (!cbuf || !dbuf) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	/* For compressed extent, we must read the whole on-disk extent */
+	for (i = 1; i <= num_copies; i++) {
+		read = csize;
+		ret = read_extent_data(fs_info, cbuf, disk_bytenr,
+				       &read, i);
+		if (ret < 0 || read != csize)
+			continue;
+		finished = true;
+		break;
+	}
+	if (!finished) {
+		ret = -EIO;
+		goto out;
 	}
 
-	return inr;
+	ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi), cbuf,
+			       csize, dbuf, dsize);
+	if (ret != dsize) {
+		ret = -EIO;
+		goto out;
+	}
+	/* Then copy the needed part */
+	memcpy(dest, dbuf + btrfs_file_extent_offset(leaf, fi), len);
+	ret = len;
+out:
+	free(cbuf);
+	free(dbuf);
+	return ret;
 }
 
-u64 btrfs_file_read(const struct btrfs_root *root, u64 inr, u64 offset,
-		    u64 size, char *buf)
+/*
+ * Get the first file extent that covers bytenr @file_offset.
+ *
+ * @file_offset must be aligned to sectorsize.
+ *
+ * return 0 for found, and path points to the file extent.
+ * return >0 for not found, and fill @next_offset.
+ * @next_offset can be 0 if there is no next file extent.
+ * return <0 for error.
+ */
+static int lookup_data_extent(struct btrfs_root *root, struct btrfs_path *path,
+			      u64 ino, u64 file_offset, u64 *next_offset)
 {
-	struct btrfs_path path;
 	struct btrfs_key key;
-	struct btrfs_file_extent_item *extent;
-	int res = 0;
-	u64 rd, rd_all = -1ULL;
+	struct btrfs_file_extent_item *fi;
+	u8 extent_type;
+	int ret = 0;
 
-	key.objectid = inr;
+	ASSERT(IS_ALIGNED(file_offset, root->fs_info->sectorsize));
+	key.objectid = ino;
 	key.type = BTRFS_EXTENT_DATA_KEY;
-	key.offset = offset;
+	key.offset = file_offset;
+
+	ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
+	/* Error or we're already at the file extent */
+	if (ret <= 0)
+		return ret;
+	if (ret > 0) {
+		/* Check previous file extent */
+		ret = btrfs_previous_item(root, path, ino,
+					  BTRFS_EXTENT_DATA_KEY);
+		if (ret < 0)
+			return ret;
+		if (ret > 0)
+			goto check_next;
+	}
+	/* Now the key.offset must be smaller than @file_offset */
+	btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
+	if (key.objectid != ino ||
+	    key.type != BTRFS_EXTENT_DATA_KEY)
+		goto check_next;
 
-	if (btrfs_search_tree(root, &key, &path))
-		return -1ULL;
+	fi = btrfs_item_ptr(path->nodes[0], path->slots[0],
+			    struct btrfs_file_extent_item);
+	extent_type = btrfs_file_extent_type(path->nodes[0], fi);
+	if (extent_type == BTRFS_FILE_EXTENT_INLINE) {
+		if (file_offset == 0)
+			return 0;
+		/* Inline extent should be the only extent, no next extent. */
+		*next_offset = 0;
+		return 1;
+	}
 
-	if (btrfs_comp_keys(&key, btrfs_path_leaf_key(&path)) < 0) {
-		if (btrfs_prev_slot(&path))
-			goto out;
+	/* This file extent covers @file_offset */
+	if (key.offset <= file_offset && key.offset +
+	    btrfs_file_extent_num_bytes(path->nodes[0], fi) > file_offset)
+		return 0;
+check_next:
+	ret = btrfs_next_item(root, path);
+	if (ret < 0)
+		return ret;
+	if (ret > 0) {
+		*next_offset = 0;
+		return 1;
+	}
 
-		if (btrfs_comp_keys_type(&key, btrfs_path_leaf_key(&path)))
-			goto out;
+	btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
+	fi = btrfs_item_ptr(path->nodes[0], path->slots[0],
+			    struct btrfs_file_extent_item);
+	/* Next next data extent */
+	if (key.objectid != ino ||
+	    key.type != BTRFS_EXTENT_DATA_KEY) {
+		*next_offset = 0;
+		return 1;
 	}
+	/* Current file extent already beyond @file_offset */
+	if (key.offset > file_offset) {
+		*next_offset = key.offset;
+		return 1;
+	}
+	/* This file extent covers @file_offset */
+	if (key.offset <= file_offset && key.offset +
+	    btrfs_file_extent_num_bytes(path->nodes[0], fi) > file_offset)
+		return 0;
+	/* This file extent ends before @file_offset, check next */
+	ret = btrfs_next_item(root, path);
+	if (ret < 0)
+		return ret;
+	if (ret > 0) {
+		*next_offset = 0;
+		return 1;
+	}
+	btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
+	if (key.type != BTRFS_EXTENT_DATA_KEY || key.objectid != ino) {
+		*next_offset = 0;
+		return 1;
+	}
+	*next_offset = key.offset;
+	return 1;
+}
 
-	rd_all = 0;
+static int read_and_truncate_page(struct btrfs_path *path,
+				  struct btrfs_file_extent_item *fi,
+				  int start, int len, char *dest)
+{
+	struct extent_buffer *leaf = path->nodes[0];
+	struct btrfs_fs_info *fs_info = leaf->fs_info;
+	u64 aligned_start = round_down(start, fs_info->sectorsize);
+	u8 extent_type;
+	char *buf;
+	int page_off = start - aligned_start;
+	int page_len = fs_info->sectorsize - page_off;
+	int ret;
 
-	do {
-		if (btrfs_comp_keys_type(&key, btrfs_path_leaf_key(&path)))
-			break;
+	ASSERT(start + len <= aligned_start + fs_info->sectorsize);
+	buf = malloc_cache_aligned(fs_info->sectorsize);
+	if (!buf)
+		return -ENOMEM;
 
-		extent = btrfs_path_item_ptr(&path,
-					     struct btrfs_file_extent_item);
+	extent_type = btrfs_file_extent_type(leaf, fi);
+	if (extent_type == BTRFS_FILE_EXTENT_INLINE) {
+		ret = btrfs_read_extent_inline(path, fi, buf);
+		memcpy(dest, buf + page_off, min(page_len, ret));
+		free(buf);
+		return len;
+	}
 
-		if (extent->type == BTRFS_FILE_EXTENT_INLINE) {
-			btrfs_file_extent_item_to_cpu_inl(extent);
-			rd = btrfs_read_extent_inline(&path, extent, offset,
-						      size, buf);
-		} else {
-			btrfs_file_extent_item_to_cpu(extent);
-			rd = btrfs_read_extent_reg(&path, extent, offset, size,
-						   buf);
-		}
+	ret = btrfs_read_extent_reg(path, fi,
+			round_down(start, fs_info->sectorsize),
+			fs_info->sectorsize, buf);
+	if (ret < 0) {
+		free(buf);
+		return ret;
+	}
+	memcpy(dest, buf + page_off, page_len);
+	free(buf);
+	return len;
+}
 
-		if (rd == -1ULL) {
-			printf("%s: Error reading extent\n", __func__);
-			rd_all = -1;
+int btrfs_file_read(struct btrfs_root *root, u64 ino, u64 file_offset, u64 len,
+		    char *dest)
+{
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	struct btrfs_file_extent_item *fi;
+	struct btrfs_path path;
+	struct btrfs_key key;
+	u64 aligned_start = round_down(file_offset, fs_info->sectorsize);
+	u64 aligned_end = round_down(file_offset + len, fs_info->sectorsize);
+	u64 next_offset;
+	u64 cur = aligned_start;
+	int ret = 0;
+
+	btrfs_init_path(&path);
+
+	/* Set the whole dest all zero, so we won't need to bother holes */
+	memset(dest, 0, len);
+
+	/* Read out the leading unaligned part */
+	if (aligned_start != file_offset) {
+		ret = lookup_data_extent(root, &path, ino, aligned_start,
+					 &next_offset);
+		if (ret < 0)
 			goto out;
+		if (ret == 0) {
+			/* Read the unaligned part out*/
+			fi = btrfs_item_ptr(path.nodes[0], path.slots[0],
+					struct btrfs_file_extent_item);
+			ret = read_and_truncate_page(&path, fi, file_offset,
+					round_up(file_offset, fs_info->sectorsize) -
+					file_offset, dest);
+			if (ret < 0)
+				goto out;
+			cur += fs_info->sectorsize;
+		} else {
+			/* The whole file is a hole */
+			if (!next_offset) {
+				memset(dest, 0, len);
+				return len;
+			}
+			cur = next_offset;
 		}
+	}
 
-		offset = 0;
-		buf += rd;
-		rd_all += rd;
-		size -= rd;
+	/* Read the aligned part */
+	while (cur < aligned_end) {
+		u64 extent_num_bytes;
+		u8 type;
 
-		if (!size)
-			break;
-	} while (!(res = btrfs_next_slot(&path)));
+		btrfs_release_path(&path);
+		ret = lookup_data_extent(root, &path, ino, cur, &next_offset);
+		if (ret < 0)
+			goto out;
+		if (ret > 0) {
+			/* No next, direct exit */
+			if (!next_offset) {
+				ret = 0;
+				goto out;
+			}
+		}
+		fi = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				    struct btrfs_file_extent_item);
+		btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+		type = btrfs_file_extent_type(path.nodes[0], fi);
+		if (type == BTRFS_FILE_EXTENT_INLINE) {
+			ret = btrfs_read_extent_inline(&path, fi, dest);
+			goto out;
+		}
+		/* Skip holes, as we have zeroed the dest */
+		if (type == BTRFS_FILE_EXTENT_PREALLOC ||
+		    btrfs_file_extent_disk_bytenr(path.nodes[0], fi) == 0) {
+			cur = key.offset + btrfs_file_extent_num_bytes(
+					path.nodes[0], fi);
+			continue;
+		}
 
-	if (res)
-		return -1ULL;
+		/* Read the remaining part of the extent */
+		extent_num_bytes = btrfs_file_extent_num_bytes(path.nodes[0],
+							       fi);
+		ret = btrfs_read_extent_reg(&path, fi, cur,
+				min(extent_num_bytes, aligned_end - cur),
+				dest + cur - file_offset);
+		if (ret < 0)
+			goto out;
+		cur += min(extent_num_bytes, aligned_end - cur);
+	}
 
+	/* Read the tailing unaligned part*/
+	if (file_offset + len != aligned_end) {
+		btrfs_release_path(&path);
+		ret = lookup_data_extent(root, &path, ino, aligned_end,
+					 &next_offset);
+		/* <0 is error, >0 means no extent */
+		if (ret)
+			goto out;
+		fi = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				    struct btrfs_file_extent_item);
+		ret = read_and_truncate_page(&path, fi, aligned_end,
+				file_offset + len - aligned_end,
+				dest + aligned_end - file_offset);
+	}
 out:
-	btrfs_free_path(&path);
-	return rd_all;
+	btrfs_release_path(&path);
+	if (ret < 0)
+		return ret;
+	return len;
 }

diff --git a/fs/btrfs/kernel-shared/btrfs_tree.h b/fs/btrfs/kernel-shared/btrfs_tree.h
new file mode 100644
index 0000000..6a76d1e
--- /dev/null
+++ b/fs/btrfs/kernel-shared/btrfs_tree.h

@@ -0,0 +1,1333 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copied from kernel/include/uapi/linux/btrfs_btree.h.
+ *
+ * Only modified the header.
+ */
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __BTRFS_TREE_H__
+#define __BTRFS_TREE_H__
+
+#include <linux/types.h>
+
+#define BTRFS_MAGIC 0x4D5F53665248425FULL /* ascii _BHRfS_M, no null */
+
+/*
+ * The max metadata block size (node size).
+ *
+ * This limit is somewhat artificial. The memmove and tree block locking cost
+ * go up with larger node size.
+ */
+#define BTRFS_MAX_METADATA_BLOCKSIZE 65536
+
+/*
+ * We can actually store much bigger names, but lets not confuse the rest
+ * of linux.
+ *
+ * btrfs_dir_item::name_len follows this limitation.
+ */
+#define BTRFS_NAME_LEN 255
+
+/*
+ * Objectids start from here.
+ *
+ * Check btrfs_disk_key for the meaning of objectids.
+ */
+
+/*
+ * Root tree holds pointers to all of the tree roots.
+ * Without special mention, the root tree contains the root bytenr of all other
+ * trees, except the chunk tree and the log tree.
+ *
+ * The super block contains the root bytenr of this tree.
+ */
+#define BTRFS_ROOT_TREE_OBJECTID 1ULL
+
+/*
+ * Extent tree stores information about which extents are in use, and backrefs
+ * for each extent.
+ */
+#define BTRFS_EXTENT_TREE_OBJECTID 2ULL
+
+/*
+ * Chunk tree stores btrfs logical address -> physical address mapping.
+ *
+ * The super block contains part of chunk tree for bootstrap, and contains
+ * the root bytenr of this tree.
+ */
+#define BTRFS_CHUNK_TREE_OBJECTID 3ULL
+
+/*
+ * Device tree stores info about which areas of a given device are in use,
+ * and physical address -> btrfs logical address mapping.
+ */
+#define BTRFS_DEV_TREE_OBJECTID 4ULL
+
+/* The fs tree is the first subvolume tree, storing files and directories. */
+#define BTRFS_FS_TREE_OBJECTID 5ULL
+
+/* Shows the directory objectid inside the root tree. */
+#define BTRFS_ROOT_TREE_DIR_OBJECTID 6ULL
+
+/* Csum tree holds checksums of all the data extents. */
+#define BTRFS_CSUM_TREE_OBJECTID 7ULL
+
+/* Quota tree holds quota configuration and tracking. */
+#define BTRFS_QUOTA_TREE_OBJECTID 8ULL
+
+/* UUID tree stores items that use the BTRFS_UUID_KEY* types. */
+#define BTRFS_UUID_TREE_OBJECTID 9ULL
+
+/* Free space cache tree (v2 space cache) tracks free space in block groups. */
+#define BTRFS_FREE_SPACE_TREE_OBJECTID 10ULL
+
+/* Indicates device stats in the device tree. */
+#define BTRFS_DEV_STATS_OBJECTID 0ULL
+
+/* For storing balance parameters in the root tree. */
+#define BTRFS_BALANCE_OBJECTID -4ULL
+
+/* Orhpan objectid for tracking unlinked/truncated files. */
+#define BTRFS_ORPHAN_OBJECTID -5ULL
+
+/* Does write ahead logging to speed up fsyncs. */
+#define BTRFS_TREE_LOG_OBJECTID -6ULL
+#define BTRFS_TREE_LOG_FIXUP_OBJECTID -7ULL
+
+/* For space balancing. */
+#define BTRFS_TREE_RELOC_OBJECTID -8ULL
+#define BTRFS_DATA_RELOC_TREE_OBJECTID -9ULL
+
+/* Extent checksums, shared between the csum tree and log trees. */
+#define BTRFS_EXTENT_CSUM_OBJECTID -10ULL
+
+/* For storing free space cache (v1 space cache). */
+#define BTRFS_FREE_SPACE_OBJECTID -11ULL
+
+/* The inode number assigned to the special inode for storing free ino cache. */
+#define BTRFS_FREE_INO_OBJECTID -12ULL
+
+/* Dummy objectid represents multiple objectids. */
+#define BTRFS_MULTIPLE_OBJECTIDS -255ULL
+
+/* All files have objectids in this range. */
+#define BTRFS_FIRST_FREE_OBJECTID 256ULL
+#define BTRFS_LAST_FREE_OBJECTID -256ULL
+#define BTRFS_FIRST_CHUNK_TREE_OBJECTID 256ULL
+
+
+/*
+ * The device items go into the chunk tree.
+ *
+ * The key is in the form
+ * (BTRFS_DEV_ITEMS_OBJECTID, BTRFS_DEV_ITEM_KEY,  <device_id>)
+ */
+#define BTRFS_DEV_ITEMS_OBJECTID 1ULL
+
+#define BTRFS_BTREE_INODE_OBJECTID 1
+
+#define BTRFS_EMPTY_SUBVOL_DIR_OBJECTID 2
+
+#define BTRFS_DEV_REPLACE_DEVID 0ULL
+
+/*
+ * Types start from here.
+ *
+ * Check btrfs_disk_key for details about types.
+ */
+
+/*
+ * Inode items have the data typically returned from stat and store other
+ * info about object characteristics.
+ *
+ * There is one for every file and dir in the FS.
+ */
+#define BTRFS_INODE_ITEM_KEY		1
+/* reserve 2-11 close to the inode for later flexibility */
+#define BTRFS_INODE_REF_KEY		12
+#define BTRFS_INODE_EXTREF_KEY		13
+#define BTRFS_XATTR_ITEM_KEY		24
+#define BTRFS_ORPHAN_ITEM_KEY		48
+
+/*
+ * Dir items are the name -> inode pointers in a directory.
+ *
+ * There is one for every name in a directory.
+ */
+#define BTRFS_DIR_LOG_ITEM_KEY  60
+#define BTRFS_DIR_LOG_INDEX_KEY 72
+#define BTRFS_DIR_ITEM_KEY	84
+#define BTRFS_DIR_INDEX_KEY	96
+
+/* Stores info (position, size ...) about a data extent of a file */
+#define BTRFS_EXTENT_DATA_KEY	108
+
+/*
+ * Extent csums are stored in a separate tree and hold csums for
+ * an entire extent on disk.
+ */
+#define BTRFS_EXTENT_CSUM_KEY	128
+
+/*
+ * Root items point to tree roots.
+ *
+ * They are typically in the root tree used by the super block to find all the
+ * other trees.
+ */
+#define BTRFS_ROOT_ITEM_KEY	132
+
+/*
+ * Root backrefs tie subvols and snapshots to the directory entries that
+ * reference them.
+ */
+#define BTRFS_ROOT_BACKREF_KEY	144
+
+/*
+ * Root refs make a fast index for listing all of the snapshots and
+ * subvolumes referenced by a given root.  They point directly to the
+ * directory item in the root that references the subvol.
+ */
+#define BTRFS_ROOT_REF_KEY	156
+
+/*
+ * Extent items are in the extent tree.
+ *
+ * These record which blocks are used, and how many references there are.
+ */
+#define BTRFS_EXTENT_ITEM_KEY	168
+
+/*
+ * The same as the BTRFS_EXTENT_ITEM_KEY, except it's metadata we already know
+ * the length, so we save the level in key->offset instead of the length.
+ */
+#define BTRFS_METADATA_ITEM_KEY	169
+
+#define BTRFS_TREE_BLOCK_REF_KEY	176
+
+#define BTRFS_EXTENT_DATA_REF_KEY	178
+
+#define BTRFS_EXTENT_REF_V0_KEY		180
+
+#define BTRFS_SHARED_BLOCK_REF_KEY	182
+
+#define BTRFS_SHARED_DATA_REF_KEY	184
+
+/*
+ * Block groups give us hints into the extent allocation trees.
+ *
+ * Stores how many free space there is in a block group.
+ */
+#define BTRFS_BLOCK_GROUP_ITEM_KEY 192
+
+/*
+ * Every block group is represented in the free space tree by a free space info
+ * item, which stores some accounting information. It is keyed on
+ * (block_group_start, FREE_SPACE_INFO, block_group_length).
+ */
+#define BTRFS_FREE_SPACE_INFO_KEY 198
+
+/*
+ * A free space extent tracks an extent of space that is free in a block group.
+ * It is keyed on (start, FREE_SPACE_EXTENT, length).
+ */
+#define BTRFS_FREE_SPACE_EXTENT_KEY 199
+
+/*
+ * When a block group becomes very fragmented, we convert it to use bitmaps
+ * instead of extents.
+ *
+ * A free space bitmap is keyed on (start, FREE_SPACE_BITMAP, length).
+ * The corresponding item is a bitmap with (length / sectorsize) bits.
+ */
+#define BTRFS_FREE_SPACE_BITMAP_KEY 200
+
+#define BTRFS_DEV_EXTENT_KEY	204
+#define BTRFS_DEV_ITEM_KEY	216
+#define BTRFS_CHUNK_ITEM_KEY	228
+
+/*
+ * Records the overall state of the qgroups.
+ *
+ * There's only one instance of this key present,
+ * (0, BTRFS_QGROUP_STATUS_KEY, 0)
+ */
+#define BTRFS_QGROUP_STATUS_KEY         240
+/*
+ * Records the currently used space of the qgroup.
+ *
+ * One key per qgroup, (0, BTRFS_QGROUP_INFO_KEY, qgroupid).
+ */
+#define BTRFS_QGROUP_INFO_KEY           242
+
+/*
+ * Contains the user configured limits for the qgroup.
+ *
+ * One key per qgroup, (0, BTRFS_QGROUP_LIMIT_KEY, qgroupid).
+ */
+#define BTRFS_QGROUP_LIMIT_KEY          244
+
+/*
+ * Records the child-parent relationship of qgroups. For
+ * each relation, 2 keys are present:
+ * (childid, BTRFS_QGROUP_RELATION_KEY, parentid)
+ * (parentid, BTRFS_QGROUP_RELATION_KEY, childid)
+ */
+#define BTRFS_QGROUP_RELATION_KEY       246
+
+/* Obsolete name, see BTRFS_TEMPORARY_ITEM_KEY. */
+#define BTRFS_BALANCE_ITEM_KEY	248
+
+/*
+ * The key type for tree items that are stored persistently, but do not need to
+ * exist for extended period of time. The items can exist in any tree.
+ *
+ * [subtype, BTRFS_TEMPORARY_ITEM_KEY, data]
+ *
+ * Existing items:
+ *
+ * - balance status item
+ *   (BTRFS_BALANCE_OBJECTID, BTRFS_TEMPORARY_ITEM_KEY, 0)
+ */
+#define BTRFS_TEMPORARY_ITEM_KEY	248
+
+/* Obsolete name, see BTRFS_PERSISTENT_ITEM_KEY */
+#define BTRFS_DEV_STATS_KEY		249
+
+/*
+ * The key type for tree items that are stored persistently and usually exist
+ * for a long period, eg. filesystem lifetime. The item kinds can be status
+ * information, stats or preference values. The item can exist in any tree.
+ *
+ * [subtype, BTRFS_PERSISTENT_ITEM_KEY, data]
+ *
+ * Existing items:
+ *
+ * - device statistics, store IO stats in the device tree, one key for all
+ *   stats
+ *   (BTRFS_DEV_STATS_OBJECTID, BTRFS_DEV_STATS_KEY, 0)
+ */
+#define BTRFS_PERSISTENT_ITEM_KEY	249
+
+/*
+ * Persistently stores the device replace state in the device tree.
+ *
+ * The key is built like this: (0, BTRFS_DEV_REPLACE_KEY, 0).
+ */
+#define BTRFS_DEV_REPLACE_KEY	250
+
+/*
+ * Stores items that allow to quickly map UUIDs to something else.
+ *
+ * These items are part of the filesystem UUID tree.
+ * The key is built like this:
+ * (UUID_upper_64_bits, BTRFS_UUID_KEY*, UUID_lower_64_bits).
+ */
+#define BTRFS_UUID_KEY_SUBVOL	251	/* for UUIDs assigned to subvols */
+#define BTRFS_UUID_KEY_RECEIVED_SUBVOL	252	/* for UUIDs assigned to
+						 * received subvols */
+
+/*
+ * String items are for debugging.
+ *
+ * They just store a short string of data in the FS.
+ */
+#define BTRFS_STRING_ITEM_KEY	253
+
+
+
+/* 32 bytes in various csum fields */
+#define BTRFS_CSUM_SIZE 32
+
+/* Csum types */
+enum btrfs_csum_type {
+	BTRFS_CSUM_TYPE_CRC32	= 0,
+	BTRFS_CSUM_TYPE_XXHASH	= 1,
+	BTRFS_CSUM_TYPE_SHA256	= 2,
+	BTRFS_CSUM_TYPE_BLAKE2	= 3,
+};
+
+/*
+ * Flags definitions for directory entry item type.
+ *
+ * Used by:
+ * struct btrfs_dir_item.type
+ *
+ * Values 0..7 must match common file type values in fs_types.h.
+ */
+#define BTRFS_FT_UNKNOWN	0
+#define BTRFS_FT_REG_FILE	1
+#define BTRFS_FT_DIR		2
+#define BTRFS_FT_CHRDEV		3
+#define BTRFS_FT_BLKDEV		4
+#define BTRFS_FT_FIFO		5
+#define BTRFS_FT_SOCK		6
+#define BTRFS_FT_SYMLINK	7
+#define BTRFS_FT_XATTR		8
+#define BTRFS_FT_MAX		9
+
+#define BTRFS_FSID_SIZE 16
+#define BTRFS_UUID_SIZE 16
+
+/*
+ * The key defines the order in the tree, and so it also defines (optimal)
+ * block layout.
+ *
+ * Objectid and offset are interpreted based on type.
+ * While normally for objectid, it either represents a root number, or an
+ * inode number.
+ *
+ * Type tells us things about the object, and is a kind of stream selector.
+ * Check the following URL for full references about btrfs_disk_key/btrfs_key:
+ * https://btrfs.wiki.kernel.org/index.php/Btree_Items
+ *
+ * btrfs_disk_key is in disk byte order.  struct btrfs_key is always
+ * in cpu native order.  Otherwise they are identical and their sizes
+ * should be the same (ie both packed)
+ */
+struct btrfs_disk_key {
+	__le64 objectid;
+	__u8 type;
+	__le64 offset;
+} __attribute__ ((__packed__));
+
+struct btrfs_key {
+	__u64 objectid;
+	__u8 type;
+	__u64 offset;
+} __attribute__ ((__packed__));
+
+struct btrfs_dev_item {
+	/* The internal btrfs device id */
+	__le64 devid;
+
+	/* Size of the device */
+	__le64 total_bytes;
+
+	/* Bytes used */
+	__le64 bytes_used;
+
+	/* Optimal io alignment for this device */
+	__le32 io_align;
+
+	/* Optimal io width for this device */
+	__le32 io_width;
+
+	/* Minimal io size for this device */
+	__le32 sector_size;
+
+	/* Type and info about this device */
+	__le64 type;
+
+	/* Expected generation for this device */
+	__le64 generation;
+
+	/*
+	 * Starting byte of this partition on the device,
+	 * to allow for stripe alignment in the future.
+	 */
+	__le64 start_offset;
+
+	/* Grouping information for allocation decisions */
+	__le32 dev_group;
+
+	/* Optimal seek speed 0-100 where 100 is fastest */
+	__u8 seek_speed;
+
+	/* Optimal bandwidth 0-100 where 100 is fastest */
+	__u8 bandwidth;
+
+	/* Btrfs generated uuid for this device */
+	__u8 uuid[BTRFS_UUID_SIZE];
+
+	/* UUID of FS who owns this device */
+	__u8 fsid[BTRFS_UUID_SIZE];
+} __attribute__ ((__packed__));
+
+struct btrfs_stripe {
+	__le64 devid;
+	__le64 offset;
+	__u8 dev_uuid[BTRFS_UUID_SIZE];
+} __attribute__ ((__packed__));
+
+struct btrfs_chunk {
+	/* Size of this chunk in bytes */
+	__le64 length;
+
+	/* Objectid of the root referencing this chunk */
+	__le64 owner;
+
+	__le64 stripe_len;
+	__le64 type;
+
+	/* Optimal io alignment for this chunk */
+	__le32 io_align;
+
+	/* Optimal io width for this chunk */
+	__le32 io_width;
+
+	/* Minimal io size for this chunk */
+	__le32 sector_size;
+
+	/*
+	 * 2^16 stripes is quite a lot, a second limit is the size of a single
+	 * item in the btree.
+	 */
+	__le16 num_stripes;
+
+	/* Sub stripes only matter for raid10 */
+	__le16 sub_stripes;
+	struct btrfs_stripe stripe;
+	/* additional stripes go here */
+} __attribute__ ((__packed__));
+
+#define BTRFS_FREE_SPACE_EXTENT	1
+#define BTRFS_FREE_SPACE_BITMAP	2
+
+struct btrfs_free_space_entry {
+	__le64 offset;
+	__le64 bytes;
+	__u8 type;
+} __attribute__ ((__packed__));
+
+struct btrfs_free_space_header {
+	struct btrfs_disk_key location;
+	__le64 generation;
+	__le64 num_entries;
+	__le64 num_bitmaps;
+} __attribute__ ((__packed__));
+
+#define BTRFS_HEADER_FLAG_WRITTEN	(1ULL << 0)
+#define BTRFS_HEADER_FLAG_RELOC		(1ULL << 1)
+
+/* Super block flags */
+/* Errors detected */
+#define BTRFS_SUPER_FLAG_ERROR		(1ULL << 2)
+
+#define BTRFS_SUPER_FLAG_SEEDING	(1ULL << 32)
+#define BTRFS_SUPER_FLAG_METADUMP	(1ULL << 33)
+#define BTRFS_SUPER_FLAG_METADUMP_V2	(1ULL << 34)
+#define BTRFS_SUPER_FLAG_CHANGING_FSID	(1ULL << 35)
+#define BTRFS_SUPER_FLAG_CHANGING_FSID_V2 (1ULL << 36)
+
+
+/*
+ * Items in the extent tree are used to record the objectid of the
+ * owner of the block and the number of references.
+ */
+struct btrfs_extent_item {
+	__le64 refs;
+	__le64 generation;
+	__le64 flags;
+} __attribute__ ((__packed__));
+
+struct btrfs_extent_item_v0 {
+	__le32 refs;
+} __attribute__ ((__packed__));
+
+
+#define BTRFS_EXTENT_FLAG_DATA		(1ULL << 0)
+#define BTRFS_EXTENT_FLAG_TREE_BLOCK	(1ULL << 1)
+
+/* Use full backrefs for extent pointers in the block */
+#define BTRFS_BLOCK_FLAG_FULL_BACKREF	(1ULL << 8)
+
+/*
+ * This flag is only used internally by scrub and may be changed at any time
+ * it is only declared here to avoid collisions.
+ */
+#define BTRFS_EXTENT_FLAG_SUPER		(1ULL << 48)
+
+struct btrfs_tree_block_info {
+	struct btrfs_disk_key key;
+	__u8 level;
+} __attribute__ ((__packed__));
+
+struct btrfs_extent_data_ref {
+	__le64 root;
+	__le64 objectid;
+	__le64 offset;
+	__le32 count;
+} __attribute__ ((__packed__));
+
+struct btrfs_shared_data_ref {
+	__le32 count;
+} __attribute__ ((__packed__));
+
+struct btrfs_extent_inline_ref {
+	__u8 type;
+	__le64 offset;
+} __attribute__ ((__packed__));
+
+/* Old style backrefs item */
+struct btrfs_extent_ref_v0 {
+	__le64 root;
+	__le64 generation;
+	__le64 objectid;
+	__le32 count;
+} __attribute__ ((__packed__));
+
+
+/* Dev extents record used space on individual devices.
+ *
+ * The owner field points back to the chunk allocation mapping tree that
+ * allocated the extent.
+ * The chunk tree uuid field is a way to double check the owner.
+ */
+struct btrfs_dev_extent {
+	__le64 chunk_tree;
+	__le64 chunk_objectid;
+	__le64 chunk_offset;
+	__le64 length;
+	__u8 chunk_tree_uuid[BTRFS_UUID_SIZE];
+} __attribute__ ((__packed__));
+
+struct btrfs_inode_ref {
+	__le64 index;
+	__le16 name_len;
+	/* Name goes here */
+} __attribute__ ((__packed__));
+
+struct btrfs_inode_extref {
+	__le64 parent_objectid;
+	__le64 index;
+	__le16 name_len;
+	__u8   name[0];
+	/* Name goes here */
+} __attribute__ ((__packed__));
+
+struct btrfs_timespec {
+	__le64 sec;
+	__le32 nsec;
+} __attribute__ ((__packed__));
+
+/* Inode flags */
+#define BTRFS_INODE_NODATASUM		(1 << 0)
+#define BTRFS_INODE_NODATACOW		(1 << 1)
+#define BTRFS_INODE_READONLY		(1 << 2)
+#define BTRFS_INODE_NOCOMPRESS		(1 << 3)
+#define BTRFS_INODE_PREALLOC		(1 << 4)
+#define BTRFS_INODE_SYNC		(1 << 5)
+#define BTRFS_INODE_IMMUTABLE		(1 << 6)
+#define BTRFS_INODE_APPEND		(1 << 7)
+#define BTRFS_INODE_NODUMP		(1 << 8)
+#define BTRFS_INODE_NOATIME		(1 << 9)
+#define BTRFS_INODE_DIRSYNC		(1 << 10)
+#define BTRFS_INODE_COMPRESS		(1 << 11)
+
+#define BTRFS_INODE_ROOT_ITEM_INIT	(1 << 31)
+
+#define BTRFS_INODE_FLAG_MASK						\
+	(BTRFS_INODE_NODATASUM |					\
+	 BTRFS_INODE_NODATACOW |					\
+	 BTRFS_INODE_READONLY |						\
+	 BTRFS_INODE_NOCOMPRESS |					\
+	 BTRFS_INODE_PREALLOC |						\
+	 BTRFS_INODE_SYNC |						\
+	 BTRFS_INODE_IMMUTABLE |					\
+	 BTRFS_INODE_APPEND |						\
+	 BTRFS_INODE_NODUMP |						\
+	 BTRFS_INODE_NOATIME |						\
+	 BTRFS_INODE_DIRSYNC |						\
+	 BTRFS_INODE_COMPRESS |						\
+	 BTRFS_INODE_ROOT_ITEM_INIT)
+
+struct btrfs_inode_item {
+	/* Nfs style generation number */
+	__le64 generation;
+	/* Transid that last touched this inode */
+	__le64 transid;
+	__le64 size;
+	__le64 nbytes;
+	__le64 block_group;
+	__le32 nlink;
+	__le32 uid;
+	__le32 gid;
+	__le32 mode;
+	__le64 rdev;
+	__le64 flags;
+
+	/* Modification sequence number for NFS */
+	__le64 sequence;
+
+	/*
+	 * A little future expansion, for more than this we can just grow the
+	 * inode item and version it
+	 */
+	__le64 reserved[4];
+	struct btrfs_timespec atime;
+	struct btrfs_timespec ctime;
+	struct btrfs_timespec mtime;
+	struct btrfs_timespec otime;
+} __attribute__ ((__packed__));
+
+struct btrfs_dir_log_item {
+	__le64 end;
+} __attribute__ ((__packed__));
+
+struct btrfs_dir_item {
+	struct btrfs_disk_key location;
+	__le64 transid;
+	__le16 data_len;
+	__le16 name_len;
+	__u8 type;
+} __attribute__ ((__packed__));
+
+#define BTRFS_ROOT_SUBVOL_RDONLY	(1ULL << 0)
+
+/*
+ * Internal in-memory flag that a subvolume has been marked for deletion but
+ * still visible as a directory
+ */
+#define BTRFS_ROOT_SUBVOL_DEAD		(1ULL << 48)
+
+struct btrfs_root_item {
+	struct btrfs_inode_item inode;
+	__le64 generation;
+	__le64 root_dirid;
+	__le64 bytenr;
+	__le64 byte_limit;
+	__le64 bytes_used;
+	__le64 last_snapshot;
+	__le64 flags;
+	__le32 refs;
+	struct btrfs_disk_key drop_progress;
+	__u8 drop_level;
+	__u8 level;
+
+	/*
+	 * The following fields appear after subvol_uuids+subvol_times
+	 * were introduced.
+	 */
+
+	/*
+	 * This generation number is used to test if the new fields are valid
+	 * and up to date while reading the root item. Every time the root item
+	 * is written out, the "generation" field is copied into this field. If
+	 * anyone ever mounted the fs with an older kernel, we will have
+	 * mismatching generation values here and thus must invalidate the
+	 * new fields. See btrfs_update_root and btrfs_find_last_root for
+	 * details.
+	 * The offset of generation_v2 is also used as the start for the memset
+	 * when invalidating the fields.
+	 */
+	__le64 generation_v2;
+	__u8 uuid[BTRFS_UUID_SIZE];
+	__u8 parent_uuid[BTRFS_UUID_SIZE];
+	__u8 received_uuid[BTRFS_UUID_SIZE];
+	__le64 ctransid; /* Updated when an inode changes */
+	__le64 otransid; /* Trans when created */
+	__le64 stransid; /* Trans when sent. Non-zero for received subvol. */
+	__le64 rtransid; /* Trans when received. Non-zero for received subvol.*/
+	struct btrfs_timespec ctime;
+	struct btrfs_timespec otime;
+	struct btrfs_timespec stime;
+	struct btrfs_timespec rtime;
+	__le64 reserved[8]; /* For future */
+} __attribute__ ((__packed__));
+
+/* This is used for both forward and backward root refs */
+struct btrfs_root_ref {
+	__le64 dirid;
+	__le64 sequence;
+	__le16 name_len;
+} __attribute__ ((__packed__));
+
+struct btrfs_disk_balance_args {
+	/*
+	 * Profiles to operate on.
+	 *
+	 * SINGLE is denoted by BTRFS_AVAIL_ALLOC_BIT_SINGLE.
+	 */
+	__le64 profiles;
+
+	/*
+	 * Usage filter
+	 * BTRFS_BALANCE_ARGS_USAGE with a single value means '0..N'
+	 * BTRFS_BALANCE_ARGS_USAGE_RANGE - range syntax, min..max
+	 */
+	union {
+		__le64 usage;
+		struct {
+			__le32 usage_min;
+			__le32 usage_max;
+		};
+	};
+
+	/* Devid filter */
+	__le64 devid;
+
+	/* Devid subset filter [pstart..pend) */
+	__le64 pstart;
+	__le64 pend;
+
+	/* Btrfs virtual address space subset filter [vstart..vend) */
+	__le64 vstart;
+	__le64 vend;
+
+	/*
+	 * Profile to convert to.
+	 *
+	 * SINGLE is denoted by BTRFS_AVAIL_ALLOC_BIT_SINGLE.
+	 */
+	__le64 target;
+
+	/* BTRFS_BALANCE_ARGS_* */
+	__le64 flags;
+
+	/*
+	 * BTRFS_BALANCE_ARGS_LIMIT with value 'limit'.
+	 * BTRFS_BALANCE_ARGS_LIMIT_RANGE - the extend version can use minimum
+	 * and maximum.
+	 */
+	union {
+		__le64 limit;
+		struct {
+			__le32 limit_min;
+			__le32 limit_max;
+		};
+	};
+
+	/*
+	 * Process chunks that cross stripes_min..stripes_max devices,
+	 * BTRFS_BALANCE_ARGS_STRIPES_RANGE.
+	 */
+	__le32 stripes_min;
+	__le32 stripes_max;
+
+	__le64 unused[6];
+} __attribute__ ((__packed__));
+
+/*
+ * Stores balance parameters to disk so that balance can be properly
+ * resumed after crash or unmount.
+ */
+struct btrfs_balance_item {
+	/* BTRFS_BALANCE_* */
+	__le64 flags;
+
+	struct btrfs_disk_balance_args data;
+	struct btrfs_disk_balance_args meta;
+	struct btrfs_disk_balance_args sys;
+
+	__le64 unused[4];
+} __attribute__ ((__packed__));
+
+enum {
+	BTRFS_FILE_EXTENT_INLINE   = 0,
+	BTRFS_FILE_EXTENT_REG      = 1,
+	BTRFS_FILE_EXTENT_PREALLOC = 2,
+	BTRFS_NR_FILE_EXTENT_TYPES = 3,
+};
+
+enum btrfs_compression_type {
+	BTRFS_COMPRESS_NONE  = 0,
+	BTRFS_COMPRESS_ZLIB  = 1,
+	BTRFS_COMPRESS_LZO   = 2,
+	BTRFS_COMPRESS_ZSTD  = 3,
+	BTRFS_NR_COMPRESS_TYPES = 4,
+};
+
+struct btrfs_file_extent_item {
+	/* Transaction id that created this extent */
+	__le64 generation;
+	/*
+	 * Max number of bytes to hold this extent in ram.
+	 *
+	 * When we split a compressed extent we can't know how big each of the
+	 * resulting pieces will be.  So, this is an upper limit on the size of
+	 * the extent in ram instead of an exact limit.
+	 */
+	__le64 ram_bytes;
+
+	/*
+	 * 32 bits for the various ways we might encode the data,
+	 * including compression and encryption.  If any of these
+	 * are set to something a given disk format doesn't understand
+	 * it is treated like an incompat flag for reading and writing,
+	 * but not for stat.
+	 */
+	__u8 compression;
+	__u8 encryption;
+	__le16 other_encoding; /* Spare for later use */
+
+	/* Are we inline data or a real extent? */
+	__u8 type;
+
+	/*
+	 * Disk space consumed by the extent, checksum blocks are not included
+	 * in these numbers
+	 *
+	 * At this offset in the structure, the inline extent data start.
+	 */
+	__le64 disk_bytenr;
+	__le64 disk_num_bytes;
+
+	/*
+	 * The logical offset inside the file extent.
+	 *
+	 * This allows a file extent to point into the middle of an existing
+	 * extent on disk, sharing it between two snapshots (useful if some
+	 * bytes in the middle of the extent have changed).
+	 */
+	__le64 offset;
+
+	/*
+	 * The logical number of bytes this file extent is referencing (no
+	 * csums included).
+	 *
+	 * This always reflects the size uncompressed and without encoding.
+	 */
+	__le64 num_bytes;
+
+} __attribute__ ((__packed__));
+
+struct btrfs_csum_item {
+	__u8 csum;
+} __attribute__ ((__packed__));
+
+enum btrfs_dev_stat_values {
+	/* Disk I/O failure stats */
+	BTRFS_DEV_STAT_WRITE_ERRS, /* EIO or EREMOTEIO from lower layers */
+	BTRFS_DEV_STAT_READ_ERRS, /* EIO or EREMOTEIO from lower layers */
+	BTRFS_DEV_STAT_FLUSH_ERRS, /* EIO or EREMOTEIO from lower layers */
+
+	/* Stats for indirect indications for I/O failures */
+	BTRFS_DEV_STAT_CORRUPTION_ERRS, /* Checksum error, bytenr error or
+					 * contents is illegal: this is an
+					 * indication that the block was damaged
+					 * during read or write, or written to
+					 * wrong location or read from wrong
+					 * location */
+	BTRFS_DEV_STAT_GENERATION_ERRS, /* An indication that blocks have not
+					 * been written */
+
+	BTRFS_DEV_STAT_VALUES_MAX
+};
+
+struct btrfs_dev_stats_item {
+	/*
+	 * Grow this item struct at the end for future enhancements and keep
+	 * the existing values unchanged.
+	 */
+	__le64 values[BTRFS_DEV_STAT_VALUES_MAX];
+} __attribute__ ((__packed__));
+
+#define BTRFS_DEV_REPLACE_ITEM_CONT_READING_FROM_SRCDEV_MODE_ALWAYS	0
+#define BTRFS_DEV_REPLACE_ITEM_CONT_READING_FROM_SRCDEV_MODE_AVOID	1
+
+struct btrfs_dev_replace_item {
+	/*
+	 * Grow this item struct at the end for future enhancements and keep
+	 * the existing values unchanged.
+	 */
+	__le64 src_devid;
+	__le64 cursor_left;
+	__le64 cursor_right;
+	__le64 cont_reading_from_srcdev_mode;
+
+	__le64 replace_state;
+	__le64 time_started;
+	__le64 time_stopped;
+	__le64 num_write_errors;
+	__le64 num_uncorrectable_read_errors;
+} __attribute__ ((__packed__));
+
+/* Different types of block groups (and chunks) */
+#define BTRFS_BLOCK_GROUP_DATA		(1ULL << 0)
+#define BTRFS_BLOCK_GROUP_SYSTEM	(1ULL << 1)
+#define BTRFS_BLOCK_GROUP_METADATA	(1ULL << 2)
+#define BTRFS_BLOCK_GROUP_RAID0		(1ULL << 3)
+#define BTRFS_BLOCK_GROUP_RAID1		(1ULL << 4)
+#define BTRFS_BLOCK_GROUP_DUP		(1ULL << 5)
+#define BTRFS_BLOCK_GROUP_RAID10	(1ULL << 6)
+#define BTRFS_BLOCK_GROUP_RAID5         (1ULL << 7)
+#define BTRFS_BLOCK_GROUP_RAID6         (1ULL << 8)
+#define BTRFS_BLOCK_GROUP_RAID1C3       (1ULL << 9)
+#define BTRFS_BLOCK_GROUP_RAID1C4       (1ULL << 10)
+#define BTRFS_BLOCK_GROUP_RESERVED	(BTRFS_AVAIL_ALLOC_BIT_SINGLE | \
+					 BTRFS_SPACE_INFO_GLOBAL_RSV)
+
+enum btrfs_raid_types {
+	BTRFS_RAID_RAID10,
+	BTRFS_RAID_RAID1,
+	BTRFS_RAID_DUP,
+	BTRFS_RAID_RAID0,
+	BTRFS_RAID_SINGLE,
+	BTRFS_RAID_RAID5,
+	BTRFS_RAID_RAID6,
+	BTRFS_RAID_RAID1C3,
+	BTRFS_RAID_RAID1C4,
+	BTRFS_NR_RAID_TYPES
+};
+
+#define BTRFS_BLOCK_GROUP_TYPE_MASK	(BTRFS_BLOCK_GROUP_DATA |    \
+					 BTRFS_BLOCK_GROUP_SYSTEM |  \
+					 BTRFS_BLOCK_GROUP_METADATA)
+
+#define BTRFS_BLOCK_GROUP_PROFILE_MASK	(BTRFS_BLOCK_GROUP_RAID0 |   \
+					 BTRFS_BLOCK_GROUP_RAID1 |   \
+					 BTRFS_BLOCK_GROUP_RAID1C3 | \
+					 BTRFS_BLOCK_GROUP_RAID1C4 | \
+					 BTRFS_BLOCK_GROUP_RAID5 |   \
+					 BTRFS_BLOCK_GROUP_RAID6 |   \
+					 BTRFS_BLOCK_GROUP_DUP |     \
+					 BTRFS_BLOCK_GROUP_RAID10)
+#define BTRFS_BLOCK_GROUP_RAID56_MASK	(BTRFS_BLOCK_GROUP_RAID5 |   \
+					 BTRFS_BLOCK_GROUP_RAID6)
+
+#define BTRFS_BLOCK_GROUP_RAID1_MASK	(BTRFS_BLOCK_GROUP_RAID1 |   \
+					 BTRFS_BLOCK_GROUP_RAID1C3 | \
+					 BTRFS_BLOCK_GROUP_RAID1C4)
+
+/*
+ * We need a bit for restriper to be able to tell when chunks of type
+ * SINGLE are available.  This "extended" profile format is used in
+ * fs_info->avail_*_alloc_bits (in-memory) and balance item fields
+ * (on-disk).  The corresponding on-disk bit in chunk.type is reserved
+ * to avoid remappings between two formats in future.
+ */
+#define BTRFS_AVAIL_ALLOC_BIT_SINGLE	(1ULL << 48)
+
+/*
+ * A fake block group type that is used to communicate global block reserve
+ * size to userspace via the SPACE_INFO ioctl.
+ */
+#define BTRFS_SPACE_INFO_GLOBAL_RSV	(1ULL << 49)
+
+#define BTRFS_EXTENDED_PROFILE_MASK	(BTRFS_BLOCK_GROUP_PROFILE_MASK | \
+					 BTRFS_AVAIL_ALLOC_BIT_SINGLE)
+
+static inline __u64 chunk_to_extended(__u64 flags)
+{
+	if ((flags & BTRFS_BLOCK_GROUP_PROFILE_MASK) == 0)
+		flags |= BTRFS_AVAIL_ALLOC_BIT_SINGLE;
+
+	return flags;
+}
+static inline __u64 extended_to_chunk(__u64 flags)
+{
+	return flags & ~BTRFS_AVAIL_ALLOC_BIT_SINGLE;
+}
+
+struct btrfs_block_group_item {
+	__le64 used;
+	__le64 chunk_objectid;
+	__le64 flags;
+} __attribute__ ((__packed__));
+
+struct btrfs_free_space_info {
+	__le32 extent_count;
+	__le32 flags;
+} __attribute__ ((__packed__));
+
+#define BTRFS_FREE_SPACE_USING_BITMAPS (1ULL << 0)
+
+#define BTRFS_QGROUP_LEVEL_SHIFT		48
+static inline __u64 btrfs_qgroup_level(__u64 qgroupid)
+{
+	return qgroupid >> BTRFS_QGROUP_LEVEL_SHIFT;
+}
+
+/* Is subvolume quota turned on? */
+#define BTRFS_QGROUP_STATUS_FLAG_ON		(1ULL << 0)
+
+/* Is qgroup rescan running? */
+#define BTRFS_QGROUP_STATUS_FLAG_RESCAN		(1ULL << 1)
+
+/*
+ * Some qgroup entries are known to be out of date, either because the
+ * configuration has changed in a way that makes a rescan necessary, or
+ * because the fs has been mounted with a non-qgroup-aware version.
+ */
+#define BTRFS_QGROUP_STATUS_FLAG_INCONSISTENT	(1ULL << 2)
+
+#define BTRFS_QGROUP_STATUS_VERSION        1
+
+struct btrfs_qgroup_status_item {
+	__le64 version;
+	/*
+	 * The generation is updated during every commit. As older
+	 * versions of btrfs are not aware of qgroups, it will be
+	 * possible to detect inconsistencies by checking the
+	 * generation on mount time.
+	 */
+	__le64 generation;
+
+	/* Flag definitions see above */
+	__le64 flags;
+
+	/*
+	 * Only used during scanning to record the progress of the scan.
+	 * It contains a logical address.
+	 */
+	__le64 rescan;
+} __attribute__ ((__packed__));
+
+struct btrfs_qgroup_info_item {
+	__le64 generation;
+	__le64 rfer;
+	__le64 rfer_cmpr;
+	__le64 excl;
+	__le64 excl_cmpr;
+} __attribute__ ((__packed__));
+
+/*
+ * Flags definition for qgroup limits
+ *
+ * Used by:
+ * struct btrfs_qgroup_limit.flags
+ * struct btrfs_qgroup_limit_item.flags
+ */
+#define BTRFS_QGROUP_LIMIT_MAX_RFER	(1ULL << 0)
+#define BTRFS_QGROUP_LIMIT_MAX_EXCL	(1ULL << 1)
+#define BTRFS_QGROUP_LIMIT_RSV_RFER	(1ULL << 2)
+#define BTRFS_QGROUP_LIMIT_RSV_EXCL	(1ULL << 3)
+#define BTRFS_QGROUP_LIMIT_RFER_CMPR	(1ULL << 4)
+#define BTRFS_QGROUP_LIMIT_EXCL_CMPR	(1ULL << 5)
+
+struct btrfs_qgroup_limit_item {
+	/* Only updated when any of the other values change. */
+	__le64 flags;
+	__le64 max_rfer;
+	__le64 max_excl;
+	__le64 rsv_rfer;
+	__le64 rsv_excl;
+} __attribute__ ((__packed__));
+
+/*
+ * Just in case we somehow lose the roots and are not able to mount,
+ * we store an array of the roots from previous transactions in the super.
+ */
+#define BTRFS_NUM_BACKUP_ROOTS 4
+struct btrfs_root_backup {
+	__le64 tree_root;
+	__le64 tree_root_gen;
+
+	__le64 chunk_root;
+	__le64 chunk_root_gen;
+
+	__le64 extent_root;
+	__le64 extent_root_gen;
+
+	__le64 fs_root;
+	__le64 fs_root_gen;
+
+	__le64 dev_root;
+	__le64 dev_root_gen;
+
+	__le64 csum_root;
+	__le64 csum_root_gen;
+
+	__le64 total_bytes;
+	__le64 bytes_used;
+	__le64 num_devices;
+	/* future */
+	__le64 unused_64[4];
+
+	u8 tree_root_level;
+	u8 chunk_root_level;
+	u8 extent_root_level;
+	u8 fs_root_level;
+	u8 dev_root_level;
+	u8 csum_root_level;
+	/* future and to align */
+	u8 unused_8[10];
+} __attribute__ ((__packed__));
+
+/*
+ * This is a very generous portion of the super block, giving us room to
+ * translate 14 chunks with 3 stripes each.
+ */
+#define BTRFS_SYSTEM_CHUNK_ARRAY_SIZE 2048
+
+#define BTRFS_LABEL_SIZE 256
+
+/* The super block basically lists the main trees of the FS. */
+struct btrfs_super_block {
+	/* The first 4 fields must match struct btrfs_header */
+	u8 csum[BTRFS_CSUM_SIZE];
+	/* FS specific UUID, visible to user */
+	u8 fsid[BTRFS_FSID_SIZE];
+	__le64 bytenr; /* this block number */
+	__le64 flags;
+
+	/* Allowed to be different from the btrfs_header from here own down. */
+	__le64 magic;
+	__le64 generation;
+	__le64 root;
+	__le64 chunk_root;
+	__le64 log_root;
+
+	/* This will help find the new super based on the log root. */
+	__le64 log_root_transid;
+	__le64 total_bytes;
+	__le64 bytes_used;
+	__le64 root_dir_objectid;
+	__le64 num_devices;
+	__le32 sectorsize;
+	__le32 nodesize;
+	__le32 __unused_leafsize;
+	__le32 stripesize;
+	__le32 sys_chunk_array_size;
+	__le64 chunk_root_generation;
+	__le64 compat_flags;
+	__le64 compat_ro_flags;
+	__le64 incompat_flags;
+	__le16 csum_type;
+	u8 root_level;
+	u8 chunk_root_level;
+	u8 log_root_level;
+	struct btrfs_dev_item dev_item;
+
+	char label[BTRFS_LABEL_SIZE];
+
+	__le64 cache_generation;
+	__le64 uuid_tree_generation;
+
+	/* The UUID written into btree blocks */
+	u8 metadata_uuid[BTRFS_FSID_SIZE];
+
+	/* Future expansion */
+	__le64 reserved[28];
+	u8 sys_chunk_array[BTRFS_SYSTEM_CHUNK_ARRAY_SIZE];
+	struct btrfs_root_backup super_roots[BTRFS_NUM_BACKUP_ROOTS];
+} __attribute__ ((__packed__));
+
+/*
+ * Feature flags
+ *
+ * Used by:
+ * struct btrfs_super_block::(compat|compat_ro|incompat)_flags
+ * struct btrfs_ioctl_feature_flags
+ */
+#define BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE		(1ULL << 0)
+
+/*
+ * Older kernels (< 4.9) on big-endian systems produced broken free space tree
+ * bitmaps, and btrfs-progs also used to corrupt the free space tree (versions
+ * < 4.7.3).  If this bit is clear, then the free space tree cannot be trusted.
+ * btrfs-progs can also intentionally clear this bit to ask the kernel to
+ * rebuild the free space tree, however this might not work on older kernels
+ * that do not know about this bit. If not sure, clear the cache manually on
+ * first mount when booting older kernel versions.
+ */
+#define BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE_VALID	(1ULL << 1)
+
+#define BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF	(1ULL << 0)
+#define BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL	(1ULL << 1)
+#define BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS	(1ULL << 2)
+#define BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO	(1ULL << 3)
+#define BTRFS_FEATURE_INCOMPAT_COMPRESS_ZSTD	(1ULL << 4)
+
+/*
+ * Older kernels tried to do bigger metadata blocks, but the
+ * code was pretty buggy.  Lets not let them try anymore.
+ */
+#define BTRFS_FEATURE_INCOMPAT_BIG_METADATA	(1ULL << 5)
+
+#define BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF	(1ULL << 6)
+#define BTRFS_FEATURE_INCOMPAT_RAID56		(1ULL << 7)
+#define BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA	(1ULL << 8)
+#define BTRFS_FEATURE_INCOMPAT_NO_HOLES		(1ULL << 9)
+#define BTRFS_FEATURE_INCOMPAT_METADATA_UUID	(1ULL << 10)
+#define BTRFS_FEATURE_INCOMPAT_RAID1C34		(1ULL << 11)
+
+/*
+ * Compat flags that we support.
+ *
+ * If any incompat flags are set other than the ones specified below then we
+ * will fail to mount.
+ */
+#define BTRFS_FEATURE_COMPAT_SUPP		0ULL
+#define BTRFS_FEATURE_COMPAT_SAFE_SET		0ULL
+#define BTRFS_FEATURE_COMPAT_SAFE_CLEAR		0ULL
+
+#define BTRFS_FEATURE_COMPAT_RO_SUPP			\
+	(BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE |	\
+	 BTRFS_FEATURE_COMPAT_RO_FREE_SPACE_TREE_VALID)
+
+#define BTRFS_FEATURE_COMPAT_RO_SAFE_SET	0ULL
+#define BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR	0ULL
+
+#define BTRFS_FEATURE_INCOMPAT_SUPP			\
+	(BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF |		\
+	 BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL |	\
+	 BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS |		\
+	 BTRFS_FEATURE_INCOMPAT_BIG_METADATA |		\
+	 BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO |		\
+	 BTRFS_FEATURE_INCOMPAT_COMPRESS_ZSTD |		\
+	 BTRFS_FEATURE_INCOMPAT_RAID56 |		\
+	 BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF |		\
+	 BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA |	\
+	 BTRFS_FEATURE_INCOMPAT_NO_HOLES	|	\
+	 BTRFS_FEATURE_INCOMPAT_METADATA_UUID	|	\
+	 BTRFS_FEATURE_INCOMPAT_RAID1C34)
+
+#define BTRFS_FEATURE_INCOMPAT_SAFE_SET			\
+	(BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF)
+#define BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR		0ULL
+
+#define BTRFS_BACKREF_REV_MAX		256
+#define BTRFS_BACKREF_REV_SHIFT		56
+#define BTRFS_BACKREF_REV_MASK		(((u64)BTRFS_BACKREF_REV_MAX - 1) << \
+					 BTRFS_BACKREF_REV_SHIFT)
+
+#define BTRFS_OLD_BACKREF_REV		0
+#define BTRFS_MIXED_BACKREF_REV		1
+
+#define BTRFS_MAX_LEVEL 8
+
+/* Every tree block (leaf or node) starts with this header. */
+struct btrfs_header {
+	/* These first four must match the super block */
+	u8 csum[BTRFS_CSUM_SIZE];
+	u8 fsid[BTRFS_FSID_SIZE]; /* FS specific uuid */
+	__le64 bytenr; /* Which block this node is supposed to live in */
+	__le64 flags;
+
+	/* Allowed to be different from the super from here on down. */
+	u8 chunk_tree_uuid[BTRFS_UUID_SIZE];
+	__le64 generation;
+	__le64 owner;
+	__le32 nritems;
+	u8 level;
+} __attribute__ ((__packed__));
+
+/*
+ * A leaf is full of items. Offset and size tell us where to find
+ * the item in the leaf (relative to the start of the data area).
+ */
+struct btrfs_item {
+	struct btrfs_disk_key key;
+	__le32 offset;
+	__le32 size;
+} __attribute__ ((__packed__));
+
+/*
+ * leaves have an item area and a data area:
+ * [item0, item1....itemN] [free space] [dataN...data1, data0]
+ *
+ * The data is separate from the items to get the keys closer together
+ * during searches.
+ */
+struct btrfs_leaf {
+	struct btrfs_header header;
+	struct btrfs_item items[];
+} __attribute__ ((__packed__));
+
+/*
+ * All non-leaf blocks are nodes, they hold only keys and pointers to children
+ * blocks.
+ */
+struct btrfs_key_ptr {
+	struct btrfs_disk_key key;
+	__le64 blockptr;
+	__le64 generation;
+} __attribute__ ((__packed__));
+
+struct btrfs_node {
+	struct btrfs_header header;
+	struct btrfs_key_ptr ptrs[];
+} __attribute__ ((__packed__));
+
+#endif /* __BTRFS_TREE_H__ */

diff --git a/fs/btrfs/root-tree.c b/fs/btrfs/root-tree.c
new file mode 100644
index 0000000..a39ad72
--- /dev/null
+++ b/fs/btrfs/root-tree.c

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "ctree.h"
+
+int btrfs_find_last_root(struct btrfs_root *root, u64 objectid,
+			struct btrfs_root_item *item, struct btrfs_key *key)
+{
+	struct btrfs_path *path;
+	struct btrfs_key search_key;
+	struct btrfs_key found_key;
+	struct extent_buffer *l;
+	int ret;
+	int slot;
+
+	path = btrfs_alloc_path();
+	if (!path)
+		return -ENOMEM;
+
+	search_key.objectid = objectid;
+	search_key.type = BTRFS_ROOT_ITEM_KEY;
+	search_key.offset = (u64)-1;
+
+	ret = btrfs_search_slot(NULL, root, &search_key, path, 0, 0);
+	if (ret < 0)
+		goto out;
+	if (path->slots[0] == 0) {
+		ret = -ENOENT;
+		goto out;
+	}
+
+	BUG_ON(ret == 0);
+	l = path->nodes[0];
+	slot = path->slots[0] - 1;
+	btrfs_item_key_to_cpu(l, &found_key, slot);
+	if (found_key.type != BTRFS_ROOT_ITEM_KEY ||
+	    found_key.objectid != objectid) {
+		ret = -ENOENT;
+		goto out;
+	}
+	read_extent_buffer(l, item, btrfs_item_ptr_offset(l, slot),
+			   sizeof(*item));
+	memcpy(key, &found_key, sizeof(found_key));
+	ret = 0;
+out:
+	btrfs_free_path(path);
+	return ret;
+}

diff --git a/fs/btrfs/root.c b/fs/btrfs/root.c
deleted file mode 100644
index 127b67f..0000000
--- a/fs/btrfs/root.c
+++ /dev/null

@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * BTRFS filesystem implementation for U-Boot
- *
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
- */
-
-#include "btrfs.h"
-
-static void read_root_item(struct btrfs_path *p, struct btrfs_root_item *item)
-{
-	u32 len;
-	int reset = 0;
-
-	len = btrfs_path_item_size(p);
-	memcpy(item, btrfs_path_item_ptr(p, struct btrfs_root_item), len);
-	btrfs_root_item_to_cpu(item);
-
-	if (len < sizeof(*item))
-		reset = 1;
-	if (!reset && item->generation != item->generation_v2) {
-		if (item->generation_v2 != 0)
-			printf("%s: generation != generation_v2 in root item",
-			       __func__);
-		reset = 1;
-	}
-	if (reset) {
-		memset(&item->generation_v2, 0,
-		       sizeof(*item) - offsetof(struct btrfs_root_item,
-						generation_v2));
-	}
-}
-
-int btrfs_find_root(u64 objectid, struct btrfs_root *root,
-		    struct btrfs_root_item *root_item)
-{
-	struct btrfs_path path;
-	struct btrfs_root_item my_root_item;
-
-	if (!btrfs_search_tree_key_type(&btrfs_info.tree_root, objectid,
-					BTRFS_ROOT_ITEM_KEY, &path))
-		return -1;
-
-	if (!root_item)
-		root_item = &my_root_item;
-	read_root_item(&path, root_item);
-
-	if (root) {
-		root->objectid = objectid;
-		root->bytenr = root_item->bytenr;
-		root->root_dirid = root_item->root_dirid;
-	}
-
-	btrfs_free_path(&path);
-	return 0;
-}
-
-u64 btrfs_lookup_root_ref(u64 subvolid, struct btrfs_root_ref *refp, char *name)
-{
-	struct btrfs_path path;
-	struct btrfs_key *key;
-	struct btrfs_root_ref *ref;
-	u64 res = -1ULL;
-
-	key = btrfs_search_tree_key_type(&btrfs_info.tree_root, subvolid,
-					       BTRFS_ROOT_BACKREF_KEY, &path);
-
-	if (!key)
-		return -1ULL;
-
-	ref = btrfs_path_item_ptr(&path, struct btrfs_root_ref);
-	btrfs_root_ref_to_cpu(ref);
-
-	if (refp)
-		*refp = *ref;
-
-	if (name) {
-		if (ref->name_len > BTRFS_VOL_NAME_MAX) {
-			printf("%s: volume name too long: %u\n", __func__,
-			       ref->name_len);
-			goto out;
-		}
-
-		memcpy(name, ref + 1, ref->name_len);
-	}
-
-	res = key->offset;
-out:
-	btrfs_free_path(&path);
-	return res;
-}
-

diff --git a/fs/btrfs/subvolume.c b/fs/btrfs/subvolume.c
index 06e54f3..2815673 100644
--- a/fs/btrfs/subvolume.c
+++ b/fs/btrfs/subvolume.c

@@ -5,126 +5,230 @@
  * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
  */
 
-#include "btrfs.h"
 #include <malloc.h>
+#include "ctree.h"
+#include "btrfs.h"
+#include "disk-io.h"
 
-static int get_subvol_name(u64 subvolid, char *name, int max_len)
+/*
+ * Resolve the path of ino inside subvolume @root into @path_ret.
+ *
+ * @path_ret must be at least PATH_MAX size.
+ */
+static int get_path_in_subvol(struct btrfs_root *root, u64 ino, char *path_ret)
 {
-	struct btrfs_root_ref rref;
-	struct btrfs_inode_ref iref;
-	struct btrfs_root root;
-	u64 dir;
-	char tmp[max(BTRFS_VOL_NAME_MAX, BTRFS_NAME_MAX)];
-	char *ptr;
+	struct btrfs_path path;
+	struct btrfs_key key;
+	char *tmp;
+	u64 cur = ino;
+	int ret = 0;
 
-	ptr = name + max_len - 1;
-	*ptr = '\0';
+	tmp = malloc(PATH_MAX);
+	if (!tmp)
+		return -ENOMEM;
+	tmp[0] = '\0';
 
-	while (subvolid != BTRFS_FS_TREE_OBJECTID) {
-		subvolid = btrfs_lookup_root_ref(subvolid, &rref, tmp);
+	btrfs_init_path(&path);
+	while (cur != BTRFS_FIRST_FREE_OBJECTID) {
+		struct btrfs_inode_ref *iref;
+		int name_len;
 
-		if (subvolid == -1ULL)
-			return -1;
+		btrfs_release_path(&path);
+		key.objectid = cur;
+		key.type = BTRFS_INODE_REF_KEY;
+		key.offset = (u64)-1;
 
-		ptr -= rref.name_len + 1;
-		if (ptr < name)
-			goto too_long;
+		ret = btrfs_search_slot(NULL, root, &key, &path, 0, 0);
+		/* Impossible */
+		if (ret == 0)
+			ret = -EUCLEAN;
+		if (ret < 0)
+			goto out;
+		ret = btrfs_previous_item(root, &path, cur,
+					  BTRFS_INODE_REF_KEY);
+		if (ret > 0)
+			ret = -ENOENT;
+		if (ret < 0)
+			goto out;
 
-		memcpy(ptr + 1, tmp, rref.name_len);
-		*ptr = '/';
+		strncpy(tmp, path_ret, PATH_MAX);
+		iref = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				      struct btrfs_inode_ref);
+		name_len = btrfs_inode_ref_name_len(path.nodes[0],
+						    iref);
+		if (name_len > BTRFS_NAME_LEN) {
+			ret = -ENAMETOOLONG;
+			goto out;
+		}
+		read_extent_buffer(path.nodes[0], path_ret,
+				   (unsigned long)(iref + 1), name_len);
+		path_ret[name_len] = '/';
+		path_ret[name_len + 1] = '\0';
+		strncat(path_ret, tmp, PATH_MAX);
 
-		if (btrfs_find_root(subvolid, &root, NULL))
-			return -1;
+		btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+		cur = key.offset;
+	}
+out:
+	btrfs_release_path(&path);
+	free(tmp);
+	return ret;
+}
 
-		dir = rref.dirid;
+static int list_one_subvol(struct btrfs_root *root, char *path_ret)
+{
+	struct btrfs_fs_info *fs_info = root->fs_info;
+	struct btrfs_root *tree_root = fs_info->tree_root;
+	struct btrfs_path path;
+	struct btrfs_key key;
+	char *tmp;
+	u64 cur = root->root_key.objectid;
+	int ret = 0;
 
-		while (dir != BTRFS_FIRST_FREE_OBJECTID) {
-			dir = btrfs_lookup_inode_ref(&root, dir, &iref, tmp);
+	tmp = malloc(PATH_MAX);
+	if (!tmp)
+		return -ENOMEM;
+	tmp[0] = '\0';
+	path_ret[0] = '\0';
+	btrfs_init_path(&path);
+	while (cur != BTRFS_FS_TREE_OBJECTID) {
+		struct btrfs_root_ref *rr;
+		struct btrfs_key location;
+		int name_len;
+		u64 ino;
 
-			if (dir == -1ULL)
-				return -1;
+		key.objectid = cur;
+		key.type = BTRFS_ROOT_BACKREF_KEY;
+		key.offset = (u64)-1;
+		btrfs_release_path(&path);
 
-			ptr -= iref.name_len + 1;
-			if (ptr < name)
-				goto too_long;
+		ret = btrfs_search_slot(NULL, tree_root, &key, &path, 0, 0);
+		if (ret == 0)
+			ret = -EUCLEAN;
+		if (ret < 0)
+			goto out;
+		ret = btrfs_previous_item(tree_root, &path, cur,
+					  BTRFS_ROOT_BACKREF_KEY);
+		if (ret > 0)
+			ret = -ENOENT;
+		if (ret < 0)
+			goto out;
 
-			memcpy(ptr + 1, tmp, iref.name_len);
-			*ptr = '/';
+		/* Get the subvolume name */
+		rr = btrfs_item_ptr(path.nodes[0], path.slots[0],
+				    struct btrfs_root_ref);
+		strncpy(tmp, path_ret, PATH_MAX);
+		name_len = btrfs_root_ref_name_len(path.nodes[0], rr);
+		if (name_len > BTRFS_NAME_LEN) {
+			ret = -ENAMETOOLONG;
+			goto out;
 		}
-	}
+		ino = btrfs_root_ref_dirid(path.nodes[0], rr);
+		read_extent_buffer(path.nodes[0], path_ret,
+				   (unsigned long)(rr + 1), name_len);
+		path_ret[name_len] = '/';
+		path_ret[name_len + 1] = '\0';
+		strncat(path_ret, tmp, PATH_MAX);
 
-	if (ptr == name + max_len - 1) {
-		name[0] = '/';
-		name[1] = '\0';
-	} else {
-		memmove(name, ptr, name + max_len - ptr);
+		/* Get the path inside the parent subvolume */
+		btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+		location.objectid = key.offset;
+		location.type = BTRFS_ROOT_ITEM_KEY;
+		location.offset = (u64)-1;
+		root = btrfs_read_fs_root(fs_info, &location);
+		if (IS_ERR(root)) {
+			ret = PTR_ERR(root);
+			goto out;
+		}
+		ret = get_path_in_subvol(root, ino, path_ret);
+		if (ret < 0)
+			goto out;
+		cur = key.offset;
 	}
-
-	return 0;
-
-too_long:
-	printf("%s: subvolume name too long\n", __func__);
-	return -1;
+	/* Add the leading '/' */
+	strncpy(tmp, path_ret, PATH_MAX);
+	strncpy(path_ret, "/", PATH_MAX);
+	strncat(path_ret, tmp, PATH_MAX);
+out:
+	btrfs_release_path(&path);
+	free(tmp);
+	return ret;
 }
 
-u64 btrfs_get_default_subvol_objectid(void)
+static int list_subvolums(struct btrfs_fs_info *fs_info)
 {
-	struct btrfs_dir_item item;
+	struct btrfs_root *tree_root = fs_info->tree_root;
+	struct btrfs_root *root;
+	struct btrfs_path path;
+	struct btrfs_key key;
+	char *result;
+	int ret = 0;
 
-	if (btrfs_lookup_dir_item(&btrfs_info.tree_root,
-				  btrfs_info.sb.root_dir_objectid, "default", 7,
-				  &item))
-		return BTRFS_FS_TREE_OBJECTID;
-	return item.location.objectid;
-}
+	result = malloc(PATH_MAX);
+	if (!result)
+		return -ENOMEM;
 
-static void list_subvols(u64 tree, char *nameptr, int max_name_len, int level)
-{
-	struct btrfs_key key, *found_key;
-	struct btrfs_path path;
-	struct btrfs_root_ref *ref;
-	int res;
+	ret = list_one_subvol(fs_info->fs_root, result);
+	if (ret < 0)
+		goto out;
+	root = fs_info->fs_root;
+	printf("ID %llu gen %llu path %.*s\n",
+		root->root_key.objectid, btrfs_root_generation(&root->root_item),
+		PATH_MAX, result);
 
-	key.objectid = tree;
-	key.type = BTRFS_ROOT_REF_KEY;
+	key.objectid = BTRFS_FIRST_FREE_OBJECTID;
+	key.type = BTRFS_ROOT_ITEM_KEY;
 	key.offset = 0;
+	btrfs_init_path(&path);
+	ret = btrfs_search_slot(NULL, tree_root, &key, &path, 0, 0);
+	if (ret < 0)
+		goto out;
+	while (1) {
+		if (path.slots[0] >= btrfs_header_nritems(path.nodes[0]))
+			goto next;
 
-	if (btrfs_search_tree(&btrfs_info.tree_root, &key, &path))
-		return;
-
-	do {
-		found_key = btrfs_path_leaf_key(&path);
-		if (btrfs_comp_keys_type(&key, found_key))
+		btrfs_item_key_to_cpu(path.nodes[0], &key, path.slots[0]);
+		if (key.objectid > BTRFS_LAST_FREE_OBJECTID)
 			break;
-
-		ref = btrfs_path_item_ptr(&path, struct btrfs_root_ref);
-		btrfs_root_ref_to_cpu(ref);
-
-		printf("ID %llu parent %llu name ", found_key->offset, tree);
-		if (nameptr && !get_subvol_name(found_key->offset, nameptr,
-						max_name_len))
-			printf("%s\n", nameptr);
-		else
-			printf("%.*s\n", (int) ref->name_len,
-			       (const char *) (ref + 1));
-
-		if (level > 0)
-			list_subvols(found_key->offset, nameptr, max_name_len,
-				     level - 1);
-		else
-			printf("%s: Too much recursion, maybe skipping some "
-			       "subvolumes\n", __func__);
-	} while (!(res = btrfs_next_slot(&path)));
-
-	btrfs_free_path(&path);
+		if (key.objectid < BTRFS_FIRST_FREE_OBJECTID ||
+		    key.type != BTRFS_ROOT_ITEM_KEY)
+			goto next;
+		key.offset = (u64)-1;
+		root = btrfs_read_fs_root(fs_info, &key);
+		if (IS_ERR(root)) {
+			ret = PTR_ERR(root);
+			if (ret == -ENOENT)
+				goto next;
+		}
+		ret = list_one_subvol(root, result);
+		if (ret < 0)
+			goto out;
+		printf("ID %llu gen %llu path %.*s\n",
+			root->root_key.objectid,
+			btrfs_root_generation(&root->root_item),
+			PATH_MAX, result);
+next:
+		ret = btrfs_next_item(tree_root, &path);
+		if (ret < 0)
+			goto out;
+		if (ret > 0) {
+			ret = 0;
+			break;
+		}
+	}
+out:
+	free(result);
+	return ret;
 }
 
 void btrfs_list_subvols(void)
 {
-	char *nameptr = malloc(4096);
+	struct btrfs_fs_info *fs_info = current_fs_info;
+	int ret;
 
-	list_subvols(BTRFS_FS_TREE_OBJECTID, nameptr, nameptr ? 4096 : 0, 40);
-
-	if (nameptr)
-		free(nameptr);
+	if (!fs_info)
+		return;
+	ret = list_subvolums(fs_info);
+	if (ret < 0)
+		error("failed to list subvolume: %d", ret);
 }

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
deleted file mode 100644
index 913a4d4..0000000
--- a/fs/btrfs/super.c
+++ /dev/null

@@ -1,257 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * BTRFS filesystem implementation for U-Boot
- *
- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
- */
-
-#include <common.h>
-#include <log.h>
-#include <memalign.h>
-#include <part.h>
-#include <linux/compat.h>
-#include "btrfs.h"
-
-#define BTRFS_SUPER_FLAG_SUPP	(BTRFS_HEADER_FLAG_WRITTEN	\
-				 | BTRFS_HEADER_FLAG_RELOC	\
-				 | BTRFS_SUPER_FLAG_ERROR	\
-				 | BTRFS_SUPER_FLAG_SEEDING	\
-				 | BTRFS_SUPER_FLAG_METADUMP)
-
-#define BTRFS_SUPER_INFO_SIZE	4096
-
-/*
- * checks if a valid root backup is present.
- * considers the case when all root backups empty valid.
- * returns -1 in case of invalid root backup and 0 for valid.
- */
-static int btrfs_check_super_roots(struct btrfs_super_block *sb)
-{
-	struct btrfs_root_backup *root_backup;
-	int i, newest = -1;
-	int num_empty = 0;
-
-	for (i = 0; i < BTRFS_NUM_BACKUP_ROOTS; ++i) {
-		root_backup = sb->super_roots + i;
-
-		if (root_backup->tree_root == 0 && root_backup->tree_root_gen == 0)
-			num_empty++;
-
-		if (root_backup->tree_root_gen == sb->generation)
-			newest = i;
-	}
-
-	if (num_empty == BTRFS_NUM_BACKUP_ROOTS) {
-		return 0;
-	} else if (newest >= 0) {
-		return 0;
-	}
-
-	return -1;
-}
-
-static inline int is_power_of_2(u64 x)
-{
-	return !(x & (x - 1));
-}
-
-static int btrfs_check_super_csum(char *raw_disk_sb)
-{
-	struct btrfs_super_block *disk_sb =
-		(struct btrfs_super_block *) raw_disk_sb;
-	u16 csum_type = le16_to_cpu(disk_sb->csum_type);
-
-	if (csum_type == BTRFS_CSUM_TYPE_CRC32) {
-		u32 crc = ~(u32) 0;
-		const int csum_size = sizeof(crc);
-		char result[csum_size];
-
-		crc = btrfs_csum_data(raw_disk_sb + BTRFS_CSUM_SIZE, crc,
-				      BTRFS_SUPER_INFO_SIZE - BTRFS_CSUM_SIZE);
-		btrfs_csum_final(crc, result);
-
-		if (memcmp(raw_disk_sb, result, csum_size))
-			return -1;
-	} else {
-		return -1;
-	}
-
-	return 0;
-}
-
-static int btrfs_check_super(struct btrfs_super_block *sb)
-{
-	int ret = 0;
-
-	if (sb->flags & ~BTRFS_SUPER_FLAG_SUPP) {
-		printf("%s: Unsupported flags: %llu\n", __func__,
-		       sb->flags & ~BTRFS_SUPER_FLAG_SUPP);
-	}
-
-	if (sb->root_level > BTRFS_MAX_LEVEL) {
-		printf("%s: tree_root level too big: %d >= %d\n", __func__,
-		       sb->root_level, BTRFS_MAX_LEVEL);
-		ret = -1;
-	}
-
-	if (sb->chunk_root_level > BTRFS_MAX_LEVEL) {
-		printf("%s: chunk_root level too big: %d >= %d\n", __func__,
-		       sb->chunk_root_level, BTRFS_MAX_LEVEL);
-		ret = -1;
-	}
-
-	if (sb->log_root_level > BTRFS_MAX_LEVEL) {
-		printf("%s: log_root level too big: %d >= %d\n", __func__,
-		       sb->log_root_level, BTRFS_MAX_LEVEL);
-		ret = -1;
-	}
-
-	if (!is_power_of_2(sb->sectorsize) || sb->sectorsize < 4096 ||
-	    sb->sectorsize > BTRFS_MAX_METADATA_BLOCKSIZE) {
-		printf("%s: invalid sectorsize %u\n", __func__,
-		       sb->sectorsize);
-		ret = -1;
-	}
-
-	if (!is_power_of_2(sb->nodesize) || sb->nodesize < sb->sectorsize ||
-	    sb->nodesize > BTRFS_MAX_METADATA_BLOCKSIZE) {
-		printf("%s: invalid nodesize %u\n", __func__, sb->nodesize);
-		ret = -1;
-	}
-
-	if (sb->nodesize != sb->__unused_leafsize) {
-		printf("%s: invalid leafsize %u, should be %u\n", __func__,
-		       sb->__unused_leafsize, sb->nodesize);
-		ret = -1;
-	}
-
-	if (!IS_ALIGNED(sb->root, sb->sectorsize)) {
-		printf("%s: tree_root block unaligned: %llu\n", __func__,
-		       sb->root);
-		ret = -1;
-	}
-
-	if (!IS_ALIGNED(sb->chunk_root, sb->sectorsize)) {
-		printf("%s: chunk_root block unaligned: %llu\n", __func__,
-		       sb->chunk_root);
-		ret = -1;
-	}
-
-	if (!IS_ALIGNED(sb->log_root, sb->sectorsize)) {
-		printf("%s: log_root block unaligned: %llu\n", __func__,
-		       sb->log_root);
-		ret = -1;
-	}
-
-	if (memcmp(sb->fsid, sb->dev_item.fsid, BTRFS_UUID_SIZE) != 0) {
-		printf("%s: dev_item UUID does not match fsid\n", __func__);
-		ret = -1;
-	}
-
-	if (sb->bytes_used < 6*sb->nodesize) {
-		printf("%s: bytes_used is too small %llu\n", __func__,
-		       sb->bytes_used);
-		ret = -1;
-	}
-
-	if (!is_power_of_2(sb->stripesize)) {
-		printf("%s: invalid stripesize %u\n", __func__, sb->stripesize);
-		ret = -1;
-	}
-
-	if (sb->sys_chunk_array_size > BTRFS_SYSTEM_CHUNK_ARRAY_SIZE) {
-		printf("%s: system chunk array too big %u > %u\n", __func__,
-		       sb->sys_chunk_array_size, BTRFS_SYSTEM_CHUNK_ARRAY_SIZE);
-		ret = -1;
-	}
-
-	if (sb->sys_chunk_array_size < sizeof(struct btrfs_key) +
-	    sizeof(struct btrfs_chunk)) {
-		printf("%s: system chunk array too small %u < %zu\n", __func__,
-		       sb->sys_chunk_array_size, sizeof(struct btrfs_key)
-		       + sizeof(struct btrfs_chunk));
-		ret = -1;
-	}
-
-	return ret;
-}
-
-int btrfs_read_superblock(void)
-{
-	const u64 superblock_offsets[4] = {
-		0x10000ull,
-		0x4000000ull,
-		0x4000000000ull,
-		0x4000000000000ull
-	};
-	ALLOC_CACHE_ALIGN_BUFFER(char, raw_sb, BTRFS_SUPER_INFO_SIZE);
-	struct btrfs_super_block *sb = (struct btrfs_super_block *) raw_sb;
-	u64 dev_total_bytes;
-	int i;
-
-	dev_total_bytes = (u64) btrfs_part_info->size * btrfs_part_info->blksz;
-
-	btrfs_info.sb.generation = 0;
-
-	for (i = 0; i < 4; ++i) {
-		if (superblock_offsets[i] + sizeof(sb) > dev_total_bytes)
-			break;
-
-		if (!btrfs_devread(superblock_offsets[i], BTRFS_SUPER_INFO_SIZE,
-				   raw_sb))
-			break;
-
-		if (btrfs_check_super_csum(raw_sb)) {
-			debug("%s: invalid checksum at superblock mirror %i\n",
-			      __func__, i);
-			continue;
-		}
-
-		btrfs_super_block_to_cpu(sb);
-
-		if (sb->magic != BTRFS_MAGIC) {
-			debug("%s: invalid BTRFS magic 0x%016llX at "
-			      "superblock mirror %i\n", __func__, sb->magic, i);
-		} else if (sb->bytenr != superblock_offsets[i]) {
-			printf("%s: invalid bytenr 0x%016llX (expected "
-			       "0x%016llX) at superblock mirror %i\n",
-			       __func__, sb->bytenr, superblock_offsets[i], i);
-		} else if (btrfs_check_super(sb)) {
-			printf("%s: Checking superblock mirror %i failed\n",
-			       __func__, i);
-		} else if (sb->generation > btrfs_info.sb.generation) {
-			memcpy(&btrfs_info.sb, sb, sizeof(*sb));
-		} else {
-			/* Nothing */
-		}
-	}
-
-	if (!btrfs_info.sb.generation) {
-		debug("%s: No valid BTRFS superblock found!\n", __func__);
-		return -1;
-	}
-
-	if (btrfs_check_super_roots(&btrfs_info.sb)) {
-		printf("%s: No valid root_backup found!\n", __func__);
-		return -1;
-	}
-
-	if (sb->sectorsize != PAGE_SIZE) {
-		printf(
-	"%s: Unsupported sector size (%u), only supports %u as sector size\n",
-			__func__, sb->sectorsize, PAGE_SIZE);
-		return -1;
-	}
-
-	if (btrfs_info.sb.num_devices != 1) {
-		printf("%s: Unsupported number of devices (%lli). This driver "
-		       "only supports filesystem on one device.\n", __func__,
-		       btrfs_info.sb.num_devices);
-		return -1;
-	}
-
-	debug("Chosen superblock with generation = %llu\n",
-	      btrfs_info.sb.generation);
-
-	return 0;
-}

diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
new file mode 100644
index 0000000..fcf52d4
--- /dev/null
+++ b/fs/btrfs/volumes.c

@@ -0,0 +1,1173 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <stdlib.h>
+#include <common.h>
+#include <fs_internal.h>
+#include "ctree.h"
+#include "disk-io.h"
+#include "volumes.h"
+#include "extent-io.h"
+
+const struct btrfs_raid_attr btrfs_raid_array[BTRFS_NR_RAID_TYPES] = {
+	[BTRFS_RAID_RAID10] = {
+		.sub_stripes	= 2,
+		.dev_stripes	= 1,
+		.devs_max	= 0,	/* 0 == as many as possible */
+		.devs_min	= 4,
+		.tolerated_failures = 1,
+		.devs_increment	= 2,
+		.ncopies	= 2,
+		.nparity	= 0,
+		.raid_name	= "raid10",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID10,
+	},
+	[BTRFS_RAID_RAID1] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 2,
+		.devs_min	= 2,
+		.tolerated_failures = 1,
+		.devs_increment	= 2,
+		.ncopies	= 2,
+		.nparity	= 0,
+		.raid_name	= "raid1",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID1,
+	},
+	[BTRFS_RAID_RAID1C3] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 3,
+		.devs_min	= 3,
+		.tolerated_failures = 2,
+		.devs_increment	= 3,
+		.ncopies	= 3,
+		.raid_name	= "raid1c3",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID1C3,
+	},
+	[BTRFS_RAID_RAID1C4] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 4,
+		.devs_min	= 4,
+		.tolerated_failures = 3,
+		.devs_increment	= 4,
+		.ncopies	= 4,
+		.raid_name	= "raid1c4",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID1C4,
+	},
+	[BTRFS_RAID_DUP] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 2,
+		.devs_max	= 1,
+		.devs_min	= 1,
+		.tolerated_failures = 0,
+		.devs_increment	= 1,
+		.ncopies	= 2,
+		.nparity	= 0,
+		.raid_name	= "dup",
+		.bg_flag	= BTRFS_BLOCK_GROUP_DUP,
+	},
+	[BTRFS_RAID_RAID0] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 0,
+		.devs_min	= 2,
+		.tolerated_failures = 0,
+		.devs_increment	= 1,
+		.ncopies	= 1,
+		.nparity	= 0,
+		.raid_name	= "raid0",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID0,
+	},
+	[BTRFS_RAID_SINGLE] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 1,
+		.devs_min	= 1,
+		.tolerated_failures = 0,
+		.devs_increment	= 1,
+		.ncopies	= 1,
+		.nparity	= 0,
+		.raid_name	= "single",
+		.bg_flag	= 0,
+	},
+	[BTRFS_RAID_RAID5] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 0,
+		.devs_min	= 2,
+		.tolerated_failures = 1,
+		.devs_increment	= 1,
+		.ncopies	= 1,
+		.nparity	= 1,
+		.raid_name	= "raid5",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID5,
+	},
+	[BTRFS_RAID_RAID6] = {
+		.sub_stripes	= 1,
+		.dev_stripes	= 1,
+		.devs_max	= 0,
+		.devs_min	= 3,
+		.tolerated_failures = 2,
+		.devs_increment	= 1,
+		.ncopies	= 1,
+		.nparity	= 2,
+		.raid_name	= "raid6",
+		.bg_flag	= BTRFS_BLOCK_GROUP_RAID6,
+	},
+};
+
+struct stripe {
+	struct btrfs_device *dev;
+	u64 physical;
+};
+
+static inline int nr_parity_stripes(struct map_lookup *map)
+{
+	if (map->type & BTRFS_BLOCK_GROUP_RAID5)
+		return 1;
+	else if (map->type & BTRFS_BLOCK_GROUP_RAID6)
+		return 2;
+	else
+		return 0;
+}
+
+static inline int nr_data_stripes(struct map_lookup *map)
+{
+	return map->num_stripes - nr_parity_stripes(map);
+}
+
+#define is_parity_stripe(x) ( ((x) == BTRFS_RAID5_P_STRIPE) || ((x) == BTRFS_RAID6_Q_STRIPE) )
+
+static LIST_HEAD(fs_uuids);
+
+/*
+ * Find a device specified by @devid or @uuid in the list of @fs_devices, or
+ * return NULL.
+ *
+ * If devid and uuid are both specified, the match must be exact, otherwise
+ * only devid is used.
+ */
+static struct btrfs_device *find_device(struct btrfs_fs_devices *fs_devices,
+		u64 devid, u8 *uuid)
+{
+	struct list_head *head = &fs_devices->devices;
+	struct btrfs_device *dev;
+
+	list_for_each_entry(dev, head, dev_list) {
+		if (dev->devid == devid &&
+		    (!uuid || !memcmp(dev->uuid, uuid, BTRFS_UUID_SIZE))) {
+			return dev;
+		}
+	}
+	return NULL;
+}
+
+static struct btrfs_fs_devices *find_fsid(u8 *fsid, u8 *metadata_uuid)
+{
+	struct btrfs_fs_devices *fs_devices;
+
+	list_for_each_entry(fs_devices, &fs_uuids, list) {
+		if (metadata_uuid && (memcmp(fsid, fs_devices->fsid,
+					     BTRFS_FSID_SIZE) == 0) &&
+		    (memcmp(metadata_uuid, fs_devices->metadata_uuid,
+			    BTRFS_FSID_SIZE) == 0)) {
+			return fs_devices;
+		} else if (memcmp(fsid, fs_devices->fsid, BTRFS_FSID_SIZE) == 0){
+			return fs_devices;
+		}
+	}
+	return NULL;
+}
+
+static int device_list_add(struct btrfs_super_block *disk_super,
+			   u64 devid, struct blk_desc *desc,
+			   struct disk_partition *part,
+			   struct btrfs_fs_devices **fs_devices_ret)
+{
+	struct btrfs_device *device;
+	struct btrfs_fs_devices *fs_devices;
+	u64 found_transid = btrfs_super_generation(disk_super);
+	bool metadata_uuid = (btrfs_super_incompat_flags(disk_super) &
+		BTRFS_FEATURE_INCOMPAT_METADATA_UUID);
+
+	if (metadata_uuid)
+		fs_devices = find_fsid(disk_super->fsid,
+				       disk_super->metadata_uuid);
+	else
+		fs_devices = find_fsid(disk_super->fsid, NULL);
+
+	if (!fs_devices) {
+		fs_devices = kzalloc(sizeof(*fs_devices), GFP_NOFS);
+		if (!fs_devices)
+			return -ENOMEM;
+		INIT_LIST_HEAD(&fs_devices->devices);
+		list_add(&fs_devices->list, &fs_uuids);
+		memcpy(fs_devices->fsid, disk_super->fsid, BTRFS_FSID_SIZE);
+		if (metadata_uuid)
+			memcpy(fs_devices->metadata_uuid,
+			       disk_super->metadata_uuid, BTRFS_FSID_SIZE);
+		else
+			memcpy(fs_devices->metadata_uuid, fs_devices->fsid,
+			       BTRFS_FSID_SIZE);
+
+		fs_devices->latest_devid = devid;
+		fs_devices->latest_trans = found_transid;
+		fs_devices->lowest_devid = (u64)-1;
+		device = NULL;
+	} else {
+		device = find_device(fs_devices, devid,
+				    disk_super->dev_item.uuid);
+	}
+	if (!device) {
+		device = kzalloc(sizeof(*device), GFP_NOFS);
+		if (!device) {
+			/* we can safely leave the fs_devices entry around */
+			return -ENOMEM;
+		}
+		device->devid = devid;
+		device->desc = desc;
+		device->part = part;
+		device->generation = found_transid;
+		memcpy(device->uuid, disk_super->dev_item.uuid,
+		       BTRFS_UUID_SIZE);
+		device->total_devs = btrfs_super_num_devices(disk_super);
+		device->super_bytes_used = btrfs_super_bytes_used(disk_super);
+		device->total_bytes =
+			btrfs_stack_device_total_bytes(&disk_super->dev_item);
+		device->bytes_used =
+			btrfs_stack_device_bytes_used(&disk_super->dev_item);
+		list_add(&device->dev_list, &fs_devices->devices);
+		device->fs_devices = fs_devices;
+	} else if (!device->desc || !device->part) {
+		/*
+		 * The existing device has newer generation, so this one could
+		 * be a stale one, don't add it.
+		 */
+		if (found_transid < device->generation) {
+			error(
+	"adding devid %llu gen %llu but found an existing device gen %llu",
+				device->devid, found_transid,
+				device->generation);
+			return -EEXIST;
+		} else {
+			device->desc = desc;
+			device->part = part;
+		}
+	}
+
+
+	if (found_transid > fs_devices->latest_trans) {
+		fs_devices->latest_devid = devid;
+		fs_devices->latest_trans = found_transid;
+	}
+	if (fs_devices->lowest_devid > devid) {
+		fs_devices->lowest_devid = devid;
+	}
+	*fs_devices_ret = fs_devices;
+	return 0;
+}
+
+int btrfs_close_devices(struct btrfs_fs_devices *fs_devices)
+{
+	struct btrfs_fs_devices *seed_devices;
+	struct btrfs_device *device;
+	int ret = 0;
+
+again:
+	if (!fs_devices)
+		return 0;
+	while (!list_empty(&fs_devices->devices)) {
+		device = list_entry(fs_devices->devices.next,
+				    struct btrfs_device, dev_list);
+		list_del(&device->dev_list);
+		/* free the memory */
+		free(device);
+	}
+
+	seed_devices = fs_devices->seed;
+	fs_devices->seed = NULL;
+	if (seed_devices) {
+		struct btrfs_fs_devices *orig;
+
+		orig = fs_devices;
+		fs_devices = seed_devices;
+		list_del(&orig->list);
+		free(orig);
+		goto again;
+	} else {
+		list_del(&fs_devices->list);
+		free(fs_devices);
+	}
+
+	return ret;
+}
+
+void btrfs_close_all_devices(void)
+{
+	struct btrfs_fs_devices *fs_devices;
+
+	while (!list_empty(&fs_uuids)) {
+		fs_devices = list_entry(fs_uuids.next, struct btrfs_fs_devices,
+					list);
+		btrfs_close_devices(fs_devices);
+	}
+}
+
+int btrfs_open_devices(struct btrfs_fs_devices *fs_devices)
+{
+	struct btrfs_device *device;
+
+	list_for_each_entry(device, &fs_devices->devices, dev_list) {
+		if (!device->desc || !device->part) {
+			printf("no device found for devid %llu, skip it \n",
+				device->devid);
+			continue;
+		}
+	}
+	return 0;
+}
+
+int btrfs_scan_one_device(struct blk_desc *desc, struct disk_partition *part,
+			  struct btrfs_fs_devices **fs_devices_ret,
+			  u64 *total_devs)
+{
+	struct btrfs_super_block *disk_super;
+	char buf[BTRFS_SUPER_INFO_SIZE];
+	int ret;
+	u64 devid;
+
+	disk_super = (struct btrfs_super_block *)buf;
+	ret = btrfs_read_dev_super(desc, part, disk_super);
+	if (ret < 0)
+		return -EIO;
+	devid = btrfs_stack_device_id(&disk_super->dev_item);
+	if (btrfs_super_flags(disk_super) & BTRFS_SUPER_FLAG_METADUMP)
+		*total_devs = 1;
+	else
+		*total_devs = btrfs_super_num_devices(disk_super);
+
+	ret = device_list_add(disk_super, devid, desc, part, fs_devices_ret);
+
+	return ret;
+}
+
+struct btrfs_device *btrfs_find_device(struct btrfs_fs_info *fs_info, u64 devid,
+				       u8 *uuid, u8 *fsid)
+{
+	struct btrfs_device *device;
+	struct btrfs_fs_devices *cur_devices;
+
+	cur_devices = fs_info->fs_devices;
+	while (cur_devices) {
+		if (!fsid ||
+		   !memcmp(cur_devices->metadata_uuid, fsid, BTRFS_FSID_SIZE)) {
+			device = find_device(cur_devices, devid, uuid);
+			if (device)
+				return device;
+		}
+		cur_devices = cur_devices->seed;
+	}
+	return NULL;
+}
+
+static struct btrfs_device *fill_missing_device(u64 devid)
+{
+	struct btrfs_device *device;
+
+	device = kzalloc(sizeof(*device), GFP_NOFS);
+	return device;
+}
+
+/*
+ * slot == -1: SYSTEM chunk
+ * return -EIO on error, otherwise return 0
+ */
+int btrfs_check_chunk_valid(struct btrfs_fs_info *fs_info,
+			    struct extent_buffer *leaf,
+			    struct btrfs_chunk *chunk,
+			    int slot, u64 logical)
+{
+	u64 length;
+	u64 stripe_len;
+	u16 num_stripes;
+	u16 sub_stripes;
+	u64 type;
+	u32 chunk_ondisk_size;
+	u32 sectorsize = fs_info->sectorsize;
+
+	/*
+	 * Basic chunk item size check.  Note that btrfs_chunk already contains
+	 * one stripe, so no "==" check.
+	 */
+	if (slot >= 0 &&
+	    btrfs_item_size_nr(leaf, slot) < sizeof(struct btrfs_chunk)) {
+		error("invalid chunk item size, have %u expect [%zu, %zu)",
+			btrfs_item_size_nr(leaf, slot),
+			sizeof(struct btrfs_chunk),
+			BTRFS_LEAF_DATA_SIZE(fs_info));
+		return -EUCLEAN;
+	}
+	length = btrfs_chunk_length(leaf, chunk);
+	stripe_len = btrfs_chunk_stripe_len(leaf, chunk);
+	num_stripes = btrfs_chunk_num_stripes(leaf, chunk);
+	sub_stripes = btrfs_chunk_sub_stripes(leaf, chunk);
+	type = btrfs_chunk_type(leaf, chunk);
+
+	if (num_stripes == 0) {
+		error("invalid num_stripes, have %u expect non-zero",
+			num_stripes);
+		return -EUCLEAN;
+	}
+	if (slot >= 0 && btrfs_chunk_item_size(num_stripes) !=
+	    btrfs_item_size_nr(leaf, slot)) {
+		error("invalid chunk item size, have %u expect %lu",
+			btrfs_item_size_nr(leaf, slot),
+			btrfs_chunk_item_size(num_stripes));
+		return -EUCLEAN;
+	}
+
+	/*
+	 * These valid checks may be insufficient to cover every corner cases.
+	 */
+	if (!IS_ALIGNED(logical, sectorsize)) {
+		error("invalid chunk logical %llu",  logical);
+		return -EIO;
+	}
+	if (btrfs_chunk_sector_size(leaf, chunk) != sectorsize) {
+		error("invalid chunk sectorsize %llu",
+		      (unsigned long long)btrfs_chunk_sector_size(leaf, chunk));
+		return -EIO;
+	}
+	if (!length || !IS_ALIGNED(length, sectorsize)) {
+		error("invalid chunk length %llu",  length);
+		return -EIO;
+	}
+	if (stripe_len != BTRFS_STRIPE_LEN) {
+		error("invalid chunk stripe length: %llu", stripe_len);
+		return -EIO;
+	}
+	/* Check on chunk item type */
+	if (slot == -1 && (type & BTRFS_BLOCK_GROUP_SYSTEM) == 0) {
+		error("invalid chunk type %llu", type);
+		return -EIO;
+	}
+	if (type & ~(BTRFS_BLOCK_GROUP_TYPE_MASK |
+		     BTRFS_BLOCK_GROUP_PROFILE_MASK)) {
+		error("unrecognized chunk type: %llu",
+		      ~(BTRFS_BLOCK_GROUP_TYPE_MASK |
+			BTRFS_BLOCK_GROUP_PROFILE_MASK) & type);
+		return -EIO;
+	}
+	if (!(type & BTRFS_BLOCK_GROUP_TYPE_MASK)) {
+		error("missing chunk type flag: %llu", type);
+		return -EIO;
+	}
+	if (!(is_power_of_2(type & BTRFS_BLOCK_GROUP_PROFILE_MASK) ||
+	      (type & BTRFS_BLOCK_GROUP_PROFILE_MASK) == 0)) {
+		error("conflicting chunk type detected: %llu", type);
+		return -EIO;
+	}
+	if ((type & BTRFS_BLOCK_GROUP_PROFILE_MASK) &&
+	    !is_power_of_2(type & BTRFS_BLOCK_GROUP_PROFILE_MASK)) {
+		error("conflicting chunk profile detected: %llu", type);
+		return -EIO;
+	}
+
+	chunk_ondisk_size = btrfs_chunk_item_size(num_stripes);
+	/*
+	 * Btrfs_chunk contains at least one stripe, and for sys_chunk
+	 * it can't exceed the system chunk array size
+	 * For normal chunk, it should match its chunk item size.
+	 */
+	if (num_stripes < 1 ||
+	    (slot == -1 && chunk_ondisk_size > BTRFS_SYSTEM_CHUNK_ARRAY_SIZE) ||
+	    (slot >= 0 && chunk_ondisk_size > btrfs_item_size_nr(leaf, slot))) {
+		error("invalid num_stripes: %u", num_stripes);
+		return -EIO;
+	}
+	/*
+	 * Device number check against profile
+	 */
+	if ((type & BTRFS_BLOCK_GROUP_RAID10 && (sub_stripes != 2 ||
+		  !IS_ALIGNED(num_stripes, sub_stripes))) ||
+	    (type & BTRFS_BLOCK_GROUP_RAID1 && num_stripes < 1) ||
+	    (type & BTRFS_BLOCK_GROUP_RAID1C3 && num_stripes < 3) ||
+	    (type & BTRFS_BLOCK_GROUP_RAID1C4 && num_stripes < 4) ||
+	    (type & BTRFS_BLOCK_GROUP_RAID5 && num_stripes < 2) ||
+	    (type & BTRFS_BLOCK_GROUP_RAID6 && num_stripes < 3) ||
+	    (type & BTRFS_BLOCK_GROUP_DUP && num_stripes > 2) ||
+	    ((type & BTRFS_BLOCK_GROUP_PROFILE_MASK) == 0 &&
+	     num_stripes != 1)) {
+		error("Invalid num_stripes:sub_stripes %u:%u for profile %llu",
+		      num_stripes, sub_stripes,
+		      type & BTRFS_BLOCK_GROUP_PROFILE_MASK);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * Slot is used to verify the chunk item is valid
+ *
+ * For sys chunk in superblock, pass -1 to indicate sys chunk.
+ */
+static int read_one_chunk(struct btrfs_fs_info *fs_info, struct btrfs_key *key,
+			  struct extent_buffer *leaf,
+			  struct btrfs_chunk *chunk, int slot)
+{
+	struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
+	struct map_lookup *map;
+	struct cache_extent *ce;
+	u64 logical;
+	u64 length;
+	u64 devid;
+	u8 uuid[BTRFS_UUID_SIZE];
+	int num_stripes;
+	int ret;
+	int i;
+
+	logical = key->offset;
+	length = btrfs_chunk_length(leaf, chunk);
+	num_stripes = btrfs_chunk_num_stripes(leaf, chunk);
+	/* Validation check */
+	ret = btrfs_check_chunk_valid(fs_info, leaf, chunk, slot, logical);
+	if (ret) {
+		error("%s checksums match, but it has an invalid chunk, %s",
+		      (slot == -1) ? "Superblock" : "Metadata",
+		      (slot == -1) ? "try btrfsck --repair -s <superblock> ie, 0,1,2" : "");
+		return ret;
+	}
+
+	ce = search_cache_extent(&map_tree->cache_tree, logical);
+
+	/* already mapped? */
+	if (ce && ce->start <= logical && ce->start + ce->size > logical) {
+		return 0;
+	}
+
+	map = kmalloc(btrfs_map_lookup_size(num_stripes), GFP_NOFS);
+	if (!map)
+		return -ENOMEM;
+
+	map->ce.start = logical;
+	map->ce.size = length;
+	map->num_stripes = num_stripes;
+	map->io_width = btrfs_chunk_io_width(leaf, chunk);
+	map->io_align = btrfs_chunk_io_align(leaf, chunk);
+	map->sector_size = btrfs_chunk_sector_size(leaf, chunk);
+	map->stripe_len = btrfs_chunk_stripe_len(leaf, chunk);
+	map->type = btrfs_chunk_type(leaf, chunk);
+	map->sub_stripes = btrfs_chunk_sub_stripes(leaf, chunk);
+
+	for (i = 0; i < num_stripes; i++) {
+		map->stripes[i].physical =
+			btrfs_stripe_offset_nr(leaf, chunk, i);
+		devid = btrfs_stripe_devid_nr(leaf, chunk, i);
+		read_extent_buffer(leaf, uuid, (unsigned long)
+				   btrfs_stripe_dev_uuid_nr(chunk, i),
+				   BTRFS_UUID_SIZE);
+		map->stripes[i].dev = btrfs_find_device(fs_info, devid, uuid,
+							NULL);
+		if (!map->stripes[i].dev) {
+			map->stripes[i].dev = fill_missing_device(devid);
+			printf("warning, device %llu is missing\n",
+			       (unsigned long long)devid);
+			list_add(&map->stripes[i].dev->dev_list,
+				 &fs_info->fs_devices->devices);
+		}
+
+	}
+	ret = insert_cache_extent(&map_tree->cache_tree, &map->ce);
+	if (ret < 0) {
+		errno = -ret;
+		error("failed to add chunk map start=%llu len=%llu: %d (%m)",
+		      map->ce.start, map->ce.size, ret);
+	}
+
+	return ret;
+}
+
+static int fill_device_from_item(struct extent_buffer *leaf,
+				 struct btrfs_dev_item *dev_item,
+				 struct btrfs_device *device)
+{
+	unsigned long ptr;
+
+	device->devid = btrfs_device_id(leaf, dev_item);
+	device->total_bytes = btrfs_device_total_bytes(leaf, dev_item);
+	device->bytes_used = btrfs_device_bytes_used(leaf, dev_item);
+	device->type = btrfs_device_type(leaf, dev_item);
+	device->io_align = btrfs_device_io_align(leaf, dev_item);
+	device->io_width = btrfs_device_io_width(leaf, dev_item);
+	device->sector_size = btrfs_device_sector_size(leaf, dev_item);
+
+	ptr = (unsigned long)btrfs_device_uuid(dev_item);
+	read_extent_buffer(leaf, device->uuid, ptr, BTRFS_UUID_SIZE);
+
+	return 0;
+}
+
+static int read_one_dev(struct btrfs_fs_info *fs_info,
+			struct extent_buffer *leaf,
+			struct btrfs_dev_item *dev_item)
+{
+	struct btrfs_device *device;
+	u64 devid;
+	int ret = 0;
+	u8 fs_uuid[BTRFS_UUID_SIZE];
+	u8 dev_uuid[BTRFS_UUID_SIZE];
+
+	devid = btrfs_device_id(leaf, dev_item);
+	read_extent_buffer(leaf, dev_uuid,
+			   (unsigned long)btrfs_device_uuid(dev_item),
+			   BTRFS_UUID_SIZE);
+	read_extent_buffer(leaf, fs_uuid,
+			   (unsigned long)btrfs_device_fsid(dev_item),
+			   BTRFS_FSID_SIZE);
+
+	if (memcmp(fs_uuid, fs_info->fs_devices->fsid, BTRFS_UUID_SIZE)) {
+		error("Seed device is not yet supported\n");
+		return -ENOTSUPP;
+	}
+
+	device = btrfs_find_device(fs_info, devid, dev_uuid, fs_uuid);
+	if (!device) {
+		device = kzalloc(sizeof(*device), GFP_NOFS);
+		if (!device)
+			return -ENOMEM;
+		list_add(&device->dev_list,
+			 &fs_info->fs_devices->devices);
+	}
+
+	fill_device_from_item(leaf, dev_item, device);
+	fs_info->fs_devices->total_rw_bytes +=
+		btrfs_device_total_bytes(leaf, dev_item);
+	return ret;
+}
+
+int btrfs_read_sys_array(struct btrfs_fs_info *fs_info)
+{
+	struct btrfs_super_block *super_copy = fs_info->super_copy;
+	struct extent_buffer *sb;
+	struct btrfs_disk_key *disk_key;
+	struct btrfs_chunk *chunk;
+	u8 *array_ptr;
+	unsigned long sb_array_offset;
+	int ret = 0;
+	u32 num_stripes;
+	u32 array_size;
+	u32 len = 0;
+	u32 cur_offset;
+	struct btrfs_key key;
+
+	if (fs_info->nodesize < BTRFS_SUPER_INFO_SIZE) {
+		printf("ERROR: nodesize %u too small to read superblock\n",
+				fs_info->nodesize);
+		return -EINVAL;
+	}
+	sb = alloc_dummy_extent_buffer(fs_info, BTRFS_SUPER_INFO_OFFSET,
+				       BTRFS_SUPER_INFO_SIZE);
+	if (!sb)
+		return -ENOMEM;
+	btrfs_set_buffer_uptodate(sb);
+	write_extent_buffer(sb, super_copy, 0, sizeof(*super_copy));
+	array_size = btrfs_super_sys_array_size(super_copy);
+
+	array_ptr = super_copy->sys_chunk_array;
+	sb_array_offset = offsetof(struct btrfs_super_block, sys_chunk_array);
+	cur_offset = 0;
+
+	while (cur_offset < array_size) {
+		disk_key = (struct btrfs_disk_key *)array_ptr;
+		len = sizeof(*disk_key);
+		if (cur_offset + len > array_size)
+			goto out_short_read;
+
+		btrfs_disk_key_to_cpu(&key, disk_key);
+
+		array_ptr += len;
+		sb_array_offset += len;
+		cur_offset += len;
+
+		if (key.type == BTRFS_CHUNK_ITEM_KEY) {
+			chunk = (struct btrfs_chunk *)sb_array_offset;
+			/*
+			 * At least one btrfs_chunk with one stripe must be
+			 * present, exact stripe count check comes afterwards
+			 */
+			len = btrfs_chunk_item_size(1);
+			if (cur_offset + len > array_size)
+				goto out_short_read;
+
+			num_stripes = btrfs_chunk_num_stripes(sb, chunk);
+			if (!num_stripes) {
+				printk(
+	    "ERROR: invalid number of stripes %u in sys_array at offset %u\n",
+					num_stripes, cur_offset);
+				ret = -EIO;
+				break;
+			}
+
+			len = btrfs_chunk_item_size(num_stripes);
+			if (cur_offset + len > array_size)
+				goto out_short_read;
+
+			ret = read_one_chunk(fs_info, &key, sb, chunk, -1);
+			if (ret)
+				break;
+		} else {
+			printk(
+		"ERROR: unexpected item type %u in sys_array at offset %u\n",
+				(u32)key.type, cur_offset);
+			ret = -EIO;
+			break;
+		}
+		array_ptr += len;
+		sb_array_offset += len;
+		cur_offset += len;
+	}
+	free_extent_buffer(sb);
+	return ret;
+
+out_short_read:
+	printk("ERROR: sys_array too short to read %u bytes at offset %u\n",
+			len, cur_offset);
+	free_extent_buffer(sb);
+	return -EIO;
+}
+
+int btrfs_read_chunk_tree(struct btrfs_fs_info *fs_info)
+{
+	struct btrfs_path *path;
+	struct extent_buffer *leaf;
+	struct btrfs_key key;
+	struct btrfs_key found_key;
+	struct btrfs_root *root = fs_info->chunk_root;
+	int ret;
+	int slot;
+
+	path = btrfs_alloc_path();
+	if (!path)
+		return -ENOMEM;
+
+	/*
+	 * Read all device items, and then all the chunk items. All
+	 * device items are found before any chunk item (their object id
+	 * is smaller than the lowest possible object id for a chunk
+	 * item - BTRFS_FIRST_CHUNK_TREE_OBJECTID).
+	 */
+	key.objectid = BTRFS_DEV_ITEMS_OBJECTID;
+	key.offset = 0;
+	key.type = 0;
+	ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
+	if (ret < 0)
+		goto error;
+	while(1) {
+		leaf = path->nodes[0];
+		slot = path->slots[0];
+		if (slot >= btrfs_header_nritems(leaf)) {
+			ret = btrfs_next_leaf(root, path);
+			if (ret == 0)
+				continue;
+			if (ret < 0)
+				goto error;
+			break;
+		}
+		btrfs_item_key_to_cpu(leaf, &found_key, slot);
+		if (found_key.type == BTRFS_DEV_ITEM_KEY) {
+			struct btrfs_dev_item *dev_item;
+			dev_item = btrfs_item_ptr(leaf, slot,
+						  struct btrfs_dev_item);
+			ret = read_one_dev(fs_info, leaf, dev_item);
+			if (ret < 0)
+				goto error;
+		} else if (found_key.type == BTRFS_CHUNK_ITEM_KEY) {
+			struct btrfs_chunk *chunk;
+			chunk = btrfs_item_ptr(leaf, slot, struct btrfs_chunk);
+			ret = read_one_chunk(fs_info, &found_key, leaf, chunk,
+					     slot);
+			if (ret < 0)
+				goto error;
+		}
+		path->slots[0]++;
+	}
+
+	ret = 0;
+error:
+	btrfs_free_path(path);
+	return ret;
+}
+
+/*
+ * Get stripe length from chunk item and its stripe items
+ *
+ * Caller should only call this function after validating the chunk item
+ * by using btrfs_check_chunk_valid().
+ */
+u64 btrfs_stripe_length(struct btrfs_fs_info *fs_info,
+			struct extent_buffer *leaf,
+			struct btrfs_chunk *chunk)
+{
+	u64 stripe_len;
+	u64 chunk_len;
+	u32 num_stripes = btrfs_chunk_num_stripes(leaf, chunk);
+	u64 profile = btrfs_chunk_type(leaf, chunk) &
+		      BTRFS_BLOCK_GROUP_PROFILE_MASK;
+
+	chunk_len = btrfs_chunk_length(leaf, chunk);
+
+	switch (profile) {
+	case 0: /* Single profile */
+	case BTRFS_BLOCK_GROUP_RAID1:
+	case BTRFS_BLOCK_GROUP_RAID1C3:
+	case BTRFS_BLOCK_GROUP_RAID1C4:
+	case BTRFS_BLOCK_GROUP_DUP:
+		stripe_len = chunk_len;
+		break;
+	case BTRFS_BLOCK_GROUP_RAID0:
+		stripe_len = chunk_len / num_stripes;
+		break;
+	case BTRFS_BLOCK_GROUP_RAID5:
+		stripe_len = chunk_len / (num_stripes - 1);
+		break;
+	case BTRFS_BLOCK_GROUP_RAID6:
+		stripe_len = chunk_len / (num_stripes - 2);
+		break;
+	case BTRFS_BLOCK_GROUP_RAID10:
+		stripe_len = chunk_len / (num_stripes /
+				btrfs_chunk_sub_stripes(leaf, chunk));
+		break;
+	default:
+		/* Invalid chunk profile found */
+		BUG_ON(1);
+	}
+	return stripe_len;
+}
+
+int btrfs_num_copies(struct btrfs_fs_info *fs_info, u64 logical, u64 len)
+{
+	struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
+	struct cache_extent *ce;
+	struct map_lookup *map;
+	int ret;
+
+	ce = search_cache_extent(&map_tree->cache_tree, logical);
+	if (!ce) {
+		fprintf(stderr, "No mapping for %llu-%llu\n",
+			(unsigned long long)logical,
+			(unsigned long long)logical+len);
+		return 1;
+	}
+	if (ce->start > logical || ce->start + ce->size < logical) {
+		fprintf(stderr, "Invalid mapping for %llu-%llu, got "
+			"%llu-%llu\n", (unsigned long long)logical,
+			(unsigned long long)logical+len,
+			(unsigned long long)ce->start,
+			(unsigned long long)ce->start + ce->size);
+		return 1;
+	}
+	map = container_of(ce, struct map_lookup, ce);
+
+	if (map->type & (BTRFS_BLOCK_GROUP_DUP | BTRFS_BLOCK_GROUP_RAID1 |
+			 BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4))
+		ret = map->num_stripes;
+	else if (map->type & BTRFS_BLOCK_GROUP_RAID10)
+		ret = map->sub_stripes;
+	else if (map->type & BTRFS_BLOCK_GROUP_RAID5)
+		ret = 2;
+	else if (map->type & BTRFS_BLOCK_GROUP_RAID6)
+		ret = 3;
+	else
+		ret = 1;
+	return ret;
+}
+
+int btrfs_next_bg(struct btrfs_fs_info *fs_info, u64 *logical,
+		  u64 *size, u64 type)
+{
+	struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
+	struct cache_extent *ce;
+	struct map_lookup *map;
+	u64 cur = *logical;
+
+	ce = search_cache_extent(&map_tree->cache_tree, cur);
+
+	while (ce) {
+		/*
+		 * only jump to next bg if our cur is not 0
+		 * As the initial logical for btrfs_next_bg() is 0, and
+		 * if we jump to next bg, we skipped a valid bg.
+		 */
+		if (cur) {
+			ce = next_cache_extent(ce);
+			if (!ce)
+				return -ENOENT;
+		}
+
+		cur = ce->start;
+		map = container_of(ce, struct map_lookup, ce);
+		if (map->type & type) {
+			*logical = ce->start;
+			*size = ce->size;
+			return 0;
+		}
+		if (!cur)
+			ce = next_cache_extent(ce);
+	}
+
+	return -ENOENT;
+}
+
+static inline int parity_smaller(u64 a, u64 b)
+{
+	return a > b;
+}
+
+/* Bubble-sort the stripe set to put the parity/syndrome stripes last */
+static void sort_parity_stripes(struct btrfs_multi_bio *bbio, u64 *raid_map)
+{
+	struct btrfs_bio_stripe s;
+	int i;
+	u64 l;
+	int again = 1;
+
+	while (again) {
+		again = 0;
+		for (i = 0; i < bbio->num_stripes - 1; i++) {
+			if (parity_smaller(raid_map[i], raid_map[i+1])) {
+				s = bbio->stripes[i];
+				l = raid_map[i];
+				bbio->stripes[i] = bbio->stripes[i+1];
+				raid_map[i] = raid_map[i+1];
+				bbio->stripes[i+1] = s;
+				raid_map[i+1] = l;
+				again = 1;
+			}
+		}
+	}
+}
+
+int __btrfs_map_block(struct btrfs_fs_info *fs_info, int rw,
+		      u64 logical, u64 *length, u64 *type,
+		      struct btrfs_multi_bio **multi_ret, int mirror_num,
+		      u64 **raid_map_ret)
+{
+	struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
+	struct cache_extent *ce;
+	struct map_lookup *map;
+	u64 offset;
+	u64 stripe_offset;
+	u64 *raid_map = NULL;
+	int stripe_nr;
+	int stripes_allocated = 8;
+	int stripes_required = 1;
+	int stripe_index;
+	int i;
+	struct btrfs_multi_bio *multi = NULL;
+
+	if (multi_ret && rw == READ) {
+		stripes_allocated = 1;
+	}
+again:
+	ce = search_cache_extent(&map_tree->cache_tree, logical);
+	if (!ce) {
+		kfree(multi);
+		*length = (u64)-1;
+		return -ENOENT;
+	}
+	if (ce->start > logical) {
+		kfree(multi);
+		*length = ce->start - logical;
+		return -ENOENT;
+	}
+
+	if (multi_ret) {
+		multi = kzalloc(btrfs_multi_bio_size(stripes_allocated),
+				GFP_NOFS);
+		if (!multi)
+			return -ENOMEM;
+	}
+	map = container_of(ce, struct map_lookup, ce);
+	offset = logical - ce->start;
+
+	if (rw == WRITE) {
+		if (map->type & (BTRFS_BLOCK_GROUP_RAID1 |
+				 BTRFS_BLOCK_GROUP_RAID1C3 |
+				 BTRFS_BLOCK_GROUP_RAID1C4 |
+				 BTRFS_BLOCK_GROUP_DUP)) {
+			stripes_required = map->num_stripes;
+		} else if (map->type & BTRFS_BLOCK_GROUP_RAID10) {
+			stripes_required = map->sub_stripes;
+		}
+	}
+	if (map->type & (BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6)
+	    && multi_ret && ((rw & WRITE) || mirror_num > 1) && raid_map_ret) {
+		    /* RAID[56] write or recovery. Return all stripes */
+		    stripes_required = map->num_stripes;
+
+		    /* Only allocate the map if we've already got a large enough multi_ret */
+		    if (stripes_allocated >= stripes_required) {
+			    raid_map = kmalloc(sizeof(u64) * map->num_stripes, GFP_NOFS);
+			    if (!raid_map) {
+				    kfree(multi);
+				    return -ENOMEM;
+			    }
+		    }
+	}
+
+	/* if our multi bio struct is too small, back off and try again */
+	if (multi_ret && stripes_allocated < stripes_required) {
+		stripes_allocated = stripes_required;
+		kfree(multi);
+		multi = NULL;
+		goto again;
+	}
+	stripe_nr = offset;
+	/*
+	 * stripe_nr counts the total number of stripes we have to stride
+	 * to get to this block
+	 */
+	stripe_nr = stripe_nr / map->stripe_len;
+
+	stripe_offset = stripe_nr * map->stripe_len;
+	BUG_ON(offset < stripe_offset);
+
+	/* stripe_offset is the offset of this block in its stripe*/
+	stripe_offset = offset - stripe_offset;
+
+	if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 |
+			 BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 |
+			 BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 |
+			 BTRFS_BLOCK_GROUP_RAID10 |
+			 BTRFS_BLOCK_GROUP_DUP)) {
+		/* we limit the length of each bio to what fits in a stripe */
+		*length = min_t(u64, ce->size - offset,
+			      map->stripe_len - stripe_offset);
+	} else {
+		*length = ce->size - offset;
+	}
+
+	if (!multi_ret)
+		goto out;
+
+	multi->num_stripes = 1;
+	stripe_index = 0;
+	if (map->type & (BTRFS_BLOCK_GROUP_RAID1 |
+			 BTRFS_BLOCK_GROUP_RAID1C3 |
+			 BTRFS_BLOCK_GROUP_RAID1C4)) {
+		if (rw == WRITE)
+			multi->num_stripes = map->num_stripes;
+		else if (mirror_num)
+			stripe_index = mirror_num - 1;
+		else
+			stripe_index = stripe_nr % map->num_stripes;
+	} else if (map->type & BTRFS_BLOCK_GROUP_RAID10) {
+		int factor = map->num_stripes / map->sub_stripes;
+
+		stripe_index = stripe_nr % factor;
+		stripe_index *= map->sub_stripes;
+
+		if (rw == WRITE)
+			multi->num_stripes = map->sub_stripes;
+		else if (mirror_num)
+			stripe_index += mirror_num - 1;
+
+		stripe_nr = stripe_nr / factor;
+	} else if (map->type & BTRFS_BLOCK_GROUP_DUP) {
+		if (rw == WRITE)
+			multi->num_stripes = map->num_stripes;
+		else if (mirror_num)
+			stripe_index = mirror_num - 1;
+	} else if (map->type & (BTRFS_BLOCK_GROUP_RAID5 |
+				BTRFS_BLOCK_GROUP_RAID6)) {
+
+		if (raid_map) {
+			int rot;
+			u64 tmp;
+			u64 raid56_full_stripe_start;
+			u64 full_stripe_len = nr_data_stripes(map) * map->stripe_len;
+
+			/*
+			 * align the start of our data stripe in the logical
+			 * address space
+			 */
+			raid56_full_stripe_start = offset / full_stripe_len;
+			raid56_full_stripe_start *= full_stripe_len;
+
+			/* get the data stripe number */
+			stripe_nr = raid56_full_stripe_start / map->stripe_len;
+			stripe_nr = stripe_nr / nr_data_stripes(map);
+
+			/* Work out the disk rotation on this stripe-set */
+			rot = stripe_nr % map->num_stripes;
+
+			/* Fill in the logical address of each stripe */
+			tmp = stripe_nr * nr_data_stripes(map);
+
+			for (i = 0; i < nr_data_stripes(map); i++)
+				raid_map[(i+rot) % map->num_stripes] =
+					ce->start + (tmp + i) * map->stripe_len;
+
+			raid_map[(i+rot) % map->num_stripes] = BTRFS_RAID5_P_STRIPE;
+			if (map->type & BTRFS_BLOCK_GROUP_RAID6)
+				raid_map[(i+rot+1) % map->num_stripes] = BTRFS_RAID6_Q_STRIPE;
+
+			*length = map->stripe_len;
+			stripe_index = 0;
+			stripe_offset = 0;
+			multi->num_stripes = map->num_stripes;
+		} else {
+			stripe_index = stripe_nr % nr_data_stripes(map);
+			stripe_nr = stripe_nr / nr_data_stripes(map);
+
+			/*
+			 * Mirror #0 or #1 means the original data block.
+			 * Mirror #2 is RAID5 parity block.
+			 * Mirror #3 is RAID6 Q block.
+			 */
+			if (mirror_num > 1)
+				stripe_index = nr_data_stripes(map) + mirror_num - 2;
+
+			/* We distribute the parity blocks across stripes */
+			stripe_index = (stripe_nr + stripe_index) % map->num_stripes;
+		}
+	} else {
+		/*
+		 * after this do_div call, stripe_nr is the number of stripes
+		 * on this device we have to walk to find the data, and
+		 * stripe_index is the number of our device in the stripe array
+		 */
+		stripe_index = stripe_nr % map->num_stripes;
+		stripe_nr = stripe_nr / map->num_stripes;
+	}
+	BUG_ON(stripe_index >= map->num_stripes);
+
+	for (i = 0; i < multi->num_stripes; i++) {
+		multi->stripes[i].physical =
+			map->stripes[stripe_index].physical + stripe_offset +
+			stripe_nr * map->stripe_len;
+		multi->stripes[i].dev = map->stripes[stripe_index].dev;
+		stripe_index++;
+	}
+	*multi_ret = multi;
+
+	if (type)
+		*type = map->type;
+
+	if (raid_map) {
+		sort_parity_stripes(multi, raid_map);
+		*raid_map_ret = raid_map;
+	}
+out:
+	return 0;
+}
+
+int btrfs_map_block(struct btrfs_fs_info *fs_info, int rw,
+		    u64 logical, u64 *length,
+		    struct btrfs_multi_bio **multi_ret, int mirror_num,
+		    u64 **raid_map_ret)
+{
+	return __btrfs_map_block(fs_info, rw, logical, length, NULL,
+				 multi_ret, mirror_num, raid_map_ret);
+}

diff --git a/fs/btrfs/volumes.h b/fs/btrfs/volumes.h
new file mode 100644
index 0000000..9d1a07a
--- /dev/null
+++ b/fs/btrfs/volumes.h

@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#ifndef __BTRFS_VOLUMES_H__
+#define __BTRFS_VOLUMES_H__
+
+#include <fs_internal.h>
+#include "ctree.h"
+
+#define BTRFS_STRIPE_LEN	SZ_64K
+
+struct btrfs_device {
+	struct list_head dev_list;
+	struct btrfs_root *dev_root;
+	struct btrfs_fs_devices *fs_devices;
+
+	struct blk_desc *desc;
+	struct disk_partition *part;
+
+	u64 total_devs;
+	u64 super_bytes_used;
+
+	u64 generation;
+
+	/* the internal btrfs device id */
+	u64 devid;
+
+	/* size of the device */
+	u64 total_bytes;
+
+	/* bytes used */
+	u64 bytes_used;
+
+	/* optimal io alignment for this device */
+	u32 io_align;
+
+	/* optimal io width for this device */
+	u32 io_width;
+
+	/* minimal io size for this device */
+	u32 sector_size;
+
+	/* type and info about this device */
+	u64 type;
+
+	/* physical drive uuid (or lvm uuid) */
+	u8 uuid[BTRFS_UUID_SIZE];
+};
+
+struct btrfs_fs_devices {
+	u8 fsid[BTRFS_FSID_SIZE]; /* FS specific uuid */
+	u8 metadata_uuid[BTRFS_FSID_SIZE]; /* FS specific uuid */
+
+	u64 latest_devid;
+	u64 lowest_devid;
+	u64 latest_trans;
+
+	u64 total_rw_bytes;
+
+	struct list_head devices;
+	struct list_head list;
+
+	int seeding;
+	struct btrfs_fs_devices *seed;
+};
+
+struct btrfs_bio_stripe {
+	struct btrfs_device *dev;
+	u64 physical;
+};
+
+struct btrfs_multi_bio {
+	int error;
+	int num_stripes;
+	struct btrfs_bio_stripe stripes[];
+};
+
+struct map_lookup {
+	struct cache_extent ce;
+	u64 type;
+	int io_align;
+	int io_width;
+	int stripe_len;
+	int sector_size;
+	int num_stripes;
+	int sub_stripes;
+	struct btrfs_bio_stripe stripes[];
+};
+
+struct btrfs_raid_attr {
+	int sub_stripes;	/* sub_stripes info for map */
+	int dev_stripes;	/* stripes per dev */
+	int devs_max;		/* max devs to use */
+	int devs_min;		/* min devs needed */
+	int tolerated_failures; /* max tolerated fail devs */
+	int devs_increment;	/* ndevs has to be a multiple of this */
+	int ncopies;		/* how many copies to data has */
+	int nparity;		/* number of stripes worth of bytes to store
+				 * parity information */
+	const char raid_name[8]; /* name of the raid */
+	u64 bg_flag;		/* block group flag of the raid */
+};
+
+extern const struct btrfs_raid_attr btrfs_raid_array[BTRFS_NR_RAID_TYPES];
+
+static inline enum btrfs_raid_types btrfs_bg_flags_to_raid_index(u64 flags)
+{
+	if (flags & BTRFS_BLOCK_GROUP_RAID10)
+		return BTRFS_RAID_RAID10;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID1)
+		return BTRFS_RAID_RAID1;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID1C3)
+		return BTRFS_RAID_RAID1C3;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID1C4)
+		return BTRFS_RAID_RAID1C4;
+	else if (flags & BTRFS_BLOCK_GROUP_DUP)
+		return BTRFS_RAID_DUP;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID0)
+		return BTRFS_RAID_RAID0;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID5)
+		return BTRFS_RAID_RAID5;
+	else if (flags & BTRFS_BLOCK_GROUP_RAID6)
+		return BTRFS_RAID_RAID6;
+
+	return BTRFS_RAID_SINGLE; /* BTRFS_BLOCK_GROUP_SINGLE */
+}
+
+#define btrfs_multi_bio_size(n) (sizeof(struct btrfs_multi_bio) + \
+			    (sizeof(struct btrfs_bio_stripe) * (n)))
+#define btrfs_map_lookup_size(n) (sizeof(struct map_lookup) + \
+				 (sizeof(struct btrfs_bio_stripe) * (n)))
+
+#define BTRFS_RAID5_P_STRIPE ((u64)-2)
+#define BTRFS_RAID6_Q_STRIPE ((u64)-1)
+
+static inline u64 calc_stripe_length(u64 type, u64 length, int num_stripes)
+{
+	u64 stripe_size;
+
+	if (type & BTRFS_BLOCK_GROUP_RAID0) {
+		stripe_size = length;
+		stripe_size /= num_stripes;
+	} else if (type & BTRFS_BLOCK_GROUP_RAID10) {
+		stripe_size = length * 2;
+		stripe_size /= num_stripes;
+	} else if (type & BTRFS_BLOCK_GROUP_RAID5) {
+		stripe_size = length;
+		stripe_size /= (num_stripes - 1);
+	} else if (type & BTRFS_BLOCK_GROUP_RAID6) {
+		stripe_size = length;
+		stripe_size /= (num_stripes - 2);
+	} else {
+		stripe_size = length;
+	}
+	return stripe_size;
+}
+
+#ifndef READ
+#define READ 0
+#define WRITE 1
+#define READA 2
+#endif
+
+int __btrfs_map_block(struct btrfs_fs_info *fs_info, int rw,
+		      u64 logical, u64 *length, u64 *type,
+		      struct btrfs_multi_bio **multi_ret, int mirror_num,
+		      u64 **raid_map);
+int btrfs_map_block(struct btrfs_fs_info *fs_info, int rw,
+		    u64 logical, u64 *length,
+		    struct btrfs_multi_bio **multi_ret, int mirror_num,
+		    u64 **raid_map_ret);
+int btrfs_next_bg(struct btrfs_fs_info *map_tree, u64 *logical,
+		     u64 *size, u64 type);
+static inline int btrfs_next_bg_metadata(struct btrfs_fs_info *fs_info,
+					 u64 *logical, u64 *size)
+{
+	return btrfs_next_bg(fs_info, logical, size,
+			BTRFS_BLOCK_GROUP_METADATA);
+}
+static inline int btrfs_next_bg_system(struct btrfs_fs_info *fs_info,
+				       u64 *logical, u64 *size)
+{
+	return btrfs_next_bg(fs_info, logical, size,
+			BTRFS_BLOCK_GROUP_SYSTEM);
+}
+int btrfs_read_sys_array(struct btrfs_fs_info *fs_info);
+int btrfs_read_chunk_tree(struct btrfs_fs_info *fs_info);
+int btrfs_open_devices(struct btrfs_fs_devices *fs_devices);
+int btrfs_close_devices(struct btrfs_fs_devices *fs_devices);
+void btrfs_close_all_devices(void);
+int btrfs_num_copies(struct btrfs_fs_info *fs_info, u64 logical, u64 len);
+int btrfs_scan_one_device(struct blk_desc *desc, struct disk_partition *part,
+			  struct btrfs_fs_devices **fs_devices_ret,
+			  u64 *total_devs);
+struct list_head *btrfs_scanned_uuids(void);
+struct btrfs_device *btrfs_find_device(struct btrfs_fs_info *fs_info, u64 devid,
+				       u8 *uuid, u8 *fsid);
+int btrfs_check_chunk_valid(struct btrfs_fs_info *fs_info,
+			    struct extent_buffer *leaf,
+			    struct btrfs_chunk *chunk,
+			    int slot, u64 logical);
+u64 btrfs_stripe_length(struct btrfs_fs_info *fs_info,
+			struct extent_buffer *leaf,
+			struct btrfs_chunk *chunk);
+#endif

diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 11461e1..ed4acd9 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h

@@ -10,7 +10,9 @@
 #define __ACPI_DEVICE_H
 
 #include <i2c.h>
+#include <irq.h>
 #include <spi.h>
+#include <asm-generic/gpio.h>
 #include <linux/bitops.h>
 
 struct acpi_ctx;
@@ -28,6 +30,9 @@
 /* Length of a full path to an ACPI device */
 #define ACPI_PATH_MAX		30
 
+/* UUID for an I2C _DSM method */
+#define ACPI_DSM_I2C_HID_UUID	"3cdff6f7-4267-4555-ad05-b30a3d8938de"
+
 /* Values that can be returned for ACPI device _STA method */
 enum acpi_dev_status {
 	ACPI_DSTATUS_PRESENT		= BIT(0),
@@ -165,6 +170,28 @@
  * @io_shared; true if GPIO is shared
  * @io_restrict: I/O restriction setting
  * @polarity: GPIO polarity
+ *
+ * Note that GpioIo doesn't have any means of Active Low / High setting, so a
+ * _DSD must be provided to mitigate this.
+ *
+ * GpioIo doesn't properly communicate the initial state of the output pin,
+ * thus Linux assumes the simple rule:
+ *
+ * Pull Bias       Polarity      Requested...
+ *
+ * Implicit        x             AS IS (assumed firmware configured for us)
+ * Explicit        x (no _DSD)   as Pull Bias (Up == High, Down == Low),
+ *                               assuming non-active (Polarity = !Pull Bias)
+ *
+ * Down            Low           as low, assuming active
+ * Down            High          as high, assuming non-active
+ * Up              Low           as high, assuming non-active
+ * Up              High          as high, assuming active
+ *
+ * GpioIo() can be used as interrupt and in this case the IoRestriction mustn't
+ * be OutputOnly. It also requires active_low flag from _DSD in cases where it's
+ * needed (better to always provide than rely on above assumption made on OS
+ * level).
  */
 struct acpi_gpio {
 	int pin_count;
@@ -233,6 +260,59 @@
 };
 
 /**
+ * struct acpi_i2c_priv - Information read from device tree
+ *
+ * This is used by devices which want to specify various pieces of ACPI
+ * information, including power control. It allows a generic function to
+ * generate the information for ACPI, based on device-tree properties.
+ *
+ * @disable_gpio_export_in_crs: Don't export GPIOs in the CRS
+ * @reset_gpio: GPIO used to assert reset to the device
+ * @enable_gpio: GPIO used to enable the device
+ * @stop_gpio: GPIO used to stop the device
+ * @irq_gpio: GPIO used for interrupt (if @irq is not used)
+ * @irq: IRQ used for interrupt (if @irq_gpio is not used)
+ * @hid: _HID value for device (required)
+ * @uid: _UID value for device
+ * @desc: _DDN value for device
+ * @wake: Wake event, e.g. GPE0_DW1_15; 0 if none
+ * @property_count: Number of other DSD properties (currently always 0)
+ * @probed: true set set 'linux,probed' property
+ * @compat_string: Device tree compatible string to report through ACPI
+ * @has_power_resource: true if this device has a power resource
+ * @reset_delay_ms: Delay after de-asserting reset, in ms
+ * @reset_off_delay_ms: Delay after asserting reset (during power off)
+ * @enable_delay_ms: Delay after asserting enable
+ * @enable_off_delay_ms: Delay after de-asserting enable (during power off)
+ * @stop_delay_ms: Delay after de-aserting stop
+ * @stop_off_delay_ms: Delay after asserting stop (during power off)
+ * @hid_desc_reg_offset: HID register offset (for Human Interface Devices)
+ */
+struct acpi_i2c_priv {
+	bool disable_gpio_export_in_crs;
+	struct gpio_desc reset_gpio;
+	struct gpio_desc enable_gpio;
+	struct gpio_desc irq_gpio;
+	struct gpio_desc stop_gpio;
+	struct irq irq;
+	const char *hid;
+	u32 uid;
+	const char *desc;
+	u32 wake;
+	u32 property_count;
+	bool probed;
+	const char *compat_string;
+	bool has_power_resource;
+	u32 reset_delay_ms;
+	u32 reset_off_delay_ms;
+	u32 enable_delay_ms;
+	u32 enable_off_delay_ms;
+	u32 stop_delay_ms;
+	u32 stop_off_delay_ms;
+	u32 hid_desc_reg_offset;
+};
+
+/**
  * acpi_device_path() - Get the full path to an ACPI device
  *
  * This gets the full path in the form XXXX.YYYY.ZZZZ where XXXX is the root
@@ -320,9 +400,20 @@
 					struct udevice *dev, const char *prop);
 
 /**
+ * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID
+ *
+ * This writes a DSM for an I2C Human-Interface Device based on the config
+ * provided
+ *
+ * @hid_desc_reg_offset: HID register offset
+ */
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+				  int hid_desc_reg_offset);
+
+/**
  * acpi_device_write_i2c_dev() - Write an I2C device to ACPI
  *
- * This creates a I2cSerialBus descriptor for an I2C device, including
+ * This creates a I2cSerialBusV2 descriptor for an I2C device, including
  * information ACPI needs to use it.
  *
  * @ctx: ACPI context pointer

diff --git a/include/acpi/acpi_dp.h b/include/acpi/acpi_dp.h
index 0b514bc..5e539b1 100644
--- a/include/acpi/acpi_dp.h
+++ b/include/acpi/acpi_dp.h

@@ -221,7 +221,7 @@
  */
 struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
 				 const char *ref, int index, int pin,
-				 enum acpi_irq_polarity polarity);
+				 enum acpi_gpio_polarity polarity);
 
 /**
  * acpi_dp_write() - Write Device Property hierarchy and clean up resources

diff --git a/include/acpi/acpi_s3.h b/include/acpi/acpi_s3.h
index baa848d..847139b 100644
--- a/include/acpi/acpi_s3.h
+++ b/include/acpi/acpi_s3.h

@@ -28,6 +28,10 @@
 #define SLP_TYP_S4	6
 #define SLP_TYP_S5	7
 
+/* PM1_STS register */
+#define RTC_EN		BIT(10)
+#define PWRBTN_EN	BIT(8)
+
 /* Memory size reserved for S3 resume */
 #define S3_RESERVE_SIZE	0x1000
 

diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index fe9b29f..abbca65 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h

@@ -13,18 +13,23 @@
 #ifndef __ACPI_TABLE_H__
 #define __ACPI_TABLE_H__
 
-#include <linux/bitops.h>
+#include <dm/acpi.h>
 
 #define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
 #define OEM_ID			"U-BOOT"	/* U-Boot */
 #define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
 #define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
+/* TODO(sjg@chromium.org): Figure out how to get compiler revision */
+#define ASL_REVISION	0
+
 #define ACPI_RSDP_REV_ACPI_1_0	0
 #define ACPI_RSDP_REV_ACPI_2_0	2
 
 #if !defined(__ACPI__)
 
+#include <linux/bitops.h>
+
 struct acpi_ctx;
 
 /*
@@ -45,7 +50,7 @@
 
 /* Generic ACPI header, provided by (almost) all tables */
 struct __packed acpi_table_header {
-	char signature[4];	/* ACPI signature (4 ASCII characters) */
+	char signature[ACPI_NAME_LEN];	/* ACPI signature (4 ASCII chars) */
 	u32 length;		/* Table length in bytes (incl. header) */
 	u8 revision;		/* Table version (not ACPI version!) */
 	volatile u8 checksum;	/* To make sum of entire table == 0 */
@@ -56,6 +61,15 @@
 	u32 aslc_revision;	/* ASL compiler revision number */
 };
 
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
+};
+
 /* A maximum number of 32 ACPI tables ought to be enough for now */
 #define MAX_ACPI_TABLES		32
 
@@ -71,6 +85,34 @@
 	u64 entry[MAX_ACPI_TABLES];
 };
 
+/* HPET timers */
+struct __packed acpi_hpet {
+	struct acpi_table_header header;
+	u32 id;
+	struct acpi_gen_regaddr addr;
+	u8 number;
+	u16 min_tick;
+	u8 attributes;
+};
+
+struct __packed acpi_tpm2 {
+	struct acpi_table_header header;
+	u16 platform_class;
+	u8  reserved[2];
+	u64 control_area;
+	u32 start_method;
+	u8  msp[12];
+	u32 laml;
+	u64 lasa;
+};
+
+struct __packed acpi_tcpa {
+	struct acpi_table_header header;
+	u16 platform_class;
+	u32 laml;
+	u64 lasa;
+};
+
 /* FADT Preferred Power Management Profile */
 enum acpi_pm_profile {
 	ACPI_PM_UNSPECIFIED = 0,
@@ -138,15 +180,6 @@
 	ACPI_ACCESS_SIZE_QWORD_ACCESS
 };
 
-struct acpi_gen_regaddr {
-	u8 space_id;	/* Address space ID */
-	u8 bit_width;	/* Register size in bits */
-	u8 bit_offset;	/* Register bit offset */
-	u8 access_size;	/* Access size */
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-};
-
 /* FADT (Fixed ACPI Description Table) */
 struct __packed acpi_fadt {
 	struct acpi_table_header header;
@@ -232,7 +265,7 @@
 
 /* FACS (Firmware ACPI Control Structure) */
 struct acpi_facs {
-	char signature[4];		/* "FACS" */
+	char signature[ACPI_NAME_LEN];	/* "FACS" */
 	u32 length;			/* Length in bytes (>= 64) */
 	u32 hardware_signature;		/* Hardware signature */
 	u32 firmware_waking_vector;	/* Firmware waking vector */
@@ -364,6 +397,49 @@
 	u32 max_block_size;
 };
 
+/* Port types for ACPI _UPC object */
+enum acpi_upc_type {
+	UPC_TYPE_A,
+	UPC_TYPE_MINI_AB,
+	UPC_TYPE_EXPRESSCARD,
+	UPC_TYPE_USB3_A,
+	UPC_TYPE_USB3_B,
+	UPC_TYPE_USB3_MICRO_B,
+	UPC_TYPE_USB3_MICRO_AB,
+	UPC_TYPE_USB3_POWER_B,
+	UPC_TYPE_C_USB2_ONLY,
+	UPC_TYPE_C_USB2_SS_SWITCH,
+	UPC_TYPE_C_USB2_SS,
+	UPC_TYPE_PROPRIETARY = 0xff,
+	/*
+	 * The following types are not directly defined in the ACPI
+	 * spec but are used by coreboot to identify a USB device type.
+	 */
+	UPC_TYPE_INTERNAL = 0xff,
+	UPC_TYPE_UNUSED,
+	UPC_TYPE_HUB
+};
+
+enum dev_scope_type {
+	SCOPE_PCI_ENDPOINT = 1,
+	SCOPE_PCI_SUB = 2,
+	SCOPE_IOAPIC = 3,
+	SCOPE_MSI_HPET = 4,
+	SCOPE_ACPI_NAMESPACE_DEVICE = 5
+};
+
+struct __packed dev_scope {
+	u8 type;
+	u8 length;
+	u8 reserved[2];
+	u8 enumeration;
+	u8 start_bus;
+	struct {
+		u8 dev;
+		u8 fn;
+	} __packed path[0];
+};
+
 enum dmar_type {
 	DMAR_DRHD = 0,
 	DMAR_RMRR = 1,
@@ -435,6 +511,29 @@
 
 #define ACPI_DBG2_UNKNOWN		0x00FF
 
+/* DBG2: Microsoft Debug Port Table 2 header */
+struct __packed acpi_dbg2_header {
+	struct acpi_table_header header;
+	u32 devices_offset;
+	u32 devices_count;
+};
+
+/* DBG2: Microsoft Debug Port Table 2 device entry */
+struct __packed acpi_dbg2_device {
+	u8  revision;
+	u16 length;
+	u8 address_count;
+	u16 namespace_string_length;
+	u16 namespace_string_offset;
+	u16 oem_data_length;
+	u16 oem_data_offset;
+	u16 port_type;
+	u16 port_subtype;
+	u8  reserved[2];
+	u16 base_address_offset;
+	u16 address_size_offset;
+};
+
 /* SPCR (Serial Port Console Redirection table) */
 struct __packed acpi_spcr {
 	struct acpi_table_header header;
@@ -510,6 +609,23 @@
 int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
 
 /**
+ * acpi_create_dbg2() - Create a DBG2 table
+ *
+ * This table describes how to access the debug UART
+ *
+ * @dbg2: Place to put information
+ * @port_type: Serial port type (see ACPI_DBG2_...)
+ * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)
+ * @address: ACPI address of port
+ * @address_size: Size of address space
+ * @device_path: Path of device (created using acpi_device_path())
+ */
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+		      int port_type, int port_subtype,
+		      struct acpi_gen_regaddr *address, uint32_t address_size,
+		      const char *device_path);
+
+/**
  * acpi_fill_header() - Set up a new table header
  *
  * This sets all fields except length, revision, checksum and aslc_revision

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 228ac9c..976f4db 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h

@@ -10,8 +10,10 @@
 #ifndef __ACPI_ACPIGEN_H
 #define __ACPI_ACPIGEN_H
 
+#include <acpi/acpi_table.h>
 #include <linux/types.h>
 
+struct acpi_cstate;
 struct acpi_ctx;
 struct acpi_gen_regaddr;
 struct acpi_gpio;
@@ -52,16 +54,89 @@
 	LOCAL5_OP		= 0x65,
 	LOCAL6_OP		= 0x66,
 	LOCAL7_OP		= 0x67,
+	ARG0_OP			= 0x68,
+	ARG1_OP			= 0x69,
+	ARG2_OP			= 0x6a,
+	ARG3_OP			= 0x6b,
+	ARG4_OP			= 0x6c,
+	ARG5_OP			= 0x6d,
+	ARG6_OP			= 0x6e,
 	STORE_OP		= 0x70,
 	AND_OP			= 0x7b,
 	OR_OP			= 0x7d,
 	NOT_OP			= 0x80,
 	DEVICE_OP		= 0x82,
+	PROCESSOR_OP		= 0x83,
 	POWER_RES_OP		= 0x84,
+	NOTIFY_OP		= 0x86,
+	LEQUAL_OP		= 0x93,
+	TO_BUFFER_OP		= 0x96,
+	TO_INTEGER_OP		= 0x99,
+	IF_OP			= 0xa0,
+	ELSE_OP			= 0xa1,
 	RETURN_OP		= 0xa4,
 };
 
 /**
+ * enum psd_coord - Coordination types for P-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum psd_coord {
+	SW_ALL = 0xfc,
+	SW_ANY = 0xfd,
+	HW_ALL = 0xfe
+};
+
+/**
+ * enum csd_coord -  Coordination types for C-states
+ *
+ * The type of coordination that exists (hardware) or is required (software) as
+ * a result of the underlying hardware dependency
+ */
+enum csd_coord {
+	CSD_HW_ALL = 0xfe,
+};
+
+/**
+ * struct acpi_cstate - Information about a C-State
+ *
+ * @ctype: C State type (1=C1, 2=C2, 3=C3)
+ * @latency: Worst-case latency to enter and exit the C State (in uS)
+ * @power: Average power consumption of the processor when in this C-State (mW)
+ * @resource: Register to read to place the processor in this state
+ */
+struct acpi_cstate {
+	uint ctype;
+	uint latency;
+	uint power;
+	struct acpi_gen_regaddr resource;
+};
+
+/**
+ * struct acpi_tstate - Information about a Throttling Supported State
+ *
+ * See ACPI v6.3 section 8.4.5.2: _TSS (Throttling Supported States)
+ *
+ * @percent: Percent of the core CPU operating frequency that will be
+ *	available when this throttling state is invoked
+ * @power: Throttling state’s maximum power dissipation (mw)
+ * @latency: Worst-case latency (uS) that the CPU is unavailable during a
+ *	transition from any throttling state to this throttling state
+ * @control: Value to be written to the Processor Control Register
+ *	(THROTTLE_CTRL) to initiate a transition to this throttling state
+ * @status: Value in THROTTLE_STATUS when in this state
+ */
+struct acpi_tstate {
+	uint percent;
+	uint power;
+	uint latency;
+	uint control;
+	uint status;
+};
+
+/**
  * acpigen_get_current() - Get the current ACPI code output pointer
  *
  * @ctx: ACPI context pointer
@@ -563,4 +638,344 @@
 			       const char *dw0_read, const char *dw0_write,
 			       struct acpi_gpio *gpio, bool enable);
 
+/**
+ * acpigen_write_prw() - Write a power resource for wake (_PRW)
+ *
+ * @ctx: ACPI context pointer
+ * @wake: GPE that wakes up the device
+ * @level: Deepest power system sleeping state that can be entered while still
+ *	providing wake functionality
+ */
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+
+/**
+ * acpigen_write_if() - Write an If block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_if(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_if_lequal_op_int() - Write comparison between op and integer
+ *
+ * Generates ACPI code for checking if operand1 and operand2 are equal
+ *
+ * If (Lequal (op, val))
+ *
+ * @ctx: ACPI context pointer
+ * @op: Operand to check
+ * @val: Value to check against
+ */
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val);
+
+/**
+ * acpigen_write_else() - Write an Ef block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_else(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_to_buffer() - Write a ToBuffer operation
+ *
+ * E.g.: to generate: ToBuffer (Arg0, Local0)
+ * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_to_integer() - Write a ToInteger operation
+ *
+ * E.g.: to generate: ToInteger (Arg0, Local0)
+ * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_return_byte_buffer() - Write a return of a byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arr: Array of bytes to return
+ * @size: Number of bytes
+ */
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+				      size_t size);
+
+/**
+ * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg);
+
+/**
+ * acpigen_write_return_byte() - Write a return of a byte
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+
+/**
+ * acpigen_write_dsm_start() - Start a _DSM method
+ *
+ * Generate ACPI AML code to start the _DSM method.
+ *
+ * The functions need to be called in the correct sequence as below.
+ *
+ * Within the <generate-code-here> region, Local0 and Local1 must be are left
+ * untouched, but Local2-Local7 can be used
+ *
+ * Arguments passed into _DSM method:
+ * Arg0 = UUID
+ * Arg1 = Revision
+ * Arg2 = Function index
+ * Arg3 = Function-specific arguments
+ *
+ * AML code generated looks like this:
+ * Method (_DSM, 4, Serialized) {   -- acpigen_write_dsm_start)
+ *	ToBuffer (Arg0, Local0)
+ *	If (LEqual (Local0, ToUUID(uuid))) {  -- acpigen_write_dsm_uuid_start
+ *		ToInteger (Arg2, Local1)
+ *		If (LEqual (Local1, 0)) {  -- acpigen_write_dsm_uuid_start_cond
+ *			<generate-code-here>
+ *		}                          -- acpigen_write_dsm_uuid_end_cond
+ *		...
+ *		If (LEqual (Local1, n)) {  -- acpigen_write_dsm_uuid_start_cond
+ *			<generate-code-here>
+ *		}                          -- acpigen_write_dsm_uuid_end_cond
+ *		Return (Buffer (One) { 0x0 })
+ *	}                                  -- acpigen_write_dsm_uuid_end
+ *	...
+ *	If (LEqual (Local0, ToUUID(uuidn))) {
+ *	...
+ *	}
+ *	Return (Buffer (One) { 0x0 })  -- acpigen_write_dsm_end
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_start(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_start() - Start a new UUID block
+ *
+ * This starts generation of code to handle a particular UUID:
+ *
+ *	If (LEqual (Local0, ToUUID(uuid))) {
+ *		ToInteger (Arg2, Local1)
+ *
+ * @ctx: ACPI context pointer
+ */
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid);
+
+/**
+ * acpigen_write_dsm_uuid_start_cond() - Start a new condition block
+ *
+ * This starts generation of condition-checking code to handle a particular
+ * function:
+ *
+ *		If (LEqual (Local1, i))
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq);
+
+/**
+ * acpigen_write_dsm_uuid_end_cond() - Start a new condition block
+ *
+ * This ends generation of condition-checking code to handle a particular
+ * function:
+ *
+ *		}
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_end() - End a UUID block
+ *
+ * This ends generation of code to handle a particular UUID:
+ *
+ *		Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_end() - End a _DSM method
+ *
+ * This ends generates of the _DSM block:
+ *
+ *	Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_processor() - Write a Processor package
+ *
+ * This emits a Processor package header with the required information. The
+ * caller must complete the information and call acpigen_pop_len() at the end
+ *
+ * @ctx: ACPI context pointer
+ * @cpuindex: CPU number
+ * @pblock_addr: PBlk system IO address
+ * @pblock_len: PBlk length
+ */
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+			     u32 pblock_addr, uint pblock_len);
+
+/**
+ * acpigen_write_processor_package() - Write a package containing the processors
+ *
+ * The package containins the name of each processor in the SoC
+ *
+ * @ctx: ACPI context pointer
+ * @name: Package name (.e.g "PPKG")
+ * @first_core: Number of the first core (e.g. 0)
+ * @core_count: Number of cores (e.g. 4)
+ */
+void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name,
+				     uint first_core, uint core_count);
+
+/**
+ * acpigen_write_processor_cnot() - Write a processor notification method
+ *
+ * This writes a method that notifies all CPU cores
+ *
+ * @ctx: ACPI context pointer
+ * @num_cores: Number of CPU cores
+ */
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores);
+
+/**
+ * acpigen_write_ppc() - generates a function returning max P-states
+ *
+ * @ctx: ACPI context pointer
+ * @num_pstates: Number of pstates to return
+ */
+void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates);
+
+/**
+ * acpigen_write_ppc() - generates a function returning PPCM
+ *
+ * This returns the maximum number of supported P-states, as saved in the
+ * variable PPCM
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_ppc_nvs(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_tpc() - Write a _TPC method that returns the TPC limit
+ *
+ * @ctx: ACPI context pointer
+ * @gnvs_tpc_limit: Variable that holds the TPC limit
+ */
+void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit);
+
+/**
+ * acpigen_write_pss_package() - Write a PSS package
+ *
+ * See ACPI v6.3 section 8.4.6: Processor Performance Control
+ *
+ * @ctx: ACPI context pointer
+ * @corefreq: CPU core frequency in MHz
+ * @translat: worst-case latency in uS that the CPU is unavailable during a
+ *	transition from any performance state to this performance state
+ * @busmlat: worst-case latency in microseconds that Bus Masters are prevented
+ *	from accessing memory during a transition from any performance state to
+ *	this performance state
+ * @control: Value to write to PERF_CTRL to move to this performance state
+ * @status: Expected PERF_STATUS value when in this state
+ */
+void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power,
+			       uint translat, uint busmlat, uint control,
+			       uint status);
+
+/**
+ * acpigen_write_psd_package() - Write a PSD package
+ *
+ * Writes a P-State dependency package
+ *
+ * See ACPI v6.3 section 8.4.6.5: _PSD (P-State Dependency)
+ *
+ * @ctx: ACPI context pointer
+ * @domain: Dependency domain number to which this P state entry belongs
+ * @numprocs: Number of processors belonging to the domain for this logical
+ *	processor’s P-states
+ * @coordtype: Coordination type
+ */
+void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
+			       enum psd_coord coordtype);
+
+/**
+ * acpigen_write_cst_package() - Write a _CST package
+ *
+ * See ACPI v6.3 section 8.4.2.1: _CST (C States)
+ *
+ * @ctx: ACPI context pointer
+ * @entry: Array of entries
+ * @nentries; Number of entries
+ */
+void acpigen_write_cst_package(struct acpi_ctx *ctx,
+			       const struct acpi_cstate *entry, int nentries);
+
+/**
+ * acpigen_write_csd_package() - Write a _CSD Package
+ *
+ * See ACPI v6.3 section 8.4.2.2: _CSD (C-State Dependency)
+ *
+ * @ctx: ACPI context pointer
+ * @domain: dependency domain number to which this C state entry belongs
+ * @numprocs: number of processors belonging to the domain for the particular
+ *	C-state
+ * @coordtype: Co-ordination type
+ * @index: Index of the C-State entry in the _CST object for which the
+ *	dependency applies
+ */
+void acpigen_write_csd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
+			       enum csd_coord coordtype, uint index);
+
+/**
+ * acpigen_write_tss_package() - Write a _TSS package
+ *
+ * @ctx: ACPI context pointer
+ * @entry: Entries to write
+ * @nentries: Number of entries to write
+ */
+void acpigen_write_tss_package(struct acpi_ctx *ctx,
+			       struct acpi_tstate *entry, int nentries);
+
+/**
+ * acpigen_write_tsd_package() - Write a _TSD package
+ *
+ * See ACPI v6.3 section 8.4.5.4: _TSD (T-State Dependency)
+ *
+ * @ctx: ACPI context pointer
+ * @domain: dependency domain number to which this T state entry belongs
+ * @numprocs: Number of processors belonging to the domain for this logical
+ *	processor’s T-states
+ * @coordtype: Coordination type
+ */
+void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
+			       enum psd_coord coordtype);
+
 #endif

diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index a57dd26..3ae1894 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h

@@ -701,4 +701,51 @@
  */
 int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio);
 
+/**
+ * devm_gpiod_get_index - Resource-managed gpiod_get()
+ * @dev:	GPIO consumer
+ * @con_id:	function within the GPIO consumer
+ * @index:	index of the GPIO to obtain in the consumer
+ * @flags:	optional GPIO initialization flags
+ *
+ * Managed gpiod_get(). GPIO descriptors returned from this function are
+ * automatically disposed on device unbind.
+ * Return the GPIO descriptor corresponding to the function con_id of device
+ * dev, -ENOENT if no GPIO has been assigned to the requested function, or
+ * another IS_ERR() code if an error occurred while trying to acquire the GPIO.
+ */
+struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id,
+				       unsigned int index, int flags);
+
+#define devm_gpiod_get(dev, id, flags) devm_gpiod_get_index(dev, id, 0, flags)
+/**
+ * gpiod_get_optional - obtain an optional GPIO for a given GPIO function
+ * @dev: GPIO consumer, can be NULL for system-global GPIOs
+ * @con_id: function within the GPIO consumer
+ * @index:	index of the GPIO to obtain in the consumer
+ * @flags: optional GPIO initialization flags
+ *
+ * This is equivalent to devm_gpiod_get(), except that when no GPIO was
+ * assigned to the requested function it will return NULL. This is convenient
+ * for drivers that need to handle optional GPIOs.
+ */
+struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev,
+						const char *id,
+						unsigned int index,
+						int flags);
+
+#define devm_gpiod_get_optional(dev, id, flags) \
+	devm_gpiod_get_index_optional(dev, id, 0, flags)
+
+/**
+ * devm_gpiod_put - Resource-managed gpiod_put()
+ * @dev:	GPIO consumer
+ * @desc:	GPIO descriptor to dispose of
+ *
+ * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or
+ * devm_gpiod_get_index(). Normally this function will not be called as the GPIO
+ * will be disposed of by the resource management code.
+ */
+void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc);
+
 #endif	/* _ASM_GENERIC_GPIO_H_ */

diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 62e61d4..637de0c 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h

@@ -27,8 +27,6 @@
 #include <linux/types.h>
 
 struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
 	unsigned long	bi_flashstart;	/* start of FLASH memory */
 	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
@@ -70,12 +68,10 @@
 #endif
 	ulong	        bi_arch_number;	/* unique id for this board */
 	ulong	        bi_boot_params;	/* where this board expects params */
-#ifdef CONFIG_NR_DRAM_BANKS
 	struct {			/* RAM configuration */
 		phys_addr_t start;
 		phys_size_t size;
 	} bi_dram[CONFIG_NR_DRAM_BANKS];
-#endif /* CONFIG_NR_DRAM_BANKS */
 };
 
 #endif /* __ASSEMBLY__ */

diff --git a/include/bloblist.h b/include/bloblist.h
index 609ac42..5784c22 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h

@@ -27,6 +27,14 @@
 	BLOBLISTT_SPL_HANDOFF,		/* Hand-off info from SPL */
 	BLOBLISTT_VBOOT_CTX,		/* Chromium OS verified boot context */
 	BLOBLISTT_VBOOT_HANDOFF,	/* Chromium OS internal handoff info */
+	/*
+	 * Advanced Configuration and Power Interface Global Non-Volatile
+	 * Sleeping table. This forms part of the ACPI tables passed to Linux.
+	 */
+	BLOBLISTT_ACPI_GNVS,
+	BLOBLISTT_INTEL_VBT,		/* Intel Video-BIOS table */
+	BLOBLISTT_TPM2_TCG_LOG,		/* TPM v2 log space */
+	BLOBLISTT_TCPA_LOG,		/* TPM log space */
 };
 
 /**

diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h
index 7f64152..738f73e 100644
--- a/include/broadcom/chimp.h
+++ b/include/broadcom/chimp.h

@@ -9,6 +9,18 @@
 
 #include <linux/compiler.h>
 
+/*
+ * Chimp binary has health status like initialization complete,
+ * crash or running fine
+ */
+#define BCM_CHIMP_RUNNIG_GOOD	0x8000
+
+enum {
+	CHIMP_HANDSHAKE_SUCCESS = 0,
+	CHIMP_HANDSHAKE_WAIT_ERROR,
+	CHIMP_HANDSHAKE_WAIT_TIMEOUT,
+};
+
 /**
  * chimp_fastboot_optee() - api to load bnxt firmware
  *

diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
deleted file mode 100644
index 5c29a4f..0000000
--- a/include/configs/P1023RDB.h
+++ /dev/null

@@ -1,338 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Authors:  Roy Zang <tie-fei.zang@freescale.com>
- *	     Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
-#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	66666666
-#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_HWCONFIG
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/* Implement conversion of addresses in the LBC */
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	1
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
-#define CONFIG_SYS_SPD_BUS_NUM          0
-#define SPD_EEPROM_ADDRESS              0x50
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
- * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
- * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
- * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
-				| BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
-
-#define CONFIG_SYS_NAND_BASE		0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
-				| BR_PS_8		/* Port Size = 8bit */ \
-				| BR_MS_FCM		/* MSEL = FCM */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
-				| OR_FCM_PGS \
-				| OR_FCM_CSCT \
-				| OR_FCM_CST \
-				| OR_FCM_CHT \
-				| OR_FCM_SCY_1 \
-				| OR_FCM_TRLX \
-				| OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_BUS_NUM		0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, Slot 1, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-/* Qman/Bman */
-#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
-#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-
-/* For FM */
-#define CONFIG_SYS_DPAA_FMAN
-
-/* Default address of microcode for the Linux Fman driver */
-/* QE microcode/firmware address */
-#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
-
-#define CONFIG_SYS_TBIPA_VALUE	8
-#define CONFIG_ETHPRIME		"FM1@DTSEC1"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS	\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"loadaddr=1000000\0"					\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
-	"tftpflash=tftpboot $loadaddr $uboot; "			\
-		"protect off $ubootaddr +$filesize; "		\
-		"erase $ubootaddr +$filesize; "			\
-		"cp.b $loadaddr $ubootaddr $filesize; "		\
-		"protect on $ubootaddr +$filesize; "		\
-		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=2000000\0"					\
-	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
-	"fdtaddr=1e00000\0"					\
-	"fdtfile=p1023rdb.dtb\0"				\
-	"othbootargs=ramdisk_size=600000\0"			\
-	"bdev=sda1\0"						\
-	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
-
-#define CONFIG_HDBOOT					\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$serverip:$rootpath "					\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"			\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-	"console=$consoledev,$baudrate $othbootargs;"			\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
-
-#endif	/* __CONFIG_H */

diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
deleted file mode 100644
index 873d39a..0000000
--- a/include/configs/P5020DS.h
+++ /dev/null

@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P5020 DS board configuration file
- * Also supports P5010 DS
- */
-#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
-
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
-#define CONFIG_SYS_FSL_RAID_ENGINE
-#define CONFIG_SYS_DPAA_RMAN
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 9c4ef36..5af90d9 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h

@@ -66,6 +66,12 @@
 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
 
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
 #if CONFIG_IS_ENABLED(CMD_PXE)
 # define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
 #else
@@ -84,6 +90,7 @@
 	func(MMC, mmc, 1) \
 	func(LEGACY_MMC, legacy_mmc, 1) \
 	func(NAND, nand, 0) \
+	BOOT_TARGET_USB(func) \
 	BOOT_TARGET_PXE(func) \
 	BOOT_TARGET_DHCP(func)
 
@@ -280,8 +287,6 @@
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
 
-/* SPI flash. */
-
 /* Network. */
 /* Enable Atheros phy driver */
 

diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index 06cbb03..ee9ddb1 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h

@@ -22,4 +22,16 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
 #endif /* __EBISU_H */

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index c8a7603..1b47e18 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h

@@ -2,7 +2,7 @@
 /*
  * Configuration header file for K3 J721E EVM
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
  */
 
@@ -23,8 +23,10 @@
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
 					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#define CONFIG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
+#define CONFIG_SYS_UBOOT_BASE		0x50080000
 /*
  * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
  * possible (to allow the build to go through), as this directly affects
@@ -81,16 +83,29 @@
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
 
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
+	"addr_mainr5f0_0load=0x88000000\0"				\
+	"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0"		\
+	"addr_mcur5f0_0load=0x89000000\0"				\
+	"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
+	"addr_mcur5f0_0load=0x89000000\0"				\
+	"name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
+#else
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
+#endif /* CONFIG_SYS_K3_SPL_ATF */
+
 /* U-Boot MMC-specific configuration */
 #define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC				\
 	"boot=mmc\0"							\
 	"mmcdev=1\0"							\
 	"bootpart=1:2\0"						\
 	"bootdir=/boot\0"						\
-	"addr_mainr5f0_0load=88000000\0"					\
-	"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0"		\
-	"addr_mcur5f0_0load=89000000\0"					\
-	"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"		\
+	EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
 	"rd_spec=-\0"							\
 	"init_mmc=run args_all args_mmc\0"				\
 	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
@@ -109,15 +124,28 @@
 		"${bootdir}/${name_fit}\0"				\
 	"partitions=" PARTS_DEFAULT
 
+/* Set the default list of remote processors to boot */
+#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #ifdef DEFAULT_RPROCS
 #undef DEFAULT_RPROCS
 #endif
+#endif
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 #define DEFAULT_RPROCS	""						\
 		"3 /lib/firmware/j7-main-r5f0_1-fw "			\
 		"4 /lib/firmware/j7-main-r5f1_0-fw "			\
+		"5 /lib/firmware/j7-main-r5f1_1-fw "			\
 		"6 /lib/firmware/j7-c66_0-fw "				\
 		"7 /lib/firmware/j7-c66_1-fw "				\
 		"8 /lib/firmware/j7-c71_0-fw "
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define DEFAULT_RPROCS ""						\
+		"2 /lib/firmware/j7200-main-r5f0_0-fw "			\
+		"3 /lib/firmware/j7200-main-r5f0_1-fw "
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
 
 /* set default dfu_bufsiz to 128KB (sector size of OSPI) */
 #define EXTRA_ENV_DFUARGS \

diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
index d7186ab..22dfb5d 100644
--- a/include/configs/km/km-mpc832x.h
+++ b/include/configs/km/km-mpc832x.h

@@ -11,20 +11,6 @@
 #define CONFIG_83XX_PCICLK		66000000
 
 /*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH1		/* GETH1 */
-#define UEC_VERBOSE_DEBUG	1
-
-#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS

diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
index bdbb8bf..798b126 100644
--- a/include/configs/km/km-mpc8360.h
+++ b/include/configs/km/km-mpc8360.h

@@ -7,20 +7,6 @@
  */
 
 /*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH1		/* GETH1 */
-#define UEC_VERBOSE_DEBUG	1
-
-#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-
-/*
  * System IO Setup
  */
 #define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)

diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 7c7f2d4..7aacd37 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h

@@ -61,16 +61,6 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_NUM_I2C_BUSES	4

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 1b74177..a9bf213 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h

@@ -12,24 +12,6 @@
 
 #include <linux/stringify.h>
 
-#if defined(CONFIG_TARGET_P1020MBG)
-#define CONFIG_BOARDNAME "P1020MBG-PC"
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK		0x03
-#define __SW_BOOT_NOR		0xe4
-#define __SW_BOOT_SD		0x54
-#define CONFIG_SYS_L2_SIZE	(256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P1020UTM)
-#define CONFIG_BOARDNAME "P1020UTM-PC"
-#define __SW_BOOT_MASK		0x03
-#define __SW_BOOT_NOR		0xe0
-#define __SW_BOOT_SD		0x50
-#define CONFIG_SYS_L2_SIZE	(256 << 10)
-#endif
-
 #if defined(CONFIG_TARGET_P1020RDB_PC)
 #define CONFIG_BOARDNAME "P1020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
@@ -74,51 +56,6 @@
  */
 #endif
 
-#if defined(CONFIG_TARGET_P1021RDB)
-#define CONFIG_BOARDNAME "P1021RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_VSC7385_ENET
-#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
-						addresses in the LBC */
-#define __SW_BOOT_MASK		0x03
-#define __SW_BOOT_NOR		0x5c
-#define __SW_BOOT_SPI		0x1c
-#define __SW_BOOT_SD		0x9c
-#define __SW_BOOT_NAND		0xec
-#define __SW_BOOT_PCIE		0x6c
-#define CONFIG_SYS_L2_SIZE	(256 << 10)
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-#endif
-
-#if defined(CONFIG_TARGET_P1024RDB)
-#define CONFIG_BOARDNAME "P1024RDB"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SLIC
-#define __SW_BOOT_MASK		0xf3
-#define __SW_BOOT_NOR		0x00
-#define __SW_BOOT_SPI		0x08
-#define __SW_BOOT_SD		0x04
-#define __SW_BOOT_NAND		0x0c
-#define CONFIG_SYS_L2_SIZE	(256 << 10)
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB)
-#define CONFIG_BOARDNAME "P1025RDB"
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SLIC
-
-#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
-						addresses in the LBC */
-#define __SW_BOOT_MASK		0xf3
-#define __SW_BOOT_NOR		0x00
-#define __SW_BOOT_SPI		0x08
-#define __SW_BOOT_SD		0x04
-#define __SW_BOOT_NAND		0x0c
-#define CONFIG_SYS_L2_SIZE	(256 << 10)
-#endif
-
 #if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_BOARDNAME "P2020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
@@ -246,7 +183,7 @@
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 #else
@@ -313,12 +250,9 @@
 /*
  * Local Bus Definitions
  */
-#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
 #define CONFIG_SYS_FLASH_BASE		0xec000000
-#elif defined(CONFIG_TARGET_P1020UTM)
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
-#define CONFIG_SYS_FLASH_BASE		0xee000000
 #else
 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
 #define CONFIG_SYS_FLASH_BASE		0xef000000
@@ -451,6 +385,7 @@
 
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
+#define __VSCFW_ADDR			"vscfw_addr=ef000000"
 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
 
 #ifdef CONFIG_PHYS_64BIT
@@ -654,42 +589,6 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #endif /* CONFIG_QE */
 
-#ifdef CONFIG_TARGET_P1025RDB
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
-
-#undef CONFIG_UEC_ETH
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1	/* ETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
-#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH5	/* ETH5 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH5
-#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
-#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
-#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
-#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
-#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
-#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_TARGET_P1025RDB */
-
 /*
  * Environment
  */
@@ -809,6 +708,7 @@
 "ramdisk_size=120000\0"	\
 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+__stringify(__VSCFW_ADDR)"\0" \
 __stringify(__NOR_RST_CMD)"\0" \
 __stringify(__SPI_RST_CMD)"\0" \
 __stringify(__SD_RST_CMD)"\0" \

diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 240df9c..db06fa5 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h

@@ -19,4 +19,16 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
 #endif /* __SALVATOR_X_H */

diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 6e39538..010d28a 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h

@@ -24,7 +24,6 @@
 
 /* No falcon support */
 #undef CONFIG_SPL_OS_BOOT
-#undef CONFIG_SPL_FPGA_SUPPORT
 
 /* FPGA commands that we don't use */
 

diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index 15fb627..165c82d 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h

@@ -19,4 +19,16 @@
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
 #endif /* __ULCB_H */

diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index d7255a0..8b41632 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h

@@ -94,6 +94,18 @@
 # define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_PXE(func)	func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func)	func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
 #if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
 # define BOOT_TARGET_DEVICES_XSPI(func)	func(XSPI, xspi, 0)
 #else
@@ -135,8 +147,8 @@
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_XSPI(func) \
 	BOOT_TARGET_DEVICES_DFU_USB(func) \
-	func(PXE, pxe, na) \
-	func(DHCP, dhcp, na)
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
 
 #include <config_distro_bootcmd.h>
 

diff --git a/include/dm/device.h b/include/dm/device.h
index 953706c..ac3b6c1 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h

@@ -197,7 +197,7 @@
 	ulong data;
 };
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 #define of_match_ptr(_ptr)	(_ptr)
 #else
 #define of_match_ptr(_ptr)	NULL

diff --git a/include/dm/device_compat.h b/include/dm/device_compat.h
index 3d8cd09..8f26053 100644
--- a/include/dm/device_compat.h
+++ b/include/dm/device_compat.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
  * Copyright (c) 2013 Google, Inc
  *
  * (C) Copyright 2012
@@ -10,6 +11,8 @@
 #ifndef _DM_DEVICE_COMPAT_H
 #define _DM_DEVICE_COMPAT_H
 
+#include <log.h>
+#include <linux/build_bug.h>
 #include <linux/compat.h>
 
 /*
@@ -33,54 +36,106 @@
 #endif
 
 /*
- * REVISIT:
- * print device name like Linux
+ * Define a new identifier which can be tested on by C code. A similar
+ * definition is made for DEBUG in <log.h>.
  */
-#define dev_printk(dev, fmt, ...)				\
-({								\
-	printk(fmt, ##__VA_ARGS__);				\
+#ifdef VERBOSE_DEBUG
+#define _VERBOSE_DEBUG 1
+#else
+#define _VERBOSE_DEBUG 0
+#endif
+
+/**
+ * dev_printk_emit() - Emit a formatted log message
+ * @cat: Category of the message
+ * @level: Log level of the message
+ * @fmt: Format string
+ * @...: Arguments for @fmt
+ *
+ * This macro logs a message through the appropriate channel. It is a macro so
+ * the if statements can be optimized out (as @level should be a constant known
+ * at compile-time).
+ *
+ * If DEBUG or VERBOSE_DEBUG is defined, then some messages are always printed
+ * (through printf()). This is to match the historical behavior of the dev_xxx
+ * functions.
+ *
+ * If LOG is enabled, use log() to emit the message, otherwise print it based on
+ * the console loglevel.
+ */
+#define dev_printk_emit(cat, level, fmt, ...) \
+({ \
+	if ((_DEBUG && level == LOGL_DEBUG) || \
+	    (_VERBOSE_DEBUG && level == LOGL_DEBUG_CONTENT)) \
+		printf(fmt, ##__VA_ARGS__); \
+	else if (CONFIG_IS_ENABLED(LOG)) \
+		log(cat, level, fmt, ##__VA_ARGS__); \
+	else if (level < CONFIG_VAL(LOGLEVEL)) \
+		printf(fmt, ##__VA_ARGS__); \
 })
 
-#define __dev_printk(level, dev, fmt, ...)			\
-({								\
-	if (level < CONFIG_VAL(LOGLEVEL))			\
-		dev_printk(dev, fmt, ##__VA_ARGS__);		\
+/**
+ * __dev_printk() - Log a message for a device
+ * @level: Log level of the message
+ * @dev: A &struct udevice or &struct device
+ * @fmt: Format string
+ * @...: Arguments for @fmt
+ *
+ * This macro formats and prints dev_xxx log messages. It is done as a macro
+ * because working with variadic argument is much easier this way, we can
+ * interrogate the type of device we are passed (and whether it *is* a &struct
+ * udevice or &struct device), and dev_printk_emit() can optimize out unused if
+ * branches.
+ *
+ * Because this is a macro, we must enforce type checks ourselves. Ideally, we
+ * would only accept udevices, but there is a significant amount of code (mostly
+ * USB) which calls dev_xxx with &struct device. When assigning ``__dev``, we
+ * must first cast ``dev`` to ``void *`` so we don't get warned when ``dev`` is
+ * a &struct device. Even though the latter branch is not taken, it will still
+ * get compiled and type-checked.
+ *
+ * The format strings in case of a ``NULL`` ``dev`` MUST be kept the same.
+ * Otherwise, @fmt will be duplicated in the data section (with slightly
+ * different prefixes). This is why ``(NULL udevice *)`` is printed as two
+ * string arguments, and not by string pasting.
+ */
+#define __dev_printk(level, dev, fmt, ...) \
+({ \
+	if (__same_type(dev, struct device  *)) { \
+		dev_printk_emit(LOG_CATEGORY, level, fmt, ##__VA_ARGS__); \
+	} else { \
+		BUILD_BUG_ON(!__same_type(dev, struct udevice *)); \
+		struct udevice *__dev = (void *)dev; \
+		if (__dev) \
+			dev_printk_emit(__dev->driver->id, level, \
+					"%s %s: " fmt, \
+					__dev->driver->name, __dev->name, \
+					##__VA_ARGS__); \
+		else \
+			dev_printk_emit(LOG_CATEGORY, level, \
+					"%s %s: " fmt, \
+					"(NULL", "udevice *)", \
+					##__VA_ARGS__); \
+	} \
 })
 
 #define dev_emerg(dev, fmt, ...) \
-	__dev_printk(0, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_EMERG, dev, fmt, ##__VA_ARGS__)
 #define dev_alert(dev, fmt, ...) \
-	__dev_printk(1, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_ALERT, dev, fmt, ##__VA_ARGS__)
 #define dev_crit(dev, fmt, ...) \
-	__dev_printk(2, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_CRIT, dev, fmt, ##__VA_ARGS__)
 #define dev_err(dev, fmt, ...) \
-	__dev_printk(3, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_ERR, dev, fmt, ##__VA_ARGS__)
 #define dev_warn(dev, fmt, ...) \
-	__dev_printk(4, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_WARNING, dev, fmt, ##__VA_ARGS__)
 #define dev_notice(dev, fmt, ...) \
-	__dev_printk(5, dev, fmt, ##__VA_ARGS__)
+	__dev_printk(LOGL_NOTICE, dev, fmt, ##__VA_ARGS__)
 #define dev_info(dev, fmt, ...) \
-	__dev_printk(6, dev, fmt, ##__VA_ARGS__)
-
-#ifdef DEBUG
+	__dev_printk(LOGL_INFO, dev, fmt, ##__VA_ARGS__)
 #define dev_dbg(dev, fmt, ...) \
-	__dev_printk(7, dev, fmt, ##__VA_ARGS__)
-#else
-#define dev_dbg(dev, fmt, ...)					\
-({								\
-	if (0)							\
-		__dev_printk(7, dev, fmt, ##__VA_ARGS__);	\
-})
-#endif
-
-#ifdef VERBOSE_DEBUG
-#define dev_vdbg	dev_dbg
-#else
-#define dev_vdbg(dev, fmt, ...)					\
-({								\
-	if (0)							\
-		__dev_printk(7, dev, fmt, ##__VA_ARGS__);	\
-})
-#endif
+	__dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__)
+#define dev_vdbg(dev, fmt, ...) \
+	__dev_printk(LOGL_DEBUG_CONTENT, dev, fmt, ##__VA_ARGS__)
 
 #endif

diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index f95a00d..2fa65c9 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h

@@ -407,6 +407,7 @@
  * @np:		pointer to a device tree node containing a list
  * @list_name:	property name that contains a list
  * @cells_name:	property name that specifies phandles' arguments count
+ * @cells_count: Cell count to use if @cells_name is NULL
  * @index:	index of a phandle to parse out
  * @out_args:	optional pointer to output arguments structure (will be filled)
  * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
@@ -440,7 +441,8 @@
  */
 int of_parse_phandle_with_args(const struct device_node *np,
 			       const char *list_name, const char *cells_name,
-			       int index, struct of_phandle_args *out_args);
+			       int cells_count, int index,
+			       struct of_phandle_args *out_args);
 
 /**
  * of_count_phandle_with_args() - Count the number of phandle in a list

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 4ec5fa6..88f10c4 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h

@@ -94,6 +94,7 @@
 	UCLASS_RESET,		/* Reset controller device */
 	UCLASS_RNG,		/* Random Number Generator */
 	UCLASS_RTC,		/* Real time clock device */
+	UCLASS_SCMI_AGENT,	/* Interface with an SCMI server */
 	UCLASS_SCSI,		/* SCSI device */
 	UCLASS_SERIAL,		/* Serial UART */
 	UCLASS_SIMPLE_BUS,	/* Bus with child devices */

diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
new file mode 100644
index 0000000..a1aa8c0
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed-clock.h

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+#define ASPEED_CLK_MAC1RCLK		36
+#define ASPEED_CLK_MAC2RCLK		37
+#define ASPEED_CLK_DPLL		38
+#define ASPEED_CLK_D2PLL	39

diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h
deleted file mode 100644
index 4803abe..0000000
--- a/include/dt-bindings/clock/ast2500-scu.h
+++ /dev/null

@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Google Inc.
- */
-
-/* Core Clocks */
-#define PLL_HPLL	1
-#define PLL_DPLL	2
-#define PLL_D2PLL	3
-#define PLL_MPLL	4
-#define ARMCLK		5
-
-
-/* Bus Clocks, derived from core clocks */
-#define BCLK_PCLK	101
-#define BCLK_LHCLK	102
-#define BCLK_MACCLK	103
-#define BCLK_SDCLK	104
-#define BCLK_ARMCLK	105
-
-#define MCLK_DDR	201
-
-/* Special clocks */
-#define PCLK_UART1	501
-#define PCLK_UART2	502
-#define PCLK_UART3	503
-#define PCLK_UART4	504
-#define PCLK_UART5	505
-#define PCLK_MAC1	506
-#define PCLK_MAC2	507

diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
index 0e3ed3f..fe852bb 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h

@@ -55,5 +55,6 @@
 #define K210_CLK_OTP    43
 #define K210_CLK_RTC    44
 #define K210_CLK_ACLK   45
+#define K210_CLK_CLINT  46
 
 #endif /* CLOCK_K210_SYSCTL_H */

diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,ipq4019-gcc.h
new file mode 100644
index 0000000..7130e22
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq4019-gcc.h

@@ -0,0 +1,96 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_CLK_IPQ4019_H__
+#define __QCOM_CLK_IPQ4019_H__
+
+#define GCC_DUMMY_CLK					0
+#define AUDIO_CLK_SRC					1
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			2
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			3
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			4
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			5
+#define BLSP1_UART1_APPS_CLK_SRC			6
+#define BLSP1_UART2_APPS_CLK_SRC			7
+#define GCC_USB3_MOCK_UTMI_CLK_SRC			8
+#define GCC_APPS_CLK_SRC				9
+#define GCC_APPS_AHB_CLK_SRC				10
+#define GP1_CLK_SRC					11
+#define GP2_CLK_SRC					12
+#define GP3_CLK_SRC					13
+#define SDCC1_APPS_CLK_SRC				14
+#define FEPHY_125M_DLY_CLK_SRC				15
+#define WCSS2G_CLK_SRC					16
+#define WCSS5G_CLK_SRC					17
+#define GCC_APSS_AHB_CLK				18
+#define GCC_AUDIO_AHB_CLK				19
+#define GCC_AUDIO_PWM_CLK				20
+#define GCC_BLSP1_AHB_CLK				21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_DCD_XO_CLK					28
+#define GCC_GP1_CLK					29
+#define GCC_GP2_CLK					30
+#define GCC_GP3_CLK					31
+#define GCC_BOOT_ROM_AHB_CLK				32
+#define GCC_CRYPTO_AHB_CLK				33
+#define GCC_CRYPTO_AXI_CLK				34
+#define GCC_CRYPTO_CLK					35
+#define GCC_ESS_CLK					36
+#define GCC_IMEM_AXI_CLK				37
+#define GCC_IMEM_CFG_AHB_CLK				38
+#define GCC_PCIE_AHB_CLK				39
+#define GCC_PCIE_AXI_M_CLK				40
+#define GCC_PCIE_AXI_S_CLK				41
+#define GCC_PCNOC_AHB_CLK				42
+#define GCC_PRNG_AHB_CLK				43
+#define GCC_QPIC_AHB_CLK				44
+#define GCC_QPIC_CLK					45
+#define GCC_SDCC1_AHB_CLK				46
+#define GCC_SDCC1_APPS_CLK				47
+#define GCC_SNOC_PCNOC_AHB_CLK				48
+#define GCC_SYS_NOC_125M_CLK				49
+#define GCC_SYS_NOC_AXI_CLK				50
+#define GCC_TCSR_AHB_CLK				51
+#define GCC_TLMM_AHB_CLK				52
+#define GCC_USB2_MASTER_CLK				53
+#define GCC_USB2_SLEEP_CLK				54
+#define GCC_USB2_MOCK_UTMI_CLK				55
+#define GCC_USB3_MASTER_CLK				56
+#define GCC_USB3_SLEEP_CLK				57
+#define GCC_USB3_MOCK_UTMI_CLK				58
+#define GCC_WCSS2G_CLK					59
+#define GCC_WCSS2G_REF_CLK				60
+#define GCC_WCSS2G_RTC_CLK				61
+#define GCC_WCSS5G_CLK					62
+#define GCC_WCSS5G_REF_CLK				63
+#define GCC_WCSS5G_RTC_CLK				64
+#define GCC_APSS_DDRPLL_VCO				65
+#define GCC_SDCC_PLLDIV_CLK				66
+#define GCC_FEPLL_VCO					67
+#define GCC_FEPLL125_CLK				68
+#define GCC_FEPLL125DLY_CLK				69
+#define GCC_FEPLL200_CLK				70
+#define GCC_FEPLL500_CLK				71
+#define GCC_FEPLL_WCSS2G_CLK				72
+#define GCC_FEPLL_WCSS5G_CLK				73
+#define GCC_APSS_CPU_PLLDIV_CLK				74
+#define GCC_PCNOC_AHB_CLK_SRC				75
+
+#endif

diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
index ac3fde1..67bf8cd 100644
--- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h

@@ -10,56 +10,50 @@
 /* r8a774a1 CPG Core Clocks */
 #define R8A774A1_CLK_Z			0
 #define R8A774A1_CLK_Z2			1
-#define R8A774A1_CLK_ZR			2
-#define R8A774A1_CLK_ZG			3
-#define R8A774A1_CLK_ZTR		4
-#define R8A774A1_CLK_ZTRD2		5
-#define R8A774A1_CLK_ZT			6
-#define R8A774A1_CLK_ZX			7
-#define R8A774A1_CLK_S0D1		8
-#define R8A774A1_CLK_S0D2		9
-#define R8A774A1_CLK_S0D3		10
-#define R8A774A1_CLK_S0D4		11
-#define R8A774A1_CLK_S0D6		12
-#define R8A774A1_CLK_S0D8		13
-#define R8A774A1_CLK_S0D12		14
-#define R8A774A1_CLK_S1D1		15
-#define R8A774A1_CLK_S1D2		16
-#define R8A774A1_CLK_S1D4		17
-#define R8A774A1_CLK_S2D1		18
-#define R8A774A1_CLK_S2D2		19
-#define R8A774A1_CLK_S2D4		20
-#define R8A774A1_CLK_S3D1		21
-#define R8A774A1_CLK_S3D2		22
-#define R8A774A1_CLK_S3D4		23
-#define R8A774A1_CLK_LB			24
-#define R8A774A1_CLK_CL			25
-#define R8A774A1_CLK_ZB3		26
-#define R8A774A1_CLK_ZB3D2		27
-#define R8A774A1_CLK_ZB3D4		28
-#define R8A774A1_CLK_CR			29
-#define R8A774A1_CLK_CRD2		30
-#define R8A774A1_CLK_SD0H		31
-#define R8A774A1_CLK_SD0		32
-#define R8A774A1_CLK_SD1H		33
-#define R8A774A1_CLK_SD1		34
-#define R8A774A1_CLK_SD2H		35
-#define R8A774A1_CLK_SD2		36
-#define R8A774A1_CLK_SD3H		37
-#define R8A774A1_CLK_SD3		38
-#define R8A774A1_CLK_SSP2		39
-#define R8A774A1_CLK_SSP1		40
-#define R8A774A1_CLK_SSPRS		41
-#define R8A774A1_CLK_RPC		42
-#define R8A774A1_CLK_RPCD2		43
-#define R8A774A1_CLK_MSO		44
-#define R8A774A1_CLK_CANFD		45
-#define R8A774A1_CLK_HDMI		46
-#define R8A774A1_CLK_CSI0		47
-#define R8A774A1_CLK_CSIREF		48
-#define R8A774A1_CLK_CP			49
-#define R8A774A1_CLK_CPEX		50
-#define R8A774A1_CLK_R			51
-#define R8A774A1_CLK_OSC		52
+#define R8A774A1_CLK_ZG			2
+#define R8A774A1_CLK_ZTR		3
+#define R8A774A1_CLK_ZTRD2		4
+#define R8A774A1_CLK_ZT			5
+#define R8A774A1_CLK_ZX			6
+#define R8A774A1_CLK_S0D1		7
+#define R8A774A1_CLK_S0D2		8
+#define R8A774A1_CLK_S0D3		9
+#define R8A774A1_CLK_S0D4		10
+#define R8A774A1_CLK_S0D6		11
+#define R8A774A1_CLK_S0D8		12
+#define R8A774A1_CLK_S0D12		13
+#define R8A774A1_CLK_S1D2		14
+#define R8A774A1_CLK_S1D4		15
+#define R8A774A1_CLK_S2D1		16
+#define R8A774A1_CLK_S2D2		17
+#define R8A774A1_CLK_S2D4		18
+#define R8A774A1_CLK_S3D1		19
+#define R8A774A1_CLK_S3D2		20
+#define R8A774A1_CLK_S3D4		21
+#define R8A774A1_CLK_LB			22
+#define R8A774A1_CLK_CL			23
+#define R8A774A1_CLK_ZB3		24
+#define R8A774A1_CLK_ZB3D2		25
+#define R8A774A1_CLK_ZB3D4		26
+#define R8A774A1_CLK_CR			27
+#define R8A774A1_CLK_CRD2		28
+#define R8A774A1_CLK_SD0H		29
+#define R8A774A1_CLK_SD0		30
+#define R8A774A1_CLK_SD1H		31
+#define R8A774A1_CLK_SD1		32
+#define R8A774A1_CLK_SD2H		33
+#define R8A774A1_CLK_SD2		34
+#define R8A774A1_CLK_SD3H		35
+#define R8A774A1_CLK_SD3		36
+#define R8A774A1_CLK_RPC		37
+#define R8A774A1_CLK_RPCD2		38
+#define R8A774A1_CLK_MSO		39
+#define R8A774A1_CLK_HDMI		40
+#define R8A774A1_CLK_CSI0		41
+#define R8A774A1_CLK_CP			42
+#define R8A774A1_CLK_CPEX		43
+#define R8A774A1_CLK_R			44
+#define R8A774A1_CLK_OSC		45
+#define R8A774A1_CLK_CANFD		46
 
 #endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
new file mode 100644
index 0000000..28e0f8f
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774b1 CPG Core Clocks */
+#define R8A774B1_CLK_Z			0
+#define R8A774B1_CLK_ZG			1
+#define R8A774B1_CLK_ZTR		2
+#define R8A774B1_CLK_ZTRD2		3
+#define R8A774B1_CLK_ZT			4
+#define R8A774B1_CLK_ZX			5
+#define R8A774B1_CLK_S0D1		6
+#define R8A774B1_CLK_S0D2		7
+#define R8A774B1_CLK_S0D3		8
+#define R8A774B1_CLK_S0D4		9
+#define R8A774B1_CLK_S0D6		10
+#define R8A774B1_CLK_S0D8		11
+#define R8A774B1_CLK_S0D12		12
+#define R8A774B1_CLK_S1D2		13
+#define R8A774B1_CLK_S1D4		14
+#define R8A774B1_CLK_S2D1		15
+#define R8A774B1_CLK_S2D2		16
+#define R8A774B1_CLK_S2D4		17
+#define R8A774B1_CLK_S3D1		18
+#define R8A774B1_CLK_S3D2		19
+#define R8A774B1_CLK_S3D4		20
+#define R8A774B1_CLK_LB			21
+#define R8A774B1_CLK_CL			22
+#define R8A774B1_CLK_ZB3		23
+#define R8A774B1_CLK_ZB3D2		24
+#define R8A774B1_CLK_CR			25
+#define R8A774B1_CLK_DDR		26
+#define R8A774B1_CLK_SD0H		27
+#define R8A774B1_CLK_SD0		28
+#define R8A774B1_CLK_SD1H		29
+#define R8A774B1_CLK_SD1		30
+#define R8A774B1_CLK_SD2H		31
+#define R8A774B1_CLK_SD2		32
+#define R8A774B1_CLK_SD3H		33
+#define R8A774B1_CLK_SD3		34
+#define R8A774B1_CLK_RPC		35
+#define R8A774B1_CLK_RPCD2		36
+#define R8A774B1_CLK_MSO		37
+#define R8A774B1_CLK_HDMI		38
+#define R8A774B1_CLK_CSI0		39
+#define R8A774B1_CLK_CP			40
+#define R8A774B1_CLK_CPEX		41
+#define R8A774B1_CLK_R			42
+#define R8A774B1_CLK_OSC		43
+#define R8A774B1_CLK_CANFD		44
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
new file mode 100644
index 0000000..b2fc1d1
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R8A774E1 CPG Core Clocks */
+#define R8A774E1_CLK_Z			0
+#define R8A774E1_CLK_Z2			1
+#define R8A774E1_CLK_ZG			2
+#define R8A774E1_CLK_ZTR		3
+#define R8A774E1_CLK_ZTRD2		4
+#define R8A774E1_CLK_ZT			5
+#define R8A774E1_CLK_ZX			6
+#define R8A774E1_CLK_S0D1		7
+#define R8A774E1_CLK_S0D2		8
+#define R8A774E1_CLK_S0D3		9
+#define R8A774E1_CLK_S0D4		10
+#define R8A774E1_CLK_S0D6		11
+#define R8A774E1_CLK_S0D8		12
+#define R8A774E1_CLK_S0D12		13
+#define R8A774E1_CLK_S1D2		14
+#define R8A774E1_CLK_S1D4		15
+#define R8A774E1_CLK_S2D1		16
+#define R8A774E1_CLK_S2D2		17
+#define R8A774E1_CLK_S2D4		18
+#define R8A774E1_CLK_S3D1		19
+#define R8A774E1_CLK_S3D2		20
+#define R8A774E1_CLK_S3D4		21
+#define R8A774E1_CLK_LB			22
+#define R8A774E1_CLK_CL			23
+#define R8A774E1_CLK_ZB3		24
+#define R8A774E1_CLK_ZB3D2		25
+#define R8A774E1_CLK_ZB3D4		26
+#define R8A774E1_CLK_CR			27
+#define R8A774E1_CLK_CRD2		28
+#define R8A774E1_CLK_SD0H		29
+#define R8A774E1_CLK_SD0		30
+#define R8A774E1_CLK_SD1H		31
+#define R8A774E1_CLK_SD1		32
+#define R8A774E1_CLK_SD2H		33
+#define R8A774E1_CLK_SD2		34
+#define R8A774E1_CLK_SD3H		35
+#define R8A774E1_CLK_SD3		36
+#define R8A774E1_CLK_RPC		37
+#define R8A774E1_CLK_RPCD2		38
+#define R8A774E1_CLK_MSO		39
+#define R8A774E1_CLK_HDMI		40
+#define R8A774E1_CLK_CSI0		41
+#define R8A774E1_CLK_CP			42
+#define R8A774E1_CLK_CPEX		43
+#define R8A774E1_CLK_R			44
+#define R8A774E1_CLK_OSC		45
+#define R8A774E1_CLK_CANFD		46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h
new file mode 100644
index 0000000..61f5287
--- /dev/null
+++ b/include/dt-bindings/net/mscc-phy-vsc8531.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Device Tree constants for Microsemi VSC8531 PHY
+ *
+ * Author: Nagaraju Lakkaraju
+ *
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#ifndef _DT_BINDINGS_MSCC_VSC8531_H
+#define _DT_BINDINGS_MSCC_VSC8531_H
+
+/* PHY LED Modes */
+#define VSC8531_LINK_ACTIVITY			0
+#define VSC8531_LINK_1000_ACTIVITY		1
+#define VSC8531_LINK_100_ACTIVITY		2
+#define VSC8531_LINK_10_ACTIVITY		3
+#define VSC8531_LINK_100_1000_ACTIVITY		4
+#define VSC8531_LINK_10_1000_ACTIVITY		5
+#define VSC8531_LINK_10_100_ACTIVITY		6
+#define VSC8584_LINK_100FX_1000X_ACTIVITY	7
+#define VSC8531_DUPLEX_COLLISION		8
+#define VSC8531_COLLISION			9
+#define VSC8531_ACTIVITY			10
+#define VSC8584_100FX_1000X_ACTIVITY		11
+#define VSC8531_AUTONEG_FAULT			12
+#define VSC8531_SERIAL_MODE			13
+#define VSC8531_FORCE_LED_OFF			14
+#define VSC8531_FORCE_LED_ON			15
+
+#define VSC8531_RGMII_CLK_DELAY_0_2_NS	0
+#define VSC8531_RGMII_CLK_DELAY_0_8_NS	1
+#define VSC8531_RGMII_CLK_DELAY_1_1_NS	2
+#define VSC8531_RGMII_CLK_DELAY_1_7_NS	3
+#define VSC8531_RGMII_CLK_DELAY_2_0_NS	4
+#define VSC8531_RGMII_CLK_DELAY_2_3_NS	5
+#define VSC8531_RGMII_CLK_DELAY_2_6_NS	6
+#define VSC8531_RGMII_CLK_DELAY_3_4_NS	7
+
+#endif

diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
index d84ea0e..d351835 100644
--- a/include/dt-bindings/power/r8a774a1-sysc.h
+++ b/include/dt-bindings/power/r8a774a1-sysc.h

@@ -18,12 +18,10 @@
 #define R8A774A1_PD_CA53_CPU2		 7
 #define R8A774A1_PD_CA53_CPU3		 8
 #define R8A774A1_PD_CA57_SCU		12
-#define R8A774A1_PD_CR7			13
 #define R8A774A1_PD_A3VC		14
 #define R8A774A1_PD_3DG_A		17
 #define R8A774A1_PD_3DG_B		18
 #define R8A774A1_PD_CA53_SCU		21
-#define R8A774A1_PD_A3IR		24
 #define R8A774A1_PD_A2VC0		25
 #define R8A774A1_PD_A2VC1		26
 

diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h
new file mode 100644
index 0000000..96afda0
--- /dev/null
+++ b/include/dt-bindings/power/r8a774b1-sysc.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774B1_PD_CA57_CPU0		 0
+#define R8A774B1_PD_CA57_CPU1		 1
+#define R8A774B1_PD_A3VP		 9
+#define R8A774B1_PD_CA57_SCU		12
+#define R8A774B1_PD_A3VC		14
+#define R8A774B1_PD_3DG_A		17
+#define R8A774B1_PD_3DG_B		18
+#define R8A774B1_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774B1_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */

diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h
new file mode 100644
index 0000000..7edb816
--- /dev/null
+++ b/include/dt-bindings/power/r8a774e1-sysc.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774E1_PD_CA57_CPU0		 0
+#define R8A774E1_PD_CA57_CPU1		 1
+#define R8A774E1_PD_CA57_CPU2		 2
+#define R8A774E1_PD_CA57_CPU3		 3
+#define R8A774E1_PD_CA53_CPU0		 5
+#define R8A774E1_PD_CA53_CPU1		 6
+#define R8A774E1_PD_CA53_CPU2		 7
+#define R8A774E1_PD_CA53_CPU3		 8
+#define R8A774E1_PD_A3VP		 9
+#define R8A774E1_PD_CA57_SCU		12
+#define R8A774E1_PD_A3VC		14
+#define R8A774E1_PD_3DG_A		17
+#define R8A774E1_PD_3DG_B		18
+#define R8A774E1_PD_3DG_C		19
+#define R8A774E1_PD_3DG_D		20
+#define R8A774E1_PD_CA53_SCU		21
+#define R8A774E1_PD_3DG_E		22
+#define R8A774E1_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774E1_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */

diff --git a/include/dt-bindings/reset/qcom,ipq4019-reset.h b/include/dt-bindings/reset/qcom,ipq4019-reset.h
new file mode 100644
index 0000000..ed047d7
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq4019-reset.h

@@ -0,0 +1,92 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_RESET_IPQ4019_H__
+#define __QCOM_RESET_IPQ4019_H__
+
+#define WIFI0_CPU_INIT_RESET				0
+#define WIFI0_RADIO_SRIF_RESET				1
+#define WIFI0_RADIO_WARM_RESET				2
+#define WIFI0_RADIO_COLD_RESET				3
+#define WIFI0_CORE_WARM_RESET				4
+#define WIFI0_CORE_COLD_RESET				5
+#define WIFI1_CPU_INIT_RESET				6
+#define WIFI1_RADIO_SRIF_RESET				7
+#define WIFI1_RADIO_WARM_RESET				8
+#define WIFI1_RADIO_COLD_RESET				9
+#define WIFI1_CORE_WARM_RESET				10
+#define WIFI1_CORE_COLD_RESET				11
+#define USB3_UNIPHY_PHY_ARES				12
+#define USB3_HSPHY_POR_ARES				13
+#define USB3_HSPHY_S_ARES				14
+#define USB2_HSPHY_POR_ARES				15
+#define USB2_HSPHY_S_ARES				16
+#define PCIE_PHY_AHB_ARES				17
+#define PCIE_AHB_ARES					18
+#define PCIE_PWR_ARES					19
+#define PCIE_PIPE_STICKY_ARES				20
+#define PCIE_AXI_M_STICKY_ARES				21
+#define PCIE_PHY_ARES					22
+#define PCIE_PARF_XPU_ARES				23
+#define PCIE_AXI_S_XPU_ARES				24
+#define PCIE_AXI_M_VMIDMT_ARES				25
+#define PCIE_PIPE_ARES					26
+#define PCIE_AXI_S_ARES					27
+#define PCIE_AXI_M_ARES					28
+#define ESS_RESET					29
+#define GCC_BLSP1_BCR					30
+#define GCC_BLSP1_QUP1_BCR				31
+#define GCC_BLSP1_UART1_BCR				32
+#define GCC_BLSP1_QUP2_BCR				33
+#define GCC_BLSP1_UART2_BCR				34
+#define GCC_BIMC_BCR					35
+#define GCC_TLMM_BCR					36
+#define GCC_IMEM_BCR					37
+#define GCC_ESS_BCR					38
+#define GCC_PRNG_BCR					39
+#define GCC_BOOT_ROM_BCR				40
+#define GCC_CRYPTO_BCR					41
+#define GCC_SDCC1_BCR					42
+#define GCC_SEC_CTRL_BCR				43
+#define GCC_AUDIO_BCR					44
+#define GCC_QPIC_BCR					45
+#define GCC_PCIE_BCR					46
+#define GCC_USB2_BCR					47
+#define GCC_USB2_PHY_BCR				48
+#define GCC_USB3_BCR					49
+#define GCC_USB3_PHY_BCR				50
+#define GCC_SYSTEM_NOC_BCR				51
+#define GCC_PCNOC_BCR					52
+#define GCC_DCD_BCR					53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR			54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR			55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR			56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR			57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR			58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR			59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR			60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR			61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR			62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR			63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR			64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR			65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR			66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR			67
+#define GCC_TCSR_BCR					68
+#define GCC_QDSS_BCR					69
+#define GCC_MPM_BCR					70
+#define GCC_SPDM_BCR					71
+
+#endif

diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index 1c8e49a..b86c8dc 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h

@@ -57,7 +57,7 @@
 		"fi;\0" \
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"devnum=${mmcdev}; " \
-		"setenv devtype mmc; " \
+		"devtype=mmc; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
 			"if run loadimage; then " \

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 152eb07..62d1660 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h

@@ -1029,7 +1029,7 @@
  *     };
  *     uint32_t phandle;
  *
- *     fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle);
+ *     fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false);
  *
  * This results in the following subnode being added to the top-level
  * /reserved-memory node:
@@ -1056,11 +1056,12 @@
  * @param carveout	information about the carveout region
  * @param phandlep	return location for the phandle of the carveout region
  *			can be NULL if no phandle should be added
+ * @param no_map	add "no-map" property if true
  * @return 0 on success or a negative error code on failure
  */
 int fdtdec_add_reserved_memory(void *blob, const char *basename,
 			       const struct fdt_memory *carveout,
-			       uint32_t *phandlep);
+			       uint32_t *phandlep, bool no_map);
 
 /**
  * fdtdec_get_carveout() - reads a carveout from an FDT

diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 41cb737..b6c02cf 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h

@@ -55,6 +55,10 @@
 		int regnum);
 int memac_mdio_reset(struct mii_dev *bus);
 
+struct fsl_pq_mdio_data {
+	u32 mdio_regs_off;
+};
+
 struct fsl_pq_mdio_info {
 	struct tsec_mii_mng __iomem *regs;
 	char *name;

diff --git a/include/fsl_qe.h b/include/fsl_qe.h
index 6e44cbd..1c69413 100644
--- a/include/fsl_qe.h
+++ b/include/fsl_qe.h

@@ -296,4 +296,7 @@
 			 qe_map_t *qe_immrr);
 #endif
 
+#if defined(CONFIG_PINCTRL)
+int par_io_of_config(struct udevice *dev);
+#endif
 #endif /* __QE_H__ */

diff --git a/include/handoff.h b/include/handoff.h
index 75d19b1..070a79c 100644
--- a/include/handoff.h
+++ b/include/handoff.h

@@ -20,12 +20,10 @@
 struct spl_handoff {
 	struct arch_spl_handoff arch;
 	u64 ram_size;
-#ifdef CONFIG_NR_DRAM_BANKS
 	struct {
 		u64 start;
 		u64 size;
 	} ram_bank[CONFIG_NR_DRAM_BANKS];
-#endif
 };
 
 void handoff_save_dram(struct spl_handoff *ho);

diff --git a/include/i2c.h b/include/i2c.h
index 1d792db..880aa80 100644
--- a/include/i2c.h
+++ b/include/i2c.h

@@ -58,6 +58,12 @@
 	I2C_MODE_10_BIT
 };
 
+/** enum i2c_device_t - Types of I2C devices, used for compatible strings */
+enum i2c_device_t {
+	I2C_DEVICE_GENERIC,
+	I2C_DEVICE_HID_OVER_I2C,
+};
+
 struct udevice;
 /**
  * struct dm_i2c_chip - information about an i2c chip
@@ -558,6 +564,23 @@
  */
 struct udevice *i2c_emul_get_device(struct udevice *emul);
 
+/* ACPI operations for generic I2C devices */
+extern struct acpi_ops i2c_acpi_ops;
+
+/**
+ * acpi_i2c_ofdata_to_platdata() - Read properties intended for ACPI
+ *
+ * This reads the generic I2C properties from the device tree, so that these
+ * can be used to create ACPI information for the device.
+ *
+ * See the i2c/generic-acpi.txt binding file for information about the
+ * properties.
+ *
+ * @dev: I2C device to process
+ * @return 0 if OK, -EINVAL if acpi,hid is not present
+ */
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+
 #ifndef CONFIG_DM_I2C
 
 /*

diff --git a/include/linux/compat.h b/include/linux/compat.h
index 363b2b9..d129780 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h

@@ -52,25 +52,6 @@
 #define dev_warn(dev, fmt, args...)		\
 	printf(fmt, ##args)
 
-#define netdev_emerg(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_alert(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_crit(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_err(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_warn(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_notice(dev, fmt, args...)	\
-	printf(fmt, ##args)
-#define netdev_info(dev, fmt, args...)		\
-	printf(fmt, ##args)
-#define netdev_dbg(dev, fmt, args...)		\
-	debug(fmt, ##args)
-#define netdev_vdbg(dev, fmt, args...)		\
-	debug(fmt, ##args)
-
 #define GFP_ATOMIC ((gfp_t) 0)
 #define GFP_KERNEL ((gfp_t) 0)
 #define GFP_NOFS ((gfp_t) 0)

diff --git a/include/mmc.h b/include/mmc.h
index 8256219..75bcaaf 100644
--- a/include/mmc.h
+++ b/include/mmc.h

@@ -888,6 +888,8 @@
 #define mmc_host_is_spi(mmc)	0
 #endif
 
+#define mmc_dev(x)	((x)->dev)
+
 void board_mmc_power_init(void);
 int board_mmc_init(struct bd_info *bis);
 int cpu_mmc_init(struct bd_info *bis);

diff --git a/include/net.h b/include/net.h
index 1bf9867..2191071 100644
--- a/include/net.h
+++ b/include/net.h

@@ -551,7 +551,7 @@
 
 enum proto_t {
 	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-	TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL
+	TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP
 };
 
 extern char	net_boot_file_name[1024];/* Boot File name */

diff --git a/net/sntp.h b/include/net/sntp.h
similarity index 93%
rename from net/sntp.h
rename to include/net/sntp.h
index d3cbfbc..30b44d1 100644
--- a/net/sntp.h
+++ b/include/net/sntp.h

@@ -52,6 +52,7 @@
 	unsigned long long transmit_timestamp;
 } __attribute__((packed));
 
-void sntp_start(void);	/* Begin SNTP */
+int sntp_prereq(void *data);
+int sntp_start(void *data);	/* Begin SNTP */
 
 #endif /* __SNTP_H__ */

diff --git a/include/net/udp.h b/include/net/udp.h
new file mode 100644
index 0000000..2ae56e8
--- /dev/null
+++ b/include/net/udp.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#ifndef __UDP
+#define __UDP
+
+/**
+ * struct udp_ops - function to handle udp packet
+ *
+ * This structure provides the function to handle udp packet in
+ * the network loop.
+ *
+ * @prereq: callback called to check the requirement
+ * @start: callback called to start the protocol/feature
+ * @data: pointer to store private data (used by prereq and start)
+ */
+struct udp_ops {
+	int (*prereq)(void *data);
+	int (*start)(void *data);
+	void *data;
+};
+
+int udp_prereq(void);
+
+int udp_start(void);
+
+/**
+ * udp_loop() - network loop for udp protocol
+ *
+ * Launch a network loop for udp protocol and use callbacks
+ * provided in parameter @ops to initialize the loop, and then
+ * to handle udp packet.
+ *
+ * @ops: udp callback
+ * @return: 0 if success, otherwise < 0 on error
+ */
+int udp_loop(struct udp_ops *ops);
+
+#endif

diff --git a/include/omap3_spi.h b/include/omap3_spi.h
new file mode 100644
index 0000000..cae3770
--- /dev/null
+++ b/include/omap3_spi.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __OMAP3_SPI_H_
+#define __OMAP3_SPI_H_
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
+
+#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
+#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
+#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
+#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
+#define MCSPI_PINDIR_D0_IN_D1_OUT	0
+#define MCSPI_PINDIR_D0_OUT_D1_IN	1
+
+#define OMAP3_MCSPI_MAX_FREQ		48000000
+#define SPI_WAIT_TIMEOUT		10
+
+#define OMAP4_MCSPI_REG_OFFSET	0x100
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
+	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
+	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
+	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
+	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned int irqstatus;		/* 0x18 */
+	unsigned int irqenable;		/* 0x1C */
+	unsigned int wakeupenable;	/* 0x20 */
+	unsigned int syst;		/* 0x24 */
+	unsigned int modulctrl;		/* 0x28 */
+	struct mcspi_channel channel[4];
+	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+	/* channel1: 0x40 - 0x50, bus 0 & 1 */
+	/* channel2: 0x54 - 0x64, bus 0 & 1 */
+	/* channel3: 0x68 - 0x78, bus 0 */
+};
+
+struct omap3_spi_plat {
+	struct mcspi *regs;
+	unsigned int pin_dir:1;
+};
+#endif

diff --git a/include/p2sb.h b/include/p2sb.h
index 93e1155..a25170e 100644
--- a/include/p2sb.h
+++ b/include/p2sb.h

@@ -10,6 +10,12 @@
 /* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */
 #define PCR_PORTID_SHIFT	16
 
+#if !defined(__ACPI__)
+
+/* These registers contain IOAPIC and HPET devfn */
+#define PCH_P2SB_IBDF		0x6c
+#define PCH_P2SB_HBDF		0x70
+
 /**
  * struct p2sb_child_platdata - Information about each child of a p2sb device
  *
@@ -164,4 +170,6 @@
  */
 void *pcr_reg_address(struct udevice *dev, uint offset);
 
+#endif /* !__ACPI__ */
+
 #endif

diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h
index 5fbf745..222288b 100644
--- a/include/power/acpi_pmc.h
+++ b/include/power/acpi_pmc.h

@@ -6,7 +6,7 @@
 #ifndef __ACPI_PMC_H
 #define __ACPI_PMC_H
 
-#ifndef __ACPI__
+#ifndef __ASSEMBLY__
 
 enum {
 	GPE0_REG_MAX	= 4,
@@ -194,6 +194,6 @@
  */
 int pmc_gpe_init(struct udevice *dev);
 
-#endif /* !__ACPI__ */
+#endif /* !__ASSEMBLY__ */
 
 #endif

diff --git a/include/regmap.h b/include/regmap.h
index 30183c5..c6258fa 100644
--- a/include/regmap.h
+++ b/include/regmap.h

@@ -75,14 +75,41 @@
 	ulong size;
 };
 
+struct regmap_bus;
+
+/**
+ * struct regmap_config - Configure the behaviour of a regmap
+ *
+ * @width:		Width of the read/write operations. Defaults to
+ *			REGMAP_SIZE_32 if set to 0.
+ * @reg_offset_shift	Left shift the register offset by this value before
+ *			performing read or write.
+ * @r_start:		If specified, the regmap is created with one range
+ *			which starts at this address, instead of finding the
+ *			start from device tree.
+ * @r_size:		Same as above for the range size
+ */
+struct regmap_config {
+	enum regmap_size_t width;
+	u32 reg_offset_shift;
+	ulong r_start;
+	ulong r_size;
+};
+
 /**
  * struct regmap - a way of accessing hardware/bus registers
  *
+ * @width:		Width of the read/write operations. Defaults to
+ *			REGMAP_SIZE_32 if set to 0.
+ * @reg_offset_shift	Left shift the register offset by this value before
+ *			performing read or write.
  * @range_count:	Number of ranges available within the map
  * @ranges:		Array of ranges
  */
 struct regmap {
 	enum regmap_endianness_t endianness;
+	enum regmap_size_t width;
+	u32 reg_offset_shift;
 	int range_count;
 	struct regmap_range ranges[0];
 };
@@ -93,32 +120,24 @@
  */
 
 /**
- * regmap_write() - Write a 32-bit value to a regmap
+ * regmap_write() - Write a value to a regmap
  *
  * @map:	Regmap to write to
  * @offset:	Offset in the regmap to write to
  * @val:	Data to write to the regmap at the specified offset
  *
- * Note that this function will only write values of 32 bit width to the
- * regmap; if the size of data to be read is different, the regmap_raw_write
- * function can be used.
- *
  * Return: 0 if OK, -ve on error
  */
 int regmap_write(struct regmap *map, uint offset, uint val);
 
 /**
- * regmap_read() - Read a 32-bit value from a regmap
+ * regmap_read() - Read a value from a regmap
  *
  * @map:	Regmap to read from
  * @offset:	Offset in the regmap to read from
  * @valp:	Pointer to the buffer to receive the data read from the regmap
  *		at the specified offset
  *
- * Note that this function will only read values of 32 bit width from the
- * regmap; if the size of data to be read is different, the regmap_raw_read
- * function can be used.
- *
  * Return: 0 if OK, -ve on error
  */
 int regmap_read(struct regmap *map, uint offset, uint *valp);
@@ -132,8 +151,9 @@
  * @val_len:	Length of the data to be written to the regmap
  *
  * Note that this function will, as opposed to regmap_write, write data of
- * arbitrary length to the regmap, and not just 32-bit values, and is thus a
- * generalized version of regmap_write.
+ * arbitrary length to the regmap, and not just the size configured in the
+ * regmap (defaults to 32-bit) and is thus a generalized version of
+ * regmap_write.
  *
  * Return: 0 if OK, -ve on error
  */
@@ -150,8 +170,9 @@
  * @val_len:	Length of the data to be read from the regmap
  *
  * Note that this function will, as opposed to regmap_read, read data of
- * arbitrary length from the regmap, and not just 32-bit values, and is thus a
- * generalized version of regmap_read.
+ * arbitrary length from the regmap, and not just the size configured in the
+ * regmap (defaults to 32-bit) and is thus a generalized version of
+ * regmap_read.
  *
  * Return: 0 if OK, -ve on error
  */
@@ -292,6 +313,43 @@
 				      timeout_ms, 0) \
 
 /**
+ * regmap_field_read_poll_timeout - Poll until a condition is met or a timeout
+ *				    occurs
+ *
+ * @field:	Regmap field to read from
+ * @val:	Unsigned integer variable to read the value into
+ * @cond:	Break condition (usually involving @val)
+ * @sleep_us:	Maximum time to sleep between reads in us (0 tight-loops).
+ * @timeout_ms:	Timeout in ms, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_field_read
+ * error return value in case of a error read. In the two former cases,
+ * the last read value at @addr is stored in @val.
+ *
+ * This is modelled after the regmap_read_poll_timeout macros in linux but
+ * with millisecond timeout.
+ */
+#define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_ms) \
+({ \
+	unsigned long __start = get_timer(0); \
+	int __ret; \
+	for (;;) { \
+		__ret = regmap_field_read((field), &(val)); \
+		if (__ret) \
+			break; \
+		if (cond) \
+			break; \
+		if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \
+			__ret = regmap_field_read((field), &(val)); \
+			break; \
+		} \
+		if ((sleep_us)) \
+			udelay((sleep_us)); \
+	} \
+	__ret ?: ((cond) ? 0 : -ETIMEDOUT); \
+})
+
+/**
  * regmap_update_bits() - Perform a read/modify/write using a mask
  *
  * @map:	The map returned by regmap_init_mem*()
@@ -336,6 +394,40 @@
 int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
 
 /**
+ * regmap_init_mem_range() - Set up a new memory region for ofnode with the
+ *			     specified range.
+ *
+ * @node:	The ofnode for the map.
+ * @r_start:	Start of the range.
+ * @r_size:	Size of the range.
+ * @mapp:	Returns allocated map.
+ *
+ * Return: 0 in success, -errno otherwise
+ *
+ * This creates a regmap with one range where instead of extracting the range
+ * from 'node', it is created based on the parameters specified. This is
+ * useful when a driver needs to calculate the base of the regmap at runtime,
+ * and can't specify it in device tree.
+ */
+int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size,
+			  struct regmap **mapp);
+
+/**
+ * devm_regmap_init() - Initialise register map (device managed)
+ *
+ * @dev: Device that will be interacted with
+ * @bus: Bus-specific callbacks to use with device (IGNORED)
+ * @bus_context: Data passed to bus-specific callbacks (IGNORED)
+ * @config: Configuration for register map
+ *
+ * @Return a valid pointer to a struct regmap or a ERR_PTR() on error.
+ * The structure is automatically freed when the device is unbound
+ */
+struct regmap *devm_regmap_init(struct udevice *dev,
+				const struct regmap_bus *bus,
+				void *bus_context,
+				const struct regmap_config *config);
+/**
  * regmap_get_range() - Obtain the base memory address of a regmap range
  *
  * @map:	Regmap to query
@@ -352,4 +444,89 @@
  */
 int regmap_uninit(struct regmap *map);
 
+/**
+ * struct reg_field - Description of an register field
+ *
+ * @reg: Offset of the register within the regmap bank
+ * @lsb: lsb of the register field.
+ * @msb: msb of the register field.
+ */
+struct reg_field {
+	unsigned int reg;
+	unsigned int lsb;
+	unsigned int msb;
+};
+
+struct regmap_field;
+
+/**
+ * REG_FIELD() - A convenient way to initialize a 'struct reg_feild'.
+ *
+ * @_reg: Offset of the register within the regmap bank
+ * @_lsb: lsb of the register field.
+ * @_msb: msb of the register field.
+ *
+ * Register fields are often described in terms of 3 things: the register it
+ * belongs to, its LSB, and its MSB. This macro can be used by drivers to
+ * clearly and easily initialize a 'struct regmap_field'.
+ *
+ * For example, say a device has a register at offset DEV_REG1 (0x100) and a
+ * field of DEV_REG1 is on bits [7:3]. So a driver can initialize a regmap
+ * field for this by doing:
+ *     struct reg_field field = REG_FIELD(DEV_REG1, 3, 7);
+ */
+#define REG_FIELD(_reg, _lsb, _msb) {		\
+				.reg = _reg,	\
+				.lsb = _lsb,	\
+				.msb = _msb,	\
+				}
+
+/**
+ * devm_regmap_field_alloc() - Allocate and initialise a register field.
+ *
+ * @dev: Device that will be interacted with
+ * @regmap: regmap bank in which this register field is located.
+ * @reg_field: Register field with in the bank.
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer
+ * to a struct regmap_field. The regmap_field will be automatically freed
+ * by the device management code.
+ */
+struct regmap_field *devm_regmap_field_alloc(struct udevice *dev,
+					     struct regmap *regmap,
+					     struct reg_field reg_field);
+/**
+ * devm_regmap_field_free() - Free a register field allocated using
+ *                            devm_regmap_field_alloc.
+ *
+ * @dev: Device that will be interacted with
+ * @field: regmap field which should be freed.
+ *
+ * Free register field allocated using devm_regmap_field_alloc(). Usually
+ * drivers need not call this function, as the memory allocated via devm
+ * will be freed as per device-driver life-cyle.
+ */
+void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field);
+
+/**
+ * regmap_field_write() - Write a value to a regmap field
+ *
+ * @field:	Regmap field to write to
+ * @val:	Data to write to the regmap at the specified offset
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_field_write(struct regmap_field *field, unsigned int val);
+
+/**
+ * regmap_read() - Read a 32-bit value from a regmap
+ *
+ * @field:	Regmap field to write to
+ * @valp:	Pointer to the buffer to receive the data read from the regmap
+ *		field
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_field_read(struct regmap_field *field, unsigned int *val);
+
 #endif

diff --git a/include/remoteproc.h b/include/remoteproc.h
index a903acb..74d0172 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h

@@ -227,19 +227,6 @@
 int rproc_elf64_sanity_check(ulong addr, ulong size);
 
 /**
- * rproc_elf_sanity_check() - Verify if an image is a valid ELF one
- *
- * Check if a valid ELF image exists at the given memory location. Auto
- * detects ELF32/ELF64 and verifies basic ELF64/ELF32 format requirements
- * like magic number and sections size.
- *
- * @addr:	address of the image to verify
- * @size:	size of the image
- * @return 0 if the image looks good, else appropriate error value.
- */
-int rproc_elf_sanity_check(ulong addr, ulong size);
-
-/**
  * rproc_elf32_load_image() - load an ELF32 image
  * @dev:	device loading the ELF32 image
  * @addr:	valid ELF32 image address

diff --git a/include/reset.h b/include/reset.h
index 4fac4e6..cde2c4b 100644
--- a/include/reset.h
+++ b/include/reset.h

@@ -7,7 +7,7 @@
 #define _RESET_H
 
 #include <dm/ofnode.h>
-#include <linux/errno.h>
+#include <linux/err.h>
 
 /**
  * A reset is a hardware signal indicating that a HW module (or IP block, or
@@ -84,6 +84,98 @@
 };
 
 #if CONFIG_IS_ENABLED(DM_RESET)
+
+/**
+ * devm_reset_control_get - resource managed reset_get_by_name()
+ * @dev: device to be reset by the controller
+ * @id: reset line name
+ *
+ * Managed reset_get_by_name(). For reset controllers returned
+ * from this function, reset_free() is called automatically on driver
+ * detach.
+ *
+ * Returns a struct reset_ctl or IS_ERR() condition containing errno.
+ */
+struct reset_ctl *devm_reset_control_get(struct udevice *dev, const char *id);
+
+/**
+ * devm_reset_control_get_optional - resource managed reset_get_by_name() that
+ *                                   can fail
+ * @dev:	The client device.
+ * @id:		reset line name
+ *
+ * Managed reset_get_by_name(). For reset controllers returned
+ * from this function, reset_free() is called automatically on driver
+ * detach.
+ *
+ * Returns a struct reset_ctl or a dummy reset controller if it failed.
+ */
+struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev,
+						  const char *id);
+
+/**
+ * devm_reset_control_get - resource managed reset_get_by_index()
+ * @dev:	The client device.
+ * @index:	The index of the reset signal to request, within the client's
+ *		list of reset signals.
+ *
+ * Managed reset_get_by_index(). For reset controllers returned
+ * from this function, reset_free() is called automatically on driver
+ * detach.
+ *
+ * Returns a struct reset_ctl or IS_ERR() condition containing errno.
+ */
+struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev,
+						  int index);
+
+/**
+ * devm_reset_bulk_get - resource managed reset_get_bulk()
+ * @dev: device to be reset by the controller
+ *
+ * Managed reset_get_bulk(). For reset controllers returned
+ * from this function, reset_free() is called automatically on driver
+ * detach.
+ *
+ * Returns a struct reset_ctl or IS_ERR() condition containing errno.
+ */
+struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev);
+
+/**
+ * devm_reset_bulk_get_optional - resource managed reset_get_bulk() that
+ *                                can fail
+ * @dev:	The client device.
+ *
+ * Managed reset_get_bulk(). For reset controllers returned
+ * from this function, reset_free() is called automatically on driver
+ * detach.
+ *
+ * Returns a struct reset_ctl or NULL if it failed.
+ */
+struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev);
+
+/**
+ * devm_reset_bulk_get_by_node - resource managed reset_get_bulk()
+ * @dev: device to be reset by the controller
+ * @node: ofnode where the "resets" property is. Usually a sub-node of
+ *        the dev's node.
+ *
+ * see devm_reset_bulk_get()
+ */
+struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev,
+						   ofnode node);
+
+/**
+ * devm_reset_bulk_get_optional_by_node - resource managed reset_get_bulk()
+ *                                        that can fail
+ * @dev: device to be reset by the controller
+ * @node: ofnode where the "resets" property is. Usually a sub-node of
+ *        the dev's node.
+ *
+ * see devm_reset_bulk_get_optional()
+ */
+struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev,
+							    ofnode node);
+
 /**
  * reset_get_by_index - Get/request a reset signal by integer index.
  *
@@ -265,7 +357,48 @@
 {
 	return reset_release_all(bulk->resets, bulk->count);
 }
+
 #else
+static inline struct reset_ctl *devm_reset_control_get(struct udevice *dev,
+						       const char *id)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
+static inline struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev,
+								const char *id)
+{
+	return NULL;
+}
+
+static inline struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev,
+								int index)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
+static inline struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
+static inline struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev)
+{
+	return NULL;
+}
+
+static inline struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev,
+								 ofnode node)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
+static inline struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev,
+									  ofnode node)
+{
+	return NULL;
+}
+
 static inline int reset_get_by_index(struct udevice *dev, int index,
 				     struct reset_ctl *reset_ctl)
 {

diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h
new file mode 100644
index 0000000..a501d1b
--- /dev/null
+++ b/include/scmi_agent-uclass.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020 Linaro Limited.
+ */
+#ifndef _SCMI_AGENT_UCLASS_H
+#define _SCMI_AGENT_UCLASS_H
+
+struct udevice;
+struct scmi_msg;
+
+/**
+ * struct scmi_transport_ops - The functions that a SCMI transport layer must implement.
+ */
+struct scmi_agent_ops {
+	/*
+	 * process_msg - Request transport to get the SCMI message processed
+	 *
+	 * @agent:		Agent using the transport
+	 * @msg:		SCMI message to be transmitted
+	 */
+	int (*process_msg)(struct udevice *dev, struct scmi_msg *msg);
+};
+
+#endif /* _SCMI_TRANSPORT_UCLASS_H */

diff --git a/include/scmi_agent.h b/include/scmi_agent.h
new file mode 100644
index 0000000..f1be9ff
--- /dev/null
+++ b/include/scmi_agent.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2019-2020, Linaro Limited
+ *
+ * An SCMI agent device represent on communication path from a
+ * device driver to the remote SCMI server which driver sends
+ * messages to and receives response messages from.
+ */
+#ifndef SCMI_AGENT_H
+#define SCMI_AGENT_H
+
+#include <asm/types.h>
+
+struct udevice;
+
+/*
+ * struct scmi_msg - Context of a SCMI message sent and the response received
+ *
+ * @protocol_id:	SCMI protocol ID
+ * @message_id:		SCMI message ID for a defined protocol ID
+ * @in_msg:		Pointer to the message payload sent by the driver
+ * @in_msg_sz:		Byte size of the message payload sent
+ * @out_msg:		Pointer to buffer to store response message payload
+ * @out_msg_sz:		Byte size of the response buffer and response payload
+ */
+struct scmi_msg {
+	unsigned int protocol_id;
+	unsigned int message_id;
+	u8 *in_msg;
+	size_t in_msg_sz;
+	u8 *out_msg;
+	size_t out_msg_sz;
+};
+
+/* Helper macro to match a message on input/output array references */
+#define SCMI_MSG_IN(_protocol, _message, _in_array, _out_array) \
+	(struct scmi_msg){			\
+		.protocol_id = (_protocol),	\
+		.message_id = (_message),	\
+		.in_msg = (uint8_t *)&(_in_array),	\
+		.in_msg_sz = sizeof(_in_array),	\
+		.out_msg = (uint8_t *)&(_out_array),	\
+		.out_msg_sz = sizeof(_out_array),	\
+	}
+
+/**
+ * scmi_send_and_process_msg() - send and process a SCMI message
+ *
+ * Send a message to a SCMI server through a target SCMI agent device.
+ * Caller sets scmi_msg::out_msg_sz to the output message buffer size.
+ * On return, scmi_msg::out_msg_sz stores the response payload size.
+ *
+ * @dev:	SCMI agent device
+ * @msg:	Message structure reference
+ * @return 0 on success and a negative errno on failure
+ */
+int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg);
+
+/**
+ * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code
+ *
+ * @scmi_errno:	SCMI error code value
+ * @return 0 for successful status and a negative errno otherwise
+ */
+int scmi_to_linux_errno(s32 scmi_errno);
+
+#endif /* SCMI_H */

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
new file mode 100644
index 0000000..ccab97c
--- /dev/null
+++ b/include/scmi_protocols.h

@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2019-2020, Linaro Limited
+ */
+#ifndef _SCMI_PROTOCOLS_H
+#define _SCMI_PROTOCOLS_H
+
+#include <linux/bitops.h>
+#include <asm/types.h>
+
+/*
+ * Subset the SCMI protocols definition
+ * based on SCMI specification v2.0 (DEN0056B)
+ * https://developer.arm.com/docs/den0056/b
+ */
+
+enum scmi_std_protocol {
+	SCMI_PROTOCOL_ID_BASE = 0x10,
+	SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
+	SCMI_PROTOCOL_ID_SYSTEM = 0x12,
+	SCMI_PROTOCOL_ID_PERF = 0x13,
+	SCMI_PROTOCOL_ID_CLOCK = 0x14,
+	SCMI_PROTOCOL_ID_SENSOR = 0x15,
+	SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
+};
+
+enum scmi_status_code {
+	SCMI_SUCCESS =  0,
+	SCMI_NOT_SUPPORTED = -1,
+	SCMI_INVALID_PARAMETERS = -2,
+	SCMI_DENIED = -3,
+	SCMI_NOT_FOUND = -4,
+	SCMI_OUT_OF_RANGE = -5,
+	SCMI_BUSY = -6,
+	SCMI_COMMS_ERROR = -7,
+	SCMI_GENERIC_ERROR = -8,
+	SCMI_HARDWARE_ERROR = -9,
+	SCMI_PROTOCOL_ERROR = -10,
+};
+
+/*
+ * SCMI Clock Protocol
+ */
+
+enum scmi_clock_message_id {
+	SCMI_CLOCK_RATE_SET = 0x5,
+	SCMI_CLOCK_RATE_GET = 0x6,
+	SCMI_CLOCK_CONFIG_SET = 0x7,
+};
+
+#define SCMI_CLK_RATE_ASYNC_NOTIFY	BIT(0)
+#define SCMI_CLK_RATE_ASYNC_NORESP	(BIT(0) | BIT(1))
+#define SCMI_CLK_RATE_ROUND_DOWN	0
+#define SCMI_CLK_RATE_ROUND_UP		BIT(2)
+#define SCMI_CLK_RATE_ROUND_CLOSEST	BIT(3)
+
+/**
+ * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command
+ * @clock_id:	SCMI clock ID
+ * @attributes:	Attributes of the targets clock state
+ */
+struct scmi_clk_state_in {
+	u32 clock_id;
+	u32 attributes;
+};
+
+/**
+ * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command
+ * @status:	SCMI command status
+ */
+struct scmi_clk_state_out {
+	s32 status;
+};
+
+/**
+ * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command
+ * @clock_id:	SCMI clock ID
+ * @attributes:	Attributes of the targets clock state
+ */
+struct scmi_clk_rate_get_in {
+	u32 clock_id;
+};
+
+/**
+ * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command
+ * @status:	SCMI command status
+ * @rate_lsb:	32bit LSB of the clock rate in Hertz
+ * @rate_msb:	32bit MSB of the clock rate in Hertz
+ */
+struct scmi_clk_rate_get_out {
+	s32 status;
+	u32 rate_lsb;
+	u32 rate_msb;
+};
+
+/**
+ * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command
+ * @clock_id:	SCMI clock ID
+ * @flags:	Flags for the clock rate set request
+ * @rate_lsb:	32bit LSB of the clock rate in Hertz
+ * @rate_msb:	32bit MSB of the clock rate in Hertz
+ */
+struct scmi_clk_rate_set_in {
+	u32 clock_id;
+	u32 flags;
+	u32 rate_lsb;
+	u32 rate_msb;
+};
+
+/**
+ * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command
+ * @status:	SCMI command status
+ */
+struct scmi_clk_rate_set_out {
+	s32 status;
+};
+
+/*
+ * SCMI Reset Domain Protocol
+ */
+
+enum scmi_reset_domain_message_id {
+	SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3,
+	SCMI_RESET_DOMAIN_RESET = 0x4,
+};
+
+#define SCMI_RD_NAME_LEN		16
+
+#define SCMI_RD_ATTRIBUTES_FLAG_ASYNC	BIT(31)
+#define SCMI_RD_ATTRIBUTES_FLAG_NOTIF	BIT(30)
+
+#define SCMI_RD_RESET_FLAG_ASYNC	BIT(2)
+#define SCMI_RD_RESET_FLAG_ASSERT	BIT(1)
+#define SCMI_RD_RESET_FLAG_CYCLE	BIT(0)
+
+/**
+ * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message
+ * @domain_id:	SCMI reset domain ID
+ */
+struct scmi_rd_attr_in {
+	u32 domain_id;
+};
+
+/**
+ * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response
+ * @status:	SCMI command status
+ * @attributes:	Retrieved attributes of the reset domain
+ * @latency:	Reset cycle max lantency
+ * @name:	Reset domain name
+ */
+struct scmi_rd_attr_out {
+	s32 status;
+	u32 attributes;
+	u32 latency;
+	char name[SCMI_RD_NAME_LEN];
+};
+
+/**
+ * struct scmi_rd_reset_in - Message payload for RESET command
+ * @domain_id:		SCMI reset domain ID
+ * @flags:		Flags for the reset request
+ * @reset_state:	Reset target state
+ */
+struct scmi_rd_reset_in {
+	u32 domain_id;
+	u32 flags;
+	u32 reset_state;
+};
+
+/**
+ * struct scmi_rd_reset_out - Response payload for RESET command
+ * @status:	SCMI command status
+ */
+struct scmi_rd_reset_out {
+	s32 status;
+};
+
+#endif /* _SCMI_PROTOCOLS_H */

diff --git a/include/timer.h b/include/timer.h
index a49b500..8b9fa51 100644
--- a/include/timer.h
+++ b/include/timer.h

@@ -15,6 +15,21 @@
  */
 int dm_timer_init(void);
 
+/**
+ * timer_timebase_fallback() - Helper for timers using timebase fallback
+ * @dev: A timer partially-probed timer device
+ *
+ * This is a helper function designed for timers which need to fall back on the
+ * cpu's timebase. This function is designed to be called during the driver's
+ * probe(). If there is a clocks or clock-frequency property in the timer's
+ * binding, then it will be used. Otherwise, the timebase of the current cpu
+ * will be used. This is initialized by the cpu driver, and usually gotten from
+ * ``/cpus/timebase-frequency`` or ``/cpus/cpu@X/timebase-frequency``.
+ *
+ * Return: 0 if OK, or negative error code on failure
+ */
+int timer_timebase_fallback(struct udevice *dev);
+
 /*
  * timer_conv_64 - convert 32-bit counter value to 64-bit
  *

diff --git a/include/tsec.h b/include/tsec.h
index 43255e5..5433cfd 100644
--- a/include/tsec.h
+++ b/include/tsec.h

@@ -394,6 +394,10 @@
 
 #define TX_BUF_CNT	2
 
+struct tsec_data {
+	u32 mdio_regs_off;
+};
+
 struct tsec_private {
 	struct txbd8 __iomem txbd[TX_BUF_CNT];
 	struct rxbd8 __iomem rxbd[PKTBUFSRX];

diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 7d34103..e1d3823 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h

@@ -101,8 +101,6 @@
 /* bits 8:18, Max Interrupters */
 #define HCS_MAX_INTRS(p)	(((p) >> 8) & 0x7ff)
 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
-#define HCS_MAX_PORTS_SHIFT	24
-#define HCS_MAX_PORTS_MASK	(0xff << HCS_MAX_PORTS_SHIFT)
 #define HCS_MAX_PORTS(p)	(((p) >> 24) & 0xff)
 
 /* HCSPARAMS2 - hcs_params2 - bitmasks */
@@ -634,11 +632,8 @@
  */
 #define	FORCE_EVENT		(0x1)
 #define ERROR_COUNT(p)		(((p) & 0x3) << 1)
-#define ERROR_COUNT_SHIFT	(1)
-#define ERROR_COUNT_MASK	(0x3)
 #define CTX_TO_EP_TYPE(p)	(((p) >> 3) & 0x7)
 #define EP_TYPE(p)		((p) << 3)
-#define EP_TYPE_SHIFT		(3)
 #define ISOC_OUT_EP		1
 #define BULK_OUT_EP		2
 #define INT_OUT_EP		3
@@ -649,13 +644,10 @@
 /* bit 6 reserved */
 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 #define MAX_BURST(p)		(((p)&0xff) << 8)
-#define MAX_BURST_MASK		(0xff)
-#define MAX_BURST_SHIFT		(8)
 #define CTX_TO_MAX_BURST(p)	(((p) >> 8) & 0xff)
 #define MAX_PACKET(p)		(((p)&0xffff) << 16)
 #define MAX_PACKET_MASK		(0xffff)
 #define MAX_PACKET_DECODED(p)	(((p) >> 16) & 0xffff)
-#define MAX_PACKET_SHIFT	(16)
 
 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
  * USB2.0 spec 9.6.6.
@@ -849,10 +841,9 @@
 /* Normal TRB fields */
 /* transfer_len bitmasks - bits 0:16 */
 #define	TRB_LEN(p)			((p) & 0x1ffff)
-#define	TRB_LEN_MASK			(0x1ffff)
+/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
+#define TRB_TD_SIZE(p)          (min((p), (u32)31) << 17)
 /* Interrupter Target - which MSI-X vector to target the completion event at */
-#define	TRB_INTR_TARGET_SHIFT		(22)
-#define	TRB_INTR_TARGET_MASK		(0x3ff)
 #define TRB_INTR_TARGET(p)		(((p) & 0x3ff) << 22)
 #define GET_INTR_TARGET(p)		(((p) >> 22) & 0x3ff)
 #define TRB_TBC(p)			(((p) & 0x3) << 7)
@@ -882,7 +873,6 @@
 /* Control transfer TRB specific fields */
 #define TRB_DIR_IN		(1<<16)
 #define	TRB_TX_TYPE(p)		((p) << 16)
-#define	TRB_TX_TYPE_SHIFT	(16)
 #define	TRB_DATA_OUT		2
 #define	TRB_DATA_IN		3
 
@@ -903,7 +893,6 @@
 /* TRB bit mask */
 #define	TRB_TYPE_BITMASK	(0xfc00)
 #define TRB_TYPE(p)		((p) << 10)
-#define TRB_TYPE_SHIFT		(10)
 #define TRB_FIELD_TO_TYPE(p)	(((p) & TRB_TYPE_BITMASK) >> 10)
 
 /* TRB type IDs */
@@ -1227,6 +1216,9 @@
 	struct xhci_scratchpad *scratchpad;
 	struct xhci_virt_device *devs[MAX_HC_SLOTS];
 	int rootdev;
+	u16 hci_version;
+	u32 quirks;
+#define XHCI_MTK_HOST		BIT(0)
 };
 
 unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);

diff --git a/include/video.h b/include/video.h
index 1a0ffd8..9d09d24 100644
--- a/include/video.h
+++ b/include/video.h

@@ -13,8 +13,6 @@
 #ifndef _VIDEO_H_
 #define _VIDEO_H_
 
-#ifdef CONFIG_DM_VIDEO
-
 #include <stdio_dev.h>
 
 struct udevice;
@@ -140,6 +138,7 @@
  */
 int video_reserve(ulong *addrp);
 
+#ifdef CONFIG_DM_VIDEO
 /**
  * video_clear() - Clear a device's frame buffer to background color.
  *
@@ -147,6 +146,7 @@
  * @return 0
  */
 int video_clear(struct udevice *dev);
+#endif /* CONFIG_DM_VIDEO */
 
 /**
  * video_sync() - Sync a device's frame buffer with its hardware
@@ -243,8 +243,6 @@
 }
 #endif
 
-#endif /* CONFIG_DM_VIDEO */
-
 #ifndef CONFIG_DM_VIDEO
 
 /* Video functions */

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index a0a52ec..35cfe17 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h

@@ -10,9 +10,6 @@
 #include <xilinx.h>
 #include <linux/bitops.h>
 
-#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
-#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
-#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS		0xC2000017
 #define ZYNQMP_FPGA_OP_INIT			(1 << 0)
 #define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
 #define ZYNQMP_FPGA_OP_DONE			(1 << 2)

diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
index 3c75b6d..95dfac5 100644
--- a/lib/acpi/acpi_device.c
+++ b/lib/acpi/acpi_device.c

@@ -487,7 +487,50 @@
 	return 0;
 }
 
-/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+				  int hid_desc_reg_offset)
+{
+	int ret;
+
+	acpigen_write_dsm_start(ctx);
+	ret = acpigen_write_dsm_uuid_start(ctx, ACPI_DSM_I2C_HID_UUID);
+	if (ret)
+		return log_ret(ret);
+
+	acpigen_write_dsm_uuid_start_cond(ctx, 0);
+	/* ToInteger (Arg1, Local2) */
+	acpigen_write_to_integer(ctx, ARG1_OP, LOCAL2_OP);
+	/* If (LEqual (Local2, 0x0)) */
+	acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x0);
+	/*   Return (Buffer (One) { 0x1f }) */
+	acpigen_write_return_singleton_buffer(ctx, 0x1f);
+	acpigen_pop_len(ctx);	/* Pop : If */
+	/* Else */
+	acpigen_write_else(ctx);
+	/*   If (LEqual (Local2, 0x1)) */
+	acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x1);
+	/*     Return (Buffer (One) { 0x3f }) */
+	acpigen_write_return_singleton_buffer(ctx, 0x3f);
+	acpigen_pop_len(ctx);	/* Pop : If */
+	/*   Else */
+	acpigen_write_else(ctx);
+	/*     Return (Buffer (One) { 0x0 }) */
+	acpigen_write_return_singleton_buffer(ctx, 0x0);
+	acpigen_pop_len(ctx);	/* Pop : Else */
+	acpigen_pop_len(ctx);	/* Pop : Else */
+	acpigen_write_dsm_uuid_end_cond(ctx);
+
+	acpigen_write_dsm_uuid_start_cond(ctx, 1);
+	acpigen_write_return_byte(ctx, hid_desc_reg_offset);
+	acpigen_write_dsm_uuid_end_cond(ctx);
+
+	acpigen_write_dsm_uuid_end(ctx);
+	acpigen_write_dsm_end(ctx);
+
+	return 0;
+}
+
+/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBusV2() */
 static void acpi_device_write_i2c(struct acpi_ctx *ctx,
 				  const struct acpi_i2c *i2c)
 {

diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c
index 579cab4..7e3e325 100644
--- a/lib/acpi/acpi_dp.c
+++ b/lib/acpi/acpi_dp.c

@@ -324,7 +324,7 @@
 
 struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
 				 const char *ref, int index, int pin,
-				 enum acpi_irq_polarity polarity)
+				 enum acpi_gpio_polarity polarity)
 {
 	struct acpi_dp *gpio;
 
@@ -336,7 +336,7 @@
 	if (!acpi_dp_add_reference(gpio, NULL, ref) ||
 	    !acpi_dp_add_integer(gpio, NULL, index) ||
 	    !acpi_dp_add_integer(gpio, NULL, pin) ||
-	    !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_IRQ_ACTIVE_LOW))
+	    !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_GPIO_ACTIVE_LOW))
 		return NULL;
 
 	if (!acpi_dp_add_array(dp, gpio))

diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index acc55e7..908d890 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c

@@ -264,3 +264,67 @@
 	 */
 	acpi_align64(ctx);
 }
+
+void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
+		      int port_type, int port_subtype,
+		      struct acpi_gen_regaddr *address, u32 address_size,
+		      const char *device_path)
+{
+	uintptr_t current;
+	struct acpi_dbg2_device *device;
+	u32 *dbg2_addr_size;
+	struct acpi_table_header *header;
+	size_t path_len;
+	const char *path;
+	char *namespace;
+
+	/* Fill out header fields. */
+	current = (uintptr_t)dbg2;
+	memset(dbg2, '\0', sizeof(struct acpi_dbg2_header));
+	header = &dbg2->header;
+
+	header->revision = acpi_get_table_revision(ACPITAB_DBG2);
+	acpi_fill_header(header, "DBG2");
+	header->aslc_revision = ASL_REVISION;
+
+	/* One debug device defined */
+	dbg2->devices_offset = sizeof(struct acpi_dbg2_header);
+	dbg2->devices_count = 1;
+	current += sizeof(struct acpi_dbg2_header);
+
+	/* Device comes after the header */
+	device = (struct acpi_dbg2_device *)current;
+	memset(device, 0, sizeof(struct acpi_dbg2_device));
+	current += sizeof(struct acpi_dbg2_device);
+
+	device->revision = 0;
+	device->address_count = 1;
+	device->port_type = port_type;
+	device->port_subtype = port_subtype;
+
+	/* Base Address comes after device structure */
+	memcpy((void *)current, address, sizeof(struct acpi_gen_regaddr));
+	device->base_address_offset = current - (uintptr_t)device;
+	current += sizeof(struct acpi_gen_regaddr);
+
+	/* Address Size comes after address structure */
+	dbg2_addr_size = (uint32_t *)current;
+	device->address_size_offset = current - (uintptr_t)device;
+	*dbg2_addr_size = address_size;
+	current += sizeof(uint32_t);
+
+	/* Namespace string comes last, use '.' if not provided */
+	path = device_path ? : ".";
+	/* Namespace string length includes NULL terminator */
+	path_len = strlen(path) + 1;
+	namespace = (char *)current;
+	device->namespace_string_length = path_len;
+	device->namespace_string_offset = current - (uintptr_t)device;
+	strncpy(namespace, path, path_len);
+	current += path_len;
+
+	/* Update structure lengths and checksum */
+	device->length = current - (uintptr_t)device;
+	header->length = current - (uintptr_t)dbg2;
+	header->checksum = table_compute_checksum(dbg2, header->length);
+}

diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index c609ef4..e395226 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c

@@ -17,6 +17,9 @@
 #include <acpi/acpi_table.h>
 #include <dm/acpi.h>
 
+/* CPU path format */
+#define ACPI_CPU_STRING "\\_PR.CP%02d"
+
 u8 *acpigen_get_current(struct acpi_ctx *ctx)
 {
 	return ctx->current;
@@ -340,6 +343,58 @@
 				      ACPI_METHOD_SERIALIZED_MASK);
 }
 
+void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex,
+			     u32 pblock_addr, uint pblock_len)
+{
+	/*
+	 * Processor (\_PR.CPnn, cpuindex, pblock_addr, pblock_len)
+	 * {
+	 */
+	char pscope[16];
+
+	acpigen_emit_ext_op(ctx, PROCESSOR_OP);
+	acpigen_write_len_f(ctx);
+
+	snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex);
+	acpigen_emit_namestring(ctx, pscope);
+	acpigen_emit_byte(ctx, cpuindex);
+	acpigen_emit_dword(ctx, pblock_addr);
+	acpigen_emit_byte(ctx, pblock_len);
+}
+
+void acpigen_write_processor_package(struct acpi_ctx *ctx,
+				     const char *const name,
+				     const uint first_core,
+				     const uint core_count)
+{
+	uint i;
+	char pscope[16];
+
+	acpigen_write_name(ctx, name);
+	acpigen_write_package(ctx, core_count);
+	for (i = first_core; i < first_core + core_count; ++i) {
+		snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, i);
+		acpigen_emit_namestring(ctx, pscope);
+	}
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores)
+{
+	int core_id;
+
+	acpigen_write_method(ctx, "\\_PR.CNOT", 1);
+	for (core_id = 0; core_id < num_cores; core_id++) {
+		char buffer[30];
+
+		snprintf(buffer, sizeof(buffer), ACPI_CPU_STRING, core_id);
+		acpigen_emit_byte(ctx, NOTIFY_OP);
+		acpigen_emit_namestring(ctx, buffer);
+		acpigen_emit_byte(ctx, ARG0_OP);
+	}
+	acpigen_pop_len(ctx);
+}
+
 void acpigen_write_device(struct acpi_ctx *ctx, const char *name)
 {
 	acpigen_emit_ext_op(ctx, DEVICE_OP);
@@ -426,6 +481,183 @@
 	acpigen_write_resourcetemplate_footer(ctx);
 }
 
+void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates)
+{
+	/*
+	 * Method (_PPC, 0, NotSerialized)
+	 * {
+	 *	Return (num_pstates)
+	 * }
+	 */
+	acpigen_write_method(ctx, "_PPC", 0);
+	acpigen_emit_byte(ctx, RETURN_OP);
+	acpigen_write_byte(ctx, num_pstates);
+	acpigen_pop_len(ctx);
+}
+
+/*
+ * Generates a func with max supported P-states saved
+ * in the variable PPCM.
+ */
+void acpigen_write_ppc_nvs(struct acpi_ctx *ctx)
+{
+	/*
+	 * Method (_PPC, 0, NotSerialized)
+	 * {
+	 *	Return (PPCM)
+	 * }
+	 */
+	acpigen_write_method(ctx, "_PPC", 0);
+	acpigen_emit_byte(ctx, RETURN_OP);
+	acpigen_emit_namestring(ctx, "PPCM");
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit)
+{
+	/*
+	 * // Sample _TPC method
+	 * Method (_TPC, 0, NotSerialized)
+	 * {
+	 *	Return (\TLVL)
+	 * }
+	 */
+	acpigen_write_method(ctx, "_TPC", 0);
+	acpigen_emit_byte(ctx, RETURN_OP);
+	acpigen_emit_namestring(ctx, gnvs_tpc_limit);
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level)
+{
+	/* Name (_PRW, Package () { wake, level } */
+	acpigen_write_name(ctx, "_PRW");
+	acpigen_write_package(ctx, 2);
+	acpigen_write_integer(ctx, wake);
+	acpigen_write_integer(ctx, level);
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_pss_package(struct acpi_ctx *ctx, u32 core_freq, u32 power,
+			       u32 trans_lat, u32 busm_lat, u32 control,
+			       u32 status)
+{
+	acpigen_write_package(ctx, 6);
+	acpigen_write_dword(ctx, core_freq);
+	acpigen_write_dword(ctx, power);
+	acpigen_write_dword(ctx, trans_lat);
+	acpigen_write_dword(ctx, busm_lat);
+	acpigen_write_dword(ctx, control);
+	acpigen_write_dword(ctx, status);
+	acpigen_pop_len(ctx);
+
+	log_debug("PSS: %uMHz power %u control 0x%x status 0x%x\n",
+		  core_freq, power, control, status);
+}
+
+void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
+			       enum psd_coord coordtype)
+{
+	acpigen_write_name(ctx, "_PSD");
+	acpigen_write_package(ctx, 1);
+	acpigen_write_package(ctx, 5);
+	acpigen_write_byte(ctx, 5);	// 5 values
+	acpigen_write_byte(ctx, 0);	// revision 0
+	acpigen_write_dword(ctx, domain);
+	acpigen_write_dword(ctx, coordtype);
+	acpigen_write_dword(ctx, numprocs);
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+}
+
+static void acpigen_write_cst_package_entry(struct acpi_ctx *ctx,
+					    const struct acpi_cstate *cstate)
+{
+	acpigen_write_package(ctx, 4);
+	acpigen_write_register_resource(ctx, &cstate->resource);
+	acpigen_write_dword(ctx, cstate->ctype);
+	acpigen_write_dword(ctx, cstate->latency);
+	acpigen_write_dword(ctx, cstate->power);
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_cst_package(struct acpi_ctx *ctx,
+			       const struct acpi_cstate *cstate, int nentries)
+{
+	int i;
+
+	acpigen_write_name(ctx, "_CST");
+	acpigen_write_package(ctx, nentries + 1);
+	acpigen_write_dword(ctx, nentries);
+
+	for (i = 0; i < nentries; i++)
+		acpigen_write_cst_package_entry(ctx, cstate + i);
+
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_csd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
+			       enum csd_coord coordtype, uint index)
+{
+	acpigen_write_name(ctx, "_CSD");
+	acpigen_write_package(ctx, 1);
+	acpigen_write_package(ctx, 6);
+	acpigen_write_byte(ctx, 6);	// 6 values
+	acpigen_write_byte(ctx, 0);	// revision 0
+	acpigen_write_dword(ctx, domain);
+	acpigen_write_dword(ctx, coordtype);
+	acpigen_write_dword(ctx, numprocs);
+	acpigen_write_dword(ctx, index);
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_tss_package(struct acpi_ctx *ctx,
+			       struct acpi_tstate *entry, int nentries)
+{
+	/*
+	 * Sample _TSS package with 100% and 50% duty cycles
+	 * Name (_TSS, Package (0x02)
+	 * {
+	 *	Package(){100, 1000, 0, 0x00, 0)
+	 *	Package(){50, 520, 0, 0x18, 0)
+	 * })
+	 */
+	struct acpi_tstate *tstate = entry;
+	int i;
+
+	acpigen_write_name(ctx, "_TSS");
+	acpigen_write_package(ctx, nentries);
+
+	for (i = 0; i < nentries; i++) {
+		acpigen_write_package(ctx, 5);
+		acpigen_write_dword(ctx, tstate->percent);
+		acpigen_write_dword(ctx, tstate->power);
+		acpigen_write_dword(ctx, tstate->latency);
+		acpigen_write_dword(ctx, tstate->control);
+		acpigen_write_dword(ctx, tstate->status);
+		acpigen_pop_len(ctx);
+		tstate++;
+	}
+
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_tsd_package(struct acpi_ctx *ctx, u32 domain, u32 numprocs,
+			       enum psd_coord coordtype)
+{
+	acpigen_write_name(ctx, "_TSD");
+	acpigen_write_package(ctx, 1);
+	acpigen_write_package(ctx, 5);
+	acpigen_write_byte(ctx, 5);	// 5 values
+	acpigen_write_byte(ctx, 0);	// revision 0
+	acpigen_write_dword(ctx, domain);
+	acpigen_write_dword(ctx, coordtype);
+	acpigen_write_dword(ctx, numprocs);
+	acpigen_pop_len(ctx);
+	acpigen_pop_len(ctx);
+}
+
 /*
  * ToUUID(uuid)
  *
@@ -531,6 +763,128 @@
 	acpigen_emit_ext_op(ctx, DEBUG_OP);
 }
 
+void acpigen_write_if(struct acpi_ctx *ctx)
+{
+	acpigen_emit_byte(ctx, IF_OP);
+	acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val)
+{
+	acpigen_write_if(ctx);
+	acpigen_emit_byte(ctx, LEQUAL_OP);
+	acpigen_emit_byte(ctx, op);
+	acpigen_write_integer(ctx, val);
+}
+
+void acpigen_write_else(struct acpi_ctx *ctx)
+{
+	acpigen_emit_byte(ctx, ELSE_OP);
+	acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+	acpigen_emit_byte(ctx, TO_BUFFER_OP);
+	acpigen_emit_byte(ctx, src);
+	acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+	acpigen_emit_byte(ctx, TO_INTEGER_OP);
+	acpigen_emit_byte(ctx, src);
+	acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_byte_buffer(struct acpi_ctx *ctx, u8 *arr, size_t size)
+{
+	size_t i;
+
+	acpigen_emit_byte(ctx, BUFFER_OP);
+	acpigen_write_len_f(ctx);
+	acpigen_write_integer(ctx, size);
+
+	for (i = 0; i < size; i++)
+		acpigen_emit_byte(ctx, arr[i]);
+
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+				      size_t size)
+{
+	acpigen_emit_byte(ctx, RETURN_OP);
+	acpigen_write_byte_buffer(ctx, arr, size);
+}
+
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg)
+{
+	u8 buf = arg;
+
+	acpigen_write_return_byte_buffer(ctx, &buf, 1);
+}
+
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg)
+{
+	acpigen_emit_byte(ctx, RETURN_OP);
+	acpigen_write_byte(ctx, arg);
+}
+
+void acpigen_write_dsm_start(struct acpi_ctx *ctx)
+{
+	/* Method (_DSM, 4, Serialized) */
+	acpigen_write_method_serialized(ctx, "_DSM", 4);
+
+	/* ToBuffer (Arg0, Local0) */
+	acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP);
+}
+
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid)
+{
+	int ret;
+
+	/* If (LEqual (Local0, ToUUID(uuid))) */
+	acpigen_write_if(ctx);
+	acpigen_emit_byte(ctx, LEQUAL_OP);
+	acpigen_emit_byte(ctx, LOCAL0_OP);
+	ret = acpigen_write_uuid(ctx, uuid);
+	if (ret)
+		return log_msg_ret("uuid", ret);
+
+	/* ToInteger (Arg2, Local1) */
+	acpigen_write_to_integer(ctx, ARG2_OP, LOCAL1_OP);
+
+	return 0;
+}
+
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq)
+{
+	/* If (LEqual (Local1, i)) */
+	acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, seq);
+}
+
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx)
+{
+	acpigen_pop_len(ctx);	/* If */
+}
+
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx)
+{
+	/* Default case: Return (Buffer (One) { 0x0 }) */
+	acpigen_write_return_singleton_buffer(ctx, 0x0);
+
+	acpigen_pop_len(ctx);	/* If (LEqual (Local0, ToUUID(uuid))) */
+}
+
+void acpigen_write_dsm_end(struct acpi_ctx *ctx)
+{
+	/* Return (Buffer (One) { 0x0 }) */
+	acpigen_write_return_singleton_buffer(ctx, 0x0);
+
+	acpigen_pop_len(ctx);	/* Method _DSM */
+}
+
 /**
  * acpigen_get_dw0_in_local5() - Generate code to put dw0 cfg0 in local5
  *

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 5f41f58..b8fc5e2 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c

@@ -1073,8 +1073,6 @@
 	return 0;
 }
 
-#if defined(CONFIG_NR_DRAM_BANKS)
-
 ofnode get_next_memory_node(ofnode mem)
 {
 	do {
@@ -1170,7 +1168,6 @@
 
 	return 0;
 }
-#endif
 
 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
@@ -1319,7 +1316,7 @@
 
 int fdtdec_add_reserved_memory(void *blob, const char *basename,
 			       const struct fdt_memory *carveout,
-			       uint32_t *phandlep)
+			       uint32_t *phandlep, bool no_map)
 {
 	fdt32_t cells[4] = {}, *ptr = cells;
 	uint32_t upper, lower, phandle;
@@ -1419,6 +1416,12 @@
 	if (err < 0)
 		return err;
 
+	if (no_map) {
+		err = fdt_setprop(blob, node, "no-map", NULL, 0);
+		if (err < 0)
+			return err;
+	}
+
 	/* return the phandle for the new node for the caller to use */
 	if (phandlep)
 		*phandlep = phandle;
@@ -1484,7 +1487,7 @@
 	fdt32_t value;
 	void *prop;
 
-	err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle);
+	err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false);
 	if (err < 0) {
 		debug("failed to add reserved memory: %d\n", err);
 		return err;
@@ -1633,7 +1636,6 @@
 }
 #endif
 
-#ifdef CONFIG_NR_DRAM_BANKS
 int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
 			   phys_addr_t *basep, phys_size_t *sizep,
 			   struct bd_info *bd)
@@ -1739,6 +1741,5 @@
 
 	return 0;
 }
-#endif /* CONFIG_NR_DRAM_BANKS */
 
 #endif /* !USE_HOSTCC */

diff --git a/lib/lmb.c b/lib/lmb.c
index 75082f3..d126f8d 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c

@@ -117,22 +117,17 @@
 /* Initialize the struct, add memory and call arch/board reserve functions */
 void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob)
 {
-#ifdef CONFIG_NR_DRAM_BANKS
 	int i;
-#endif
 
 	lmb_init(lmb);
-#ifdef CONFIG_NR_DRAM_BANKS
+
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		if (bd->bi_dram[i].size) {
 			lmb_add(lmb, bd->bi_dram[i].start,
 				bd->bi_dram[i].size);
 		}
 	}
-#else
-	if (bd->bi_memsize)
-		lmb_add(lmb, bd->bi_memstart, bd->bi_memsize);
-#endif
+
 	lmb_reserve_common(lmb, fdt_blob);
 }
 

diff --git a/lib/optee/optee.c b/lib/optee/optee.c
index 457d4cc..9e66065 100644
--- a/lib/optee/optee.c
+++ b/lib/optee/optee.c

@@ -192,7 +192,7 @@
 				ret = fdtdec_add_reserved_memory(new_blob,
 								 nodename,
 								 &carveout,
-								 NULL);
+								 NULL, true);
 				free(oldname);
 
 				if (ret < 0)

diff --git a/net/Kconfig b/net/Kconfig
index 6874b55..1b3e420 100644
--- a/net/Kconfig
+++ b/net/Kconfig

@@ -8,6 +8,12 @@
 
 if NET
 
+config PROT_UDP
+	bool "Enable generic udp framework"
+	help
+	  Enable a generic udp framework that allows defining a custom
+	  handler for udp protocol.
+
 config BOOTP_SEND_HOSTNAME
 	bool "Send hostname to DNS server"
 	help

diff --git a/net/Makefile b/net/Makefile
index fef71b9..76527f7 100644
--- a/net/Makefile
+++ b/net/Makefile

@@ -27,6 +27,7 @@
 obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
 obj-$(CONFIG_UDP_FUNCTION_FASTBOOT)  += fastboot.o
 obj-$(CONFIG_CMD_WOL)  += wol.o
+obj-$(CONFIG_PROT_UDP) += udp.o
 
 # Disable this warning as it is triggered by:
 # sprintf(buf, index ? "foo%d" : "foo", index)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 0d9b75a..396418e 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c

@@ -273,7 +273,7 @@
 	if (!current) {
 		current = eth_get_dev();
 		if (!current) {
-			printf("No ethernet found.\n");
+			log_err("No ethernet found.\n");
 			return -ENODEV;
 		}
 	}
@@ -414,7 +414,7 @@
 	 */
 	uclass_first_device_check(UCLASS_ETH, &dev);
 	if (!dev) {
-		printf("No ethernet found.\n");
+		log_err("No ethernet found.\n");
 		bootstage_error(BOOTSTAGE_ID_NET_ETH_START);
 	} else {
 		char *ethprime = env_get("ethprime");
@@ -449,7 +449,7 @@
 		} while (dev);
 
 		if (!num_devices)
-			printf("No ethernet found.\n");
+			log_err("No ethernet found.\n");
 		putc('\n');
 	}
 

diff --git a/net/eth_legacy.c b/net/eth_legacy.c
index 992d188..6e0c058 100644
--- a/net/eth_legacy.c
+++ b/net/eth_legacy.c

@@ -261,7 +261,7 @@
 	}
 
 	if (!eth_devices) {
-		puts("No ethernet found.\n");
+		log_err("No ethernet found.\n");
 		bootstage_error(BOOTSTAGE_ID_NET_ETH_START);
 	} else {
 		struct eth_device *dev = eth_devices;
@@ -319,7 +319,7 @@
 	struct eth_device *old_current;
 
 	if (!eth_current) {
-		puts("No ethernet found.\n");
+		log_err("No ethernet found.\n");
 		return -ENODEV;
 	}
 

diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
index 66ee2e1..b5e8e46 100644
--- a/net/mdio-uclass.c
+++ b/net/mdio-uclass.c

@@ -145,7 +145,7 @@
 			break;
 
 	if (!ofnode_valid(phandle.node)) {
-		dev_dbg(dev, "can't find PHY node\n");
+		dev_dbg(ethdev, "can't find PHY node\n");
 		return NULL;
 	}
 
@@ -161,7 +161,7 @@
 	if (uclass_get_device_by_ofnode(UCLASS_MDIO,
 					ofnode_get_parent(phandle.node),
 					&mdiodev)) {
-		dev_dbg(dev, "can't find MDIO bus for node %s\n",
+		dev_dbg(ethdev, "can't find MDIO bus for node %s\n",
 			ofnode_get_name(ofnode_get_parent(phandle.node)));
 		return NULL;
 	}

diff --git a/net/net.c b/net/net.c
index 28d9eeb..197fde3 100644
--- a/net/net.c
+++ b/net/net.c

@@ -72,12 +72,6 @@
  *	We want:	- load the boot file
  *	Next step:	none
  *
- * SNTP:
- *
- *	Prerequisites:	- own ethernet address
- *			- own IP address
- *	We want:	- network time
- *	Next step:	none
  *
  * WOL:
  *
@@ -102,6 +96,7 @@
 #if defined(CONFIG_CMD_PCAP)
 #include <net/pcap.h>
 #endif
+#include <net/udp.h>
 #if defined(CONFIG_LED_STATUS)
 #include <miiphy.h>
 #include <status_led.h>
@@ -118,9 +113,6 @@
 #include "nfs.h"
 #include "ping.h"
 #include "rarp.h"
-#if defined(CONFIG_CMD_SNTP)
-#include "sntp.h"
-#endif
 #if defined(CONFIG_CMD_WOL)
 #include "wol.h"
 #endif
@@ -184,13 +176,6 @@
 /* Boot file size in blocks as reported by the DHCP server */
 u32 net_boot_file_expected_size_in_blocks;
 
-#if defined(CONFIG_CMD_SNTP)
-/* NTP server IP address */
-struct in_addr	net_ntp_server;
-/* offset time from UTC */
-int		net_ntp_time_offset;
-#endif
-
 static uchar net_pkt_buf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
 /* Receive packets */
 uchar *net_rx_packets[PKTBUFSRX];
@@ -520,11 +505,6 @@
 			nc_start();
 			break;
 #endif
-#if defined(CONFIG_CMD_SNTP)
-		case SNTP:
-			sntp_start();
-			break;
-#endif
 #if defined(CONFIG_CMD_DNS)
 		case DNS:
 			dns_start();
@@ -544,6 +524,9 @@
 			break;
 		}
 
+		if (IS_ENABLED(CONFIG_PROT_UDP) && protocol == UDP)
+			udp_start();
+
 		break;
 	}
 
@@ -1348,14 +1331,6 @@
 		}
 		goto common;
 #endif
-#if defined(CONFIG_CMD_SNTP)
-	case SNTP:
-		if (net_ntp_server.s_addr == 0) {
-			puts("*** ERROR: NTP server address not given\n");
-			return 1;
-		}
-		goto common;
-#endif
 #if defined(CONFIG_CMD_DNS)
 	case DNS:
 		if (net_dns_server.s_addr == 0) {
@@ -1364,6 +1339,13 @@
 		}
 		goto common;
 #endif
+#if defined(CONFIG_PROT_UDP)
+	case UDP:
+		if (udp_prereq())
+			return 1;
+		goto common;
+#endif
+
 #if defined(CONFIG_CMD_NFS)
 	case NFS:
 #endif
@@ -1374,8 +1356,8 @@
 			puts("*** ERROR: `serverip' not set\n");
 			return 1;
 		}
-#if	defined(CONFIG_CMD_PING) || defined(CONFIG_CMD_SNTP) || \
-	defined(CONFIG_CMD_DNS)
+#if	defined(CONFIG_CMD_PING) || \
+	defined(CONFIG_CMD_DNS) || defined(CONFIG_PROT_UDP)
 common:
 #endif
 		/* Fall through */

diff --git a/net/sntp.c b/net/sntp.c
index 39d7664..d5d5671 100644
--- a/net/sntp.c
+++ b/net/sntp.c

@@ -12,12 +12,17 @@
 #include <net.h>
 #include <rtc.h>
 
-#include "sntp.h"
+#include <net/sntp.h>
 
 #define SNTP_TIMEOUT 10000UL
 
 static int sntp_our_port;
 
+/* NTP server IP address */
+struct in_addr	net_ntp_server;
+/* offset time from UTC */
+int		net_ntp_time_offset;
+
 static void sntp_send(void)
 {
 	struct sntp_pkt_t pkt;
@@ -93,7 +98,25 @@
 	net_set_state(NETLOOP_SUCCESS);
 }
 
+/*
+ * SNTP:
+ *
+ *	Prerequisites:	- own ethernet address
+ *			- own IP address
+ *	We want:	- network time
+ *	Next step:	none
+ */
+int sntp_prereq(void *data)
+{
+	if (net_ntp_server.s_addr == 0) {
+		puts("*** ERROR: NTP server address not given\n");
+		return 1;
+	}
+
+	return 0;
+}
+
-void sntp_start(void)
+int sntp_start(void *data)
 {
 	debug("%s\n", __func__);
 
@@ -102,4 +125,6 @@
 	memset(net_server_ethaddr, 0, sizeof(net_server_ethaddr));
 
 	sntp_send();
+
+	return 0;
 }

diff --git a/net/tftp.c b/net/tftp.c
index 84e970b..6fdb1a8 100644
--- a/net/tftp.c
+++ b/net/tftp.c

@@ -159,7 +159,8 @@
 
 static inline int store_block(int block, uchar *src, unsigned int len)
 {
-	ulong offset = block * tftp_block_size + tftp_block_wrap_offset;
+	ulong offset = block * tftp_block_size + tftp_block_wrap_offset -
+			tftp_block_size;
 	ulong newsize = offset + len;
 	ulong store_addr = tftp_load_addr + offset;
 #ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
@@ -233,7 +234,8 @@
 static int load_block(unsigned block, uchar *dst, unsigned len)
 {
 	/* We may want to get the final block from the previous set */
-	ulong offset = ((int)block - 1) * len + tftp_block_wrap_offset;
+	ulong offset = block * tftp_block_size + tftp_block_wrap_offset -
+		       tftp_block_size;
 	ulong tosend = len;
 
 	tosend = min(net_boot_file_size - offset, tosend);
@@ -502,6 +504,7 @@
 				int block = ntohs(*s);
 				int ack_ok = (tftp_cur_block == block);
 
+				tftp_prev_block = tftp_cur_block;
 				tftp_cur_block = (unsigned short)(block + 1);
 				update_block_number();
 				if (ack_ok)
@@ -651,7 +654,7 @@
 		timeout_count_max = tftp_timeout_count_max;
 		net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
 
-		if (store_block(tftp_cur_block - 1, pkt + 2, len)) {
+		if (store_block(tftp_cur_block, pkt + 2, len)) {
 			eth_halt();
 			net_set_state(NETLOOP_FAIL);
 			break;

diff --git a/net/udp.c b/net/udp.c
new file mode 100644
index 0000000..a93822f
--- /dev/null
+++ b/net/udp.c

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <common.h>
+#include <net.h>
+#include <net/udp.h>
+
+static struct udp_ops *udp_ops;
+
+int udp_prereq(void)
+{
+	int ret = 0;
+
+	if (udp_ops->prereq)
+		ret = udp_ops->prereq(udp_ops->data);
+
+	return ret;
+}
+
+int udp_start(void)
+{
+	return udp_ops->start(udp_ops->data);
+}
+
+int udp_loop(struct udp_ops *ops)
+{
+	int ret = -1;
+
+	if (!ops) {
+		printf("%s: ops should not be null\n", __func__);
+		goto out;
+	}
+
+	if (!ops->start) {
+		printf("%s: no start function defined\n", __func__);
+		goto out;
+	}
+
+	udp_ops = ops;
+	ret = net_loop(UDP);
+
+ out:
+	return ret;
+}

diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped
index fae0b27..1d69ad3 100644
--- a/scripts/dtc/pylibfdt/libfdt.i_shipped
+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped

@@ -786,7 +786,8 @@
             Fdt object allowing access to the newly created device tree
         """
         fdtsw = bytearray(self._fdt)
-        check_err(fdt_finish(fdtsw))
+        while self.check_space(fdt_finish(fdtsw)):
+            fdtsw = bytearray(self._fdt)
         return Fdt(fdtsw)
 
     def check_space(self, val):

diff --git a/test/dm/Makefile b/test/dm/Makefile
index 864c8d0..70ba1b6 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile

@@ -80,4 +80,5 @@
 obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
 obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
 obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
+obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o
 endif

diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c
index e0fa612..44bcabd 100644
--- a/test/dm/acpi_dp.c
+++ b/test/dm/acpi_dp.c

@@ -398,9 +398,9 @@
 
 	/* Try a few different parameters */
 	ut_assertnonnull(acpi_dp_add_gpio(dp, "reset", TEST_REF, 0x23, 0x24,
-					  ACPI_IRQ_ACTIVE_HIGH));
+					  ACPI_GPIO_ACTIVE_HIGH));
 	ut_assertnonnull(acpi_dp_add_gpio(dp, "allow", TEST_REF, 0, 0,
-					  ACPI_IRQ_ACTIVE_LOW));
+					  ACPI_GPIO_ACTIVE_LOW));
 
 	ptr = acpigen_get_current(ctx);
 	ut_assertok(acpi_dp_write(ctx, dp));

diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 1b2767e..3ec2743 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c

@@ -10,6 +10,7 @@
 #include <dm.h>
 #include <irq.h>
 #include <malloc.h>
+#include <uuid.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
 #include <acpi/acpi_table.h>
@@ -1097,3 +1098,649 @@
 	return 0;
 }
 DM_TEST(dm_test_acpi_write_name, 0);
+
+/* Test emitting a _PRW component */
+static int dm_test_acpi_write_prw(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_prw(ctx, 5, 3);
+	ut_asserteq(NAME_OP, *ptr++);
+
+	ut_asserteq_strn("_PRW", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ut_asserteq(8, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(2, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(5, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(3, *ptr++);
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_prw, 0);
+
+/* Test emitting writing conditionals */
+static int dm_test_acpi_write_cond(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_if(ctx);
+	acpigen_pop_len(ctx);
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(3, acpi_test_get_length(ptr));
+	ptr += 3;
+
+	acpigen_write_else(ctx);
+	acpigen_pop_len(ctx);
+	ut_asserteq(ELSE_OP, *ptr++);
+	ut_asserteq(3, acpi_test_get_length(ptr));
+	ptr += 3;
+
+	acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, 5);
+	acpigen_pop_len(ctx);
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(7, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL1_OP, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(5, *ptr++);
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_cond, 0);
+
+/* Test emitting writing return values and ToBuffer/ToInteger */
+static int dm_test_acpi_write_return(struct unit_test_state *uts)
+{
+	int len = sizeof(TEST_STRING);
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP);
+	ut_asserteq(TO_BUFFER_OP, *ptr++);
+	ut_asserteq(ARG0_OP, *ptr++);
+	ut_asserteq(LOCAL0_OP, *ptr++);
+
+	acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP);
+	ut_asserteq(TO_INTEGER_OP, *ptr++);
+	ut_asserteq(ARG0_OP, *ptr++);
+	ut_asserteq(LOCAL0_OP, *ptr++);
+
+	acpigen_write_return_byte_buffer(ctx, (u8 *)TEST_STRING, len);
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ut_asserteq(5 + len, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(len, *ptr++);
+	ut_asserteq_mem(TEST_STRING, ptr, len);
+	ptr += len;
+
+	acpigen_write_return_singleton_buffer(ctx, 123);
+	len = 1;
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ut_asserteq(4 + len, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(ONE_OP, *ptr++);
+	ut_asserteq(123, *ptr++);
+
+	acpigen_write_return_byte(ctx, 43);
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(43, *ptr++);
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_return, 0);
+
+/* Test emitting a DSM for an I2C HID */
+static int dm_test_acpi_write_i2c_dsm(struct unit_test_state *uts)
+{
+	char uuid_str[UUID_STR_LEN + 1];
+	const int reg_offset = 0x20;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	ut_assertok(acpi_device_write_dsm_i2c_hid(ctx, reg_offset));
+
+	/* acpigen_write_dsm_start() */
+	ut_asserteq(METHOD_OP, *ptr++);
+	ut_asserteq(0x78, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq_strn("_DSM", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(ACPI_METHOD_SERIALIZED_MASK | 4, *ptr++);
+
+	ut_asserteq(TO_BUFFER_OP, *ptr++);
+	ut_asserteq(ARG0_OP, *ptr++);
+	ut_asserteq(LOCAL0_OP, *ptr++);
+
+	/* acpigen_write_dsm_uuid_start() */
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(0x65, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL0_OP, *ptr++);
+
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ut_asserteq(UUID_BIN_LEN + 6, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(WORD_PREFIX, *ptr++);
+	ut_asserteq(UUID_BIN_LEN, get_unaligned((u16 *)ptr));
+	ptr += 2;
+	uuid_bin_to_str(ptr, uuid_str, UUID_STR_FORMAT_GUID);
+	ut_asserteq_str(ACPI_DSM_I2C_HID_UUID, uuid_str);
+	ptr += UUID_BIN_LEN;
+
+	ut_asserteq(TO_INTEGER_OP, *ptr++);
+	ut_asserteq(ARG2_OP, *ptr++);
+	ut_asserteq(LOCAL1_OP, *ptr++);
+
+	/* acpigen_write_dsm_uuid_start_cond() */
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(0x34, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL1_OP, *ptr++);
+	ut_asserteq(ZERO_OP, *ptr++);
+
+	/*
+	 * See code from acpi_device_write_dsm_i2c_hid(). We don't check every
+	 * piece
+	 */
+	ut_asserteq(TO_INTEGER_OP, *ptr++);
+	ut_asserteq(ARG1_OP, *ptr++);
+	ut_asserteq(LOCAL2_OP, *ptr++);
+
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(0xd, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL2_OP, *ptr++);
+	ut_asserteq(ZERO_OP, *ptr++);	/* function 0 */
+
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ptr += 5;
+
+	ut_asserteq(ELSE_OP, *ptr++);
+	ptr += 3;
+
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(0xd, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL2_OP, *ptr++);
+	ut_asserteq(ONE_OP, *ptr++);
+
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ptr += 5;
+
+	ut_asserteq(ELSE_OP, *ptr++);
+	ptr += 3;
+
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ptr += 5;
+
+	/* acpigen_write_dsm_uuid_start_cond() */
+	ut_asserteq(IF_OP, *ptr++);
+	ut_asserteq(9, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq(LEQUAL_OP, *ptr++);
+	ut_asserteq(LOCAL1_OP, *ptr++);
+	ut_asserteq(ONE_OP, *ptr++);	/* function 1 */
+
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(reg_offset, *ptr++);
+
+	/* acpigen_write_dsm_uuid_end() */
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ptr += 5;
+
+	/* acpigen_write_dsm_end */
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ptr += 5;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_i2c_dsm, 0);
+
+/* Test emitting a processor */
+static int dm_test_acpi_write_processor(struct unit_test_state *uts)
+{
+	const int cpuindex = 6;
+	const u32 pblock_addr = 0x12345600;
+	const u32 pblock_len = 0x60;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_processor(ctx, cpuindex, pblock_addr, pblock_len);
+	acpigen_pop_len(ctx);
+
+	ut_asserteq(EXT_OP_PREFIX, *ptr++);
+	ut_asserteq(PROCESSOR_OP, *ptr++);
+	ut_asserteq(0x13, acpi_test_get_length(ptr));
+	ptr += 3;
+	ut_asserteq_strn("\\._PR_CP06", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(cpuindex, *ptr++);
+	ut_asserteq(pblock_addr, get_unaligned((u32 *)ptr));
+	ptr += 4;
+	ut_asserteq(pblock_len, *ptr++);
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_processor, 0);
+
+/* Test emitting a processor package */
+static int dm_test_acpi_write_processor_package(struct unit_test_state *uts)
+{
+	const int core_count = 3;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_processor_package(ctx, "XCPU", 0, core_count);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("XCPU", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(core_count, *ptr++);
+
+	ut_asserteq_strn("\\._PR_CP00", (char *)ptr);
+	ptr += 10;
+	ut_asserteq_strn("\\._PR_CP01", (char *)ptr);
+	ptr += 10;
+	ut_asserteq_strn("\\._PR_CP02", (char *)ptr);
+	ptr += 10;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_processor_package, 0);
+
+/* Test emitting a processor notification package */
+static int dm_test_acpi_write_processor_cnot(struct unit_test_state *uts)
+{
+	const int core_count = 3;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_processor_cnot(ctx, core_count);
+
+	ut_asserteq(METHOD_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq_strn("\\._PR_CNOT", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(1, *ptr++);
+
+	ut_asserteq(NOTIFY_OP, *ptr++);
+	ut_asserteq_strn("\\._PR_CP00", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(ARG0_OP, *ptr++);
+	ut_asserteq(NOTIFY_OP, *ptr++);
+	ut_asserteq_strn("\\._PR_CP01", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(ARG0_OP, *ptr++);
+	ut_asserteq(NOTIFY_OP, *ptr++);
+	ut_asserteq_strn("\\._PR_CP02", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(ARG0_OP, *ptr++);
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_processor_cnot, 0);
+
+/* Test acpigen_write_tpc */
+static int dm_test_acpi_write_tpc(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_tpc(ctx, "\\TLVL");
+
+	ut_asserteq(METHOD_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq_strn("_TPC", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(0, *ptr++);
+	ut_asserteq(RETURN_OP, *ptr++);
+	ut_asserteq_strn("\\TLVL", (char *)ptr);
+	ptr += 5;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_tpc, 0);
+
+/* Test acpigen_write_pss_package(), etc. */
+static int dm_test_acpi_write_pss_psd(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_pss_package(ctx, 1, 2, 3, 4, 5, 6);
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(6, *ptr++);
+
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(1, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(2, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(3, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(4, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(5, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(6, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	acpigen_write_psd_package(ctx, 6, 7, HW_ALL);
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("_PSD", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(1, *ptr++);
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(5, *ptr++);
+
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(5, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(0, *ptr++);
+
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(6, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(HW_ALL, get_unaligned((u32 *)ptr));
+	ptr += 5;
+
+	ut_asserteq(7, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_pss_psd, 0);
+
+/* Test acpi_write_cst_package() */
+static int dm_test_acpi_write_cst(struct unit_test_state *uts)
+{
+	static struct acpi_cstate cstate_map[] = {
+		{
+			/* C1 */
+			.ctype = 1,		/* ACPI C1 */
+			.latency = 1,
+			.power = 1000,
+			.resource = {
+				.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			},
+		}, {
+			.ctype = 2,		/* ACPI C2 */
+			.latency = 50,
+			.power = 10,
+			.resource = {
+				.space_id = ACPI_ADDRESS_SPACE_IO,
+				.bit_width = 8,
+				.addrl = 0x415,
+			},
+		},
+	};
+	int nentries = ARRAY_SIZE(cstate_map);
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+	int i;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_cst_package(ctx, cstate_map, nentries);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("_CST", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(nentries + 1, *ptr++);
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(nentries, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	for (i = 0; i < nentries; i++) {
+		ut_asserteq(PACKAGE_OP, *ptr++);
+		ptr += 3;  /* skip length */
+		ut_asserteq(4, *ptr++);
+		ut_asserteq(BUFFER_OP, *ptr++);
+		ptr += 0x17;
+		ut_asserteq(DWORD_PREFIX, *ptr++);
+		ut_asserteq(cstate_map[i].ctype, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(cstate_map[i].latency, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(cstate_map[i].power, get_unaligned((u32 *)ptr));
+		ptr += 4;
+	}
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_cst, 0);
+
+/* Test acpi_write_cst_package() */
+static int dm_test_acpi_write_csd(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_csd_package(ctx, 12, 34, CSD_HW_ALL, 56);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("_CSD", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(1, *ptr++);
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(6, *ptr++);
+
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(6, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(0, *ptr++);
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(12, get_unaligned((u32 *)ptr));
+	ptr += 5;
+	ut_asserteq(CSD_HW_ALL, get_unaligned((u32 *)ptr));
+	ptr += 5;
+	ut_asserteq(34, get_unaligned((u32 *)ptr));
+	ptr += 5;
+	ut_asserteq(56, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_csd, 0);
+
+/* Test acpigen_write_tss_package() */
+static int dm_test_acpi_write_tss(struct unit_test_state *uts)
+{
+	static struct acpi_tstate tstate_list[] = {
+		{ 1, 2, 3, 4, 5, },
+		{ 6, 7, 8, 9, 10, },
+	};
+	int nentries = ARRAY_SIZE(tstate_list);
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+	int i;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_tss_package(ctx, tstate_list, nentries);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("_TSS", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(nentries, *ptr++);
+
+	for (i = 0; i < nentries; i++) {
+		ut_asserteq(PACKAGE_OP, *ptr++);
+		ptr += 3;  /* skip length */
+		ut_asserteq(5, *ptr++);
+		ut_asserteq(DWORD_PREFIX, *ptr++);
+		ut_asserteq(tstate_list[i].percent, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(tstate_list[i].power, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(tstate_list[i].latency, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(tstate_list[i].control, get_unaligned((u32 *)ptr));
+		ptr += 5;
+		ut_asserteq(tstate_list[i].status, get_unaligned((u32 *)ptr));
+		ptr += 4;
+	}
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_tss, 0);
+
+/* Test acpigen_write_tsd_package() */
+static int dm_test_acpi_write_tsd_package(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+
+	ptr = acpigen_get_current(ctx);
+	acpigen_write_tsd_package(ctx, 12, 34, HW_ALL);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("_TSD", (char *)ptr);
+	ptr += 4;
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(1, *ptr++);
+	ut_asserteq(PACKAGE_OP, *ptr++);
+	ptr += 3;  /* skip length */
+	ut_asserteq(5, *ptr++);
+
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(5, *ptr++);
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(0, *ptr++);
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(12, get_unaligned((u32 *)ptr));
+	ptr += 5;
+	ut_asserteq(CSD_HW_ALL, get_unaligned((u32 *)ptr));
+	ptr += 5;
+	ut_asserteq(34, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_tsd_package, 0);

diff --git a/test/dm/bus.c b/test/dm/bus.c
index 865e8bd..27b7266 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c

@@ -120,7 +120,7 @@
 /* Test that we can probe for children */
 static int dm_test_bus_children(struct unit_test_state *uts)
 {
-	int num_devices = 8;
+	int num_devices = 9;
 	struct udevice *bus;
 	struct uclass *uc;
 

diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index 716993f..017157a 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c

@@ -80,7 +80,7 @@
 	resv.start = 0x1000;
 	resv.end = 0x1fff;
 	ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region",
-					       &resv, &phandle));
+					       &resv, &phandle, false));
 
 	/* Test /reserve-memory and its subnode should exist */
 	parent = fdt_path_offset(blob, "/reserved-memory");
@@ -101,10 +101,13 @@
 	resv.start = 0x2000;
 	resv.end = 0x2fff;
 	ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1",
-					       &resv, &phandle1));
+					       &resv, &phandle1, true));
 	subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1");
 	ut_assert(subnode > 0);
 
+	/* check that no-map property is present */
+	ut_assert(fdt_getprop(blob, subnode, "no-map", NULL) > 0);
+
 	/* phandles must be different */
 	ut_assert(phandle != phandle1);
 
@@ -115,7 +118,7 @@
 	resv.start = 0x1000;
 	resv.end = 0x1fff;
 	ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2",
-					       &resv, &phandle1));
+					       &resv, &phandle1, false));
 	subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2");
 	ut_assert(subnode < 0);
 

diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 4848152..54e960b 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c

@@ -10,6 +10,7 @@
 #include <malloc.h>
 #include <acpi/acpi_device.h>
 #include <asm/gpio.h>
+#include <dm/device-internal.h>
 #include <dm/root.h>
 #include <dm/test.h>
 #include <dm/util.h>
@@ -480,3 +481,104 @@
 	return 0;
 }
 DM_TEST(dm_test_gpio_get_acpi_irq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test that we can get/release GPIOs using managed API */
+static int dm_test_gpio_devm(struct unit_test_state *uts)
+{
+	static const u32 flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
+	struct gpio_desc *desc1, *desc2, *desc3, *desc_err;
+	struct udevice *dev;
+	struct udevice *dev2;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_TEST_FDT, "a-test",
+					      &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_TEST_FDT, "another-test",
+					      &dev2));
+
+	/* Get 3 GPIOs from 'a-test' dev */
+	desc1 = devm_gpiod_get_index(dev, "test4", 0, flags);
+	ut_assert(!IS_ERR(desc1));
+	desc2 = devm_gpiod_get_index(dev, "test4", 1, flags);
+	ut_assert(!IS_ERR(desc2));
+	desc3 = devm_gpiod_get_index_optional(dev, "test5", 0, flags);
+	ut_assert(!IS_ERR(desc3));
+	ut_assert(desc3);
+
+	/*
+	 * Try get the same 3 GPIOs from 'a-test' and 'another-test' devices.
+	 * check that it fails
+	 */
+	desc_err = devm_gpiod_get_index(dev, "test4", 0, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index(dev2, "test4", 0, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index(dev, "test4", 1, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index(dev2, "test4", 1, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index_optional(dev, "test5", 0, flags);
+	ut_asserteq_ptr(NULL, desc_err);
+	desc_err = devm_gpiod_get_index_optional(dev2, "test5", 0, flags);
+	ut_asserteq_ptr(NULL, desc_err);
+
+	/* Try get GPIOs outside of the list */
+	desc_err = devm_gpiod_get_index(dev, "test4", 2, flags);
+	ut_assert(IS_ERR(desc_err));
+	desc_err = devm_gpiod_get_index_optional(dev, "test5", 1, flags);
+	ut_asserteq_ptr(NULL, desc_err);
+
+	/* Manipulate the GPIOs */
+	ut_assertok(dm_gpio_set_value(desc1, 1));
+	ut_asserteq(1, dm_gpio_get_value(desc1));
+	ut_assertok(dm_gpio_set_value(desc1, 0));
+	ut_asserteq(0, dm_gpio_get_value(desc1));
+
+	ut_assertok(dm_gpio_set_value(desc2, 1));
+	ut_asserteq(1, dm_gpio_get_value(desc2));
+	ut_assertok(dm_gpio_set_value(desc2, 0));
+	ut_asserteq(0, dm_gpio_get_value(desc2));
+
+	ut_assertok(dm_gpio_set_value(desc3, 1));
+	ut_asserteq(1, dm_gpio_get_value(desc3));
+	ut_assertok(dm_gpio_set_value(desc3, 0));
+	ut_asserteq(0, dm_gpio_get_value(desc3));
+
+	/* Check that the GPIO cannot be owned by more than one device */
+	desc_err = devm_gpiod_get_index(dev2, "test4", 0, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index(dev2, "test4", 1, flags);
+	ut_asserteq(-EBUSY, PTR_ERR(desc_err));
+	desc_err = devm_gpiod_get_index_optional(dev2, "test5", 0, flags);
+	ut_asserteq_ptr(NULL, desc_err);
+
+	/*
+	 * Release one GPIO and check that we can get it back using
+	 * 'another-test' and then 'a-test'
+	 */
+	devm_gpiod_put(dev, desc2);
+	desc2 = devm_gpiod_get_index(dev2, "test4", 1, flags);
+	ut_assert(!IS_ERR(desc2));
+
+	devm_gpiod_put(dev2, desc2);
+	desc2 = devm_gpiod_get_index(dev, "test4", 1, flags);
+	ut_assert(!IS_ERR(desc2));
+
+	/* Release one GPIO before removing the 'a-test' dev. */
+	devm_gpiod_put(dev, desc2);
+	device_remove(dev, DM_REMOVE_NORMAL);
+
+	/* All the GPIOs must have been freed. We should be able to claim
+	 * them with the 'another-test' device.
+	 */
+	desc1 = devm_gpiod_get_index(dev2, "test4", 0, flags);
+	ut_assert(!IS_ERR(desc1));
+	desc2 = devm_gpiod_get_index(dev2, "test4", 1, flags);
+	ut_assert(!IS_ERR(desc2));
+	desc3 = devm_gpiod_get_index_optional(dev2, "test5", 0, flags);
+	ut_assert(!IS_ERR(desc3));
+	ut_assert(desc3);
+
+	device_remove(dev2, DM_REMOVE_NORMAL);
+	return 0;
+}
+DM_TEST(dm_test_gpio_devm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);

diff --git a/test/dm/regmap.c b/test/dm/regmap.c
index bd21c83..2effef3 100644
--- a/test/dm/regmap.c
+++ b/test/dm/regmap.c

@@ -9,8 +9,10 @@
 #include <mapmem.h>
 #include <regmap.h>
 #include <syscon.h>
+#include <rand.h>
 #include <asm/test.h>
 #include <dm/test.h>
+#include <dm/devres.h>
 #include <linux/err.h>
 #include <test/test.h>
 #include <test/ut.h>
@@ -187,3 +189,199 @@
 }
 
 DM_TEST(dm_test_regmap_poll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+struct regmaptest_priv {
+	struct regmap *cfg_regmap; /* For testing regmap_config options. */
+	struct regmap *fld_regmap; /* For testing regmap fields. */
+	struct regmap_field **fields;
+};
+
+static const struct reg_field field_cfgs[] = {
+	{
+		.reg = 0,
+		.lsb = 0,
+		.msb = 6,
+	},
+	{
+		.reg = 2,
+		.lsb = 4,
+		.msb = 12,
+	},
+	{
+		.reg = 2,
+		.lsb = 12,
+		.msb = 15,
+	}
+};
+
+#define REGMAP_TEST_BUF_START 0
+#define REGMAP_TEST_BUF_SZ 5
+
+static int remaptest_probe(struct udevice *dev)
+{
+	struct regmaptest_priv *priv = dev_get_priv(dev);
+	struct regmap *regmap;
+	struct regmap_field *field;
+	struct regmap_config cfg;
+	int i;
+	static const int n = ARRAY_SIZE(field_cfgs);
+
+	/*
+	 * To exercise all the regmap config options, create a regmap that
+	 * points to a custom memory area instead of the one defined in device
+	 * tree. Use 2-byte elements. To allow directly indexing into the
+	 * elements, use an offset shift of 1. So, accessing offset 1 gets the
+	 * element at index 1 at memory location 2.
+	 *
+	 * REGMAP_TEST_BUF_SZ is the number of elements, so we need to multiply
+	 * it by 2 because r_size expects number of bytes.
+	 */
+	cfg.reg_offset_shift = 1;
+	cfg.r_start = REGMAP_TEST_BUF_START;
+	cfg.r_size = REGMAP_TEST_BUF_SZ * 2;
+	cfg.width = REGMAP_SIZE_16;
+
+	regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+	priv->cfg_regmap = regmap;
+
+	memset(&cfg, 0, sizeof(struct regmap_config));
+	cfg.width = REGMAP_SIZE_16;
+
+	regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+	priv->fld_regmap = regmap;
+
+	priv->fields = devm_kzalloc(dev, sizeof(struct regmap_field *) * n,
+				    GFP_KERNEL);
+	if (!priv->fields)
+		return -ENOMEM;
+
+	for (i = 0 ; i < n; i++) {
+		field = devm_regmap_field_alloc(dev, priv->fld_regmap,
+						field_cfgs[i]);
+		if (IS_ERR(field))
+			return PTR_ERR(field);
+		priv->fields[i] = field;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id regmaptest_ids[] = {
+	{ .compatible = "sandbox,regmap_test" },
+	{ }
+};
+
+U_BOOT_DRIVER(regmap_test) = {
+	.name	= "regmaptest_drv",
+	.of_match	= regmaptest_ids,
+	.id	= UCLASS_NOP,
+	.probe = remaptest_probe,
+	.priv_auto_alloc_size = sizeof(struct regmaptest_priv),
+};
+
+static int dm_test_devm_regmap(struct unit_test_state *uts)
+{
+	int i = 0;
+	u32 val;
+	u16 pattern[REGMAP_TEST_BUF_SZ];
+	u16 *buffer;
+	struct udevice *dev;
+	struct regmaptest_priv *priv;
+
+	sandbox_set_enable_memio(true);
+
+	/*
+	 * Map the memory area the regmap should point to so we can make sure
+	 * the writes actually go to that location.
+	 */
+	buffer = map_physmem(REGMAP_TEST_BUF_START,
+			     REGMAP_TEST_BUF_SZ * 2, MAP_NOCACHE);
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
+					      &dev));
+	priv = dev_get_priv(dev);
+
+	srand(get_ticks() + rand());
+	for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
+		pattern[i] = rand();
+		ut_assertok(regmap_write(priv->cfg_regmap, i, pattern[i]));
+	}
+	for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
+		ut_assertok(regmap_read(priv->cfg_regmap, i, &val));
+		ut_asserteq(val, buffer[i]);
+		ut_asserteq(val, pattern[i]);
+	}
+
+	ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
+					  val));
+	ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
+					 &val));
+	ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, -1, val));
+	ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, -1, &val));
+
+	return 0;
+}
+DM_TEST(dm_test_devm_regmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int test_one_field(struct unit_test_state *uts,
+			  struct regmap *regmap,
+			  struct regmap_field *field,
+			  struct reg_field field_cfg)
+{
+	int j;
+	unsigned int val;
+	int mask = (1 << (field_cfg.msb - field_cfg.lsb + 1)) - 1;
+	int shift = field_cfg.lsb;
+
+	ut_assertok(regmap_write(regmap, field_cfg.reg, 0));
+	ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
+	ut_asserteq(0, val);
+
+	for (j = 0; j <= mask; j++) {
+		ut_assertok(regmap_field_write(field, j));
+		ut_assertok(regmap_field_read(field, &val));
+		ut_asserteq(j, val);
+		ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
+		ut_asserteq(j << shift, val);
+	}
+
+	ut_assertok(regmap_field_write(field, mask + 1));
+	ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
+	ut_asserteq(0, val);
+
+	ut_assertok(regmap_field_write(field, 0xFFFF));
+	ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
+	ut_asserteq(mask << shift, val);
+
+	ut_assertok(regmap_write(regmap, field_cfg.reg, 0xFFFF));
+	ut_assertok(regmap_field_write(field, 0));
+	ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
+	ut_asserteq(0xFFFF & ~(mask << shift), val);
+	return 0;
+}
+
+static int dm_test_devm_regmap_field(struct unit_test_state *uts)
+{
+	int i, rc;
+	struct udevice *dev;
+	struct regmaptest_priv *priv;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
+					      &dev));
+	priv = dev_get_priv(dev);
+
+	sandbox_set_enable_memio(true);
+	for (i = 0 ; i < ARRAY_SIZE(field_cfgs); i++) {
+		rc = test_one_field(uts, priv->fld_regmap, priv->fields[i],
+				    field_cfgs[i]);
+		if (rc)
+			break;
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_devm_regmap_field, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);

diff --git a/test/dm/reset.c b/test/dm/reset.c
index f5f3661..fc8e925 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c

@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <log.h>
 #include <malloc.h>
 #include <reset.h>
@@ -60,12 +61,39 @@
 	ut_assertok(sandbox_reset_test_deassert(dev_test));
 	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
 
+	ut_asserteq(1, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
 	ut_assertok(sandbox_reset_test_free(dev_test));
+	ut_asserteq(0, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
 
 	return 0;
 }
 DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
 
+static int dm_test_reset_devm(struct unit_test_state *uts)
+{
+	struct udevice *dev_reset;
+	struct udevice *dev_test;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
+					      &dev_reset));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+					      &dev_test));
+	ut_assertok(sandbox_reset_test_get_devm(dev_test));
+
+	ut_assertok(sandbox_reset_test_assert(dev_test));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_assertok(sandbox_reset_test_deassert(dev_test));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+
+	ut_asserteq(1, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
+	ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
+	ut_asserteq(0, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
+
+	return 0;
+}
+DM_TEST(dm_test_reset_devm, UT_TESTF_SCAN_FDT);
+
 static int dm_test_reset_bulk(struct unit_test_state *uts)
 {
 	struct udevice *dev_reset;
@@ -95,3 +123,35 @@
 	return 0;
 }
 DM_TEST(dm_test_reset_bulk, UT_TESTF_SCAN_FDT);
+
+static int dm_test_reset_bulk_devm(struct unit_test_state *uts)
+{
+	struct udevice *dev_reset;
+	struct udevice *dev_test;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
+					      &dev_reset));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+					      &dev_test));
+	ut_assertok(sandbox_reset_test_get_bulk_devm(dev_test));
+
+	ut_assertok(sandbox_reset_test_assert_bulk(dev_test));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_assertok(sandbox_reset_test_deassert_bulk(dev_test));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_asserteq(1, sandbox_reset_is_requested(dev_reset, OTHER_RESET_ID));
+	ut_asserteq(1, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
+	ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
+	ut_asserteq(0, sandbox_reset_is_requested(dev_reset, TEST_RESET_ID));
+	ut_asserteq(0, sandbox_reset_is_requested(dev_reset, OTHER_RESET_ID));
+
+	return 0;
+}
+DM_TEST(dm_test_reset_bulk_devm, UT_TESTF_SCAN_FDT);

diff --git a/test/dm/scmi.c b/test/dm/scmi.c
new file mode 100644
index 0000000..be60b44
--- /dev/null
+++ b/test/dm/scmi.c

@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Linaro Limited
+ *
+ * Tests scmi_agent uclass and the SCMI drivers implemented in other
+ * uclass devices probe when a SCMI server exposes resources.
+ *
+ * Note in test.dts the protocol@10 node in agent 1. Protocol 0x10 is not
+ * implemented in U-Boot SCMI components but the implementation is exepected
+ * to not complain on unknown protocol IDs, as long as it is not used. Note
+ * in test.dts tests that SCMI drivers probing does not fail for such an
+ * unknown SCMI protocol ID.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <asm/scmi_test.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <linux/kconfig.h>
+#include <test/ut.h>
+
+static int ut_assert_scmi_state_preprobe(struct unit_test_state *uts)
+{
+	struct sandbox_scmi_service *scmi_ctx = sandbox_scmi_service_ctx();
+
+	ut_assertnonnull(scmi_ctx);
+	if (scmi_ctx->agent_count)
+		ut_asserteq(2, scmi_ctx->agent_count);
+
+	return 0;
+}
+
+static int ut_assert_scmi_state_postprobe(struct unit_test_state *uts,
+					  struct udevice *dev)
+{
+	struct sandbox_scmi_devices *scmi_devices;
+	struct sandbox_scmi_service *scmi_ctx;
+
+	/* Device references to check context against test sequence */
+	scmi_devices = sandbox_scmi_devices_ctx(dev);
+
+	ut_assertnonnull(scmi_devices);
+	if (IS_ENABLED(CONFIG_CLK_SCMI))
+		ut_asserteq(3, scmi_devices->clk_count);
+	if (IS_ENABLED(CONFIG_RESET_SCMI))
+		ut_asserteq(1, scmi_devices->reset_count);
+
+	/* State of the simulated SCMI server exposed */
+	scmi_ctx = sandbox_scmi_service_ctx();
+
+	ut_asserteq(2, scmi_ctx->agent_count);
+
+	ut_assertnonnull(scmi_ctx->agent[0]);
+	ut_asserteq(2, scmi_ctx->agent[0]->clk_count);
+	ut_assertnonnull(scmi_ctx->agent[0]->clk);
+	ut_asserteq(1, scmi_ctx->agent[0]->reset_count);
+	ut_assertnonnull(scmi_ctx->agent[0]->reset);
+
+	ut_assertnonnull(scmi_ctx->agent[1]);
+	ut_assertnonnull(scmi_ctx->agent[1]->clk);
+	ut_asserteq(1, scmi_ctx->agent[1]->clk_count);
+
+	return 0;
+}
+
+static int load_sandbox_scmi_test_devices(struct unit_test_state *uts,
+					  struct udevice **dev)
+{
+	int ret;
+
+	ret = ut_assert_scmi_state_preprobe(uts);
+	if (ret)
+		return ret;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_scmi",
+					      dev));
+	ut_assertnonnull(*dev);
+
+	return ut_assert_scmi_state_postprobe(uts, *dev);
+}
+
+static int release_sandbox_scmi_test_devices(struct unit_test_state *uts,
+					     struct udevice *dev)
+{
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
+
+	/* Not sure test devices are fully removed, agent may not be visible */
+	return 0;
+}
+
+/*
+ * Test SCMI states when loading and releasing resources
+ * related to SCMI drivers.
+ */
+static int dm_test_scmi_sandbox_agent(struct unit_test_state *uts)
+{
+	struct udevice *dev = NULL;
+	int ret;
+
+	ret = load_sandbox_scmi_test_devices(uts, &dev);
+	if (!ret)
+		ret = release_sandbox_scmi_test_devices(uts, dev);
+
+	return ret;
+}
+
+DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT);
+
+static int dm_test_scmi_clocks(struct unit_test_state *uts)
+{
+	struct sandbox_scmi_devices *scmi_devices;
+	struct sandbox_scmi_service *scmi_ctx;
+	struct udevice *dev = NULL;
+	int ret_dev;
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_CLK_SCMI))
+		return 0;
+
+	ret = load_sandbox_scmi_test_devices(uts, &dev);
+	if (ret)
+		return ret;
+
+	scmi_devices = sandbox_scmi_devices_ctx(dev);
+	scmi_ctx = sandbox_scmi_service_ctx();
+
+	/* Test SCMI clocks rate manipulation */
+	ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0]));
+	ut_asserteq(333, clk_get_rate(&scmi_devices->clk[1]));
+	ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2]));
+
+	ret_dev = clk_set_rate(&scmi_devices->clk[1], 1088);
+	ut_assert(!ret_dev || ret_dev == 1088);
+
+	ut_asserteq(1000, scmi_ctx->agent[0]->clk[0].rate);
+	ut_asserteq(1088, scmi_ctx->agent[0]->clk[1].rate);
+	ut_asserteq(44, scmi_ctx->agent[1]->clk[0].rate);
+
+	ut_asserteq(1000, clk_get_rate(&scmi_devices->clk[0]));
+	ut_asserteq(1088, clk_get_rate(&scmi_devices->clk[1]));
+	ut_asserteq(44, clk_get_rate(&scmi_devices->clk[2]));
+
+	/* restore original rate for further tests */
+	ret_dev = clk_set_rate(&scmi_devices->clk[1], 333);
+	ut_assert(!ret_dev || ret_dev == 333);
+
+	/* Test SCMI clocks gating manipulation */
+	ut_assert(!scmi_ctx->agent[0]->clk[0].enabled);
+	ut_assert(!scmi_ctx->agent[0]->clk[1].enabled);
+	ut_assert(!scmi_ctx->agent[1]->clk[0].enabled);
+
+	ut_asserteq(0, clk_enable(&scmi_devices->clk[1]));
+	ut_asserteq(0, clk_enable(&scmi_devices->clk[2]));
+
+	ut_assert(!scmi_ctx->agent[0]->clk[0].enabled);
+	ut_assert(scmi_ctx->agent[0]->clk[1].enabled);
+	ut_assert(scmi_ctx->agent[1]->clk[0].enabled);
+
+	ut_assertok(clk_disable(&scmi_devices->clk[1]));
+	ut_assertok(clk_disable(&scmi_devices->clk[2]));
+
+	ut_assert(!scmi_ctx->agent[0]->clk[0].enabled);
+	ut_assert(!scmi_ctx->agent[0]->clk[1].enabled);
+	ut_assert(!scmi_ctx->agent[1]->clk[0].enabled);
+
+	return release_sandbox_scmi_test_devices(uts, dev);
+}
+
+DM_TEST(dm_test_scmi_clocks, UT_TESTF_SCAN_FDT);
+
+static int dm_test_scmi_resets(struct unit_test_state *uts)
+{
+	struct sandbox_scmi_devices *scmi_devices;
+	struct sandbox_scmi_service *scmi_ctx;
+	struct udevice *dev = NULL;
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_RESET_SCMI))
+		return 0;
+
+	ret = load_sandbox_scmi_test_devices(uts, &dev);
+	if (ret)
+		return ret;
+
+	scmi_devices = sandbox_scmi_devices_ctx(dev);
+	scmi_ctx = sandbox_scmi_service_ctx();
+
+	/* Test SCMI resect controller manipulation */
+	ut_assert(!scmi_ctx->agent[0]->reset[0].asserted)
+
+	ut_assertok(reset_assert(&scmi_devices->reset[0]));
+	ut_assert(scmi_ctx->agent[0]->reset[0].asserted)
+
+	ut_assertok(reset_deassert(&scmi_devices->reset[0]));
+	ut_assert(!scmi_ctx->agent[0]->reset[0].asserted);
+
+	return release_sandbox_scmi_test_devices(uts, dev);
+}
+
+DM_TEST(dm_test_scmi_resets, UT_TESTF_SCAN_FDT);

diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 04802de..26d57f4 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c

@@ -251,7 +251,7 @@
 /* Test that FDT-based binding works correctly */
 static int dm_test_fdt(struct unit_test_state *uts)
 {
-	const int num_devices = 8;
+	const int num_devices = 9;
 	struct udevice *dev;
 	struct uclass *uc;
 	int ret;
@@ -473,12 +473,12 @@
 	count = 0;
 	uclass_id_foreach_dev(UCLASS_TEST_FDT, dev, uc)
 		count++;
-	ut_asserteq(8, count);
+	ut_asserteq(9, count);
 
 	count = 0;
 	uclass_foreach_dev(dev, uc)
 		count++;
-	ut_asserteq(8, count);
+	ut_asserteq(9, count);
 
 	return 0;
 }

diff --git a/test/dm/timer.c b/test/dm/timer.c
index 95dab97..70043b9 100644
--- a/test/dm/timer.c
+++ b/test/dm/timer.c

@@ -7,8 +7,10 @@
 #include <dm.h>
 #include <timer.h>
 #include <dm/test.h>
+#include <dm/device-internal.h>
 #include <test/test.h>
 #include <test/ut.h>
+#include <asm/cpu.h>
 
 /*
  * Basic test of the timer uclass.
@@ -17,9 +19,32 @@
 {
 	struct udevice *dev;
 
-	ut_assertok(uclass_get_device(UCLASS_TIMER, 0, &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@0", &dev));
 	ut_asserteq(1000000, timer_get_rate(dev));
 
 	return 0;
 }
 DM_TEST(dm_test_timer_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/*
+ * Test of timebase fallback
+ */
+static int dm_test_timer_timebase_fallback(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+
+	cpu_sandbox_set_current("cpu-test1");
+	ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev));
+	ut_asserteq(3000000, timer_get_rate(dev));
+	ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
+
+	cpu_sandbox_set_current("cpu-test2");
+	ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev));
+	ut_asserteq(2000000, timer_get_rate(dev));
+
+	cpu_sandbox_set_current("cpu-test1");
+
+	return 0;
+}
+DM_TEST(dm_test_timer_timebase_fallback,
+	UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);

diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 5e73d40..6703325 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py

@@ -16,7 +16,7 @@
                         leaf = leaf + '`'
 
 	leaf = leaf + '-- ' + name
-	line = (r' *{:10.10}    [0-9]*  \[ [ +] \]   {:20.20}  [` |]{}$'
+	line = (r' *{:10.10} *[0-9]*  \[ [ +] \]   {:20.20}  [` |]{}$'
 	        .format(uclass, drv, leaf))
 	prog = re.compile(line)
 	for l in lines:

diff --git a/tools/binman/README b/tools/binman/README
index 37ee3fc..fbcfdc7 100644
--- a/tools/binman/README
+++ b/tools/binman/README

@@ -343,6 +343,12 @@
 	Sets the compression algortihm to use (for blobs only). See the entry
 	documentation for details.
 
+missing-msg:
+	Sets the tag of the message to show if this entry is missing. This is
+	used for external blobs. When they are missing it is helpful to show
+	information about what needs to be fixed. See missing-blob-help for the
+	message for each tag.
+
 The attributes supported for images and sections are described below. Several
 are similar to those for entries.
 
@@ -884,6 +890,12 @@
 but the --toolpath option can be used to specify additional search paths to
 use. This option can be specified multiple times to add more than one path.
 
+For some compile tools binman will use the versions specified by commonly-used
+environment variables like CC and HOSTCC for the C compiler, based on whether
+the tool's output will be used for the target or for the host machine. If those
+aren't given, it will also try to derive target-specific versions from the
+CROSS_COMPILE environment variable during a cross-compilation.
+
 
 Code coverage
 -------------
@@ -918,6 +930,24 @@
 this.
 
 
+Running tests on non-x86 architectures
+--------------------------------------
+
+Binman's tests have been written under the assumption that they'll be run on a
+x86-like host and there hasn't been an attempt to make them portable yet.
+However, it's possible to run the tests by cross-compiling to x86.
+
+To install an x86 cross-compiler on Debian-type distributions (e.g. Ubuntu):
+
+  $ sudo apt-get install gcc-x86-64-linux-gnu
+
+Then, you can run the tests under cross-compilation:
+
+  $ CROSS_COMPILE=x86_64-linux-gnu- binman test -T
+
+You can also use gcc-i686-linux-gnu similar to the above.
+
+
 Advanced Features / Technical docs
 ----------------------------------
 

diff --git a/tools/binman/README.entries b/tools/binman/README.entries
index bf8edce..c1d4365 100644
--- a/tools/binman/README.entries
+++ b/tools/binman/README.entries

@@ -11,6 +11,20 @@
 
 
 
+Entry: atf-bl31: Entry containing an ARM Trusted Firmware (ATF) BL31 blob
+-------------------------------------------------------------------------
+
+Properties / Entry arguments:
+    - atf-bl31-path: Filename of file to read into entry. This is typically
+        called bl31.bin or bl31.elf
+
+This entry holds the run-time firmware, typically started by U-Boot SPL.
+See the U-Boot README for your architecture or board for how to use it. See
+https://github.com/ARM-software/arm-trusted-firmware for more information
+about ATF.
+
+
+
 Entry: blob: Entry containing an arbitrary binary blob
 ------------------------------------------------------
 
@@ -60,7 +74,7 @@
 
 Properties / Entry arguments:
     - <xxx>-path: Filename containing the contents of this entry (optional,
-        defaults to 0)
+        defaults to None)
 
 where <xxx> is the blob_fname argument to the constructor.
 
@@ -325,6 +339,7 @@
     binman {
         fit {
             description = "Test FIT";
+            fit,fdt-list = "of-list";
 
             images {
                 kernel@1 {
@@ -343,7 +358,56 @@
         };
     };
 
-Properties:
+U-Boot supports creating fdt and config nodes automatically. To do this,
+pass an of-list property (e.g. -a of-list=file1 file2). This tells binman
+that you want to generates nodes for two files: file1.dtb and file2.dtb
+The fit,fdt-list property (see above) indicates that of-list should be used.
+If the property is missing you will get an error.
+
+Then add a 'generator node', a node with a name starting with '@':
+
+    images {
+        @fdt-SEQ {
+            description = "fdt-NAME";
+            type = "flat_dt";
+            compression = "none";
+        };
+    };
+
+This tells binman to create nodes fdt-1 and fdt-2 for each of your two
+files. All the properties you specify will be included in the node. This
+node acts like a template to generate the nodes. The generator node itself
+does not appear in the output - it is replaced with what binman generates.
+
+You can create config nodes in a similar way:
+
+    configurations {
+        default = "@config-DEFAULT-SEQ";
+        @config-SEQ {
+            description = "NAME";
+            firmware = "uboot";
+            loadables = "atf";
+            fdt = "fdt-SEQ";
+        };
+    };
+
+This tells binman to create nodes config-1 and config-2, i.e. a config for
+each of your two files.
+
+Available substitutions for '@' nodes are:
+
+    SEQ    Sequence number of the generated fdt (1, 2, ...)
+    NAME   Name of the dtb as provided (i.e. without adding '.dtb')
+
+Note that if no devicetree files are provided (with '-a of-list' as above)
+then no nodes will be generated.
+
+The 'default' property, if present, will be automatically set to the name
+if of configuration whose devicetree matches the 'default-dt' entry
+argument, e.g. with '-a default-dt=sun50i-a64-pine64-lts'.
+
+
+Properties (in the 'fit' node itself):
     fit,external-offset: Indicates that the contents of the FIT are external
         and provides the external offset. This is passsed to mkimage via
         the -E and -p flags.
@@ -691,6 +755,11 @@
     name-prefix: Adds a prefix to the name of every entry in the section
         when writing out the map
 
+Properties:
+    allow_missing: True if this section permits external blobs to be
+        missing their contents. The second will produce an image but of
+        course it will not work.
+
 Since a section is also an entry, it inherits all the properies of entries
 too.
 

diff --git a/tools/binman/control.py b/tools/binman/control.py
index 60e89d3..ee5771e 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py

@@ -8,6 +8,9 @@
 from collections import OrderedDict
 import glob
 import os
+import pkg_resources
+import re
+
 import sys
 from patman import tools
 
@@ -20,6 +23,11 @@
 # Make this global so that it can be referenced from tests
 images = OrderedDict()
 
+# Help text for each type of missing blob, dict:
+#    key: Value of the entry's 'missing-msg' or entry name
+#    value: Text for the help
+missing_blob_help = {}
+
 def _ReadImageDesc(binman_node):
     """Read the image descriptions from the /binman node
 
@@ -52,14 +60,74 @@
             return node
     return None
 
+def _ReadMissingBlobHelp():
+    """Read the missing-blob-help file
+
+    This file containins help messages explaining what to do when external blobs
+    are missing.
+
+    Returns:
+        Dict:
+            key: Message tag (str)
+            value: Message text (str)
+    """
+
+    def _FinishTag(tag, msg, result):
+        if tag:
+            result[tag] = msg.rstrip()
+            tag = None
+            msg = ''
+        return tag, msg
+
+    my_data = pkg_resources.resource_string(__name__, 'missing-blob-help')
+    re_tag = re.compile('^([-a-z0-9]+):$')
+    result = {}
+    tag = None
+    msg = ''
+    for line in my_data.decode('utf-8').splitlines():
+        if not line.startswith('#'):
+            m_tag = re_tag.match(line)
+            if m_tag:
+                _, msg = _FinishTag(tag, msg, result)
+                tag = m_tag.group(1)
+            elif tag:
+                msg += line + '\n'
+    _FinishTag(tag, msg, result)
+    return result
+
+def _ShowBlobHelp(path, text):
+    tout.Warning('\n%s:' % path)
+    for line in text.splitlines():
+        tout.Warning('   %s' % line)
+
+def _ShowHelpForMissingBlobs(missing_list):
+    """Show help for each missing blob to help the user take action
+
+    Args:
+        missing_list: List of Entry objects to show help for
+    """
+    global missing_blob_help
+
+    if not missing_blob_help:
+        missing_blob_help = _ReadMissingBlobHelp()
+
+    for entry in missing_list:
+        tags = entry.GetHelpTags()
+
+        # Show the first match help message
+        for tag in tags:
+            if tag in missing_blob_help:
+                _ShowBlobHelp(entry._node.path, missing_blob_help[tag])
+                break
+
 def GetEntryModules(include_testing=True):
     """Get a set of entry class implementations
 
     Returns:
         Set of paths to entry class filenames
     """
-    our_path = os.path.dirname(os.path.realpath(__file__))
-    glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
+    glob_list = pkg_resources.resource_listdir(__name__, 'etype')
+    glob_list = [fname for fname in glob_list if fname.endswith('.py')]
     return set([os.path.splitext(os.path.basename(item))[0]
                 for item in glob_list
                 if include_testing or '_testing' not in item])
@@ -344,6 +412,11 @@
         dtb_fname: Filename of the device tree file to use (.dts or .dtb)
         selected_images: List of images to output, or None for all
         update_fdt: True to update the FDT wth entry offsets, etc.
+
+    Returns:
+        OrderedDict of images:
+            key: Image name (str)
+            value: Image object
     """
     # Import these here in case libfdt.py is not available, in which case
     # the above help option still works.
@@ -471,6 +544,7 @@
     if missing_list:
         tout.Warning("Image '%s' is missing external blobs and is non-functional: %s" %
                      (image.name, ' '.join([e.name for e in missing_list])))
+        _ShowHelpForMissingBlobs(missing_list)
     return bool(missing_list)
 
 
@@ -556,7 +630,7 @@
                 tools.WriteFile(dtb_item._fname, dtb_item.GetContents())
 
             if missing:
-                tout.Warning("Some images are invalid")
+                tout.Warning("\nSome images are invalid")
         finally:
             tools.FinaliseOutputDir()
     finally:

diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index f88031c..5e566e5 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py

@@ -234,8 +234,10 @@
     #   text section at the start
     # -m32: Build for 32-bit x86
     # -T...: Specifies the link script, which sets the start address
-    stdout = command.Output('cc', '-static', '-nostdlib', '-Wl,--build-id=none',
-                            '-m32','-T', lds_file, '-o', elf_fname, s_file)
+    cc, args = tools.GetTargetCompileTool('cc')
+    args += ['-static', '-nostdlib', '-Wl,--build-id=none', '-m32', '-T',
+            lds_file, '-o', elf_fname, s_file]
+    stdout = command.Output(cc, *args)
     shutil.rmtree(outdir)
 
 def DecodeElf(data, location):

diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index 37e1b42..e3d218a 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py

@@ -186,7 +186,9 @@
         # Make an Elf file and then convert it to a fkat binary file. This
         # should produce the original data.
         elf.MakeElf(elf_fname, expected_text, expected_data)
-        stdout = command.Output('objcopy', '-O', 'binary', elf_fname, bin_fname)
+        objcopy, args = tools.GetTargetCompileTool('objcopy')
+        args += ['-O', 'binary', elf_fname, bin_fname]
+        stdout = command.Output(objcopy, *args)
         with open(bin_fname, 'rb') as fd:
             data = fd.read()
         self.assertEqual(expected_text + expected_data, data)

diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 3434a3f..f7adc3b 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py

@@ -16,8 +16,6 @@
 
 modules = {}
 
-our_path = os.path.dirname(os.path.realpath(__file__))
-
 
 # An argument which can be passed to entries on the command line, in lieu of
 # device-tree properties.
@@ -59,6 +57,10 @@
         compress: Compression algoithm used (e.g. 'lz4'), 'none' if none
         orig_offset: Original offset value read from node
         orig_size: Original size value read from node
+        missing: True if this entry is missing its contents
+        allow_missing: Allow children of this entry to be missing (used by
+            subclasses such as Entry_section)
+        external: True if this entry contains an external binary blob
     """
     def __init__(self, section, etype, node, name_prefix=''):
         # Put this here to allow entry-docs and help to work without libfdt
@@ -85,6 +87,8 @@
         self._expand_size = False
         self.compress = 'none'
         self.missing = False
+        self.external = False
+        self.allow_missing = False
 
     @staticmethod
     def Lookup(node_path, etype):
@@ -174,6 +178,7 @@
         self.align_end = fdt_util.GetInt(self._node, 'align-end')
         self.offset_unset = fdt_util.GetBool(self._node, 'offset-unset')
         self.expand_size = fdt_util.GetBool(self._node, 'expand-size')
+        self.missing_msg = fdt_util.GetString(self._node, 'missing-msg')
 
     def GetDefaultFilename(self):
         return None
@@ -815,3 +820,19 @@
         """
         if self.missing:
             missing_list.append(self)
+
+    def GetAllowMissing(self):
+        """Get whether a section allows missing external blobs
+
+        Returns:
+            True if allowed, False if not allowed
+        """
+        return self.allow_missing
+
+    def GetHelpTags(self):
+        """Get the tags use for missing-blob help
+
+        Returns:
+            list of possible tags, most desirable first
+        """
+        return list(filter(None, [self.missing_msg, self.name, self.etype]))

diff --git a/tools/binman/etype/atf_bl31.py b/tools/binman/etype/atf_bl31.py
new file mode 100644
index 0000000..195adc7
--- /dev/null
+++ b/tools/binman/etype/atf_bl31.py

@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2020 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for Intel Management Engine binary blob
+#
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+
+class Entry_atf_bl31(Entry_blob_named_by_arg):
+    """Entry containing an ARM Trusted Firmware (ATF) BL31 blob
+
+    Properties / Entry arguments:
+        - atf-bl31-path: Filename of file to read into entry. This is typically
+            called bl31.bin or bl31.elf
+
+    This entry holds the run-time firmware, typically started by U-Boot SPL.
+    See the U-Boot README for your architecture or board for how to use it. See
+    https://github.com/ARM-software/arm-trusted-firmware for more information
+    about ATF.
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node, 'atf-bl31')
+        self.external = True

diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
index e507203..ecfb1e4 100644
--- a/tools/binman/etype/blob.py
+++ b/tools/binman/etype/blob.py

@@ -37,7 +37,14 @@
 
     def ObtainContents(self):
         self._filename = self.GetDefaultFilename()
-        self._pathname = tools.GetInputFilename(self._filename)
+        self._pathname = tools.GetInputFilename(self._filename,
+            self.external and self.section.GetAllowMissing())
+        # Allow the file to be missing
+        if not self._pathname:
+            self.SetContents(b'')
+            self.missing = True
+            return True
+
         self.ReadBlobContents()
         return True
 

diff --git a/tools/binman/etype/blob_ext.py b/tools/binman/etype/blob_ext.py
index 8d64100..e372445 100644
--- a/tools/binman/etype/blob_ext.py
+++ b/tools/binman/etype/blob_ext.py

@@ -26,14 +26,3 @@
     def __init__(self, section, etype, node):
         Entry_blob.__init__(self, section, etype, node)
         self.external = True
-
-    def ObtainContents(self):
-        self._filename = self.GetDefaultFilename()
-        self._pathname = tools.GetInputFilename(self._filename,
-                                                self.section.GetAllowMissing())
-        # Allow the file to be missing
-        if not self._pathname:
-            self.SetContents(b'')
-            self.missing = True
-            return True
-        return super().ObtainContents()

diff --git a/tools/binman/etype/blob_named_by_arg.py b/tools/binman/etype/blob_named_by_arg.py
index e95dabe..7c486b2 100644
--- a/tools/binman/etype/blob_named_by_arg.py
+++ b/tools/binman/etype/blob_named_by_arg.py

@@ -17,7 +17,7 @@
 
     Properties / Entry arguments:
         - <xxx>-path: Filename containing the contents of this entry (optional,
-            defaults to 0)
+            defaults to None)
 
     where <xxx> is the blob_fname argument to the constructor.
 
@@ -28,7 +28,9 @@
 
     See cros_ec_rw for an example of this.
     """
-    def __init__(self, section, etype, node, blob_fname):
+    def __init__(self, section, etype, node, blob_fname, required=False):
         super().__init__(section, etype, node)
-        self._filename, = self.GetEntryArgsOrProps(
-            [EntryArg('%s-path' % blob_fname, str)])
+        filename, = self.GetEntryArgsOrProps(
+            [EntryArg('%s-path' % blob_fname, str)], required=required)
+        if filename:
+            self._filename = filename

diff --git a/tools/binman/etype/cros_ec_rw.py b/tools/binman/etype/cros_ec_rw.py
index 741372e..bf676b2 100644
--- a/tools/binman/etype/cros_ec_rw.py
+++ b/tools/binman/etype/cros_ec_rw.py

@@ -7,7 +7,6 @@
 
 from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
 
-
 class Entry_cros_ec_rw(Entry_blob_named_by_arg):
     """A blob entry which contains a Chromium OS read-write EC image
 
@@ -18,5 +17,5 @@
     updating the EC on startup via software sync.
     """
     def __init__(self, section, etype, node):
-        super().__init__(section, etype, node, 'cros-ec-rw')
+        super().__init__(section, etype, node, 'cros-ec-rw', required=True)
         self.external = True

diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index 75712f4..de4745c 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py

@@ -8,7 +8,7 @@
 from collections import defaultdict, OrderedDict
 import libfdt
 
-from binman.entry import Entry
+from binman.entry import Entry, EntryArg
 from dtoc import fdt_util
 from dtoc.fdt import Fdt
 from patman import tools
@@ -27,6 +27,7 @@
         binman {
             fit {
                 description = "Test FIT";
+                fit,fdt-list = "of-list";
 
                 images {
                     kernel@1 {
@@ -45,7 +46,60 @@
             };
         };
 
-    Properties:
+    U-Boot supports creating fdt and config nodes automatically. To do this,
+    pass an of-list property (e.g. -a of-list=file1 file2). This tells binman
+    that you want to generates nodes for two files: file1.dtb and file2.dtb
+    The fit,fdt-list property (see above) indicates that of-list should be used.
+    If the property is missing you will get an error.
+
+    Then add a 'generator node', a node with a name starting with '@':
+
+        images {
+            @fdt-SEQ {
+                description = "fdt-NAME";
+                type = "flat_dt";
+                compression = "none";
+            };
+        };
+
+    This tells binman to create nodes fdt-1 and fdt-2 for each of your two
+    files. All the properties you specify will be included in the node. This
+    node acts like a template to generate the nodes. The generator node itself
+    does not appear in the output - it is replaced with what binman generates.
+
+    You can create config nodes in a similar way:
+
+        configurations {
+            default = "@config-DEFAULT-SEQ";
+            @config-SEQ {
+                description = "NAME";
+                firmware = "uboot";
+                loadables = "atf";
+                fdt = "fdt-SEQ";
+            };
+        };
+
+    This tells binman to create nodes config-1 and config-2, i.e. a config for
+    each of your two files.
+
+    Available substitutions for '@' nodes are:
+
+        SEQ    Sequence number of the generated fdt (1, 2, ...)
+        NAME   Name of the dtb as provided (i.e. without adding '.dtb')
+
+    Note that if no devicetree files are provided (with '-a of-list' as above)
+    then no nodes will be generated.
+
+    The 'default' property, if present, will be automatically set to the name
+    if of configuration whose devicetree matches the 'default-dt' entry
+    argument, e.g. with '-a default-dt=sun50i-a64-pine64-lts'.
+
+    Available substitutions for '@' property values are:
+
+        DEFAULT-SEQ  Sequence number of the default fdt,as provided by the
+                     'default-dt' entry argument
+
+    Properties (in the 'fit' node itself):
         fit,external-offset: Indicates that the contents of the FIT are external
             and provides the external offset. This is passsed to mkimage via
             the -E and -p flags.
@@ -55,15 +109,28 @@
         """
         Members:
             _fit: FIT file being built
-            _fit_content: dict:
+            _fit_sections: dict:
                 key: relative path to entry Node (from the base of the FIT)
-                value: List of Entry objects comprising the contents of this
+                value: Entry_section object comprising the contents of this
                     node
         """
         super().__init__(section, etype, node)
         self._fit = None
-        self._fit_content = defaultdict(list)
+        self._fit_sections = {}
         self._fit_props = {}
+        for pname, prop in self._node.props.items():
+            if pname.startswith('fit,'):
+                self._fit_props[pname] = prop
+
+        self._fdts = None
+        self._fit_list_prop = self._fit_props.get('fit,fdt-list')
+        if self._fit_list_prop:
+            fdts, = self.GetEntryArgsOrProps(
+                [EntryArg(self._fit_list_prop.value, str)])
+            if fdts is not None:
+                self._fdts = fdts.split()
+        self._fit_default_dt = self.GetEntryArgsOrProps([EntryArg('default-dt',
+                                                                  str)])[0]
 
     def ReadNode(self):
         self._ReadSubnodes()
@@ -84,22 +151,71 @@
                   image
             """
             for pname, prop in node.props.items():
-                if pname.startswith('fit,'):
-                    self._fit_props[pname] = prop
-                else:
+                if not pname.startswith('fit,'):
+                    if pname == 'default':
+                        val = prop.value
+                        # Handle the 'default' property
+                        if val.startswith('@'):
+                            if not self._fdts:
+                                continue
+                            if not self._fit_default_dt:
+                                self.Raise("Generated 'default' node requires default-dt entry argument")
+                            if self._fit_default_dt not in self._fdts:
+                                self.Raise("default-dt entry argument '%s' not found in fdt list: %s" %
+                                           (self._fit_default_dt,
+                                            ', '.join(self._fdts)))
+                            seq = self._fdts.index(self._fit_default_dt)
+                            val = val[1:].replace('DEFAULT-SEQ', str(seq + 1))
+                            fsw.property_string(pname, val)
+                            continue
                     fsw.property(pname, prop.bytes)
 
             rel_path = node.path[len(base_node.path):]
-            has_images = depth == 2 and rel_path.startswith('/images/')
+            in_images = rel_path.startswith('/images')
+            has_images = depth == 2 and in_images
+            if has_images:
+                # This node is a FIT subimage node (e.g. "/images/kernel")
+                # containing content nodes. We collect the subimage nodes and
+                # section entries for them here to merge the content subnodes
+                # together and put the merged contents in the subimage node's
+                # 'data' property later.
+                entry = Entry.Create(self.section, node, etype='section')
+                entry.ReadNode()
+                self._fit_sections[rel_path] = entry
+
             for subnode in node.subnodes:
                 if has_images and not (subnode.name.startswith('hash') or
                                        subnode.name.startswith('signature')):
-                    # This is a content node. We collect all of these together
-                    # and put them in the 'data' property. They do not appear
-                    # in the FIT.
-                    entry = Entry.Create(self.section, subnode)
-                    entry.ReadNode()
-                    self._fit_content[rel_path].append(entry)
+                    # This subnode is a content node not meant to appear in
+                    # the FIT (e.g. "/images/kernel/u-boot"), so don't call
+                    # fsw.add_node() or _AddNode() for it.
+                    pass
+                elif subnode.name.startswith('@'):
+                    if self._fdts:
+                        # Generate notes for each FDT
+                        for seq, fdt_fname in enumerate(self._fdts):
+                            node_name = subnode.name[1:].replace('SEQ',
+                                                                 str(seq + 1))
+                            fname = tools.GetInputFilename(fdt_fname + '.dtb')
+                            with fsw.add_node(node_name):
+                                for pname, prop in subnode.props.items():
+                                    val = prop.bytes.replace(
+                                        b'NAME', tools.ToBytes(fdt_fname))
+                                    val = val.replace(
+                                        b'SEQ', tools.ToBytes(str(seq + 1)))
+                                    fsw.property(pname, val)
+
+                                    # Add data for 'fdt' nodes (but not 'config')
+                                    if depth == 1 and in_images:
+                                        fsw.property('data',
+                                                     tools.ReadFile(fname))
+                    else:
+                        if self._fdts is None:
+                            if self._fit_list_prop:
+                                self.Raise("Generator node requires '%s' entry argument" %
+                                           self._fit_list_prop.value)
+                            else:
+                                self.Raise("Generator node requires 'fit,fdt-list' property")
                 else:
                     with fsw.add_node(subnode.name):
                         _AddNode(base_node, depth + 1, subnode)
@@ -123,9 +239,8 @@
         This adds the 'data' properties to the input ITB (Image-tree Binary)
         then runs mkimage to process it.
         """
+        # self._BuildInput() either returns bytes or raises an exception.
         data = self._BuildInput(self._fdt)
-        if data == False:
-            return False
         uniq = self.GetUniqueName()
         input_fname = tools.GetOutputFilename('%s.itb' % uniq)
         output_fname = tools.GetOutputFilename('%s.fit' % uniq)
@@ -150,15 +265,30 @@
         Returns:
             New fdt contents (bytes)
         """
-        for path, entries in self._fit_content.items():
+        for path, section in self._fit_sections.items():
             node = fdt.GetNode(path)
-            data = b''
-            for entry in entries:
-                if not entry.ObtainContents():
-                    return False
-                data += entry.GetData()
+            # Entry_section.ObtainContents() either returns True or
+            # raises an exception.
+            section.ObtainContents()
+            section.Pack(0)
+            data = section.GetData()
             node.AddData('data', data)
 
         fdt.Sync(auto_resize=True)
         data = fdt.GetContents()
         return data
+
+    def CheckMissing(self, missing_list):
+        """Check if any entries in this FIT have missing external blobs
+
+        If there are missing blobs, the entries are added to the list
+
+        Args:
+            missing_list: List of Entry objects to be added to
+        """
+        for path, section in self._fit_sections.items():
+            section.CheckMissing(missing_list)
+
+    def SetAllowMissing(self, allow_missing):
+        for section in self._fit_sections.values():
+            section.SetAllowMissing(allow_missing)

diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index 73c5553..515c97f 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py

@@ -35,7 +35,7 @@
             when writing out the map
 
     Properties:
-        _allow_missing: True if this section permits external blobs to be
+        allow_missing: True if this section permits external blobs to be
             missing their contents. The second will produce an image but of
             course it will not work.
 
@@ -54,8 +54,6 @@
         self._sort = False
         self._skip_at_start = None
         self._end_4gb = False
-        self._allow_missing = False
-        self.missing = False
 
     def ReadNode(self):
         """Read properties from the image node"""
@@ -83,7 +81,7 @@
 
     def _ReadEntries(self):
         for node in self._node.subnodes:
-            if node.name == 'hash':
+            if node.name.startswith('hash') or node.name.startswith('signature'):
                 continue
             entry = Entry.Create(self, node)
             entry.ReadNode()
@@ -152,7 +150,7 @@
         for entry in self._entries.values():
             data = entry.GetData()
             base = self.pad_before + (entry.offset or 0) - self._skip_at_start
-            pad = base - len(section_data)
+            pad = base - len(section_data) + (entry.pad_before or 0)
             if pad > 0:
                 section_data += tools.GetBytes(self._pad_byte, pad)
             section_data += data
@@ -549,18 +547,10 @@
         Args:
             allow_missing: True if allowed, False if not allowed
         """
-        self._allow_missing = allow_missing
+        self.allow_missing = allow_missing
         for entry in self._entries.values():
             entry.SetAllowMissing(allow_missing)
 
-    def GetAllowMissing(self):
-        """Get whether a section allows missing external blobs
-
-        Returns:
-            True if allowed, False if not allowed
-        """
-        return self._allow_missing
-
     def CheckMissing(self, missing_list):
         """Check if any entries in this section have missing external blobs
 

diff --git a/tools/binman/etype/u_boot_env.py b/tools/binman/etype/u_boot_env.py
new file mode 100644
index 0000000..1694c2a
--- /dev/null
+++ b/tools/binman/etype/u_boot_env.py

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+import struct
+import zlib
+
+from binman.etype.blob import Entry_blob
+from dtoc import fdt_util
+from patman import tools
+
+class Entry_u_boot_env(Entry_blob):
+    """An entry which contains a U-Boot environment
+
+    Properties / Entry arguments:
+        - filename: File containing the environment text, with each line in the
+            form var=value
+    """
+    def __init__(self, section, etype, node):
+        super().__init__(section, etype, node)
+
+    def ReadNode(self):
+        super().ReadNode()
+        if self.size is None:
+            self.Raise("'u-boot-env' entry must have a size property")
+        self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
+
+    def ReadBlobContents(self):
+        indata = tools.ReadFile(self._pathname)
+        data = b''
+        for line in indata.splitlines():
+            data += line + b'\0'
+        data += b'\0';
+        pad = self.size - len(data) - 5
+        if pad < 0:
+            self.Raise("'u-boot-env' entry too small to hold data (need %#x more bytes)" % -pad)
+        data += tools.GetBytes(self.fill_value, pad)
+        crc = zlib.crc32(data)
+        buf = struct.pack('<I', crc) + b'\x01' + data
+        self.SetContents(buf)
+        return True

diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 5f650b5..b771b9d 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py

@@ -74,6 +74,13 @@
 FSP_M_DATA            = b'fsp_m'
 FSP_S_DATA            = b'fsp_s'
 FSP_T_DATA            = b'fsp_t'
+ATF_BL31_DATA         = b'bl31'
+TEST_FDT1_DATA        = b'fdt1'
+TEST_FDT2_DATA        = b'test-fdt2'
+ENV_DATA              = b'var1=1\nvar2="2"'
+
+# Subdirectory of the input dir to use to put test FDTs
+TEST_FDT_SUBDIR       = 'fdts'
 
 # The expected size for the device tree in some tests
 EXTRACT_DTB_SIZE = 0x3c9
@@ -167,6 +174,15 @@
                         os.path.join(cls._indir, 'files'))
 
         TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
+        TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
+
+        # Add a few .dtb files for testing
+        TestFunctional._MakeInputFile('%s/test-fdt1.dtb' % TEST_FDT_SUBDIR,
+                                      TEST_FDT1_DATA)
+        TestFunctional._MakeInputFile('%s/test-fdt2.dtb' % TEST_FDT_SUBDIR,
+                                      TEST_FDT2_DATA)
+
+        TestFunctional._MakeInputFile('env.txt', ENV_DATA)
 
         # Travis-CI may have an old lz4
         cls.have_lz4 = True
@@ -285,7 +301,7 @@
 
     def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False,
                     entry_args=None, images=None, use_real_dtb=False,
-                    verbosity=None, allow_missing=False):
+                    verbosity=None, allow_missing=False, extra_indirs=None):
         """Run binman with a given test file
 
         Args:
@@ -298,6 +314,14 @@
                 key: arg name
                 value: value of that arg
             images: List of image names to build
+            use_real_dtb: True to use the test file as the contents of
+                the u-boot-dtb entry. Normally this is not needed and the
+                test contents (the U_BOOT_DTB_DATA string) can be used.
+                But in some test we need the real contents.
+            verbosity: Verbosity level to use (0-3, None=don't set it)
+            allow_missing: Set the '--allow-missing' flag so that missing
+                external binaries just produce a warning instead of an error
+            extra_indirs: Extra input directories to add using -I
         """
         args = []
         if debug:
@@ -324,6 +348,9 @@
         if images:
             for image in images:
                 args += ['-i', image]
+        if extra_indirs:
+            for indir in extra_indirs:
+                args += ['-I', indir]
         return self._DoBinman(*args)
 
     def _SetupDtb(self, fname, outfile='u-boot.dtb'):
@@ -357,6 +384,13 @@
         We still want the DTBs for SPL and TPL to be different though, since
         otherwise it is confusing to know which one we are looking at. So add
         an 'spl' or 'tpl' property to the top-level node.
+
+        Args:
+            dtb_data: dtb data to modify (this should be a value devicetree)
+            name: Name of a new property to add
+
+        Returns:
+            New dtb data with the property added
         """
         dtb = fdt.Fdt.FromData(dtb_data)
         dtb.Scan()
@@ -366,7 +400,8 @@
         return dtb.GetContents()
 
     def _DoReadFileDtb(self, fname, use_real_dtb=False, map=False,
-                       update_dtb=False, entry_args=None, reset_dtbs=True):
+                       update_dtb=False, entry_args=None, reset_dtbs=True,
+                       extra_indirs=None):
         """Run binman and return the resulting image
 
         This runs binman with a given test file and then reads the resulting
@@ -384,6 +419,13 @@
             map: True to output map files for the images
             update_dtb: Update the offset and size of each entry in the device
                 tree before packing it into the image
+            entry_args: Dict of entry args to supply to binman
+                key: arg name
+                value: value of that arg
+            reset_dtbs: With use_real_dtb the test dtb is overwritten by this
+                function. If reset_dtbs is True, then the original test dtb
+                is written back before this function finishes
+            extra_indirs: Extra input directories to add using -I
 
         Returns:
             Tuple:
@@ -407,7 +449,8 @@
 
         try:
             retcode = self._DoTestFile(fname, map=map, update_dtb=update_dtb,
-                    entry_args=entry_args, use_real_dtb=use_real_dtb)
+                    entry_args=entry_args, use_real_dtb=use_real_dtb,
+                    extra_indirs=extra_indirs)
             self.assertEqual(0, retcode)
             out_dtb_fname = tools.GetOutputFilename('u-boot.dtb.out')
 
@@ -1382,8 +1425,9 @@
         }
         with self.assertRaises(ValueError) as e:
             self._DoReadFileDtb('064_entry_args_required.dts')
-        self.assertIn("Node '/binman/_testing': Missing required "
-            'properties/entry args: test-str-arg, test-int-fdt, test-int-arg',
+        self.assertIn("Node '/binman/_testing': "
+            'Missing required properties/entry args: test-str-arg, '
+            'test-int-fdt, test-int-arg',
             str(e.exception))
 
     def testEntryArgsInvalidFormat(self):
@@ -1487,8 +1531,7 @@
         entry_args = {
             'cros-ec-rw-path': 'ecrw.bin',
         }
-        data, _, _, _ = self._DoReadFileDtb('068_blob_named_by_arg.dts',
-                                            entry_args=entry_args)
+        self._DoReadFileDtb('068_blob_named_by_arg.dts', entry_args=entry_args)
 
     def testFill(self):
         """Test for an fill entry type"""
@@ -3467,7 +3510,7 @@
         self.assertEqual(len(U_BOOT_SPL_DTB_DATA), int(data_sizes[1].split()[0]))
 
     def testFitExternal(self):
-        """Test an image with an FIT"""
+        """Test an image with an FIT with external images"""
         data = self._DoReadFile('162_fit_external.dts')
         fit_data = data[len(U_BOOT_DATA):-2]  # _testing is 2 bytes
 
@@ -3477,5 +3520,231 @@
         fnode = dtb.GetNode('/images/kernel')
         self.assertNotIn('data', fnode.props)
 
+    def testSectionIgnoreHashSignature(self):
+        """Test that sections ignore hash, signature nodes for its data"""
+        data = self._DoReadFile('165_section_ignore_hash_signature.dts')
+        expected = (U_BOOT_DATA + U_BOOT_DATA)
+        self.assertEqual(expected, data)
+
+    def testPadInSections(self):
+        """Test pad-before, pad-after for entries in sections"""
+        data = self._DoReadFile('166_pad_in_sections.dts')
+        expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
+                    U_BOOT_DATA + tools.GetBytes(ord('!'), 6) +
+                    U_BOOT_DATA)
+        self.assertEqual(expected, data)
+
+    def testFitImageSubentryAlignment(self):
+        """Test relative alignability of FIT image subentries"""
+        entry_args = {
+            'test-id': TEXT_DATA,
+        }
+        data, _, _, _ = self._DoReadFileDtb('167_fit_image_subentry_alignment.dts',
+                                            entry_args=entry_args)
+        dtb = fdt.Fdt.FromData(data)
+        dtb.Scan()
+
+        node = dtb.GetNode('/images/kernel')
+        data = dtb.GetProps(node)["data"].bytes
+        align_pad = 0x10 - (len(U_BOOT_SPL_DATA) % 0x10)
+        expected = (tools.GetBytes(0, 0x20) + U_BOOT_SPL_DATA +
+                    tools.GetBytes(0, align_pad) + U_BOOT_DATA)
+        self.assertEqual(expected, data)
+
+        node = dtb.GetNode('/images/fdt-1')
+        data = dtb.GetProps(node)["data"].bytes
+        expected = (U_BOOT_SPL_DTB_DATA + tools.GetBytes(0, 20) +
+                    tools.ToBytes(TEXT_DATA) + tools.GetBytes(0, 30) +
+                    U_BOOT_DTB_DATA)
+        self.assertEqual(expected, data)
+
+    def testFitExtblobMissingOk(self):
+        """Test a FIT with a missing external blob that is allowed"""
+        with test_util.capture_sys_output() as (stdout, stderr):
+            self._DoTestFile('168_fit_missing_blob.dts',
+                             allow_missing=True)
+        err = stderr.getvalue()
+        self.assertRegex(err, "Image 'main-section'.*missing.*: atf-bl31")
+
+    def testBlobNamedByArgMissing(self):
+        """Test handling of a missing entry arg"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFile('068_blob_named_by_arg.dts')
+        self.assertIn("Missing required properties/entry args: cros-ec-rw-path",
+                      str(e.exception))
+
+    def testPackBl31(self):
+        """Test that an image with an ATF BL31 binary can be created"""
+        data = self._DoReadFile('169_atf_bl31.dts')
+        self.assertEqual(ATF_BL31_DATA, data[:len(ATF_BL31_DATA)])
+
+    def testFitFdt(self):
+        """Test an image with an FIT with multiple FDT images"""
+        def _CheckFdt(seq, expected_data):
+            """Check the FDT nodes
+
+            Args:
+                seq: Sequence number to check (0 or 1)
+                expected_data: Expected contents of 'data' property
+            """
+            name = 'fdt-%d' % seq
+            fnode = dtb.GetNode('/images/%s' % name)
+            self.assertIsNotNone(fnode)
+            self.assertEqual({'description','type', 'compression', 'data'},
+                             set(fnode.props.keys()))
+            self.assertEqual(expected_data, fnode.props['data'].bytes)
+            self.assertEqual('fdt-test-fdt%d.dtb' % seq,
+                             fnode.props['description'].value)
+
+        def _CheckConfig(seq, expected_data):
+            """Check the configuration nodes
+
+            Args:
+                seq: Sequence number to check (0 or 1)
+                expected_data: Expected contents of 'data' property
+            """
+            cnode = dtb.GetNode('/configurations')
+            self.assertIn('default', cnode.props)
+            self.assertEqual('config-2', cnode.props['default'].value)
+
+            name = 'config-%d' % seq
+            fnode = dtb.GetNode('/configurations/%s' % name)
+            self.assertIsNotNone(fnode)
+            self.assertEqual({'description','firmware', 'loadables', 'fdt'},
+                             set(fnode.props.keys()))
+            self.assertEqual('conf-test-fdt%d.dtb' % seq,
+                             fnode.props['description'].value)
+            self.assertEqual('fdt-%d' % seq, fnode.props['fdt'].value)
+
+        entry_args = {
+            'of-list': 'test-fdt1 test-fdt2',
+            'default-dt': 'test-fdt2',
+        }
+        data = self._DoReadFileDtb(
+            '172_fit_fdt.dts',
+            entry_args=entry_args,
+            extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
+        self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
+        fit_data = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)]
+
+        dtb = fdt.Fdt.FromData(fit_data)
+        dtb.Scan()
+        fnode = dtb.GetNode('/images/kernel')
+        self.assertIn('data', fnode.props)
+
+        # Check all the properties in fdt-1 and fdt-2
+        _CheckFdt(1, TEST_FDT1_DATA)
+        _CheckFdt(2, TEST_FDT2_DATA)
+
+        # Check configurations
+        _CheckConfig(1, TEST_FDT1_DATA)
+        _CheckConfig(2, TEST_FDT2_DATA)
+
+    def testFitFdtMissingList(self):
+        """Test handling of a missing 'of-list' entry arg"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFile('172_fit_fdt.dts')
+        self.assertIn("Generator node requires 'of-list' entry argument",
+                      str(e.exception))
+
+    def testFitFdtEmptyList(self):
+        """Test handling of an empty 'of-list' entry arg"""
+        entry_args = {
+            'of-list': '',
+        }
+        data = self._DoReadFileDtb('170_fit_fdt.dts', entry_args=entry_args)[0]
+
+    def testFitFdtMissingProp(self):
+        """Test handling of a missing 'fit,fdt-list' property"""
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFile('171_fit_fdt_missing_prop.dts')
+        self.assertIn("Generator node requires 'fit,fdt-list' property",
+                      str(e.exception))
+
+    def testFitFdtEmptyList(self):
+        """Test handling of an empty 'of-list' entry arg"""
+        entry_args = {
+            'of-list': '',
+        }
+        data = self._DoReadFileDtb('172_fit_fdt.dts', entry_args=entry_args)[0]
+
+    def testFitFdtMissing(self):
+        """Test handling of a missing 'default-dt' entry arg"""
+        entry_args = {
+            'of-list': 'test-fdt1 test-fdt2',
+        }
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb(
+                '172_fit_fdt.dts',
+                entry_args=entry_args,
+                extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
+        self.assertIn("Generated 'default' node requires default-dt entry argument",
+                      str(e.exception))
+
+    def testFitFdtNotInList(self):
+        """Test handling of a default-dt that is not in the of-list"""
+        entry_args = {
+            'of-list': 'test-fdt1 test-fdt2',
+            'default-dt': 'test-fdt3',
+        }
+        with self.assertRaises(ValueError) as e:
+            self._DoReadFileDtb(
+                '172_fit_fdt.dts',
+                entry_args=entry_args,
+                extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
+        self.assertIn("default-dt entry argument 'test-fdt3' not found in fdt list: test-fdt1, test-fdt2",
+                      str(e.exception))
+
+    def testFitExtblobMissingHelp(self):
+        """Test display of help messages when an external blob is missing"""
+        control.missing_blob_help = control._ReadMissingBlobHelp()
+        control.missing_blob_help['wibble'] = 'Wibble test'
+        control.missing_blob_help['another'] = 'Another test'
+        with test_util.capture_sys_output() as (stdout, stderr):
+            self._DoTestFile('168_fit_missing_blob.dts',
+                             allow_missing=True)
+        err = stderr.getvalue()
+
+        # We can get the tag from the name, the type or the missing-msg
+        # property. Check all three.
+        self.assertIn('You may need to build ARM Trusted', err)
+        self.assertIn('Wibble test', err)
+        self.assertIn('Another test', err)
+
+    def testMissingBlob(self):
+        """Test handling of a blob containing a missing file"""
+        with self.assertRaises(ValueError) as e:
+            self._DoTestFile('173_missing_blob.dts', allow_missing=True)
+        self.assertIn("Filename 'missing' not found in input path",
+                      str(e.exception))
+
+    def testEnvironment(self):
+        """Test adding a U-Boot environment"""
+        data = self._DoReadFile('174_env.dts')
+        self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)])
+        self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
+        env = data[len(U_BOOT_DATA):-len(U_BOOT_NODTB_DATA)]
+        self.assertEqual(b'\x1b\x97\x22\x7c\x01var1=1\0var2="2"\0\0\xff\xff',
+                         env)
+
+    def testEnvironmentNoSize(self):
+        """Test that a missing 'size' property is detected"""
+        with self.assertRaises(ValueError) as e:
+            data = self._DoTestFile('175_env_no_size.dts')
+        self.assertIn("'u-boot-env' entry must have a size property",
+                      str(e.exception))
+
+    def testEnvironmentTooSmall(self):
+        """Test handling of an environment that does not fit"""
+        with self.assertRaises(ValueError) as e:
+            data = self._DoTestFile('176_env_too_small.dts')
+
+        # checksum, start byte, environment with \0 terminator, final \0
+        need = 4 + 1 + len(ENV_DATA) + 1 + 1
+        short = need - 0x8
+        self.assertIn("too small to hold data (need %#x more bytes)" % short,
+                      str(e.exception))
+
+
 if __name__ == "__main__":
     unittest.main()

diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help
new file mode 100644
index 0000000..7cf1c34
--- /dev/null
+++ b/tools/binman/missing-blob-help

@@ -0,0 +1,15 @@
+# This file contains help messages for missing external blobs. Each message has
+# a tag (MUST be just lower-case text, digits and hyphens) starting in column 1,
+# followed by a colon (:) to indicate its start. The message can include any
+# number of lines, including blank lines.
+#
+# When looking for a tag, Binman uses the value of 'missing-msg' for the entry,
+# the entry name or the entry type, in that order
+
+atf-bl31:
+See the documentation for your board. You may need to build ARM Trusted
+Firmware and build with BL31=/path/to/bl31.bin
+
+atf-bl31-sunxi:
+Please read the section on ARM Trusted Firmware (ATF) in
+board/sunxi/README.sunxi64

diff --git a/tools/binman/test/165_section_ignore_hash_signature.dts b/tools/binman/test/165_section_ignore_hash_signature.dts
new file mode 100644
index 0000000..8adbe25
--- /dev/null
+++ b/tools/binman/test/165_section_ignore_hash_signature.dts

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		section@0 {
+			u-boot {
+			};
+			hash {
+				algo = "sha256";
+			};
+			signature {
+				algo = "sha256,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+		section@1 {
+			u-boot {
+			};
+			hash-1 {
+				algo = "sha1";
+			};
+			hash-2 {
+				algo = "sha256";
+			};
+			signature-1 {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+			signature-2 {
+				algo = "sha256,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+	};
+};

diff --git a/tools/binman/test/166_pad_in_sections.dts b/tools/binman/test/166_pad_in_sections.dts
new file mode 100644
index 0000000..f2b327f
--- /dev/null
+++ b/tools/binman/test/166_pad_in_sections.dts

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		pad-byte = <0x26>;
+		section {
+			pad-byte = <0x21>;
+
+			before {
+				type = "u-boot";
+			};
+			u-boot {
+				pad-before = <12>;
+				pad-after = <6>;
+			};
+			after {
+				type = "u-boot";
+			};
+		};
+	};
+};

diff --git a/tools/binman/test/167_fit_image_subentry_alignment.dts b/tools/binman/test/167_fit_image_subentry_alignment.dts
new file mode 100644
index 0000000..360cac5
--- /dev/null
+++ b/tools/binman/test/167_fit_image_subentry_alignment.dts

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		fit {
+			description = "test-desc";
+			#address-cells = <1>;
+
+			images {
+				kernel {
+					description = "Offset-Align Test";
+					type = "kernel";
+					arch = "arm64";
+					os = "linux";
+					compression = "none";
+					load = <00000000>;
+					entry = <00000000>;
+					u-boot-spl {
+						offset = <0x20>;
+					};
+					u-boot {
+						align = <0x10>;
+					};
+				};
+				fdt-1 {
+					description = "Pad-Before-After Test";
+					type = "flat_dt";
+					arch = "arm64";
+					compression = "none";
+					u-boot-spl-dtb {
+					};
+					text {
+						text-label = "test-id";
+						pad-before = <20>;
+						pad-after = <30>;
+					};
+					u-boot-dtb {
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-1";
+				conf-1 {
+					description = "Kernel with FDT blob";
+					kernel = "kernel";
+					fdt = "fdt-1";
+				};
+			};
+		};
+	};
+};

diff --git a/tools/binman/test/168_fit_missing_blob.dts b/tools/binman/test/168_fit_missing_blob.dts
new file mode 100644
index 0000000..15f6cc0
--- /dev/null
+++ b/tools/binman/test/168_fit_missing_blob.dts

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		fit {
+			description = "test-desc";
+			#address-cells = <1>;
+			fit,fdt-list = "of-list";
+
+			images {
+				kernel {
+					description = "ATF BL31";
+					type = "kernel";
+					arch = "ppc";
+					os = "linux";
+					compression = "gzip";
+					load = <00000000>;
+					entry = <00000000>;
+					hash-1 {
+						algo = "crc32";
+					};
+					hash-2 {
+						algo = "sha1";
+					};
+					atf-bl31 {
+						filename = "missing";
+					};
+					cros-ec-rw {
+						type = "atf-bl31";
+						missing-msg = "wibble";
+					};
+					another {
+						type = "atf-bl31";
+					};
+				};
+			};
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/169_atf_bl31.dts b/tools/binman/test/169_atf_bl31.dts
new file mode 100644
index 0000000..2b7547d
--- /dev/null
+++ b/tools/binman/test/169_atf_bl31.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		size = <16>;
+
+		atf-bl31 {
+			filename = "bl31.bin";
+		};
+	};
+};

diff --git a/tools/binman/test/171_fit_fdt_missing_prop.dts b/tools/binman/test/171_fit_fdt_missing_prop.dts
new file mode 100644
index 0000000..c361347
--- /dev/null
+++ b/tools/binman/test/171_fit_fdt_missing_prop.dts

@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		fit {
+			description = "test-desc";
+			#address-cells = <1>;
+
+			images {
+				kernel {
+					description = "Vanilla Linux kernel";
+					type = "kernel";
+					arch = "ppc";
+					os = "linux";
+					compression = "gzip";
+					load = <00000000>;
+					entry = <00000000>;
+					hash-1 {
+						algo = "crc32";
+					};
+					hash-2 {
+						algo = "sha1";
+					};
+					u-boot {
+					};
+				};
+				@fdt-SEQ {
+					description = "fdt-NAME.dtb";
+					type = "flat_dt";
+					compression = "none";
+				};
+			};
+
+			configurations {
+				default = "config-1";
+				@config-SEQ {
+					description = "conf-NAME.dtb";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt-SEQ";
+				};
+			};
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/172_fit_fdt.dts b/tools/binman/test/172_fit_fdt.dts
new file mode 100644
index 0000000..99d710c
--- /dev/null
+++ b/tools/binman/test/172_fit_fdt.dts

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		fit {
+			description = "test-desc";
+			#address-cells = <1>;
+			fit,fdt-list = "of-list";
+
+			images {
+				kernel {
+					description = "Vanilla Linux kernel";
+					type = "kernel";
+					arch = "ppc";
+					os = "linux";
+					compression = "gzip";
+					load = <00000000>;
+					entry = <00000000>;
+					hash-1 {
+						algo = "crc32";
+					};
+					hash-2 {
+						algo = "sha1";
+					};
+					u-boot {
+					};
+				};
+				@fdt-SEQ {
+					description = "fdt-NAME.dtb";
+					type = "flat_dt";
+					compression = "none";
+				};
+			};
+
+			configurations {
+				default = "@config-DEFAULT-SEQ";
+				@config-SEQ {
+					description = "conf-NAME.dtb";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt-SEQ";
+				};
+			};
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/173_missing_blob.dts b/tools/binman/test/173_missing_blob.dts
new file mode 100644
index 0000000..ffb655a
--- /dev/null
+++ b/tools/binman/test/173_missing_blob.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		blob {
+			filename = "missing";
+		};
+	};
+};

diff --git a/tools/binman/test/174_env.dts b/tools/binman/test/174_env.dts
new file mode 100644
index 0000000..d1393d2
--- /dev/null
+++ b/tools/binman/test/174_env.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		u-boot-env {
+			filename = "env.txt";
+			size = <0x18>;
+			fill-byte = [ff];
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/175_env_no_size.dts b/tools/binman/test/175_env_no_size.dts
new file mode 100644
index 0000000..267acd1
--- /dev/null
+++ b/tools/binman/test/175_env_no_size.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		u-boot-env {
+			filename = "env.txt";
+			fill-byte = [ff];
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/176_env_too_small.dts b/tools/binman/test/176_env_too_small.dts
new file mode 100644
index 0000000..2db8d05
--- /dev/null
+++ b/tools/binman/test/176_env_too_small.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		u-boot {
+		};
+		u-boot-env {
+			filename = "env.txt";
+			size = <0x8>;
+			fill-byte = [ff];
+		};
+		u-boot-nodtb {
+		};
+	};
+};

diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile
index e4fd97b..0b19b7d 100644
--- a/tools/binman/test/Makefile
+++ b/tools/binman/test/Makefile

@@ -7,6 +7,19 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+HOSTARCH := $(shell uname -m | sed -e s/i.86/x86/ )
+ifeq ($(findstring $(HOSTARCH),"x86" "x86_64"),)
+ifeq ($(findstring $(MAKECMDGOALS),"help" "clean"),)
+ifndef CROSS_COMPILE
+$(error Binman tests need to compile to x86, but the CPU arch of your \
+	machine is $(HOSTARCH). Set CROSS_COMPILE to a suitable cross compiler)
+endif
+endif
+endif
+
+CC		= $(CROSS_COMPILE)gcc
+OBJCOPY		= $(CROSS_COMPILE)objcopy
+
 VPATH := $(SRC)
 CFLAGS := -march=i386 -m32 -nostdlib -I $(SRC)../../../include \
 	-Wl,--no-dynamic-linker
@@ -32,7 +45,7 @@
 bss_data: bss_data.c
 
 u_boot_binman_syms.bin: u_boot_binman_syms
-	objcopy -O binary $< -R .note.gnu.build-id $@
+	$(OBJCOPY) -O binary $< -R .note.gnu.build-id $@
 
 u_boot_binman_syms: CFLAGS += $(LDS_BINMAN)
 u_boot_binman_syms: u_boot_binman_syms.c

diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index dbb75b3..c939468 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py

@@ -1541,41 +1541,73 @@
         """Prepare the working directory for a thread.
 
         This clones or fetches the repo into the thread's work directory.
+        Optionally, it can create a linked working tree of the repo in the
+        thread's work directory instead.
 
         Args:
             thread_num: Thread number (0, 1, ...)
-            setup_git: True to set up a git repo clone
+            setup_git:
+               'clone' to set up a git clone
+               'worktree' to set up a git worktree
         """
         thread_dir = self.GetThreadDir(thread_num)
         builderthread.Mkdir(thread_dir)
         git_dir = os.path.join(thread_dir, '.git')
 
-        # Clone the repo if it doesn't already exist
-        # TODO(sjg@chromium): Perhaps some git hackery to symlink instead, so
-        # we have a private index but uses the origin repo's contents?
+        # Create a worktree or a git repo clone for this thread if it
+        # doesn't already exist
         if setup_git and self.git_dir:
             src_dir = os.path.abspath(self.git_dir)
-            if os.path.exists(git_dir):
+            if os.path.isdir(git_dir):
+                # This is a clone of the src_dir repo, we can keep using
+                # it but need to fetch from src_dir.
                 Print('\rFetching repo for thread %d' % thread_num,
                       newline=False)
                 gitutil.Fetch(git_dir, thread_dir)
                 terminal.PrintClear()
-            else:
+            elif os.path.isfile(git_dir):
+                # This is a worktree of the src_dir repo, we don't need to
+                # create it again or update it in any way.
+                pass
+            elif os.path.exists(git_dir):
+                # Don't know what could trigger this, but we probably
+                # can't create a git worktree/clone here.
+                raise ValueError('Git dir %s exists, but is not a file '
+                                 'or a directory.' % git_dir)
+            elif setup_git == 'worktree':
+                Print('\rChecking out worktree for thread %d' % thread_num,
+                      newline=False)
+                gitutil.AddWorktree(src_dir, thread_dir)
+                terminal.PrintClear()
+            elif setup_git == 'clone' or setup_git == True:
                 Print('\rCloning repo for thread %d' % thread_num,
                       newline=False)
                 gitutil.Clone(src_dir, thread_dir)
                 terminal.PrintClear()
+            else:
+                raise ValueError("Can't setup git repo with %s." % setup_git)
 
     def _PrepareWorkingSpace(self, max_threads, setup_git):
         """Prepare the working directory for use.
 
-        Set up the git repo for each thread.
+        Set up the git repo for each thread. Creates a linked working tree
+        if git-worktree is available, or clones the repo if it isn't.
 
         Args:
             max_threads: Maximum number of threads we expect to need.
-            setup_git: True to set up a git repo clone
+            setup_git: True to set up a git worktree or a git clone
         """
         builderthread.Mkdir(self._working_dir)
+        if setup_git and self.git_dir:
+            src_dir = os.path.abspath(self.git_dir)
+            if gitutil.CheckWorktreeIsAvailable(src_dir):
+                setup_git = 'worktree'
+                # If we previously added a worktree but the directory for it
+                # got deleted, we need to prune its files from the repo so
+                # that we can check out another in its place.
+                gitutil.PruneWorktrees(src_dir)
+            else:
+                setup_git = 'clone'
         for thread in range(max_threads):
             self._PrepareThread(thread, setup_git)
 

diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 418677f..3dd2e6e 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py

@@ -319,6 +319,8 @@
             return command.CommandResult(return_code=0)
         elif sub_cmd == 'checkout':
             return command.CommandResult(return_code=0)
+        elif sub_cmd == 'worktree':
+            return command.CommandResult(return_code=0)
 
         # Not handled, so abort
         print('git', git_args, sub_cmd, args)

diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 3eaba075..1a259d5 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py

@@ -9,9 +9,6 @@
 import time
 import unittest
 
-# Bring in the patman libraries
-our_path = os.path.dirname(os.path.realpath(__file__))
-
 from buildman import board
 from buildman import bsettings
 from buildman import builder

diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
index b040793..37e96b9 100644
--- a/tools/dtoc/fdt_util.py
+++ b/tools/dtoc/fdt_util.py

@@ -68,22 +68,23 @@
 
     search_paths = [os.path.join(os.getcwd(), 'include')]
     root, _ = os.path.splitext(fname)
-    args = ['-E', '-P', '-x', 'assembler-with-cpp', '-D__ASSEMBLY__']
+    cc, args = tools.GetTargetCompileTool('cc')
+    args += ['-E', '-P', '-x', 'assembler-with-cpp', '-D__ASSEMBLY__']
     args += ['-Ulinux']
     for path in search_paths:
         args.extend(['-I', path])
     args += ['-o', dts_input, fname]
-    command.Run('cc', *args)
+    command.Run(cc, *args)
 
     # If we don't have a directory, put it in the tools tempdir
     search_list = []
     for path in search_paths:
         search_list.extend(['-i', path])
-    args = ['-I', 'dts', '-o', dtb_output, '-O', 'dtb',
+    dtc, args = tools.GetTargetCompileTool('dtc')
+    args += ['-I', 'dts', '-o', dtb_output, '-O', 'dtb',
             '-W', 'no-unit_address_vs_reg']
     args.extend(search_list)
     args.append(dts_input)
-    dtc = os.environ.get('DTC') or 'dtc'
     command.Run(dtc, *args, capture_stderr=capture_stderr)
     return dtb_output
 

diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 192d8e6..27a0a9f 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py

@@ -259,6 +259,48 @@
     if result.return_code != 0:
         raise OSError('git fetch: %s' % result.stderr)
 
+def CheckWorktreeIsAvailable(git_dir):
+    """Check if git-worktree functionality is available
+
+    Args:
+        git_dir: The repository to test in
+
+    Returns:
+        True if git-worktree commands will work, False otherwise.
+    """
+    pipe = ['git', '--git-dir', git_dir, 'worktree', 'list']
+    result = command.RunPipe([pipe], capture=True, capture_stderr=True,
+                             raise_on_error=False)
+    return result.return_code == 0
+
+def AddWorktree(git_dir, output_dir, commit_hash=None):
+    """Create and checkout a new git worktree for this build
+
+    Args:
+        git_dir: The repository to checkout the worktree from
+        output_dir: Path for the new worktree
+        commit_hash: Commit hash to checkout
+    """
+    # We need to pass --detach to avoid creating a new branch
+    pipe = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
+    if commit_hash:
+        pipe.append(commit_hash)
+    result = command.RunPipe([pipe], capture=True, cwd=output_dir,
+                             capture_stderr=True)
+    if result.return_code != 0:
+        raise OSError('git worktree add: %s' % result.stderr)
+
+def PruneWorktrees(git_dir):
+    """Remove administrative files for deleted worktrees
+
+    Args:
+        git_dir: The repository whose deleted worktrees should be pruned
+    """
+    pipe = ['git', '--git-dir', git_dir, 'worktree', 'prune']
+    result = command.RunPipe([pipe], capture=True, capture_stderr=True)
+    if result.return_code != 0:
+        raise OSError('git worktree prune: %s' % result.stderr)
+
 def CreatePatches(branch, start, count, ignore_binary, series):
     """Create a series of patches from the top of the current branch.
 

diff --git a/tools/patman/tools.py b/tools/patman/tools.py
index d41115a..bbb157d 100644
--- a/tools/patman/tools.py
+++ b/tools/patman/tools.py

@@ -188,6 +188,120 @@
             return True
     return False
 
+def GetHostCompileTool(name):
+    """Get the host-specific version for a compile tool
+
+    This checks the environment variables that specify which version of
+    the tool should be used (e.g. ${HOSTCC}).
+
+    The following table lists the host-specific versions of the tools
+    this function resolves to:
+
+        Compile Tool  | Host version
+        --------------+----------------
+        as            |  ${HOSTAS}
+        ld            |  ${HOSTLD}
+        cc            |  ${HOSTCC}
+        cpp           |  ${HOSTCPP}
+        c++           |  ${HOSTCXX}
+        ar            |  ${HOSTAR}
+        nm            |  ${HOSTNM}
+        ldr           |  ${HOSTLDR}
+        strip         |  ${HOSTSTRIP}
+        objcopy       |  ${HOSTOBJCOPY}
+        objdump       |  ${HOSTOBJDUMP}
+        dtc           |  ${HOSTDTC}
+
+    Args:
+        name: Command name to run
+
+    Returns:
+        host_name: Exact command name to run instead
+        extra_args: List of extra arguments to pass
+    """
+    host_name = None
+    extra_args = []
+    if name in ('as', 'ld', 'cc', 'cpp', 'ar', 'nm', 'ldr', 'strip',
+                'objcopy', 'objdump', 'dtc'):
+        host_name, *host_args = env.get('HOST' + name.upper(), '').split(' ')
+    elif name == 'c++':
+        host_name, *host_args = env.get('HOSTCXX', '').split(' ')
+
+    if host_name:
+        return host_name, extra_args
+    return name, []
+
+def GetTargetCompileTool(name, cross_compile=None):
+    """Get the target-specific version for a compile tool
+
+    This first checks the environment variables that specify which
+    version of the tool should be used (e.g. ${CC}). If those aren't
+    specified, it checks the CROSS_COMPILE variable as a prefix for the
+    tool with some substitutions (e.g. "${CROSS_COMPILE}gcc" for cc).
+
+    The following table lists the target-specific versions of the tools
+    this function resolves to:
+
+        Compile Tool  | First choice   | Second choice
+        --------------+----------------+----------------------------
+        as            |  ${AS}         | ${CROSS_COMPILE}as
+        ld            |  ${LD}         | ${CROSS_COMPILE}ld.bfd
+                      |                |   or ${CROSS_COMPILE}ld
+        cc            |  ${CC}         | ${CROSS_COMPILE}gcc
+        cpp           |  ${CPP}        | ${CROSS_COMPILE}gcc -E
+        c++           |  ${CXX}        | ${CROSS_COMPILE}g++
+        ar            |  ${AR}         | ${CROSS_COMPILE}ar
+        nm            |  ${NM}         | ${CROSS_COMPILE}nm
+        ldr           |  ${LDR}        | ${CROSS_COMPILE}ldr
+        strip         |  ${STRIP}      | ${CROSS_COMPILE}strip
+        objcopy       |  ${OBJCOPY}    | ${CROSS_COMPILE}objcopy
+        objdump       |  ${OBJDUMP}    | ${CROSS_COMPILE}objdump
+        dtc           |  ${DTC}        | (no CROSS_COMPILE version)
+
+    Args:
+        name: Command name to run
+
+    Returns:
+        target_name: Exact command name to run instead
+        extra_args: List of extra arguments to pass
+    """
+    env = dict(os.environ)
+
+    target_name = None
+    extra_args = []
+    if name in ('as', 'ld', 'cc', 'cpp', 'ar', 'nm', 'ldr', 'strip',
+                'objcopy', 'objdump', 'dtc'):
+        target_name, *extra_args = env.get(name.upper(), '').split(' ')
+    elif name == 'c++':
+        target_name, *extra_args = env.get('CXX', '').split(' ')
+
+    if target_name:
+        return target_name, extra_args
+
+    if cross_compile is None:
+        cross_compile = env.get('CROSS_COMPILE', '')
+    if not cross_compile:
+        return name, []
+
+    if name in ('as', 'ar', 'nm', 'ldr', 'strip', 'objcopy', 'objdump'):
+        target_name = cross_compile + name
+    elif name == 'ld':
+        try:
+            if Run(cross_compile + 'ld.bfd', '-v'):
+                target_name = cross_compile + 'ld.bfd'
+        except:
+            target_name = cross_compile + 'ld'
+    elif name == 'cc':
+        target_name = cross_compile + 'gcc'
+    elif name == 'cpp':
+        target_name = cross_compile + 'gcc'
+        extra_args = ['-E']
+    elif name == 'c++':
+        target_name = cross_compile + 'g++'
+    else:
+        target_name = name
+    return target_name, extra_args
+
 def Run(name, *args, **kwargs):
     """Run a tool with some arguments
 
@@ -198,16 +312,27 @@
     Args:
         name: Command name to run
         args: Arguments to the tool
+        for_host: True to resolve the command to the version for the host
+        for_target: False to run the command as-is, without resolving it
+                   to the version for the compile target
 
     Returns:
         CommandResult object
     """
     try:
         binary = kwargs.get('binary')
+        for_host = kwargs.get('for_host', False)
+        for_target = kwargs.get('for_target', not for_host)
         env = None
         if tool_search_paths:
             env = dict(os.environ)
             env['PATH'] = ':'.join(tool_search_paths) + ':' + env['PATH']
+        if for_target:
+            name, extra_args = GetTargetCompileTool(name)
+            args = tuple(extra_args) + args
+        elif for_host:
+            name, extra_args = GetHostCompileTool(name)
+            args = tuple(extra_args) + args
         all_args = (name,) + args
         result = command.RunPipe([all_args], capture=True, capture_stderr=True,
                                  env=env, raise_on_error=False, binary=binary)

diff --git a/tools/rmboard.py b/tools/rmboard.py
index 06c3562..de68563 100755
--- a/tools/rmboard.py
+++ b/tools/rmboard.py

@@ -28,9 +28,6 @@
 import re
 import sys
 
-# Bring in the patman libraries
-our_path = os.path.dirname(os.path.realpath(__file__))
-
 from patman import command
 
 def rm_kconfig_include(path):
commit	2a8bc03c860f913f8adf9bda8279ee9b718fc786	[log] [tgz]
author	Tom Rini <trini@konsulko.com>	Mon Oct 05 10:54:27 2020 -0400
committer	Tom Rini <trini@konsulko.com>	Mon Oct 05 10:54:27 2020 -0400
tree	24fcdb0737bea1d87c0a36f7eb371017af83e5c2
parent	8ac4a898eb101112d8703cb8f706ff47f637c38f [diff]
parent	929f5cc1859dd679a6d8c5044760198c3e31fda2 [diff]