diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
index 1024a41..00dc180 100644
--- a/board/prodrive/alpr/Makefile
+++ b/board/prodrive/alpr/Makefile
@@ -25,7 +25,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o fpga.o nand.o
+COBJS	= $(BOARD).o fpga.o nand.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
@@ -33,7 +33,7 @@
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index e8435bf..2389561 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 #include <ppc4xx_enet.h>
+#include <miiphy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,24 +34,14 @@
 
 int board_early_init_f (void)
 {
-	unsigned long mfr;
-
-	/*-------------------------------------------------------------------------+
-	  | Initialize EBC CONFIG
-	  +-------------------------------------------------------------------------*/
-#if 0
-	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
-	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
-	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
-	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
-	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#else
+	/*-------------------------------------------------------------------------
+	 * Initialize EBC CONFIG
+	 *-------------------------------------------------------------------------*/
 	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
 	      EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
 	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
 	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
 	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#endif
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -58,8 +49,8 @@
 	mtdcr (uic0sr, 0xffffffff);	/* clear all */
 	mtdcr (uic0er, 0x00000000);	/* disable all */
 	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0pr, 0xfffffe03);	/* per manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per manual */
 	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic0sr, 0xffffffff);	/* clear all */
 
@@ -85,12 +76,57 @@
 	mtdcr (uicb0pr, 0xfc000000); /* */
 	mtdcr (uicb0tr, 0x00000000); /* */
 	mtdcr (uicb0vr, 0x00000001); /* */
-	mfsdr (sdr_mfr, mfr);
-	mfr &= ~SDR0_MFR_ECS_MASK;
+
+	/* Setup GPIO/IRQ multiplexing */
+	mtsdr(sdr_pfc0, 0x01a03e00);
 
 	return 0;
 }
 
+int last_stage_init(void)
+{
+	unsigned short reg;
+
+	/*
+	 * Configure LED's of both Marvell 88E1111 PHY's
+	 *
+	 * This has to be done after the 4xx ethernet driver is loaded,
+	 * so "last_stage_init()" is the right place.
+	 */
+	miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+	miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
+
+	return 0;
+}
+
+static int board_rev(void)
+{
+	int rev;
+	u32 pfc0;
+
+	/* Setup GPIO14 & 15 as GPIO */
+	mfsdr(sdr_pfc0, pfc0);
+	pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
+	mtsdr(sdr_pfc0, pfc0);
+
+	/* Setup as input */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
+
+	rev = (in32(GPIO0_IR) >> 16) & 0x3;
+
+	/* Setup GPIO14 & 15 as non GPIO again */
+	mfsdr(sdr_pfc0, pfc0);
+	pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
+	mtsdr(sdr_pfc0, pfc0);
+
+	return rev;
+}
+
 int checkboard (void)
 {
 	char *s = getenv ("serial#");
@@ -100,7 +136,7 @@
 		puts (", serial# ");
 		puts (s);
 	}
-	putc ('\n');
+	printf(" (Rev. %d)\n", board_rev());
 
 	return (0);
 }
@@ -224,10 +260,26 @@
  *
  ************************************************************************/
 #if defined(CONFIG_PCI)
+
+static void wait_for_pci_ready(void)
+{
+	/*
+	 * Configure EREADY as input
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+	udelay(1000);
+
+	for (;;) {
+		if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+			return;
+	}
+
+}
+
 int is_pci_host(struct pci_controller *hose)
 {
-    /* The ocotea board is always configured as host. */
-    return(1);
+	wait_for_pci_ready();
+	return 1;		/* return 1 for host controller */
 }
 #endif /* defined(CONFIG_PCI) */
 
@@ -274,11 +326,3 @@
 	return (ctrlc());
 }
 #endif
-
-void board_reset(void)
-{
-	/*
-	 * Initiate chip reset in debug control register DBCR
-	 */
-	mtspr(dbcr0, 0x20000000);
-}
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
index 78307b4..e94360f 100644
--- a/board/prodrive/alpr/fpga.c
+++ b/board/prodrive/alpr/fpga.c
@@ -36,7 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
 
 #ifdef FPGA_DEBUG
 #define	PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -44,46 +44,38 @@
 #define	PRINTF(fmt,args...)
 #endif
 
-static	unsigned long	regval;
+static unsigned long regval;
 
-#define SET_GPIO_REG_0(reg, bit) {\
-					regval = in32(reg);\
-					regval &= ~(0x80000000 >> bit);\
-					out32(reg, regval);\
-					}
-
-#define SET_GPIO_REG_1(reg, bit) {\
-					regval = in32(reg);\
-					regval |= (0x80000000 >> bit);\
-					out32(reg, regval);\
-					}
-
-#define	GPIO_CLK_PIN			0x00002000
-#define	GPIO_CLK_PIN_I			0xffffdfff
-#define GPIO_DAT_PIN			0x00001000
-#define GPIO_DAT_PIN_I			0xffffefff
-#define GPIO_CLKDAT_PIN_I		0xffffcfff
+#define SET_GPIO_REG_0(reg, bit) {				\
+		regval = in32(reg);				\
+		regval &= ~(0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
 
-#define SET_GPIO_CLK_0			out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I);
-#define SET_GPIO_CLK_1			out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN);
-#define SET_GPIO_DAT_0			out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I);
-#define SET_GPIO_DAT_1			out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN);
+#define SET_GPIO_REG_1(reg, bit) {				\
+		regval = in32(reg);				\
+		regval |= (0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
 
-#define	SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
-#define	SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
+#define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
+#define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)
 
-#define SET_GPIO_CLK_0_Z1		out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN);
-#define SET_GPIO_CLK_0_Z0		out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I);
+#define FPGA_PRG		(0x80000000 >> CFG_GPIO_PROG_EN)
+#define FPGA_CONFIG		(0x80000000 >> CFG_GPIO_CONFIG)
+#define FPGA_DATA		(0x80000000 >> CFG_GPIO_DATA)
+#define FPGA_CLK		(0x80000000 >> CFG_GPIO_CLK)
+#define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)
 
-#define FPGA_WRITE_1 { \
-			SET_GPIO_CLK_0_Z1\
-			SET_GPIO_CLK_1}
+#define SET_FPGA(data)		out32(GPIO0_OR, data)
 
-#define FPGA_WRITE_0 { \
-			SET_GPIO_CLK_0_Z0\
-			SET_GPIO_CLK_1}
+#define FPGA_WRITE_1 {							\
+		SET_FPGA(OLD_VAL | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
 
-#define P_GP(reg) (reg & 0x00023f00)
+#define FPGA_WRITE_0 {							\
+		SET_FPGA(OLD_VAL | 0        | 0        );   /* set data to 0  */ \
+		SET_FPGA(OLD_VAL | FPGA_CLK | 0        );}  /* set data to 1  */
 
 /* Plattforminitializations */
 /* Here we have to set the FPGA Chain */
@@ -102,7 +94,7 @@
 	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
 	SET_GPIO_0((CFG_GPIO_SEL_DPR));
 
-	/* initialize the GPIO Pins */	
+	/* initialize the GPIO Pins */
 	/* output */
 	SET_GPIO_0(CFG_GPIO_CLK);
 	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
@@ -174,7 +166,7 @@
 }
 
 /* writes the complete buffer to the FPGA
-   writing the complete buffer in one function is very faster,
+   writing the complete buffer in one function is much faster,
    then calling it for every bit */
 int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
 {
@@ -182,14 +174,10 @@
 	unsigned char *data = (unsigned char *) buf;
 	unsigned char val=0;
 	int		i;
+	int len_40 = len / 40;
 
 	while (bytecount < len) {
-#ifdef CFG_FPGA_CHECK_CTRLC
-		if (ctrlc ()) {
-			return FPGA_FAIL;
-		}
-#endif
-		val = data[bytecount ++ ];
+		val = data[bytecount++];
 		i = 8;
 		do {
 			if (val & 0x01) {
@@ -202,8 +190,13 @@
 		} while (i > 0);
 
 #ifdef CFG_FPGA_PROG_FEEDBACK
-		if (bytecount % (len / 40) == 0)
+		if (bytecount % len_40 == 0) {
 			putc ('.');		/* let them know we are alive */
+#ifdef CFG_FPGA_CHECK_CTRLC
+			if (ctrlc ())
+				return FPGA_FAIL;
+#endif
+		}
 #endif
 	}
 	return FPGA_SUCCESS;
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 1baa609..135674c 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -34,7 +34,6 @@
 #define SZ_64K	    0x00000030
 #define SZ_256K	    0x00000040
 #define SZ_1M	    0x00000050
-#define SZ_8M       0x00000060
 #define SZ_16M	    0x00000070
 #define SZ_256M	    0x00000090
 
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 20a8098..e63c921 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -32,19 +32,19 @@
 #include <nand.h>
 
 struct alpr_ndfc_regs {
-	u16 cmd[4];
-	u16 addr_wait;
-	u16 term;
-	u16 dummy;
-	u16 dummy2;
-	u16 data;
+	u8 cmd[4];
+	u8 addr_wait;
+	u8 term;
+	u8 dummy;
+	u8 dummy2;
+	u8 data;
 };
 
 static u8 hwctl;
 static struct alpr_ndfc_regs *alpr_ndfc = NULL;
 
-#define readb(addr)	(u8)(*(volatile u16 *)(addr))
-#define writeb(d,addr)	*(volatile u16 *)(addr) = ((u16)(d))
+#define readb(addr)	(u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr)	*(volatile u8 *)(addr) = ((u8)(d))
 
 /*
  * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to