ARM: renesas: Add R8A77990 E3 Ebisu board
Add support for the R8A77990 Ebisu board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/board/renesas/ebisu/Kconfig b/board/renesas/ebisu/Kconfig
new file mode 100644
index 0000000..f500a94
--- /dev/null
+++ b/board/renesas/ebisu/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EBISU
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "ebisu"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "ebisu"
+
+endif
diff --git a/board/renesas/ebisu/MAINTAINERS b/board/renesas/ebisu/MAINTAINERS
new file mode 100644
index 0000000..facad52
--- /dev/null
+++ b/board/renesas/ebisu/MAINTAINERS
@@ -0,0 +1,6 @@
+EBISU BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/ebisu/
+F: include/configs/ebisu.h
+F: configs/r8a77990_ebisu_defconfig
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
new file mode 100644
index 0000000..2741035
--- /dev/null
+++ b/board/renesas/ebisu/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/ebisu/Makefile
+#
+# Copyright (C) 2018 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ebisu.o
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
new file mode 100644
index 0000000..9206214
--- /dev/null
+++ b/board/renesas/ebisu/ebisu.c
@@ -0,0 +1,87 @@
+/*
+ * board/renesas/ebisu/ebisu.c
+ * This file is Ebisu board support.
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+#define TMU0_MSTP125 BIT(25) /* secure */
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}