mpc5xxx: Add MVBC_P board support
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile
new file mode 100644
index 0000000..ea72f77
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/matrix_vision/mvbc_p/config.mk b/board/matrix_vision/mvbc_p/config.mk
new file mode 100644
index 0000000..c2c09f4
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c
new file mode 100644
index 0000000..356af1a
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/fpga.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn,
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+ 0
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ passive_serial,
+ Altera_EP2C8_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvbc_p_init_fpga(void)
+{
+ fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+ gd->reloc_off);
+ fpga_init(gd->reloc_off);
+ fpga_add(fpga_altera, &cyclone2);
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+ u32 dvo = gpio->simple_dvo;
+
+ fpga_debug("SET config : %s\n", assert ? "low" : "high");
+ if (assert)
+ dvo |= FPGA_CONFIG;
+ else
+ dvo &= ~FPGA_CONFIG;
+
+ if (flush)
+ gpio->simple_dvo = dvo;
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+ int result = 0;
+
+ udelay(10);
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio->simple_ival & FPGA_CONF_DONE) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+ int result = 0;
+
+ fpga_debug("STATUS check ... ");
+ if (gpio->sint_ival & FPGA_STATUS) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+ u32 dvo = gpio->simple_dvo;
+
+ fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+ if (assert_clk)
+ dvo |= FPGA_CCLK;
+ else
+ dvo &= ~FPGA_CCLK;
+
+ if (flush)
+ gpio->simple_dvo = dvo;
+
+ return assert_clk;
+}
+
+static inline int _write_fpga(u8 val)
+{
+ int i;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+ u32 dvo = gpio->simple_dvo;
+
+ for (i=0; i<8; i++) {
+ dvo &= ~FPGA_CCLK;
+ gpio->simple_dvo = dvo;
+ dvo &= ~FPGA_DIN;
+ if (val & 1)
+ dvo |= FPGA_DIN;
+ gpio->simple_dvo = dvo;
+ dvo |= FPGA_CCLK;
+ gpio->simple_dvo = dvo;
+ val >>= 1;
+ }
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("\n");
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h
new file mode 100644
index 0000000..3723073
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvbc_p_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c
new file mode 100644
index 0000000..b61e84e
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/mvbc_p.c
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2007
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvbc_p.h"
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+ long hi_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
+
+ /* precharge all banks */
+ out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+ /* precharge all banks */
+ out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
+
+ /* auto refresh */
+ out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
+
+ /* set mode register */
+ out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1,
+ test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+ /* setup config registers */
+ out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ if (dramsize > 0)
+ out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1);
+ else
+ out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
+
+ return dramsize;
+}
+
+void mvbc_init_gpio(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ printf("Ports : 0x%08x\n", gpio->port_config);
+ printf("PORCFG: 0x%08x\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
+
+ out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+ out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+ out_be32(&gpio->simple_ode, SIMPLE_ODE);
+ out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+ out_be32((u32*)&gpio->sint_ode, SINT_ODE);
+ out_be32((u32*)&gpio->sint_ddr, SINT_DDR);
+ out_be32((u32*)&gpio->sint_dvo, SINT_DVO);
+ out_be32((u32*)&gpio->sint_inten, SINT_INTEN);
+ out_be32((u32*)&gpio->sint_itype, SINT_ITYPE);
+ out_be32((u32*)&gpio->sint_gpioe, SINT_GPIOEN);
+
+ out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
+ out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
+ out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
+ out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
+
+ printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
+ printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
+}
+
+void reset_environment(void)
+{
+ char *s, sernr[64];
+
+ printf("\n*** RESET ENVIRONMENT ***\n");
+ memset(sernr, 0, sizeof(sernr));
+ s = getenv("serial#");
+ if (s) {
+ printf("found serial# : %s\n", s);
+ strncpy(sernr, s, 64);
+ }
+ gd->env_valid = 0;
+ env_relocate();
+ if (s)
+ setenv("serial#", sernr);
+}
+
+int misc_init_r(void)
+{
+ char *s = getenv("reset_env");
+
+ if (!s) {
+ if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+ return 0;
+ udelay(50000);
+ if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+ return 0;
+ udelay(50000);
+ if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
+ return 0;
+ }
+ printf(" === FACTORY RESET ===\n");
+ reset_environment();
+ saveenv();
+
+ return -1;
+}
+
+int checkboard(void)
+{
+ mvbc_init_gpio();
+ printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
+
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+ out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
+ size));
+ out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
+ size));
+ out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
+ size));
+ out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
+ size));
+}
+
+void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char line = 0xff;
+ u32 base;
+
+ if (PCI_BUS(dev) == 0) {
+ switch (PCI_DEV (dev)) {
+ case 0xa: /* FPGA */
+ line = 3;
+ pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
+ printf("found FPA - enable arbitration\n");
+ writel(0x03, (u32*)(base + 0x80c0));
+ writel(0xf0, (u32*)(base + 0x8080));
+ break;
+ case 0xb: /* LAN */
+ line = 2;
+ break;
+ case 0x1a:
+ break;
+ default:
+ printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
+ break;
+ }
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
+ }
+}
+
+struct pci_controller hose = {
+ fixup_irq:pci_mvbc_fixup_irq
+};
+
+int mvbc_p_load_fpga(void)
+{
+ size_t data_size = 0;
+ void *fpga_data = NULL;
+ char *datastr = getenv("fpgadata");
+ char *sizestr = getenv("fpgadatasize");
+
+ if (datastr)
+ fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+ if (sizestr)
+ data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+ return fpga_load(0, fpga_data, data_size);
+}
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ char *s;
+ int load_fpga = 1;
+
+ mvbc_p_init_fpga();
+ s = getenv("skip_fpga");
+ if (s) {
+ printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+ load_fpga = 0;
+ }
+ if (load_fpga) {
+ printf("loading FPGA ... ");
+ mvbc_p_load_fpga();
+ printf("done\n");
+ }
+ pci_mpc5xxx_init(&hose);
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+ char *ptr;
+
+ /* DHCP vendor-class-identifier = 60 */
+ if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
+ *e++ = 60;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+ /* DHCP_CLIENT_IDENTIFIER = 61 */
+ if ((ptr = getenv("dhcp_client_id"))) {
+ *e++ = 61;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+
+ return e;
+}
+
+u8 *dhcp_vendorex_proc (u8 *popt)
+{
+ return NULL;
+}
+
+void show_boot_progress(int val)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ switch(val) {
+ case 0: /* FPGA ok */
+ setbits_be32(&gpio->simple_dvo, 0x80);
+ break;
+ case 1:
+ setbits_be32(&gpio->simple_dvo, 0x40);
+ break;
+ case 12:
+ setbits_be32(&gpio->simple_dvo, 0x20);
+ break;
+ case 15:
+ setbits_be32(&gpio->simple_dvo, 0x10);
+ break;
+ default:
+ break;
+ }
+
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h
new file mode 100644
index 0000000..3330798
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/mvbc_p.h
@@ -0,0 +1,43 @@
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0
+#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1
+#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2
+#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3
+#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
+
+#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define FACT_RST MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
+
+#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
+ FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
+#define SIMPLE_DVO (FPGA_CONFIG)
+#define SIMPLE_ODE (FPGA_CONFIG)
+#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
+ FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
+ WD_WDI | COP_PRESENT)
+
+#define SINT_ODE 0
+#define SINT_DDR 0
+#define SINT_DVO 0
+#define SINT_INTEN 0
+#define SINT_ITYPE 0
+#define SINT_GPIOEN (FPGA_STATUS)
+
+#define WKUP_ODE (MAN_RST)
+#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
+#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
+
+#endif
diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript
new file mode 100644
index 0000000..5cee6c5
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/mvbc_p_autoscript
@@ -0,0 +1,44 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+if test ${console} = yes;
+then
+setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
+else
+setenv addcons setenv bootargs \${bootargs} console=tty0
+fi
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscr_boot} != no;
+then
+ if test ${netboot} = yes;
+ then
+ bootp
+ if test $? = 0;
+ then
+ echo "=== bootp succeeded -> netboot ==="
+ run set_ip
+ run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb
+ else
+ echo "=== netboot failed ==="
+ fi
+ fi
+ run set_static_ip set_static_nm set_static_gw set_ip
+ echo "=== bootfromflash ==="
+ run cpdtb rundtb bootfromflash
+else
+ echo "=== boot stopped with autoscr_boot no ==="
+fi