| commit | 1f987044706682fe4296eb4d47e2b8c0e6a216dd | [log] [tgz] |
|---|---|---|
| author | Patrick Delaunay <patrick.delaunay@st.com> | Wed Apr 10 14:09:22 2019 +0200 |
| committer | Patrice Chotard <patrice.chotard@st.com> | Thu May 23 11:38:10 2019 +0200 |
| tree | 49ed36ed0ab1c83ab82b0aa849454638365460f0 | |
| parent | 250bf90e2962b6cd240e824f31b2c5531caa6fa7 [diff] |
stm32mp1: ram: increase the delay after reset to 128 cycles Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>