tree fd8ef54e242e4c0a0607f86045a2e6c893a4728a
parent e57dcf6bdf85f892d988b98c572855684a22b9aa
author Ye.Li <B37916@freescale.com> 1410229020 +0800
committer Stefano Babic <sbabic@denx.de> 1411979047 +0200

imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset

Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.

Signed-off-by: Ye.Li <B37916@freescale.com>