commit 2874b2ae0abc0407357229994a51ac4cfacf07db
author Michal Simek <michal.simek@xilinx.com> Wed Aug 22 16:18:34 2018 +0200
committer Michal Simek <michal.simek@xilinx.com> Tue Oct 16 16:53:24 2018 +0200
tree 47991cc6058205842cc8da5722917c72a7af1e3e
parent 4b066a1dd1eb07712f94739c5b9e510a86ff605e

net: gem: Do not setup any clock for Xilinx SoC Versal

Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers/net/zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index e22d048..bc33126 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -461,6 +461,7 @@
 		break;
 	}
 
+#if !defined(CONFIG_ARCH_VERSAL)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -472,6 +473,9 @@
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
 	}
+#else
+	debug("requested clk_rate %ld\n", clk_rate);
+#endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);