ppc4xx: Complete remove bogus dflush()
Since the current dflush() implementation is know to have some problems
(as seem on lwmon5 ECC init) this patch removes it completely and replaces
it by using clean_dcache_range().
Tested on Katmai with ECC DIMM.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 0b16b505..6b1b53a 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -34,11 +34,11 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <ppc440.h>
void hcu_led_set(u32 value);
void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
@@ -185,14 +185,14 @@
#endif
sync();
- eieio();
puts(str);
/* ECC bit set method for cached memory */
/* Fast method, no noticeable delay */
dcbz_area(start_address, num_bytes);
- dflush();
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(start_address, start_address + num_bytes);
blank_string(strlen(str));
/* Clear error status */
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 9e722b9..5b5de48 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -40,6 +40,7 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
@@ -237,7 +238,6 @@
static void ppc440sp_sdram_register_dump(void);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
static u32 mfdcr_any(u32 dcr)
{
@@ -2355,7 +2355,8 @@
} else {
/* ECC bit set method for cached memory */
dcbz_area(start_address, num_bytes);
- dflush();
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(start_address, start_address + num_bytes);
}
blank_string(strlen(str));
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index e20c9eb..acf0f49 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -92,7 +92,6 @@
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
@@ -1201,7 +1200,8 @@
#else
#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
#endif
- dflush();
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
debug("Completed\n");
sync();
remove_tlb(CFG_SDRAM_BASE, dram_size);
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 8d2777d..a513b45 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1675,35 +1675,6 @@
sync
blr
function_epilog(dcbz_area)
-
-/*----------------------------------------------------------------------------+
-| dflush. Assume 32K at vector address is cachable.
-+----------------------------------------------------------------------------*/
- function_prolog(dflush)
- mfmsr r9
- rlwinm r8,r9,0,15,13
- rlwinm r8,r8,0,17,15
- mtmsr r8
- mfspr r8,dvlim
- addi r3,r0,0x0000
- mtspr dvlim,r3
- mfspr r3,ivpr
- addi r4,r0,1024
- mtctr r4
-..dflush_loop:
- lwz r6,0x0(r3)
- addi r3,r3,32
- bdnz ..dflush_loop
- addi r3,r3,-32
- mtctr r4
-..ag: dcbf r0,r3
- addi r3,r3,-32
- bdnz ..ag
- mtspr dvlim,r8
- sync
- mtmsr r9
- blr
- function_epilog(dflush)
#endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */