| commit | 28540c5bb45a9bc15e283d4a2737c034f9944a0d | [log] [tgz] |
|---|---|---|
| author | Ian Ray <ian.ray@ge.com> | Mon Oct 15 09:59:44 2018 +0200 |
| committer | Stefano Babic <sbabic@denx.de> | Mon Oct 22 14:32:07 2018 +0200 |
| tree | 5794ea461b0c07477a6409dbb8d259627808b87e | |
| parent | 5494ab229eaee4ac3c61498faaba062888c42d16 [diff] |
board: ge: bx50v3: correct LDB clock Use Video PLL to provide 65MHz for all displays. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.com>