| commit | 27c8320d30f9a469e86f991ad79cb6e4f77bb7fc | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@amd.com> | Fri Sep 22 12:35:43 2023 +0200 |
| committer | Michal Simek <michal.simek@amd.com> | Mon Oct 09 10:25:32 2023 +0200 |
| tree | d63ea0c3380afebc3c9698e52c3bd8f8251ab2a2 | |
| parent | d9974450d9926a30173d62589a30b92a89754914 [diff] [blame] |
arm64: zynqmp: Aligned QSPI configuration with latest spec Official DT binding description for dual stacked/paralllel configurations have been merged that's why switch to it. Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 4fcb466..e72ed50 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -354,11 +354,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */