diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
index d7c07f4..d0eefcb 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
@@ -9,6 +9,10 @@
 #include <asm/arch/iomux.h>
 
 enum {
+	IMX8ULP_PAD_PTA3__TPM0_CH2                         = IOMUX_PAD(0x000c, 0x000c, IOMUX_CONFIG_MPORTS | 0x6, 0x0948, 0x1, 0),
+	IMX8ULP_PAD_PTA8__LPI2C0_SCL                       = IOMUX_PAD(0x0020, 0x0020, IOMUX_CONFIG_MPORTS | 0x5, 0x097c, 0x2, 0),
+	IMX8ULP_PAD_PTA9__LPI2C0_SDA                       = IOMUX_PAD(0x0024, 0x0024, IOMUX_CONFIG_MPORTS | 0x5, 0x0980, 0x2, 0),
+
 	IMX8ULP_PAD_PTB7__PMIC0_MODE2                       = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
 	IMX8ULP_PAD_PTB8__PMIC0_MODE1                       = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
 	IMX8ULP_PAD_PTB9__PMIC0_MODE0                       = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0),
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 02e90f7..e599e6c 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -186,6 +186,9 @@
 		LPI2C7_PCC4_SLOT << 8 | 4,
 	};
 
+	if (i2c_num == 0)
+		return 0;
+
 	if (i2c_num < 4 || i2c_num > 7)
 		return -EINVAL;
 
@@ -214,6 +217,9 @@
 		LPI2C7_PCC4_SLOT << 8 | 4,
 	};
 
+	if (i2c_num == 0)
+		return 24000000;
+
 	if (i2c_num < 4 || i2c_num > 7)
 		return 0;
 
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index f64a8fb..427b5e4 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -465,6 +465,11 @@
 
 	/* flexspi0 */
 	trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
+
+	/* tpm0: PBridge1 slot 21 */
+	trdc_mbc_set_access(2, 7, 1, 21, false);
+	/* lpi2c0: PBridge1 slot 24 */
+	trdc_mbc_set_access(2, 7, 1, 24, false);
 	return 0;
 }
 
diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index 3ff4d43..1502e4d 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -12,6 +12,7 @@
 #include <asm/arch/sys_proto.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,11 +49,66 @@
 }
 #endif
 
+#define I2C_PAD_CTRL	(PAD_CTL_ODE)
+static const iomux_cfg_t lpi2c0_pads[] = {
+	IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
+#define TPM_PAD_CTRL	(PAD_CTL_DSE)
+static const iomux_cfg_t tpm0_pads[] = {
+	IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL),
+};
+
+void mipi_dsi_mux_panel(void)
+{
+	int ret;
+	struct gpio_desc desc;
+
+	/* It is temp solution to directly access i2c, need change to rpmsg later */
+
+	/* enable lpi2c0 clock and iomux */
+	imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads));
+	writel(0xD2000000, 0x28091060);
+
+	ret = dm_gpio_lookup_name("gpio@20_9", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "dsi_mux");
+	if (ret) {
+		printf("%s request dsi_mux failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+void mipi_dsi_panel_backlight(void)
+{
+	/* It is temp solution to directly access pwm, need change to rpmsg later */
+	imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads));
+	writel(0xD4000001, 0x28091054);
+
+	/* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */
+	writel(1000, 0x28095018);
+	writel(1000, 0x28095034); /* MOD = CV, full duty */
+	writel(0x28, 0x28095010);
+	writel(0x20, 0x28095030);
+}
+
 int board_init(void)
 {
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
 
+	if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+		mipi_dsi_mux_panel();
+		mipi_dsi_panel_backlight();
+	}
+
 	return 0;
 }