arc: add support for SLC (System Level Cache, AKA L2-cache)
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidate
For now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 48ee86e..e1ef19c 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -18,6 +18,10 @@
mov %fp, %sp
/* Unconditionally disable caches */
+#ifdef CONFIG_ISA_ARCV2
+ bl slc_flush
+ bl slc_disable
+#endif
bl flush_dcache_all
bl dcache_disable
bl icache_disable