usb: UniPhier: add UniPhier on-chip xHCI host driver support
Support xHCI host driver used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0e005c2..24a595f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -17,6 +17,14 @@
if USB_XHCI_HCD
+config USB_XHCI_UNIPHIER
+ bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
+ depends on ARCH_UNIPHIER
+ default y
+ ---help---
+ Enables support for the on-chip xHCI controller on Panasonic
+ UniPhier SoCs.
+
endif
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 66d6e9a..eb6f34b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,6 +48,7 @@
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
new file mode 100644
index 0000000..08b15e0
--- /dev/null
+++ b/drivers/usb/host/xhci-uniphier.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <usb.h>
+#include <fdtdec.h>
+#include "xhci.h"
+
+static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int node_list[2];
+ fdt_addr_t addr;
+ int count;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
+ COMPAT_PANASONIC_XHCI, node_list,
+ ARRAY_SIZE(node_list));
+
+ if (index >= count)
+ return -ENODEV;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ *base = (struct xhci_hccr *)addr;
+
+ return 0;
+}
+
+#define USB3_RST_CTRL 0x00100040
+#define IOMMU_RST_N (1 << 5)
+#define LINK_RST_N (1 << 4)
+
+static void uniphier_xhci_reset(void __iomem *base, int on)
+{
+ u32 tmp;
+
+ tmp = readl(base + USB3_RST_CTRL);
+
+ if (on)
+ tmp &= ~(IOMMU_RST_N | LINK_RST_N);
+ else
+ tmp |= IOMMU_RST_N | LINK_RST_N;
+
+ writel(tmp, base + USB3_RST_CTRL);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ int ret;
+ struct xhci_hccr *cr;
+ struct xhci_hcor *or;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return ret;
+
+ uniphier_xhci_reset(cr, 0);
+
+ or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
+
+ *hccr = cr;
+ *hcor = or;
+
+ return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+ int ret;
+ struct xhci_hccr *cr;
+
+ ret = get_uniphier_xhci_base(index, &cr);
+ if (ret < 0)
+ return;
+
+ uniphier_xhci_reset(cr, 1);
+}