phy: marvell: a3700: revise the USB3 comphy setting during power on
This commit is based on commit d9899826 by
zachary <zhangzg@marvell.com>
from u-boot-marvell, see
github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826
- According to design specification, the transmitter should be set to high
impedence mode during electrical idle. Thus transmitter should detect RX
at high impedence mode also, and delay is needed to accommodate high
impedence off latency. Otherwise the USB3 will have detection issue that
most of the time the USB3 device can not be detected at all, or be
detected as USB2 device sometimes.
Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
Bit 6: set to 1 to let Tx detect Rx at HiZ mode
Bit [3:4]: set to 2 to be delayed by 2 clock cycles
Bit 0: set to 1 to set transmitter to high impedance mode during idle.
- USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
(emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
to select 0x1(3.5dB emphasize). Thus need to override what comes from
the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
0x181 and bit0 of register 0x180).
- According to USB3 application note, need to update below comphy
registers:
Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index 07f4792..7990aab 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -141,6 +141,11 @@
#define LANE_CFG1 0x181
#define bf_use_max_pll_rate BIT(9)
+#define prd_txdeemph1_mask BIT(15)
+#define tx_det_rx_mode BIT(6)
+#define gen2_tx_data_dly_deft (2 << 3)
+#define gen2_tx_data_dly_mask (BIT(3) | BIT(4))
+#define tx_elec_idle_mode_en BIT(0)
#define LANE_CFG4 0x188
#define bf_spread_spectrum_clock_en BIT(7)