diff --git a/CHANGELOG b/CHANGELOG
index a834568..da67d36 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,91 @@
+commit 2d78074d2e806edc380c1464eb9e5df335ece65e
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 22 17:32:28 2007 +0200
+
+    ppc7xx: Update CPCI750 board
+
+    This small CPCI750 update extends the board specific command
+    "show_config" to display the Marvell strapping registers and
+    extends the PCI IDE controller.
+
+    Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Aug 15 11:55:35 2007 -0500
+
+    86xx: Fix lingering CFG_CMD_* references in sbc8641d.h
+
+    Remove a leftover in net/tftp.c while we're at it.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Aug 15 12:20:40 2007 -0500
+
+    Move the MPC8641HPCN board under board/freescale.
+
+    Minor path corrections needed to ensure buildability.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8662577fe36fdb6a44b55b998d9daac6392a736a
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Aug 15 11:46:22 2007 -0500
+
+    86xx: Fix lingering CFG_CMD_* references in sbc8641d.h
+
+    Remove a leftover in net/tftp.c while we're at it.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 210f463c71917b7a4495c2103c228b9c179ae64d
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date:	Wed Aug 15 11:13:15 2007 -0400
+
+    Fix where the #ifdef CFG_BOOTMAPSZ is placed.
+
+    Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb
+    interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT)
+    when it should have gone inside of the conditional.  As a result, it
+    broke non-LIBFDT board builds.
+
+    Also added a missing "not." to the comment.
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Tue Aug 14 14:06:45 2007 -0500
+
+    Fix malloc size error in ahci_init_one.
+
+    Typically this causes scsi init to corrupt the
+    devlist and break the coninfo command.
+    Fix a compiler size warning.
+
+    Signed-off-by: Jason Jin <jason.jin@freescale.com>
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit b361acd64fd2525c081b9b288b0804efe209c0e9
+Author: ksi@koi8.net <ksi@koi8.net>
+Date:	Tue Aug 14 10:02:16 2007 -0700
+
+    TI DaVinci - fix unsupported %hhx format
+
+    Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
+
+commit f01dbb5424a81453c81190dd30e945891466f621
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Aug 14 18:42:36 2007 +0200
+
+    Coding style cleanup. Update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924
 Author: Andy Fleming <afleming@freescale.com>
 Date:	Tue Aug 14 10:32:59 2007 -0500
@@ -20,6 +108,50 @@
 
     Supply spi interface in at45.c
 
+commit 4ce846ec59f36b85d6644a769690ad3feb667575
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 14 15:12:01 2007 +0200
+
+    POST: Fix merge problem
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 14 15:03:17 2007 +0200
+
+    Coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 779e975117a75e91fcebe226a63104dbfb924ab1
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 14 14:44:41 2007 +0200
+
+    ppc4xx: Add initial Zeus (PPC405EP) board support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c5a172a5fd636c12467429e3f7910e53773979c6
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 14 14:41:55 2007 +0200
+
+    POST: Add option for external ethernet loopback test
+
+    When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
+    is not done using an internal loopback connection, but by assuming
+    that an external loopback connector is plugged into the board.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit eb2b4010ae426245172988804ee8d9193fb41038
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 14 14:39:44 2007 +0200
+
+    POST: Add ppc405 support to cache and UART POST
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c
 Author: Peter Pearse <peter.pearse@arm.com>
 Date:	Tue Aug 14 10:46:32 2007 +0100
@@ -391,6 +523,17 @@
     Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
     Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
 
+commit 273db7e1bdd1937e32f1d4507321bb721ebd3118
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Aug 13 09:05:33 2007 +0200
+
+    ppc4xx: Fix problem in PLL clock calculation
+
+    This patch was originall provided by David Mitchell <dmitchell@amcc.com>
+    and fixes a bug in the PLL clock calculation.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sun Aug 12 21:34:50 2007 +0200
@@ -849,6 +992,14 @@
     Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
     Signed-off-by: Jon Loeliger <jdl@freescale.com>
 
+commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Aug 10 10:42:25 2007 +0200
+
+    Coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f
 Author: Dirk Behme <dirk.behme@googlemail.com>
 Date:	Thu Aug 2 17:42:08 2007 +0200
@@ -873,6 +1024,105 @@
 
     Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
 
+commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:31:22 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: HCU5 files
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 6e5de26c6e7580faf16e87745cd488b92b492d0c
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:30:33 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: HCU4 files
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit e8397fc78c9394d71de233a4d810fbc9047e4c76
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:38:26 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: common files
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit ac982ea5a4f2f993efcf52dca122f5a59df047d8
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:28:44 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: make related
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 137fdd9f474ecb853efdace5200576308c67f18d
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:28:03 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: HCU5 config
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:27:15 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: HCU4 config
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:25:31 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: READMEs
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 641cca9569ce351ddb287fd3343d8b1dcb591db4
+Author: Niklaus Giger <niklausgiger@gmx.ch>
+Date:	Fri Jul 27 11:37:40 2007 +0200
+
+    Add PPC4xx-HCU4 and HCU5 boards: Infrastructure
+
+    This series of patches adds support for 2 boards from Netstal Maschinen.
+
+    The HCU4 has a PPC405Gpr and
+    the HCU5 has a PPC440EPX.
+
+    The HCU4 has a somehow complicated flash setup, as the booteprom is
+    only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more
+    elegant solution.
+
+    The HCU5 has only a booteprom as the whole code will be downloaded from a
+    different board which has HD, CD-ROM, etc and where all code is stored.
+
+    This is my third try. I incorporated all suggestions made by Wolfgang and Stefan.
+    Thanks them a lot.
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+
+commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Aug 10 08:42:55 2007 +0200
+
+    ppc4xx: Update lwmon5 POST configuration
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Fri Aug 10 08:25:22 2007 +0200
+
+    POST: Add ppc4xx UART POST support without external uart clock (lwmon5)
+
+    The patch adds support for UART POST on ppc44x-based boards with no
+    external serial clocks installed.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
 commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Mon Aug 6 18:18:34 2007 -0500
@@ -1169,6 +1419,17 @@
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 537223afa61f64480df31ce440a9cb386df4a814
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Aug 6 21:10:17 2007 +0200
+
+    ppc4xx: Update AMCC Bamboo README doc/README.bamboo
+
+    As suggested by Eugene O'Brien <Eugene.O'Brien@advantechamt.com>,
+    here an updated Bamboo README.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 9c7e4b06214db61bb21f1bcbe57c97519669baae
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Aug 6 02:17:36 2007 +0200
@@ -1316,6 +1577,42 @@
 
     Minor cleanup of <board>_nand build rules.
 
+commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Aug 2 08:33:56 2007 +0200
+
+    ppc4xx: Code cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c92409812206ac67a7fa7aae298539a9c3804a46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Tue Jul 31 18:51:48 2007 +0200
+
+    [ppc440SPe] Graceful recovery from machine check during PCIe configuration
+
+    During config transactions on the PCIe bus an attempt to scan for a
+    non-existent device can lead to a machine check exception with certain
+    peripheral devices. In order to avoid crashing in such scenarios the
+    instrumented versions of the config cycle read routines are introduced, so
+    the exceptions fixups framework can gracefully recover.
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+    Acked-by: Rafal Jaworowski <raj@semihalf.com>
+
+commit dec99558b9ea75a37940d07f41a3565a50b54ad1
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date:	Tue Jul 31 18:19:54 2007 +0200
+
+    [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
+
+    This brings back separate settings for PCIe bus numbers depending on chip
+    revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa
+    commit. 440SPe rev. A does NOT work properly with the same settings as for
+    the rev. B (no devices are seen on the bus during enumeration).
+
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+
 commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Aug 2 00:48:45 2007 +0200
@@ -1324,6 +1621,55 @@
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68
+Author: Eugene OBrien <eugene.obrien@advantechamt.com>
+Date:	Tue Jul 31 10:24:56 2007 +0200
+
+    ppc4xx: Update AMCC Bamboo 440EP support
+
+    Changed storage type of cfg_simulate_spd_eeprom to const
+    Changed storage type of gpio_tab to stack storage
+    (Cannot access global data declarations in .bss until afer code relocation)
+
+    Improved SDRAM tests to catch problems where data is not uniquely addressable
+    (e.g. incorrectly programmed SDRAM row or columns)
+
+    Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
+    Fixed AM29LV320DT (OpCode Flash) sector map
+
+    Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jul 31 08:37:01 2007 +0200
+
+    ppc4xx: Update 440EPx lwmon5 board support
+
+    - Clear ECC status regs after ECC POST test
+    - Set dcbz for ECC generation with caches enabled as default
+    - Code cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 30 11:04:57 2007 +0200
+
+    ppc4xx: Only print ECC related info when the error bis are set
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e36220a4baf1f188ba60f17e9d0f043069b1362a
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Jul 27 16:44:31 2007 +0200
+
+    new FPGA image for PLU405 board
+
+    new FPGA image for PLU405 board with improved CompactFlash timing
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
 commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6
 Author: Rafal Jaworowski <raj@semihalf.com>
 Date:	Fri Jul 27 14:43:59 2007 +0200
@@ -1351,6 +1697,73 @@
 
     Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
 
+commit d4024bb72dd81695ec099b2199eda0d27c623e62
+Author: John Otken <john@softadvances.com>
+Date:	Thu Jul 26 17:49:11 2007 +0200
+
+    ppc4xx: Add support for AMCC 405EP Taihu board
+
+    Signed-off-by: John Otken <john@softadvances.com>
+
+commit b66091de6c7390620312c2501db23d8391e7cabb
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Thu Jul 26 15:08:01 2007 +0200
+
+    ppc4xx: lwmon5: Update Lime initialization
+
+    Change Lime SDRAM initialization to now support 100MHz and
+    133MHz (if enabled). Also the framebuffer is initialized to
+    display a blue rectangle with a white border.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9f24a808f17fc0f37b7fb4805f734741335caecc
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jul 24 09:52:52 2007 +0200
+
+    ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added
+
+    The used Intel NOR FLASH chips have internally two dies, and are now
+    treated as two seperate chips.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit aedf5bde179ecfbd0a96130d18996a96518b785f
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jul 24 07:20:09 2007 +0200
+
+    ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)
+
+    As suggested by Hakan Eryigit, here an updated setup for the lwmon5
+    interrupt controller.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a71d96eac8130b53a91f93cd10c70fca0db18d52
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jul 20 15:03:44 2007 +0200
+
+    ppc4xx: Fix bug with default GPIO output value
+
+    As spotted by Matthias Fuchs, the default output values for all GPIO1
+    outputs were not setup correctly. This patch fixes this issue.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 531e3e8b831f357056448fa573137d5fb37000fd
+Author: Pavel Kolesnikov <concord@emcraft.com>
+Date:	Fri Jul 20 15:03:03 2007 +0200
+
+    POST: Add ECC POST for the lwmon5 board
+
+    This patch adds ECC Post test for the Lwmon5 board based
+    on PPC440EPx to U-Boot.
+
+    Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
+    Acked-by: Yuri Tikhonov <yur@emcraft.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
 commit cc3023b9f95d7ac959a764471a65001062aecf41
 Author: Rafal Jaworowski <raj@semihalf.com>
 Date:	Thu Jul 19 17:12:28 2007 +0200
@@ -1362,6 +1775,58 @@
 
     Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
 
+commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 16 10:02:12 2007 +0200
+
+    ppc4xx: Code cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 16 10:01:38 2007 +0200
+
+    ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 16 10:00:43 2007 +0200
+
+    ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c
+
+    The new boardspecific DDR2 controller configuration is used for the Yucca
+    board. Now the Yucca board with 440SPe Rev. A chips is also supported.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 16 09:57:00 2007 +0200
+
+    ppc4xx: Add new weak functions to support boardspecific DDR2 configuration
+
+    The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better
+    support non default, boardspecific DDR(2) controller configuration.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5743a9207a370b90f09b20ebd61167c806b937f3
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 16 08:53:51 2007 +0200
+
+    ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
+
+    The new function remove_tlb() can be used to remove the TLB's used to
+    map a specific memory region. This is especially useful for the DDR(2)
+    setup routines which configure the SDRAM area temporarily as a cached
+    area (for speedup on auto-calibration and ECC generation) and later
+    need this area uncached for normal usage.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 3a6cab844cf74f76639d795e0be8717e02c86af7
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat Jul 14 22:51:02 2007 +0200
@@ -1393,6 +1858,17 @@
 
     Signed-off-by: Heiko Schocher <hs@denx.de>
 
+commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jul 12 16:32:08 2007 +0200
+
+    ppc4xx: Change receive buffer handling in the 4xx emac driver
+
+    This change fixes a bug in the receive buffer handling, that
+    could lead to problems upon high network traffic (broadcasts...).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Jul 12 01:45:34 2007 +0200
@@ -1975,6 +2451,50 @@
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit c8603cfbd4573379a6076c9c208545ba2bbf019a
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jul 9 11:00:24 2007 +0200
+
+    Small coding style cleanup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Jul 9 10:10:08 2007 +0200
+
+    Migrate esd 405EP boards to new NAND subsystem
+
+    Remove unused CFG_NAND_LEGACY define
+
+    These boards to not have NAND.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Jul 9 10:10:06 2007 +0200
+
+    Migrate esd 405EP boards to new NAND subsystem
+
+    Migrate esd 405EP boards to new NAND subsystem
+
+    -cleanup
+    -use correct io accessors (in/out_be32())
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit e09f7ab5749c345f924da272bea0521a73af5b11
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Jul 9 10:10:04 2007 +0200
+
+    Migrate esd 405EP boards to new NAND subsystem
+
+    This patch prepares the migration from the legacy NAND driver
+    to U-Boot's new NAND subsystem for esd boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
 commit c3517f919d0f61650cf3027fd4faf0f631142f6c
 Author: Jon Loeliger <jdl@freescale.com>
 Date:	Sun Jul 8 18:10:08 2007 -0500
@@ -2162,6 +2682,41 @@
 
     Signed-off-by: Jon Loeliger <jdl@freescale.com>
 
+commit 10e038932f22ee80ebd53de312531e70e6590a2f
+Author: Thomas Knobloch <knobloch@siemens.com>
+Date:	Fri Jul 6 14:58:39 2007 +0200
+
+    [NAND] Bad block skipping for command nboot
+
+    The old implementation of command nboot does not support reading the image from
+    NAND flash with skipping of bad blocks. The patch implements a new version of
+    the nboot command: by calling nboot.jffs2 from the u-boot command line the
+    command will load the image from NAND flash with respect to bad blocks (by using
+    nand_read_opts()). This is similar to e.g. the NAND read command: "nand
+    read.jffs2 ...".
+
+    Signed-off-by: Thomas Knobloch <knobloch@siemens.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jul 6 12:26:51 2007 +0200
+
+    ppc4xx: Update lwmon5 default environment
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5d187430a055d62f17ca84d75e7245439d1f7e75
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jul 6 11:48:24 2007 +0200
+
+    ppc4xx: Update lwmon5 board
+
+    Add unlock=yes environment variable to default variables to unlock
+    the CFI flash by default.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e
 Author: Stefan Roese <sr@denx.de>
 Date:	Fri Jul 6 09:45:47 2007 +0200
@@ -3151,6 +3706,18 @@
     - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
     - minor 4xx cleanup
 
+commit d677b32855f577ae2690dcd64a172cdd706e0ffc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Fri Jun 22 10:34:12 2007 +0200
+
+    [patch] add nand_init() prototype to nand.h
+
+    since nand_init() is expected to be called by other parts of u-boot, there
+    should be a prototype for it in nand.h
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Jun 20 18:14:24 2007 +0200
@@ -3767,6 +4334,16 @@
     Signed-off-by: Marian Balakowicz <m8@semihalf.com>
     Acked-by: Bartlomiej Sieka <tur@semihalf.com>
 
+commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b
+Author: Ulf Samuelsson <ulf@atmel.com>
+Date:	Thu May 24 12:12:47 2007 +0200
+
+    [PATCH][NAND] Define the Vendor Id for Micron NAND Flash
+
+    Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit d756894722c888d09a9fa1df8323753772d3dcce
 Author: Stefan Roese <sr@denx.de>
 Date:	Thu May 24 09:49:00 2007 +0200
diff --git a/MAINTAINERS b/MAINTAINERS
index f812431..d5249e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -158,12 +158,12 @@
 	VOH405			PPC405EP
 	VOM405			PPC405EP
 	WUH405			PPC405EP
-	CMS700                  PPC405EP
+	CMS700			PPC405EP
 
 Niklaus Giger <niklaus.giger@netstal.com>
 
-        HCU4                    PPC405GPr
-        HCU5                    PPC440EPx
+	HCU4			PPC405GPr
+	HCU5			PPC440EPx
 
 Frank Gottschling <fgottschling@eltec.de>
 
diff --git a/MAKEALL b/MAKEALL
index 4775cfe..4467d75 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -358,6 +358,12 @@
 	ZUMA		\
 "
 
+LIST_TSEC="		\
+	${LIST_85xx}	\
+	${LIST_86xx}	\
+	${LIST_83xx}	\
+"
+
 LIST_7xx="		\
 	BAB7xx		\
 	CPCI750		\
@@ -673,7 +679,7 @@
 	mips|mips_el| \
 	nios|nios2| \
 	ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
-	x86|I486)
+	x86|I486|TSEC)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
diff --git a/Makefile b/Makefile
index 92db8f4..2bb11b6 100644
--- a/Makefile
+++ b/Makefile
@@ -1914,7 +1914,7 @@
 #########################################################################
 
 MPC8641HPCN_config:    unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn
+	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -28,7 +28,9 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index f41eb7b..8a5b03b 100644
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -33,6 +34,7 @@
 #endif
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
 
 /* fpga configuration data - gzip compressed and generated by bin2c */
 const unsigned char fpgadata[] =
@@ -164,18 +166,12 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;
@@ -218,35 +214,17 @@
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
 /* ------------------------------------------------------------------------- */
 
-int testdram (void)
+void reset_phy(void)
 {
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
+#ifdef CONFIG_LXT971_NO_SLEEP
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
 #endif
+}
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index df48766..0d4ab2d 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -33,7 +33,10 @@
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 635ba2f..2cdd7be 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -68,9 +69,9 @@
 	/*
 	 * Reset CPLD via GPIO12 (CS3) pin
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
 
 	return 0;
@@ -94,13 +95,7 @@
  	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 
 	return (0);
 }
@@ -153,11 +148,6 @@
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
@@ -180,17 +170,17 @@
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
 			break;
 		}
 	}
@@ -235,19 +225,6 @@
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 62f6c20..da147ee 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -31,7 +31,9 @@
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
+#if defined(CFG_NAND_LEGACY)
 #include <linux/mtd/nand_legacy.h>
+#endif
 #include <fat.h>
 #include <part.h>
 
@@ -294,6 +296,8 @@
 			rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
 				     start, nbytes, (size_t *)&total, (uchar *)addr);
 			debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#else
+			rc = -1;
 #endif
 		}
 		if (rc != 0) {
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
new file mode 100644
index 0000000..7bf6847
--- /dev/null
+++ b/board/esd/common/esd405ep_nand.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch(cmd) {
+	case NAND_CTL_SETCLE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+		break;
+	case NAND_CTL_CLRCLE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+		break;
+	case NAND_CTL_SETALE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+		break;
+	case NAND_CTL_CLRALE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+		break;
+	case NAND_CTL_SETNCE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+		break;
+	case NAND_CTL_CLRNCE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+		break;
+	}
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+	if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+		return 1;
+	return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+	/*
+	 * Set NAND-FLASH GPIO signals to defaults
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Initialize nand_chip structure
+	 */
+	nand->hwcontrol = esd405ep_nand_hwcontrol;
+	nand->dev_ready = esd405ep_nand_device_ready;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->chip_delay = NAND_BIG_DELAY_US;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
+}
+#endif
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 17e3568..298aa6a 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -55,6 +55,71 @@
 #define DP(x)
 #endif
 
+static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
+				     {"PCI0DLL_1     "},  /* 30 */
+				     {"PCI0DLL_0     "},  /* 29 */
+				     {"PCI1DLL_2     "},  /* 28 */
+				     {"PCI1DLL_1     "},  /* 27 */
+				     {"PCI1DLL_0     "},  /* 26 */
+				     {"BbEP2En       "},  /* 25 */
+				     {"SDRAMRdDataDel"},  /* 24 */
+				     {"SDRAMRdDel    "},  /* 23 */
+				     {"SDRAMSync     "},  /* 22 */
+				     {"SDRAMPipeSel_1"},  /* 21 */
+				     {"SDRAMPipeSel_0"},  /* 20 */
+				     {"SDRAMAddDel   "},  /* 19 */
+				     {"SDRAMClkSel   "},  /* 18 */
+				     {"Reserved(1!)  "},  /* 17 */
+				     {"PCIRty        "},  /* 16 */
+				     {"BootCSWidth_1 "},  /* 15 */
+				     {"BootCSWidth_0 "},  /* 14 */
+				     {"PCI1PadsCal   "},  /* 13 */
+				     {"PCI0PadsCal   "},  /* 12 */
+				     {"MultiMVId_1   "},  /* 11 */
+				     {"MultiMVId_0   "},  /* 10 */
+				     {"MultiGTEn     "},  /* 09 */
+				     {"Int60xArb     "},  /* 08 */
+				     {"CPUBusConfig_1"},  /* 07 */
+				     {"CPUBusConfig_0"},  /* 06 */
+				     {"DefIntSpc     "},  /* 05 */
+				     {0               },  /* 04 */
+				     {"SROMAdd_1     "},  /* 03 */
+				     {"SROMAdd_0     "},  /* 02 */
+				     {"DRAMPadCal    "},  /* 01 */
+				     {"SInitEn       "},  /* 00 */
+				     {0               },  /* 31 */
+				     {0               },  /* 30 */
+				     {0               },  /* 29 */
+				     {0               },  /* 28 */
+				     {0               },  /* 27 */
+				     {0               },  /* 26 */
+				     {0               },  /* 25 */
+				     {0               },  /* 24 */
+				     {0               },  /* 23 */
+				     {0               },  /* 22 */
+				     {"JTAGCalBy     "},  /* 21 */
+				     {"GB2Sel        "},  /* 20 */
+				     {"GB1Sel        "},  /* 19 */
+				     {"DRAMPLL_MDiv_5"},  /* 18 */
+				     {"DRAMPLL_MDiv_4"},  /* 17 */
+				     {"DRAMPLL_MDiv_3"},  /* 16 */
+				     {"DRAMPLL_MDiv_2"},  /* 15 */
+				     {"DRAMPLL_MDiv_1"},  /* 14 */
+				     {"DRAMPLL_MDiv_0"},  /* 13 */
+				     {"GB0Sel        "},  /* 12 */
+				     {"DRAMPLLPU     "},  /* 11 */
+				     {"DRAMPLL_HIKVCO"},  /* 10 */
+				     {"DRAMPLLNP     "},  /* 09 */
+				     {"DRAMPLL_NDiv_7"},  /* 08 */
+				     {"DRAMPLL_NDiv_6"},  /* 07 */
+				     {"CPUPadCal     "},  /* 06 */
+				     {"DRAMPLL_NDiv_5"},  /* 05 */
+				     {"DRAMPLL_NDiv_4"},  /* 04 */
+				     {"DRAMPLL_NDiv_3"},  /* 03 */
+				     {"DRAMPLL_NDiv_2"},  /* 02 */
+				     {"DRAMPLL_NDiv_1"},  /* 01 */
+				     {"DRAMPLL_NDiv_0"}}; /* 00 */
+
 extern void flush_data_cache (void);
 extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
@@ -901,21 +966,37 @@
 	dcache_disable ();
 }
 
-
-int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	unsigned int reset_sample_low;
 	unsigned int reset_sample_high;
+	unsigned int l, l1, l2;
 
 	GT_REG_READ(0x3c4, &reset_sample_low);
 	GT_REG_READ(0x3d4, &reset_sample_high);
 	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
 
+	l2 = 0;
+	for (l=0; l<63; l++) {
+		if (show_config_tab[l][0] != 0) {
+			printf("%14s:%1x ", show_config_tab[l],
+			       ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+			l2++;
+			if ((l2 % 4) == 0)
+				printf("\n");
+		} else {
+			l1++;
+		}
+		if (l == 32)
+			reset_sample_low = reset_sample_high;
+	}
+	printf("\n");
+
 	return(0);
 }
 
 U_BOOT_CMD(
-	show_cfg,	1,	1,	do_show_cfg,
-	"show_cfg- Show Marvell strapping register\n",
+	show_config,	1,	1,	do_show_config,
+	"show_config - Show Marvell strapping register\n",
 	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
 	);
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 01b90c6..0adafe2 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -43,6 +43,8 @@
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
 	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn == -1)
+	        devbusfn = pci_find_device (0x1095, 0x3114, 0);
 	if (devbusfn != -1) {
 		status = 0;
 
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
index ce7876c..0e5e57a 100644
--- a/board/esd/hh405/Makefile
+++ b/board/esd/hh405/Makefile
@@ -28,7 +28,10 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 9ef5907..67b5d54 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -5,7 +5,7 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -477,12 +477,6 @@
 	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Reset touch-screen controller
 	 */
 	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
@@ -690,20 +684,6 @@
 #endif /* CONFIG_IDE_RESET */
 
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/hub405/Makefile
+++ b/board/esd/hub405/Makefile
@@ -28,7 +28,9 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index dd3706e..25c8068 100644
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -153,12 +153,6 @@
 	out32(GPIO0_OR, val);
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * check board type and setup AP power
 	 */
 	str = getenv("bd_type"); /* this is only set on non prototype hardware */
@@ -242,33 +236,5 @@
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
-
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
index ce7876c..0e5e57a 100644
--- a/board/esd/plu405/Makefile
+++ b/board/esd/plu405/Makefile
@@ -28,7 +28,10 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 920f717..f026a7a 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -31,6 +32,8 @@
 #define FPGA_DEBUG
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 extern void lxt971_no_sleep(void);
 
@@ -114,6 +117,10 @@
 	int index;
 	int i;
 
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 	dst = malloc(CFG_FPGA_MAX_SIZE);
 	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
@@ -177,18 +184,12 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;
@@ -226,24 +227,10 @@
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
 
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
@@ -262,31 +249,6 @@
 #endif /* CONFIG_IDE_RESET */
 
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active)
-{
-	if (au_active) {
-		printf("\n Dies ist die board-funktion: Updating!!!\n");
-	} else {
-		printf("\n Dies ist die board-funktion: Updating done!!!\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/voh405/Makefile
+++ b/board/esd/voh405/Makefile
@@ -28,7 +28,9 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 3e118e7..2857a0b 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -195,12 +195,6 @@
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;
@@ -340,17 +334,3 @@
 	}
 }
 #endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/wuh405/Makefile
+++ b/board/esd/wuh405/Makefile
@@ -28,7 +28,9 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index 61d1d6c..dba3ce8 100644
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -170,12 +170,6 @@
 	udelay(1000); /* wait 1ms */
 
 	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
-	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
 	*duart0_mcr = 0x08;
@@ -218,35 +212,5 @@
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
diff --git a/board/fads/fads.h b/board/fads/fads.h
index c6f7ccd..a7fe2e9 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -71,7 +71,10 @@
 #undef CONFIG_BOOTARGS
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if !defined(CONFIG_MPC885ADS)
 #define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+#endif
 
 /*
  * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
similarity index 100%
rename from board/mpc8641hpcn/sys_eeprom.c
rename to board/freescale/common/sys_eeprom.c
diff --git a/board/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
similarity index 92%
rename from board/mpc8641hpcn/Makefile
rename to board/freescale/mpc8641hpcn/Makefile
index df56b31..93b015d 100644
--- a/board/mpc8641hpcn/Makefile
+++ b/board/freescale/mpc8641hpcn/Makefile
@@ -24,13 +24,14 @@
 include $(TOPDIR)/config.mk
 
 ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../freescale/common)
+$(shell mkdir -p $(obj)../common)
 endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o sys_eeprom.o \
-		../freescale/common/pixis.o
+COBJS	:= $(BOARD).o \
+		../common/sys_eeprom.o \
+		../common/pixis.o
 
 SOBJS	:= init.o
 
diff --git a/board/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk
similarity index 100%
rename from board/mpc8641hpcn/config.mk
rename to board/freescale/mpc8641hpcn/config.mk
diff --git a/board/mpc8641hpcn/init.S b/board/freescale/mpc8641hpcn/init.S
similarity index 100%
rename from board/mpc8641hpcn/init.S
rename to board/freescale/mpc8641hpcn/init.S
diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
similarity index 99%
rename from board/mpc8641hpcn/mpc8641hpcn.c
rename to board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 1bfbe88..ffd11cb 100644
--- a/board/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -33,7 +33,7 @@
 extern void ft_cpu_setup(void *blob, bd_t *bd);
 #endif
 
-#include "../freescale/common/pixis.h"
+#include "../common/pixis.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
diff --git a/board/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds
similarity index 98%
rename from board/mpc8641hpcn/u-boot.lds
rename to board/freescale/mpc8641hpcn/u-boot.lds
index 5864464..fd16362 100644
--- a/board/mpc8641hpcn/u-boot.lds
+++ b/board/freescale/mpc8641hpcn/u-boot.lds
@@ -51,7 +51,7 @@
   .text      :
   {
     cpu/mpc86xx/start.o	(.text)
-    board/mpc8641hpcn/init.o (.bootpg)
+    board/freescale/mpc8641hpcn/init.o (.bootpg)
     cpu/mpc86xx/traps.o (.text)
     cpu/mpc86xx/interrupts.o (.text)
     cpu/mpc86xx/cpu_init.o (.text)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 8249dce..bcb927f 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -924,16 +924,17 @@
 		initrd_end = 0;
 	}
 
+#if defined(CONFIG_OF_LIBFDT)
+
 #ifdef CFG_BOOTMAPSZ
 	/*
 	 * The blob must be within CFG_BOOTMAPSZ,
-	 * so we flag it to be copied if it is
+	 * so we flag it to be copied if it is not.
 	 */
 	if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
-		of_data = of_flat_tree;
+		of_data = (ulong)of_flat_tree;
 #endif
 
-#if defined(CONFIG_OF_LIBFDT)
 	/* move of_flat_tree if needed */
 	if (of_data) {
 		int err;
@@ -986,6 +987,15 @@
 #endif
 #endif /* CONFIG_OF_LIBFDT */
 #if defined(CONFIG_OF_FLAT_TREE)
+#ifdef CFG_BOOTMAPSZ
+	/*
+	 * The blob must be within CFG_BOOTMAPSZ,
+	 * so we flag it to be copied if it is not.
+	 */
+	if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
+		of_data = (ulong)of_flat_tree;
+#endif
+
 	/* move of_flat_tree if needed */
 	if (of_data) {
 		ulong of_start, of_len;
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index c72612d..254a775 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -468,14 +468,31 @@
 			   ulong offset, ulong addr, char *cmd)
 {
 	int r;
-	char *ep;
+	char *ep, *s;
 	ulong cnt;
 	image_header_t *hdr;
+	int jffs2 = 0;
+
+	s = strchr(cmd, '.');
+	if (s != NULL &&
+	    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")))
+		jffs2 = 1;
 
 	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
 
 	cnt = nand->oobblock;
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	if (jffs2) {
+		nand_read_options_t opts;
+		memset(&opts, 0, sizeof(opts));
+		opts.buffer	= (u_char*) addr;
+		opts.length	= cnt;
+		opts.offset	= offset;
+		opts.quiet      = 1;
+		r = nand_read_opts(nand, &opts);
+	} else {
+		r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	}
+
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-56);
@@ -495,8 +512,18 @@
 	print_image_hdr(hdr);
 
 	cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
+	if (jffs2) {
+		nand_read_options_t opts;
+		memset(&opts, 0, sizeof(opts));
+		opts.buffer	= (u_char*) addr;
+		opts.length	= cnt;
+		opts.offset	= offset;
+		opts.quiet      = 1;
+		r = nand_read_opts(nand, &opts);
+	} else {
+		r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	}
 
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
 		show_boot_progress (-58);
@@ -545,7 +572,7 @@
 			if (argc > 3)
 				goto usage;
 			if (argc == 3)
-				addr = simple_strtoul(argv[2], NULL, 16);
+				addr = simple_strtoul(argv[1], NULL, 16);
 			else
 				addr = CFG_LOAD_ADDR;
 			return nand_load_image(cmdtp, &nand_info[dev->id->num],
@@ -604,7 +631,7 @@
 
 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
 	"nboot   - boot from NAND device\n",
-	"[partition] | [[[loadAddr] dev] offset]\n");
+	"[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
 
 #endif
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index caaa682..175d59e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -46,7 +46,6 @@
 
 int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 {
-	bd_t *bd = gd->bd;
 	int   nodeoffset;
 	int   err;
 	u32   tmp;		/* used to set 32 bit integer properties */
diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c
index 4c4bc8d..8f1d8b2 100644
--- a/drivers/bios_emulator/besys.c
+++ b/drivers/bios_emulator/besys.c
@@ -47,9 +47,12 @@
 *
 ****************************************************************************/
 
-#include "biosemui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
+
+#include "biosemui.h"
+
 /*------------------------- Global Variables ------------------------------*/
 
 #ifndef __i386__
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index 7aa1bfb2e..70e9ce1 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -41,9 +41,12 @@
 *
 ****************************************************************************/
 
-#include "biosemui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
+
+#include "biosemui.h"
+
 /*----------------------------- Implementation ----------------------------*/
 
 /****************************************************************************
diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c
index 4c3aedf..ccfc872 100644
--- a/drivers/bios_emulator/biosemu.c
+++ b/drivers/bios_emulator/biosemu.c
@@ -45,11 +45,13 @@
 *
 ****************************************************************************/
 
-#include "biosemui.h"
 #include <malloc.h>
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "biosemui.h"
+
 BE_sysEnv _BE_env = {{0}};
 static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = {
 	BE_rdb,
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index 915739c..5cbcc95 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -37,11 +37,13 @@
 *
 ****************************************************************************/
 
-#include "x86emu/x86emui.h"
 #include <stdarg.h>
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*----------------------------- Implementation ----------------------------*/
 
 #ifdef DEBUG
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index 879f0a0..7a9a1dd 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -36,11 +36,12 @@
 *		instruction decoding and accessess of immediate data via IP.  etc.
 *
 ****************************************************************************/
-
-#include "x86emu/x86emui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*----------------------------- Implementation ----------------------------*/
 
 /****************************************************************************
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index d334fb5..a77bd9b 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -75,10 +75,12 @@
 *
 ****************************************************************************/
 
-#include "x86emu/x86emui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*----------------------------- Implementation ----------------------------*/
 
 /* constant arrays to do several instructions in just one function */
diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c
index 81c0d49..d6a210c 100644
--- a/drivers/bios_emulator/x86emu/ops2.c
+++ b/drivers/bios_emulator/x86emu/ops2.c
@@ -44,10 +44,12 @@
 *
 ****************************************************************************/
 
-#include "x86emu/x86emui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*----------------------------- Implementation ----------------------------*/
 
 /****************************************************************************
diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c
index c1152ea..2a254a4 100644
--- a/drivers/bios_emulator/x86emu/prim_ops.c
+++ b/drivers/bios_emulator/x86emu/prim_ops.c
@@ -97,11 +97,14 @@
 *
 ****************************************************************************/
 
+#include <common.h>
+
 #define PRIM_OPS_NO_REDEFINE_ASM
-#include "x86emu/x86emui.h"
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*------------------------- Global Variables ------------------------------*/
 
 static u32 x86emu_parity_tab[8] =
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index 566389f..dd44ff1 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -39,10 +39,12 @@
 *
 ****************************************************************************/
 
-#include "x86emu/x86emui.h"
+#include <common.h>
 
 #if defined(CONFIG_BIOSEMU)
 
+#include "x86emu/x86emui.h"
+
 /*------------------------- Global Variables ------------------------------*/
 
 X86EMU_sysEnv _X86EMU_env;	/* Global emulator machine state */
diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c
index 075cae6..6d7e347 100644
--- a/drivers/nand/nand_ids.c
+++ b/drivers/nand/nand_ids.c
@@ -123,6 +123,7 @@
 	{NAND_MFR_NATIONAL, "National"},
 	{NAND_MFR_RENESAS, "Renesas"},
 	{NAND_MFR_STMICRO, "ST Micro"},
+	{NAND_MFR_MICRON, "Micron"},
 	{0x0, "Unknown"}
 };
 #endif
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 89a7279..dc2765b 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1110,7 +1110,7 @@
 		if (dev->enetaddr[0] & 0x01) {
 			printf("%s: MacAddress is multcast address\n",
 				 __FUNCTION__);
-			return -EINVAL;
+			return 0;
 		}
 		uec_set_mac_address(uec, dev->enetaddr);
 		uec->the_first_run = 1;
@@ -1119,10 +1119,10 @@
 	err = uec_open(uec, COMM_DIR_RX_AND_TX);
 	if (err) {
 		printf("%s: cannot enable UEC device\n", dev->name);
-		return err;
+		return 0;
 	}
 
-	return 0;
+	return uec->mii_info->link;
 }
 
 static void uec_halt(struct eth_device* dev)
diff --git a/drivers/tsec.c b/drivers/tsec.c
index fd21ed4..6bca4dc 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -65,38 +65,30 @@
  *   FEC_PHYIDX
  */
 static struct tsec_info_struct tsec_info[] = {
-#if defined(CONFIG_TSEC1)
-#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
-	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
-#else
-	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC1
+	{TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
 #else
 	{0, 0, 0},
 #endif
-#if defined(CONFIG_TSEC2)
-#if defined(CONFIG_MPC8641HPCN)
-	{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
-#else
-	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC2
+	{TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
 #else
 	{0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_FEC
-	{FEC_PHY_ADDR, 0, FEC_PHYIDX},
+	{FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
 #else
-#if defined(CONFIG_TSEC3)
-	{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
+#ifdef CONFIG_TSEC3
+	{TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
 #else
 	{0, 0, 0},
 #endif
-#if defined(CONFIG_TSEC4)
-	{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#ifdef CONFIG_TSEC4
+	{TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
 #else
 	{0, 0, 0},
-#endif
-#endif
+#endif	/* CONFIG_TSEC4 */
+#endif	/* CONFIG_MPC85XX_FEC */
 };
 
 #define MAXCONTROLLERS	(4)
@@ -355,17 +347,16 @@
 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 {
 	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation
-	 * is not complete.
+	 * Wait if the link is up, and autonegotiation is in progress
+	 * (ie - we're capable and it's not done)
 	 */
 	mii_reg = read_phy_reg(priv, MIIM_STATUS);
-	if ((mii_reg & PHY_BMSR_AUTN_ABLE)
+	if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
 	    && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 		int i = 0;
 
 		puts("Waiting for PHY auto negotiation to complete");
-		while (!((mii_reg & PHY_BMSR_AUTN_COMP)
-			 && (mii_reg & MIIM_STATUS_LINK))) {
+		while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 			/*
 			 * Timeout reached ?
 			 */
@@ -385,7 +376,10 @@
 		priv->link = 1;
 		udelay(500000);	/* another 500 ms (results in faster booting) */
 	} else {
-		priv->link = 1;
+		if (mii_reg & MIIM_STATUS_LINK)
+			priv->link = 1;
+		else
+			priv->link = 0;
 	}
 
 	return 0;
@@ -525,16 +519,13 @@
 
 	mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 
-	if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
-	      (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
+	if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
+		!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 		int i = 0;
 
 		puts("Waiting for PHY realtime link");
-		while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
-			 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
-			/*
-			 * Timeout reached ?
-			 */
+		while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
+			/* Timeout reached ? */
 			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 				puts(" TIMEOUT !\n");
 				priv->link = 0;
@@ -549,6 +540,11 @@
 		}
 		puts(" done\n");
 		udelay(500000);	/* another 500 ms (results in faster booting) */
+	} else {
+		if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
+			priv->link = 1;
+		else
+			priv->link = 0;
 	}
 
 	if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 3d4816f..496fc72 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1596,7 +1596,7 @@
 	uint	svr;		/* 0xe00a4 - System version register */
 	char	res10a[8];
 	uint	rstcr;		/* 0xe00b0 - Reset control register */
-#ifdef MPC8568
+#ifdef CONFIG_MPC8568
 	char	res10b[76];
 	par_io_t qe_par_io[7];  /* 0xe0100 - 0xe01bf */
 	char	res10c[3136];
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 9e0ee37..0718c85 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -53,9 +53,13 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
+
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
@@ -144,39 +148,16 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 08ef9b5..1fd2b53 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -90,8 +90,6 @@
 #define CONFIG_CMD_EEPROM
 
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -157,34 +155,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 0a4e1e9..1b948f6 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -92,8 +92,6 @@
 
 #define CONFIG_SUPPORT_VFAT
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index ceeba6e..fb71c5f 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -114,8 +114,6 @@
 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 #endif
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 1aefbba..4994319 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -100,9 +100,6 @@
 
 #define CONFIG_SUPPORT_VFAT
 
-#define CFG_NAND_LEGACY
-
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index e2652e6..29f9292 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -111,8 +111,6 @@
 
 #undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 00f481c..ea8e61a 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -141,8 +141,6 @@
 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 #undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
 
-#define CFG_NAND_LEGACY
-
 #undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 #undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -209,34 +207,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 661b895..ed669c5 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -147,36 +147,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 81db96f..f92dce5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -310,6 +310,8 @@
 #define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR			0x1c
 #define TSEC2_PHY_ADDR			4
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC2_FLAGS			TSEC_GIGABIT
 #define TSEC1_PHYIDX			0
 #define TSEC2_PHYIDX			0
 
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 1567fcf..10af5f0 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -440,6 +440,8 @@
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 44649d0..58ee13d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -382,6 +382,7 @@
 #define CFG_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
 #endif
 
 #ifdef CONFIG_TSEC2
@@ -391,6 +392,7 @@
 #define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
+#define TSEC2_FLAGS		TSEC_GIGABIT
 #endif
 
 #define CONFIG_ETHPRIME		"Freescale TSEC"
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5a7c879..b774992 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -374,6 +374,8 @@
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 
 #if CONFIG_HAS_FEC
@@ -381,6 +383,7 @@
 #define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
+#define FEC_FLAGS		0
 #endif
 
 /* Options are: TSEC[0-1], FEC */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 0ce25cf..5c03ac8 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -224,6 +224,10 @@
 #define TSEC1_PHYIDX            0
 #define TSEC2_PHYIDX            0
 #define FEC_PHYIDX              0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define FEC_FLAGS		0
+
 /* Options are: TSEC[0-1], FEC */
 #define CONFIG_ETHPRIME                "TSEC0"
 
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 232f171..33a153e 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -384,13 +384,12 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
-#define FEC_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define FEC_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 32934e1..7863447 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -364,15 +364,13 @@
 #define CONFIG_TSEC1_NAME	"eTSEC1"
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
-#undef CONFIG_MPC85XX_FEC
-
-#define CONFIG_TSEC_TBI		1	/* enable internal TBI phy */
-#define CONFIG_SGMII_RISER
-#define TSEC1_SGMII_PHY_ADDR_OFFSET	0x1c	/* sgmii phy base */
 
 #define TSEC1_PHY_ADDR		0
 #define TSEC3_PHY_ADDR		1
 
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
 #define TSEC1_PHYIDX		0
 #define TSEC3_PHYIDX		0
 
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index cda9fd5..7345a3e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -447,6 +447,10 @@
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index e8fe99a..48a2663 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -384,13 +384,12 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
-#define FEC_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define FEC_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index c10e551..da41dad 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -360,11 +360,12 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index dc9cb1f..80ccda5 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -35,7 +35,7 @@
 
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
-#undef CONFIG_QE			/* Enable QE */
+#define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -348,7 +348,7 @@
  */
 #define CONFIG_UEC_ETH
 #ifndef CONFIG_TSEC_ENET
-#define CONFIG_ETHPRIME         "Freescale GETH"
+#define CONFIG_ETHPRIME         "FSL UEC0"
 #endif
 #define CONFIG_PHY_MODE_NEED_CHANGE
 #define CONFIG_eTSEC_MDIO_BUS
@@ -399,9 +399,6 @@
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
-#undef  CONFIG_TSEC3
-#undef  CONFIG_TSEC4
-#undef  CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
@@ -409,7 +406,10 @@
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
-/* Options are: eTSEC[0-3] */
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
 #define CONFIG_ETHPRIME		"eTSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 64dcbd0..e912331 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -417,6 +417,10 @@
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 
 #define CONFIG_ETHPRIME		"eTSEC1"
 
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 5470373..4acbcd5 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -96,7 +96,6 @@
 #define CONFIG_SUPPORT_VFAT
 
 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -168,36 +167,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
@@ -276,11 +254,6 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -306,9 +279,6 @@
 #define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
@@ -317,7 +287,7 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#if 1 /* test-only */
+
 /* CAT24WC08/16... */
 #define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
@@ -325,15 +295,6 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last 5 bits of the address	*/
-#endif
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index dbf9422..93090b9 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -270,11 +270,14 @@
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 #define CONFIG_MPC85XX_FEC	1
 #define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
+#define FEC_FLAGS		0
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 6bdfa5d..6105747 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -262,11 +262,12 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 #endif  /* CONFIG_TSEC_ENET */
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 661712b..91c1694 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -253,6 +253,8 @@
 #define TSEC2_PHY_ADDR			1
 #define TSEC1_PHYIDX			0
 #define TSEC2_PHYIDX			0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC0"
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d5ce3ba..cb9bf54 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -266,8 +266,11 @@
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
+#define FEC_FLAGS		0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 34f0ebd..3880ec7 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -153,36 +153,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index c1b3da8..656784a 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -145,38 +145,16 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
 
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 1831bef..aa515ea 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -410,6 +410,8 @@
 #define TSEC2_PHY_ADDR		0x1a
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"TSEC0"
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 68d31ca..760b754 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -380,6 +380,10 @@
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC4_FLAGS		TSEC_GIGABIT
 
 #define CFG_TBIPA_VALUE	0x1e	/* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 
@@ -492,7 +496,7 @@
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
     #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
     #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
@@ -513,7 +517,7 @@
 /* Cache Configuration */
 #define CFG_DCACHE_SIZE		32768
 #define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
@@ -525,7 +529,7 @@
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 1f41cf7..43b185b 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -234,12 +234,13 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 #define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 55e2c8d..3dae27a 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -260,12 +260,13 @@
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#define CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
 #define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4b48564..49ff80f 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -348,6 +348,7 @@
 #define NAND_MFR_NATIONAL	0x8f
 #define NAND_MFR_RENESAS	0x07
 #define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_MICRON		0x2c
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
diff --git a/include/nand.h b/include/nand.h
index 23493f7..3c0752e 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -32,6 +32,7 @@
 
 extern int nand_curr_device;
 extern nand_info_t nand_info[];
+extern void nand_init(void);
 
 static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
 {
diff --git a/net/tftp.c b/net/tftp.c
index 888ec98..d6db91c 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -614,4 +614,4 @@
 
 #endif /* Multicast TFTP */
 
-#endif /* CFG_CMD_NET */
+#endif