tree 6f2c45a89ceabac10b7abfe3f795ae16507b7d4d
parent 068962bb3675085aa4316d0b9a9b2f77424d9e70
author Andre Przywara <andre.przywara@arm.com> 1662391557 +0100
committer Andre Przywara <andre.przywara@arm.com> 1698014511 +0100

pinctrl: sunxi: add Allwinner D1 pinctrl description

Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>