diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index bbd6c15..bfa2d4a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -107,7 +107,7 @@
 #endif
 	}
 
-#ifdef CONFIG_SMP
+#if CONFIG_IS_ENABLED(SMP)
 	ret = riscv_init_ipi();
 	if (ret)
 		return ret;
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index 78fc6c8..b9a2c64 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -26,6 +26,9 @@
 
 int riscv_get_time(u64 *time)
 {
+	/* ensure timer register base has a sane value */
+	riscv_init_ipi();
+
 	*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
 
 	return 0;
@@ -33,6 +36,9 @@
 
 int riscv_set_timecmp(int hart, u64 cmp)
 {
+	/* ensure timer register base has a sane value */
+	riscv_init_ipi();
+
 	writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
 
 	return 0;
@@ -40,11 +46,13 @@
 
 int riscv_init_ipi(void)
 {
-	long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
+	if (!gd->arch.clint) {
+		long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
 
-	if (IS_ERR(ret))
-		return PTR_ERR(ret);
-	gd->arch.clint = ret;
+		if (IS_ERR(ret))
+			return PTR_ERR(ret);
+		gd->arch.clint = ret;
+	}
 
 	return 0;
 }