tree df338133e8def1152c763175f6c428442fee873f
parent 01ec498071189bf36bba70a21b507586467fce8d
author Pragnesh Patel <pragnesh.patel@sifive.com> 1590732214 +0530
committer Andes <uboot@andestech.com> 1591235049 +0800

riscv: cpu: fu540: Add support for cpu fu540

Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>