tree 36232fa5b868ef1572a9da4baebe235c84b5ac84
parent eb955440393f8580f88e01ccafc70231533755c8
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1414475539 +0530
committer Michal Simek <michal.simek@xilinx.com> 1422258957 +0100

ARM: zynq: slcr: Dont modify the reserved bits

Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>