| commit | 24f10caf7db555f17061617c21820d568d47619b | [log] [tgz] |
|---|---|---|
| author | Christian Marangi <ansuelsmth@gmail.com> | Sat Aug 03 10:43:25 2024 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Mon Aug 19 16:15:26 2024 -0600 |
| tree | 0552b2d21de8843ede60460e97476ed57964a6fa | |
| parent | 66b75e4f874bb8f0ee0f260088c536b41f97cbc7 [diff] |
clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also convert pericfg to mux + gate implementation as now we have also mux on top of gates. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>