ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7
Synchronize stm32f7 device tree with kernel v4.20.
All pinctrl bindings are updated.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index ceab5e5..bc337b1 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -19,7 +19,7 @@
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
- mmc0 = &sdio;
+ mmc0 = &sdio1;
spi0 = &qspi;
};
@@ -109,15 +109,15 @@
&pinctrl {
ethernet_mii: mii@0 {
pins {
- pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
- <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
- <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
- <STM32F746_PA2_FUNC_ETH_MDIO>,
- <STM32F746_PC1_FUNC_ETH_MDC>,
- <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
- <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
- <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
- <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
slew-rate = <2>;
};
};
@@ -126,99 +126,99 @@
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
- pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
- <STM32F746_PD9_FUNC_FMC_D14>,
- <STM32F746_PD8_FUNC_FMC_D13>,
- <STM32F746_PE15_FUNC_FMC_D12>,
- <STM32F746_PE14_FUNC_FMC_D11>,
- <STM32F746_PE13_FUNC_FMC_D10>,
- <STM32F746_PE12_FUNC_FMC_D9>,
- <STM32F746_PE11_FUNC_FMC_D8>,
- <STM32F746_PE10_FUNC_FMC_D7>,
- <STM32F746_PE9_FUNC_FMC_D6>,
- <STM32F746_PE8_FUNC_FMC_D5>,
- <STM32F746_PE7_FUNC_FMC_D4>,
- <STM32F746_PD1_FUNC_FMC_D3>,
- <STM32F746_PD0_FUNC_FMC_D2>,
- <STM32F746_PD15_FUNC_FMC_D1>,
- <STM32F746_PD14_FUNC_FMC_D0>,
+ pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D9 */
+ <STM32_PINMUX('E',11, AF12)>, /* D8 */
+ <STM32_PINMUX('E',10, AF12)>, /* D7 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D6 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D5 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D4 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D3 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D2 */
+ <STM32_PINMUX('D',15, AF12)>, /* D1 */
+ <STM32_PINMUX('D',14, AF12)>, /* D0 */
- <STM32F746_PE1_FUNC_FMC_NBL1>,
- <STM32F746_PE0_FUNC_FMC_NBL0>,
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
- <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
- <STM32F746_PG1_FUNC_FMC_A11>,
- <STM32F746_PG0_FUNC_FMC_A10>,
- <STM32F746_PF15_FUNC_FMC_A9>,
- <STM32F746_PF14_FUNC_FMC_A8>,
- <STM32F746_PF13_FUNC_FMC_A7>,
- <STM32F746_PF12_FUNC_FMC_A6>,
- <STM32F746_PF5_FUNC_FMC_A5>,
- <STM32F746_PF4_FUNC_FMC_A4>,
- <STM32F746_PF3_FUNC_FMC_A3>,
- <STM32F746_PF2_FUNC_FMC_A2>,
- <STM32F746_PF1_FUNC_FMC_A1>,
- <STM32F746_PF0_FUNC_FMC_A0>,
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A9 */
+ <STM32_PINMUX('F',14, AF12)>, /* A8 */
+ <STM32_PINMUX('F',13, AF12)>, /* A7 */
+ <STM32_PINMUX('F',12, AF12)>, /* A6 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A5 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A4 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A3 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A2 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A1 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A0 */
- <STM32F746_PH3_FUNC_FMC_SDNE0>,
- <STM32F746_PH5_FUNC_FMC_SDNWE>,
- <STM32F746_PF11_FUNC_FMC_SDNRAS>,
- <STM32F746_PG15_FUNC_FMC_SDNCAS>,
- <STM32F746_PC3_FUNC_FMC_SDCKE0>,
- <STM32F746_PG8_FUNC_FMC_SDCLK>;
+ <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+ <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
};
};
ltdc_pins: ltdc@0 {
pins {
- pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
- <STM32F746_PG12_FUNC_LCD_B4>,
- <STM32F746_PI9_FUNC_LCD_VSYNC>,
- <STM32F746_PI10_FUNC_LCD_HSYNC>,
- <STM32F746_PI14_FUNC_LCD_CLK>,
- <STM32F746_PI15_FUNC_LCD_R0>,
- <STM32F746_PJ0_FUNC_LCD_R1>,
- <STM32F746_PJ1_FUNC_LCD_R2>,
- <STM32F746_PJ2_FUNC_LCD_R3>,
- <STM32F746_PJ3_FUNC_LCD_R4>,
- <STM32F746_PJ4_FUNC_LCD_R5>,
- <STM32F746_PJ5_FUNC_LCD_R6>,
- <STM32F746_PJ6_FUNC_LCD_R7>,
- <STM32F746_PJ7_FUNC_LCD_G0>,
- <STM32F746_PJ8_FUNC_LCD_G1>,
- <STM32F746_PJ9_FUNC_LCD_G2>,
- <STM32F746_PJ10_FUNC_LCD_G3>,
- <STM32F746_PJ11_FUNC_LCD_G4>,
- <STM32F746_PJ13_FUNC_LCD_B1>,
- <STM32F746_PJ14_FUNC_LCD_B2>,
- <STM32F746_PJ15_FUNC_LCD_B3>,
- <STM32F746_PK0_FUNC_LCD_G5>,
- <STM32F746_PK1_FUNC_LCD_G6>,
- <STM32F746_PK2_FUNC_LCD_G7>,
- <STM32F746_PK4_FUNC_LCD_B5>,
- <STM32F746_PK5_FUNC_LCD_B6>,
- <STM32F746_PK6_FUNC_LCD_B7>,
- <STM32F746_PK7_FUNC_LCD_DE>;
+ pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
+ <STM32_PINMUX('G',12, AF14)>, /* B4 */
+ <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
+ <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
+ <STM32_PINMUX('I',14, AF14)>, /* CLK */
+ <STM32_PINMUX('I',15, AF14)>, /* R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* G2 */
+ <STM32_PINMUX('J',10, AF14)>, /* G3 */
+ <STM32_PINMUX('J',11, AF14)>, /* G4 */
+ <STM32_PINMUX('J',13, AF14)>, /* B1 */
+ <STM32_PINMUX('J',14, AF14)>, /* B2 */
+ <STM32_PINMUX('J',15, AF14)>, /* B3 */
+ <STM32_PINMUX('K', 0, AF14)>, /* G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* G7 */
+ <STM32_PINMUX('K', 4, AF14)>, /* B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* DE */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
- pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
- <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
- <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
- <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
- <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
- <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+ pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
+ <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+ <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
+ <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
+ <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
+ <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
slew-rate = <2>;
};
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_b: usart1@1 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;