Merge branch '2022-07-05-more-Kconfig-migrations' into next

- Migrate more CONFIG symbols to Kconfig, remove some dead code and
  clean-up arch/Kconfig.nxp slightly more.
diff --git a/README b/README
index c1d516b..6bdfca6 100644
--- a/README
+++ b/README
@@ -388,10 +388,6 @@
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 
-		CONFIG_SYS_FSL_DDR_EMU
-		Specify emulator support for DDR. Some DDR features such as
-		deskew training are not available.
-
 		CONFIG_SYS_FSL_DDRC_GEN1
 		Freescale DDR1 controller.
 
@@ -1306,11 +1302,6 @@
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
-		CONFIG_SYS_SPD_BUS_NUM
-
-		If defined, then this indicates the I2C bus number for DDR SPD.
-		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
-
 		CONFIG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
@@ -1518,20 +1509,6 @@
 		overwriting the architecture dependent default
 		settings.
 
-- Frame Buffer Address:
-		CONFIG_FB_ADDR
-
-		Define CONFIG_FB_ADDR if you want to use specific
-		address for frame buffer.  This is typically the case
-		when using a graphics controller has separate video
-		memory.  U-Boot will then place the frame buffer at
-		the given address instead of dynamically reserving it
-		in system RAM by calling lcd_setmem(), which grabs
-		the memory for the frame buffer depending on the
-		configured panel size.
-
-		Please see board_init_f function.
-
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -2088,12 +2065,6 @@
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
-- CONFIG_SYS_DDR_RAW_TIMING
-		Get DDR timing information from other than SPD. Common with
-		soldered DDR chips onboard without SPD. DDR raw timing
-		parameters are extracted from datasheet and hard-coded into
-		header files or board specific files.
-
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 
diff --git a/arch/Kconfig b/arch/Kconfig
index d35a590..6495e78 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -451,6 +451,12 @@
 source "arch/xtensa/Kconfig"
 source "arch/riscv/Kconfig"
 
+if ARM || M68K || PPC
+
+source "arch/Kconfig.nxp"
+
+endif
+
 source "board/keymile/Kconfig"
 
 if MIPS || MICROBLAZE
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
new file mode 100644
index 0000000..5971ec5
--- /dev/null
+++ b/arch/Kconfig.nxp
@@ -0,0 +1,240 @@
+config NXP_ESBC
+	bool "NXP ESBC (secure boot) functionality"
+	help
+	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
+	  If unsure, do not change.
+
+menu "Chain of trust / secure boot options"
+	depends on !FIT_SIGNATURE && NXP_ESBC
+
+config CHAIN_OF_TRUST
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select FSL_SEC_MON
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SPL_HASH if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	select CMD_EXT4 if ARM
+	select CMD_EXT4_WRITE if ARM
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	def_bool y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
+
+config ESBC_HDR_LS
+	bool
+
+config ESBC_ADDR_64BIT
+	def_bool y
+	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
+	help
+	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
+
+config SYS_FSL_SFP_BE
+	def_bool y
+	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
+
+config SYS_FSL_SFP_LE
+	def_bool y
+	depends on !SYS_FSL_SFP_BE
+
+choice
+	prompt "SFP IP revision"
+	default SYS_FSL_SFP_VER_3_0 if PPC
+	default SYS_FSL_SFP_VER_3_4
+
+config SYS_FSL_SFP_VER_3_0
+	bool "SFP version 3.0"
+
+config SYS_FSL_SFP_VER_3_2
+	bool "SFP version 3.2"
+
+config SYS_FSL_SFP_VER_3_4
+	bool "SFP version 3.4"
+
+endchoice
+
+config SPL_UBOOT_KEY_HASH
+	string "Non-SRK key hash for U-Boot public/private key pair"
+	depends on SPL
+	default ""
+	help
+	  Set the key hash for U-Boot here if public/private key pair used to
+	  sign U-boot are different from the SRK hash put in the fuse.  Example
+	  of a key hash is
+	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
+	  Otherwise leave this empty.
+
+if PPC
+
+config BOOTSCRIPT_COPY_RAM
+	bool "Secure boot copies boot script to RAM"
+	help
+	  On systems that support chain of trust booting, a number of addresses
+	  are required to set variables that are used in the copying and then
+	  verification of different parts of the system.  If enabled, the subsequent
+	  options are for what location to use in each step.
+
+config BS_ADDR_DEVICE
+	hex "Address in RAM for bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_SIZE
+	hex "The size of bs_size which is the amount read from bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_ADDR_RAM
+	hex "Address in RAM for bs_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_DEVICE
+	hex "Address in RAM for bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_SIZE
+	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_RAM
+	hex "Address in RAM for bs_hdr_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BOOTSCRIPT_HDR_ADDR
+	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
+	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
+
+endif
+
+config SYS_FSL_SRK_LE
+	def_bool y
+	depends on ARM
+
+config KEY_REVOCATION
+	def_bool y
+
+endmenu
+
+comment "Other functionality shared between NXP SoCs"
+
+config DEEP_SLEEP
+	bool "Enable SoC deep sleep feature"
+	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
+	default y
+	help
+	  Indicates this SoC supports deep sleep feature. If deep sleep is
+	  supported, core will start to execute uboot when wakes up.
+
+config LAYERSCAPE_NS_ACCESS
+	bool "Layerscape non-secure access support"
+	depends on ARCH_LS1021A || FSL_LSCH2
+
+config PCIE1
+	bool "PCIe controller #1"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+	bool "PCIe controller #2"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+	bool "PCIe controller #3"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+	bool "PCIe controller #4"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config FSL_USE_PCA9547_MUX
+	bool "Enable PCA9547 I2C Mux on Freescale boards"
+	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+	help
+	 This option enables the PCA9547 I2C mux on Freescale boards.
+
+config VID
+	bool "Enable Freescale VID"
+	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
+	help
+	 This option enables setting core voltage based on individual
+	 values saved in SoC fuses.
+
+config SPL_VID
+	bool "Enable Freescale VID in SPL"
+	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
+	help
+	 This option enables setting core voltage based on individual
+	 values saved in SoC fuses, in SPL.
+
+if VID || SPL_VID
+
+config VID_FLS_ENV
+	string "Environment variable for overriding VDD"
+	help
+	  This option allows for specifying the environment variable
+	  to check to override VDD information.
+
+config VOL_MONITOR_INA220
+	bool "Enable the INA220 voltage monitor read"
+	help
+	  This option enables INA220 voltage monitor read
+	  functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_READ
+	bool "Enable the IR36021 voltage monitor read"
+	help
+	 This option enables IR36021 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_SET
+	bool "Enable the IR36021 voltage monitor set"
+	help
+	 This option enables IR36021 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_LTC3882_READ
+	bool "Enable the LTC3882 voltage monitor read"
+	help
+	 This option enables LTC3882 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+	bool "Enable the LTC3882 voltage monitor set"
+	help
+	 This option enables LTC3882 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+	bool "Enable the ISL68233 voltage monitor read"
+	help
+	 This option enables ISL68233 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+	bool "Enable the ISL68233 voltage monitor set"
+	help
+	 This option enables ISL68233 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+endif
+
+config FSL_QIXIS
+	bool "Enable QIXIS support"
+	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+
+config QIXIS_I2C_ACCESS
+	bool "Access to QIXIS is over i2c"
+	depends on FSL_QIXIS
+	default y
+
+config HAS_FSL_DR_USB
+	def_bool y
+	depends on USB_EHCI_HCD && PPC
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index c496e64..a901360 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -41,12 +41,6 @@
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
-config NXP_ESBC
-	bool	"NXP_ESBC"
-	help
-		Enable Freescale Secure Boot feature. Normally selected
-		by defconfig. If unsure, do not change.
-
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index bfe0238..0985420 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -3,14 +3,13 @@
 # Copyright (C) 2009 Samsung Electronics
 # Minkyu Kang <mk7.kang@samsung.com>
 
+obj-$(CONFIG_PWM_S5P) += pwm.o
 ifdef CONFIG_ARCH_NEXELL
-obj-$(CONFIG_PWM_NX) += pwm.o
 obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
 else
 obj-y += cpu_info.o
 ifndef CONFIG_SPL_BUILD
 obj-y += timer.o
 obj-y += sromc.o
-obj-$(CONFIG_PWM) += pwm.o
 endif
 endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5a809b4..602b624 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -26,6 +26,7 @@
 config ARCH_LS1028A
 	bool
 	select ARMV8_SET_SMPEN
+	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
@@ -138,6 +139,7 @@
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
+	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
@@ -187,6 +189,7 @@
 	select ARM_ERRATA_828024
 	select ARM_ERRATA_829520
 	select ARM_ERRATA_833471
+	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
@@ -239,6 +242,7 @@
 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
+	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
@@ -277,6 +281,7 @@
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
+	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
@@ -456,11 +461,6 @@
 	 Enable the EMC2305 fan controller for configuration of fan
 	 speed.
 
-config NXP_ESBC
-	bool "NXP_ESBC"
-	help
-		Enable Freescale Secure Boot feature
-
 config QSPI_AHB_INIT
 	bool "Init the QSPI AHB bus"
 	help
@@ -511,6 +511,11 @@
 	depends on SYS_FSL_HAS_DP_DDR
 	default 2 if ARCH_LS2080A
 
+config DP_DDR_DIMM_SLOTS_PER_CTLR
+	int
+	depends on SYS_FSL_HAS_DP_DDR
+	default 1 if ARCH_LS2080A
+
 config DP_DDR_NUM_CTRLS
 	int
 	depends on SYS_FSL_HAS_DP_DDR
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 1315beb..cd795d6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -55,17 +55,6 @@
 /* SMMU Defintions */
 #define SMMU_BASE			0x05000000 /* GR0 Base */
 
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
-/* Security Monitor */
-#define CONFIG_SYS_FSL_SEC_MON_LE
-
-/* Secure Boot */
-#define CONFIG_ESBC_HDR_LS
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_CCSR_GUR_LE
 
@@ -160,17 +149,6 @@
 
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
-/* Security Monitor */
-#define CONFIG_SYS_FSL_SEC_MON_LE
-
-/* Secure Boot */
-#define CONFIG_ESBC_HDR_LS
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_CCSR_GUR_LE
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
@@ -215,17 +193,6 @@
 /* SMMU Definitions */
 #define SMMU_BASE				0x05000000 /* GR0 Base */
 
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
-/* Security Monitor */
-#define CONFIG_SYS_FSL_SEC_MON_LE
-
-/* Secure Boot */
-#define CONFIG_ESBC_HDR_LS
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_CCSR_GUR_LE
 
@@ -274,20 +241,9 @@
 
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
 /* SEC */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
-/* Security Monitor */
-#define CONFIG_SYS_FSL_SEC_MON_LE
-
-/* Secure Boot */
-#define CONFIG_ESBC_HDR_LS
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_CCSR_GUR_LE
 
@@ -321,11 +277,6 @@
 #define QE_NUM_OF_SNUM		28
 
 #define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
 
 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000
@@ -361,11 +312,6 @@
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
@@ -380,11 +326,6 @@
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
 
 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index aa790ab..796e2b2 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -87,10 +87,6 @@
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
 
 #define DCU_LAYER_MAX_NUM			16
 
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index b0c7599..a4f4961 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -8,31 +8,6 @@
 #define __FSL_SECURE_BOOT_H
 
 #ifdef CONFIG_CHAIN_OF_TRUST
-#define CONFIG_FSL_SEC_MON
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Define the key hash for U-Boot here if public/private key pair used to
- * sign U-boot are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_SPL_UBOOT_KEY_HASH \
- *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- * else leave it defined as NULL
- */
-
-#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
-#endif /* ifdef CONFIG_SPL_BUILD */
-
-#define CONFIG_KEY_REVOCATION
-
-#if defined(CONFIG_FSL_LAYERSCAPE)
-/*
- * For fsl layerscape based platforms, ESBC image Address in Header
- * is 64 bit.
- */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images
@@ -47,76 +22,6 @@
  */
 #define CONFIG_FSL_ISBC_KEY_EXT
 
-#endif
-
-#ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_EXTRA_ENV \
-	"setenv fdt_high 0xa0000000;"	\
-	"setenv initrd_high 0xcfffffff;"	\
-	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
-#else
-#define CONFIG_EXTRA_ENV \
-	"setenv fdt_high 0xffffffff;"	\
-	"setenv initrd_high 0xffffffff;"	\
-	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
-#endif
-
-/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
- * Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
-	defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#endif
-/* The address needs to be modified according to NOR, NAND, SD and
- * DDR memory map
- */
-#ifdef CONFIG_FSL_LSCH3
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_BS_ADDR_DEVICE		0x20600000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x20640000
-#else /* NOR BOOT */
-#define CONFIG_BS_ADDR_DEVICE		0x580600000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x580640000
-#endif /*ifdef CONFIG_QSPI_BOOT */
-#define CONFIG_BS_SIZE			0x00001000
-#define CONFIG_BS_HDR_SIZE		0x00004000
-#define CONFIG_BS_ADDR_RAM		0xa0600000
-#define CONFIG_BS_HDR_ADDR_RAM		0xa0640000
-#else
-#ifdef CONFIG_SD_BOOT
-/* For SD boot address and size are assigned in terms of sector
- * offset and no. of sectors respectively.
- */
-#define CONFIG_BS_ADDR_DEVICE		0x00003000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x00003200
-#define CONFIG_BS_SIZE			0x00000008
-#define CONFIG_BS_HDR_SIZE		0x00000010
-#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_BS_ADDR_DEVICE		0x00600000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x00640000
-#define CONFIG_BS_SIZE			0x00001000
-#define CONFIG_BS_HDR_SIZE		0x00002000
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BS_ADDR_DEVICE		0x40600000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x40640000
-#define CONFIG_BS_SIZE			0x00001000
-#define CONFIG_BS_HDR_SIZE		0x00002000
-#else /* Default NOR Boot */
-#define CONFIG_BS_ADDR_DEVICE		0x60600000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x60640000
-#define CONFIG_BS_SIZE			0x00001000
-#define CONFIG_BS_HDR_SIZE		0x00002000
-#endif
-#define CONFIG_BS_ADDR_RAM		0x81000000
-#define CONFIG_BS_HDR_ADDR_RAM		0x81020000
-#endif
-
-#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
-#define CONFIG_BOOTSCRIPT_ADDR		CONFIG_BS_ADDR_RAM
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
-#else
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_DEVICE
-/* BOOTSCRIPT_ADDR is not required */
 #endif
 
 #ifdef CONFIG_FSL_LS_PPA
@@ -129,7 +34,6 @@
 #define PPA_KEY_HASH		NULL
 #endif /* ifdef CONFIG_FSL_LS_PPA */
 
-#include <config_fsl_chain_trust.h>
 #endif /* #ifndef CONFIG_SPL_BUILD */
 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 #endif
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca2da00..98bb10c 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -121,6 +121,18 @@
 config SYS_SOC
 	default "kirkwood"
 
+config KIRKWOOD_RGMII_PAD_1V8
+	bool "Configures the I/O voltage of the pads connected gigabit interface to 1.8V"
+	default y
+
+config KIRKWOOD_EGIGA_INIT
+	bool "Enable GbePort0/1 for kernel"
+	default y
+
+config KIRKWOOD_PCIE_INIT
+	bool "Enable PCIe Port0 for kernel"
+	default y
+
 source "board/Marvell/openrd/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Synology/ds109/Kconfig"
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index ca34157..90e86ab 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -23,9 +23,6 @@
 #endif /* CONFIG_KW88F6281 */
 
 #include <asm/arch/soc.h>
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
 
 #define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
 #define MV_UART_CONSOLE_BASE	KW_UART0_BASE
diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile
index ba90fc3..6a38c48 100644
--- a/arch/m68k/cpu/mcf5445x/Makefile
+++ b/arch/m68k/cpu/mcf5445x/Makefile
@@ -6,4 +6,4 @@
 # ccflags-y += -DET_DEBUG
 
 extra-y	= start.o
-obj-y	= cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c
deleted file mode 100644
index d487468..0000000
--- a/arch/m68k/cpu/mcf5445x/pci.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * PCI Configuration space access support
- */
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/immap.h>
-#include <linux/delay.h>
-
-#if defined(CONFIG_PCI)
-/* System RAM mapped over PCI */
-#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
-#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
-
-#define PCI_OP(rw, size, type, op, mask)				\
-int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
-	pci_dev_t dev, int offset, type val)				\
-{									\
-	u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev),	\
-				     PCI_FUNC(dev), offset);		\
-	out_be32(hose->cfg_addr, addr);					\
-	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
-	out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE);		\
-	return 0;							\
-}
-
-PCI_OP(read, byte, u8 *, in_8, 3)
-PCI_OP(read, word, u16 *, in_le16, 2)
-PCI_OP(read, dword, u32 *, in_le32, 0)
-PCI_OP(write, byte, u8, out_8, 3)
-PCI_OP(write, word, u16, out_le16, 2)
-PCI_OP(write, dword, u32, out_le32, 0)
-
-void pci_mcf5445x_init(struct pci_controller *hose)
-{
-	pci_t *pci = (pci_t *)MMAP_PCI;
-	pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	u32 barEn = 0;
-
-	out_be32(&pciarb->acr, 0x001f001f);
-
-	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
-	   PCIREQ2, PCIGNT2 */
-	out_be16(&gpio->par_pci,
-		GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
-		GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
-		GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
-		GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
-
-	/* Assert reset bit */
-	setbits_be32(&pci->gscr, PCI_GSCR_PR);
-
-	setbits_be32(&pci->tcr1, PCI_TCR1_P);
-
-	/* Initiator windows */
-	out_be32(&pci->iw0btar,
-		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
-	out_be32(&pci->iw1btar,
-		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
-	out_be32(&pci->iw2btar,
-		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
-
-	out_be32(&pci->iwcr,
-		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
-		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
-
-	out_be32(&pci->icr, 0);
-
-	/* Enable bus master and mem access */
-	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
-
-	/* Cache line size and master latency */
-	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
-	out_be32(&pci->cr2, 0);
-
-#ifdef CONFIG_SYS_PCI_BAR0
-	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
-	out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B0E;
-#endif
-#ifdef CONFIG_SYS_PCI_BAR1
-	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
-	out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B1E;
-#endif
-#ifdef CONFIG_SYS_PCI_BAR2
-	out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
-	out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B2E;
-#endif
-#ifdef CONFIG_SYS_PCI_BAR3
-	out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
-	out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B3E;
-#endif
-#ifdef CONFIG_SYS_PCI_BAR4
-	out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
-	out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B4E;
-#endif
-#ifdef CONFIG_SYS_PCI_BAR5
-	out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
-	out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
-	barEn |= PCI_TCR2_B5E;
-#endif
-
-	out_be32(&pci->tcr2, barEn);
-
-	/* Deassert reset bit */
-	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
-	udelay(1000);
-
-	/* Enable PCI bus master support */
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
-		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
-	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
-		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
-		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 3;
-
-	hose->cfg_addr = &(pci->car);
-	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
-
-	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
-		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
-		    pci_write_cfg_dword);
-
-	/* Hose scan */
-	pci_register_hose(hose);
-	hose->last_busno = pci_hose_scan(hose);
-}
-#endif				/* CONFIG_PCI */
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 02efa1c..e7003d3 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -187,6 +187,7 @@
 	select E500MC
 	select E6500
 	select FSL_LAW
+	select HETROGENOUS_CLUSTERS
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005871
@@ -195,7 +196,7 @@
 	select SYS_FSL_ERRATUM_A006475
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007075
-	select SYS_FSL_ERRATUM_A007186
+	select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
@@ -214,6 +215,7 @@
 	select E500MC
 	select E6500
 	select FSL_LAW
+	select HETROGENOUS_CLUSTERS
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A005871
@@ -222,7 +224,7 @@
 	select SYS_FSL_ERRATUM_A006475
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007075
-	select SYS_FSL_ERRATUM_A007186
+	select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
@@ -733,7 +735,7 @@
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
-	select SYS_FSL_ERRATUM_A007186
+	select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
@@ -766,7 +768,7 @@
 	select SYS_FSL_ERRATUM_A006261
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
-	select SYS_FSL_ERRATUM_A007186
+	select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
 	select SYS_FSL_ERRATUM_A007798
 	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
@@ -822,11 +824,8 @@
 	help
 		Use Freescale common code for Local Access Window
 
-config NXP_ESBC
-	bool	"NXP_ESBC"
-	help
-		Enable Freescale Secure Boot feature. Normally selected
-		by defconfig. If unsure, do not change.
+config HETROGENOUS_CLUSTERS
+	bool
 
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for MPC85xx"
@@ -1121,6 +1120,35 @@
 		Number of TLB CAM entries for Book-E chips. 64 for E500MC,
 		16 for other E500 SoCs.
 
+if HETROGENOUS_CLUSTERS
+
+config SYS_MAPLE
+	def_bool y
+
+config SYS_CPRI
+	def_bool y
+
+config PPC_CLUSTER_START
+	int
+	default 0
+
+config DSP_CLUSTER_START
+	int
+	default 1
+
+config SYS_CPRI_CLK
+	int
+	default 3
+
+config SYS_ULB_CLK
+	int
+	default 4
+
+config SYS_ETVPE_CLK
+	int
+	default 1
+endif
+
 config BACKSIDE_L2_CACHE
 	bool
 
@@ -1185,6 +1213,9 @@
 		Defines divider of platform clock(clock input to
 		eLBC controller).
 
+config ENABLE_36BIT_PHYS
+	bool "Enable 36bit physical address space support"
+
 config SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up"
 	depends on MPC85xx
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 06f66d0..a43e6e5 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -18,8 +18,6 @@
 
 /* IP endianness */
 #define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SEC_MON_BE
 
 #if defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
@@ -35,7 +33,6 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_ARCH_P1011)
@@ -150,7 +147,6 @@
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
-#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_FSL_SDHC_V2_3
@@ -162,7 +158,6 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_ARCH_T4240)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -200,32 +195,21 @@
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
-#define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
-#define CONFIG_PPC_CLUSTER_START	0 /*Start index of ppc clusters*/
-#define CONFIG_DSP_CLUSTER_START	1 /*Start index of dsp clusters*/
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_MAPLE
-#define CONFIG_SYS_CPRI
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FM1_CLK		0
-#define CONFIG_SYS_CPRI_CLK		3
-#define CONFIG_SYS_ULB_CLK		4
-#define CONFIG_SYS_ETVPE_CLK		1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
@@ -273,7 +257,6 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
-#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T1024)
 #define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
@@ -300,7 +283,6 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
-#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T2080)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -310,7 +292,6 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCI_VER_3_X
 #if defined(CONFIG_ARCH_T2080)
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	4
@@ -330,10 +311,8 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER		2
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
-#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 
 #elif defined(CONFIG_ARCH_C29X)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 3a1d858..a96a1ac 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -10,19 +10,12 @@
 #ifdef CONFIG_NXP_ESBC
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
-#elif defined(CONFIG_TARGET_BSC9132QDS)
-#define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
-#elif defined(CONFIG_TARGET_C29XPCIE)
-#define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
 #else
 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
 #endif
 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
-#if defined(CONFIG_TARGET_B4860QDS) || \
-	defined(CONFIG_TARGET_B4420QDS) || \
-	defined(CONFIG_TARGET_T4240QDS) || \
-	defined(CONFIG_TARGET_T2080QDS) || \
+#if defined(CONFIG_TARGET_T2080QDS) || \
 	defined(CONFIG_TARGET_T2080RDB) || \
 	defined(CONFIG_TARGET_T1042RDB) || \
 	defined(CONFIG_TARGET_T1042D4RDB) || \
@@ -31,7 +24,6 @@
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_CPC_REINIT_F
 #endif
-#define CONFIG_KEY_REVOCATION
 #undef CONFIG_SYS_INIT_L3_ADDR
 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
 #endif
@@ -47,10 +39,6 @@
 #endif
 #endif
 
-#if defined(CONFIG_TARGET_C29XPCIE)
-#define CONFIG_KEY_REVOCATION
-#endif
-
 #if defined(CONFIG_ARCH_P3041)	||	\
 	defined(CONFIG_ARCH_P4080) ||	\
 	defined(CONFIG_ARCH_P5040) ||	\
@@ -80,55 +68,9 @@
 #define CONFIG_SPL_SPAACT_ADDR		0x2f000000
 #define CONFIG_SPL_JR0_LIODN_S		454
 #define CONFIG_SPL_JR0_LIODN_NS		458
-/*
- * Define the key hash for U-Boot here if public/private key pair used to
- * sign U-boot are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_SPL_UBOOT_KEY_HASH \
- *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- * else leave it defined as NULL
- */
-
-#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
 #endif /* ifdef CONFIG_SPL_BUILD */
 
-#define CONFIG_FSL_SEC_MON
-
 #ifndef CONFIG_SPL_BUILD
-/*
- * fsl_setenv_chain_of_trust() must be called from
- * board_late_init()
- */
-
-/* If Boot Script is not on NOR and is required to be copied on RAM */
-#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
-#define CONFIG_BS_HDR_ADDR_RAM		0x00010000
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x00800000
-#define CONFIG_BS_HDR_SIZE		0x00002000
-#define CONFIG_BS_ADDR_RAM		0x00012000
-#define CONFIG_BS_ADDR_DEVICE		0x00802000
-#define CONFIG_BS_SIZE			0x00001000
-
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
-#else
-
-/* The bootscript header address is different for B4860 because the NOR
- * mapping is different on B4 due to reduced NOR size.
- */
-#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
-#elif defined(CONFIG_FSL_CORENET)
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
-#elif defined(CONFIG_TARGET_BSC9132QDS)
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
-#elif defined(CONFIG_TARGET_C29XPCIE)
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
-#else
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
-#endif
-
-#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
-
 #include <config_fsl_chain_trust.h>
 #endif /* #ifndef CONFIG_SPL_BUILD */
 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
diff --git a/board/advantech/imx8mp_rsb3720a1/Kconfig b/board/advantech/imx8mp_rsb3720a1/Kconfig
index 4486ed6..95cac7c 100644
--- a/board/advantech/imx8mp_rsb3720a1/Kconfig
+++ b/board/advantech/imx8mp_rsb3720a1/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "imx8mp_rsb3720"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig
index 8bf3a7d..c846537 100644
--- a/board/advantech/imx8qm_rom7720_a1/Kconfig
+++ b/board/advantech/imx8qm_rom7720_a1/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/advantech/imx8qm_rom7720_a1/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig
index 63f064e..e5d8aa3 100644
--- a/board/beacon/imx8mm/Kconfig
+++ b/board/beacon/imx8mm/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig
index fb30139..e11286c 100644
--- a/board/beacon/imx8mn/Kconfig
+++ b/board/beacon/imx8mn/Kconfig
@@ -18,6 +18,4 @@
 config IMX_CONFIG
 	default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/bsh/imx8mn_smm_s2/Kconfig b/board/bsh/imx8mn_smm_s2/Kconfig
index f43d058..041a9c7 100644
--- a/board/bsh/imx8mn_smm_s2/Kconfig
+++ b/board/bsh/imx8mn_smm_s2/Kconfig
@@ -22,8 +22,6 @@
 	def_bool y
 	select BSH_SMM_S2_DDR3L_256
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_IMX8MN_BSH_SMM_S2PRO
@@ -44,6 +42,4 @@
 	def_bool y
 	select BSH_SMM_S2_DDR3L_512
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig
index d4a238d..a1f2139 100644
--- a/board/congatec/common/Kconfig
+++ b/board/congatec/common/Kconfig
@@ -1,44 +1,3 @@
-if !ARCH_IMX8M && !ARCH_IMX8
-
-config CHAIN_OF_TRUST
-	depends on !FIT_SIGNATURE && SECURE_BOOT
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	select FSL_CAAM
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	bool
-	default y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y if CHAIN_OF_TRUST
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-endif
-
-config VOL_MONITOR_LTC3882_READ
-	depends on VID
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	depends on VID
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by common VID driver.
-
 config USB_TCPC
 	bool "USB Typec port controller simple driver"
 	help
diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
index 348fcf3..99edaa3 100644
--- a/board/emulation/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -32,6 +32,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Virtual address range for PCI region maps */
+#define SYS_PCI_MAP_START	0x80000000
+#define SYS_PCI_MAP_END		0xe0000000
+
 static void *get_fdt_virt(void)
 {
 	if (gd->flags & GD_FLG_RELOC)
@@ -101,7 +105,7 @@
 	map_addr += size - 1;
 	map_addr &= ~(size - 1);
 
-	if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
+	if (map_addr + size >= SYS_PCI_MAP_END)
 		return -1;
 
 	/* Map virtual memory for range */
@@ -137,7 +141,7 @@
 	pci_get_regions(dev, &io, &mem, &pre);
 
 	/* Start MMIO and PIO range maps above RAM */
-	map_addr = CONFIG_SYS_PCI_MAP_START;
+	map_addr = SYS_PCI_MAP_START;
 
 	/* Map MMIO range */
 	ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig
index 5495b3b..3b3b93b 100644
--- a/board/engicam/imx8mm/Kconfig
+++ b/board/engicam/imx8mm/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
deleted file mode 100644
index 195fc47..0000000
--- a/board/freescale/common/Kconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-config CHAIN_OF_TRUST
-	depends on !FIT_SIGNATURE && NXP_ESBC
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	select FSL_CAAM
-	select ARCH_MISC_INIT
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SPL_HASH if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	bool
-	default y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y if CHAIN_OF_TRUST
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-config DEEP_SLEEP
-	bool "Enable SoC deep sleep feature"
-	default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
-	help
-	  Indicates this SoC supports deep sleep feature. If deep sleep is
-	  supported, core will start to execute uboot when wakes up.
-
-config FSL_USE_PCA9547_MUX
-	bool "Enable PCA9547 I2C Mux on Freescale boards"
-	help
-	 This option enables the PCA9547 I2C mux on Freescale boards.
-
-config VID
-	bool "Enable Freescale VID"
-	depends on I2C || DM_I2C
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses.
-
-config SPL_VID
-	bool "Enable Freescale VID in SPL"
-	depends on I2C || DM_I2C
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses, in SPL.
-
-if VID || SPL_VID
-
-config VID_FLS_ENV
-	string "Environment variable for overriding VDD"
-	help
-	  This option allows for specifying the environment variable
-	  to check to override VDD information.
-
-config VOL_MONITOR_INA220
-	bool "Enable the INA220 voltage monitor read"
-	help
-	  This option enables INA220 voltage monitor read
-	  functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_READ
-	bool "Enable the IR36021 voltage monitor read"
-	help
-	 This option enables IR36021 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_SET
-	bool "Enable the IR36021 voltage monitor set"
-	help
-	 This option enables IR36021 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_READ
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_READ
-	bool "Enable the ISL68233 voltage monitor read"
-	help
-	 This option enables ISL68233 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_SET
-	bool "Enable the ISL68233 voltage monitor set"
-	help
-	 This option enables ISL68233 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-endif
-
-config FSL_QIXIS
-	bool "Enable QIXIS support"
-
-config QIXIS_I2C_ACCESS
-	bool "Access to QIXIS is over i2c"
-	depends on FSL_QIXIS
-	default y
-
-config HAS_FSL_DR_USB
-	def_bool y
-	depends on USB_EHCI_HCD && PPC
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 7ffb315..d31fb82 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -12,6 +12,7 @@
 #include <fsl_sfp.h>
 #include <log.h>
 #include <dm/root.h>
+#include <asm/fsl_secure_boot.h>
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
 #include <spl.h>
@@ -76,14 +77,14 @@
 
 	/* If Boot mode is Secure, set the environment variables
 	 * bootdelay = 0 (To disable Boot Prompt)
-	 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
+	 * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script)
 	 */
 	env_set("bootdelay", "-2");
 
 #ifdef CONFIG_ARM
 	env_set("secureboot", "y");
 #else
-	env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+	env_set("bootcmd", CHAIN_BOOT_CMD);
 #endif
 
 	return 0;
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 34875d0..f1a0b0c 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -871,7 +871,7 @@
 	int ret, i, hash_cmd = 0;
 	u32 srk_hash[8];
 
-	if (arg_hash_str != NULL) {
+	if (strlen(arg_hash_str) != 0) {
 		const char *cp = arg_hash_str;
 		int i = 0;
 
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 0860bd2..af76327 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -166,4 +166,25 @@
 #define QIXIS_ESDHC_NO_ADAPTER		0x7
 #endif
 
+/*
+ * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
+ */
+static inline u8 qixis_esdhc_detect_quirk(void)
+{
+	/*
+	 * SDHC1 Card ID:
+	 * Specifies the type of card installed in the SDHC1 adapter slot.
+	 * 000= (reserved)
+	 * 001= eMMC V4.5 adapter is installed.
+	 * 010= SD/MMC 3.3V adapter is installed.
+	 * 011= eMMC V4.4 adapter is installed.
+	 * 100= eMMC V5.0 adapter is installed.
+	 * 101= MMC card/Legacy (3.3V) adapter is installed.
+	 * 110= SDCard V2/V3 adapter installed.
+	 * 111= no adapter is installed.
+	 */
+	return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
+		 QIXIS_ESDHC_NO_ADAPTER);
+}
+
 #endif
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index e92b0d0..dbcd1af 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -9,8 +9,6 @@
 config SYS_CONFIG_NAME
 	default "P3041DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_P4080DS
@@ -24,8 +22,6 @@
 config SYS_CONFIG_NAME
 	default "P4080DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_P5040DS
@@ -39,6 +35,4 @@
 config SYS_CONFIG_NAME
 	default "P5040DS"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
index 0adf87b..a148a9b 100644
--- a/board/freescale/imx8mn_evk/Kconfig
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -15,6 +15,4 @@
 config IMX_CONFIG
 	default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig
index 42625fd..cafa632 100644
--- a/board/freescale/imx8mp_evk/Kconfig
+++ b/board/freescale/imx8mp_evk/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig
index aed6ab2..5f2413f 100644
--- a/board/freescale/imx8qm_mek/Kconfig
+++ b/board/freescale/imx8qm_mek/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/freescale/imx8qm_mek/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig
index b9aab37..6533b4d 100644
--- a/board/freescale/imx8qxp_mek/Kconfig
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/freescale/imx8qxp_mek/imximage.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig
index 1e461ee..4637b96 100644
--- a/board/freescale/imx8ulp_evk/Kconfig
+++ b/board/freescale/imx8ulp_evk/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "imx8ulp_evk"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 4ac69d7..75de782af 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -89,7 +89,3 @@
 	hex "length of PFE Firmware HDR"
 	default 0xc00
 endif
-
-if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
-source "board/freescale/common/Kconfig"
-endif
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index 59b1a87..991ba60 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -77,7 +77,4 @@
 
 endif
 
-
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index c4acea3..aa15f5a 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -63,8 +63,6 @@
 
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_LS1012A2G5RDB
@@ -119,6 +117,4 @@
 
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
index c6b1606..4a12c16 100644
--- a/board/freescale/ls1021aiot/Kconfig
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -12,6 +12,4 @@
 config SYS_CONFIG_NAME
 	default "ls1021aiot"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
index 60b8472..119b955 100644
--- a/board/freescale/ls1021aqds/Kconfig
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -12,6 +12,4 @@
 config SYS_CONFIG_NAME
 	default "ls1021aqds"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig
index d999fa4..aa42a06 100644
--- a/board/freescale/ls1021atsn/Kconfig
+++ b/board/freescale/ls1021atsn/Kconfig
@@ -13,6 +13,4 @@
 config SYS_CONFIG_NAME
 	default "ls1021atsn"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
index a4641cb..bc50b8d 100644
--- a/board/freescale/ls1021atwr/Kconfig
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -12,6 +12,4 @@
 config SYS_CONFIG_NAME
 	default "ls1021atwr"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index 4093981..5c27f0f 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -32,8 +32,6 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
 
 if TARGET_LS1028ARDB
@@ -58,6 +56,4 @@
 	default 0x82000000 if TFABOOT
 	default 0x20100000
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
index 182900e..4be445e 100644
--- a/board/freescale/ls1043aqds/Kconfig
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -28,6 +28,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index d66c780..56502f9 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -27,6 +27,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig
index 6a4c3e9..68329d7 100644
--- a/board/freescale/ls1046afrwy/Kconfig
+++ b/board/freescale/ls1046afrwy/Kconfig
@@ -13,5 +13,4 @@
 config SYS_CONFIG_NAME
 	default "ls1046afrwy"
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
index 1616dcc..adf325f 100644
--- a/board/freescale/ls1046aqds/Kconfig
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -28,6 +28,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
index 4c31e0e..1fb391c 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -27,5 +27,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig
index 8bb828e..f1a4523 100644
--- a/board/freescale/ls1088a/Kconfig
+++ b/board/freescale/ls1088a/Kconfig
@@ -26,7 +26,6 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LS1088ARDB
@@ -57,5 +56,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 6b2b645..1036f33 100644
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -29,6 +29,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 678d582..c8b0b94 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -12,8 +12,6 @@
 config SYS_CONFIG_NAME
 	default "ls2080ardb"
 
-source "board/freescale/common/Kconfig"
-
 if FSL_LS_PPA
 config SYS_LS_PPA_FW_ADDR
 	hex "PPA Firmware Addr"
@@ -30,6 +28,4 @@
 endif
 endif
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig
index 7556f7d..0e4b415 100644
--- a/board/freescale/lx2160a/Kconfig
+++ b/board/freescale/lx2160a/Kconfig
@@ -12,7 +12,6 @@
 config SYS_CONFIG_NAME
 	default "lx2160ardb"
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LX2160AQDS
@@ -29,7 +28,6 @@
 config SYS_CONFIG_NAME
 	default "lx2160aqds"
 
-source "board/freescale/common/Kconfig"
 endif
 
 if TARGET_LX2162AQDS
@@ -46,5 +44,4 @@
 config SYS_CONFIG_NAME
 	default "lx2162aqds"
 
-source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 49d96d3..a078643 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -356,27 +356,6 @@
 }
 
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
-/*
- * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
- */
-u8 qixis_esdhc_detect_quirk(void)
-{
-	/*
-	 * SDHC1 Card ID:
-	 * Specifies the type of card installed in the SDHC1 adapter slot.
-	 * 000= (reserved)
-	 * 001= eMMC V4.5 adapter is installed.
-	 * 010= SD/MMC 3.3V adapter is installed.
-	 * 011= eMMC V4.4 adapter is installed.
-	 * 100= eMMC V5.0 adapter is installed.
-	 * 101= MMC card/Legacy (3.3V) adapter is installed.
-	 * 110= SDCard V2/V3 adapter installed.
-	 * 111= no adapter is installed.
-	 */
-	return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
-		 QIXIS_ESDHC_NO_ADAPTER);
-}
-
 static void esdhc_adapter_card_ident(void)
 {
 	u8 card_id, val;
diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig
index 87f3374..bd9153b 100644
--- a/board/freescale/mpc8548cds/Kconfig
+++ b/board/freescale/mpc8548cds/Kconfig
@@ -1,5 +1,8 @@
 if TARGET_MPC8548CDS
 
+config PCI1
+	def_bool y
+
 config SYS_BOARD
 	default "mpc8548cds"
 
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
index 3adac4a..159bcc4 100644
--- a/board/freescale/p1010rdb/Kconfig
+++ b/board/freescale/p1010rdb/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "P1010RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index db7b47a..cd36150 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -11,6 +11,4 @@
 config SYS_CONFIG_NAME
 	default "p1_p2_rdb_pc"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
index 7e187dd..78e1121 100644
--- a/board/freescale/p2041rdb/Kconfig
+++ b/board/freescale/p2041rdb/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "P2041RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
index 6deeb24..d538386 100644
--- a/board/freescale/t102xrdb/Kconfig
+++ b/board/freescale/t102xrdb/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "T102xRDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
index e6e46fa..e33d317 100644
--- a/board/freescale/t104xrdb/Kconfig
+++ b/board/freescale/t104xrdb/Kconfig
@@ -11,6 +11,4 @@
 config SYS_CONFIG_NAME
 	default "T104xRDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
index 58a31b6..c419a59 100644
--- a/board/freescale/t208xqds/Kconfig
+++ b/board/freescale/t208xqds/Kconfig
@@ -12,6 +12,4 @@
 config SRIO_PCIE_BOOT_SLAVE
 	bool "Boot as a SRIO PCIe slave device"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
index d4c061a..35d884e 100644
--- a/board/freescale/t208xrdb/Kconfig
+++ b/board/freescale/t208xrdb/Kconfig
@@ -12,6 +12,4 @@
 config T2080RDB_REV_D
 	bool "Support for T2080RDB revisions D and up"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index 542e574..d93e453 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -9,6 +9,4 @@
 config SYS_CONFIG_NAME
 	default "T4240RDB"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/board/friendlyarm/Kconfig b/board/friendlyarm/Kconfig
index f8f9cfd..fa04727 100644
--- a/board/friendlyarm/Kconfig
+++ b/board/friendlyarm/Kconfig
@@ -11,6 +11,7 @@
 
 config PWM_NX
 	bool "PWM"
+	select PWM_S5P
 	help
 	  This enables LCD-Backlight control via PWM.
 endchoice
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 3430a1e..27aad4e 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -59,7 +59,8 @@
 		f = get_board_sys_clk();
 	} else {
 		src = "PCI_CLK";
-		f = CONFIG_PCI_CLK_FREQ;
+		/* PCI is clocked by the external source at 33 MHz */
+		f = 33000000;
 	}
 	printf ("PCI1:  32 bit, %d MHz (%s)\n",	f/1000000, src);
 #else
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
index 4abcdb3..49d0274 100644
--- a/board/sysam/stmark2/Kconfig
+++ b/board/sysam/stmark2/Kconfig
@@ -3,6 +3,9 @@
 config CF_SBF
 	def_bool y
 
+config EXTRA_CLOCK
+	def_bool y
+
 config SYS_INPUT_CLKSRC
 	hex
 	default 30000000
diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig
index cfe6fc8..9a4003a 100644
--- a/board/variscite/imx8mn_var_som/Kconfig
+++ b/board/variscite/imx8mn_var_som/Kconfig
@@ -12,6 +12,4 @@
 config IMX_CONFIG
 	default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg"
 
-source "board/freescale/common/Kconfig"
-
 endif
diff --git a/boot/Kconfig b/boot/Kconfig
index 38fc71c..945ef1c 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -575,6 +575,19 @@
 
 endchoice
 
+config FSL_FIXED_MMC_LOCATION
+	bool "PBL MMC is at a fixed location"
+	depends on SDCARD && !RAMBOOT_PBL
+
+config ESDHC_HC_BLK_ADDR
+	def_bool y
+	depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_BSC9132 || ARCH_P1010)
+	help
+	  In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+	  code length of these soc specify the memory address in block address
+	  format. Block length is fixed to 512 bytes as per the SD High
+	  Capacity specification.
+
 config SYS_FSL_PBL_PBI
 	string "PBI(pre-boot instructions) commands for the PBL image"
 	depends on RAMBOOT_PBL
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ad36ae6..bb956e3 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1298,6 +1298,10 @@
 	  and erasing blocks. It allso provides a way to show and change
 	  bad blocks, and test the device.
 
+config USE_ONENAND_BOARD_INIT
+	bool "Call onenand_board_init() in the onenand command"
+	depends on CMD_ONENAND
+
 config CMD_OSD
 	bool "osd"
 	help
diff --git a/common/board_f.c b/common/board_f.c
index a5666ca..5c86fae 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -400,13 +400,9 @@
 	      ((unsigned long)gd->relocaddr - addr) >> 10, addr);
 	gd->relocaddr = addr;
 #elif defined(CONFIG_LCD)
-#  ifdef CONFIG_FB_ADDR
-	gd->fb_base = CONFIG_FB_ADDR;
-#  else
 	/* reserve memory for LCD display (always full pages) */
 	gd->relocaddr = lcd_setmem(gd->relocaddr);
 	gd->fb_base = gd->relocaddr;
-#  endif /* CONFIG_FB_ADDR */
 #endif
 
 	return 0;
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index f2dd5d3..6fa89aa 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -10,6 +10,8 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
 CONFIG_PHYS_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 55acf63..8277649 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -10,6 +10,8 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 4bd0b1a..c21ed57 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -10,7 +10,9 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_TARGET_MPC8548CDS_LEGACY=y
+CONFIG_PCIE1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index d1de705..7a50cd7 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -79,7 +82,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 570ba4b..5030afd 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -8,12 +8,16 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -46,7 +50,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index c407c27..dd04cff 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -13,13 +13,17 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -68,7 +72,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index fd2156a..46613cc 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -71,7 +74,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index eaa9efc..49acfd2 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -78,7 +81,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 681af51..89fccd6 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -8,11 +8,15 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -45,7 +49,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e18919e..a278661 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -13,12 +13,16 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -67,7 +71,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 9f3c337..17daecd 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -70,7 +73,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 7a55298..6b73bf4 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -80,7 +83,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7f749ed..7a5e057 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -8,12 +8,16 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -47,7 +51,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 3e7db0a..ef85d48 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -13,13 +13,17 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -69,7 +73,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index c93e4d4..bda32cc 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -72,7 +75,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index b85d14a..50667e5 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -79,7 +82,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 5861409..c13369e 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -8,11 +8,15 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -46,7 +50,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index f9a0664..691d6e3 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -13,12 +13,16 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
@@ -68,7 +72,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 45945ca..a630e96 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -71,7 +74,9 @@
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 3b320bc..8288e85 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -77,7 +80,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index c4d5fe8..b581cb1 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -13,8 +13,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -22,6 +25,7 @@
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -67,7 +71,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index cc9b113..e8543c6 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -70,7 +73,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 6d98c2e..2b9fcb0 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -9,13 +9,17 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -46,7 +50,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index d77c3ed..fdb163f 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -76,7 +79,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 75a967b..7489ad3 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -13,14 +13,18 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -66,7 +70,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f0d9d29..728592f 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -69,7 +72,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 2631bb3..ada7e2d 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -9,12 +9,16 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -45,7 +49,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index f92e3f0..0839286 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -79,7 +82,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8796
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index bb60f1f..ddd9e33 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -13,14 +13,18 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -69,7 +73,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index c03914e..88365bf 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -72,7 +75,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 2e81747..ef31e09 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -9,12 +9,16 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -48,7 +52,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 91ebd89..99f1d26 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -81,7 +84,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index fddd5da..856a78f 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -13,8 +13,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -22,6 +25,7 @@
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -71,7 +75,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 69ccb8d..b03c17c 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
@@ -74,7 +77,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index d9bf4dc..c1a5ef9 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -9,13 +9,17 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_PHYS_64BIT=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -50,7 +54,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 5a62055..2558596 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -14,8 +14,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -80,7 +83,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 3e152f8..29cc147 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -13,14 +13,18 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -70,7 +74,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 1b6ed86..3ee43f8 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -15,8 +15,11 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -73,7 +76,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index d69e948..7af0244 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -9,12 +9,16 @@
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_FSL_FIXED_MMC_LOCATION=y
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
@@ -49,7 +53,9 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 193e471..5063470 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -7,6 +7,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 4a97e85..a64f892 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -7,6 +7,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 3a19e4d..f295174 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 5dddbda..e3dd1e9 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index d9bc803..3e4cb51 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -7,6 +7,11 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -47,6 +52,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index e0e65ee..66eb6c3 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -7,6 +7,11 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -47,6 +52,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 761a902..87c62be 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -8,6 +8,11 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -49,6 +54,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 6798c1d..d083c25 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -8,6 +8,11 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -44,6 +49,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index dde3351..ed6f3de 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -7,6 +7,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -46,6 +50,7 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 1db4471..e77085a 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -48,6 +52,7 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 9eb49bf..91aa75d 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -43,6 +47,7 @@
 CONFIG_DM=y
 CONFIG_LBA48=y
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 75b9c96..3a48362 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -7,6 +7,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -48,6 +52,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 015feac..9aa293d 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -7,6 +7,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -47,6 +51,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 7aa0769..6f0d51a 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -49,6 +53,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 8d5f107..ae5f7b7 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -44,6 +48,7 @@
 CONFIG_FSL_SATA_V2=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 940538b..ad33aa8 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -12,8 +12,12 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index ac31a55..06bb7b7 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -13,7 +13,11 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 7688304..f88fb38 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -15,7 +15,11 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index a88b6a3..a0908ac 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -8,6 +8,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index f8772cc..bb32ddf 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -11,8 +11,13 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 99280a0..932a4e1 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -12,7 +12,12 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 0f624f7..0c4e339 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -14,7 +14,12 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index ae2f005..4445801 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -7,6 +7,11 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 3299fcd..05e46e6 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -18,8 +18,23 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index b35c964..1818762 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -19,7 +19,22 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 6959754..30d1b85 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -1,8 +1,17 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_NXP_ESBC=y
+CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
@@ -10,9 +19,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_MP=y
 CONFIG_FIT=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index ce0b15c..73c50b9 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -21,7 +21,22 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 362d9fd..48ef69c 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -2,6 +2,19 @@
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
+<<<<<<< HEAD
+=======
+CONFIG_ENV_ADDR=0xFFE20000
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SRIO_PCIE_BOOT_SLAVE=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
@@ -13,6 +26,7 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SRIO_PCIE_BOOT_SLAVE=y
 CONFIG_MP=y
 CONFIG_FIT=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index e2b3ee1..a94fd3f 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -3,6 +3,18 @@
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
+<<<<<<< HEAD
+=======
+CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
@@ -14,6 +26,7 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index c33ff6f..6566226 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -15,8 +15,20 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 4d4c37b..3333ac1 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -16,7 +16,19 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 040e5bc..5812daa 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -18,7 +18,19 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 0e001e2..563d0b5 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -11,6 +11,18 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 26ee297..9844343 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -15,9 +15,21 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index c3c399c..004f677 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -16,8 +16,20 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index fbae2c4..610f3f8 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -18,8 +18,20 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index ef87c2e..ca6a741 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -11,7 +11,19 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index dd5861e..3e43f9b 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -16,7 +16,19 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 01236ed..9f6457f 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -11,6 +11,18 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 104532b..5ae13d5 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -49,6 +49,7 @@
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index c9e4ee8..c332878 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -74,6 +74,8 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 0044d89..ea9e7e2 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -114,6 +114,7 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 0858025..c0c7c0d 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -118,6 +118,7 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index e2eab2b..7ce02fe 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -124,6 +124,7 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 00f0a67..17c97ac 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -52,6 +52,7 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_ONENAND=y
+CONFIG_USE_ONENAND_BOARD_INIT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_MTDPARTS=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 1d8ae58..655759b 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_TEXT_BASE=0x07d00000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_TARGET_KM_KIRKWOOD=y
+# CONFIG_KIRKWOOD_PCIE_INIT is not set
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index d2f2ff4..65378d3 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_TEXT_BASE=0x07d00000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_TARGET_KM_KIRKWOOD=y
+# CONFIG_KIRKWOOD_PCIE_INIT is not set
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 17e899a..cd6fb96 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -10,6 +10,9 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_PCIE1=y
 CONFIG_KM_DEF_NETDEV="eth2"
 CONFIG_KM_IVM_BUS=2
 CONFIG_MP=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 9654b8d..8b54f9c 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SYS_TEXT_BASE=0x07d00000
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_TARGET_KM_KIRKWOOD=y
+# CONFIG_KIRKWOOD_PCIE_INIT is not set
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_ENV_SECT_SIZE=0x10000
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 0ab5c86..da72b39 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -12,6 +12,7 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index 4a65705..8219d70 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -14,6 +14,7 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 8c70bf0..c679b2b 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index c425a7a..b580a59 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -13,6 +13,7 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index 7c69d56..1f12a3b 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -5,11 +5,13 @@
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_FSL_LS_PPA=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -47,6 +49,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index bb30e27..dfa525f 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -12,6 +12,8 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x401D0000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 21c989c..50855d5 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -6,12 +6,14 @@
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -45,6 +47,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 129855f..2bdebe2 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -13,6 +13,8 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 1adf0fe..0f6c2ac 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -9,10 +9,12 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_FSL_QIXIS=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index a77e124..fcc7914 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -6,13 +6,15 @@
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_FSL_QIXIS=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -52,6 +54,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 5f361b6..98e48f2 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -10,11 +10,13 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_FSL_QIXIS=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 02d6e0f..6147d4b 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -5,12 +5,14 @@
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -50,6 +52,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 0a6c43f..f9b0e6e 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -13,6 +13,8 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x40300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 6dc5674..a603bd9 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -6,13 +6,15 @@
 CONFIG_SYS_MALLOC_LEN=0x500000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -48,6 +50,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index 4224b48..5a86992 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -14,6 +14,8 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 8b588f7..d731936 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -12,9 +12,12 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
-# CONFIG_DEEP_SLEEP is not set
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_QSPI_BOOT=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index d34897a..c71ab78 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -14,12 +14,15 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-# CONFIG_DEEP_SLEEP is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_RAMBOOT_PBL=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 9158713..165e1a7 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -12,12 +12,15 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 00d9d3e..13ded15 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -12,12 +12,15 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index cfa81ba..1423d73 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -16,14 +16,17 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -95,6 +98,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index ad7e390..d4b9cd2 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -6,17 +6,20 @@
 CONFIG_SYS_MALLOC_LEN=0x1002000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 # CONFIG_SYS_MALLOC_F is not set
@@ -62,6 +65,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 1434817..7cc6121 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -12,12 +12,15 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -65,6 +68,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 9bfbe2e..04cb087 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -12,12 +12,15 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -65,6 +68,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 02d056f..2d560b2 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -13,10 +13,13 @@
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -62,6 +65,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 164e8b0..8e23ccc 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -16,15 +16,18 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
-# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -93,6 +96,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 8a6357b..ff8fbeb 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -16,14 +16,17 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_FSL_QIXIS=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_FIT=y
@@ -89,6 +92,7 @@
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index cfa83b8..b368791 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -14,6 +14,9 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 5e93f73..64266af 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -19,6 +19,9 @@
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 175f10f..41887e0 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -6,7 +6,6 @@
 CONFIG_SYS_MALLOC_LEN=0x1020000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -14,6 +13,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index e80b793..c806309 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -15,6 +15,9 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index a22d2a5..de02593 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -15,6 +15,9 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index aadc61b..b5b2cf1 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -15,6 +15,9 @@
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index f16c156..2b76f0a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -9,7 +9,6 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -21,6 +20,10 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index c9a265d..161fa1e 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -21,6 +21,9 @@
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index e4f2b85..2dc01e1 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -21,6 +21,9 @@
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 5a40f00..364a347 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -12,6 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
@@ -19,9 +26,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 0acb881..7b083b3 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -12,6 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
@@ -19,9 +26,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 1fe04fe..7446f01 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -15,6 +15,15 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
@@ -22,11 +31,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index af362b1..6dd797c 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -12,6 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
@@ -19,9 +26,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 6ba6b42..30cc15a 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -13,15 +13,19 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x40300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 21231cb..53f19a3 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -15,6 +15,16 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
@@ -22,12 +32,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 7991458..447a515 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -15,18 +15,22 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 9035594..4c8a615 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -6,22 +6,26 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -64,6 +68,7 @@
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 6bf7500..d04d1d9 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -14,16 +14,20 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x60500000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_ENV_ADDR=0x60500000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 7f4729f..8b2f094 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -5,7 +5,6 @@
 CONFIG_SYS_MALLOC_LEN=0x120000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -13,6 +12,11 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -45,10 +49,12 @@
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 454f3dc..341fb0f 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -14,6 +14,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FSL_LS_PPA=y
 CONFIG_ENV_ADDR=0x60300000
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -49,6 +53,7 @@
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 401bc39..305734d 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -7,7 +7,6 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_SPL_TEXT_BASE=0x10000000
@@ -15,6 +14,11 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -73,6 +77,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 3c5e5ce..56cdef8 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -19,6 +19,10 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 9d29c36..bf2805d 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -7,7 +7,6 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_SPL_TEXT_BASE=0x10000000
@@ -16,6 +15,11 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -73,6 +77,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 # CONFIG_SPL_DM_MMC is not set
 CONFIG_FSL_ESDHC=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 0c34861..f1370b5 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -20,6 +20,10 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 34f6952..4ebc636 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -6,7 +6,6 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -15,6 +14,11 @@
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
@@ -44,10 +48,12 @@
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 5d36183..db52294 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -17,6 +17,10 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x60500000
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
@@ -51,6 +55,7 @@
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index 0044442..1be7002 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -6,14 +6,18 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
-CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
@@ -45,6 +49,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x52
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 95ecf2a..f41434c 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -10,12 +10,16 @@
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
-CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x40500000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index 8b17130..fdeedca 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -5,13 +5,19 @@
 CONFIG_SYS_MALLOC_LEN=0x120000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x20000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
@@ -19,8 +25,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -64,6 +68,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index bf9f480..a66099c 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -12,6 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
@@ -19,9 +26,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index c4672d0..835159d 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -12,6 +12,13 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x60300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
@@ -19,9 +26,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x60300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index d63e5a5..2a70d66 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -15,6 +15,15 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
@@ -22,11 +31,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index d62e5b6..049cf1e 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -13,15 +13,19 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FSL_LS_PPA=y
+CONFIG_ENV_ADDR=0x40300000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_ENV_ADDR=0x40300000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 0fa3ea1..11554a8 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -15,6 +15,16 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
@@ -22,12 +32,6 @@
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
 # CONFIG_QIXIS_I2C_ACCESS is not set
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index e55712f..68aae88 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -15,18 +15,22 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
 CONFIG_SPL_TEXT_BASE=0x10000000
-CONFIG_FSL_USE_PCA9547_MUX=y
-CONFIG_VID=y
-CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
-CONFIG_VOL_MONITOR_INA220=y
-CONFIG_VOL_MONITOR_IR36021_SET=y
-CONFIG_FSL_QIXIS=y
 CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 58bc95d..7fd2412 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -6,22 +6,26 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
@@ -64,6 +68,7 @@
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 881f1f1..52d3d302 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -14,16 +14,20 @@
 CONFIG_SYS_I2C_MXC_I2C4=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x60500000
+CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_FSL_USE_PCA9547_MUX=y
 CONFIG_VID=y
 CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
 CONFIG_VOL_MONITOR_INA220=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
 CONFIG_FSL_QIXIS=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_ENV_ADDR=0x60500000
-CONFIG_AHCI=y
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x9fffffff
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 9cba997..3314198 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -21,6 +21,10 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 2a7c730..2ea72cc 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -5,7 +5,6 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -15,6 +14,11 @@
 CONFIG_FSL_LS_PPA=y
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -57,6 +61,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 6f9a2e8..c6b537f 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -17,6 +17,10 @@
 CONFIG_QSPI_AHB_INIT=y
 CONFIG_ENV_ADDR=0x40300000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 799d460..57cebf5 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -23,6 +23,10 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 4301d38..6960aa9 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -7,7 +7,6 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -20,6 +19,11 @@
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
@@ -80,6 +84,7 @@
 CONFIG_DM_I2C=y
 # CONFIG_SPL_DM_I2C is not set
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 # CONFIG_SPL_DM_MMC is not set
 CONFIG_FSL_ESDHC=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 50efffa..9ca4315 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -21,6 +21,10 @@
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 62020ee..e192ef4 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -6,7 +6,6 @@
 CONFIG_SYS_MALLOC_LEN=0x102000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
@@ -17,6 +16,11 @@
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_AHCI=y
+CONFIG_NXP_ESBC=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
@@ -51,6 +55,7 @@
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_FSL_SEC_MON_BE=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index c068577..6e5f29a 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -19,6 +19,10 @@
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x40500000
 CONFIG_AHCI=y
+CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 1580ceb..be351a3 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -71,6 +71,7 @@
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index b20a5d2..7c2134a 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -65,6 +65,7 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index caf5d77..0aed102 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -68,6 +68,7 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 663aacf..6ec9f2b 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -90,6 +90,7 @@
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index f3e2048..0ca54c8 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -86,6 +86,7 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index a135de3..e5063be 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -79,6 +79,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index abc958f..383e892 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -59,6 +59,7 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 9278a6e..92f1295 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -62,6 +62,7 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index dab9a7f..855d117 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -83,6 +83,7 @@
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index afa2469..8ca856c 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -64,6 +64,7 @@
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 3d6aa69..bc9febc 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -78,6 +78,7 @@
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index c46e506..60e489f 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -73,6 +73,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 317347b..d65d611 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -69,6 +69,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index b6441a3..97cfb66 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -76,6 +76,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_ESDHC_DETECT_QUIRK=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index cbea4fa..be86890 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -38,5 +38,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCNET=y
+CONFIG_PCI_GT64120=y
+CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 206d5bb..6eef89d 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -40,5 +40,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCNET=y
+CONFIG_PCI_GT64120=y
+CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 7b1b505..88c0d56 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -37,5 +37,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCNET=y
+CONFIG_PCI_GT64120=y
+CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 540864b..58d31d6 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -39,5 +39,7 @@
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCNET=y
+CONFIG_PCI_GT64120=y
+CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 15dbaf8..ea0c764 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -97,6 +97,8 @@
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index c41b2d9..1985ff9 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -60,6 +60,8 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 6b0f176..d4ab938 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -75,6 +75,8 @@
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 8beb6a0..9f4543c 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -72,6 +72,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
 CONFIG_LIB_HW_RAND=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 0a36472..9a429a8 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -54,5 +54,6 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index c5d6574..4b205e1 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -18,6 +18,8 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60060000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_DEF_NETDEV="eth2"
 CONFIG_KM_COMMON_ETH_INIT=y
 CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index c2b079d..98f3dcc 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -17,6 +17,8 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60220000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_DEF_NETDEV="eth2"
 CONFIG_KM_COMMON_ETH_INIT=y
 CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 56e922a..ce3e7eb 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -18,6 +18,8 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60060000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_DEF_NETDEV="eth2"
 CONFIG_KM_COMMON_ETH_INIT=y
 CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index 9d25094..623afa3 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -17,6 +17,8 @@
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_ENV_ADDR=0x60220000
 CONFIG_AHCI=y
+# CONFIG_DEEP_SLEEP is not set
+CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_KM_DEF_NETDEV="eth2"
 CONFIG_KM_COMMON_ETH_INIT=y
 CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 8c7b8b4..034f7e6 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -6,6 +6,7 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_QEMU_PPCE500=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index 5a38b07..2beda3a 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -52,6 +52,7 @@
 CONFIG_RTL8139=y
 CONFIG_TULIP=y
 CONFIG_PCI=y
+CONFIG_SH7751_PCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SERIAL_RX_BUFFER=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index a010404..c13602d 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -32,6 +32,7 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_ONENAND=y
+CONFIG_USE_ONENAND_BOARD_INIT=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
@@ -50,13 +51,16 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
+CONFIG_SAMSUNG_ONENAND=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_MAX8998=y
+CONFIG_PWM_S5P=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Samsung"
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index af7fef5..cab0ac8 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -49,6 +49,7 @@
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_S5P=y
 CONFIG_MTD=y
+CONFIG_SAMSUNG_ONENAND=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_MAX8998=y
 CONFIG_SOFT_SPI=y
@@ -58,5 +59,6 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 2c8bd1c..1ed3a8c 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -26,6 +26,7 @@
 CONFIG_SYS_PBSIZE=384
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_ONENAND=y
+CONFIG_USE_ONENAND_BOARD_INIT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
@@ -36,5 +37,7 @@
 CONFIG_ENV_IS_IN_ONENAND=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_SAMSUNG_ONENAND=y
 CONFIG_SMC911X=y
 CONFIG_SMC911X_BASE=0x98800300
+CONFIG_PWM_S5P=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index d902019..28ea447 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -9,6 +9,7 @@
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_SOCRATES=y
+CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index 8ca8929..6461065 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -48,6 +48,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPI=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 55e44f8..753a4b8 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -69,6 +69,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 22274f9..e3f80ab 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -48,6 +48,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPI=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index c174984..927d28d 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -69,6 +69,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 9845eb0..b7e9ee9 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -47,6 +47,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPI=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index a5dc89c..bae28b4 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -68,6 +68,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index d03d984..2c14306 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -37,6 +37,7 @@
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_PHY_RESET_DELAY=10000
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 CONFIG_MII=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_HAS_CQSPI_REF_CLK=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 4b304f8..892d7c6 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -83,6 +83,8 @@
 CONFIG_MII=y
 CONFIG_PCI=y
 # CONFIG_PCI_PNP is not set
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_RTC=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 5c47a22..b48ed9c 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -62,6 +62,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
 CONFIG_LIB_HW_RAND=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 008a8ff..3e0fdfe 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -59,6 +59,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
 CONFIG_LIB_HW_RAND=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index da78288..8d87857 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -84,6 +84,8 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_PCIE_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index eec9d48..738b788 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -30,5 +30,10 @@
 	  For memory controllers that can utilize it, add enable support for
 	  using the JEDEC SDP standard.
 
+config SYS_SPD_BUS_NUM
+	int "I2C bus number for DDR SPD"
+	depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY
+	default 0
+
 source "drivers/ddr/altera/Kconfig"
 source "drivers/ddr/imx/Kconfig"
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index fe69bef..d93ed8d 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -10,6 +10,12 @@
 	help
 	  Select Freescale Multi Mode DDR controller (MMDC).
 
+config SYS_FSL_DDR_EMU
+	bool
+	help
+	  Specify emulator support for DDR. Some DDR features such as deskew
+	  training are not available.
+
 if SYS_FSL_DDR || SYS_FSL_MMDC
 
 config SYS_FSL_DDR_BE
@@ -169,6 +175,13 @@
 	  Use the DDR controller to auto initialize memory.  If not enabled,
 	  the DMA controller is responsible for doing this.
 
+config SYS_DDR_RAW_TIMING
+	bool "Get DDR timing information from something other than SPD"
+	help
+	  This is common with soldered DDR chips onboard without SPD. DDR raw
+	  timing parameters are extracted from datasheet and hard-coded into
+	  header files or board specific files.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 28d5da4..92264e5 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -275,6 +275,20 @@
 	  Security Monitor can be transitioned on any security failures,
 	  like software violations or hardware security violations.
 
+choice
+	prompt "Security monitor interaction endianess"
+	depends on FSL_SEC_MON
+	default SYS_FSL_SEC_MON_BE if PPC
+	default SYS_FSL_SEC_MON_LE
+
+config SYS_FSL_SEC_MON_LE
+	bool "Security monitor interactions are little endian"
+
+config SYS_FSL_SEC_MON_BE
+	bool "Security monitor interactions are big endian"
+
+endchoice
+
 config IRQ
 	bool "Interrupt controller"
 	help
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5a87db6..53a6b00 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -844,6 +844,10 @@
 	depends on FSL_ESDHC
 	default 1
 
+config ESDHC_DETECT_QUIRK
+	bool "QIXIS-based eSDHC quirk detection"
+	depends on FSL_ESDHC && FSL_QIXIS
+
 config FSL_ESDHC_IMX
 	bool "Freescale/NXP i.MX eSDHC controller support"
 	help
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4e7bfdf..b49a7b4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -30,6 +30,7 @@
 #include <linux/iopoll.h>
 #include <linux/dma-mapping.h>
 #include <sdhci.h>
+#include "../../board/freescale/common/qixis.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -773,7 +774,7 @@
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 
 #ifdef CONFIG_ESDHC_DETECT_QUIRK
-	if (CONFIG_ESDHC_DETECT_QUIRK)
+	if (qixis_esdhc_detect_quirk())
 		return 1;
 #endif
 	if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index d0ab7c1..3d1f6e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -168,6 +168,9 @@
 	 This is the driver of embedded flash for some STMicroelectronics
 	 STM32 MCU.
 
+config SAMSUNG_ONENAND
+	bool "Samsung OneNAND driver support"
+
 config USE_SYS_MAX_FLASH_BANKS
 	bool "Enable Max number of Flash memory banks"
 	help
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 56f9416..40b5c82 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -312,6 +312,7 @@
 config ETH_DESIGNWARE_SOCFPGA
 	select REGMAP
 	select SYSCON
+	select DW_ALTDESCRIPTOR
 	bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
 	depends on DM_ETH && ETH_DESIGNWARE
 	help
@@ -326,6 +327,10 @@
 	  This provides glue layer to use Synopsys Designware Ethernet MAC
 	  present on Actions S700 SoC.
 
+config DW_ALTDESCRIPTOR
+	bool "Designware Ethernet MAC uses alternate (enhanced) descriptors"
+	depends on ETH_DESIGNWARE
+
 config ETHOC
 	bool "OpenCores 10/100 Mbps Ethernet MAC"
 	help
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ddc3d4f..3793d55 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -85,10 +85,8 @@
 
 #define DW_DMA_BASE_OFFSET	(0x1000)
 
-/* Default DMA Burst length */
-#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
-#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
-#endif
+/* DMA Burst length */
+#define GMAC_DEFAULT_DMA_PBL	8
 
 /* Bus mode register definitions */
 #define FIXEDBURST		(1 << 16)
@@ -96,7 +94,7 @@
 #define PRIORXTX_31		(2 << 14)
 #define PRIORXTX_21		(1 << 14)
 #define PRIORXTX_11		(0 << 14)
-#define DMA_PBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
+#define DMA_PBL			(GMAC_DEFAULT_DMA_PBL << 8)
 #define RXHIGHPRIO		(1 << 1)
 #define DMAMAC_SRST		(1 << 0)
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index fd22034..436acca 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -48,6 +48,10 @@
 	  region type. This helps to add support for SoC's like OcteonTX/TX2
 	  where every peripheral is on the PCI bus.
 
+config PCI_CONFIG_HOST_BRIDGE
+	bool "Configure PCI host bridges"
+	default y if X86
+
 config PCI_MAP_SYSTEM_MEMORY
 	bool "Map local system memory from a virtual base address"
 	depends on MIPS
@@ -81,6 +85,10 @@
           support on PCI devices. This helps to skip some devices in BDF
           scan that are not present.
 
+config PCI_SCAN_SHOW
+	bool "Show PCI devices during startup"
+	depends on PCIE_IMX
+
 config PCIE_ECAM_GENERIC
 	bool "Generic ECAM-based PCI host controller support"
 	help
@@ -97,6 +105,10 @@
 	  Note that this must be configured when boot because Linux driver
 	  expects the PCIe RC has been configured in the bootloader.
 
+config PCI_GT64120
+	bool "GT64120 PCI support"
+	depends on MIPS
+
 config PCI_PHYTIUM
 	bool "Phytium PCIe support"
 	help
@@ -121,8 +133,12 @@
 	  Say Y here if you want to enable PCIe controller support on
 	  FU740.
 
+config SYS_FSL_PCI_VER_3_X
+	bool
+
 config PCIE_FSL
 	bool "FSL PowerPC PCIe support"
+	select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240
 	help
 	  Say Y here if you want to enable PCIe controller support on FSL
 	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
@@ -134,6 +150,10 @@
 	  Say Y here if you want to enable PCI controller support on FSL
 	  PowerPC MPC85xx SoC.
 
+config PCI_MSC01
+	bool "MSC01 PCI support"
+	depends on TARGET_MALTA
+
 config PCI_RCAR_GEN2
 	bool "Renesas RCar Gen2 PCIe driver"
 	depends on RCAR_32
@@ -159,6 +179,12 @@
 	  the device tree but the normal PCI scan technique is used to find
 	  then.
 
+config SH7751_PCI
+	bool "SH7751 PCI controller support"
+	depends on SH
+	help
+	  SuperH PCI Bridge Configuration
+
 config PCI_TEGRA
 	bool "Tegra PCI support"
 	depends on ARCH_TEGRA
@@ -254,6 +280,10 @@
 	  This compatible is used to find pci controller ep node in Kernel DT
 	  to complete fixup.
 
+config PCIE_IMX
+	bool "i.MX PCIe support"
+	depends on ARCH_MX6
+
 config PCIE_INTEL_FPGA
 	bool "Intel FPGA PCIe support"
 	help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 04f6236..cfcd6fd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -20,7 +20,6 @@
 obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
-obj-$(CONFIG_SH4_PCI) += pci_sh4.o
 obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c
deleted file mode 100644
index aac9be0..0000000
--- a/drivers/pci/pci_sh4.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SH4 PCI Controller (PCIC) for U-Boot.
- * (C) Dustin McIntire (dustin@sensoria.com)
- * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- *
- * u-boot/arch/sh/cpu/sh4/pci-sh4.c
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <pci.h>
-
-int pci_sh4_init(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->region_count = 0;
-	hose->last_busno = 0xff;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		CONFIG_PCI_MEM_BUS,
-		CONFIG_PCI_MEM_PHYS,
-		CONFIG_PCI_MEM_SIZE,
-		PCI_REGION_MEM);
-	hose->region_count++;
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		CONFIG_PCI_IO_BUS,
-		CONFIG_PCI_IO_PHYS,
-		CONFIG_PCI_IO_SIZE,
-		PCI_REGION_IO);
-	hose->region_count++;
-
-#if defined(CONFIG_PCI_SYS_BUS)
-	/* PCI System Memory space */
-	pci_set_region(hose->regions + 2,
-		CONFIG_PCI_SYS_BUS,
-		CONFIG_PCI_SYS_PHYS,
-		CONFIG_PCI_SYS_SIZE,
-		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-	hose->region_count++;
-#endif
-
-	udelay(1000);
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    pci_sh4_read_config_dword,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    pci_sh4_write_config_dword);
-
-	pci_register_hose(hose);
-
-	udelay(1000);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	hose->last_busno = pci_hose_scan(hose);
-	return 0;
-}
-
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	return 0;
-}
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	return 1;
-}
-#endif /* CONFIG_PCI_SCAN_SHOW */
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb54e67..8fd5a2e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -84,6 +84,11 @@
 	  useful. The PWM can be enabled but is not connected to any outputs
 	  so this is not very useful.
 
+config PWM_S5P
+	bool "Enable non-DM support for S5P PWM"
+	depends on (S5P || ARCH_NEXELL)
+	default y
+
 config PWM_SIFIVE
 	bool "Enable support for SiFive PWM"
 	depends on DM_PWM
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index d81a9c5..350036f 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -92,6 +92,11 @@
 
 if USB_GADGET_DWC2_OTG
 
+config USB_GADGET_DWC2_OTG_PHY
+	bool "DesignWare USB2.0 HS OTG PHY"
+	help
+	  Enable the DesignWare USB2.0 HS OTG physical device interface.
+
 config USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
 	bool "DesignWare USB2.0 HS OTG controller 8-bit PHY bus width"
 	help
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8..532ada8 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -64,8 +64,8 @@
 
 config DESIGNWARE_WATCHDOG
 	bool "Designware watchdog timer support"
-	select HW_WATCHDOG if !WDT
-	default y if WDT && ROCKCHIP_RK3399
+	depends on WDT
+	default y if ROCKCHIP_RK3399
 	help
 	  Enable this to support Designware Watchdog Timer IP, present e.g.
 	  on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index cfec29b..cad756a 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -60,26 +60,6 @@
 		writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
 }
 
-#if !CONFIG_IS_ENABLED(WDT)
-void hw_watchdog_reset(void)
-{
-	designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
-}
-
-void hw_watchdog_init(void)
-{
-	/* reset to disable the watchdog */
-	hw_watchdog_reset();
-	/* set timer in miliseconds */
-	designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
-				  CONFIG_DW_WDT_CLOCK_KHZ,
-				  CONFIG_WATCHDOG_TIMEOUT_MSECS);
-	/* enable the watchdog */
-	designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
-	/* reset the watchdog */
-	hw_watchdog_reset();
-}
-#else
 static int designware_wdt_reset(struct udevice *dev)
 {
 	struct designware_wdt_priv *priv = dev_get_priv(dev);
@@ -195,4 +175,3 @@
 	.ops = &designware_wdt_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-#endif
diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h
index 3922241..380c906 100644
--- a/include/config_fsl_chain_trust.h
+++ b/include/config_fsl_chain_trust.h
@@ -10,10 +10,6 @@
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 
-#ifndef CONFIG_EXTRA_ENV
-#define CONFIG_EXTRA_ENV	""
-#endif
-
 /*
  * Control should not reach back to uboot after validation of images
  * for secure boot flow and therefore bootscript should have
@@ -21,43 +17,22 @@
  * after validating images, core should just spin.
  */
 
-/*
- * Define the key hash for boot script here if public/private key pair used to
- * sign bootscript are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_BOOTSCRIPT_KEY_HASH \
- *	 "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- */
-
 #ifdef CONFIG_USE_BOOTARGS
-#define CONFIG_SET_BOOTARGS	"setenv bootargs \'" CONFIG_BOOTARGS" \';"
+#define SET_BOOTARGS	"setenv bootargs \'" CONFIG_BOOTARGS" \';"
 #else
-#define CONFIG_SET_BOOTARGS	"setenv bootargs \'root=/dev/ram "	\
+#define SET_BOOTARGS	"setenv bootargs \'root=/dev/ram "	\
 				"rw console=ttyS0,115200 ramdisk_size=600000\';"
 #endif
 
-
-#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
-#define CONFIG_SECBOOT \
+#define SECBOOT \
 	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
-	CONFIG_SET_BOOTARGS	\
-	CONFIG_EXTRA_ENV	\
-	"esbc_validate $bs_hdraddr " \
-	  __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
-	"source $img_addr;"	\
-	"esbc_halt\0"
-#else
-#define CONFIG_SECBOOT \
-	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
-	CONFIG_SET_BOOTARGS	\
-	CONFIG_EXTRA_ENV	\
+	SET_BOOTARGS	\
 	"esbc_validate $bs_hdraddr;" \
 	"source $img_addr;"	\
 	"esbc_halt\0"
-#endif
 
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
-#define CONFIG_BS_COPY_ENV \
+#define BS_COPY_ENV \
 	"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
 	"setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \
 	"setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
@@ -68,33 +43,28 @@
 /* For secure boot flow, default environment used will be used */
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \
 	defined(CONFIG_SD_BOOT)
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT)
-#define CONFIG_BS_COPY_CMD \
+#if defined(CONFIG_NAND_BOOT)
+#define BS_COPY_CMD \
 	"nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
 	"nand read $bs_ram $bs_device $bs_size ;"
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BS_COPY_CMD \
+#define BS_COPY_CMD \
 	"mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
 	"mmc read $bs_ram $bs_device $bs_size ;"
 #endif
 #else
-#define CONFIG_BS_COPY_CMD \
+#define BS_COPY_CMD \
 	"cp.b $bs_hdr_device $bs_hdr_ram  $bs_hdr_size ;" \
 	"cp.b $bs_device $bs_ram  $bs_size ;"
 #endif
+#else /* !CONFIG_BOOTSCRIPT_COPY_RAM */
+#define BS_COPY_ENV
+#define BS_COPY_CMD
 #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
 
-#ifndef CONFIG_BS_COPY_ENV
-#define CONFIG_BS_COPY_ENV
-#endif
-
-#ifndef CONFIG_BS_COPY_CMD
-#define CONFIG_BS_COPY_CMD
-#endif
-
-#define CONFIG_CHAIN_BOOT_CMD	CONFIG_BS_COPY_ENV \
-				CONFIG_BS_COPY_CMD \
-				CONFIG_SECBOOT
+#define CHAIN_BOOT_CMD	BS_COPY_ENV \
+			BS_COPY_CMD \
+			SECBOOT
 
 #endif
 #endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 8e75d77..3e4d668 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -198,43 +198,15 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
 
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
-
-#ifdef CONFIG_PCI
-#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
 
 /*
  * TSEC
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index d8ffa2e..2eb3381 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -16,10 +16,6 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 
-#define CONFIG_PCI1		/* PCI controller 1 */
-#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
-#undef CONFIG_PCI2
-
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #ifndef __ASSEMBLY__
@@ -34,7 +30,6 @@
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
-#define CONFIG_ENABLE_36BIT_PHYS	1
 
 #define CONFIG_SYS_CCSRBAR		0xe0000000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
@@ -264,8 +259,6 @@
  */
 #if !CONFIG_IS_ENABLED(DM_I2C)
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-#else
-#define CONFIG_SYS_SPD_BUS_NUM 0
 #endif
 
 /* EEPROM */
@@ -319,10 +312,6 @@
 #endif
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_TSEC1	1
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index ad78dba..aea744c 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -53,7 +53,6 @@
 #endif
 
 #ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
@@ -64,9 +63,6 @@
 /* High Level Configuration Options */
 
 #if defined(CONFIG_PCI)
-#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
-
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
@@ -98,8 +94,6 @@
 #else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 
 #define CONFIG_HWCONFIG
@@ -108,12 +102,7 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x52
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
@@ -353,8 +342,7 @@
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
-	defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
@@ -472,9 +460,7 @@
 /*
  * Environment
  */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#elif defined(CONFIG_MTD_RAW_NAND)
+#if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define SPL_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index df16319..e019c16 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -33,9 +33,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
@@ -43,11 +40,6 @@
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-	#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
 #endif
@@ -58,8 +50,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 
 /*
@@ -91,7 +81,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x52
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
@@ -332,10 +321,6 @@
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index 6063113..bc8aa3c 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -9,8 +9,6 @@
  */
 #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
 
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
 #define CONFIG_SYS_DPAA_RMAN
 
 #define CONFIG_SYS_SRIO
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 6615dd0..6375c65 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -9,8 +9,6 @@
  */
 #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
 
-#define CONFIG_PCIE3
-
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index 6e6e5be..fb73f0b 100644
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -9,7 +9,6 @@
  */
 #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
 
-#define CONFIG_PCIE3
 #define CONFIG_SYS_FSL_RAID_ENGINE
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 8114373..e42e6d5 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -9,10 +9,6 @@
 /* additions for new ARM relocation support */
 #define CONFIG_SYS_SDRAM_BASE	0x00000000
 
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index b70829c..8926c26 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -9,10 +9,6 @@
 /* additions for new ARM relocation support */
 #define CONFIG_SYS_SDRAM_BASE	0x00000000
 
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index bd458ff..a519b5a 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -15,7 +15,6 @@
 
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
@@ -127,11 +126,9 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_SDRAM_SIZE   2048
 #endif
 
@@ -355,9 +352,6 @@
  * General PCIe
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
 
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -383,8 +377,6 @@
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
 /*
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 505bae9..3a7c643 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -61,18 +61,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_PCIE4			/* PCIE controller 4 */
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#endif
-#endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -83,8 +71,6 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /*
  *  Config the L3 Cache as L3 SRAM
  */
@@ -108,7 +94,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x51
 
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
@@ -377,8 +362,6 @@
 #define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
 /*
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2db2b07..eff22c1 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -22,7 +22,6 @@
 
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
 
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
@@ -96,7 +95,6 @@
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
@@ -370,10 +368,6 @@
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE4		/* PCIE controller 4 */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
@@ -397,10 +391,6 @@
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#endif
-
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 07e1108..ba9bfdd 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -17,7 +17,6 @@
 
 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
 
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
@@ -91,7 +90,6 @@
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
@@ -323,10 +321,6 @@
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE4		/* PCIE controller 4 */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
@@ -350,10 +344,6 @@
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#endif
-
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 526d40f..12b479f 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -12,8 +12,6 @@
 
 #include <linux/stringify.h>
 
-#define CONFIG_PCIE4
-
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #ifdef CONFIG_RAMBOOT_PBL
@@ -44,9 +42,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -56,8 +51,6 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /*
  *  Config the L3 Cache as L3 SRAM
  */
@@ -145,10 +138,6 @@
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
 /*
  * Environment
  */
@@ -180,7 +169,6 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x52
 #define SPD_EEPROM_ADDRESS2	0x54
 #define SPD_EEPROM_ADDRESS3	0x56
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index a362282..6a4092a 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -19,9 +19,6 @@
 #define FDT_MODULE			"apalis-v1.2"
 #define FDT_MODULE_V1_0			"apalis"
 
-/* PCI host support */
-#undef CONFIG_PCI_SCAN_SHOW
-
 /*
  * Custom Distro Boot configuration:
  * 1. 8bit SD port (MMC1)
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index e335028..e418edd 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -22,8 +22,6 @@
 
 /* LCD */
 #define LCD_BPP				LCD_COLOR8
-/* Let board_init_f handle the framebuffer allocation */
-#undef CONFIG_FB_ADDR
 
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 9969269..9c9e950 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -28,9 +28,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define RELOCATION_LIMITS_ENV_SETTINGS	\
 	"fdt_high=0x10000000\0"		\
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index bb1595f..5da2778 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -17,9 +17,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /*
  * Environment Configuration
  */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f563a5f..2252bf8 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -15,17 +15,8 @@
 #include "../board/freescale/common/ics307_clk.h"
 
 #ifdef CONFIG_RAMBOOT_PBL
-#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_RAMBOOT_NAND
-#endif
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#else
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#endif
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -45,13 +36,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -62,8 +46,6 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
 
 /*
@@ -94,7 +76,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM	1
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
@@ -333,10 +314,6 @@
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index 6912f39..b9d03d2 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -14,9 +14,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* NAND */
 
 /* Keep device tree and initrd in lower memory so the kernel can access them */
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 3b3a7ab..bba2b60 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -17,9 +17,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"fdt_high=0x10000000\0"		\
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 715a6d7..7b30595 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -21,9 +21,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* NAND */
 
 /*
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 7e3f657..f8273a9 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -19,9 +19,6 @@
 /* I2C */
 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
diff --git a/include/configs/durian.h b/include/configs/durian.h
index c224511..7971df8 100644
--- a/include/configs/durian.h
+++ b/include/configs/durian.h
@@ -13,9 +13,6 @@
 #define PHYS_SDRAM_1_SIZE		0x7B000000
 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
 
-/* PCI CONFIG */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* BOOT */
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 7986021..246aa9b 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -18,9 +18,6 @@
 
 /* select serial console configuration */
 
-/* PWM */
-#define CONFIG_PWM
-
 /* Miscellaneous configurable options */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 625a2d8..054cb53 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -23,8 +23,6 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
-#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-
 /* Common environment variables */
 #define ENV_ITB \
 	"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index c50ecf2..49f57dd 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -21,9 +21,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-/* 10/100M Ethernet support */
-#define CONFIG_DW_ALTDESCRIPTOR
-
 /* Environment configuration */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index d813c6c..ad00769 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -109,7 +109,4 @@
 
 #define CONFIG_IMX6_PWM_PER_CLK	66000000
 
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-
 #endif	/* __GE_BX50V3_CONFIG_H */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 47a72fc..4a0aaf4 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -31,9 +31,6 @@
 /*
  * PCI express
  */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCIE_IMX
-#endif
 
 /*
  * PMIC
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index ff2c506..fc32487 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -28,9 +28,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define RELOCATION_LIMITS_ENV_SETTINGS	\
 	"fdt_high=0x10000000\0"		\
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 7430185..a129233 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -22,7 +22,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM		0
 #define SPD_EEPROM_ADDRESS		0x54
 
 /* POST memory regions test */
@@ -174,7 +173,6 @@
 					{1, {I2C_NULL_HOP}                 }, \
 				}
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e58a695..01482d5 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -23,7 +23,6 @@
 /* KM_KIRKWOOD */
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_HOSTNAME			"km_kirkwood"
-#define CONFIG_KM_DISABLE_PCIE
 
 /* KM_KIRKWOOD_PCI */
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
@@ -34,7 +33,6 @@
 /* KM_KIRKWOOD_128M16 */
 #elif defined(CONFIG_KM_KIRKWOOD_128M16)
 #define CONFIG_HOSTNAME			"km_kirkwood_128m16"
-#define CONFIG_KM_DISABLE_PCIE
 
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
@@ -44,7 +42,6 @@
 /* KMCOGE5UN */
 #elif defined(CONFIG_KM_COGE5UN)
 #define CONFIG_HOSTNAME			"kmcoge5un"
-#define CONFIG_KM_DISABLE_PCIE
 
 /* KM_SUSE2 */
 #elif defined(CONFIG_KM_SUSE2)
@@ -118,8 +115,4 @@
 	MVGBE_SET_MII_SPEED_TO_100)
 #endif
 
-#ifdef CONFIG_KM_DISABLE_PCIE
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
-#endif
-
 #endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 4de5736..ed24733 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -140,7 +140,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
 
 /* Environment in parallel NOR-Flash */
 #define CONFIG_ENV_TOTAL_SIZE		0x040000
@@ -152,8 +151,6 @@
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /* POST memory regions test */
 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
 
@@ -173,7 +170,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x54
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 19201a7..0c194ee 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -15,9 +15,6 @@
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
 
-/* CSU */
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 /*SPI device */
 #define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
 
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 7f083c5..a0ff3b8 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -25,10 +25,6 @@
 	func(USB, usb, 0) \
 	func(DHCP, dhcp, na)
 
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-
-#define CONFIG_PCI_SCAN_SHOW
-
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"verify=no\0"				\
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index b599236..b124ce5 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -82,10 +82,6 @@
 				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 				DSPI_CTAR_DT(0))
 
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-
-#define CONFIG_PCI_SCAN_SHOW
-
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"verify=no\0"				\
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index c57b598..4f77acd 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -36,10 +36,6 @@
 #define __PHY_ETH2_MASK		0xFB
 #define __PHY_ETH1_MASK		0xFD
 
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-
-#define CONFIG_PCI_SCAN_SHOW
-
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"verify=no\0"				\
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 6a0ccbf..ec68874 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -97,18 +97,9 @@
 #define TSEC2_PHYIDX			0
 #endif
 
-/* PCIe */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-
 #define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index e17bdca..1a46f72 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -23,11 +23,6 @@
 #endif
 
 #define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
-
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_DDR_RAW_TIMING
-#endif
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
@@ -304,18 +299,9 @@
 #define CONFIG_SYS_TBIPA_VALUE		8
 #endif
 
-#endif
-
-/* PCIe */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
 #endif
 
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index b06394c..e5754c9 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -80,14 +80,7 @@
 #define FSL_QSPI_FLASH_NUM		2
 
 /* PCIe */
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
 #define FSL_PCIE_COMPAT			"fsl,ls1021a-pcie"
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index d85a776..09dce21 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -171,16 +171,7 @@
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM		1
 
-/* PCIe */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8363969..ed32e20 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -108,17 +108,6 @@
 
 /* I2C */
 
-/* PCIe */
-#ifndef SPL_NO_PCIE
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-#endif
-
 /*  DSPI  */
 
 /* FMan ucode */
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 75d655c..15c3ff5 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -8,12 +8,9 @@
 
 #include "ls1043a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 /* Physical Memory Map */
 
 #define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index edb4e64..6c33847 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -8,14 +8,9 @@
 
 #include "ls1043a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 /* Physical Memory Map */
 
-#define CONFIG_SYS_SPD_BUS_NUM		0
-
 #ifndef CONFIG_SPL
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e139aa9..94118c4 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -76,15 +76,6 @@
 
 /* I2C */
 
-/* PCIe */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 /* SATA */
 #ifndef SPL_NO_SATA
 #define CONFIG_SYS_SATA				AHCI_BASE_ADDR
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index e663fa0..43717cd 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -8,8 +8,6 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 #define CONFIG_SYS_UBOOT_BASE		0x40100000
 
 /*
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 6271135..36c64db 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -8,12 +8,9 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 /* Physical Memory Map */
 
 #define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 4ad62b4..382d5c7 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -9,12 +9,9 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
 /* Physical Memory Map */
 
 #define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index e532c34..debb60d 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -16,7 +16,6 @@
 
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 
 /*
@@ -306,10 +305,6 @@
 
 #define CONFIG_FSL_MEMAC
 
-/*  MMC  */
-#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
-	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
-
 #define COMMON_ENV \
 	"kernelheader_addr_r=0x80200000\0"	\
 	"fdtheader_addr_r=0x80100000\0"		\
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index c690030..c0567c3 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -15,13 +15,8 @@
 
 #define COUNTER_FREQUENCY_REAL		25000000	/* 25MHz */
 
-#ifdef CONFIG_EMU
-#define CONFIG_SYS_FSL_DDR_EMU
-#else
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
 #define SPD_EEPROM_ADDRESS	0x51
-#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
 
 
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index f9eb829..d297871 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -16,10 +16,6 @@
 
 /* Link Definitions */
 
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_DDR_RAW_TIMING
-#endif
-
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
 #define CONFIG_VERY_BIG_RAM
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 21ca4af..9ba7258 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -24,10 +24,6 @@
 #define SPD_EEPROM_ADDRESS5	0x55
 #define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
-#endif
 
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
@@ -243,14 +239,6 @@
 #define FSL_QIXIS_BRDCFG9_QSPI		0x1
 
 /*
- * MMC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
-	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
-#endif
-
-/*
  * RTC configuration
  */
 #define RTC
@@ -263,10 +251,6 @@
 
 #define CONFIG_FSL_MEMAC
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #ifdef CONFIG_NXP_ESBC
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 43bcc5a..a504a0e 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -29,10 +29,6 @@
 #define SPD_EEPROM_ADDRESS5	0x55
 #define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
-#endif
 
 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
 
@@ -242,10 +238,6 @@
 
 #define CONFIG_FSL_MEMAC
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 #define BOOT_TARGET_DEVICES(func) \
 	func(USB, usb, 0) \
 	func(MMC, mmc, 0) \
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 1669ecd..77e2582 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -31,7 +31,6 @@
 #define SPD_EEPROM_ADDRESS5		0x55
 #define SPD_EEPROM_ADDRESS6		0x56
 #define SPD_EEPROM_ADDRESS		SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD on I2C bus 0 */
 #define CONFIG_SYS_MONITOR_LEN		(936 * 1024)
 
 /* Miscellaneous configurable options */
@@ -90,11 +89,6 @@
 /* Qixis */
 #define CONFIG_SYS_I2C_FPGA_ADDR		0x66
 
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 /* USB */
 
 #define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index e7aec6b..585aab2 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -11,16 +11,6 @@
 /* RTC */
 #define CONFIG_SYS_RTC_BUS_NUM		0
 
-/*
- * MMC
- */
-#ifdef CONFIG_MMC
-#ifndef __ASSEMBLY__
-u8 qixis_esdhc_detect_quirk(void);
-#endif
-#define CONFIG_ESDHC_DETECT_QUIRK  qixis_esdhc_detect_quirk()
-#endif
-
 /* MAC/PHY configuration */
 
 /* EEPROM */
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index 729c270..d1ae403 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h
@@ -13,16 +13,6 @@
 /* RTC */
 #define CONFIG_SYS_RTC_BUS_NUM		0
 
-/*
- * MMC
- */
-#ifdef CONFIG_MMC
-#ifndef __ASSEMBLY__
-u8 qixis_esdhc_detect_quirk(void);
-#endif
-#define CONFIG_ESDHC_DETECT_QUIRK  qixis_esdhc_detect_quirk()
-#endif
-
 /* EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM		0
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 225ed7c..affee00 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -13,9 +13,6 @@
 
 #define CONFIG_MEMSIZE_IN_BYTES
 
-#define CONFIG_PCI_GT64120
-#define CONFIG_PCI_MSC01
-
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
 
 /*
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index ef255aa..16f8858 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -24,8 +24,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
 #define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
 #endif
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 7bbc500..58d550f 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -129,8 +129,6 @@
 #endif
 
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 0)
 #define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 1)
 #endif
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 72a9f4e..2007b48 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -97,12 +97,4 @@
 
 /* Environment organization */
 
-/*
- * PCI express
- */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-#endif
-
 #endif	       /* __CONFIG_H */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index ee39b3c..1696aa2 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -39,7 +39,6 @@
 
 /* I2C */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 /* I2C EEPROM */
 
@@ -49,8 +48,6 @@
 
 /* PCI express */
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(3, 29)
 #define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(7, 12)
 #endif
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 6be2147..97f47ea 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -66,7 +66,6 @@
 	BOOTENV
 
 /* OneNAND config */
-#define CONFIG_USE_ONENAND_BOARD_INIT
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 #define CONFIG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 2a24236..f4bf2ab 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -102,23 +102,16 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
@@ -348,8 +341,6 @@
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
 #endif
 
-#define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
-
 /*
  * I2C2 EEPROM
  */
@@ -393,8 +384,6 @@
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -421,9 +410,7 @@
 /*
  * Environment
  */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#elif defined(CONFIG_MTD_RAW_NAND)
+#if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define SPL_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index c3fef0d..451ae0e 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -11,8 +11,6 @@
 
 #define CONFIG_SYS_RAMBOOT
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 /* Needed to fill the ccsrbar pointer */
 
 /* Virtual address to CCSRBAR */
@@ -27,10 +25,6 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
 #endif
 
-/* Virtual address range for PCI region maps */
-#define CONFIG_SYS_PCI_MAP_START	0x80000000
-#define CONFIG_SYS_PCI_MAP_END		0xe0000000
-
 /* Virtual address to a temporary map if we need it (max 128MB) */
 #define CONFIG_SYS_TMPVIRT		0xe8000000
 
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index ae71262..409d5af 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -25,9 +25,4 @@
  */
 #define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
 
-/*
- * SuperH PCI Bridge Configration
- */
-#define CONFIG_SH7751_PCI
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 8b7e2e5..712a47a 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -21,9 +21,6 @@
 /* MMC */
 #define SDHCI_MAX_HOSTS		4
 
-/* PWM */
-#define CONFIG_PWM			1
-
 /* USB Composite download gadget - g_dnl */
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
@@ -129,10 +126,6 @@
 /* FLASH and environment organization */
 #define CONFIG_MMC_DEFAULT_DEV	0
 
-#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_SAMSUNG_ONENAND		1
 #define CONFIG_SYS_ONENAND_BASE		0xB0000000
 
-#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index ab4fe6b..137537d 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -87,12 +87,8 @@
 	"mmcrootpart=3\0" \
 	"opts=always_resume=1"
 
-#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_SAMSUNG_ONENAND
 #define CONFIG_SYS_ONENAND_BASE		0x0C000000
 
-#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-
 #ifndef	__ASSEMBLY__
 void universal_spi_scl(int bit);
 void universal_spi_sda(int bit);
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index a7b0ce9..1395b8d 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -24,9 +24,6 @@
  * select serial console configuration
  */
 
-/* PWM */
-#define CONFIG_PWM			1
-
 #define COMMON_BOOT	"console=ttySAC0,115200n8" \
 				" mem=128M " \
 				" " CONFIG_MTDPARTS_DEFAULT
@@ -89,22 +86,10 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
 
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
-#define CONFIG_ENABLE_MMU
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
-#else
-#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
-#endif
-
 /*-----------------------------------------------------------------------
  * Boot configuration
  */
 
-#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_SAMSUNG_ONENAND		1
 #define CONFIG_SYS_ONENAND_BASE		0xE7100000
 
 /*
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index bb0f547..0b1f0c5 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -10,8 +10,6 @@
 
 #include "exynos4-common.h"
 
-#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
-
 /* High Level Configuration Options */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 10ba2d2..4a7da76 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -52,13 +52,6 @@
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
- * Ethernet on SoC (EMAC)
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif
-
-/*
  * L4 OSC1 Timer 0
  */
 #ifndef CONFIG_TIMER
@@ -73,7 +66,6 @@
 /*
  * L4 Watchdog
  */
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
 
 /*
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index c388ae9..a3e8d54 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -89,15 +89,9 @@
  * Flash configurations
  */
 
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif /* CONFIG_CMD_NET */
-
 /*
  * L4 Watchdog
  */
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3309779..6a78cb1 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -22,7 +22,6 @@
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
-#define CONFIG_ENABLE_36BIT_PHYS	1
 
 /*
  * sysclk for MPC85xx
@@ -119,15 +118,11 @@
 #define CONFIG_SYS_LIME_BASE		0xc8000000
 #define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
 
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
 /*
  * General PCI
  * Memory space is mapped 1-1.
  */
 
-/* PCI is clocked by the external source at 33 MHz */
-#define CONFIG_PCI_CLK_FREQ	33000000
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 05ac900..df05ee4 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -20,9 +20,6 @@
 
 #define CONFIG_SYS_MAX_FLASH_SECT	8
 
-#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL	(8)
-#define CONFIG_DW_ALTDESCRIPTOR
-
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 2195fee..797d9bb 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
 
 /* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
 
 #define CONFIG_PRAM			2048	/* 2048 KB */
 
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index c57b1ad..567aa1f 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -20,10 +20,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR		0x00190000
 /* U-Boot Load Address */
 
-/* GMAC related configs */
-
-#define CONFIG_DW_ALTDESCRIPTOR
-
 /* Misc configuration */
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index dd2c5d7..c93df00 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -26,8 +26,6 @@
 
 /* PCI */
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
 #endif
 
diff --git a/include/configs/trats.h b/include/configs/trats.h
index bca239a..53f5a69 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -149,7 +149,6 @@
 #define LCD_BPP			LCD_COLOR16
 
 /* LCD */
-#define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 20bd116..b7449da 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -139,7 +139,6 @@
 #define LCD_BPP                 LCD_COLOR16
 
 /* LCD */
-#define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 7f4bfb5..32d9df0 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -26,7 +26,6 @@
 #define CONFIG_FEC_MXC_PHYADDR          0
 
 /* I2C Configs */
-#define CONFIG_SYS_SPD_BUS_NUM		0
 
 /*
  * We do have 128MB of memory on the Vybrid Tower board. Leave the last
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 9cc8fc5..6eb022f 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -45,8 +45,6 @@
 #define CONFIG_MXC_USB_FLAGS   0
 
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(4, 6)
 #endif
 
diff --git a/include/configs/x530.h b/include/configs/x530.h
index 1f1b4e1..cb12683 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -47,9 +47,6 @@
 
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
-/* PCIe support */
-#define CONFIG_PCI_SCAN_SHOW
-
 /* NAND */
 
 #include <asm/arch/config.h>
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index b45d2bb..4109af7 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -12,18 +12,6 @@
 #define CONFIG_X86_REFCODE_ADDR			0xffea0000
 #define CONFIG_X86_REFCODE_RUN_ADDR		0
 
-#define CONFIG_PCI_MEM_BUS	0xe0000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_PREF_BUS	0xd0000000
-#define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
-#define CONFIG_PCI_PREF_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x1000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0xefff
-
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index f28fafe..1366f62 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -45,11 +45,6 @@
  */
 
 /*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/*-----------------------------------------------------------------------
  * USB configuration
  */
 
diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h
index fb838db..3092a0e 100644
--- a/include/fsl_sec_mon.h
+++ b/include/fsl_sec_mon.h
@@ -23,8 +23,6 @@
 #define sec_mon_in16(a)       in_be16(a)
 #define sec_mon_clrbits32     clrbits_be32
 #define sec_mon_setbits32     setbits_be32
-#else
-#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
 #endif
 
 struct ccsr_sec_mon_regs {
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 613814d..e7674c1 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -24,8 +24,6 @@
 #define sfp_in32(a)       in_be32(a)
 #define sfp_out32(a, v)   out_be32(a, v)
 #define sfp_in16(a)       in_be16(a)
-#else
-#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
 #endif
 
 /* Number of SRKH registers */
diff --git a/include/i2c.h b/include/i2c.h
index 22add0b..e0ee94e 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -647,9 +647,6 @@
 #if !defined(CONFIG_SYS_RTC_BUS_NUM)
 #define CONFIG_SYS_RTC_BUS_NUM		0
 #endif
-#if !defined(CONFIG_SYS_SPD_BUS_NUM)
-#define CONFIG_SYS_SPD_BUS_NUM		0
-#endif
 
 struct i2c_adapter {
 	void		(*init)(struct i2c_adapter *adap, int speed,