Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip
u-boot-rockchip changes for 2019.04-rc1:
* support for Chromebook Bob
* full pinctrl driver using DTS properties
* documentation improvements
* I2S support for some Rockchip SoCs
diff --git a/Kconfig b/Kconfig
index a078f7b..2a48f53 100644
--- a/Kconfig
+++ b/Kconfig
@@ -224,6 +224,20 @@
which are not shipped in the U-Boot source tree.
Please, see doc/README.x86 for details.
+config BUILD_TARGET
+ string "Build target special images"
+ default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
+ default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
+ default "u-boot-elf.srec" if RCAR_GEN3
+ default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
+ default "u-boot.kwb" if KIRKWOOD
+ help
+ Some SoCs need special image types (e.g. U-Boot binary
+ with a special header) as build targets. By defining
+ CONFIG_BUILD_TARGET in the SoC / board header, this
+ special image will be automatically built upon calling
+ make / buildman.
+
endmenu # General setup
menu "Boot images"
diff --git a/MAINTAINERS b/MAINTAINERS
index 95e9bda..e3a1586 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -561,7 +561,7 @@
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
-F: drivers/net/ocelot_switch.c
+F: drivers/net/mscc_eswitch/
MIPS JZ4780
M: Ezequiel Garcia <ezequiel@collabora.com>
diff --git a/README b/README
index da033dc..b81500f 100644
--- a/README
+++ b/README
@@ -1986,13 +1986,6 @@
200 ms.
- Configuration Management:
- CONFIG_BUILD_TARGET
-
- Some SoCs need special image types (e.g. U-Boot binary
- with a special header) as build targets. By defining
- CONFIG_BUILD_TARGET in the SoC / board header, this
- special image will be automatically built upon calling
- make / buildman.
CONFIG_IDENT_STRING
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b396428..876c032 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -195,6 +195,7 @@
am335x-icev2.dtb \
am335x-pxm50.dtb \
am335x-rut.dtb \
+ am335x-shc.dtb \
am335x-pdu001.dtb \
am335x-chiliboard.dtb \
am335x-sl50.dtb \
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi
index 0341600..b6b97ed 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -7,3 +7,7 @@
&mmc3 {
status = "disabled";
};
+
+&usb0 {
+ dr_mode = "peripheral";
+};
diff --git a/arch/arm/dts/am335x-shc-u-boot.dtsi b/arch/arm/dts/am335x-shc-u-boot.dtsi
new file mode 100644
index 0000000..2975839
--- /dev/null
+++ b/arch/arm/dts/am335x-shc-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+/ {
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&l4_wkup {
+ u-boot,dm-pre-reloc;
+};
+
+&scm {
+ u-boot,dm-pre-reloc;
+};
+
+&am33xx_pinmux {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0_pins {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+ u-boot,dm-pre-reloc;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&emmc_pins {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc2 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1_pins {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc3 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts
new file mode 100644
index 0000000..5cdd309
--- /dev/null
+++ b/arch/arm/dts/am335x-shc.dts
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * support for the bosch am335x based shc c3 board
+ *
+ * Copyright, (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Bosch SHC";
+ compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
+
+ aliases {
+ mmcblk0 = &mmc1;
+ mmcblk1 = &mmc2;
+ };
+
+ cpus {
+ cpu@0 {
+ /*
+ * To consider voltage drop between PMIC and SoC,
+ * tolerance value is reduced to 2% from 4% and
+ * voltage value is increased as a precaution.
+ */
+ operating-points = <
+ /* kHz uV */
+ 594000 1225000
+ 294000 1125000
+ >;
+ voltage-tolerance = <2>; /* 2 percentage */
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ back_button {
+ label = "Back Button";
+ gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_BACK>;
+ debounce-interval = <1000>;
+ wakeup-source;
+ };
+
+ front_button {
+ label = "Front Button";
+ gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_FRONT>;
+ debounce-interval = <1000>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "shc:power:red";
+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "shc:power:bl";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ default-state = "on";
+ };
+
+ led3 {
+ label = "shc:lan:red";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led4 {
+ label = "shc:lan:bl";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led5 {
+ label = "shc:cloud:red";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led6 {
+ label = "shc:cloud:bl";
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ vmmcsd_fixed: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&aes {
+ status = "okay";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+
+ ethernetphy0: ethernet-phy@0 {
+ reg = <0>;
+ smsc,disable-energy-detect;
+ };
+};
+
+&epwmss1 {
+ status = "okay";
+
+ ehrpwm1: pwm@48302200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehrpwm1_pins>;
+ status = "okay";
+ };
+};
+
+&gpio1 {
+ hmtc_rst {
+ gpio-hog;
+ gpios = <24 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "homematic_reset";
+ };
+
+ hmtc_prog {
+ gpio-hog;
+ gpios = <27 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "homematic_program";
+ };
+};
+
+&gpio3 {
+ zgb_rst {
+ gpio-hog;
+ gpios = <18 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "zigbee_reset";
+ };
+
+ zgb_boot {
+ gpio-hog;
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "zigbee_boot";
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ at24@50 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+
+ pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+ slaves = <1>;
+ cpsw_emac0: slave@4a100200 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+ phy-handle = <ðernetphy0>;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ bus-width = <0x4>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ max-frequency = <26000000>;
+ vmmc-supply = <&vmmcsd_fixed>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ bus-width = <8>;
+ max-frequency = <26000000>;
+ sd-uhs-sdr25;
+ vmmc-supply = <&vmmcsd_fixed>;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ bus-width = <4>;
+ cap-power-off-card;
+ max-frequency = <26000000>;
+ sd-uhs-sdr25;
+ vmmc-supply = <&vmmcsd_fixed>;
+ status = "okay";
+};
+
+&rtc {
+ ti,no-init;
+};
+
+&sham {
+ status = "okay";
+};
+
+&tps {
+ compatible = "ti,tps65217";
+ ti,pmic-shutdown-controller;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dcdc1_reg: regulator@0 {
+ reg = <0>;
+ regulator-name = "vdds_dpr";
+ regulator-compatible = "dcdc1";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ reg = <1>;
+ /*
+ * VDD_MPU voltage limits 0.95V - 1.26V with
+ * +/-4% tolerance
+ */
+ regulator-compatible = "dcdc2";
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1375000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <70000>;
+ };
+
+ dcdc3_reg: regulator@2 {
+ reg = <2>;
+ /*
+ * VDD_CORE voltage limits 0.95V - 1.1V with
+ * +/-4% tolerance
+ */
+ regulator-name = "vdd_core";
+ regulator-compatible = "dcdc3";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ reg = <3>;
+ regulator-name = "vio,vrtc,vdds";
+ regulator-compatible = "ldo1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ reg = <4>;
+ regulator-name = "vdd_3v3aux";
+ regulator-compatible = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ reg = <5>;
+ regulator-name = "vdd_1v8";
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ reg = <6>;
+ regulator-name = "vdd_3v3a";
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ /* xdma_event_intr1.clkout2 */
+ AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+ /* mdio_clk.mdio_clk */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ ehrpwm1_pins: pinmux_ehrpwm1 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
+ >;
+ };
+
+ emmc_pins: pinmux_emmc_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
+ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
+ >;
+ };
+
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
+ AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
+ AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
+ AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
+ AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
+ AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
+ >;
+ };
+
+ uart1_pins: pinmux_uart1 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
+ AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
+ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
+ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
+ AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
+ >;
+ };
+
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+};
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index 1e2bb68..3527c0f 100644
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -20,6 +20,10 @@
display0 = &lcd0;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/dts/am4372-u-boot.dtsi b/arch/arm/dts/am4372-u-boot.dtsi
index 99922ca..986ae17 100644
--- a/arch/arm/dts/am4372-u-boot.dtsi
+++ b/arch/arm/dts/am4372-u-boot.dtsi
@@ -3,6 +3,13 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
+/{
+ aliases {
+ usb0 = &usb1;
+ usb1 = &usb2;
+ };
+};
+
&am43xx_control_usb2phy1 {
compatible = "ti,control-phy-usb2-am437", "syscon";
};
@@ -38,3 +45,23 @@
&ocp2scp0 {
u-boot,dm-spl;
};
+
+&dwc3_2 {
+ u-boot,dm-spl;
+};
+
+&usb2 {
+ u-boot,dm-spl;
+};
+
+&usb2_phy2 {
+ u-boot,dm-spl;
+};
+
+&am43xx_control_usb2phy2 {
+ u-boot,dm-spl;
+};
+
+&ocp2scp1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts
index a3c9b34..f04bc3e 100644
--- a/arch/arm/dts/da850-evm.dts
+++ b/arch/arm/dts/da850-evm.dts
@@ -94,6 +94,28 @@
regulator-boot-on;
};
+ baseboard_3v3: fixedregulator-3v3 {
+ /* TPS73701DCQ */
+ compatible = "regulator-fixed";
+ regulator-name = "baseboard_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vbat>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ baseboard_1v8: fixedregulator-1v8 {
+ /* TPS73701DCQ */
+ compatible = "regulator-fixed";
+ regulator-name = "baseboard_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vbat>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
backlight_lcd: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "lcd_backlight_pwr";
@@ -105,7 +127,7 @@
sound {
compatible = "simple-audio-card";
- simple-audio-card,name = "DA850/OMAP-L138 EVM";
+ simple-audio-card,name = "DA850-OMAPL138 EVM";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
@@ -210,10 +232,9 @@
/* Regulators */
IOVDD-supply = <&vdcdc2_reg>;
- /* Derived from VBAT: Baseboard 3.3V / 1.8V */
- AVDD-supply = <&vbat>;
- DRVDD-supply = <&vbat>;
- DVDD-supply = <&vbat>;
+ AVDD-supply = <&baseboard_3v3>;
+ DRVDD-supply = <&baseboard_3v3>;
+ DVDD-supply = <&baseboard_1v8>;
};
tca6416: gpio@20 {
compatible = "ti,tca6416";
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index ebd8ff9..9f1e0f6 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -181,7 +181,7 @@
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT)
return MMCSD_MODE_FS;
#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
return MMCSD_MODE_EMMCBOOT;
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index e2fe00c..a555319 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -106,7 +106,7 @@
#endif
/* Everything else use filesystem if available */
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index f165d10..e3235fc 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -40,11 +40,6 @@
#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
-/* Add target to build it automatically upon "make" */
-#ifdef CONFIG_SPL
-#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
-#endif
-
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d9bdcb3..1cac443 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -13,8 +13,8 @@
select ARM_ERRATA_725233
select USE_TINY_PRINTF
imply NAND_OMAP_GPMC
- imply SPL_EXT_SUPPORT
- imply SPL_FAT_SUPPORT
+ imply SPL_FS_EXT4
+ imply SPL_FS_FAT
imply SPL_GPIO_SUPPORT
imply SPL_I2C_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
@@ -35,8 +35,8 @@
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
- imply SPL_EXT_SUPPORT
- imply SPL_FAT_SUPPORT
+ imply SPL_FS_EXT4
+ imply SPL_FS_FAT
imply SPL_GPIO_SUPPORT
imply SPL_I2C_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
@@ -59,8 +59,8 @@
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
imply SPL_ENV_SUPPORT
- imply SPL_EXT_SUPPORT
- imply SPL_FAT_SUPPORT
+ imply SPL_FS_EXT4
+ imply SPL_FS_FAT
imply SPL_GPIO_SUPPORT
imply SPL_I2C_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 4f15346..4d47d09 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -38,8 +38,8 @@
imply SPL_DM
imply SPL_DM_SEQ_ALIAS
imply SPL_ENV_SUPPORT
- imply SPL_EXT_SUPPORT
- imply SPL_FAT_SUPPORT
+ imply SPL_FS_EXT4
+ imply SPL_FS_FAT
imply SPL_GPIO_SUPPORT
imply SPL_I2C_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
@@ -232,8 +232,8 @@
imply DM_SPI_FLASH
imply SPI_FLASH_BAR
imply SPL_ENV_SUPPORT
- imply SPL_EXT_SUPPORT
- imply SPL_FAT_SUPPORT
+ imply SPL_FS_EXT4
+ imply SPL_FS_FAT
imply SPL_GPIO_SUPPORT
imply SPL_I2C_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 3ea64f7..c97eacb 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -58,7 +58,7 @@
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index ccdc661..4c9f799 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -55,7 +55,7 @@
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index cc5dc4f..a3db20a 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -33,7 +33,7 @@
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 21dfebf..79f831e 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -3,7 +3,7 @@
config SPL_LDSCRIPT
default "arch/arm/mach-zynq/u-boot-spl.lds"
-config SPL_FAT_SUPPORT
+config SPL_FS_FAT
default y
config SPL_LIBCOMMON_SUPPORT
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 8a311e1..e9f7e7e 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -1,6 +1,6 @@
if ARCH_ZYNQMP
-config SPL_FAT_SUPPORT
+config SPL_FS_FAT
default y
config SPL_LIBCOMMON_SUPPORT
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index 951d8da..315172b 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -55,3 +55,54 @@
};
};
+&mdio0 {
+ status = "okay";
+};
+
+&port0 {
+ phy-handle = <&phy0>;
+};
+
+&port1 {
+ phy-handle = <&phy1>;
+};
+
+&port2 {
+ phy-handle = <&phy2>;
+};
+
+&port3 {
+ phy-handle = <&phy3>;
+};
+
+&port4 {
+ phy-handle = <&phy4>;
+};
+
+&port5 {
+ phy-handle = <&phy5>;
+};
+
+&port6 {
+ phy-handle = <&phy6>;
+};
+
+&port7 {
+ phy-handle = <&phy7>;
+};
+
+&port8 {
+ phy-handle = <&phy8>;
+};
+
+&port9 {
+ phy-handle = <&phy9>;
+};
+
+&port10 {
+ phy-handle = <&phy10>;
+};
+
+&port11 {
+ phy-handle = <&phy11>;
+};
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index bf638b2..9b4d628 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -61,3 +61,54 @@
};
};
+&mdio0 {
+ status = "okay";
+};
+
+&port0 {
+ phy-handle = <&phy0>;
+};
+
+&port1 {
+ phy-handle = <&phy1>;
+};
+
+&port2 {
+ phy-handle = <&phy2>;
+};
+
+&port3 {
+ phy-handle = <&phy3>;
+};
+
+&port4 {
+ phy-handle = <&phy4>;
+};
+
+&port5 {
+ phy-handle = <&phy5>;
+};
+
+&port6 {
+ phy-handle = <&phy6>;
+};
+
+&port7 {
+ phy-handle = <&phy7>;
+};
+
+&port8 {
+ phy-handle = <&phy8>;
+};
+
+&port9 {
+ phy-handle = <&phy9>;
+};
+
+&port10 {
+ phy-handle = <&phy10>;
+};
+
+&port11 {
+ phy-handle = <&phy11>;
+};
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index d11ec48..de354fe 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -92,5 +92,170 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ switch: switch@1010000 {
+ compatible = "mscc,vsc7527-switch";
+ reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
+ <0x1f0000 0x0100>, // VTSS_TO_DEV_1
+ <0x200000 0x0100>, // VTSS_TO_DEV_2
+ <0x210000 0x0100>, // VTSS_TO_DEV_3
+ <0x220000 0x0100>, // VTSS_TO_DEV_4
+ <0x230000 0x0100>, // VTSS_TO_DEV_5
+ <0x240000 0x0100>, // VTSS_TO_DEV_6
+ <0x250000 0x0100>, // VTSS_TO_DEV_7
+ <0x260000 0x0100>, // VTSS_TO_DEV_8
+ <0x270000 0x0100>, // VTSS_TO_DEV_9
+ <0x280000 0x0100>, // VTSS_TO_DEV_10
+ <0x290000 0x0100>, // VTSS_TO_DEV_11
+ <0x2a0000 0x0100>, // VTSS_TO_DEV_12
+ <0x2b0000 0x0100>, // VTSS_TO_DEV_13
+ <0x2c0000 0x0100>, // VTSS_TO_DEV_14
+ <0x2d0000 0x0100>, // VTSS_TO_DEV_15
+ <0x2e0000 0x0100>, // VTSS_TO_DEV_16
+ <0x2f0000 0x0100>, // VTSS_TO_DEV_17
+ <0x300000 0x0100>, // VTSS_TO_DEV_18
+ <0x310000 0x0100>, // VTSS_TO_DEV_19
+ <0x320000 0x0100>, // VTSS_TO_DEV_20
+ <0x330000 0x0100>, // VTSS_TO_DEV_21
+ <0x340000 0x0100>, // VTSS_TO_DEV_22
+ <0x350000 0x0100>, // VTSS_TO_DEV_23
+ <0x010000 0x1000>, // VTSS_TO_SYS
+ <0x020000 0x1000>, // VTSS_TO_ANA
+ <0x030000 0x1000>, // VTSS_TO_REW
+ <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
+ <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
+ <0x0a0000 0x0100>; // VTSS_TO_HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11",
+ "port12", "port13", "port14", "port15",
+ "port16", "port17", "port18", "port19",
+ "port20", "port21", "port22", "port23",
+ "sys", "ana", "rew", "gcb", "qs", "hsio";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ };
+ port11: port@11 {
+ reg = <11>;
+ };
+ port12: port@12 {
+ reg = <12>;
+ };
+ port13: port@13 {
+ reg = <13>;
+ };
+ port14: port@14 {
+ reg = <14>;
+ };
+ port15: port@15 {
+ reg = <15>;
+ };
+ port16: port@16 {
+ reg = <16>;
+ };
+ port17: port@17 {
+ reg = <17>;
+ };
+ port18: port@18 {
+ reg = <18>;
+ };
+ port19: port@19 {
+ reg = <19>;
+ };
+ port20: port@20 {
+ reg = <20>;
+ };
+ port21: port@21 {
+ reg = <21>;
+ };
+ port22: port@22 {
+ reg = <22>;
+ };
+ port23: port@23 {
+ reg = <23>;
+ };
+ };
+ };
+
+ mdio0: mdio@700a0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,luton-miim";
+ reg = <0x700a0 0x24>;
+ status = "disabled";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ };
};
};
diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS
index ae3c035..58104cc 100644
--- a/board/bosch/shc/MAINTAINERS
+++ b/board/bosch/shc/MAINTAINERS
@@ -6,6 +6,6 @@
F: configs/am335x_shc_defconfig
F: configs/am335x_shc_ict_defconfig
F: configs/am335x_shc_netboot_defconfig
-F: configs/am335x_shc_prompt_defconfig
F: configs/am335x_shc_sdboot_defconfig
-F: configs/am335x_shc_sdboot_prompt_defconfig
+F: arch/arm/dts/am335x-shc.dts
+F: arch/arm/dts/am335x-shc-u-boot.dtsi
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index 1ec9a3f..feed63b 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -38,10 +38,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#endif
static struct shc_eeprom __attribute__((section(".data"))) header;
static int shc_eeprom_valid;
@@ -254,7 +250,7 @@
}
}
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
@@ -275,6 +271,8 @@
leds_set_booting();
}
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
#define OSC (V_OSCK/1000000)
/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
@@ -464,120 +462,16 @@
return 0;
}
-#endif
-
-#ifndef CONFIG_DM_ETH
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
#endif
-/*
- * This function will:
- * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
- * in the environment
- * Perform fixups to the PHY present on certain boards. We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
- defined(CONFIG_SPL_USB_ETHER)) && \
- defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
- cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
-
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
+int board_eth_init(bd_t *bis)
+{
+ return usb_eth_initialize(bis);
}
#endif
-#endif /* CONFIG_DM_ETH */
-
#ifdef CONFIG_SHOW_BOOT_PROGRESS
static void bosch_check_reset_pin(void)
{
@@ -624,24 +518,9 @@
break;
}
}
-#endif
void arch_preboot_os(void)
{
leds_set_finish();
}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
- ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
- if (ret)
- return ret;
-
- ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
- return ret;
-}
#endif
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index eac4dca..58a4a04 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -64,6 +64,13 @@
}
}
+void board_debug_uart_init(void)
+{
+ /* too early for the pinctrl driver, so configure the UART pins here */
+ vcoreiii_gpio_set_alternate(10, 1);
+ vcoreiii_gpio_set_alternate(11, 1);
+}
+
static void do_board_detect(void)
{
int i;
@@ -73,6 +80,9 @@
for (i = 56; i < 60; i++)
vcoreiii_gpio_set_alternate(i, 1);
+ /* small delay for settling the pins */
+ mdelay(30);
+
if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
((pval >> 4) & 0x3F) == 0x3c) {
gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
diff --git a/common/bootm.c b/common/bootm.c
index a4618b6..7c7505f 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -59,8 +59,8 @@
mem_start = env_get_bootm_low();
mem_size = env_get_bootm_size();
- lmb_init_and_reserve(&images->lmb, (phys_addr_t)mem_start, mem_size,
- NULL);
+ lmb_init_and_reserve_range(&images->lmb, (phys_addr_t)mem_start,
+ mem_size, NULL);
}
#else
#define lmb_reserve(lmb, base, size)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 54b0dc3..5902852 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -387,7 +387,7 @@
is required since the network stack uses a number of environment
variables. See also SPL_NET_SUPPORT.
-config SPL_EXT_SUPPORT
+config SPL_FS_EXT4
bool "Support EXT filesystems"
help
Enable support for EXT2/3/4 filesystems with SPL. This permits
@@ -395,7 +395,7 @@
filesystem from within SPL. Support for the underlying block
device (e.g. MMC or USB) must be enabled separately.
-config SPL_FAT_SUPPORT
+config SPL_FS_FAT
bool "Support FAT filesystems"
select FS_FAT
help
@@ -404,6 +404,13 @@
filesystem from within SPL. Support for the underlying block
device (e.g. MMC or USB) must be enabled separately.
+config SPL_FAT_WRITE
+ bool "Support write for FAT filesystems"
+ help
+ Enable write support for FAT and VFAT filesystems with SPL.
+ Support for the underlying block device (e.g. MMC or USB) must be
+ enabled separately.
+
config SPL_FPGA_SUPPORT
bool "Support FPGAs"
help
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 6f8d759..e1daabf 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -23,8 +23,8 @@
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
-obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
-obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
+obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
+obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 4d55dcc..324d91c 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -238,7 +238,7 @@
{
int err = -ENOSYS;
-#ifdef CONFIG_SPL_FAT_SUPPORT
+#ifdef CONFIG_SPL_FS_FAT
if (!spl_start_uboot()) {
err = spl_load_image_fat_os(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
@@ -253,7 +253,7 @@
return err;
#endif
#endif
-#ifdef CONFIG_SPL_EXT_SUPPORT
+#ifdef CONFIG_SPL_FS_EXT4
if (!spl_start_uboot()) {
err = spl_load_image_ext_os(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
@@ -269,7 +269,7 @@
#endif
#endif
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
err = -ENOENT;
#endif
@@ -284,7 +284,7 @@
u32 __weak spl_boot_mode(const u32 boot_device)
{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
return MMCSD_MODE_EMMCBOOT;
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index d2c8825..aa8fee5 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
@@ -16,7 +16,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 21c5bdb..9241168 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -10,9 +10,14 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00080000
# CONFIG_CMD_FLASH is not set
@@ -51,7 +56,8 @@
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
-# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
deleted file mode 100644
index bda1785..0000000
--- a/configs/am335x_evm_usbspl_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_ETHER=y
-# CONFIG_SPL_YMODEM_SUPPORT is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NETCONSOLE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index b158fd1..faa6c2b 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -17,7 +17,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_YMODEM_SUPPORT is not set
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index e5f54a0..02332db 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -6,7 +6,7 @@
CONFIG_ISW_ENTRY_ADDR=0x40301950
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_SPL=y
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
@@ -20,7 +20,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index 7c3d7c0..ea2a68f 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -9,7 +9,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -17,7 +17,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index 2a8d318..05077c5 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LOCALVERSION="-EETS-1.0.0"
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 0eaf9c5..98efb6f 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -8,14 +8,16 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
@@ -32,15 +34,19 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 06339a9..94672f6 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -8,15 +8,17 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
@@ -33,15 +35,19 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 25582f3..ab7afdd 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -8,16 +8,18 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
@@ -34,15 +36,19 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
deleted file mode 100644
index 5a08c9b..0000000
--- a/configs/am335x_shc_prompt_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 7b74e85..ea77f4e 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -8,15 +8,17 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
@@ -33,15 +35,19 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
deleted file mode 100644
index 7b74e85..0000000
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SHC_SDBOOT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 20b64d5..678ead9 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -8,14 +8,14 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 0e210f0..530407b 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=10
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SYS_PROMPT="AM3517_CRANE # "
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 0fe3f7e..7a74e9e 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -13,7 +13,7 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
@@ -49,7 +49,11 @@
# CONFIG_TWL4030_POWER is not set
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index a17cf7c..8f6fd25 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -9,7 +9,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 237b9e8..d2ec2dd 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -10,7 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 3a25639..17015b9 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_DISTRO_DEFAULTS=y
@@ -17,7 +17,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index fd29396..af3dbcf 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_DISTRO_DEFAULTS=y
@@ -17,7 +17,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 7f4c8de..80bff7d 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -21,7 +21,7 @@
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index ceba006..a6c36ed 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
index fec5e60..c409d34 100644
--- a/configs/cl-som-am57x_defconfig
+++ b/configs/cl-som-am57x_defconfig
@@ -8,7 +8,7 @@
CONFIG_NR_DRAM_BANKS=2
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index b948b89..3df94d2 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index a27c502..cfbe97c 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -8,7 +8,7 @@
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index a2530b7..fe548f2 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
@@ -19,7 +19,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index be64c1a..60f679c 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index bc6b85f..b48d8e7 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=10
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
CONFIG_CMD_EEPROM=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index a6b03f9..525e0d9 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 0df8843..6391c1b 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -13,7 +13,7 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index ec5b96c..493f04f 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index c30a4dd..a70865c 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -10,7 +10,7 @@
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index 040e1e1..d80ca41 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -56,3 +56,9 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LZMA=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 7154e97..0fdd9b8 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
+CONFIG_MSCC_LUTON_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_DM_SERIAL=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 1635c69..33b961a 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -9,7 +9,7 @@
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
CONFIG_CMD_EEPROM=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 64a55e9..506e3a7 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -17,7 +17,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 40386c2..cc53b93 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -17,7 +17,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 3babfd5..c2750f4 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -16,7 +16,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 742a643..bcfeb30 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -15,7 +15,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index f3851b2..fa955aa 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -17,7 +17,7 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index a23bb8e..2134f6e 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -16,7 +16,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index c4061cf..c941dd2 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -16,7 +16,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index eab3c66..4c9c1cb 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -9,7 +9,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
@@ -23,7 +23,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 9581dd9..e199673 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -9,7 +9,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="BeagleBoard # "
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 2b8caf2..22e6233 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -9,7 +9,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 6b3fb31..8b71e26 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -7,7 +7,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 7ee9eea..9885f6a 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -8,7 +8,7 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 274549f..1780307 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
@@ -18,7 +18,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NET_SUPPORT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index a41ed14..27431ee 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
@@ -18,7 +18,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NET_SUPPORT=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 9665142..af4768f 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -22,7 +22,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index a0206f6f..b0c0520 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -17,7 +17,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index b573854..a1dbf5f 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index 491b4b0..2eb59e4 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -22,7 +22,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 67cfed6..49e6d5e 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -9,7 +9,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 21b5f12..edb1199 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -17,7 +17,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 3b99ca1..a317ebb 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -17,7 +17,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 527d4a3..06523de 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 09b64a3..7fbcdc3 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 8213469..2298d5b 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -18,7 +18,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 958d21b..6c712b2 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 13395ef..5f4abe8 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=82000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index e260554..5dcd80c 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=82000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 4e61692..d6c30e2 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index fd25261..49e2a73 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 3f3d2c9..3454aa1 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 0244360..404af1f 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 32ebb17..cbfb645 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 0b2067e..a121af4 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -13,7 +13,7 @@
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index dccece1..b614f97 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -23,7 +23,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPIO=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index b7ded76..deb2261 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -11,7 +11,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_PROMPT="sniper # "
# CONFIG_CMD_FLASH is not set
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 5f3d733..bc3a3a3 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -5,7 +5,7 @@
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_SPL=y
CONFIG_IDENT_STRING="socfpga_stratix10"
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=5
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index daca05e..01c7554 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -6,7 +6,7 @@
CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=3
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index b856b9d..2adf156 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -11,7 +11,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 8866d6d..c4c3dd9 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 381f464..2e8a598 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -8,7 +8,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 5632e6d..04c713f 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -7,7 +7,7 @@
CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=10
-# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="twister => "
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 0f0b786..a8cec9b 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -16,7 +16,7 @@
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPIO=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index b698fb7..eac1dc9 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -17,7 +17,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 136bc30..5725487 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -21,7 +21,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
index 983e61e..9026f00 100644
--- a/configs/xilinx_zynqmp_zc1232_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig
@@ -5,7 +5,7 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
index 10d3489..3eed069 100644
--- a/configs/xilinx_zynqmp_zc1254_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig
@@ -5,7 +5,7 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig
index 9ac3dd8..8bd7c9c 100644
--- a/configs/xilinx_zynqmp_zc1275_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig
@@ -5,7 +5,7 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig
index c154b15..9f023c2 100644
--- a/configs/xilinx_zynqmp_zc1275_revB_defconfig
+++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig
@@ -6,7 +6,7 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index bbbbb8e..fb369b1 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -5,7 +5,7 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index f3d02fd..908d92e 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -16,7 +16,7 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index f0b51b6..cca1f2d 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -19,7 +19,7 @@
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 1105b9f..cfe80b3 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -19,7 +19,7 @@
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index c15877d..70a76e6 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -6,7 +6,7 @@
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
CONFIG_SPL_STACK_R_ADDR=0x200000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index 60627da..2a6ffa5 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -6,7 +6,7 @@
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16"
CONFIG_SPL_STACK_R_ADDR=0x200000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index aa20971..8c92505 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
CONFIG_SPL_STACK_R_ADDR=0x200000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index a08bd29..630e392 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL=y
CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
CONFIG_SPL_STACK_R_ADDR=0x200000
-# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_FS_FAT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
diff --git a/doc/README.SPL b/doc/README.SPL
index fc1ca1a..7a30fef 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -53,8 +53,8 @@
CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o)
CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
-CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
-CONFIG_SPL_EXT_SUPPORT
+CONFIG_SPL_FS_FAT (fs/fat/libfat.o)
+CONFIG_SPL_FS_EXT4
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/raw/libnand.o)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 39ce4e8..6a57028 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -432,12 +432,7 @@
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
-config MSCC_OCELOT_SWITCH
- bool "Ocelot switch driver"
- depends on DM_ETH && ARCH_MSCC
- select PHYLIB
- help
- This driver supports the Ocelot network switch device.
+source "drivers/net/mscc_eswitch/Kconfig"
config ETHER_ON_FEC1
bool "FEC1"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e38c164..51be72b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,4 +75,4 @@
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-y += mscc_eswitch/
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
new file mode 100644
index 0000000..88e5a97
--- /dev/null
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Microsemi Corporation
+
+config MSCC_OCELOT_SWITCH
+ bool "Ocelot switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Ocelot network switch device.
+
+config MSCC_LUTON_SWITCH
+ bool "Luton switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Luton network switch device.
diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile
new file mode 100644
index 0000000..751a839
--- /dev/null
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c
new file mode 100644
index 0000000..6667614
--- /dev/null
+++ b/drivers/net/mscc_eswitch/luton_switch.c
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <miiphy.h>
+#include <net.h>
+#include <wait_bit.h>
+
+#include "mscc_miim.h"
+#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
+
+#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
+#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
+#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
+#define ANA_PORT_CPU_FWD_CFG(x) (0x50 + 0x80 * (x))
+#define ANA_PORT_CPU_FWD_CFG_SRC_COPY_ENA BIT(1)
+#define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x))
+#define ANA_PORT_PORT_CFG_RECV_ENA BIT(5)
+#define ANA_PGID(x) (0x1000 + 4 * (x))
+
+#define SYS_FRM_AGING 0x8300
+
+#define SYS_SYSTEM_RST_CFG 0x81b0
+#define SYS_SYSTEM_RST_MEM_INIT BIT(0)
+#define SYS_SYSTEM_RST_MEM_ENA BIT(1)
+#define SYS_SYSTEM_RST_CORE_ENA BIT(2)
+#define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x))
+#define SYS_PORT_MODE_INCL_INJ_HDR BIT(0)
+#define SYS_SWITCH_PORT_MODE(x) (0x8294 + 0x4 * (x))
+#define SYS_SWITCH_PORT_MODE_PORT_ENA BIT(3)
+#define SYS_EGR_NO_SHARING 0x8378
+#define SYS_SCH_CPU 0x85a0
+
+#define REW_PORT_CFG(x) (0x8 + 0x80 * (x))
+#define REW_PORT_CFG_IFH_INSERT_ENA BIT(7)
+
+#define GCB_DEVCPU_RST_SOFT_CHIP_RST 0x90
+#define GCB_DEVCPU_RST_SOFT_CHIP_RST_SOFT_PHY BIT(1)
+#define GCB_MISC_STAT 0x11c
+#define GCB_MISC_STAT_PHY_READY BIT(3)
+
+#define QS_XTR_MAP(x) (0x10 + 4 * (x))
+#define QS_XTR_MAP_GRP BIT(4)
+#define QS_XTR_MAP_ENA BIT(0)
+
+#define HSIO_PLL5G_CFG_PLL5G_CFG2 0x8
+
+#define HSIO_RCOMP_CFG_CFG0 0x20
+#define HSIO_RCOMP_CFG_CFG0_MODE_SEL(x) ((x) << 8)
+#define HSIO_RCOMP_CFG_CFG0_RUN_CAL BIT(12)
+#define HSIO_RCOMP_STATUS 0x24
+#define HSIO_RCOMP_STATUS_BUSY BIT(12)
+#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
+#define HSIO_SERDES6G_ANA_CFG_DES_CFG 0x64
+#define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(x) ((x) << 1)
+#define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(x) ((x) << 5)
+#define HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(x) ((x) << 10)
+#define HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(x) ((x) << 13)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG 0x68
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(x) ((x) << 4)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(x) ((x) << 7)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(x) ((x) << 9)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(x) ((x) << 14)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1 0x6c
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST BIT(0)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC BIT(2)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC BIT(3)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE BIT(6)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF BIT(7)
+#define HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(x) ((x) << 8)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG 0x70
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG_SR(x) ((x) << 4)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG_SR_H BIT(8)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(x) ((x) << 23)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG_POL BIT(29)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE BIT(30)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG1 0x74
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(x) (x)
+#define HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(x) ((x) << 6)
+#define HSIO_SERDES6G_ANA_CFG_COMMON_CFG 0x7c
+#define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(x) (x)
+#define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE BIT(18)
+#define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST BIT(31)
+#define HSIO_SERDES6G_ANA_CFG_PLL_CFG 0x80
+#define HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA BIT(7)
+#define HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
+#define HSIO_SERDES6G_ANA_CFG_SER_CFG 0x84
+#define HSIO_SERDES6G_DIG_CFG_MISC_CFG 0x88
+#define HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST BIT(0)
+#define HSIO_MCB_SERDES6G_CFG 0xac
+#define HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT BIT(31)
+#define HSIO_MCB_SERDES6G_CFG_ADDR(x) (x)
+
+#define DEV_GMII_PORT_MODE_CLK 0x0
+#define DEV_GMII_PORT_MODE_CLK_PHY_RST BIT(0)
+#define DEV_GMII_MAC_CFG_MAC_ENA 0xc
+#define DEV_GMII_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
+#define DEV_GMII_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
+
+#define DEV_PORT_MODE_CLK 0x4
+#define DEV_PORT_MODE_CLK_PHY_RST BIT(2)
+#define DEV_PORT_MODE_CLK_LINK_SPEED_1000 1
+#define DEV_MAC_CFG_MAC_ENA 0x10
+#define DEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
+#define DEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
+#define DEV_MAC_CFG_MAC_IFG 0x24
+#define DEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8)
+#define DEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4)
+#define DEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x)
+#define DEV_PCS1G_CFG_PCS1G_CFG 0x40
+#define DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0)
+#define DEV_PCS1G_CFG_PCS1G_MODE 0x44
+#define DEV_PCS1G_CFG_PCS1G_SD 0x48
+#define DEV_PCS1G_CFG_PCS1G_ANEG 0x4c
+#define DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16)
+
+#define IFH_INJ_BYPASS BIT(31)
+#define IFH_TAG_TYPE_C 0
+#define MAC_VID 1
+#define CPU_PORT 26
+#define INTERNAL_PORT_MSK 0xFFFFFF
+#define IFH_LEN 2
+#define ETH_ALEN 6
+#define PGID_BROADCAST 28
+#define PGID_UNICAST 29
+#define PGID_SRC 80
+
+enum luton_target {
+ PORT0,
+ PORT1,
+ PORT2,
+ PORT3,
+ PORT4,
+ PORT5,
+ PORT6,
+ PORT7,
+ PORT8,
+ PORT9,
+ PORT10,
+ PORT11,
+ PORT12,
+ PORT13,
+ PORT14,
+ PORT15,
+ PORT16,
+ PORT17,
+ PORT18,
+ PORT19,
+ PORT20,
+ PORT21,
+ PORT22,
+ PORT23,
+ SYS,
+ ANA,
+ REW,
+ GCB,
+ QS,
+ HSIO,
+ TARGET_MAX,
+};
+
+#define MAX_PORT (PORT23 - PORT0 + 1)
+
+#define MIN_INT_PORT PORT0
+#define MAX_INT_PORT (PORT11 - PORT0 + 1)
+#define MIN_EXT_PORT PORT12
+#define MAX_EXT_PORT MAX_PORT
+
+enum luton_mdio_target {
+ MIIM,
+ TARGET_MDIO_MAX,
+};
+
+enum luton_phy_id {
+ INTERNAL,
+ EXTERNAL,
+ NUM_PHY,
+};
+
+struct luton_private {
+ void __iomem *regs[TARGET_MAX];
+ struct mii_dev *bus[NUM_PHY];
+};
+
+static const unsigned long luton_regs_qs[] = {
+ [MSCC_QS_XTR_RD] = 0x18,
+ [MSCC_QS_XTR_FLUSH] = 0x28,
+ [MSCC_QS_XTR_DATA_PRESENT] = 0x2c,
+ [MSCC_QS_INJ_WR] = 0x3c,
+ [MSCC_QS_INJ_CTRL] = 0x44,
+};
+
+static const unsigned long luton_regs_ana_table[] = {
+ [MSCC_ANA_TABLES_MACHDATA] = 0x11b0,
+ [MSCC_ANA_TABLES_MACLDATA] = 0x11b4,
+ [MSCC_ANA_TABLES_MACACCESS] = 0x11b8,
+};
+
+static struct mscc_miim_dev miim[NUM_PHY];
+
+static struct mii_dev *luton_mdiobus_init(struct udevice *dev,
+ int mdiobus_id)
+{
+ unsigned long phy_size[NUM_PHY];
+ phys_addr_t phy_base[NUM_PHY];
+ struct ofnode_phandle_args phandle;
+ ofnode eth_node, node, mdio_node;
+ struct resource res;
+ struct mii_dev *bus;
+ fdt32_t faddr;
+ int i;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return NULL;
+
+ /* gather only the first mdio bus */
+ eth_node = dev_read_first_subnode(dev);
+ node = ofnode_first_subnode(eth_node);
+ ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
+ &phandle);
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ for (i = 0; i < TARGET_MDIO_MAX; i++) {
+ if (ofnode_read_resource(mdio_node, i, &res)) {
+ pr_err("%s: get OF resource failed\n", __func__);
+ return NULL;
+ }
+
+ faddr = cpu_to_fdt32(res.start);
+ phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
+ phy_size[i] = res.end - res.start;
+ }
+
+ strcpy(bus->name, "miim-internal");
+ miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id],
+ phy_size[mdiobus_id]);
+ bus->priv = &miim[mdiobus_id];
+ bus->read = mscc_miim_read;
+ bus->write = mscc_miim_write;
+
+ if (mdio_register(bus))
+ return NULL;
+ else
+ return bus;
+}
+
+static void luton_stop(struct udevice *dev)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+
+ /*
+ * Switch core only reset affects VCORE-III bus and MIPS frequency
+ * and thereby also the DDR SDRAM controller. The workaround is to
+ * not to redirect any trafic to the CPU after the data transfer.
+ */
+ writel(GENMASK(9, 2), priv->regs[SYS] + SYS_SCH_CPU);
+}
+
+static void luton_cpu_capture_setup(struct luton_private *priv)
+{
+ int i;
+
+ /* map the 8 CPU extraction queues to CPU port 26 */
+ writel(0x0, priv->regs[SYS] + SYS_SCH_CPU);
+
+ for (i = 0; i <= 1; i++) {
+ /*
+ * One to one mapping from CPU Queue number to Group extraction
+ * number
+ */
+ writel(QS_XTR_MAP_ENA | (QS_XTR_MAP_GRP * i),
+ priv->regs[QS] + QS_XTR_MAP(i));
+
+ /* Enable IFH insertion/parsing on CPU ports */
+ setbits_le32(priv->regs[REW] + REW_PORT_CFG(CPU_PORT + i),
+ REW_PORT_CFG_IFH_INSERT_ENA);
+
+ /* Enable IFH parsing on CPU port 0 and 1 */
+ setbits_le32(priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i),
+ SYS_PORT_MODE_INCL_INJ_HDR);
+ }
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
+ ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID,
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
+
+ /* Disable learning (only RECV_ENA must be set) */
+ writel(ANA_PORT_PORT_CFG_RECV_ENA,
+ priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
+
+ /* Enable switching to/from cpu port */
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(CPU_PORT),
+ SYS_SWITCH_PORT_MODE_PORT_ENA);
+
+ setbits_le32(priv->regs[SYS] + SYS_EGR_NO_SHARING, BIT(CPU_PORT));
+}
+
+static void luton_gmii_port_init(struct luton_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ writel(0, regs + DEV_GMII_PORT_MODE_CLK);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_GMII_MAC_CFG_MAC_ENA_RX_ENA |
+ DEV_GMII_MAC_CFG_MAC_ENA_TX_ENA,
+ regs + DEV_GMII_MAC_CFG_MAC_ENA);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
+ ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID,
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+
+ /* Enable switching to/from port */
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ SYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static void luton_port_init(struct luton_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ writel(0, regs + DEV_PORT_MODE_CLK);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
+ DEV_MAC_CFG_MAC_ENA_TX_ENA,
+ regs + DEV_MAC_CFG_MAC_ENA);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
+ ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID,
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+
+ /* Enable switching to/from port */
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ SYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static void luton_ext_port_init(struct luton_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ /* Enable PCS */
+ writel(DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA,
+ regs + DEV_PCS1G_CFG_PCS1G_CFG);
+
+ /* Disable Signal Detect */
+ writel(0, regs + DEV_PCS1G_CFG_PCS1G_SD);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
+ DEV_MAC_CFG_MAC_ENA_TX_ENA,
+ regs + DEV_MAC_CFG_MAC_ENA);
+
+ /* Clear sgmii_mode_ena */
+ writel(0, regs + DEV_PCS1G_CFG_PCS1G_MODE);
+
+ /*
+ * Clear sw_resolve_ena(bit 0) and set adv_ability to
+ * something meaningful just in case
+ */
+ writel(DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(0x20),
+ regs + DEV_PCS1G_CFG_PCS1G_ANEG);
+
+ /* Set MAC IFG Gaps */
+ writel(DEV_MAC_CFG_MAC_IFG_TX_IFG(7) |
+ DEV_MAC_CFG_MAC_IFG_RX_IFG1(1) |
+ DEV_MAC_CFG_MAC_IFG_RX_IFG2(5),
+ regs + DEV_MAC_CFG_MAC_IFG);
+
+ /* Set link speed and release all resets */
+ writel(DEV_PORT_MODE_CLK_LINK_SPEED_1000,
+ regs + DEV_PORT_MODE_CLK);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
+ ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID,
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+
+ /* Enable switching to/from port */
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ SYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static void serdes6g_write(struct luton_private *priv, u32 addr)
+{
+ u32 data;
+
+ writel(HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT |
+ HSIO_MCB_SERDES6G_CFG_ADDR(addr),
+ priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG);
+
+ do {
+ data = readl(priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG);
+ } while (data & HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT);
+
+ mdelay(100);
+}
+
+static void serdes6g_cfg(struct luton_private *priv)
+{
+ writel(HSIO_RCOMP_CFG_CFG0_MODE_SEL(0x3) |
+ HSIO_RCOMP_CFG_CFG0_RUN_CAL,
+ priv->regs[HSIO] + HSIO_RCOMP_CFG_CFG0);
+
+ while (readl(priv->regs[HSIO] + HSIO_RCOMP_STATUS) &
+ HSIO_RCOMP_STATUS_BUSY)
+ ;
+
+ writel(HSIO_SERDES6G_ANA_CFG_OB_CFG_SR(0xb) |
+ HSIO_SERDES6G_ANA_CFG_OB_CFG_SR_H |
+ HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(0x10) |
+ HSIO_SERDES6G_ANA_CFG_OB_CFG_POL |
+ HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE,
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG);
+ writel(HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(0x18) |
+ HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(0x1),
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG1);
+ writel(HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(0xc) |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(0x4) |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(0x5) |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(0xf) |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(0x4),
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG);
+ writel(HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF |
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(0x4),
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1);
+ writel(HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(0x5) |
+ HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(0x5) |
+ HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(0x2) |
+ HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(0x6),
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_DES_CFG);
+ writel(HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA |
+ HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(0x78),
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_PLL_CFG);
+ writel(HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(0x30) |
+ HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE,
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
+ /*
+ * There are 4 serdes6g, configure all except serdes6g0, therefore
+ * the address is b1110
+ */
+ serdes6g_write(priv, 0xe);
+
+ writel(readl(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) |
+ HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST,
+ priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
+ serdes6g_write(priv, 0xe);
+
+ clrbits_le32(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1,
+ HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST);
+ writel(HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST,
+ priv->regs[HSIO] + HSIO_SERDES6G_DIG_CFG_MISC_CFG);
+ serdes6g_write(priv, 0xe);
+}
+
+static int luton_switch_init(struct luton_private *priv)
+{
+ setbits_le32(priv->regs[HSIO] + HSIO_PLL5G_CFG_PLL5G_CFG2, BIT(1));
+ clrbits_le32(priv->regs[HSIO] + HSIO_PLL5G_CFG_PLL5G_CFG2, BIT(1));
+
+ /* Reset switch & memories */
+ writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
+ priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
+
+ /* Wait to complete */
+ if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
+ printf("Timeout in memory reset\n");
+ }
+
+ /* Enable switch core */
+ setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_CORE_ENA);
+
+ /* Setup the Serdes6g macros */
+ serdes6g_cfg(priv);
+
+ return 0;
+}
+
+static int luton_initialize(struct luton_private *priv)
+{
+ int ret, i;
+
+ /* Initialize switch memories, enable core */
+ ret = luton_switch_init(priv);
+ if (ret)
+ return ret;
+
+ /*
+ * Disable port-to-port by switching
+ * Put front ports in "port isolation modes" - i.e. they can't send
+ * to other ports - via the PGID sorce masks.
+ */
+ for (i = 0; i < MAX_PORT; i++)
+ writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
+
+ /* Flush queues */
+ mscc_flush(priv->regs[QS], luton_regs_qs);
+
+ /* Setup frame ageing - "2 sec" - The unit is 4ns on Luton*/
+ writel(2000000000 / 4,
+ priv->regs[SYS] + SYS_FRM_AGING);
+
+ for (i = PORT0; i < MAX_PORT; i++) {
+ if (i < PORT10)
+ luton_gmii_port_init(priv, i);
+ else
+ if (i == PORT10 || i == PORT11)
+ luton_port_init(priv, i);
+ else
+ luton_ext_port_init(priv, i);
+ }
+
+ luton_cpu_capture_setup(priv);
+
+ return 0;
+}
+
+static int luton_write_hwaddr(struct udevice *dev)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int luton_start(struct udevice *dev)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff };
+ int ret;
+
+ ret = luton_initialize(priv);
+ if (ret)
+ return ret;
+
+ /* Set MAC address tables entries for CPU redirection */
+ mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
+ mac, PGID_BROADCAST);
+
+ writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
+ priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
+
+ mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int luton_send(struct udevice *dev, void *packet, int length)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ u32 ifh[IFH_LEN];
+ int port = BIT(0); /* use port 0 */
+ u32 *buf = packet;
+
+ ifh[0] = IFH_INJ_BYPASS | port;
+ ifh[1] = (IFH_TAG_TYPE_C << 16);
+
+ return mscc_send(priv->regs[QS], luton_regs_qs,
+ ifh, IFH_LEN, buf, length);
+}
+
+static int luton_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ u32 *rxbuf = (u32 *)net_rx_packets[0];
+ int byte_cnt = 0;
+
+ byte_cnt = mscc_recv(priv->regs[QS], luton_regs_qs, rxbuf, IFH_LEN,
+ true);
+
+ *packetp = net_rx_packets[0];
+
+ return byte_cnt;
+}
+
+static int luton_probe(struct udevice *dev)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ int i;
+
+ struct {
+ enum luton_target id;
+ char *name;
+ } reg[] = {
+ { PORT0, "port0" },
+ { PORT1, "port1" },
+ { PORT2, "port2" },
+ { PORT3, "port3" },
+ { PORT4, "port4" },
+ { PORT5, "port5" },
+ { PORT6, "port6" },
+ { PORT7, "port7" },
+ { PORT8, "port8" },
+ { PORT9, "port9" },
+ { PORT10, "port10" },
+ { PORT11, "port11" },
+ { PORT12, "port12" },
+ { PORT13, "port13" },
+ { PORT14, "port14" },
+ { PORT15, "port15" },
+ { PORT16, "port16" },
+ { PORT17, "port17" },
+ { PORT18, "port18" },
+ { PORT19, "port19" },
+ { PORT20, "port20" },
+ { PORT21, "port21" },
+ { PORT22, "port22" },
+ { PORT23, "port23" },
+ { SYS, "sys" },
+ { ANA, "ana" },
+ { REW, "rew" },
+ { GCB, "gcb" },
+ { QS, "qs" },
+ { HSIO, "hsio" },
+ };
+
+ if (!priv)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(reg); i++) {
+ priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
+ if (!priv->regs[reg[i].id]) {
+ debug
+ ("Error can't get regs base addresses for %s\n",
+ reg[i].name);
+ return -ENOMEM;
+ }
+ }
+
+ /* Release reset in the CU-PHY */
+ writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST);
+
+ /* Ports with ext phy don't need to reset clk */
+ for (i = PORT0; i < MAX_INT_PORT; i++) {
+ if (i < PORT10)
+ clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK,
+ DEV_GMII_PORT_MODE_CLK_PHY_RST);
+ else
+ clrbits_le32(priv->regs[i] + DEV_PORT_MODE_CLK,
+ DEV_PORT_MODE_CLK_PHY_RST);
+ }
+
+ /* Wait for internal PHY to be ready */
+ if (wait_for_bit_le32(priv->regs[GCB] + GCB_MISC_STAT,
+ GCB_MISC_STAT_PHY_READY, true, 500, false))
+ return -EACCES;
+
+ priv->bus[INTERNAL] = luton_mdiobus_init(dev, INTERNAL);
+
+ for (i = 0; i < MAX_INT_PORT; i++) {
+ phy_connect(priv->bus[INTERNAL], i, dev,
+ PHY_INTERFACE_MODE_NONE);
+ }
+
+ /*
+ * coma_mode is need on only one phy, because all the other phys
+ * will be affected.
+ */
+ mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0x10);
+ mscc_miim_write(priv->bus[INTERNAL], 0, 0, 14, 0x800);
+ mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0);
+
+ return 0;
+}
+
+static int luton_remove(struct udevice *dev)
+{
+ struct luton_private *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < NUM_PHY; i++) {
+ mdio_unregister(priv->bus[i]);
+ mdio_free(priv->bus[i]);
+ }
+
+ return 0;
+}
+
+static const struct eth_ops luton_ops = {
+ .start = luton_start,
+ .stop = luton_stop,
+ .send = luton_send,
+ .recv = luton_recv,
+ .write_hwaddr = luton_write_hwaddr,
+};
+
+static const struct udevice_id mscc_luton_ids[] = {
+ {.compatible = "mscc,vsc7527-switch", },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(luton) = {
+ .name = "luton-switch",
+ .id = UCLASS_ETH,
+ .of_match = mscc_luton_ids,
+ .probe = luton_probe,
+ .remove = luton_remove,
+ .ops = &luton_ops,
+ .priv_auto_alloc_size = sizeof(struct luton_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.c b/drivers/net/mscc_eswitch/mscc_mac_table.c
new file mode 100644
index 0000000..833e233
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <linux/io.h>
+#include "mscc_mac_table.h"
+
+#define ANA_TABLES_MACACCESS_VALID BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE 0
+#define MACACCESS_CMD_LEARN 1
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ */
+enum macaccess_entry_type {
+ ENTRYTYPE_NORMAL = 0,
+ ENTRYTYPE_LOCKED,
+};
+
+static int vlan_wait_for_completion(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset)
+{
+ unsigned int val, timeout = 10;
+
+ /* Wait for the issued mac table command to be completed, or timeout.
+ * When the command read from ANA_TABLES_MACACCESS is
+ * MACACCESS_CMD_IDLE, the issued command completed successfully.
+ */
+ do {
+ val = readl(regs +
+ mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+ val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+ } while (val != MACACCESS_CMD_IDLE && timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid)
+{
+ u32 macl = 0, mach = 0;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+ * understood by the hardware.
+ */
+ mach |= MAC_VID << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ writel(macl, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACLDATA]);
+ writel(mach, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACHDATA]);
+
+ writel(ANA_TABLES_MACACCESS_VALID |
+ ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+ ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+ ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+ regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+
+ return vlan_wait_for_completion(regs, mscc_mac_table_offset);
+}
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.h b/drivers/net/mscc_eswitch/mscc_mac_table.h
new file mode 100644
index 0000000..17fed2e
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#define ETH_LEN 6
+#define MAC_VID 1
+
+enum mscc_regs_ana_table {
+ MSCC_ANA_TABLES_MACHDATA,
+ MSCC_ANA_TABLES_MACLDATA,
+ MSCC_ANA_TABLES_MACACCESS,
+};
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid);
diff --git a/drivers/net/mscc_eswitch/mscc_miim.c b/drivers/net/mscc_eswitch/mscc_miim.c
new file mode 100644
index 0000000..419dcc1
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <miiphy.h>
+#include <wait_bit.h>
+#include "mscc_miim.h"
+
+#define MIIM_STATUS 0x0
+#define MIIM_STAT_BUSY BIT(3)
+#define MIIM_CMD 0x8
+#define MIIM_CMD_SCAN BIT(0)
+#define MIIM_CMD_OPR_WRITE BIT(1)
+#define MIIM_CMD_OPR_READ BIT(2)
+#define MIIM_CMD_SINGLE_SCAN BIT(3)
+#define MIIM_CMD_WRDATA(x) ((x) << 4)
+#define MIIM_CMD_REGAD(x) ((x) << 20)
+#define MIIM_CMD_PHYAD(x) ((x) << 25)
+#define MIIM_CMD_VLD BIT(31)
+#define MIIM_DATA 0xC
+#define MIIM_DATA_ERROR (0x2 << 16)
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+ false, 250, false);
+}
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+ miim->regs + MIIM_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + MIIM_DATA);
+ if (val & MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+ MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+ return ret;
+}
diff --git a/drivers/net/mscc_eswitch/mscc_miim.h b/drivers/net/mscc_eswitch/mscc_miim.h
new file mode 100644
index 0000000..0e5d5e3
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ void __iomem *phy_regs;
+};
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg);
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val);
diff --git a/drivers/net/mscc_eswitch/mscc_xfer.c b/drivers/net/mscc_eswitch/mscc_xfer.c
new file mode 100644
index 0000000..f412901
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_xfer.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <linux/io.h>
+#include "mscc_xfer.h"
+
+#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
+#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
+#define QS_INJ_CTRL_EOF BIT(19)
+#define QS_INJ_CTRL_SOF BIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
+
+#define XTR_EOF_0 ntohl(0x80000000u)
+#define XTR_EOF_1 ntohl(0x80000001u)
+#define XTR_EOF_2 ntohl(0x80000002u)
+#define XTR_EOF_3 ntohl(0x80000003u)
+#define XTR_PRUNED ntohl(0x80000004u)
+#define XTR_ABORT ntohl(0x80000005u)
+#define XTR_ESCAPE ntohl(0x80000006u)
+#define XTR_NOT_READY ntohl(0x80000007u)
+
+#define BUF_CELL_SZ 60
+#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len)
+{
+ int i, count = (buff_len + 3) / 4, last = buff_len % 4;
+
+ writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+ regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ for (i = 0; i < ifh_len; i++)
+ writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ for (i = 0; i < count; i++)
+ writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ /* Add padding */
+ while (i < (BUF_CELL_SZ / 4)) {
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+ i++;
+ }
+
+ /* Indicate EOF and valid bytes in last word */
+ writel(QS_INJ_CTRL_GAP_SIZE(1) |
+ QS_INJ_CTRL_VLD_BYTES(buff_len < BUF_CELL_SZ ? 0 : last) |
+ QS_INJ_CTRL_EOF, regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ /* Add dummy CRC */
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ return 0;
+}
+
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *rxbuf, size_t ifh_len, bool byte_swap)
+{
+ u8 grp = 0; /* Recv everything on CPU group 0 */
+ int i, byte_cnt = 0;
+ bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+ if (!(readl(regs + mscc_qs_offset[MSCC_QS_XTR_DATA_PRESENT]) &
+ BIT(grp)))
+ return -EAGAIN;
+
+ /* skip IFH */
+ for (i = 0; i < ifh_len; i++)
+ readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+
+ while (!eof_flag) {
+ u32 val = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ u32 cmp = val;
+
+ if (byte_swap)
+ cmp = ntohl(val);
+
+ switch (cmp) {
+ case XTR_NOT_READY:
+ debug("%d NOT_READY...?\n", byte_cnt);
+ break;
+ case XTR_ABORT:
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ abort_flag = true;
+ eof_flag = true;
+ debug("XTR_ABORT\n");
+ break;
+ case XTR_EOF_0:
+ case XTR_EOF_1:
+ case XTR_EOF_2:
+ case XTR_EOF_3:
+ byte_cnt += XTR_VALID_BYTES(val);
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ eof_flag = true;
+ debug("EOF\n");
+ break;
+ case XTR_PRUNED:
+ /* But get the last 4 bytes as well */
+ eof_flag = true;
+ pruned_flag = true;
+ debug("PRUNED\n");
+ /* fallthrough */
+ case XTR_ESCAPE:
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ byte_cnt += 4;
+ rxbuf++;
+ debug("ESCAPED\n");
+ break;
+ default:
+ *rxbuf = val;
+ byte_cnt += 4;
+ rxbuf++;
+ }
+ }
+
+ if (abort_flag || pruned_flag || !eof_flag) {
+ debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
+ abort_flag, pruned_flag, eof_flag);
+ return -EAGAIN;
+ }
+
+ return byte_cnt;
+}
+
+void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset)
+{
+ /* All Queues flush */
+ setbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
+ QS_XTR_FLUSH_FLUSH);
+
+ /* Allow to drain */
+ mdelay(1);
+
+ /* All Queues normal */
+ clrbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
+ QS_XTR_FLUSH_FLUSH);
+}
diff --git a/drivers/net/mscc_eswitch/mscc_xfer.h b/drivers/net/mscc_eswitch/mscc_xfer.h
new file mode 100644
index 0000000..c880a4e
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_xfer.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+enum mscc_regs_qs {
+ MSCC_QS_XTR_RD,
+ MSCC_QS_XTR_FLUSH,
+ MSCC_QS_XTR_DATA_PRESENT,
+ MSCC_QS_INJ_WR,
+ MSCC_QS_INJ_CTRL,
+};
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len);
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *rxbuf, size_t ifh_len, bool byte_swap);
+void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset);
diff --git a/drivers/net/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c
similarity index 62%
rename from drivers/net/ocelot_switch.c
rename to drivers/net/mscc_eswitch/ocelot_switch.c
index 9fed26c..bf08c35 100644
--- a/drivers/net/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -15,19 +15,9 @@
#include <net.h>
#include <wait_bit.h>
-#define MIIM_STATUS 0x0
-#define MIIM_STAT_BUSY BIT(3)
-#define MIIM_CMD 0x8
-#define MIIM_CMD_SCAN BIT(0)
-#define MIIM_CMD_OPR_WRITE BIT(1)
-#define MIIM_CMD_OPR_READ BIT(2)
-#define MIIM_CMD_SINGLE_SCAN BIT(3)
-#define MIIM_CMD_WRDATA(x) ((x) << 4)
-#define MIIM_CMD_REGAD(x) ((x) << 20)
-#define MIIM_CMD_PHYAD(x) ((x) << 25)
-#define MIIM_CMD_VLD BIT(31)
-#define MIIM_DATA 0xC
-#define MIIM_DATA_ERROR (0x2 << 16)
+#include "mscc_miim.h"
+#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
#define PHY_CFG 0x0
#define PHY_CFG_ENA 0xF
@@ -41,17 +31,6 @@
#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
-#define ANA_TABLES_MACHDATA 0x8b34
-#define ANA_TABLES_MACLDATA 0x8b38
-#define ANA_TABLES_MACACCESS 0x8b3c
-#define ANA_TABLES_MACACCESS_VALID BIT(11)
-#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
-#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
-#define MACACCESS_CMD_IDLE 0
-#define MACACCESS_CMD_LEARN 1
-#define MACACCESS_CMD_GET_NEXT 4
#define ANA_PGID(x) (0x8c00 + 4 * (x))
#define SYS_FRM_AGING 0x574
@@ -99,37 +78,16 @@
#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
-#define QS_XTR_RD(x) (0x8 + 4 * (x))
-#define QS_XTR_FLUSH 0x18
-#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
-#define QS_XTR_DATA_PRESENT 0x1c
#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
-#define QS_INJ_WR(x) (0x2c + 4 * (x))
-#define QS_INJ_CTRL(x) (0x34 + 4 * (x))
-#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
-#define QS_INJ_CTRL_EOF BIT(19)
-#define QS_INJ_CTRL_SOF BIT(18)
-#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
-
-#define XTR_EOF_0 ntohl(0x80000000u)
-#define XTR_EOF_1 ntohl(0x80000001u)
-#define XTR_EOF_2 ntohl(0x80000002u)
-#define XTR_EOF_3 ntohl(0x80000003u)
-#define XTR_PRUNED ntohl(0x80000004u)
-#define XTR_ABORT ntohl(0x80000005u)
-#define XTR_ESCAPE ntohl(0x80000006u)
-#define XTR_NOT_READY ntohl(0x80000007u)
#define IFH_INJ_BYPASS BIT(31)
#define IFH_TAG_TYPE_C 0
-#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
#define MAC_VID 1
#define CPU_PORT 11
#define INTERNAL_PORT_MSK 0xF
#define IFH_LEN 4
-#define OCELOT_BUF_CELL_SZ 60
#define ETH_ALEN 6
#define PGID_BROADCAST 13
#define PGID_UNICAST 14
@@ -151,19 +109,6 @@
#define MAX_PORT (PORT3 - PORT0)
-/* MAC table entry types.
- * ENTRYTYPE_NORMAL is subject to aging.
- * ENTRYTYPE_LOCKED is not subject to aging.
- * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
- * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
- */
-enum macaccess_entry_type {
- ENTRYTYPE_NORMAL = 0,
- ENTRYTYPE_LOCKED,
- ENTRYTYPE_MACv4,
- ENTRYTYPE_MACv6,
-};
-
enum ocelot_mdio_target {
MIIM,
PHY,
@@ -178,33 +123,24 @@
struct ocelot_private {
void __iomem *regs[TARGET_MAX];
-
struct mii_dev *bus[NUM_PHY];
- struct phy_device *phydev;
- int phy_mode;
- int max_speed;
-
- int rx_pos;
- int rx_siz;
- int rx_off;
- int tx_num;
-
- u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
- void *tx_adj_buf;
};
-struct mscc_miim_dev {
- void __iomem *regs;
- void __iomem *phy_regs;
+static const unsigned long ocelot_regs_qs[] = {
+ [MSCC_QS_XTR_RD] = 0x8,
+ [MSCC_QS_XTR_FLUSH] = 0x18,
+ [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
+ [MSCC_QS_INJ_WR] = 0x2c,
+ [MSCC_QS_INJ_CTRL] = 0x34,
};
-struct mscc_miim_dev miim[NUM_PHY];
+static const unsigned long ocelot_regs_ana_table[] = {
+ [MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
+ [MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
+ [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
+};
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
- false, 250, false);
-}
+static struct mscc_miim_dev miim[NUM_PHY];
static int mscc_miim_reset(struct mii_dev *bus)
{
@@ -220,52 +156,6 @@
return 0;
}
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
- MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
- miim->regs + MIIM_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + MIIM_DATA);
- if (val & MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
- MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
- MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
- out:
- return ret;
-}
-
/* For now only setup the internal mdio bus */
static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
{
@@ -436,16 +326,6 @@
return 0;
}
-static void ocelot_switch_flush(struct ocelot_private *priv)
-{
- /* All Queues flush */
- setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
- /* Allow to drain */
- mdelay(1);
- /* All Queues normal */
- clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
-}
-
static int ocelot_initialize(struct ocelot_private *priv)
{
int ret, i;
@@ -463,7 +343,7 @@
writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
/* Flush queues */
- ocelot_switch_flush(priv);
+ mscc_flush(priv->regs[QS], ocelot_regs_qs);
/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
writel(SYS_FRM_AGING_ENA | (20000000 / 65),
@@ -479,62 +359,13 @@
return 0;
}
-static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
-{
- unsigned int val, timeout = 10;
-
- /* Wait for the issued mac table command to be completed, or timeout.
- * When the command read from ANA_TABLES_MACACCESS is
- * MACACCESS_CMD_IDLE, the issued command completed successfully.
- */
- do {
- val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
- val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
- } while (val != MACACCESS_CMD_IDLE && timeout--);
-
- if (!timeout)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int ocelot_mac_table_add(struct ocelot_private *priv,
- const unsigned char mac[ETH_ALEN], int pgid)
-{
- u32 macl = 0, mach = 0;
- int ret;
-
- /* Set the MAC address to handle and the vlan associated in a format
- * understood by the hardware.
- */
- mach |= MAC_VID << 16;
- mach |= ((u32)mac[0]) << 8;
- mach |= ((u32)mac[1]) << 0;
- macl |= ((u32)mac[2]) << 24;
- macl |= ((u32)mac[3]) << 16;
- macl |= ((u32)mac[4]) << 8;
- macl |= ((u32)mac[5]) << 0;
-
- writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
- writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
-
- writel(ANA_TABLES_MACACCESS_VALID |
- ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
- ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
- ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
- priv->regs[ANA] + ANA_TABLES_MACACCESS);
-
- ret = ocelot_vlant_wait_for_completion(priv);
-
- return ret;
-}
-
static int ocelot_write_hwaddr(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
@@ -554,13 +385,15 @@
return ret;
/* Set MAC address tables entries for CPU redirection */
- ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
+ PGID_BROADCAST);
writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
/* It should be setup latter in ocelot_write_hwaddr */
- ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
@@ -572,13 +405,8 @@
struct ocelot_private *priv = dev_get_priv(dev);
u32 ifh[IFH_LEN];
int port = BIT(0); /* use port 0 */
- u8 grp = 0; /* Send everything on CPU group 0 */
- int i, count = (length + 3) / 4, last = length % 4;
u32 *buf = packet;
- writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
- priv->regs[QS] + QS_INJ_CTRL(grp));
-
/*
* Generate the IFH for frame injection
*
@@ -595,91 +423,18 @@
ifh[2] = (0xff & port) << 24;
ifh[3] = (IFH_TAG_TYPE_C << 16);
- for (i = 0; i < IFH_LEN; i++)
- writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
-
- for (i = 0; i < count; i++)
- writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
-
- /* Add padding */
- while (i < (OCELOT_BUF_CELL_SZ / 4)) {
- writel(0, priv->regs[QS] + QS_INJ_WR(grp));
- i++;
- }
-
- /* Indicate EOF and valid bytes in last word */
- writel(QS_INJ_CTRL_GAP_SIZE(1) |
- QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
- QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
-
- /* Add dummy CRC */
- writel(0, priv->regs[QS] + QS_INJ_WR(grp));
-
- return 0;
+ return mscc_send(priv->regs[QS], ocelot_regs_qs,
+ ifh, IFH_LEN, buf, length);
}
static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct ocelot_private *priv = dev_get_priv(dev);
- u8 grp = 0; /* Send everything on CPU group 0 */
u32 *rxbuf = (u32 *)net_rx_packets[0];
- int i, byte_cnt = 0;
- bool eof_flag = false, pruned_flag = false, abort_flag = false;
-
- if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
- return -EAGAIN;
-
- /* skip IFH */
- for (i = 0; i < IFH_LEN; i++)
- readl(priv->regs[QS] + QS_XTR_RD(grp));
-
- while (!eof_flag) {
- u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ int byte_cnt;
- switch (val) {
- case XTR_NOT_READY:
- debug("%d NOT_READY...?\n", byte_cnt);
- break;
- case XTR_ABORT:
- /* really nedeed?? not done in linux */
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- abort_flag = true;
- eof_flag = true;
- debug("XTR_ABORT\n");
- break;
- case XTR_EOF_0:
- case XTR_EOF_1:
- case XTR_EOF_2:
- case XTR_EOF_3:
- byte_cnt += XTR_VALID_BYTES(val);
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- eof_flag = true;
- debug("EOF\n");
- break;
- case XTR_PRUNED:
- /* But get the last 4 bytes as well */
- eof_flag = true;
- pruned_flag = true;
- debug("PRUNED\n");
- /* fallthrough */
- case XTR_ESCAPE:
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- byte_cnt += 4;
- rxbuf++;
- debug("ESCAPED\n");
- break;
- default:
- *rxbuf = val;
- byte_cnt += 4;
- rxbuf++;
- }
- }
-
- if (abort_flag || pruned_flag || !eof_flag) {
- debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
- abort_flag, pruned_flag, eof_flag);
- return -EAGAIN;
- }
+ byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
+ false);
*packetp = net_rx_packets[0];
diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c
index 366f97b..4ed3c94 100644
--- a/drivers/power/regulator/pbias_regulator.c
+++ b/drivers/power/regulator/pbias_regulator.c
@@ -14,6 +14,11 @@
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <dm/read.h>
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#endif
struct pbias_reg_info {
u32 enable;
@@ -223,8 +228,11 @@
static int pbias_regulator_set_value(struct udevice *dev, int uV)
{
const struct pbias_reg_info *p = dev_get_priv(dev);
- int rc;
+ int rc, ret;
u32 reg;
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
+#endif
rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
if (rc)
@@ -240,7 +248,23 @@
debug("Setting %s voltage to %s\n", p->name,
(reg & p->vmode) ? "3.0v" : "1.8v");
- return pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ /* Disable extended drain IO before changing PBIAS */
+ wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
+ writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
+ }
+#endif
+ ret = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ /* Enable extended drain IO after changing PBIAS */
+ writel(wkup_ctrl |
+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+ OMAP34XX_CTRL_WKUP_CTRL);
+ }
+#endif
+ return ret;
}
static int pbias_regulator_get_enable(struct udevice *dev)
@@ -264,9 +288,20 @@
const struct pbias_reg_info *p = dev_get_priv(dev);
int rc;
u32 reg;
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
+#endif
debug("Turning %s %s\n", enable ? "on" : "off", p->name);
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ /* Disable extended drain IO before changing PBIAS */
+ wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
+ writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
+ }
+#endif
+
rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
if (rc)
return rc;
@@ -278,6 +313,16 @@
reg |= p->disable_val;
rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
+
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ /* Enable extended drain IO after changing PBIAS */
+ writel(wkup_ctrl |
+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+ OMAP34XX_CTRL_WKUP_CTRL);
+ }
+#endif
+
if (rc)
return rc;
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index e4993dc..0b5a1a4 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -2333,6 +2333,8 @@
}
/*-------------------------------------------------------------------------*/
+static void _usb_eth_halt(struct ether_priv *priv);
+
static int _usb_eth_init(struct ether_priv *priv)
{
struct eth_dev *dev = &priv->ethdev;
@@ -2406,6 +2408,7 @@
rx_submit(dev, dev->rx_req, 0);
return 0;
fail:
+ _usb_eth_halt(priv);
return -1;
}
@@ -2485,7 +2488,7 @@
return 0;
}
-void _usb_eth_halt(struct ether_priv *priv)
+static void _usb_eth_halt(struct ether_priv *priv)
{
struct eth_dev *dev = &priv->ethdev;
diff --git a/fs/Makefile b/fs/Makefile
index f21cd23..10c735a 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -6,8 +6,8 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_FS_LOADER) += fs.o
-obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
-obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
+obj-$(CONFIG_SPL_FS_FAT) += fat/
+obj-$(CONFIG_SPL_FS_EXT4) += ext4/
else
obj-y += fs.o
diff --git a/fs/fat/Makefile b/fs/fat/Makefile
index e64b61a..f84efac 100644
--- a/fs/fat/Makefile
+++ b/fs/fat/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_FS_FAT) := fat.o
-obj-$(CONFIG_FAT_WRITE):= fat_write.o
+obj-$(CONFIG_$(SPL_)FS_FAT) = fat.o
+obj-$(CONFIG_$(SPL_)FAT_WRITE) = fat_write.o
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 179bf4f..dac86ea 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -145,7 +145,8 @@
}
static int flush_dirty_fat_buffer(fsdata *mydata);
-#if !defined(CONFIG_FAT_WRITE)
+
+#if !CONFIG_IS_ENABLED(FAT_WRITE)
/* Stub for read only operation */
int flush_dirty_fat_buffer(fsdata *mydata)
{
diff --git a/fs/fs.c b/fs/fs.c
index 7fd2210..0e9c2f1 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -168,7 +168,7 @@
.exists = fat_exists,
.size = fat_size,
.read = fat_read_file,
-#ifdef CONFIG_FAT_WRITE
+#if CONFIG_IS_ENABLED(FAT_WRITE)
.write = file_fat_write,
.unlink = fat_unlink,
.mkdir = fat_mkdir,
@@ -183,7 +183,8 @@
.closedir = fat_closedir,
},
#endif
-#ifdef CONFIG_FS_EXT4
+
+#if CONFIG_IS_ENABLED(FS_EXT4)
{
.fstype = FS_TYPE_EXT,
.name = "ext4",
@@ -453,8 +454,7 @@
if (len && len < read_len)
read_len = len;
- lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
- gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
lmb_dump_all(&lmb);
if (lmb_alloc_addr(&lmb, addr, read_len) == addr)
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 07b65f8..d62fd35 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -13,7 +13,6 @@
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index d73752c..3c8c216 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -13,7 +13,6 @@
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index b10857a..b3b89d2 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -7,7 +7,7 @@
#define __CONFIG_GARDENA_SMART_GATEWAY_H
/* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index f8d3c3b6..5e54441 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -15,9 +15,6 @@
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/* Add target to build it automatically upon "make" */
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
-
/*
* Compression configuration
*/
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 720ff04..3d9a7dc 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -43,7 +43,7 @@
#endif
/* Define the payload for FAT/EXT support */
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
# ifdef CONFIG_OF_CONTROL
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
# else
diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h
index 1eb6cd8..aca32db 100644
--- a/include/configs/imx7_spl.h
+++ b/include/configs/imx7_spl.h
@@ -38,7 +38,7 @@
#endif
/* Define the payload for FAT/EXT support */
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
# ifdef CONFIG_OF_CONTROL
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
# else
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index 3bae92d..2adf385 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -7,7 +7,7 @@
#define __CONFIG_LINKIT_SMART_7688_H
/* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
index f424e2c..486650f 100644
--- a/include/configs/mv-plug-common.h
+++ b/include/configs/mv-plug-common.h
@@ -13,9 +13,6 @@
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/* Add target to build it automatically upon "make" */
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
index 1ca9a01..eb465e0 100644
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -15,9 +15,6 @@
#define CONFIG_KW88F6702 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/* add target to build it automatically upon "make" */
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
-
/* compression configuration */
#define CONFIG_BZIP2
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 6c2fa6a..06d5d32 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -12,7 +12,6 @@
#include <asm/arch/rmobile.h>
#define CONFIG_REMAKE_ELF
-#define CONFIG_BUILD_TARGET "u-boot-elf.srec"
/* boot option */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 3b32dd2..c9cbf8f 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -14,9 +14,6 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-/* add target to build it automatically upon "make" */
-#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
-
/*
* Memory configurations
*/
@@ -266,7 +263,7 @@
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ed0cfc2..b01d1c3 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -32,7 +32,6 @@
#endif
#ifdef CONFIG_ARM64
-#define CONFIG_BUILD_TARGET "u-boot.itb"
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#endif
diff --git a/include/lmb.h b/include/lmb.h
index e87c0b0..3b338df 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -4,6 +4,8 @@
#ifdef __KERNEL__
#include <asm/types.h>
+#include <asm/u-boot.h>
+
/*
* Logical memory blocks.
*
@@ -29,8 +31,9 @@
};
extern void lmb_init(struct lmb *lmb);
-extern void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, void *fdt_blob);
+extern void lmb_init_and_reserve(struct lmb *lmb, bd_t *bd, void *fdt_blob);
+extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size, void *fdt_blob);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
diff --git a/include/part.h b/include/part.h
index 0750aee..ebca546 100644
--- a/include/part.h
+++ b/include/part.h
@@ -246,7 +246,7 @@
*/
#ifdef CONFIG_SPL_BUILD
# define part_print_ptr(x) NULL
-# if defined(CONFIG_SPL_EXT_SUPPORT) || defined(CONFIG_SPL_FAT_SUPPORT) || \
+# if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
# define part_get_info_ptr(x) x
# else
diff --git a/lib/lmb.c b/lib/lmb.c
index 7aff2c2..b3b84e4 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -98,12 +98,8 @@
lmb->reserved.size = 0;
}
-/* Initialize the struct, add memory and call arch/board reserve functions */
-void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size,
- void *fdt_blob)
+static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
{
- lmb_init(lmb);
- lmb_add(lmb, base, size);
arch_lmb_reserve(lmb);
board_lmb_reserve(lmb);
@@ -111,6 +107,37 @@
boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
}
+/* Initialize the struct, add memory and call arch/board reserve functions */
+void lmb_init_and_reserve(struct lmb *lmb, bd_t *bd, void *fdt_blob)
+{
+#ifdef CONFIG_NR_DRAM_BANKS
+ int i;
+#endif
+
+ lmb_init(lmb);
+#ifdef CONFIG_NR_DRAM_BANKS
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (bd->bi_dram[i].size) {
+ lmb_add(lmb, bd->bi_dram[i].start,
+ bd->bi_dram[i].size);
+ }
+ }
+#else
+ if (bd->bi_memsize)
+ lmb_add(lmb, bd->bi_memstart, bd->bi_memsize);
+#endif
+ lmb_reserve_common(lmb, fdt_blob);
+}
+
+/* Initialize the struct, add memory and call arch/board reserve functions */
+void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size, void *fdt_blob)
+{
+ lmb_init(lmb);
+ lmb_add(lmb, base, size);
+ lmb_reserve_common(lmb, fdt_blob);
+}
+
/* This routine called with relocation disabled. */
static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size)
{
diff --git a/net/tftp.c b/net/tftp.c
index eca801a..34488b7 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -606,8 +606,7 @@
struct lmb lmb;
phys_size_t max_size;
- lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
- gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
max_size = lmb_get_free_size(&lmb, load_addr);
if (!max_size)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c05fc37..b425cc3 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -178,7 +178,6 @@
CONFIG_BTB
CONFIG_BUFNO_AUTO_INCR_BIT
CONFIG_BUILD_ENVCRC
-CONFIG_BUILD_TARGET
CONFIG_BUS_WIDTH
CONFIG_BZIP2
CONFIG_CADDY2
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 9a22852..ec68227 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -15,9 +15,11 @@
phys_addr_t base2, phys_size_t size2,
phys_addr_t base3, phys_size_t size3)
{
- ut_asserteq(lmb->memory.cnt, 1);
- ut_asserteq(lmb->memory.region[0].base, ram_base);
- ut_asserteq(lmb->memory.region[0].size, ram_size);
+ if (ram_size) {
+ ut_asserteq(lmb->memory.cnt, 1);
+ ut_asserteq(lmb->memory.region[0].base, ram_base);
+ ut_asserteq(lmb->memory.region[0].size, ram_size);
+ }
ut_asserteq(lmb->reserved.cnt, num_reserved);
if (num_reserved > 0) {
@@ -45,8 +47,9 @@
* Test helper function that reserves 64 KiB somewhere in the simulated RAM and
* then does some alloc + free tests.
*/
-static int test_multi_alloc(struct unit_test_state *uts,
- const phys_addr_t ram, const phys_size_t ram_size,
+static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram,
+ const phys_size_t ram_size, const phys_addr_t ram0,
+ const phys_size_t ram0_size,
const phys_addr_t alloc_64k_addr)
{
const phys_addr_t ram_end = ram + ram_size;
@@ -65,82 +68,119 @@
lmb_init(&lmb);
+ if (ram0_size) {
+ ret = lmb_add(&lmb, ram0, ram0_size);
+ ut_asserteq(ret, 0);
+ }
+
ret = lmb_add(&lmb, ram, ram_size);
ut_asserteq(ret, 0);
+ if (ram0_size) {
+ ut_asserteq(lmb.memory.cnt, 2);
+ ut_asserteq(lmb.memory.region[0].base, ram0);
+ ut_asserteq(lmb.memory.region[0].size, ram0_size);
+ ut_asserteq(lmb.memory.region[1].base, ram);
+ ut_asserteq(lmb.memory.region[1].size, ram_size);
+ } else {
+ ut_asserteq(lmb.memory.cnt, 1);
+ ut_asserteq(lmb.memory.region[0].base, ram);
+ ut_asserteq(lmb.memory.region[0].size, ram_size);
+ }
+
/* reserve 64KiB somewhere */
ret = lmb_reserve(&lmb, alloc_64k_addr, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
/* allocate somewhere, should be at the end of RAM */
a = lmb_alloc(&lmb, 4, 1);
ut_asserteq(a, ram_end - 4);
- ASSERT_LMB(&lmb, ram, ram_size, 2, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(&lmb, 0, 0, 2, alloc_64k_addr, 0x10000,
ram_end - 4, 4, 0, 0);
/* alloc below end of reserved region -> below reserved region */
b = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
ut_asserteq(b, alloc_64k_addr - 4);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 4, 0x10000 + 4, ram_end - 4, 4, 0, 0);
/* 2nd time */
c = lmb_alloc(&lmb, 4, 1);
ut_asserteq(c, ram_end - 8);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 4, 0x10000 + 4, ram_end - 8, 8, 0, 0);
d = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
ut_asserteq(d, alloc_64k_addr - 8);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0);
ret = lmb_free(&lmb, a, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
/* allocate again to ensure we get the same address */
a2 = lmb_alloc(&lmb, 4, 1);
ut_asserteq(a, a2);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0);
ret = lmb_free(&lmb, a2, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
ret = lmb_free(&lmb, b, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 3,
+ ASSERT_LMB(&lmb, 0, 0, 3,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000,
ram_end - 8, 4);
/* allocate again to ensure we get the same address */
b2 = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
ut_asserteq(b, b2);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
ret = lmb_free(&lmb, b2, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 3,
+ ASSERT_LMB(&lmb, 0, 0, 3,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000,
ram_end - 8, 4);
ret = lmb_free(&lmb, c, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2,
+ ASSERT_LMB(&lmb, 0, 0, 2,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, 0, 0);
ret = lmb_free(&lmb, d, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
+ if (ram0_size) {
+ ut_asserteq(lmb.memory.cnt, 2);
+ ut_asserteq(lmb.memory.region[0].base, ram0);
+ ut_asserteq(lmb.memory.region[0].size, ram0_size);
+ ut_asserteq(lmb.memory.region[1].base, ram);
+ ut_asserteq(lmb.memory.region[1].size, ram_size);
+ } else {
+ ut_asserteq(lmb.memory.cnt, 1);
+ ut_asserteq(lmb.memory.region[0].base, ram);
+ ut_asserteq(lmb.memory.region[0].size, ram_size);
+ }
+
return 0;
}
static int test_multi_alloc_512mb(struct unit_test_state *uts,
const phys_addr_t ram)
{
+ return test_multi_alloc(uts, ram, 0x20000000, 0, 0, ram + 0x10000000);
+}
+
+static int test_multi_alloc_512mb_x2(struct unit_test_state *uts,
+ const phys_addr_t ram,
+ const phys_addr_t ram0)
+{
- return test_multi_alloc(uts, ram, 0x20000000, ram + 0x10000000);
+ return test_multi_alloc(uts, ram, 0x20000000, ram0, 0x20000000,
+ ram + 0x10000000);
}
/* Create a memory region with one reserved region and allocate */
@@ -159,6 +199,22 @@
DM_TEST(lib_test_lmb_simple, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* Create two memory regions with one reserved region and allocate */
+static int lib_test_lmb_simple_x2(struct unit_test_state *uts)
+{
+ int ret;
+
+ /* simulate 512 MiB RAM beginning at 2GiB and 1 GiB */
+ ret = test_multi_alloc_512mb_x2(uts, 0x80000000, 0x40000000);
+ if (ret)
+ return ret;
+
+ /* simulate 512 MiB RAM beginning at 3.5GiB and 1 GiB */
+ return test_multi_alloc_512mb_x2(uts, 0xE0000000, 0x40000000);
+}
+
+DM_TEST(lib_test_lmb_simple_x2, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/* Simulate 512 MiB RAM, allocate some blocks that fit/don't fit */
static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram)
{
diff --git a/tools/dumpimage.c b/tools/dumpimage.c
index 7115df0..ee3d41d 100644
--- a/tools/dumpimage.c
+++ b/tools/dumpimage.c
@@ -60,27 +60,26 @@
int ifd = -1;
struct stat sbuf;
char *ptr;
- int retval = 0;
+ int retval = EXIT_SUCCESS;
struct image_type_params *tparams = NULL;
params.cmdname = *argv;
- while ((opt = getopt(argc, argv, "li:o:T:p:V")) != -1) {
+ while ((opt = getopt(argc, argv, "hlo:T:p:V")) != -1) {
switch (opt) {
case 'l':
params.lflag = 1;
break;
- case 'i':
- params.imagefile = optarg;
- params.iflag = 1;
- break;
case 'o':
params.outfile = optarg;
+ params.iflag = 1;
break;
case 'T':
params.type = genimg_get_type_id(optarg);
if (params.type < 0) {
- usage();
+ fprintf(stderr, "%s: Invalid type\n",
+ params.cmdname);
+ exit(EXIT_FAILURE);
}
break;
case 'p':
@@ -95,15 +94,24 @@
case 'V':
printf("dumpimage version %s\n", PLAIN_VERSION);
exit(EXIT_SUCCESS);
+ case 'h':
+ usage();
default:
usage();
break;
}
}
- if (optind >= argc)
+ if (argc < 2)
usage();
+ if (optind >= argc) {
+ fprintf(stderr, "%s: image file missing\n", params.cmdname);
+ exit(EXIT_FAILURE);
+ }
+
+ params.imagefile = argv[optind];
+
/* set tparams as per input type_id */
tparams = imagetool_get_type(params.type);
if (tparams == NULL) {
@@ -117,78 +125,69 @@
* as per image type to be generated/listed
*/
if (tparams->check_params) {
- if (tparams->check_params(¶ms))
- usage();
+ if (tparams->check_params(¶ms)) {
+ fprintf(stderr, "%s: Parameter check failed\n",
+ params.cmdname);
+ exit(EXIT_FAILURE);
+ }
}
- if (params.iflag)
- params.datafile = argv[optind];
- else
- params.imagefile = argv[optind];
- if (!params.outfile)
- params.outfile = params.datafile;
+ if (!params.lflag && !params.outfile) {
+ fprintf(stderr, "%s: No output file provided\n",
+ params.cmdname);
+ exit(EXIT_FAILURE);
+ }
ifd = open(params.imagefile, O_RDONLY|O_BINARY);
if (ifd < 0) {
- fprintf(stderr, "%s: Can't open \"%s\": %s\n",
- params.cmdname, params.imagefile,
- strerror(errno));
+ fprintf(stderr, "%s: Can't open \"%s\": %s\n", params.cmdname,
+ params.imagefile, strerror(errno));
exit(EXIT_FAILURE);
}
- if (params.lflag || params.iflag) {
- if (fstat(ifd, &sbuf) < 0) {
- fprintf(stderr, "%s: Can't stat \"%s\": %s\n",
- params.cmdname, params.imagefile,
- strerror(errno));
- exit(EXIT_FAILURE);
- }
+ if (fstat(ifd, &sbuf) < 0) {
+ fprintf(stderr, "%s: Can't stat \"%s\": %s\n", params.cmdname,
+ params.imagefile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
- if ((uint32_t)sbuf.st_size < tparams->header_size) {
- fprintf(stderr,
- "%s: Bad size: \"%s\" is not valid image\n",
- params.cmdname, params.imagefile);
- exit(EXIT_FAILURE);
- }
+ if ((uint32_t)sbuf.st_size < tparams->header_size) {
+ fprintf(stderr, "%s: Bad size: \"%s\" is not valid image\n",
+ params.cmdname, params.imagefile);
+ exit(EXIT_FAILURE);
+ }
- ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
- if (ptr == MAP_FAILED) {
- fprintf(stderr, "%s: Can't read \"%s\": %s\n",
- params.cmdname, params.imagefile,
- strerror(errno));
- exit(EXIT_FAILURE);
- }
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, "%s: Can't read \"%s\": %s\n", params.cmdname,
+ params.imagefile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ /*
+ * Both calls bellow scan through dumpimage registry for all
+ * supported image types and verify the input image file
+ * header for match
+ */
+ if (params.iflag) {
/*
- * Both calls bellow scan through dumpimage registry for all
- * supported image types and verify the input image file
- * header for match
+ * Extract the data files from within the matched
+ * image type. Returns the error code if not matched
*/
- if (params.iflag) {
- /*
- * Extract the data files from within the matched
- * image type. Returns the error code if not matched
- */
- retval = dumpimage_extract_subimage(tparams, ptr,
- &sbuf);
- } else {
- /*
- * Print the image information for matched image type
- * Returns the error code if not matched
- */
- retval = imagetool_verify_print_header(ptr, &sbuf,
- tparams, ¶ms);
- }
-
- (void)munmap((void *)ptr, sbuf.st_size);
- (void)close(ifd);
-
- return retval;
+ retval = dumpimage_extract_subimage(tparams, ptr, &sbuf);
+ } else {
+ /*
+ * Print the image information for matched image type
+ * Returns the error code if not matched
+ */
+ retval = imagetool_verify_print_header(ptr, &sbuf, tparams,
+ ¶ms);
}
+ (void)munmap((void *)ptr, sbuf.st_size);
(void)close(ifd);
- return EXIT_SUCCESS;
+ return retval;
}
static void usage(void)
@@ -197,14 +196,17 @@
" -l ==> list image header information\n",
params.cmdname);
fprintf(stderr,
- " %s -i image -T type [-p position] [-o outfile] data_file\n"
- " -i ==> extract from the 'image' a specific 'data_file'\n"
- " -T ==> set image type to 'type'\n"
- " -p ==> 'position' (starting at 0) of the 'data_file' inside the 'image'\n",
+ " %s [-T type] [-p position] [-o outfile] image\n"
+ " -T ==> declare image type as 'type'\n"
+ " -p ==> 'position' (starting at 0) of the component to extract from image\n"
+ " -o ==> extract component to file 'outfile'\n",
params.cmdname);
fprintf(stderr,
+ " %s -h ==> print usage information and exit\n",
+ params.cmdname);
+ fprintf(stderr,
" %s -V ==> print version information and exit\n",
params.cmdname);
- exit(EXIT_FAILURE);
+ exit(EXIT_SUCCESS);
}