arm: Migrate GICV2 / GICV3 to Kconfig
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig. We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 695c753..30fb7b6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -63,6 +63,12 @@
endif
endif
+config GICV2
+ bool
+
+config GICV3
+ bool
+
config GIC_V3_ITS
bool "ARM GICV3 ITS"
select REGMAP
@@ -953,6 +959,7 @@
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
+ select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
@@ -1063,6 +1070,7 @@
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GICV3
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SOC_DEVICE
@@ -1132,6 +1140,7 @@
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select FIRMWARE
+ select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
@@ -1881,6 +1890,7 @@
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
+ select GICV2
config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 3344730..9ca61b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -4,6 +4,7 @@
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
@@ -25,6 +26,7 @@
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
@@ -58,6 +60,7 @@
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -91,6 +94,7 @@
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -129,6 +133,7 @@
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -175,6 +180,7 @@
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -223,6 +229,7 @@
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
@@ -255,6 +262,7 @@
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 7a7f166..733373e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -123,7 +123,6 @@
#elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@@ -235,7 +234,6 @@
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index a6dcce1..9854974 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -4,61 +4,73 @@
config R8A774A1
bool "Renesas SoC R8A774A1"
+ select GICV2
imply CLK_R8A774A1
imply PINCTRL_PFC_R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
+ select GICV2
imply CLK_R8A774B1
imply PINCTRL_PFC_R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
+ select GICV2
imply CLK_R8A774C0
imply PINCTRL_PFC_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
+ select GICV2
imply CLK_R8A774E1
imply PINCTRL_PFC_R8A774E1
config R8A7795
bool "Renesas SoC R8A7795"
+ select GICV2
imply CLK_R8A7795
imply PINCTRL_PFC_R8A7795
config R8A7796
bool "Renesas SoC R8A7796"
+ select GICV2
imply CLK_R8A7796
imply PINCTRL_PFC_R8A7796
config R8A77965
bool "Renesas SoC R8A77965"
+ select GICV2
imply CLK_R8A77965
imply PINCTRL_PFC_R8A77965
config R8A77970
bool "Renesas SoC R8A77970"
+ select GICV2
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
config R8A77980
bool "Renesas SoC R8A77980"
+ select GICV2
imply CLK_R8A77980
imply PINCTRL_PFC_R8A77980
config R8A77990
bool "Renesas SoC R8A77990"
+ select GICV2
imply CLK_R8A77990
imply PINCTRL_PFC_R8A77990
config R8A77995
bool "Renesas SoC R8A77995"
+ select GICV2
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
config R8A779A0
bool "Renesas SoC R8A779A0"
+ select GICV3
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 478c7a9..3112664 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -124,6 +124,7 @@
config TEGRA210
bool "Tegra210 family"
+ select GICV2
select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST
select TEGRA_GPIO
@@ -137,6 +138,7 @@
config TEGRA186
bool "Tegra186 family"
select DM_MAILBOX
+ select GICV2
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index ebd2da3..0c6ad34 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -21,9 +21,6 @@
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
-config GICV3
- def_bool y
-
config SYS_MALLOC_LEN
default 0x2000000