commit 249ce73b3dafaf6334c0a08d8b1a84744df4817a
author Leo Yu-Chi Liang <ycliang@andestech.com> Tue Feb 14 20:42:49 2023 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Fri Feb 17 19:07:48 2023 +0800
tree e58677bfd533bfc4d9e95a69603f444ae6d84fae
parent 7b170665da09036053f910f6d6b6a8ee0b9506d3

riscv: Rename Andes cpu and board names

The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

configs/ae350_rv64_spl_xip_defconfig

diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 5a1fa8b..e0773fa 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -9,7 +9,7 @@
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_XIP=y