ppc4xx: Big lwmon5 board support rework/update
This patch brings the lwmon5 board support up-to-date. Here a
summary of the changes:
lwmon5 board port related:
- GPIO's changed to control the LSB transmitter
- Reset USB PHY's upon power-up
- Enable CAN upon power-up
- USB init error workaround (errata CHIP_6)
- EBC: Enable burstmode and modify the timings for the GDC memory
- EBC: Speed up NOR flash timings
lwmon5 board POST related:
- Add FPGA memory test
- Add GDC memory test
- DSP POST reworked
- SYSMON POST: Fix handling of negative temperatures
- Add output for sysmon1 POST
- HW-watchdog min. time test reworked
Additionally some coding-style changes were done.
Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 72e02f8..2349583 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@@ -18,58 +18,63 @@
* MA 02111-1307 USA
*/
-/************************************************************************
+/*
* lwmon5.h - configuration for lwmon5 board
- ***********************************************************************/
+ */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*-----------------------------------------------------------------------
+/*
+ * Liebherr extra version info
+ */
+#define CONFIG_IDENT_STRING " - v2.0"
+
+/*
* High Level Configuration Options
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_RESET 1 /* Call board_reset */
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
+#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
+#define CONFIG_MISC_INIT_R /* Call misc_init_r */
+#define CONFIG_BOARD_RESET /* Call board_reset */
-/*-----------------------------------------------------------------------
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+ */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_LIME_BASE_0 0xc0000000
-#define CONFIG_SYS_LIME_BASE_1 0xc1000000
-#define CONFIG_SYS_LIME_BASE_2 0xc2000000
-#define CONFIG_SYS_LIME_BASE_3 0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
+#define CONFIG_SYS_LIME_BASE_0 0xc0000000
+#define CONFIG_SYS_LIME_BASE_1 0xc1000000
+#define CONFIG_SYS_LIME_BASE_2 0xc2000000
+#define CONFIG_SYS_LIME_BASE_3 0xc3000000
+#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
+#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
/*
+ * Initial RAM & stack pointer
+ *
* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
* the POST_WORD from OCM to a 440EPx register that preserves it's
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
@@ -77,18 +82,18 @@
*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
+#define CONFIG_SYS_INIT_RAM_END (4 << 10)
#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+/* unused GPT0 COMP reg */
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
- /* unused GPT0 COMP reg */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
#define CONFIG_SYS_OCM_SIZE (16 << 10)
+/* 440EPx errata CHIP 11: don't use last 4kbytes */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
/* Additional registers for watchdog timer post test */
-
#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
@@ -100,9 +105,9 @@
#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
-/*-----------------------------------------------------------------------
+/*
* Serial Port
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@@ -110,77 +115,79 @@
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-/*-----------------------------------------------------------------------
+/*
* Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+ */
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-/*-----------------------------------------------------------------------
+/*
* FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH0 0xFC000000
#define CONFIG_SYS_FLASH1 0xF8000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-/*-----------------------------------------------------------------------
+/*
* DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
+ */
+#define CONFIG_SYS_MBYTES_SDRAM 256
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
-#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
-#define CONFIG_DDR_ECC 1 /* enable ECC */
-#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_DDR_ECC /* enable ECC */
/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC_ON | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_OCM | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SYSMON | \
- CONFIG_SYS_POST_WATCHDOG | \
- CONFIG_SYS_POST_DSP | \
- CONFIG_SYS_POST_BSPEC1 | \
- CONFIG_SYS_POST_BSPEC2 | \
- CONFIG_SYS_POST_BSPEC3 | \
- CONFIG_SYS_POST_BSPEC4 | \
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ECC | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_FPU | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_OCM | \
+ CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_SPR | \
+ CONFIG_SYS_POST_UART | \
+ CONFIG_SYS_POST_SYSMON | \
+ CONFIG_SYS_POST_WATCHDOG | \
+ CONFIG_SYS_POST_DSP | \
+ CONFIG_SYS_POST_BSPEC1 | \
+ CONFIG_SYS_POST_BSPEC2 | \
+ CONFIG_SYS_POST_BSPEC3 | \
+ CONFIG_SYS_POST_BSPEC4 | \
CONFIG_SYS_POST_BSPEC5)
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { UART0_BASE, UART1_BASE }
+
-#define CONFIG_POST_WATCHDOG {\
+#define CONFIG_POST_WATCHDOG { \
"Watchdog timer test", \
"watchdog", \
"This test checks the watchdog timer.", \
@@ -188,10 +195,10 @@
&lwmon5_watchdog_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_WATCHDOG \
+ CONFIG_SYS_POST_WATCHDOG \
}
-#define CONFIG_POST_BSPEC1 {\
+#define CONFIG_POST_BSPEC1 { \
"dsPIC init test", \
"dspic_init", \
"This test returns result of dsPIC READY test run earlier.", \
@@ -199,10 +206,10 @@
&dspic_init_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC1 \
+ CONFIG_SYS_POST_BSPEC1 \
}
-#define CONFIG_POST_BSPEC2 {\
+#define CONFIG_POST_BSPEC2 { \
"dsPIC test", \
"dspic", \
"This test gets result of dsPIC POST and dsPIC version.", \
@@ -210,32 +217,32 @@
&dspic_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC2 \
+ CONFIG_SYS_POST_BSPEC2 \
}
-#define CONFIG_POST_BSPEC3 {\
+#define CONFIG_POST_BSPEC3 { \
"FPGA test", \
"fpga", \
"This test checks FPGA registers and memory.", \
- POST_RAM | POST_ALWAYS, \
+ POST_RAM | POST_ALWAYS | POST_MANUAL, \
&fpga_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC3 \
+ CONFIG_SYS_POST_BSPEC3 \
}
-#define CONFIG_POST_BSPEC4 {\
+#define CONFIG_POST_BSPEC4 { \
"GDC test", \
"gdc", \
"This test checks GDC registers and memory.", \
- POST_RAM | POST_ALWAYS, \
+ POST_RAM | POST_ALWAYS | POST_MANUAL,\
&gdc_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC4 \
+ CONFIG_SYS_POST_BSPEC4 \
}
-#define CONFIG_POST_BSPEC5 {\
+#define CONFIG_POST_BSPEC5 { \
"SYSMON1 test", \
"sysmon1", \
"This test checks GPIO_62_EPX pin indicating power failure.", \
@@ -243,7 +250,7 @@
&sysmon1_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC5 \
+ CONFIG_SYS_POST_BSPEC5 \
}
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
@@ -253,34 +260,53 @@
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-/*-----------------------------------------------------------------------
+/*
* I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
+#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
+#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
+#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
+
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
/* 64 byte page write mode using*/
/* last 6 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
-#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
-#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
+#define I2C_ADDR_LIST { \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_2_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
-#if 0
-#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d sec...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
-#endif
#define CONFIG_PREBOOT "setenv bootdelay 15"
@@ -314,15 +340,11 @@
"cp.b 200000 FFF80000 80000\0" \
"upd=run load update\0" \
"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
- "source 200000\0" \
+ "autoscr 200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@@ -410,9 +432,9 @@
#define CONFIG_CMD_USB
#endif
-/*-----------------------------------------------------------------------
+/*
* Miscellaneous configurable options
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -445,9 +467,9 @@
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *----------------------------------------------------------------------*/
+ */
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
@@ -461,29 +483,32 @@
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
#define CONFIG_WD_PERIOD 40000 /* in usec */
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03050200
+#define CONFIG_SYS_EBC_PB0AP 0x03000280
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
/* Memory Bank 1 (Lime) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x01004380
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000)
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x01004400
@@ -495,19 +520,27 @@
#define CONFIG_SYS_EBC_CFG 0xb8400000
-/*-----------------------------------------------------------------------
+/*
* Graphics (Fujitsu Lime)
- *----------------------------------------------------------------------*/
+ */
+/* SDRAM Clock frequency adjustment register */
+#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
+#if 1 /* 133MHz is not tested enough, use 100MHz for now */
/* Lime Clock frequency is to set 100MHz */
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
-#if 0
+#else
/* Lime Clock frequency for 133MHz */
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
#endif
-/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- and pixel flare on display when 133MHz was configured. According to
- SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+/* SDRAM Parameter register */
+#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
+/*
+ * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ * and pixel flare on display when 133MHz was configured. According to
+ * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
+ * Grade
+ */
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
@@ -516,13 +549,15 @@
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
#endif
-/*-----------------------------------------------------------------------
+/*
* GPIO Setup
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_PHY0_RST 22
#define CONFIG_SYS_GPIO_DSPIC_READY 51
+#define CONFIG_SYS_GPIO_CAN_ENABLE 53
+#define CONFIG_SYS_GPIO_LSB_ENABLE 54
#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
#define CONFIG_SYS_GPIO_HIGHSIDE 56
#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
@@ -532,7 +567,7 @@
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_WATCHDOG 63
-/*-----------------------------------------------------------------------
+/*
* PPC440 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \