imx8ulp: clock: Support to enable/disable the ADC1 clock
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index 745fd7f..e15ef1d 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -56,6 +56,10 @@
PLL4_PFD2_DIV2,
PLL4_PFD3_DIV1,
PLL4_PFD3_DIV2,
+ CM33_BUSCLK,
+ PLL1_VCO_DIV,
+ PLL0_PFD2_DIV,
+ PLL0_PFD1_DIV,
};
struct cgc1_regs {
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index cc70284..c0f32cc 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -41,4 +41,5 @@
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
void reset_lcdclk(void);
void enable_mipi_dsi_clk(unsigned char enable);
+void enable_adc1_clk(bool enable);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index af6845c..91adc85 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -30,6 +30,7 @@
#define PCC_XRDC_MGR_ADDR 0x292d00bc
+#define PCC1_RBASE 0x28091000
#define PCC3_RBASE 0x292d0000
#define PCC4_RBASE 0x29800000
#define PCC5_RBASE 0x2da70000
diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 4680154..46386f1 100644
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -8,6 +8,10 @@
#include <asm/arch/cgc.h>
+enum pcc1_entry {
+ ADC1_PCC1_SLOT = 34,
+};
+
enum pcc3_entry {
DMA1_MP_PCC3_SLOT = 1,
DMA1_CH0_PCC3_SLOT = 2,