tree 202fc206bcd9b7023f816a9d03454925e0c45d3c
parent 7d4195c41f62445c5a492a122891382545184b8a
author Ye Li <ye.li@nxp.com> 1616140634 +0800
committer Stefano Babic <sbabic@denx.de> 1617866309 +0200

imx8m: ddr: Disable CA VREF Training for LPDDR4

Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D.  According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>