commit 21df1a434a9060350cb2d6563d98b58b11b4a44d
author Stefan Roese <sr@denx.de> Mon Nov 27 14:46:06 2006 +0100
committer Stefan Roese <sr@denx.de> Mon Nov 27 14:46:06 2006 +0100
tree 980ba07ed67b7e2b9276973c487f4b0b74f9eb24
parent 2a4a943d1144a2a11a1d9020224419542088b852

[PATCH] Remove testing 4xx enet PHY setup

Signed-off-by: Stefan Roese <sr@denx.de>

cpu/ppc4xx/4xx_enet.c

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 8c517ba..7a2483c 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -560,22 +560,7 @@
 	 * otherwise, just check the speeds & feeds
 	 */
 	if (hw_p->first_init == 0) {
-#if defined(CONFIG_88E1111_CLK_DELAY)
-		/*
-		 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
-		 * the "RGMII transmit timing control" and "RGMII receive
-		 * timing control" bits set, so that Gbit communication works
-		 * without problems.
-		 * Also set the "Transmitter disable" to 1 to enable the
-		 * transmitter.
-		 * After setting these bits a soft-reset must occur for this
-		 * change to become active.
-		 */
-		miiphy_read (dev->name, reg, 0x14, &reg_short);
-		reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
-		miiphy_write (dev->name, reg, 0x14, reg_short);
-#endif
-#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+#if defined(CONFIG_M88E1111_PHY)
 		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
 		miiphy_write (dev->name, reg, 0x18, 0x4101);
 		miiphy_write (dev->name, reg, 0x09, 0x0e00);