clk: renesas: Add support for RPCD2 clock

This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 09d84c4..763e268 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -289,6 +289,7 @@
 		return -EINVAL;
 
 	case CLK_TYPE_GEN3_RPC:
+	case CLK_TYPE_GEN3_RPCD2:
 		rate = gen3_clk_get_rate64(&parent);
 
 		value = readl(priv->base + core->offset);
@@ -304,13 +305,21 @@
 
 		postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
 			  CPG_RPC_POSTDIV_MASK;
-		rate /= postdiv + 1;
 
-		debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
-		      __func__, __LINE__,
-		      core->parent, prediv, postdiv, rate);
+		if (postdiv % 2 != 0) {
+			rate /= postdiv + 1;
+
+			if (core->type == CLK_TYPE_GEN3_RPCD2)
+				rate /= 2;
+
+			debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
+			      __func__, __LINE__,
+			      core->parent, prediv, postdiv, rate);
+
+			return rate;
+		}
 
-		return rate;
+		return -EINVAL;
 
 	}