Blackfin: Remove
The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 6f1c419..ed9659a 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -4,7 +4,6 @@
obj-y += bootcount.o
obj-$(CONFIG_AT91SAM9XE) += bootcount_at91.o
-obj-$(CONFIG_BLACKFIN) += bootcount_blackfin.o
obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
diff --git a/drivers/bootcount/bootcount_blackfin.c b/drivers/bootcount/bootcount_blackfin.c
deleted file mode 100644
index 6cf6dd5..0000000
--- a/drivers/bootcount/bootcount_blackfin.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * functions for handling bootcount support
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-/* This version uses one 32bit storage and combines the magic/count */
-
-#include <common.h>
-
-/* We abuse the EVT0 MMR for bootcount storage by default */
-#ifndef CONFIG_SYS_BOOTCOUNT_ADDR
-# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0
-#endif
-
-#define MAGIC_MASK 0xffff0000
-#define COUNT_MASK 0x0000ffff
-
-void bootcount_store(ulong cnt)
-{
- ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK);
- bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic);
-}
-
-ulong bootcount_load(void)
-{
- ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR);
- if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK))
- return magic & COUNT_MASK;
- else
- return 0;
-}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 446af22..4872c1d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@
obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c
deleted file mode 100644
index 4ed0923..0000000
--- a/drivers/i2c/pca9564_i2c.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * File: drivers/i2c/pca9564.c
- * Based on: drivers/i2c/s3c44b0_i2c.c
- * Author:
- *
- * Created: 2009-06-23
- * Description: PCA9564 i2c bridge driver
- *
- * Modified:
- * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *
- * Bugs:
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <pca9564.h>
-#include <asm/io.h>
-
-#define PCA_STA (CONFIG_PCA9564_BASE + 0)
-#define PCA_TO (CONFIG_PCA9564_BASE + 0)
-#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2))
-#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2))
-#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2))
-
-static unsigned char pca_read_reg(unsigned int reg)
-{
- return readb((void *)reg);
-}
-
-static void pca_write_reg(unsigned int reg, unsigned char value)
-{
- writeb(value, (void *)reg);
-}
-
-static int pca_wait_busy(void)
-{
- unsigned int timeout = 10000;
-
- while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout)
- udelay(1);
-
- if (timeout == 0)
- debug("I2C timeout!\n");
-
- debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON),
- pca_read_reg(PCA_STA));
-
- return timeout ? 0 : 1;
-}
-
-/*=====================================================================*/
-/* Public Functions */
-/*=====================================================================*/
-
-/*-----------------------------------------------------------------------
- * Initialization
- */
-void i2c_init(int speed, int slaveaddr)
-{
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed);
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-
-int i2c_probe(uchar chip)
-{
- unsigned char res;
-
- pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
- pca_wait_busy();
-
- pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1) | 1);
- res = pca_wait_busy();
-
- if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48))
- res = 1;
-
- pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
- return res;
-}
-
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int i;
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1));
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- if (alen > 0) {
- pca_write_reg(PCA_DAT, addr);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
- udelay(500);
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1) | 1);
- pca_wait_busy();
-
- for (i = 0; i < len; ++i) {
- if (i == len - 1)
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- else
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA);
-
- pca_wait_busy();
- buffer[i] = pca_read_reg(PCA_DAT);
-
- }
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
- return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int i;
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, chip << 1);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- if (alen > 0) {
- pca_write_reg(PCA_DAT, addr);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- for (i = 0; i < len; ++i) {
- pca_write_reg(PCA_DAT, buffer[i]);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
- return 0;
-}
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d9e5fc9..b025001 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -241,7 +241,6 @@
chip->write_buf(mtd, (uint8_t *)&word, 2);
}
-#if !defined(CONFIG_BLACKFIN)
static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
{
int i;
@@ -274,7 +273,6 @@
for (i = 0; i < len; i++)
writew(p[i], addr);
}
-#endif
/**
* nand_write_buf - [DEFAULT] write buffer to chip
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 5197f36..a31f6f6 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -253,8 +253,6 @@
#ifdef CONFIG_ADNPESC1
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
-#elif CONFIG_BLACKFIN
-#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#elif CONFIG_ARM64
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
@@ -264,11 +262,6 @@
#ifdef CONFIG_ADNPESC1
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
-#elif CONFIG_BLACKFIN
-#define SMC_outw(a, d, r) \
- ({ (*((volatile word*)((a)->iobase+((r)))) = d); \
- SSYNC(); \
- })
#elif CONFIG_ARM64
#define SMC_outw(a, d, r) \
(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 84a22ce..4ed4bba 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,7 +35,6 @@
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
-obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
diff --git a/drivers/serial/serial_bfin.c b/drivers/serial/serial_bfin.c
deleted file mode 100644
index 1d5be2a..0000000
--- a/drivers/serial/serial_bfin.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * U-Boot - serial.c Blackfin Serial Driver
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* Anomaly notes:
- * 05000086 - we don't support autobaud
- * 05000099 - we only use DR bit, so losing others is not a problem
- * 05000100 - we don't use the UART_IIR register
- * 05000215 - we poll the uart (no dma/interrupts)
- * 05000225 - no workaround possible, but this shouldnt cause errors ...
- * 05000230 - we tweak the baud rate calculation slightly
- * 05000231 - we always use 1 stop bit
- * 05000309 - we always enable the uart before we modify it in anyway
- * 05000350 - we always enable the uart regardless of boot mode
- * 05000363 - we don't support break signals, so don't generate one
- */
-
-#include <common.h>
-#include <post.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_UART_CONSOLE
-
-#ifdef CONFIG_DEBUG_SERIAL
-static uart_lsr_t cached_lsr[256];
-static uart_lsr_t cached_rbr[256];
-static size_t cache_count;
-
-/* The LSR is read-to-clear on some parts, so we have to make sure status
- * bits aren't inadvertently lost when doing various tests. This also
- * works around anomaly 05000099 at the same time by keeping a cumulative
- * tally of all the status bits.
- */
-static uart_lsr_t uart_lsr_save;
-static uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- uart_lsr_t lsr = _lsr_read(pUART);
- uart_lsr_save |= (lsr & (OE|PE|FE|BI));
- return lsr | uart_lsr_save;
-}
-/* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(uint32_t uart_base)
-{
- uart_lsr_save = 0;
- _lsr_write(pUART, -1);
-}
-#else
-/* When debugging is disabled, we only care about the DR bit, so if other
- * bits get set/cleared, we don't really care since we don't read them
- * anyways (and thus anomaly 05000099 is irrelevant).
- */
-static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- return _lsr_read(pUART);
-}
-static void uart_lsr_clear(uint32_t uart_base)
-{
- _lsr_write(pUART, -1);
-}
-#endif
-
-static void uart_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- serial_putc('\r');
-
- WATCHDOG_RESET();
-
- /* wait for the hardware fifo to clear up */
- while (!(uart_lsr_read(uart_base) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-
- WATCHDOG_RESET();
-}
-
-static int uart_tstc(uint32_t uart_base)
-{
- WATCHDOG_RESET();
- return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
-}
-
-static int uart_getc(uint32_t uart_base)
-{
- uint16_t uart_rbr_val;
-
- /* wait for data ! */
- while (!uart_tstc(uart_base))
- continue;
-
- /* grab the new byte */
- uart_rbr_val = bfin_read(&pUART->rbr);
-
-#ifdef CONFIG_DEBUG_SERIAL
- /* grab & clear the LSR */
- uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
-
- cached_lsr[cache_count] = uart_lsr_val;
- cached_rbr[cache_count] = uart_rbr_val;
- cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- printf("\n[SERIAL ERROR]\n");
- do {
- --cache_count;
- printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
- cached_rbr[cache_count], cached_lsr[cache_count]);
- } while (cache_count > 0);
- return -1;
- }
-#endif
- uart_lsr_clear(uart_base);
-
- return uart_rbr_val;
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-# define LOOP(x) x
-#else
-# define LOOP(x)
-#endif
-
-#if BFIN_UART_HW_VER < 4
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u16 mcr;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- mcr = bfin_read(&pUART->mcr);
- if (state)
- mcr |= LOOP_ENA | MRTS;
- else
- mcr &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->mcr, mcr);
-}
-)
-
-#else
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u32 control;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- control = bfin_read(&pUART->control);
- if (state)
- control |= LOOP_ENA | MRTS;
- else
- control &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->control, control);
-}
-)
-
-#endif
-
-static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- serial_early_set_baud(uart_base, baud);
-#else
- uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
- - ANOMALY_05000230;
-
- /* Program the divisor to get the baud rate we want */
- serial_set_divisor(uart_base, divisor);
-#endif
-}
-
-static void uart_puts(uint32_t uart_base, const char *s)
-{
- while (*s)
- uart_putc(uart_base, *s++);
-}
-
-#define DECL_BFIN_UART(n) \
-static int uart##n##_init(void) \
-{ \
- const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
- peripheral_request_list(pins, "bfin-uart"); \
- uart_init(MMR_UART(n)); \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
- uart_lsr_clear(MMR_UART(n)); \
- return 0; \
-} \
-\
-static int uart##n##_uninit(void) \
-{ \
- return serial_early_uninit(MMR_UART(n)); \
-} \
-\
-static void uart##n##_setbrg(void) \
-{ \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
-} \
-\
-static int uart##n##_getc(void) \
-{ \
- return uart_getc(MMR_UART(n)); \
-} \
-\
-static int uart##n##_tstc(void) \
-{ \
- return uart_tstc(MMR_UART(n)); \
-} \
-\
-static void uart##n##_putc(const char c) \
-{ \
- uart_putc(MMR_UART(n), c); \
-} \
-\
-static void uart##n##_puts(const char *s) \
-{ \
- uart_puts(MMR_UART(n), s); \
-} \
-\
-LOOP( \
-static void uart##n##_loop(int state) \
-{ \
- uart_loop(MMR_UART(n), state); \
-} \
-) \
-\
-struct serial_device bfin_serial##n##_device = { \
- .name = "bfin_uart"#n, \
- .start = uart##n##_init, \
- .stop = uart##n##_uninit, \
- .setbrg = uart##n##_setbrg, \
- .getc = uart##n##_getc, \
- .tstc = uart##n##_tstc, \
- .putc = uart##n##_putc, \
- .puts = uart##n##_puts, \
- LOOP(.loop = uart##n##_loop) \
-};
-
-#ifdef UART0_RBR
-DECL_BFIN_UART(0)
-#endif
-#ifdef UART1_RBR
-DECL_BFIN_UART(1)
-#endif
-#ifdef UART2_RBR
-DECL_BFIN_UART(2)
-#endif
-#ifdef UART3_RBR
-DECL_BFIN_UART(3)
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if CONFIG_UART_CONSOLE == 0
- return &bfin_serial0_device;
-#elif CONFIG_UART_CONSOLE == 1
- return &bfin_serial1_device;
-#elif CONFIG_UART_CONSOLE == 2
- return &bfin_serial2_device;
-#elif CONFIG_UART_CONSOLE == 3
- return &bfin_serial3_device;
-#endif
-}
-
-void bfin_serial_initialize(void)
-{
-#ifdef UART0_RBR
- serial_register(&bfin_serial0_device);
-#endif
-#ifdef UART1_RBR
- serial_register(&bfin_serial1_device);
-#endif
-#ifdef UART2_RBR
- serial_register(&bfin_serial2_device);
-#endif
-#ifdef UART3_RBR
- serial_register(&bfin_serial3_device);
-#endif
-}
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-inline void uart_early_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- uart_early_putc(uart_base, '\r');
-
- /* wait for the hardware fifo to clear up */
- while (!(_lsr_read(pUART) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-}
-
-void uart_early_puts(const char *s)
-{
- while (*s)
- uart_early_putc(UART_BASE, *s++);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_set_baud(uint32_t baud)
-{
- serial_early_set_baud(UART_BASE, baud);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_init(void)
-{
- serial_early_init(UART_BASE);
-}
-#endif
-
-#elif defined(CONFIG_UART_MEM)
-
-char serial_logbuf[CONFIG_UART_MEM];
-char *serial_logbuf_head = serial_logbuf;
-
-int serial_mem_init(void)
-{
- serial_logbuf_head = serial_logbuf;
- return 0;
-}
-
-void serial_mem_setbrg(void)
-{
-}
-
-int serial_mem_tstc(void)
-{
- return 0;
-}
-
-int serial_mem_getc(void)
-{
- return 0;
-}
-
-void serial_mem_putc(const char c)
-{
- *serial_logbuf_head = c;
- if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
- serial_logbuf_head = serial_logbuf;
-}
-
-void serial_mem_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-struct serial_device bfin_serial_mem_device = {
- .name = "bfin_uart_mem",
- .start = serial_mem_init,
- .setbrg = serial_mem_setbrg,
- .getc = serial_mem_getc,
- .tstc = serial_mem_tstc,
- .putc = serial_mem_putc,
- .puts = serial_mem_puts,
-};
-
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &bfin_serial_mem_device;
-}
-
-void bfin_serial_initialize(void)
-{
- serial_register(&bfin_serial_mem_device);
-}
-#endif /* CONFIG_UART_MEM */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fa9a1d2..c090562 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,8 +19,6 @@
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
-obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
-obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
deleted file mode 100644
index 9a6fc78..0000000
--- a/drivers/spi/bfin_spi.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Driver for Blackfin On-Chip SPI device
- *
- * Copyright (c) 2005-2010 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*#define DEBUG*/
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi.h>
-
-struct bfin_spi_slave {
- struct spi_slave slave;
- void *mmr_base;
- u16 ctl, baud, flg;
-};
-
-#define MAKE_SPI_FUNC(mmr, off) \
-static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
-static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
-MAKE_SPI_FUNC(SPI_CTL, 0x00)
-MAKE_SPI_FUNC(SPI_FLG, 0x04)
-MAKE_SPI_FUNC(SPI_STAT, 0x08)
-MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
-MAKE_SPI_FUNC(SPI_RDBR, 0x10)
-MAKE_SPI_FUNC(SPI_BAUD, 0x14)
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (is_gpio_cs(cs))
- return gpio_is_valid(gpio_cs(cs));
- else
- return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, bss->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
- } else {
- write_SPI_FLG(bss,
- (read_SPI_FLG(bss) &
- ~((!bss->flg << 8) << slave->cs)) |
- (1 << slave->cs));
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
- }
-
- SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, !bss->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
- } else {
- u16 flg;
-
- /* make sure we force the cs to deassert rather than let the
- * pin float back up. otherwise, exact timings may not be
- * met some of the time leading to random behavior (ugh).
- */
- flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
- write_SPI_FLG(bss, flg);
- SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
-
- flg &= ~(1 << slave->cs);
- write_SPI_FLG(bss, flg);
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
- }
-
- SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
-
-#define SPI_PINS(n) \
- [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_CTL
- SPI_PINS(0),
-#endif
-#ifdef SPI1_CTL
- SPI_PINS(1),
-#endif
-#ifdef SPI2_CTL
- SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
- [n] = { \
- P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
- P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
- P_SPI##n##_SSEL7, \
- }
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_CTL
- SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_CTL
- SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_CTL
- SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong clk;
- u32 baud;
-
- clk = get_spi_clk();
- /* baud should be rounded up */
- baud = DIV_ROUND_UP(clk, 2 * hz);
- if (baud < 2)
- baud = 2;
- else if (baud > (u16)-1)
- baud = -1;
- bss->baud = baud;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct bfin_spi_slave *bss;
- u32 mmr_base;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- switch (bus) {
-#ifdef SPI0_CTL
- case 0:
- mmr_base = SPI0_CTL; break;
-#endif
-#ifdef SPI1_CTL
- case 1:
- mmr_base = SPI1_CTL; break;
-#endif
-#ifdef SPI2_CTL
- case 2:
- mmr_base = SPI2_CTL; break;
-#endif
- default:
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
-
- bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
- if (!bss)
- return NULL;
-
- bss->mmr_base = (void *)mmr_base;
- bss->ctl = SPE | MSTR | TDBR_CORE;
- if (mode & SPI_CPHA) bss->ctl |= CPHA;
- if (mode & SPI_CPOL) bss->ctl |= CPOL;
- if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
- bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(&bss->slave, max_hz);
-
- debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
- bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
-
- return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_request(cs, "bfin-spi");
- gpio_direction_output(cs, !bss->flg);
- pins[slave->bus][0] = P_DONTCARE;
- } else
- pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
- peripheral_request_list(pins[slave->bus], "bfin-spi");
-
- write_SPI_CTL(bss, bss->ctl);
- write_SPI_BAUD(bss, bss->baud);
- SSYNC();
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- peripheral_free_list(pins[slave->bus]);
- if (is_gpio_cs(slave->cs))
- gpio_free(gpio_cs(slave->cs));
-
- write_SPI_CTL(bss, 0);
- SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
- uint bytes)
-{
- /* discard invalid data and clear RXS */
- read_SPI_RDBR(bss);
- /* todo: take advantage of hardware fifos */
- while (bytes--) {
- u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
- debug("%s: tx:%x ", __func__, value);
- write_SPI_TDBR(bss, value);
- SSYNC();
- while ((read_SPI_STAT(bss) & TXS))
- if (ctrlc())
- return -1;
- while (!(read_SPI_STAT(bss) & SPIF))
- if (ctrlc())
- return -1;
- while (!(read_SPI_STAT(bss) & RXS))
- if (ctrlc())
- return -1;
- value = read_SPI_RDBR(bss);
- if (rx)
- *rx++ = value;
- debug("rx:%x\n", value);
- }
-
- return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- const u8 *tx = dout;
- u8 *rx = din;
- uint bytes = bitlen / 8;
- int ret = 0;
-
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return ret;
-}
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
deleted file mode 100644
index 9a27b78..0000000
--- a/drivers/spi/bfin_spi6xx.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Analog Devices SPI3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi6xx.h>
-
-struct bfin_spi_slave {
- struct spi_slave slave;
- u32 control, clock;
- struct bfin_spi_regs *regs;
- int cs_pol;
-};
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (is_gpio_cs(cs))
- return gpio_is_valid(gpio_cs(cs));
- else
- return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, bss->cs_pol);
- } else {
- u32 ssel;
- ssel = bfin_read32(&bss->regs->ssel);
- ssel |= 1 << slave->cs;
- if (bss->cs_pol)
- ssel |= BIT(8) << slave->cs;
- else
- ssel &= ~(BIT(8) << slave->cs);
- bfin_write32(&bss->regs->ssel, ssel);
- }
-
- SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, !bss->cs_pol);
- } else {
- u32 ssel;
- ssel = bfin_read32(&bss->regs->ssel);
- if (bss->cs_pol)
- ssel &= ~(BIT(8) << slave->cs);
- else
- ssel |= BIT(8) << slave->cs;
- /* deassert cs */
- bfin_write32(&bss->regs->ssel, ssel);
- SSYNC();
- /* disable cs */
- ssel &= ~(1 << slave->cs);
- bfin_write32(&bss->regs->ssel, ssel);
- }
-
- SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#define SPI_PINS(n) \
- { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_REGBASE
- [0] = SPI_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
- [1] = SPI_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
- [2] = SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
- { \
- P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
- P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
- P_SPI##n##_SSEL7, \
- }
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_REGBASE
- [0] = SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
- [1] = SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
- [2] = SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong clk;
- u32 clock;
-
- clk = get_spi_clk();
- clock = clk / hz;
- if (clock)
- clock--;
- bss->clock = clock;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct bfin_spi_slave *bss;
- u32 reg_base;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- switch (bus) {
-#ifdef SPI0_REGBASE
- case 0:
- reg_base = SPI0_REGBASE;
- break;
-#endif
-#ifdef SPI1_REGBASE
- case 1:
- reg_base = SPI1_REGBASE;
- break;
-#endif
-#ifdef SPI2_REGBASE
- case 2:
- reg_base = SPI2_REGBASE;
- break;
-#endif
- default:
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
-
- bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
- if (!bss)
- return NULL;
-
- bss->regs = (struct bfin_spi_regs *)reg_base;
- bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
- if (mode & SPI_CPHA)
- bss->control |= SPI_CTL_CPHA;
- if (mode & SPI_CPOL)
- bss->control |= SPI_CTL_CPOL;
- if (mode & SPI_LSB_FIRST)
- bss->control |= SPI_CTL_LSBF;
- bss->control &= ~SPI_CTL_ASSEL;
- bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(&bss->slave, max_hz);
-
- return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_request(cs, "bfin-spi");
- gpio_direction_output(cs, !bss->cs_pol);
- pins[slave->bus][0] = P_DONTCARE;
- } else
- pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
- peripheral_request_list(pins[slave->bus], "bfin-spi");
-
- bfin_write32(&bss->regs->control, bss->control);
- bfin_write32(&bss->regs->clock, bss->clock);
- bfin_write32(&bss->regs->delay, 0x0);
- bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN);
- bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI);
- SSYNC();
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- peripheral_free_list(pins[slave->bus]);
- if (is_gpio_cs(slave->cs))
- gpio_free(gpio_cs(slave->cs));
-
- bfin_write32(&bss->regs->rx_control, 0x0);
- bfin_write32(&bss->regs->tx_control, 0x0);
- bfin_write32(&bss->regs->control, 0x0);
- SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
- uint bytes)
-{
- /* discard invalid rx data and empty rfifo */
- while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE))
- bfin_read32(&bss->regs->rfifo);
-
- while (bytes--) {
- u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
- debug("%s: tx:%x ", __func__, value);
- bfin_write32(&bss->regs->tfifo, value);
- SSYNC();
- while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE)
- if (ctrlc())
- return -1;
- value = bfin_read32(&bss->regs->rfifo);
- if (rx)
- *rx++ = value;
- debug("rx:%x\n", value);
- }
-
- return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- const u8 *tx = dout;
- u8 *rx = din;
- uint bytes = bitlen / 8;
- int ret = 0;
-
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return ret;
-}
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index 84cb21b..79e118e 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -116,12 +116,9 @@
{
return dev_get_drvdata(dev);
}
-#endif
/*-------------------------------------------------------------------------*/
-#ifndef __UBOOT__
-#ifndef CONFIG_BLACKFIN
static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
{
void __iomem *addr = phy->io_priv;
@@ -203,10 +200,6 @@
return ret;
}
-#else
-#define musb_ulpi_read NULL
-#define musb_ulpi_write NULL
-#endif
static struct usb_phy_io_ops musb_ulpi_access = {
.read = musb_ulpi_read,
@@ -216,7 +209,7 @@
/*-------------------------------------------------------------------------*/
-#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
+#if !defined(CONFIG_USB_MUSB_TUSB6010)
/*
* Load an endpoint's FIFO
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index 4ae0ae2..6394bb0 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -152,8 +152,7 @@
*/
#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
- || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
- || defined(CONFIG_ARCH_OMAP4)
+ || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_ARCH_OMAP4)
/* REVISIT indexed access seemed to
* misbehave (on DaVinci) for at least peripheral IN ...
*/
@@ -455,37 +454,9 @@
return container_of(g, struct musb, g);
}
-#ifdef CONFIG_BLACKFIN
static inline int musb_read_fifosize(struct musb *musb,
struct musb_hw_ep *hw_ep, u8 epnum)
{
- musb->nr_endpoints++;
- musb->epmask |= (1 << epnum);
-
- if (epnum < 5) {
- hw_ep->max_packet_sz_tx = 128;
- hw_ep->max_packet_sz_rx = 128;
- } else {
- hw_ep->max_packet_sz_tx = 1024;
- hw_ep->max_packet_sz_rx = 1024;
- }
- hw_ep->is_shared_fifo = false;
-
- return 0;
-}
-
-static inline void musb_configure_ep0(struct musb *musb)
-{
- musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].is_shared_fifo = true;
-}
-
-#else
-
-static inline int musb_read_fifosize(struct musb *musb,
- struct musb_hw_ep *hw_ep, u8 epnum)
-{
void *mbase = musb->mregs;
u8 reg = 0;
@@ -519,8 +490,6 @@
musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
musb->endpoints[0].is_shared_fifo = true;
}
-#endif /* CONFIG_BLACKFIN */
-
/***************************** Glue it together *****************************/
diff --git a/drivers/usb/musb-new/musb_dma.h b/drivers/usb/musb-new/musb_dma.h
index 30e39f5..c94abb8 100644
--- a/drivers/usb/musb-new/musb_dma.h
+++ b/drivers/usb/musb-new/musb_dma.h
@@ -56,17 +56,6 @@
#define tusb_dma_omap() 0
#endif
-/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- * Only allow DMA mode 1 to be used when the USB will actually generate the
- * interrupts we expect.
- */
-#ifdef CONFIG_BLACKFIN
-# undef USE_MODE1
-# if !ANOMALY_05000456
-# define USE_MODE1
-# endif
-#endif
-
/*
* DMA channel status ... updated by the dma controller driver whenever that
* status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index ea8efb3..7668212 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -23,8 +23,8 @@
#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
&& !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
- && !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN) \
- && !defined(CONFIG_MIPS) && !defined(CONFIG_M68K)
+ && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
+ && !defined(CONFIG_M68K)
static inline void readsl(const void __iomem *addr, void *buf, int len)
{ insl((unsigned long)addr, buf, len); }
static inline void readsw(const void __iomem *addr, void *buf, int len)
@@ -41,8 +41,6 @@
#endif
-#ifndef CONFIG_BLACKFIN
-
/* NOTE: these offsets are all in bytes */
static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
@@ -101,26 +99,4 @@
#endif /* CONFIG_USB_MUSB_TUSB6010 */
-#else
-
-static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- { return (u8) (bfin_read16(addr + offset)); }
-
-static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- { return bfin_read16(addr + offset); }
-
-static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- { return (u32) (bfin_read16(addr + offset)); }
-
-static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- { bfin_write16(addr + offset, (u16) data); }
-
-static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- { bfin_write16(addr + offset, data); }
-
-static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
- { bfin_write16(addr + offset, (u16) data); }
-
-#endif /* CONFIG_BLACKFIN */
-
#endif
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 0f18dd7..a3cc38e 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -190,8 +190,6 @@
#define MUSB_HUBADDR_MULTI_TT 0x80
-#ifndef CONFIG_BLACKFIN
-
/* SUNXI has different reg addresses, but identical r/w functions */
#ifndef CONFIG_ARCH_SUNXI
@@ -526,193 +524,4 @@
return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
}
-#else /* CONFIG_BLACKFIN */
-
-#define USB_BASE USB_FADDR
-#define USB_OFFSET(reg) (reg - USB_BASE)
-
-/*
- * Common USB registers
- */
-#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
-#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
-#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
-#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
-#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
-#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
-#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
-#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
-#define MUSB_FRAME USB_OFFSET(USB_FRAME)
-#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
-#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
-
-/* Get offset for a given FIFO from musb->mregs */
-#define MUSB_FIFO_OFFSET(epnum) \
- (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
-
-/*
- * Additional Control Registers
- */
-
-#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
-
-#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
-#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
-#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
-#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
-#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
-
-/* Offsets to endpoint registers */
-#define MUSB_TXMAXP 0x00
-#define MUSB_TXCSR 0x04
-#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
-#define MUSB_RXMAXP 0x08
-#define MUSB_RXCSR 0x0C
-#define MUSB_RXCOUNT 0x10
-#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
-#define MUSB_TXTYPE 0x14
-#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
-#define MUSB_TXINTERVAL 0x18
-#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
-#define MUSB_RXTYPE 0x1C
-#define MUSB_RXINTERVAL 0x20
-#define MUSB_TXCOUNT 0x28
-
-/* Offsets to endpoint registers in indexed model (using INDEX register) */
-#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
- (0x40 + (_offset))
-
-/* Offsets to endpoint registers in flat models */
-#define MUSB_FLAT_OFFSET(_epnum, _offset) \
- (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-
-/* Not implemented - HW has separate Tx/Rx FIFO */
-#define MUSB_TXCSR_MODE 0x0000
-
-static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
-{
-}
-
-static inline u8 musb_read_txfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_txfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_configdata(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_hwvers(void __iomem *mbase)
-{
- /*
- * This register is invisible on Blackfin, actually the MUSB
- * RTL version of Blackfin is 1.9, so just harcode its value.
- */
- return MUSB_HWVERS_1900;
-}
-
-static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
-{
- return NULL;
-}
-
-static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
- u8 qh_addr_req)
-{
-}
-
-static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
- u8 qh_h_addr_reg)
-{
-}
-
-static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
- u8 qh_h_port_reg)
-{
-}
-
-static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
- u8 qh_h_port_reg)
-{
-}
-
-static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-#endif /* CONFIG_BLACKFIN */
-
#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index bd2b7c5..9554edd 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -7,7 +7,6 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
-obj-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
obj-$(CONFIG_USB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
obj-$(CONFIG_USB_DA8XX) += da8xx.o
diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c
deleted file mode 100644
index 65fff88..0000000
--- a/drivers/usb/musb/blackfin_usb.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-#include <usb.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/usb.h>
-
-#include "musb_core.h"
-
-#ifndef CONFIG_USB_BLACKFIN_CLKIN
-#define CONFIG_USB_BLACKFIN_CLKIN 24
-#endif
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
- .regs = (struct musb_regs *)USB_FADDR,
- .timeout = 0x3FFFFFF,
- .musb_speed = 0,
-};
-
-/*
- * This function read or write data to endpoint fifo
- * Blackfin use DMA polling method to avoid buffer alignment issues
- *
- * ep - Endpoint number
- * length - Number of bytes to write to FIFO
- * fifo_data - Pointer to data buffer to be read/write
- * is_write - Flag for read or write
- */
-void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
-{
- struct bfin_musb_dma_regs *regs;
- u32 val = (u32)fifo_data;
-
- blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
-
- regs = (void *)USB_DMA_INTERRUPT;
- regs += ep;
-
- /* Setup DMA address register */
- bfin_write16(®s->addr_low, val);
- SSYNC();
-
- bfin_write16(®s->addr_high, val >> 16);
- SSYNC();
-
- /* Setup DMA count register */
- bfin_write16(®s->count_low, length);
- bfin_write16(®s->count_high, 0);
- SSYNC();
-
- /* Enable the DMA */
- val = (ep << 4) | DMA_ENA | INT_ENA;
- if (is_write)
- val |= DIRECTION;
- bfin_write16(®s->control, val);
- SSYNC();
-
- /* Wait for compelete */
- while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
- continue;
-
- /* acknowledge dma interrupt */
- bfin_write_USB_DMA_INTERRUPT(1 << ep);
- SSYNC();
-
- /* Reset DMA */
- bfin_write16(®s->control, 0);
- SSYNC();
-}
-
-void write_fifo(u8 ep, u32 length, void *fifo_data)
-{
- rw_fifo(ep, length, fifo_data, 1);
-}
-
-void read_fifo(u8 ep, u32 length, void *fifo_data)
-{
- rw_fifo(ep, length, fifo_data, 0);
-}
-
-
-/*
- * CPU and board-specific MUSB initializations. Aliased function
- * signals caller to move on.
- */
-static void __def_musb_init(void)
-{
-}
-void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
-
-static void bfin_anomaly_init(void)
-{
- u32 revid;
-
- if (!ANOMALY_05000346 && !ANOMALY_05000347)
- return;
-
- revid = bfin_revid();
-
-#ifdef __ADSPBF54x__
- if (revid > 0)
- return;
-#endif
-#ifdef __ADSPBF52x__
- if (ANOMALY_BF526 && revid > 0)
- return;
- if (ANOMALY_BF527 && revid > 1)
- return;
-#endif
-
- if (ANOMALY_05000346) {
- bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
- SSYNC();
- }
-
- if (ANOMALY_05000347) {
- bfin_write_USB_APHY_CNTRL(0x0);
- SSYNC();
- }
-}
-
-int musb_platform_init(void)
-{
- /* board specific initialization */
- board_musb_init();
-
- bfin_anomaly_init();
-
- /* Configure PLL oscillator register */
- bfin_write_USB_PLLOSC_CTRL(0x3080 |
- ((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
- SSYNC();
-
- bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
- SSYNC();
-
- bfin_write_USB_EP_NI0_RXMAXP(64);
- SSYNC();
-
- bfin_write_USB_EP_NI0_TXMAXP(64);
- SSYNC();
-
- /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
- bfin_write_USB_GLOBINTR(0x7);
- SSYNC();
-
- bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
- EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
- EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
- EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
- EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
- SSYNC();
-
- return 0;
-}
-
-/*
- * This function performs Blackfin platform specific deinitialization for usb.
-*/
-void musb_platform_deinit(void)
-{
-}
diff --git a/drivers/usb/musb/blackfin_usb.h b/drivers/usb/musb/blackfin_usb.h
deleted file mode 100644
index de994bf..0000000
--- a/drivers/usb/musb/blackfin_usb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_USB_H__
-#define __BLACKFIN_USB_H__
-
-#include <linux/types.h>
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-
-#define musb_regs musb_regs
-struct musb_regs {
- /* common registers */
- ureg(faddr)
- ureg(power)
- ureg(intrtx)
- ureg(intrrx)
- ureg(intrtxe)
- ureg(intrrxe)
- ureg(intrusb)
- ureg(intrusbe)
- ureg(frame)
- ureg(index)
- ureg(testmode)
- ureg(globintr)
- ureg(global_ctl)
- u32 reserved0[3];
- /* indexed registers */
- ureg(txmaxp)
- ureg(txcsr)
- ureg(rxmaxp)
- ureg(rxcsr)
- ureg(rxcount)
- ureg(txtype)
- ureg(txinterval)
- ureg(rxtype)
- ureg(rxinterval)
- u32 reserved1;
- ureg(txcount)
- u32 reserved2[5];
- /* fifo */
- u16 fifox[32];
- /* OTG, dynamic FIFO, version & vendor registers */
- u32 reserved3[16];
- ureg(devctl)
- ureg(vbus_irq)
- ureg(vbus_mask)
- u32 reserved4[15];
- ureg(linkinfo)
- ureg(vplen)
- ureg(hseof1)
- ureg(fseof1)
- ureg(lseof1)
- u32 reserved5[41];
- /* target address registers */
- struct musb_tar_regs {
- ureg(txmaxp)
- ureg(txcsr)
- ureg(rxmaxp)
- ureg(rxcsr)
- ureg(rxcount)
- ureg(txtype)
- ureg(txinternal)
- ureg(rxtype)
- ureg(rxinternal)
- u32 reserved6;
- ureg(txcount)
- u32 reserved7[5];
- } tar[8];
-} __attribute__((packed));
-
-struct bfin_musb_dma_regs {
- ureg(interrupt);
- ureg(control);
- ureg(addr_low);
- ureg(addr_high);
- ureg(count_low);
- ureg(count_high);
- u32 reserved0[2];
-};
-
-#undef ureg
-
-/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
-#define MUSB_BULK_EP 5
-
-/* Blackfin FIFO's are static */
-#define MUSB_NO_DYNAMIC_FIFO
-
-/* No HUB support :( */
-#define MUSB_NO_MULTIPOINT
-
-#endif
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index dc863bd..ae352ce 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -13,10 +13,6 @@
#include <usb_defs.h>
#include <asm/io.h>
-#ifdef CONFIG_USB_BLACKFIN
-# include "blackfin_usb.h"
-#endif
-
#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
/* EP0 */
@@ -336,36 +332,13 @@
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
-#if defined(CONFIG_USB_BLACKFIN)
-/* Every USB register is accessed as a 16-bit even if the value itself
- * is only 8-bits in size. Fun stuff.
- */
-# undef readb
-# define readb(addr) (u8)bfin_read16(addr)
-# undef writeb
-# define writeb(b, addr) bfin_write16(addr, b)
-# undef MUSB_TXCSR_MODE /* not supported */
-# define MUSB_TXCSR_MODE 0
-/*
- * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
- * However, it has no ULPI support - so there are no registers at all.
- * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
- */
static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
{
- return 0;
-}
-static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
-{}
-#else
-static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
-{
return readb(&musbr->ulpi_busctl);
}
static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
{
writeb(val, &musbr->ulpi_busctl);
}
-#endif
#endif /* __MUSB_HDRC_DEFS_H__ */
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 4947936..fee0848 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -913,11 +913,6 @@
nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
(len-txlen) : dev->epmaxpacketout[ep];
-#ifdef CONFIG_USB_BLACKFIN
- /* Set the transfer data size */
- writew(nextlen, &musbr->txcount);
-#endif
-
/* Write the data to the FIFO */
write_fifo(MUSB_BULK_EP, nextlen,
(void *)(((u8 *)buffer) + txlen));