| commit | 1f370d31d843f24321778e434af28236571f6b28 | [log] [tgz] |
|---|---|---|
| author | Michael Walle <michael@walle.cc> | Mon May 30 23:02:07 2022 +0200 |
| committer | Peng Fan <peng.fan@nxp.com> | Mon Jun 20 15:52:45 2022 +0800 |
| tree | 4fd174441b93ae79f561109b68f714bfa7d6227d | |
| parent | 98fbb5654f3abf1f50fca1c750beccde31e1a7ac [diff] |
board: sl28: set CPO value With a 8GiB memory board, it seems that the "very unlikely event" of a DDR initialization with non-optimal values are not really that unlikely. It happens in about every other reboot. As described in erratum A-009942, preset the DEBUG_28 register with an optimal value. The value iself depends on the memory configuration of the board, but the used value seems to work well for all variants. Signed-off-by: Michael Walle <michael@walle.cc>