* Patch by Yuli Barcohen, 13 Jul 2004:
Allow clock setting on MPC866/MPC885 series chips according to
environment variable `cpuclk'
* Patch by Yuli Barcohen, 20 Apr 2004:
Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 13e6c35..f807546 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -41,7 +41,14 @@
#define FEC_ENET
#endif /* CONFIG_FEC_ENET */
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#ifdef CONFIG_MPC852T
+#define CFG_8xx_CPUCLK_MAX 50000000
+#else
+#define CFG_8xx_CPUCLK_MAX 120000000
+#endif /* CONFIG_MPC852T */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
@@ -89,6 +96,15 @@
#define CFG_MAMR 0x00802114
+/*
+ * 2048 SDRAM rows
+ * 1000 factor s -> ms
+ * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
+
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 1aaca14..30d3d21 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -44,25 +44,25 @@
/*
* 10 MHz - PLL input clock
*/
-#define CFG_866_OSCCLK 10000000
+#define CFG_8xx_OSCCLK 10000000
/*
* 50 MHz - default CPU clock
*/
-#define CFG_866_CPUCLK_DEFAULT 50000000
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
/*
* 15 MHz - CPU minimum clock
*/
-#define CFG_866_CPUCLK_MIN 15000000
+#define CFG_8xx_CPUCLK_MIN 15000000
/*
* 133 MHz - CPU maximum clock
*/
-#define CFG_866_CPUCLK_MAX 133000000
+#define CFG_8xx_CPUCLK_MAX 133000000
#define CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN CFG_866_OSCCLK
+#define CFG_8XX_XIN CFG_8xx_OSCCLK
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
@@ -307,7 +307,7 @@
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
-#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
* Memory Periodic Timer Prescaler
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 713cc40..2328118 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -36,10 +36,10 @@
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
-#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
-#define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
-#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
-#define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
+#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
+#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
/* (it will be used if there is no */
/* 'cpuclk' variable with valid value) */
@@ -404,12 +404,12 @@
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
-#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
* Memory Periodic Timer Prescaler
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
- * (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
+ * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
*/
#define CFG_MAMR_PTA 39