drivers: clk: adi: Add in SC5XX-family clock driver
This adds support for the SC5XX clock trees which are required for reading
clock speeds on the SoCs. This is largely a port of the same support for
Linux, which has not yet been submitted upstream.
Co-developed-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c
new file mode 100644
index 0000000..dcadcaf
--- /dev/null
+++ b/drivers/clk/adi/clk-shared.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include "clk.h"
+
+static ulong adi_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong adi_set_rate(struct clk *clk, ulong rate)
+{
+ //Not yet implemented
+ return 0;
+}
+
+static int adi_enable(struct clk *clk)
+{
+ //Not yet implemented
+ return 0;
+}
+
+static int adi_disable(struct clk *clk)
+{
+ //Not yet implemented
+ return 0;
+}
+
+const struct clk_ops adi_clk_ops = {
+ .set_rate = adi_set_rate,
+ .get_rate = adi_get_rate,
+ .enable = adi_enable,
+ .disable = adi_disable,
+};
+