tree fef55fc0b6b9f9b5e745c7e37de9d1293b28adc3
parent 4599bea9ef3856fff9b98bbfcbc487269d8e275b
author Pali Rohár <pali@kernel.org> 1632517158 +0200
committer Stefan Roese <sr@denx.de> 1633674832 +0200

arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration

Enabling Common Clock Configuration bit in PCIe Root Port Link Control
Register should not be done unconditionally. It is enabled by operating
system as part of ASPM. Also after enabling Common Clock Configuration it
is required to do more work, like retraining link. Some cards may be broken
due to this incomplete Common Clock Configuration and some cards are broken
and do not support ASPM at all.

Remove this incomplete code for Common Clock Configuration. It really
should not be done in SerDes code as it is not related to SerDes, but to
PCIe subsystem.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>