| commit | 1ffdcefca11825c7e248107fc5bc76e245761378 | [log] [tgz] |
|---|---|---|
| author | Pierre-Clément Tosi <ptosi@google.com> | Fri Aug 27 18:04:10 2021 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Thu Sep 23 08:55:06 2021 -0400 |
| tree | 6fcc08d95f57b7523b77b701e892a6e2ec86b12f | |
| parent | eba9a0ba9cebf6b6dbf044eb53f3aaf92a366767 [diff] |
armv8/cache.S: Triple with single instruction Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size. Fix the comment as the tripled cache level is placed in x12, not x0. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>