board: cssi: Add new board MCR3000_2G
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.
That CPU board is shared with another equipment that will
be added in a later patch.
That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
new file mode 100644
index 0000000..adda0f3
--- /dev/null
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CMPC885 Device Tree Source
+ *
+ * Copyright 2020 CS Group
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "CMPC885";
+ compatible = "fsl, cmpc885", "fsl,mod885";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ stdout-path = &SERIAL;
+ };
+
+ WDT: watchdog@0 {
+ device_type = "watchdog";
+ compatible = "fsl,pq1-wdt";
+ };
+
+ SERIAL: serial {
+ compatible = "fsl,pq1-smc";
+ };
+
+ FEC1: fec@0 {
+ compatible = "fsl,pq1-fec1";
+ };
+
+ FEC2: fec@1 {
+ compatible = "fsl,pq1-fec2";
+ };
+
+ soc: immr@ff000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device-type = "soc";
+ compatible = "simple-bus";
+ ranges = <0 0xff000000 0x4000>;
+ reg = <0xff000000 0x00000200>;
+
+ CPM1_PIO_B: gpio-controller@ab8 {
+ #gpio-cells = <2>;
+ compatible = "fsl,cpm1-pario-bank-b";
+ reg = <0xab8 0x10>;
+ gpio-controller;
+ };
+
+ CPM1_PIO_D: gpio-controller@970 {
+ #gpio-cells = <2>;
+ compatible = "fsl,cpm1-pario-bank-d";
+ reg = <0x970 0x10>;
+ gpio-controller;
+ };
+
+ CPM1_PIO_A: gpio-controller@950 {
+ #gpio-cells = <2>;
+ compatible = "fsl,cpm1-pario-bank-a";
+ reg = <0x950 0x10>;
+ gpio-controller;
+ };
+
+ CPM1_PIO_C: gpio-controller@960 {
+ #gpio-cells = <2>;
+ compatible = "fsl,cpm1-pario-bank-c";
+ reg = <0x960 0x10>;
+ gpio-controller;
+ };
+
+ CPM1_PIO_E: gpio-controller@ac8 {
+ #gpio-cells = <2>;
+ compatible = "fsl,cpm1-pario-bank-e";
+ reg = <0xac8 0x18>;
+ gpio-controller;
+ };
+
+ spi: spi@aa0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ compatible = "fsl,mpc8xx-spi";
+ gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
+
+ eeprom@0 {
+ cell-index = <1>;
+ };
+ };
+ };
+};