tree 5aba573d6bbdf5dc1a874ee4e9e8d8228ffaf965
parent b52fd3be26fce46333b55d4ab043b05d189c4884
author Marek Vasut <marek.vasut+renesas@mailbox.org> 1728150302 +0200
committer Tom Rini <trini@konsulko.com> 1728155722 -0600

clk: renesas: rcar-gen3: Fix SSCG caching replacement with MDSEL/PE caching

The SSCG is active with MDSEL[12] is not set. Previous commit
99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching
with MDSEL/PE caching") inverted the conditional assignment
of priv->sscg = !(cpg_mode & BIT(12)) during conversion from
(priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Invert the assignment back to the correct state.

This fixes R8A77980, R8A77990, R8A77995 and R8A774C0.

Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>