arm: am57xx: cl-som-am57x: add ETH support
Add MAC support.
Use PHY, connected to RGMII1 as a default Eth adapter,
by appropriate setting of 'cpsw_data.active_slave'.
'cpsw_phy' env variable can override this setting.
Set the MAC addresses in the U-Boot environment.
The addresses are retrieved from the on-board EEPROM or from the SOC's
MAC fuses.
Set the following PHYs RGMII clock delays:
- Enable RX delay
- Disable TX delay
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
[uri.mashiach@compulab.co.il: add RGMII clock delays]
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c
index 625cbc1..5b71975 100644
--- a/board/compulab/cl-som-am57x/mux.c
+++ b/board/compulab/cl-som-am57x/mux.c
@@ -83,6 +83,28 @@
{USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */
};
+/* Ethernet */
+static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
+ /* MDIO bus */
+ {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */
+ {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */
+ /* EMAC Slave 1 at addr 0x1 - Default interface */
+ {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */
+ {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */
+ {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */
+ {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */
+ {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */
+ {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */
+ {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */
+ {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */
+ {VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */
+ {VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */
+ {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */
+ {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */
+ /* Eth PHY1 reset GPIOs*/
+ {VIN1B_CLK1, (IDIS | PDIS | PTD | M14)}, /* VIN1B_CLK1.GPIO2_31 */
+};
+
#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
mux_array, ARRAY_SIZE(mux_array))
@@ -97,4 +119,5 @@
SET_MUX(cl_som_am57x_padconf_i2c_gpio);
SET_MUX(cl_som_am57x_padconf_emmc);
SET_MUX(cl_som_am57x_padconf_usb);
+ SET_MUX(cl_som_am57x_padconf_ethernet);
}