Support for XUPV2P board
Reset support
BSP autoconfig support
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 4dc2afc..f4a8a1f 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -31,27 +31,31 @@
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
-#define CONFIG_SERIAL_BASE CONFIG_XILINX_UARTLITE_0_BASEADDR
-#define CONFIG_BAUDRATE CONFIG_XILINX_UARTLITE_0_BAUDRATE
+#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
+#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* setting reset address */
#define CFG_RESET_ADDRESS TEXT_BASE
+/* ethernet */
+#define CONFIG_EMACLITE 1
+#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+
/* gpio */
#define CFG_GPIO_0 1
-#define CFG_GPIO_0_ADDR CONFIG_XILINX_GPIO_0_BASEADDR
+#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
/* interrupt controller */
#define CFG_INTC_0 1
-#define CFG_INTC_0_ADDR CONFIG_XILINX_INTC_0_BASEADDR
-#define CFG_INTC_0_NUM CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS
+#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
+#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
/* timer */
#define CFG_TIMER_0 1
-#define CFG_TIMER_0_ADDR CONFIG_XILINX_TIMER_0_BASEADDR
-#define CFG_TIMER_0_IRQ CONFIG_XILINX_TIMER_0_IRQ
-#define FREQUENCE 66666666
+#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
+#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
+#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
/*
@@ -62,6 +66,7 @@
*
* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
+ * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
*
* 0x1000_0000 CFG_SDRAM_BASE
* FREE
@@ -71,16 +76,18 @@
* FREE
*
* STACK
+ * 0x13F7_F000 CFG_MALLOC_BASE
+ * MALLOC_AREA 256kB Alloc
* 0x11FB_F000 CFG_MONITOR_BASE
- * MONITOR_CODE
+ * MONITOR_CODE 256kB Env
* 0x13FF_F000 CFG_GBL_DATA_OFFSET
- * GLOBAL_DATA
+ * GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
/* ddr sdram - main memory */
-#define CFG_SDRAM_BASE CONFIG_XILINX_ERAM_START
-#define CFG_SDRAM_SIZE CONFIG_XILINX_ERAM_SIZE
+#define CFG_SDRAM_BASE XILINX_RAM_START
+#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
@@ -92,7 +99,9 @@
#define SIZE 0x40000
#define CFG_MONITOR_LEN SIZE
#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
+#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_MALLOC_LEN SIZE
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
/* stack */
#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
@@ -101,8 +110,8 @@
#define FLASH
#ifdef FLASH
- #define CFG_FLASH_BASE CONFIG_XILINX_FLASH_START
- #define CFG_FLASH_SIZE CONFIG_XILINX_FLASH_SIZE
+ #define CFG_FLASH_BASE XILINX_FLASH_START
+ #define CFG_FLASH_SIZE XILINX_FLASH_SIZE
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
@@ -214,8 +223,8 @@
/* system ace */
/*#define CONFIG_SYSTEMACE
#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE 0xCF000000
-#define CFG_SYSTEMACE_WIDTH 8
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
#define CONFIG_DOS_PARTITION
*/
#endif /* __CONFIG_H */