tree f12fdfb7245ee816c55f69124e04a261ee3e9578
parent 3ccbb4be828cf54b3d79385ab106edd329ecb4cf
author Vladimir Oltean <vladimir.oltean@nxp.com> 1588803112 +0200
committer Tom Rini <trini@konsulko.com> 1588863900 -0400

phy: atheros: Clarify the intention of ar8021_config

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>