Merge tag 'u-boot-imx-next-20250321' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25267
- Allow the registration and enablement of the i.MX UART clocks via DM,
without the need of manually calling init_uart_clk().
- Remove duplicated 'mmc dev ${mmcdev}' commands.
- Rework some of the RAM related Kconfig symbols for phycore_imx8mp.
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12013aa..93ee5b7 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -100,9 +100,6 @@
int ret;
arch_cpu_init();
-
- init_uart_clk(1);
-
timer_init();
/* Clear the BSS. */
@@ -114,8 +111,6 @@
hang();
}
- preloader_console_init();
-
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
@@ -124,6 +119,7 @@
hang();
}
+ preloader_console_init();
enable_tzc380();
power_init_board();
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index f03841e..e91d3fd 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -111,8 +111,6 @@
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
- init_uart_clk(1);
-
return 0;
}
diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 30d577f..6b357d9 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -112,8 +112,6 @@
arch_cpu_init();
- init_uart_clk(1);
-
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index bdf9e97..caf9cb0 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -45,7 +45,6 @@
config PHYCORE_IMX8MP_RAM_SIZE_8GB
bool "8GB RAM"
- select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
help
Set RAM size fix to 8GB for phyCORE-i.MX8MP.
Only 2GHz RAMs are supported.
@@ -54,7 +53,6 @@
config PHYCORE_IMX8MP_RAM_FREQ_FIX
bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
- default false
help
RAM frequency is automatic being detected with the help of
the EEPROM introspection data. Set RAM frequency to a fix value
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index a69e2ba..288626c 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -87,6 +87,7 @@
CONFIG_ETHPRIME="eth1"
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 870b7a1..25b0b11 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -13,7 +13,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f841b21..737a079 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -24,7 +24,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 11a18d1..964d00a 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -24,7 +24,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 316f74c..369bc0f 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -14,7 +14,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 8be5963..97d4f9f 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -15,7 +15,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2c13dd4..1a49bc2 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -14,7 +14,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 56d893e..d17a54f 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -60,6 +60,7 @@
depends on ARCH_IMX8M && SPL
select SPL_CLK
select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
help
This enables SPL DM/DTS support for clock driver in i.MX8MP
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f028..61ca298 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,8 @@
static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
"pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
static int imx6q_clk_probe(struct udevice *dev)
{
@@ -78,6 +80,15 @@
imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ if (of_machine_is_compatible("fsl,imx6qp")) {
+ clk_dm(IMX6QDL_CLK_UART_SEL,
+ imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels,
+ ARRAY_SIZE(uart_sels)));
+ clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+ imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
+ ARRAY_SIZE(ecspi_sels)));
+ }
+
clk_dm(IMX6QDL_CLK_USDHC1_PODF,
imx_clk_divider("usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
@@ -91,8 +102,17 @@
imx_clk_divider("usdhc4_podf", "usdhc4_sel",
base + 0x24, 22, 3));
- clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
- imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+ if (of_machine_is_compatible("fsl,imx6qp")) {
+ clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+ imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+ } else {
+ clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+ imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+ }
clk_dm(IMX6QDL_CLK_ECSPI1,
imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
@@ -102,6 +122,10 @@
imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
clk_dm(IMX6QDL_CLK_ECSPI4,
imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+ clk_dm(IMX6QDL_CLK_UART_IPG,
+ imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24));
+ clk_dm(IMX6QDL_CLK_UART_SERIAL,
+ imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26));
clk_dm(IMX6QDL_CLK_USDHC1,
imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
clk_dm(IMX6QDL_CLK_USDHC2,
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bb6958f..378c07c 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -81,6 +81,22 @@
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
+static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+ "audio_pll2_out", };
+
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m",
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
@@ -322,6 +338,24 @@
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+
+ clk_dm(IMX8MM_CLK_UART1,
+ imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MM_CLK_UART2,
+ imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MM_CLK_UART3,
+ imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MM_CLK_UART4,
+ imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MM_CLK_UART1_ROOT,
+ imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MM_CLK_UART2_ROOT,
+ imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MM_CLK_UART3_ROOT,
+ imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MM_CLK_UART4_ROOT,
+ imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be15ebd..54ae887 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -97,6 +97,22 @@
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
+static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
#ifndef CONFIG_XPL_BUILD
static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
@@ -311,6 +327,14 @@
imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
clk_dm(IMX8MN_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MN_CLK_UART1,
+ imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MN_CLK_UART2,
+ imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MN_CLK_UART3,
+ imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MN_CLK_UART4,
+ imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080));
clk_dm(IMX8MN_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
clk_dm(IMX8MN_CLK_USDHC3,
@@ -355,6 +379,14 @@
imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
"nand_usdhc_bus", base + 0x4300, 0,
&share_count_nand));
+ clk_dm(IMX8MN_CLK_UART1_ROOT,
+ imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MN_CLK_UART2_ROOT,
+ imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MN_CLK_UART3_ROOT,
+ imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MN_CLK_UART4_ROOT,
+ imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index c5fd740..28f4435 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
*/
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
@@ -312,7 +313,17 @@
static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_plat *plat = dev_get_plat(dev);
+#if CONFIG_IS_ENABLED(CLK_CCF)
+ int ret;
+ ret = clk_get_bulk(dev, &plat->clks);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(&plat->clks);
+ if (ret)
+ return ret;
+#endif
_mxc_serial_init(plat->reg, plat->use_dte);
return 0;
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index cc59eeb..52657aa 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,9 @@
/* Information about a serial port */
struct mxc_serial_plat {
struct mxc_uart *reg; /* address of registers in physical memory */
+#if CONFIG_IS_ENABLED(CLK_CCF)
+ struct clk_bulk clks;
+#endif
bool use_dte;
};