i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 27dabaa..29cf295 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,7 +46,7 @@
void init_sc520_enet (void)
{
/* Set CPU Speed to 100MHz */
- write_mmcr_byte(SC520_CPUCTL, 1);
+ sc520_mmcr->cpuctl = 0x01;
gd->cpu_clk = 100000000;
/* wait at least one millisecond */
@@ -56,7 +56,7 @@
"loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
- write_mmcr_byte(SC520_DBCTL, 0x11);
+ sc520_mmcr->dbctl = 0x11;
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
@@ -71,51 +71,51 @@
{
init_sc520_enet();
- write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
- write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
- write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
- write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
- write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
- write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
- write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
+ sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */
+ sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */
+ sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */
+ sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */
+ sc520_mmcr->gprdoff = 0x01; /* GP Read offset */
+ sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
+ sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
- write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
- write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
- write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
- write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
- write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
- write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
- write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
+ sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
+ sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
+ sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
+ sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
+ sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
+ sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
+ sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
- write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
- write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
- write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
- write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
- write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
- write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
- write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
- write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
-/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
-/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+ sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+ sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+ sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+ sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+ sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */
+ sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+ sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+ sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */
+ sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */
+ sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */
+ sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */
+ sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */
+/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
+/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */
- write_mmcr_word(0x0cb0, 0x3333);
- write_mmcr_word(0x0cb0, 0xcccc);
- write_mmcr_word(0x0cb0, 0x0000);
+ sc520_mmcr->wdtmrctl = 0x3333;
+ sc520_mmcr->wdtmrctl = 0xcccc;
+ sc520_mmcr->wdtmrctl = 0x0000;
/* Chip Select Configuration */
- write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
- write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
- write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
+ sc520_mmcr->bootcsctl = 0x0033;
+ sc520_mmcr->romcs1ctl = 0x0615;
+ sc520_mmcr->romcs2ctl = 0x0615;
- write_mmcr_byte(SC520_ADDDECCTL, 0x02);
- write_mmcr_byte(SC520_UART1CTL, 0x07);
- write_mmcr_byte(SC520_SYSARBCTL,0x06);
- write_mmcr_word(SC520_SYSARBMENB, 0x0003);
+ sc520_mmcr->adddecctl = 0x02;
+ sc520_mmcr->uart1ctl = 0x07;
+ sc520_mmcr->sysarbctl = 0x06;
+ sc520_mmcr->sysarbmenb = 0x0003;
/* Crystal is 33.000MHz */
gd->bus_clk = 33000000;