Merge http://git.denx.de/u-boot-samsung
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/peach-pi_defconfig
configs/peach-pit_defconfig
diff --git a/Kconfig b/Kconfig
index f53759a..4b46216 100644
--- a/Kconfig
+++ b/Kconfig
@@ -268,7 +268,7 @@
config SYS_TEXT_BASE
depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
- (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
+ (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
depends on !EFI_APP
hex "Text Base"
help
diff --git a/Makefile b/Makefile
index 4dc179b..742b165 100644
--- a/Makefile
+++ b/Makefile
@@ -801,13 +801,6 @@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
all: $(ALL-y)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo "===================== WARNING ======================"
- @echo "Please convert this board to generic board."
- @echo "Otherwise it will be removed by the end of 2014."
- @echo "See doc/README.generic-board for further information"
- @echo "===================================================="
-endif
ifeq ($(CONFIG_DM_I2C_COMPAT),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -1257,13 +1250,6 @@
prepare1: prepare2 $(version_h) $(timestamp_h) \
include/config/auto.conf
-ifeq ($(CONFIG_HAVE_GENERIC_BOARD),)
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
- @echo >&2 " Your architecture does not support generic board."
- @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
- @/bin/false
-endif
-endif
ifeq ($(wildcard $(LDSCRIPT)),)
@echo >&2 " Could not find linker script."
@/bin/false
diff --git a/README b/README
index 6f4c09a..1d0b946 100644
--- a/README
+++ b/README
@@ -4048,16 +4048,6 @@
If defined, don't allow the -f switch to env set override variable
access flags.
-- CONFIG_SYS_GENERIC_BOARD
- This selects the architecture-generic board system instead of the
- architecture-specific board files. It is intended to move boards
- to this new framework over time. Defining this will disable the
- arch/foo/lib/board.c file and use common/board_f.c and
- common/board_r.c instead. To use this option your architecture
- must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig).
- If you find problems enabling this option on your board please report
- the problem and send patches!
-
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
This is set by OMAP boards for the max time that reset should
be asserted. See doc/README.omap-reset-time for details on how
diff --git a/arch/Kconfig b/arch/Kconfig
index ec12013..566f044 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,13 +1,6 @@
config CREATE_ARCH_SYMLINK
bool
-config HAVE_GENERIC_BOARD
- bool
-
-config SYS_GENERIC_BOARD
- bool
- depends on HAVE_GENERIC_BOARD
-
choice
prompt "Architecture select"
default SANDBOX
@@ -15,57 +8,39 @@
config ARC
bool "ARC architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config ARM
bool "ARM architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config AVR32
bool "AVR32 architecture"
select CREATE_ARCH_SYMLINK
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config BLACKFIN
bool "Blackfin architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config MICROBLAZE
bool "MicroBlaze architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config MIPS
bool "MIPS architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
config NIOS2
bool "Nios II architecture"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
@@ -77,14 +52,10 @@
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
config SANDBOX
bool "Sandbox"
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select DM
select DM_SPI_FLASH
@@ -99,15 +70,12 @@
config SPARC
bool "SPARC architecture"
- select HAVE_GENERIC_BOARD
select CREATE_ARCH_SYMLINK
config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
- select HAVE_GENERIC_BOARD
- select SYS_GENERIC_BOARD
select SUPPORT_OF_CONTROL
select DM
select DM_SERIAL
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3eb6e5d..30ed279 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,20 @@
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
+config SYS_ARM_ARCH
+ int
+ default 4 if CPU_ARM720T
+ default 4 if CPU_ARM920T
+ default 5 if CPU_ARM926EJS
+ default 5 if CPU_ARM946ES
+ default 6 if CPU_ARM1136
+ default 6 if CPU_ARM1176
+ default 7 if CPU_V7
+ default 7 if CPU_V7M
+ default 5 if CPU_PXA
+ default 4 if CPU_SA1100
+ default 8 if ARM64
+
config SEMIHOSTING
bool "support boot from semihosting"
help
@@ -77,6 +91,14 @@
If SoC does not support L2CACHE or one do not want to enable
L2CACHE, choose this option.
+config ENABLE_ARM_SOC_BOOT0_HOOK
+ bool "prepare BOOT0 header"
+ help
+ If the SoC's BOOT0 requires a header area filled with (magic)
+ values, then choose this option, and create a define called
+ ARM_SOC_BOOT0_HOOK which contains the required assembler
+ preprocessor code.
+
choice
prompt "Target select"
default TARGET_HIKEY
@@ -381,12 +403,6 @@
select DM
select DM_SERIAL
-config TARGET_AM43XX_EVM
- bool "Support am43xx_evm"
- select CPU_V7
- select SUPPORT_SPL
- select TI_I2C_BOARD_DETECT
-
config TARGET_BAV335X
bool "Support bav335x"
select CPU_V7
@@ -455,6 +471,13 @@
select SUPPORT_SPL
select CMD_POWEROFF
+config ARCH_MESON
+ bool "Amlogic Meson"
+ help
+ Support for the Meson SoC family developed by Amlogic Inc.,
+ targeted at media players and tablet computers. We currently
+ support the S905 (GXBaby) 64-bit SoC.
+
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
@@ -506,6 +529,17 @@
select CPU_V7
select SUPPORT_SPL
+config AM43XX
+ bool "AM43XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
+ help
+ Support for AM43xx SOC from Texas Instruments.
+ The AM43xx high performance SOC features a Cortex-A9
+ ARM core, a quad core PRU-ICSS for industrial Ethernet
+ protocols, dual camera support, optional 3D graphics
+ and an optional customer programmable secure boot.
+
config RMOBILE
bool "Renesas ARM SoCs"
select CPU_V7
@@ -537,7 +571,16 @@
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
+ select CMD_BOOTZ
+ select CMD_DHCP
+ select CMD_EXT2
+ select CMD_EXT4
+ select CMD_FAT
+ select CMD_FS_GENERIC
select CMD_GPIO
+ select CMD_MII
+ select CMD_MMC if MMC
+ select CMD_PING
select CMD_USB
select DM
select DM_ETH
@@ -545,6 +588,7 @@
select DM_KEYBOARD
select DM_SERIAL
select DM_USB
+ select HUSH_PARSER
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
@@ -673,6 +717,33 @@
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+config TARGET_LS1012AQDS
+ bool "Support ls1012aqds"
+ select ARM64
+ help
+ Support for Freescale LS1012AQDS platform.
+ The LS1012A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012ARDB
+ bool "Support ls1012ardb"
+ select ARM64
+ help
+ Support for Freescale LS1012ARDB platform.
+ The LS1012A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
+config TARGET_LS1012AFRDM
+ bool "Support ls1012afrdm"
+ select ARM64
+ help
+ Support for Freescale LS1012AFRDM platform.
+ The LS1012A Freedom board (FRDM) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -743,6 +814,7 @@
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
+ select ARM64
select OF_CONTROL
endchoice
@@ -771,16 +843,14 @@
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/cpu/armv7/omap3/Kconfig"
-
-source "arch/arm/cpu/armv7/omap4/Kconfig"
-
-source "arch/arm/cpu/armv7/omap5/Kconfig"
+source "arch/arm/cpu/armv7/omap-common/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-meson/Kconfig"
+
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s5pc1xx/Kconfig"
@@ -831,6 +901,9 @@
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d516345..6a07cd1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -11,7 +11,7 @@
arch-$(CONFIG_CPU_ARM720T) =-march=armv4
arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
-arch-$(CONFIG_CPU_ARM946ES) =-march=armv4
+arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5
@@ -50,6 +50,7 @@
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig
new file mode 100644
index 0000000..dc51e9b
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/Kconfig
@@ -0,0 +1,40 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+ bool "Support am43xx_evm"
+ select TI_I2C_BOARD_DETECT
+ help
+ This option specifies support for the AM43xx
+ GP and HS EVM development platforms.The AM437x
+ GP EVM is a standalone test, development, and
+ evaluation module system that enables developers
+ to write software and develop hardware around
+ an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+ hex "Address in memory or XIP flash of bootloader entry point"
+ help
+ After any reset, the boot ROM on the AM43XX SOC
+ searches the boot media for a valid boot image.
+ For non-XIP devices, the ROM then copies the
+ image into internal memory.
+ For all boot modes, after the ROM processes the
+ boot image it eventually computes the entry
+ point address depending on the device type
+ (secure/non-secure), boot media (xip/non-xip) and
+ image headers.
+ default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+ hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+ help
+ During the device boot, the public ROM uses the top of
+ the public L3 OCMC RAM to store r/w data like stack,
+ heap, globals etc. When the ROM is copying the boot
+ image from the boot media into memory, the image must
+ not spill over into this area. This value can be used
+ during compile time to determine the maximum size of a
+ boot image. Once the ROM transfers control to the boot
+ image, this area is no longer used, and can be reclaimed
+ for run time use by the boot image.
+ default 0x8400
+endif
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index aae3f09..6fda482 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,3 +18,5 @@
obj-y += emif4.o
obj-y += board.o
obj-y += mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
new file mode 100644
index 0000000..316e677
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
@@ -0,0 +1,104 @@
+/*
+ * clk-synthesizer.c
+ *
+ * Clock synthesizer apis
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <i2c.h>
+
+/**
+ * clk_synthesizer_reg_read - Read register from synthesizer.
+ * @addr: addr within the i2c device
+ * buf: Buffer to which value is to be read.
+ *
+ * For reading the register from this clock synthesizer, a command needs to
+ * be send along with enabling byte read more, and then read can happen.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_read(int addr, uint8_t *buf)
+{
+ int rc;
+
+ /* Enable Bye read */
+ addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
+
+ /* Send the command byte */
+ rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+ if (rc)
+ printf("Failed to send command to clock synthesizer\n");
+
+ /* Read the Data */
+ return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+}
+
+/**
+ * clk_synthesizer_reg_write - Write a value to register in synthesizer.
+ * @addr: addr within the i2c device
+ * val: Value to be written in the addr.
+ *
+ * Enable the byte read mode in the address and start the i2c transfer.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_write(int addr, uint8_t val)
+{
+ uint8_t cmd[2];
+ int rc = 0;
+
+ /* Enable byte write */
+ cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
+ cmd[1] = val;
+
+ rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
+ if (rc)
+ printf("Clock synthesizer reg write failed at addr = 0x%x\n",
+ addr);
+ return rc;
+}
+
+/**
+ * setup_clock_syntherizer - Program the clock synthesizer to get the desired
+ * frequency.
+ * @data: Data containing the desired output
+ *
+ * This is a PLL-based high performance synthesizer which gives 3 outputs
+ * as per the PLL_DIV and load capacitor programmed.
+ */
+int setup_clock_synthesizer(struct clk_synth *data)
+{
+ int rc;
+ uint8_t val;
+
+ rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
+ if (rc) {
+ printf("i2c probe failed at address 0x%x\n",
+ CLK_SYNTHESIZER_I2C_ADDR);
+ return rc;
+ }
+
+ rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val);
+ if (val != data->id)
+ return rc;
+
+ /* Crystal Load capacitor selection */
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2);
+ if (rc)
+ return rc;
+ rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3);
+ if (rc)
+ return rc;
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 5c2a2ab..73ea955 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -160,7 +160,7 @@
}
#endif
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 *usbclkctrl = 0;
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5294d16..6d95d32 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -3,9 +3,29 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
+
+include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y += u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
ALL-y += MLO
ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+endif
ALL-y += u-boot.img
endif
diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig
new file mode 100644
index 0000000..7b39506
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/Kconfig
@@ -0,0 +1,17 @@
+config TI_SECURE_DEVICE
+ bool "HS Device Type Support"
+ depends on OMAP54XX || AM43XX
+ help
+ If a high secure (HS) device type is being used, this config
+ must be set. This option impacts various aspects of the
+ build system (to create signed boot images that can be
+ authenticated) and the code. See the doc/README.ti-secure
+ file for further details.
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/armv7/am33xx/Kconfig"
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index ef2ac98..2de9935 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -236,6 +236,8 @@
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
+
+ bypass_dpll(base);
goto setup_post_dividers;
}
}
@@ -251,13 +253,13 @@
writel(temp, &dpll_regs->cm_clksel_dpll);
+setup_post_dividers:
+ setup_post_dividers(base, params);
+
/* Lock */
if (lock)
do_lock_dpll(base);
-setup_post_dividers:
- setup_post_dividers(base, params);
-
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk
new file mode 100644
index 0000000..c7bb101
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk
@@ -0,0 +1,66 @@
+#
+# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+quiet_cmd_mkomapsecimg = MKIMAGE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
+ifneq ($(CONFIG_SPL_BUILD),)
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+endif
+else
+cmd_mkomapsecimg = echo "WARNING:" \
+ "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
+ "$@ was NOT created!"
+endif
+else
+cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+ "variable must be defined for TI secure devices. $@ was NOT created!"
+endif
+
+# Standard X-LOADER target (QPSI, NOR flash)
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For MLO targets (SD card boot) the final file name
+# that is copied to the SD card fAT partition must
+# be MLO, so we make a copy of the output file to a
+# new file with that name
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+ @if [ -f $@ ]; then \
+ cp -f $@ MLO; \
+ fi
+
+# Standard 2ND target (certain peripheral boot modes)
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# Standard ULO target (certain peripheral boot modes)
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# Standard ISSW target (certain devices, various boot modes)
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For SPI flash on AM335x and AM43xx, these
+# require special byte swap handling so we use
+# the SPI_X-LOADER target instead of X-LOADER
+# and let the create-boot-image.sh script handle
+# that
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkomapsecimg)
+
+# For supporting single stage XiP QSPI on AM43xx, the
+# image is a full u-boot file, not an SPL. In this case
+# the mkomapsecimg command looks for a u-boot-HS_* prefix
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+ $(call if_changed,mkomapsecimg)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 01c2d57..2f9693f 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -65,12 +65,30 @@
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
+ const char *sec_s;
+
+ switch (get_device_type()) {
+ case TST_DEVICE:
+ sec_s = "TST";
+ break;
+ case EMU_DEVICE:
+ sec_s = "EMU";
+ break;
+ case HS_DEVICE:
+ sec_s = "HS";
+ break;
+ case GP_DEVICE:
+ sec_s = "GP";
+ break;
+ default:
+ sec_s = "?";
+ }
+
if (soc_variant)
printf("OMAP");
else
printf("DRA");
- printf("%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+ printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
}
#ifdef CONFIG_SPL_BUILD
@@ -94,6 +112,16 @@
{
}
+/**
+ * vcores_init() - Assign omap_vcores based on board
+ *
+ * Function to pick the vcores based on board. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak vcores_init(void)
+{
+}
+
void s_init(void)
{
}
@@ -131,6 +159,7 @@
#endif
setup_early_clocks();
do_board_detect();
+ vcores_init();
prcm_init();
}
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
index 52ea734..2d03ebf 100644
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -108,6 +108,6 @@
omap_die_id(die_id);
- printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1],
- die_id[2], die_id[3]);
+ printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2],
+ die_id[1], die_id[0]);
}
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index f2930d5..3caba86 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -12,4 +12,5 @@
obj-y += prcm-regs.o
obj-y += hw_data.o
obj-y += abb.o
+obj-y += fdt.o
obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index ef2725a..a7e55a5 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -6,8 +6,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
+include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
+else
ALL-y += MLO
+endif
else
ALL-y += u-boot.img
endif
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
new file mode 100644
index 0000000..0493cd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/fdt.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2016 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-omap5/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+static u32 hs_irq_skip[] = {
+ 8, /* Secure violation reporting interrupt */
+ 15, /* One interrupt for SDMA by secure world */
+ 118 /* One interrupt for Crypto DMA by secure world */
+};
+
+static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ int len, i, old_cnt, new_cnt;
+ u32 *temp;
+ const u32 *p_data;
+
+ /*
+ * Increase the size of the fdt
+ * so we have some breathing room
+ */
+ ret = fdt_increase_size(fdt, 512);
+ if (ret < 0) {
+ printf("Could not increase size of device tree: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+
+ /* Reserve IRQs that are used/needed by secure world */
+ path = "/ocp/crossbar";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* Get current entries */
+ p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
+ if (p_data)
+ old_cnt = len / sizeof(u32);
+ else
+ old_cnt = 0;
+
+ new_cnt = sizeof(hs_irq_skip) /
+ sizeof(hs_irq_skip[0]);
+
+ /* Create new/updated skip list for HS parts */
+ temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
+ for (i = 0; i < new_cnt; i++)
+ temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
+ for (i = 0; i < old_cnt; i++)
+ temp[i + new_cnt] = p_data[i];
+
+ /* Blow away old data and set new data */
+ fdt_delprop(fdt, offs, "ti,irqs-skip");
+ ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
+ temp,
+ (old_cnt + new_cnt) * sizeof(u32));
+ free(temp);
+
+ /* Check if the update worked */
+ if (ret < 0) {
+ printf("Could not add ti,irqs-skip property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+
+ /* Make HW RNG reserved for secure world use */
+ path = "/ocp/rng";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+ ret = fdt_setprop_string(fdt, offs,
+ "status", "disabled");
+ if (ret < 0) {
+ printf("Could not add status property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+ return 0;
+}
+
+#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
+ (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ u32 temp[2];
+
+ /*
+ * Update SRAM reservations on secure devices. The OCMC RAM
+ * is always reserved for secure use from the start of that
+ * memory region
+ */
+ path = "/ocp/ocmcram@40300000/sram-hs";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* relative start offset */
+ temp[0] = cpu_to_fdt32(0);
+ /* reservation size */
+ temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
+ CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+ fdt_delprop(fdt, offs, "reg");
+ ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
+ if (ret < 0) {
+ printf("Could not add reg property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+ /* Check we are running on an HS/EMU device type */
+ if (GP_DEVICE != get_device_type()) {
+ if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
+ (ft_hs_disable_rng(fdt, bd) == 0) &&
+ (ft_hs_fixup_sram(fdt, bd) == 0))
+ return;
+ } else {
+ printf("ERROR: Incorrect device type (GP) detected!");
+ }
+ /* Fixup failed or wrong device type */
+ hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+}
+#endif
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+ ft_hs_fixups(fdt, bd);
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 88e8920..5b91446a 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,35 +365,35 @@
};
struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
@@ -401,15 +401,15 @@
};
struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA72x,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA72x,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
@@ -418,22 +418,22 @@
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
- .gpu.value = VDD_GPU_DRA72x,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA72x,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .iva.value = VDD_IVA_DRA72x,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
@@ -602,7 +602,7 @@
}
#endif
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
@@ -614,9 +614,14 @@
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
- /* Enable 32 KHz clock for dwc3 */
+ /* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Enable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
@@ -664,9 +669,14 @@
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
- /* Disable 32 KHz clock for dwc3 */
+ /* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Disable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 655e92b..b5f1d70 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -820,6 +820,7 @@
.cm_clkmode_dpll_gmac = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
+ .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
.cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
/* cm1.mpu */
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index a9f4fec..46f25e6 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -14,15 +14,15 @@
#include <linux/linkage.h>
/*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
*
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
*
* x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@
b.ge loop_set
ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
*
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
*/
ENTRY(__asm_dcache_all)
mov x1, x0
@@ -87,7 +87,7 @@
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
b.lt skip /* skip if no cache or icache */
- bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
+ bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
@@ -104,19 +104,13 @@
ENDPROC(__asm_dcache_all)
ENTRY(__asm_flush_dcache_all)
- mov x16, lr
mov x0, #0
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
- mov x16, lr
mov x0, #0x1
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
/*
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5f86ef9..eb2cbc3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,3 +28,7 @@
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644
index 0000000..8eee016
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -0,0 +1,129 @@
+SoC overview
+
+ 1. LS1043A
+ 2. LS2080A
+ 3. LS1012A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+ - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x QSGMII
+ - Up to 4 x SGMII supporting 1000Mbps
+ - Up to 2 x SGMII supporting 2500Mbps
+ - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+ - Three PCIe 2.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+ 16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+ Two Serdes PLLs supported for usage by any SerDes data lane
+ Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+ - One PCI Express Gen2 controller, supporting x1 operation
+ - One serial ATA (SATA Gen 3.0) controller
+ - One USB 3.0/2.0 controller with integrated PHY
+ - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+ - One quad serial peripheral interface (QuadSPI) controller
+ - One serial peripheral interface (SPI) controller
+ - Two enhanced secure digital host controllers
+ - Two I2C controllers
+ - One 16550 compliant DUART (two UART interfaces)
+ - Two general purpose IOs (GPIO)
+ - Two FlexTimers
+ - Five synchronous audio interfaces (SAI)
+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+ - Single-source clocking solution enabling generation of core, platform,
+ DDR, SerDes, and USB clocks from a single external crystal and internal
+ crystaloscillator
+ - Thermal monitor unit (TMU) with +/- 3C accuracy
+ - Two WatchDog timers
+ - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 453a93d..3a77b21 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,10 @@
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+ defined(CONFIG_SYS_DPAA_FMAN)
+
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -56,12 +59,18 @@
sys_info->freq_ddrbus = sysclk;
#endif
+#ifdef CONFIG_LS1012A
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -80,6 +89,11 @@
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
+#ifdef CONFIG_LS1012A
+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+ sys_info->freq_ddrbus *= 2;
+#endif
+
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 04831ca..5af6b73 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -94,11 +94,13 @@
bl ccn504_set_qos
#endif
+#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]
orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
str w0, [x1, #0x10]
+#endif
/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
@@ -181,6 +183,7 @@
ret
ENDPROC(lowlevel_init)
+#ifdef CONFIG_FSL_LSCH3
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@@ -258,6 +261,7 @@
mov lr, x29
ret
ENDPROC(__asm_flush_l3_cache)
+#endif
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
new file mode 100644
index 0000000..ff0903c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+ {0x0008, {NONE, NONE, NONE, SATA1} },
+ {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+ {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+ {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+ {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+ {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..dd633f3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,8 +12,10 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
+#endif
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
@@ -224,7 +226,7 @@
}
#endif
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 9efcc5a..079e250 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -8,6 +8,7 @@
#include <config.h>
#include <version.h>
#include <asm/macro.h>
+#include <asm/psci.h>
#include <asm/system.h>
/*
@@ -73,3 +74,18 @@
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17");
}
+
+void __noreturn psci_system_reset(bool conduit_smc)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+
+ if (conduit_smc)
+ smc_call(®s);
+ else
+ hvc_call(®s);
+
+ while (1)
+ ;
+}
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e933021..c1a2f45 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -21,6 +21,16 @@
_start:
b reset
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
.align 3
.globl _TEXT_BASE
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 5dd3cd8..509f0aa 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -63,6 +63,11 @@
};
struct mm_region *mem_map = zynqmp_mem_map;
+u64 get_page_table_size(void)
+{
+ return 0x14000;
+}
+
static unsigned int zynqmp_get_silicon_version_secure(void)
{
u32 ver;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index da25715..a827613 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -27,6 +27,8 @@
rk3288-jerry.dtb \
rk3288-rock2-square.dtb \
rk3036-sdk.dtb
+dtb-$(CONFIG_ARCH_MESON) += \
+ meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -46,6 +48,7 @@
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb \
+ tegra186-p2771-0000.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
@@ -89,9 +92,15 @@
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
+ zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
-dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
+ am335x-evmsk.dtb \
+ am335x-bonegreen.dtb \
+ am335x-icev2.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
+ am43x-epos-evm.dtb \
+ am437x-idk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
@@ -101,7 +110,8 @@
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
- socfpga_cyclone5_sr1500.dtb
+ socfpga_cyclone5_sr1500.dtb \
+ socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
@@ -114,7 +124,10 @@
fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
- fsl-ls1043a-rdb.dtb
+ fsl-ls1043a-rdb.dtb \
+ fsl-ls1012a-qds.dtb \
+ fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
@@ -219,7 +232,8 @@
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-plus.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
- pine64_plus.dtb
+ sun50i-a64-pine64-plus.dtb \
+ sun50i-a64-pine64.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index fec7834..40a3c35 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -13,6 +13,11 @@
};
};
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
@@ -383,8 +388,7 @@
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&aes {
diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts
index 81441cc..6b84937 100644
--- a/arch/arm/dts/am335x-bone.dts
+++ b/arch/arm/dts/am335x-bone.dts
@@ -13,9 +13,6 @@
/ {
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
- chosen {
- stdout-path = &uart0;
- };
};
&ldo3_reg {
diff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts
new file mode 100644
index 0000000..9c59da9
--- /dev/null
+++ b/arch/arm/dts/am335x-bonegreen.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone Green";
+ compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+};
+
+&ldo3_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&am33xx_pinmux {
+ uart2_pins: uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
+ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&rtc {
+ system-power-controller;
+};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index c0bc2af..a6f20af 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -717,7 +717,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc3 {
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
new file mode 100644
index 0000000..b3e9b61
--- /dev/null
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -0,0 +1,720 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x Starter Kit
+ * http://www.ti.com/tool/tmdssk3358
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "TI AM335x EVM-SK";
+ compatible = "ti,am335x-evmsk", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ lis3_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lis3_reg";
+ regulator-boot-on;
+ };
+
+ wl12xx_vmmc: fixedregulator@2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_gpio>;
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 29 0>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ vtt_fixed: fixedregulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "evmsk:green:usr0";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "evmsk:green:usr1";
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "evmsk:green:mmc0";
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "evmsk:green:heartbeat";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ gpio_buttons: gpio_buttons@0 {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@1 {
+ label = "button0";
+ linux,code = <0x100>;
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ switch@2 {
+ label = "button1";
+ linux,code = <0x101>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ switch@3 {
+ label = "button2";
+ linux,code = <0x102>;
+ gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
+ };
+
+ switch@4 {
+ label = "button3";
+ linux,code = <0x103>;
+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 58 61 66 75 90 125 170 255>;
+ default-brightness-level = <8>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM335x-EVMSK";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24000000>;
+ };
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&lcd_pins_default>;
+ pinctrl-1 = <&lcd_pins_sleep>;
+ status = "okay";
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+ display-timings {
+ 480x272 {
+ hactive = <480>;
+ vactive = <272>;
+ hback-porch = <43>;
+ hfront-porch = <8>;
+ hsync-len = <4>;
+ vback-porch = <12>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+ clock-frequency = <9000000>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
+
+ lcd_pins_default: lcd_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
+ AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
+ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
+ AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
+ AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
+ AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
+ AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
+ AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
+ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+ lcd_pins_sleep: lcd_pins_sleep {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
+ AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
+ AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
+ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
+ AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
+ AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
+ AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
+ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
+ AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
+ AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
+ AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
+ AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
+ >;
+ };
+
+ gpio_keys_s0: gpio_keys_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
+ AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
+ AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ ecap2_pins: backlight_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+
+ /* Slave 2 */
+ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
+ AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+ /* Slave 2 reset value*/
+ AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+ AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+ >;
+ };
+
+ mcasp1_pins_sleep: mcasp1_pins_sleep {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ >;
+ };
+
+ wl12xx_gpio: pinmux_wl12xx_gpio {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+
+ lis331dlh: lis331dlh@18 {
+ compatible = "st,lis331dlh", "st,lis3lv02d";
+ reg = <0x18>;
+ Vdd-supply = <&lis3_reg>;
+ Vdd_IO-supply = <&lis3_reg>;
+
+ st,click-single-x;
+ st,click-single-y;
+ st,click-single-z;
+ st,click-thresh-x = <10>;
+ st,click-thresh-y = <10>;
+ st,click-thresh-z = <10>;
+ st,irq1-click;
+ st,irq2-click;
+ st,wakeup-x-lo;
+ st,wakeup-x-hi;
+ st,wakeup-y-lo;
+ st,wakeup-y-hi;
+ st,wakeup-z-lo;
+ st,wakeup-z-hi;
+ st,min-limit-x = <120>;
+ st,min-limit-y = <120>;
+ st,min-limit-z = <140>;
+ st,max-limit-x = <550>;
+ st,max-limit-y = <550>;
+ st,max-limit-z = <750>;
+ };
+
+ tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&vaux2_reg>;
+ IOVDD-supply = <&vaux2_reg>;
+ DRVDD-supply = <&vaux2_reg>;
+ DVDD-supply = <&vbat>;
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&epwmss2 {
+ status = "okay";
+
+ ecap2: ecap@48304100 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap2_pins>;
+ };
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0 {
+ ti,no-reset-on-init;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&wl12xx_vmmc>;
+ ti,non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_pins_sleep>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordinate-readouts = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ };
+};
+
+&lcdc {
+ status = "okay";
+};
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
new file mode 100644
index 0000000..debc6f6
--- /dev/null
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x ICE V2 board
+ * http://www.ti.com/tool/tmdsice3359
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "TI AM3359 ICE-V2";
+ compatible = "ti,am3359-icev2", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart3;
+ tick-timer = &timer2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ vtt_fixed: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ leds@0 {
+ compatible = "gpio-leds";
+
+ led@0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ /* Tricolor status LEDs */
+ leds@1 {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds>;
+
+ led@0 {
+ label = "status0:red:cpu0";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ led@1 {
+ label = "status0:green:usr";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "status0:yellow:usr";
+ gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "status1:red:mmc0";
+ gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+
+ led@4 {
+ label = "status1:green:usr";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "status1:yellow:usr";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&am33xx_pinmux {
+ user_leds: user_leds {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+ AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+ AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+ AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+ >;
+ };
+
+ mmc0_pins_default: mmc0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
+ >;
+ };
+
+ i2c0_pins_default: i2c0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+ >;
+ };
+
+ spi0_pins_default: spi0_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ uart3_pins_default: uart3_pins_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+ AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1, RMII mode */
+ AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */
+ AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */
+ AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */
+ AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */
+ AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */
+ AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */
+ AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */
+ AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */
+ /* Slave 2, RMII mode */
+ AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */
+ AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */
+ AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */
+ AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */
+ AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */
+ AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */
+ AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */
+ AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+
+ /* Slave 2 reset value */
+ AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_default>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: power-controller@2d {
+ reg = <0x2d>;
+ };
+
+ tpic2810: gpio@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1326000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+};
+
+&gpio0 {
+ /* Do not idle the GPIO used for holding the VTT regulator */
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+
+ p7 {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FET_SWITCH_CTRL";
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_default>;
+ status = "okay";
+};
+
+&gpio3 {
+ p4 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PR1_MII_CTRL";
+ };
+
+ p10 {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MUX_MII_CTRL";
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+ dual_emac;
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>; /* PHY datasheet states 1uS min */
+};
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
new file mode 100644
index 0000000..478f0a6
--- /dev/null
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "TI AM437x Industrial Development Kit";
+ compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ v24_0d: fixed-regulator-v24_0d {
+ compatible = "regulator-fixed";
+ regulator-name = "V24_0D";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ v3_3d: fixed-regulator-v3_3d {
+ compatible = "regulator-fixed";
+ regulator-name = "V3_3D";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ vdd_corereg: fixed-regulator-vdd_corereg {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_COREREG";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ vdd_core: fixed-regulator-vdd_core {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_corereg>;
+ };
+
+ v1_8dreg: fixed-regulator-v1_8dreg{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_8DREG";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ v1_8d: fixed-regulator-v1_8d{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_8D";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v1_8dreg>;
+ };
+
+ v1_5dreg: fixed-regulator-v1_5dreg{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_5DREG";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v24_0d>;
+ };
+
+ v1_5d: fixed-regulator-v1_5d{
+ compatible = "regulator-fixed";
+ regulator-name = "V1_5D";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&v1_5dreg>;
+ };
+
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ label = "power-button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /* fixed 32k external oscillator clock */
+ clk_32k_rtc: clk_32k_rtc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+};
+
+&am43xx_pinmux {
+ gpio_keys_pins_default: gpio_keys_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
+ >;
+ };
+
+ i2c0_pins_default: i2c0_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c0_pins_sleep: i2c0_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ i2c2_pins_default: i2c2_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+ AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+ >;
+ };
+
+ i2c2_pins_sleep: i2c2_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins_default: pinmux_mmc1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ ecap0_pins_default: backlight_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
+ AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
+ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
+ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ qspi_pins_default: qspi_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
+ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
+ >;
+ };
+
+ qspi_pins_sleep: qspi_pins_sleep{
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c0_pins_default>;
+ pinctrl-1 = <&i2c0_pins_sleep>;
+ clock-frequency = <400000>;
+
+ at24@50 {
+ compatible = "at24,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+
+ tps: tps62362@60 {
+ compatible = "ti,tps62362";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1330000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ vin-supply = <&v3_3d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_default>;
+ pinctrl-1 = <&i2c2_pins_sleep>;
+ clock-frequency = <100000>;
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins_default>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_sleep>;
+ vmmc-supply = <&v3_3d>;
+ bus-width = <4>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_pins_default>;
+ pinctrl-1 = <&qspi_pins_sleep>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "mx66l51235l";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * MTD partition table. The ROM checks the first 512KiB for a
+ * valid file to boot(XIP).
+ */
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x00000000 0x000080000>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x00080000 0x00080000>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x00100000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x00110000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x00120000 0x00010000>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x00130000 0x0800000>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x00930000 0x36D0000>;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii";
+};
+
+&rtc {
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&cpu {
+ cpu0-supply = <&tps>;
+};
diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
new file mode 100644
index 0000000..fa4d1e3
--- /dev/null
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -0,0 +1,806 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
+
+/ {
+ model = "TI AM43x EPOS EVM";
+ compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
+
+ aliases {
+ display0 = &lcd0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ vmmcsd_fixed: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ lcd0: display {
+ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+ label = "lcd";
+
+ panel-timing {
+ clock-frequency = <33000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <210>;
+ hback-porch = <16>;
+ hsync-len = <30>;
+ vback-porch = <10>;
+ vfront-porch = <22>;
+ vsync-len = <13>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
+
+ matrix_keypad: matrix_keypad@0 {
+ compatible = "gpio-matrix-keypad";
+ debounce-delay-ms = <5>;
+ col-scan-delay-us = <2>;
+
+ row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
+ &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
+ &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
+ &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
+
+ col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
+ &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
+ &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
+ &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
+
+ linux,keymap = <0x00000201 /* P1 */
+ 0x01000204 /* P4 */
+ 0x02000207 /* P7 */
+ 0x0300020a /* NUMERIC_STAR */
+ 0x00010202 /* P2 */
+ 0x01010205 /* P5 */
+ 0x02010208 /* P8 */
+ 0x03010200 /* P0 */
+ 0x00020203 /* P3 */
+ 0x01020206 /* P6 */
+ 0x02020209 /* P9 */
+ 0x0302020b /* NUMERIC_POUND */
+ 0x00030067 /* UP */
+ 0x0103006a /* RIGHT */
+ 0x0203006c /* DOWN */
+ 0x03030069>; /* LEFT */
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
+ default-brightness-level = <8>;
+ };
+
+ sound0: sound@0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM43-EPOS-EVM";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MIC1LP", "Microphone Jack",
+ "MIC1RP", "Microphone Jack",
+ "MIC1LP", "MICBIAS",
+ "MIC1RP", "MICBIAS",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Speaker", "SPL",
+ "Speaker", "SPR";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ system-clock-frequency = <12000000>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3111>;
+ system-clock-frequency = <12000000>;
+ };
+ };
+};
+
+&am43xx_pinmux {
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
+ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
+ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
+ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
+ AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
+ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
+ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
+ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
+ AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
+ AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
+ AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
+ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ pixcir_ts_pins: pixcir_ts_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
+ >;
+ };
+
+ hdq_pins: pinmux_hdq_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
+ >;
+ };
+
+ dss_pins: dss_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+ AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+ AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+ AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+ AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+ AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+ AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+ >;
+ };
+
+ display_mux_pins: display_mux_pins {
+ pinctrl-single,pins = <
+ /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
+ AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ vpfe1_pins_default: vpfe1_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
+ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
+ AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
+ AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
+ AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
+ AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
+ AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
+ AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
+ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
+ AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
+ AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
+ AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
+ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
+ >;
+ };
+
+ vpfe1_pins_sleep: vpfe1_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+ >;
+ };
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
+ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
+ AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
+ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
+ >;
+ };
+
+ mcasp1_sleep_pins: mcasp1_sleep_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <16>;
+ phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rmii";
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+
+ tps65218: tps65218@24 {
+ reg = <0x24>;
+ compatible = "ti,tps65218";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dcdc1: regulator-dcdc1 {
+ compatible = "ti,tps65218-dcdc1";
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc2: regulator-dcdc2 {
+ compatible = "ti,tps65218-dcdc2";
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3: regulator-dcdc3 {
+ compatible = "ti,tps65218-dcdc3";
+ regulator-name = "vdcdc3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc4: regulator-dcdc4 {
+ compatible = "ti,tps65218-dcdc4";
+ regulator-name = "vdcdc4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc5: regulator-dcdc5 {
+ compatible = "ti,tps65218-dcdc5";
+ regulator-name = "v1_0bat";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ dcdc6: regulator-dcdc6 {
+ compatible = "ti,tps65218-dcdc6";
+ regulator-name = "v1_8bat";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo1: regulator-ldo1 {
+ compatible = "ti,tps65218-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+
+ at24@50 {
+ compatible = "at24,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+
+ pixcir_ts@5c {
+ compatible = "pixcir,pixcir_tangoc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pixcir_ts_pins>;
+ reg = <0x5c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+
+ attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+
+ tlv320aic3111: tlv320aic3111@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3111";
+ reg = <0x18>;
+ status = "okay";
+
+ ai31xx-micbias-vg = <MICBIAS_2_0V>;
+
+ /* Regulators */
+ HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ SPRVDD-supply = <&vbat>; /* vbat */
+ SPLVDD-supply = <&vbat>; /* vbat */
+ AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
+ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_mux_pins>;
+ status = "okay";
+
+ p1 {
+ /*
+ * SelLCDorHDMI selects between display and audio paths:
+ * Low: HDMI display with audio via HDMI
+ * High: LCD display with analog audio via aic3111 codec
+ */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SelLCDorHDMI";
+ };
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_flash_x8>;
+ ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+ nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-ecc-opt = "bch16";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+ gpmc,cs-wr-off-ns = <40>;
+ gpmc,adv-on-ns = <0>; /* cs-on-ns */
+ gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+ gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+ gpmc,we-on-ns = <0>; /* cs-on-ns */
+ gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+ gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
+ gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+ gpmc,access-ns = <30>; /* tCEA + 4*/
+ gpmc,rd-cycle-ns = <40>;
+ gpmc,wr-cycle-ns = <40>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x000C0000 0x00040000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00100000 0x00080000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x00180000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x00280000 0x00040000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x002C0000 0x00040000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00300000 0x00700000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x1f600000>;
+ };
+ };
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&tscadc {
+ status = "okay";
+
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb2_phy2 {
+ status = "okay";
+};
+
+&usb2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&qspi {
+ status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_default>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "mx66l51235l";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first 512KiB
+ * for a valid file to boot(XIP).
+ */
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x00000000 0x000080000>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x00080000 0x00080000>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x00100000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x00110000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x00120000 0x00010000>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x00130000 0x0800000>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x00930000 0x36D0000>;
+ };
+ };
+};
+
+&hdq {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdq_pins>;
+};
+
+&dss {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_pins>;
+
+ port {
+ dpi_out: endpoint@0 {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&vpfe1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&vpfe1_pins_default>;
+ pinctrl-1 = <&vpfe1_pins_sleep>;
+
+ port {
+ vpfe1_ep: endpoint {
+ /* remote-endpoint = <&sensor>; add once we have it */
+ ti,am437x-vpfe-interface = <0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_sleep_pins>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&synctimer_32kclk {
+ assigned-clocks = <&mux_synctimer32k_ck>;
+ assigned-clock-parents = <&clkdiv32k_ick>;
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..983e599
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 0000000..25dcdd2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A FREEDOM Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..76db36c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644
index 0000000..dde7134
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A QDS Board";
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi0;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..f683812
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644
index 0000000..bf407ae
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A RDB Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..546a87a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ compatible = "fsl,ls1012a";
+ interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1012a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x4000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <2>;
+ big-endian;
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
similarity index 83%
copy from arch/arm/dts/pine64.dts
copy to arch/arm/dts/meson-gxbb-odroidc2.dts
index dcc998f..653c2fa 100644
--- a/arch/arm/dts/pine64.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -1,5 +1,7 @@
/*
- * Copyright (c) 2016 ARM Ltd.
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -42,21 +44,26 @@
/dts-v1/;
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
+#include "meson-gxbb.dtsi"
/ {
- model = "Pine64";
- compatible = "pine64,pine64", "allwinner,a64";
+ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+ model = "Hardkernel ODROID-C2";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
chosen {
stdout-path = "serial0:115200n8";
};
- memory {
- reg = <0x40000000 0x20000000>;
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
};
};
+
+&uart_AO {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
new file mode 100644
index 0000000..832815d
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "amlogic,meson-gxbb";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cbus: cbus@c1100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc1100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+
+ uart_A: serial@84c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x084c0 0x0 0x14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@c4301000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xc4301000 0 0x1000>,
+ <0x0 0xc4302000 0 0x2000>,
+ <0x0 0xc4304000 0 0x2000>,
+ <0x0 0xc4306000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ aobus: aobus@c8100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+
+ uart_AO: serial@4c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x004c0 0x0 0x14>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ apb: apb@d0000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xd0000000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index 5aec1b8..072eaa6 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -146,6 +146,22 @@
status = "okay";
};
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 8d7446f..34073c9 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -111,7 +111,7 @@
};
&gmac {
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
new file mode 100644
index 0000000..f168e4f
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "samtec VIN|ING FPGA";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ udc0 = &usb0;
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "stm,m41t82";
+ reg = <0x68>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ flash0: n25q128@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128", "spi-flash";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+
+ flash1: n25q00@1 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00", "spi-flash";
+ reg = <1>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
similarity index 88%
rename from arch/arm/dts/pine64_common.dtsi
rename to arch/arm/dts/sun50i-a64-pine64-common.dtsi
index d968d76..d5a7249 100644
--- a/arch/arm/dts/pine64_common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -40,7 +40,23 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "a64.dtsi"
+#include "sun50i-a64.dtsi"
+
+/ {
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+};
&mmc0 {
pinctrl-names = "default";
@@ -57,20 +73,8 @@
status = "okay";
};
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_a>;
- status = "okay";
-};
-
-&uart4 {
+&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins>;
+ pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
similarity index 91%
rename from arch/arm/dts/pine64_plus.dts
rename to arch/arm/dts/sun50i-a64-pine64-plus.dts
index 5daff51..549dc15 100644
--- a/arch/arm/dts/pine64_plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -42,15 +42,11 @@
/dts-v1/;
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
+#include "sun50i-a64-pine64-common.dtsi"
/ {
model = "Pine64+";
- compatible = "pine64,pine64_plus", "allwinner,a64";
+ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
chosen {
stdout-path = "serial0:115200n8";
diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
similarity index 91%
rename from arch/arm/dts/pine64.dts
rename to arch/arm/dts/sun50i-a64-pine64.dts
index dcc998f..ebe029e 100644
--- a/arch/arm/dts/pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -42,15 +42,11 @@
/dts-v1/;
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
+#include "sun50i-a64-pine64-common.dtsi"
/ {
model = "Pine64";
- compatible = "pine64,pine64", "allwinner,a64";
+ compatible = "pine64,pine64", "allwinner,sun50i-a64";
chosen {
stdout-path = "serial0:115200n8";
diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
similarity index 63%
rename from arch/arm/dts/a64.dtsi
rename to arch/arm/dts/sun50i-a64.dtsi
index f3ad000..1bd436f 100644
--- a/arch/arm/dts/a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2016 ARM Ltd.
* based on the Allwinner H3 dtsi:
- * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -46,19 +46,10 @@
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
- compatible = "allwinner,a64";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -93,18 +84,29 @@
};
psci {
- compatible = "arm,psci-0.2", "arm,psci";
+ compatible = "arm,psci-0.2";
method = "smc";
- cpu_suspend = <0xc4000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0xc4000003>;
};
- memory {
+ memory {
device_type = "memory";
reg = <0x40000000 0>;
};
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@@ -136,7 +138,7 @@
clock-output-names = "osc32k";
};
- pll1: clk@01c20000 {
+ pll1: pll1_clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-pll1-clk";
reg = <0x01c20000 0x4>;
@@ -144,7 +146,7 @@
clock-output-names = "pll1";
};
- pll6: clk@01c20028 {
+ pll6: pll6_clk@1c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
@@ -161,23 +163,24 @@
clock-output-names = "pll6d2";
};
- /* dummy clock until pll6 can be reused */
- pll8: pll8_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1>;
- clock-output-names = "pll8";
+ pll7: pll7_clk@1c2002c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c2002c 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll7", "pll7x2";
};
- cpu: cpu_clk@01c20050 {
+ cpu: cpu_clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
clock-output-names = "cpu";
+ critical-clocks = <0>;
};
- axi: axi_clk@01c20050 {
+ axi: axi_clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20050 0x4>;
@@ -185,7 +188,7 @@
clock-output-names = "axi";
};
- ahb1: ahb1_clk@01c20054 {
+ ahb1: ahb1_clk@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
@@ -193,7 +196,7 @@
clock-output-names = "ahb1";
};
- ahb2: ahb2_clk@01c2005c {
+ ahb2: ahb2_clk@1c2005c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ahb2-clk";
reg = <0x01c2005c 0x4>;
@@ -201,7 +204,7 @@
clock-output-names = "ahb2";
};
- apb1: apb1_clk@01c20054 {
+ apb1: apb1_clk@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
@@ -209,7 +212,7 @@
clock-output-names = "apb1";
};
- apb2: apb2_clk@01c20058 {
+ apb2: apb2_clk@1c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
@@ -217,112 +220,112 @@
clock-output-names = "apb2";
};
- bus_gates: clk@01c20060 {
+ bus_gates: bus_gates_clk@1c20060 {
#clock-cells = <1>;
- compatible = "allwinner,a64-bus-gates-clk",
- "allwinner,sun8i-h3-bus-gates-clk";
+ compatible = "allwinner,sun50i-a64-bus-gates-clk",
+ "allwinner,sunxi-multi-bus-gates-clk";
reg = <0x01c20060 0x14>;
- clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
- clock-names = "ahb1", "ahb2", "apb1", "apb2";
- clock-indices = <1>,
- <5>, <6>, <8>,
- <9>, <10>, <13>,
- <14>, <17>, <18>,
- <19>, <20>,
- <21>, <23>,
- <24>, <25>,
- <28>, <29>,
- <32>, <35>,
- <36>, <37>,
- <40>, <43>,
- <44>, <52>, <53>,
- <54>, <64>,
- <65>, <69>, <72>,
- <76>, <77>, <78>,
- <96>, <97>, <98>,
- <101>,
- <112>, <113>,
- <114>, <115>,
- <116>, <135>;
- clock-output-names = "bus_mipidsi",
- "bus_ce", "bus_dma", "bus_mmc0",
- "bus_mmc1", "bus_mmc2", "bus_nand",
- "bus_sdram", "bus_gmac", "bus_ts",
- "bus_hstimer", "bus_spi0",
- "bus_spi1", "bus_otg",
- "bus_otg_ehci0", "bus_ehci0",
- "bus_otg_ohci0", "bus_ohci0",
- "bus_ve", "bus_lcd0",
- "bus_lcd1", "bus_deint",
- "bus_csi", "bus_hdmi",
- "bus_de", "bus_gpu", "bus_msgbox",
- "bus_spinlock", "bus_codec",
- "bus_spdif", "bus_pio", "bus_ths",
- "bus_i2s0", "bus_i2s1", "bus_i2s2",
- "bus_i2c0", "bus_i2c1", "bus_i2c2",
- "bus_scr",
- "bus_uart0", "bus_uart1",
- "bus_uart2", "bus_uart3",
- "bus_uart4", "bus_dbg";
+ ahb1_parent {
+ clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>,
+ <9>, <10>,
+ <13>, <14>,
+ <18>, <19>,
+ <20>, <21>,
+ <23>, <24>,
+ <25>, <28>,
+ <32>, <35>,
+ <36>, <37>,
+ <40>, <43>,
+ <44>, <52>,
+ <53>, <54>,
+ <135>;
+ clock-output-names = "bus_mipidsi", "bus_ce",
+ "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2",
+ "bus_nand", "bus_sdram",
+ "bus_ts", "bus_hstimer",
+ "bus_spi0", "bus_spi1",
+ "bus_otg", "bus_otg_ehci0",
+ "bus_ehci0", "bus_otg_ohci0",
+ "bus_ve", "bus_lcd0",
+ "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_hdmi",
+ "bus_de", "bus_gpu",
+ "bus_msgbox", "bus_spinlock",
+ "bus_dbg";
+ };
+ ahb2_parent {
+ clocks = <&ahb2>;
+ clock-indices = <17>, <29>;
+ clock-output-names = "bus_gmac", "bus_ohci0";
+ };
+ apb1_parent {
+ clocks = <&apb1>;
+ clock-indices = <64>, <65>,
+ <69>, <72>,
+ <76>, <77>,
+ <78>;
+ clock-output-names = "bus_codec", "bus_spdif",
+ "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1",
+ "bus_i2s2";
+ };
+ abp2_parent {
+ clocks = <&apb2>;
+ clock-indices = <96>, <97>,
+ <98>, <101>,
+ <112>, <113>,
+ <114>, <115>,
+ <116>;
+ clock-output-names = "bus_i2c0", "bus_i2c1",
+ "bus_i2c2", "bus_scr",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_uart4";
+ };
};
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
+ mmc0_clk: mmc0_clk@1c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
+ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+ clock-output-names = "mmc0";
+ };
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
+ mmc1_clk: mmc1_clk@1c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
+ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+ clock-output-names = "mmc1";
};
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
+ mmc2_clk: mmc2_clk@1c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
+ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+ clock-output-names = "mmc2";
};
};
- regulators {
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&bus_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&bus_gates 8>, <&mmc0_clk>,
+ <&mmc0_clk>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
resets = <&ahb_rst 8>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -331,17 +334,14 @@
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&bus_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&bus_gates 9>, <&mmc1_clk>,
+ <&mmc1_clk>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
resets = <&ahb_rst 9>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -350,17 +350,14 @@
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&bus_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&bus_gates 10>, <&mmc2_clk>,
+ <&mmc2_clk>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc",
+ "output", "sample";
resets = <&ahb_rst 10>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -369,8 +366,8 @@
#size-cells = <0>;
};
- pio: pinctrl@01c20800 {
- compatible = "allwinner,a64-pinctrl";
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,sun50i-a64-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
@@ -395,14 +392,28 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- uart1_pins: uart1@0 {
+ uart1_2pins: uart1_2@0 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_4pins: uart1_4@0 {
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ uart2_2pins: uart2_2@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
- uart2_pins: uart2@0 {
+ uart2_4pins: uart2_4@0 {
allwinner,pins = "PB0", "PB1", "PB2", "PB3";
allwinner,function = "uart2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -416,14 +427,28 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- uart3_pins_b: uart3@1 {
+ uart3_2pins_b: uart3_2@1 {
+ allwinner,pins = "PH4", "PH5";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_4pins_b: uart3_4@1 {
allwinner,pins = "PH4", "PH5", "PH6", "PH7";
allwinner,function = "uart3";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- uart4_pins: uart4@0 {
+ uart4_2pins: uart4_2@0 {
+ allwinner,pins = "PD2", "PD3";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_4pins: uart4_4@0 {
allwinner,pins = "PD2", "PD3", "PD4", "PD5";
allwinner,function = "uart4";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -460,27 +485,48 @@
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ i2c0_pins: i2c0_pins {
+ allwinner,pins = "PH0", "PH1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins: i2c1_pins {
+ allwinner,pins = "PH2", "PH3";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins: i2c2_pins {
+ allwinner,pins = "PE14", "PE15";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
- ahb_rst: reset@01c202c0 {
+ ahb_rst: reset@1c202c0 {
#reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-ahb1-reset";
+ compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202c0 0xc>;
};
- apb1_rst: reset@01c202d0 {
+ apb1_rst: reset@1c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
- apb2_rst: reset@01c202d8 {
+ apb2_rst: reset@1c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,11 +534,10 @@
reg-io-width = <4>;
clocks = <&bus_gates 112>;
resets = <&apb2_rst 16>;
- reset-names = "apb2";
status = "disabled";
};
- uart1: serial@01c28400 {
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,11 +545,10 @@
reg-io-width = <4>;
clocks = <&bus_gates 113>;
resets = <&apb2_rst 17>;
- reset-names = "apb2";
status = "disabled";
};
- uart2: serial@01c28800 {
+ uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -512,11 +556,10 @@
reg-io-width = <4>;
clocks = <&bus_gates 114>;
resets = <&apb2_rst 18>;
- reset-names = "apb2";
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -524,11 +567,10 @@
reg-io-width = <4>;
clocks = <&bus_gates 115>;
resets = <&apb2_rst 19>;
- reset-names = "apb2";
status = "disabled";
};
- uart4: serial@01c29000 {
+ uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -536,29 +578,47 @@
reg-io-width = <4>;
clocks = <&bus_gates 116>;
resets = <&apb2_rst 20>;
- reset-names = "apb2";
status = "disabled";
};
- rtc: rtc@01f00000 {
+ rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- };
- gic: interrupt-controller@{
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 96>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- reg = <0x01C81000 0x1000>,
- <0x01C82000 0x2000>,
- <0x01C84000 0x2000>,
- <0x01C86000 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 97>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 98>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts
new file mode 100644
index 0000000..5f29ee4
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "tegra186.dtsi"
+
+/ {
+ model = "NVIDIA P2771-0000";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ sdhci0 = "/sdhci@3460000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x60000000>;
+ };
+
+ sdhci@3460000 {
+ status = "okay";
+ bus-width = <8>;
+ };
+};
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
new file mode 100644
index 0000000..18b6a26
--- /dev/null
+++ b/arch/arm/dts/tegra186.dtsi
@@ -0,0 +1,56 @@
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "nvidia,tegra186";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uarta: serial@3100000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03100000 0x0 0x10000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sdhci@3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x200>;
+ interrupts = <GIC_SPI 31 0x04>;
+ status = "disabled";
+ };
+
+ gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index 88e7f53..b148e9f 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -49,6 +49,18 @@
status = "okay";
};
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
/* for U-Boot only */
/ {
soc {
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index 7d498ce..e485f90 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -190,6 +190,42 @@
reg = <0x59801000 0x400>;
};
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 243 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio 3>, <&mio 6>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 244 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio 4>, <&mio 6>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 245 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio 5>, <&mio 6>;
+ };
+
+ mio: mioctrl@5b3e0000 {
+ compatible = "socionext,ph1-ld11-mioctrl";
+ reg = <0x5b3e0000 0x800>;
+ #clock-cells = <1>;
+ };
+
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld11-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 0000000..03f1ad7
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,212 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm018-dc4";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ ethernet2 = &gem2;
+ ethernet3 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+ xlnx,overfetch; /* for testing purpose */
+ xlnx,ratectrl = <0>; /* for testing purpose */
+ xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+ xlnx,ratectrl = <100>; /* for testing purpose */
+ xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&xlnx_dp {
+ status = "okay";
+};
+
+&xlnx_dpdma {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ local-mac-address = [00 0a 35 00 02 90];
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ local-mac-address = [00 0a 35 00 02 91];
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy7>;
+};
+
+&gem2 {
+ status = "okay";
+ local-mac-address = [00 0a 35 00 02 92];
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy3>;
+};
+
+&gem3 {
+ status = "okay";
+ local-mac-address = [00 0a 35 00 02 93];
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy8>;
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
new file mode 100644
index 0000000..a5af012
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -0,0 +1,43 @@
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG 0x0
+#define CLK_SYNTHESIZER_XCSEL 0x05
+#define CLK_SYNTHESIZER_MUX_REG 0x14
+#define CLK_SYNTHESIZER_PDIV2_REG 0x16
+#define CLK_SYNTHESIZER_PDIV3_REG 0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE 0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ * for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+ u32 id;
+ u32 capacitor;
+ u32 mux;
+ u32 pdiv2;
+ u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 97bbfe2..43e122e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -54,6 +54,21 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz 0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
+#define MT41J128MJT125_RD_DQS_400MHz 0x3A
+#define MT41J128MJT125_WR_DQS_400MHz 0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
+
/* Micron MT41K128M16JT-187E */
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
new file mode 100644
index 0000000..7e72882
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK \
+ .word 0xbabeface; \
+ .word _end - _start
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index fbdaa52..44fe0c0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -14,8 +14,11 @@
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
+
+#ifndef CONFIG_LS1012A
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#endif
/*
* Reserve secure memory
@@ -200,6 +203,32 @@
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
+
+#define GICD_BASE 0x01401000
+#define GICC_BASE 0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..1cebe2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -14,6 +14,7 @@
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
CPU_TYPE_ENTRY(LS1023, LS1023, 2),
CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+ CPU_TYPE_ENTRY(LS1012, LS1012, 1),
};
#ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index f71c2c1..487cba8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -55,7 +55,7 @@
FSL_SRDS_1 = 0,
FSL_SRDS_2 = 1,
};
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
NONE = 0,
PCIE1,
@@ -134,6 +134,7 @@
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
+ TX_CLK,
SERDES_PRCTL_COUNT
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..e98e055 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -60,7 +60,11 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE 0xC0000
+#else
#define PCIE_LUT_BASE 0x10000
+#endif
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index a3ccdb0..db76066 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -69,7 +69,12 @@
CSU_CSLX_IIC4 = 77,
CSU_CSLX_WDT4,
CSU_CSLX_WDT3,
+ CSU_CSLX_ESDHC2 = 80,
CSU_CSLX_WDT5 = 81,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
CSU_CSLX_FTM2 = 86,
CSU_CSLX_FTM1,
CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@
{CSU_CSLX_IIC4, CSU_ALL_RW},
{CSU_CSLX_WDT4, CSU_ALL_RW},
{CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
{CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
{CSU_CSLX_FTM2, CSU_ALL_RW},
{CSU_CSLX_FTM1, CSU_ALL_RW},
{CSU_CSLX_FTM4, CSU_ALL_RW},
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 831d817..02ecc62 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -41,6 +41,7 @@
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1012 0x870400
#define SVR_LS1043 0x879200
#define SVR_LS1023 0x879208
#define SVR_LS2045 0x870120
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
new file mode 100644
index 0000000..f90f632
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GXBB_H__
+#define __GXBB_H__
+
+#define GXBB_PERIPHS_BASE 0xc8834400
+#define GXBB_HIU_BASE 0xc883c000
+#define GXBB_ETH_BASE 0xc9410000
+
+/* Peripherals registers */
+#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
+#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
+#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
+
+/* Pinmux registers 0 to 12 */
+#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
+
+#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
+#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define GXBB_ETH_REG_0_CLK_EN BIT(12)
+
+/* HIU registers */
+#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
+
+#define GXBB_GCLK_MPEG_1_ETH BIT(3)
+
+#endif /* __GXBB_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
new file mode 100644
index 0000000..225438d
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 53cc2b0..e8aa786 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -59,13 +59,8 @@
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-/* device type */
-#define DEVICE_MASK (0x7 << 8)
+/* boot pin mask */
#define SYSBOOT_MASK 0x1F
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
/* device speed */
#define SKUID_CLK_MASK 0xf
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 38d50d6..551c927 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -239,19 +239,22 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752 1100
-#define VDD_EVE_DRA752 1060
-#define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA752 1060
-#define VDD_IVA_DRA752 1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM 1150
+#define VDD_CORE_DRA7_NOM 1150
+#define VDD_EVE_DRA7_NOM 1060
+#define VDD_GPU_DRA7_NOM 1060
+#define VDD_IVA_DRA7_NOM 1060
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x 1100
-#define VDD_EVE_DRA72x 1060
-#define VDD_GPU_DRA72x 1060
-#define VDD_CORE_DRA72x 1060
-#define VDD_IVA_DRA72x 1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD 1150
+#define VDD_GPU_DRA7_OD 1150
+#define VDD_IVA_DRA7_OD 1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH 1250
+#define VDD_GPU_DRA7_HIGH 1250
+#define VDD_IVA_DRA7_HIGH 1250
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
@@ -283,6 +286,20 @@
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
+
+#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM
+#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM
+
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 804266a..ab0e7fa 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -51,6 +51,7 @@
void setup_early_clocks(void);
void prcm_init(void);
void do_board_detect(void);
+void vcores_init(void);
void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d2690c7..8a8ca9c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@
SDIO0_DIV_MASK = 0x3f,
};
+/* CRU_CLKSEL21_CON */
+enum {
+ MAC_DIV_CON_SHIFT = 0xf,
+ MAC_DIV_CON_MASK = 0x1f,
+
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK = 1,
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+ EMAC_PLL_SHIFT = 0,
+ EMAC_PLL_MASK = 0x3,
+ EMAC_PLL_SELECT_NEW = 0x0,
+ EMAC_PLL_SELECT_CODEC = 0x1,
+ EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 0117a17..aaffd19 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -718,6 +718,40 @@
MSCH0_MAINPARTIALPOP_MASK = 1,
};
+/* GRF_SOC_CON1 */
+enum {
+ RMII_MODE_SHIFT = 0xe,
+ RMII_MODE_MASK = 1,
+ RMII_MODE = 1,
+
+ GMAC_CLK_SEL_SHIFT = 0xc,
+ GMAC_CLK_SEL_MASK = 3,
+ GMAC_CLK_SEL_125M = 0,
+ GMAC_CLK_SEL_25M = 0x3,
+ GMAC_CLK_SEL_2_5M = 0x2,
+
+ RMII_CLK_SEL_SHIFT = 0xb,
+ RMII_CLK_SEL_MASK = 1,
+ RMII_CLK_SEL_2_5M = 0,
+ RMII_CLK_SEL_25M,
+
+ GMAC_SPEED_SHIFT = 0xa,
+ GMAC_SPEED_MASK = 1,
+ GMAC_SPEED_10M = 0,
+ GMAC_SPEED_100M,
+
+ GMAC_FLOWCTRL_SHIFT = 0x9,
+ GMAC_FLOWCTRL_MASK = 1,
+
+ GMAC_PHY_INTF_SEL_SHIFT = 0x6,
+ GMAC_PHY_INTF_SEL_MASK = 0x7,
+ GMAC_PHY_INTF_SEL_RGMII = 0x1,
+ GMAC_PHY_INTF_SEL_RMII = 0x4,
+
+ HOST_REMAP_SHIFT = 0x5,
+ HOST_REMAP_MASK = 1
+};
+
/* GRF_SOC_CON2 */
enum {
UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
@@ -765,4 +799,23 @@
PWM_PWM = 0,
};
+/* GRF_SOC_CON3 */
+enum {
+ RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+ RXCLK_DLY_ENA_GMAC_MASK = 1,
+ RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RXCLK_DLY_ENA_GMAC_ENABLE,
+
+ TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+ TXCLK_DLY_ENA_GMAC_MASK = 1,
+ TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ TXCLK_DLY_ENA_GMAC_ENABLE,
+
+ CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ CLK_RX_DL_CFG_GMAC_MASK = 0x7f,
+
+ CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ CLK_TX_DL_CFG_GMAC_MASK = 0x7f,
+};
+
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
new file mode 100644
index 0000000..ea5675e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -0,0 +1,14 @@
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* reserve space for BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK \
+ .space 1532
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index ca9a4f9..a0f33b0 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -18,6 +18,10 @@
#define SPL_ADDR 0x0
#endif
+/* The low 8-bits of the 'boot_media' field in the SPL header */
+#define SUNXI_BOOTED_FROM_MMC0 0
+#define SUNXI_BOOTED_FROM_SPI 3
+
/* boot head definition from sun4i boot code */
struct boot_file_head {
uint32_t b_instruction; /* one intruction jumping to real code */
@@ -45,7 +49,9 @@
uint8_t spl_signature[4];
};
uint32_t fel_script_address;
- uint32_t reserved; /* padding, align to 32 bytes */
+ uint32_t reserved1[3];
+ uint32_t boot_media; /* written here by the boot ROM */
+ uint32_t reserved2[5]; /* padding, align to 64 bytes */
};
#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index daf5698..db60864 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -6,6 +6,8 @@
#ifndef _TEGRA_GPIO_H_
#define _TEGRA_GPIO_H_
+#include <dt-bindings/gpio/tegra-gpio.h>
+
#define TEGRA_GPIOS_PER_PORT 8
#define TEGRA_PORTS_PER_BANK 4
#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a20bdaa..75e56c4 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -134,7 +134,9 @@
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
+#ifndef CONFIG_TEGRA186
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
+#endif
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
index 1a6dcb8..ba748a5 100644
--- a/arch/arm/include/asm/arch-tegra124/gpio.h
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -41,263 +41,4 @@
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7,
- GPIO_PFF0, /* pin 248 */
- GPIO_PFF1,
- GPIO_PFF2,
- GPIO_PFF3,
- GPIO_PFF4,
- GPIO_PFF5,
- GPIO_PFF6,
- GPIO_PFF7, /* pin 255 */
-};
-
#endif /* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000..aaecfc7
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000..8031f23
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */
+#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE 0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
index b40b1ff..af301e7 100644
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -33,231 +33,4 @@
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7, /* pin 223 */
-};
-
#endif /* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
index 71af423..389d5b6 100644
--- a/arch/arm/include/asm/arch-tegra210/gpio.h
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -41,263 +41,4 @@
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7,
- GPIO_PFF0, /* pin 248 */
- GPIO_PFF1,
- GPIO_PFF2,
- GPIO_PFF3,
- GPIO_PFF4,
- GPIO_PFF5,
- GPIO_PFF6,
- GPIO_PFF7, /* pin 255 */
-};
-
#endif /* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
index d2c6c78..e384327 100644
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -40,255 +40,4 @@
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-enum gpio_pin {
- GPIO_PA0 = 0, /* pin 0 */
- GPIO_PA1,
- GPIO_PA2,
- GPIO_PA3,
- GPIO_PA4,
- GPIO_PA5,
- GPIO_PA6,
- GPIO_PA7,
- GPIO_PB0, /* pin 8 */
- GPIO_PB1,
- GPIO_PB2,
- GPIO_PB3,
- GPIO_PB4,
- GPIO_PB5,
- GPIO_PB6,
- GPIO_PB7,
- GPIO_PC0, /* pin 16 */
- GPIO_PC1,
- GPIO_PC2,
- GPIO_PC3,
- GPIO_PC4,
- GPIO_PC5,
- GPIO_PC6,
- GPIO_PC7,
- GPIO_PD0, /* pin 24 */
- GPIO_PD1,
- GPIO_PD2,
- GPIO_PD3,
- GPIO_PD4,
- GPIO_PD5,
- GPIO_PD6,
- GPIO_PD7,
- GPIO_PE0, /* pin 32 */
- GPIO_PE1,
- GPIO_PE2,
- GPIO_PE3,
- GPIO_PE4,
- GPIO_PE5,
- GPIO_PE6,
- GPIO_PE7,
- GPIO_PF0, /* pin 40 */
- GPIO_PF1,
- GPIO_PF2,
- GPIO_PF3,
- GPIO_PF4,
- GPIO_PF5,
- GPIO_PF6,
- GPIO_PF7,
- GPIO_PG0, /* pin 48 */
- GPIO_PG1,
- GPIO_PG2,
- GPIO_PG3,
- GPIO_PG4,
- GPIO_PG5,
- GPIO_PG6,
- GPIO_PG7,
- GPIO_PH0, /* pin 56 */
- GPIO_PH1,
- GPIO_PH2,
- GPIO_PH3,
- GPIO_PH4,
- GPIO_PH5,
- GPIO_PH6,
- GPIO_PH7,
- GPIO_PI0, /* pin 64 */
- GPIO_PI1,
- GPIO_PI2,
- GPIO_PI3,
- GPIO_PI4,
- GPIO_PI5,
- GPIO_PI6,
- GPIO_PI7,
- GPIO_PJ0, /* pin 72 */
- GPIO_PJ1,
- GPIO_PJ2,
- GPIO_PJ3,
- GPIO_PJ4,
- GPIO_PJ5,
- GPIO_PJ6,
- GPIO_PJ7,
- GPIO_PK0, /* pin 80 */
- GPIO_PK1,
- GPIO_PK2,
- GPIO_PK3,
- GPIO_PK4,
- GPIO_PK5,
- GPIO_PK6,
- GPIO_PK7,
- GPIO_PL0, /* pin 88 */
- GPIO_PL1,
- GPIO_PL2,
- GPIO_PL3,
- GPIO_PL4,
- GPIO_PL5,
- GPIO_PL6,
- GPIO_PL7,
- GPIO_PM0, /* pin 96 */
- GPIO_PM1,
- GPIO_PM2,
- GPIO_PM3,
- GPIO_PM4,
- GPIO_PM5,
- GPIO_PM6,
- GPIO_PM7,
- GPIO_PN0, /* pin 104 */
- GPIO_PN1,
- GPIO_PN2,
- GPIO_PN3,
- GPIO_PN4,
- GPIO_PN5,
- GPIO_PN6,
- GPIO_PN7,
- GPIO_PO0, /* pin 112 */
- GPIO_PO1,
- GPIO_PO2,
- GPIO_PO3,
- GPIO_PO4,
- GPIO_PO5,
- GPIO_PO6,
- GPIO_PO7,
- GPIO_PP0, /* pin 120 */
- GPIO_PP1,
- GPIO_PP2,
- GPIO_PP3,
- GPIO_PP4,
- GPIO_PP5,
- GPIO_PP6,
- GPIO_PP7,
- GPIO_PQ0, /* pin 128 */
- GPIO_PQ1,
- GPIO_PQ2,
- GPIO_PQ3,
- GPIO_PQ4,
- GPIO_PQ5,
- GPIO_PQ6,
- GPIO_PQ7,
- GPIO_PR0, /* pin 136 */
- GPIO_PR1,
- GPIO_PR2,
- GPIO_PR3,
- GPIO_PR4,
- GPIO_PR5,
- GPIO_PR6,
- GPIO_PR7,
- GPIO_PS0, /* pin 144 */
- GPIO_PS1,
- GPIO_PS2,
- GPIO_PS3,
- GPIO_PS4,
- GPIO_PS5,
- GPIO_PS6,
- GPIO_PS7,
- GPIO_PT0, /* pin 152 */
- GPIO_PT1,
- GPIO_PT2,
- GPIO_PT3,
- GPIO_PT4,
- GPIO_PT5,
- GPIO_PT6,
- GPIO_PT7,
- GPIO_PU0, /* pin 160 */
- GPIO_PU1,
- GPIO_PU2,
- GPIO_PU3,
- GPIO_PU4,
- GPIO_PU5,
- GPIO_PU6,
- GPIO_PU7,
- GPIO_PV0, /* pin 168 */
- GPIO_PV1,
- GPIO_PV2,
- GPIO_PV3,
- GPIO_PV4,
- GPIO_PV5,
- GPIO_PV6,
- GPIO_PV7,
- GPIO_PW0, /* pin 176 */
- GPIO_PW1,
- GPIO_PW2,
- GPIO_PW3,
- GPIO_PW4,
- GPIO_PW5,
- GPIO_PW6,
- GPIO_PW7,
- GPIO_PX0, /* pin 184 */
- GPIO_PX1,
- GPIO_PX2,
- GPIO_PX3,
- GPIO_PX4,
- GPIO_PX5,
- GPIO_PX6,
- GPIO_PX7,
- GPIO_PY0, /* pin 192 */
- GPIO_PY1,
- GPIO_PY2,
- GPIO_PY3,
- GPIO_PY4,
- GPIO_PY5,
- GPIO_PY6,
- GPIO_PY7,
- GPIO_PZ0, /* pin 200 */
- GPIO_PZ1,
- GPIO_PZ2,
- GPIO_PZ3,
- GPIO_PZ4,
- GPIO_PZ5,
- GPIO_PZ6,
- GPIO_PZ7,
- GPIO_PAA0, /* pin 208 */
- GPIO_PAA1,
- GPIO_PAA2,
- GPIO_PAA3,
- GPIO_PAA4,
- GPIO_PAA5,
- GPIO_PAA6,
- GPIO_PAA7,
- GPIO_PBB0, /* pin 216 */
- GPIO_PBB1,
- GPIO_PBB2,
- GPIO_PBB3,
- GPIO_PBB4,
- GPIO_PBB5,
- GPIO_PBB6,
- GPIO_PBB7,
- GPIO_PCC0, /* pin 224 */
- GPIO_PCC1,
- GPIO_PCC2,
- GPIO_PCC3,
- GPIO_PCC4,
- GPIO_PCC5,
- GPIO_PCC6,
- GPIO_PCC7,
- GPIO_PDD0, /* pin 232 */
- GPIO_PDD1,
- GPIO_PDD2,
- GPIO_PDD3,
- GPIO_PDD4,
- GPIO_PDD5,
- GPIO_PDD6,
- GPIO_PDD7,
- GPIO_PEE0, /* pin 240 */
- GPIO_PEE1,
- GPIO_PEE2,
- GPIO_PEE3,
- GPIO_PEE4,
- GPIO_PEE5,
- GPIO_PEE6,
- GPIO_PEE7, /* pin 247 */
-};
-
#endif /* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 11b80fb..ae1e42f 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -15,6 +15,7 @@
*/
#include <config.h>
+#include <asm/unified.h>
/*
* Endian independent macros for shifting bytes within registers.
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8fb05e1..07f3848 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
+ u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
@@ -717,6 +718,17 @@
#define DRA722_ES2_0 0x07220200
/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+
+/*
* SRAM scratch space entries
*/
#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606..3704f07 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,7 +18,7 @@
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
-/* PSCI interface */
+/* PSCI 0.1 interface */
#define ARM_PSCI_FN_BASE 0x95c1ba5e
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
@@ -32,6 +32,21 @@
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE 0x84000000
+#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
new file mode 100644
index 0000000..b8b85b7
--- /dev/null
+++ b/arch/arm/include/asm/setjmp.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2016
+ * Alexander Graf <agraf@suse.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_ 1
+
+struct jmp_buf_data {
+ ulong target;
+ ulong regs[5];
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+static inline int setjmp(jmp_buf jmp)
+{
+ long r = 0;
+
+#ifdef CONFIG_ARM64
+ asm volatile(
+ "adr x1, jmp_target\n"
+ "str x1, %1\n"
+ "stp x26, x27, %2\n"
+ "stp x28, x29, %3\n"
+ "mov x1, sp\n"
+ "str x1, %4\n"
+ "b 2f\n"
+ "jmp_target: "
+ "mov %0, #1\n"
+ "2:\n"
+ : "+r" (r), "=m" (jmp->target),
+ "=m" (jmp->regs[0]), "=m" (jmp->regs[2]),
+ "=m" (jmp->regs[4])
+ :
+ : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22",
+ "x23", "x24", "x25", /* x26, x27, x28, x29, sp */
+ "x30", "cc", "memory");
+#else
+ asm volatile(
+#ifdef CONFIG_SYS_THUMB_BUILD
+ "adr r0, jmp_target + 1\n"
+#else
+ "adr r0, jmp_target\n"
+#endif
+ "mov r1, %1\n"
+ "mov r2, sp\n"
+ "stm r1, {r0, r2, r4, r5, r6, r7}\n"
+ "b 2f\n"
+ "jmp_target: "
+ "mov %0, #1\n"
+ "2:\n"
+ : "+l" (r)
+ : "l" (&jmp->target)
+ : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
+ "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
+ "cc", "memory");
+#endif
+
+printf("%s:%d target=%#lx\n", __func__, __LINE__, jmp->target);
+
+ return r;
+}
+
+static inline __noreturn void longjmp(jmp_buf jmp)
+{
+#ifdef CONFIG_ARM64
+ asm volatile(
+ "ldr x0, %0\n"
+ "ldr x1, %3\n"
+ "mov sp, x1\n"
+ "ldp x26, x27, %1\n"
+ "ldp x28, x25, %2\n"
+ "mov x29, x25\n"
+ "br x0\n"
+ :
+ : "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]),
+ "m" (jmp->regs[4])
+ : "x0", "x1", "x25", "x26", "x27", "x28");
+#else
+ asm volatile(
+ "mov r1, %0\n"
+ "ldm r1, {r0, r2, r4, r5, r6, r7}\n"
+ "mov sp, r2\n"
+ "bx r0\n"
+ :
+ : "l" (&jmp->target)
+ : "r1");
+#endif
+
+ while (1) { }
+}
+
+
+#endif /* _SETJMP_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9ae890a..2bdc0be 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -128,6 +128,8 @@
*/
void smc_call(struct pt_regs *args);
+void __noreturn psci_system_reset(bool smc);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index 11407be..f343ac2 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -35,10 +35,12 @@
uint32_t sdrcr;
union {
uint32_t abncr[4];
- uint32_t ab1cr;
- uint32_t ab2cr;
- uint32_t ab3cr;
- uint32_t ab4cr;
+ struct {
+ uint32_t ab1cr;
+ uint32_t ab2cr;
+ uint32_t ab3cr;
+ uint32_t ab4cr;
+ };
};
uint32_t sdtimr;
uint32_t ddrsr;
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 0000000..1b26002
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,129 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+ .syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...) x
+#else
+#define AR_CLASS(x...) x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...) x
+#ifdef __ASSEMBLY__
+#define W(instr) instr.w
+#else
+#define WASM(instr) #instr ".w"
+#endif
+
+#else /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE 0
+
+#define ARM(x...) x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr) instr
+#else
+#define WASM(instr) #instr
+#endif
+
+#endif /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+ .macro it, cond
+ .endm
+ .macro itt, cond
+ .endm
+ .macro ite, cond
+ .endm
+ .macro ittt, cond
+ .endm
+ .macro itte, cond
+ .endm
+ .macro itet, cond
+ .endm
+ .macro itee, cond
+ .endm
+ .macro itttt, cond
+ .endm
+ .macro ittte, cond
+ .endm
+ .macro ittet, cond
+ .endm
+ .macro ittee, cond
+ .endm
+ .macro itett, cond
+ .endm
+ .macro itete, cond
+ .endm
+ .macro iteet, cond
+ .endm
+ .macro iteee, cond
+ .endm
+#else /* !__ASSEMBLY__ */
+__asm__(
+" .macro it, cond\n"
+" .endm\n"
+" .macro itt, cond\n"
+" .endm\n"
+" .macro ite, cond\n"
+" .endm\n"
+" .macro ittt, cond\n"
+" .endm\n"
+" .macro itte, cond\n"
+" .endm\n"
+" .macro itet, cond\n"
+" .endm\n"
+" .macro itee, cond\n"
+" .endm\n"
+" .macro itttt, cond\n"
+" .endm\n"
+" .macro ittte, cond\n"
+" .endm\n"
+" .macro ittet, cond\n"
+" .endm\n"
+" .macro ittee, cond\n"
+" .endm\n"
+" .macro itett, cond\n"
+" .endm\n"
+" .macro itete, cond\n"
+" .endm\n"
+" .macro iteet, cond\n"
+" .endm\n"
+" .macro iteee, cond\n"
+" .endm\n");
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_ASM_UNIFIED */
+
+#endif /* !__ASM_UNIFIED_H */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 7a0fb58..0e05e87 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
- _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
- _uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+ lib1funcs.o uldivmod.o div0.o \
+ div64.o muldi3.o
ifdef CONFIG_CPU_V7M
obj-y += vectors_m.o crt0.o
@@ -46,7 +46,7 @@
else
obj-y += interrupts.o
endif
-ifndef CONFIG_RESET
+ifndef CONFIG_SYSRESET
obj-y += reset.o
endif
@@ -62,9 +62,17 @@
extra-y += eabi_compat.o
endif
+asflags-y += -DCONFIG_ARM_ASM_UNIFIED
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+asflags-y += -D__LINUX_ARM_ARCH__=4
+else
+asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
+asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
ifndef CONFIG_HAS_THUMB2
# for C files, just apend -marm, which will override previous -mthumb*
@@ -82,6 +90,5 @@
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
-
endif
endif
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S
deleted file mode 100644
index c463c68..0000000
--- a/arch/arm/lib/_divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \curbit, \divisor
- clz \result, \dividend
- sub \result, \curbit, \result
- mov \curbit, #1
- mov \divisor, \divisor, lsl \result
- mov \curbit, \curbit, lsl \result
- mov \result, #0
-
-#else
-
- @ Initially shift the divisor left 3 bits if possible,
- @ set curbit accordingly. This allows for curbit to be located
- @ at the left end of each 4 bit nibbles in the division loop
- @ to save one loop in most cases.
- tst \divisor, #0xe0000000
- moveq \divisor, \divisor, lsl #3
- moveq \curbit, #8
- movne \curbit, #1
-
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
-1: cmp \divisor, #0x10000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #4
- movlo \curbit, \curbit, lsl #4
- blo 1b
-
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
-1: cmp \divisor, #0x80000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #1
- movlo \curbit, \curbit, lsl #1
- blo 1b
-
- mov \result, #0
-
-#endif
-
- @ Division loop
-1: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- orrhs \result, \result, \curbit
- cmp \dividend, \divisor, lsr #1
- subhs \dividend, \dividend, \divisor, lsr #1
- orrhs \result, \result, \curbit, lsr #1
- cmp \dividend, \divisor, lsr #2
- subhs \dividend, \dividend, \divisor, lsr #2
- orrhs \result, \result, \curbit, lsr #2
- cmp \dividend, \divisor, lsr #3
- subhs \dividend, \dividend, \divisor, lsr #3
- orrhs \result, \result, \curbit, lsr #3
- cmp \dividend, #0 @ Early termination?
- movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
- movne \divisor, \divisor, lsr #4
- bne 1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \order, \divisor
- rsb \order, \order, #31
-
-#else
-
- cmp \divisor, #(1 << 16)
- movhs \divisor, \divisor, lsr #16
- movhs \order, #16
- movlo \order, #0
-
- cmp \divisor, #(1 << 8)
- movhs \divisor, \divisor, lsr #8
- addhs \order, \order, #8
-
- cmp \divisor, #(1 << 4)
- movhs \divisor, \divisor, lsr #4
- addhs \order, \order, #4
-
- cmp \divisor, #(1 << 2)
- addhi \order, \order, #3
- addls \order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
- .align 5
-.globl __divsi3
-__divsi3:
-ENTRY(__aeabi_idiv)
- cmp r1, #0
- eor ip, r0, r1 @ save the sign of the result.
- beq Ldiv0
- rsbmi r1, r1, #0 @ loops below use unsigned.
- subs r2, r1, #1 @ division by 1 or -1 ?
- beq 10f
- movs r3, r0
- rsbmi r3, r0, #0 @ positive dividend value
- cmp r3, r1
- bls 11f
- tst r1, r2 @ divisor is power of 2 ?
- beq 12f
-
- ARM_DIV_BODY r3, r1, r0, r2
-
- cmp ip, #0
- rsbmi r0, r0, #0
- mov pc, lr
-
-10: teq ip, r0 @ same sign ?
- rsbmi r0, r0, #0
- mov pc, lr
-
-11: movlo r0, #0
- moveq r0, ip, asr #31
- orreq r0, r0, #1
- mov pc, lr
-
-12: ARM_DIV2_ORDER r1, r2
-
- cmp ip, #0
- mov r0, r3, lsr r2
- rsbmi r0, r0, #0
- mov pc, lr
-
-Ldiv0:
-
- str lr, [sp, #-4]!
- bl __div0
- mov r0, #0 @ About as wrong as it could be.
- ldr pc, [sp], #4
-ENDPROC(__aeabi_idiv)
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S
deleted file mode 100644
index c5e1c22..0000000
--- a/arch/arm/lib/_modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
- clz \order, \divisor
- clz \spare, \dividend
- sub \order, \order, \spare
- mov \divisor, \divisor, lsl \order
-
-#else
-
- mov \order, #0
-
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
-1: cmp \divisor, #0x10000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #4
- addlo \order, \order, #4
- blo 1b
-
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
-1: cmp \divisor, #0x80000000
- cmplo \divisor, \dividend
- movlo \divisor, \divisor, lsl #1
- addlo \order, \order, #1
- blo 1b
-
-#endif
-
- @ Perform all needed substractions to keep only the reminder.
- @ Do comparisons in batch of 4 first.
- subs \order, \order, #3 @ yes, 3 is intended here
- blt 2f
-
-1: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- cmp \dividend, \divisor, lsr #1
- subhs \dividend, \dividend, \divisor, lsr #1
- cmp \dividend, \divisor, lsr #2
- subhs \dividend, \dividend, \divisor, lsr #2
- cmp \dividend, \divisor, lsr #3
- subhs \dividend, \dividend, \divisor, lsr #3
- cmp \dividend, #1
- mov \divisor, \divisor, lsr #4
- subges \order, \order, #4
- bge 1b
-
- tst \order, #3
- teqne \dividend, #0
- beq 5f
-
- @ Either 1, 2 or 3 comparison/substractions are left.
-2: cmn \order, #2
- blt 4f
- beq 3f
- cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- mov \divisor, \divisor, lsr #1
-3: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
- mov \divisor, \divisor, lsr #1
-4: cmp \dividend, \divisor
- subhs \dividend, \dividend, \divisor
-5:
-.endm
-
- .align 5
-ENTRY(__modsi3)
- cmp r1, #0
- beq Ldiv0
- rsbmi r1, r1, #0 @ loops below use unsigned.
- movs ip, r0 @ preserve sign of dividend
- rsbmi r0, r0, #0 @ if negative make positive
- subs r2, r1, #1 @ compare divisor with 1
- cmpne r0, r1 @ compare dividend with divisor
- moveq r0, #0
- tsthi r1, r2 @ see if divisor is power of 2
- andeq r0, r0, r2
- bls 10f
-
- ARM_MOD_BODY r0, r1, r2, r3
-
-10: cmp ip, #0
- rsbmi r0, r0, #0
- mov pc, lr
-ENDPROC(__modsi3)
-
-Ldiv0:
-
- str lr, [sp, #-4]!
- bl __div0
- mov r0, #0 @ About as wrong as it could be.
- ldr pc, [sp], #4
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S
deleted file mode 100644
index 3b653be..0000000
--- a/arch/arm/lib/_udivsi3.S
+++ /dev/null
@@ -1,95 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend .req r0
-divisor .req r1
-result .req r2
-curbit .req r3
-/* ip .req r12 */
-/* sp .req r13 */
-/* lr .req r14 */
-/* pc .req r15 */
- .text
- .globl __udivsi3
- .type __udivsi3 ,function
- .globl __aeabi_uidiv
- .type __aeabi_uidiv ,function
- .align 0
- __udivsi3:
- __aeabi_uidiv:
- cmp divisor, #0
- beq Ldiv0
- mov curbit, #1
- mov result, #0
- cmp dividend, divisor
- bcc Lgot_result
-Loop1:
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
- cmp divisor, #0x10000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #4
- movcc curbit, curbit, lsl #4
- bcc Loop1
-Lbignum:
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
- cmp divisor, #0x80000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #1
- movcc curbit, curbit, lsl #1
- bcc Lbignum
-Loop3:
- @ Test for possible subtractions, and note which bits
- @ are done in the result. On the final pass, this may subtract
- @ too much from the dividend, but the result will be ok, since the
- @ "bit" will have been shifted out at the bottom.
- cmp dividend, divisor
- subcs dividend, dividend, divisor
- orrcs result, result, curbit
- cmp dividend, divisor, lsr #1
- subcs dividend, dividend, divisor, lsr #1
- orrcs result, result, curbit, lsr #1
- cmp dividend, divisor, lsr #2
- subcs dividend, dividend, divisor, lsr #2
- orrcs result, result, curbit, lsr #2
- cmp dividend, divisor, lsr #3
- subcs dividend, dividend, divisor, lsr #3
- orrcs result, result, curbit, lsr #3
- cmp dividend, #0 @ Early termination?
- movnes curbit, curbit, lsr #4 @ No, any more bits to do?
- movne divisor, divisor, lsr #4
- bne Loop3
-Lgot_result:
- mov r0, result
- mov pc, lr
-Ldiv0:
- str lr, [sp, #-4]!
- bl __div0 (PLT)
- mov r0, #0 @ about as wrong as it could be
- ldmia sp!, {pc}
- .size __udivsi3 , . - __udivsi3
-
-ENTRY(__aeabi_uidivmod)
-
- stmfd sp!, {r0, r1, ip, lr}
- bl __aeabi_uidiv
- ldmfd sp!, {r1, r2, ip, lr}
- mul r3, r0, r2
- sub r1, r1, r3
- mov pc, lr
-ENDPROC(__aeabi_uidivmod)
-
-ENTRY(__aeabi_idivmod)
-
- stmfd sp!, {r0, r1, ip, lr}
- bl __aeabi_idiv
- ldmfd sp!, {r1, r2, ip, lr}
- mul r3, r0, r2
- sub r1, r1, r3
- mov pc, lr
-ENDPROC(__aeabi_idivmod)
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S
deleted file mode 100644
index b166737..0000000
--- a/arch/arm/lib/_umodsi3.S
+++ /dev/null
@@ -1,90 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend .req r0
-divisor .req r1
-overdone .req r2
-curbit .req r3
-/* ip .req r12 */
-/* sp .req r13 */
-/* lr .req r14 */
-/* pc .req r15 */
- .text
- .type __umodsi3 ,function
- .align 0
- ENTRY(__umodsi3)
- cmp divisor, #0
- beq Ldiv0
- mov curbit, #1
- cmp dividend, divisor
- movcc pc, lr
-Loop1:
- @ Unless the divisor is very big, shift it up in multiples of
- @ four bits, since this is the amount of unwinding in the main
- @ division loop. Continue shifting until the divisor is
- @ larger than the dividend.
- cmp divisor, #0x10000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #4
- movcc curbit, curbit, lsl #4
- bcc Loop1
-Lbignum:
- @ For very big divisors, we must shift it a bit at a time, or
- @ we will be in danger of overflowing.
- cmp divisor, #0x80000000
- cmpcc divisor, dividend
- movcc divisor, divisor, lsl #1
- movcc curbit, curbit, lsl #1
- bcc Lbignum
-Loop3:
- @ Test for possible subtractions. On the final pass, this may
- @ subtract too much from the dividend, so keep track of which
- @ subtractions are done, we can fix them up afterwards...
- mov overdone, #0
- cmp dividend, divisor
- subcs dividend, dividend, divisor
- cmp dividend, divisor, lsr #1
- subcs dividend, dividend, divisor, lsr #1
- orrcs overdone, overdone, curbit, ror #1
- cmp dividend, divisor, lsr #2
- subcs dividend, dividend, divisor, lsr #2
- orrcs overdone, overdone, curbit, ror #2
- cmp dividend, divisor, lsr #3
- subcs dividend, dividend, divisor, lsr #3
- orrcs overdone, overdone, curbit, ror #3
- mov ip, curbit
- cmp dividend, #0 @ Early termination?
- movnes curbit, curbit, lsr #4 @ No, any more bits to do?
- movne divisor, divisor, lsr #4
- bne Loop3
- @ Any subtractions that we should not have done will be recorded in
- @ the top three bits of "overdone". Exactly which were not needed
- @ are governed by the position of the bit, stored in ip.
- @ If we terminated early, because dividend became zero,
- @ then none of the below will match, since the bit in ip will not be
- @ in the bottom nibble.
- ands overdone, overdone, #0xe0000000
- moveq pc, lr @ No fixups needed
- tst overdone, ip, ror #3
- addne dividend, dividend, divisor, lsr #3
- tst overdone, ip, ror #2
- addne dividend, dividend, divisor, lsr #2
- tst overdone, ip, ror #1
- addne dividend, dividend, divisor, lsr #1
- mov pc, lr
-Ldiv0:
- str lr, [sp, #-4]!
- bl __div0 (PLT)
- mov r0, #0 @ about as wrong as it could be
- ldmia sp!, {pc}
- .size __umodsi3 , . - __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
-ENDPROC(__umodsi3)
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/ashldi3.S
similarity index 65%
rename from arch/arm/lib/_ashldi3.S
rename to arch/arm/lib/ashldi3.S
index 9c34c21..e9ec890 100644
--- a/arch/arm/lib/_ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -5,6 +5,7 @@
*/
#include <linux/linkage.h>
+#include <asm/assembler.h>
#ifdef __ARMEB__
#define al r1
@@ -14,15 +15,20 @@
#define ah r1
#endif
-.globl __ashldi3
-__ashldi3:
+.pushsection .text.__ashldi3, "ax"
+ENTRY(__ashldi3)
ENTRY(__aeabi_llsl)
subs r3, r2, #32
rsb ip, r2, #32
movmi ah, ah, lsl r2
movpl ah, al, lsl r3
- orrmi ah, ah, al, lsr ip
+ ARM( orrmi ah, ah, al, lsr ip )
+ THUMB( lsrmi r3, al, ip )
+ THUMB( orrmi ah, ah, r3 )
mov al, al, lsl r2
- mov pc, lr
+ ret lr
+
+ENDPROC(__ashldi3)
ENDPROC(__aeabi_llsl)
+.popsection
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/ashrdi3.S
similarity index 65%
rename from arch/arm/lib/_ashrdi3.S
rename to arch/arm/lib/ashrdi3.S
index c74fd64..6e15774 100644
--- a/arch/arm/lib/_ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -5,6 +5,7 @@
*/
#include <linux/linkage.h>
+#include <asm/assembler.h>
#ifdef __ARMEB__
#define al r1
@@ -14,15 +15,20 @@
#define ah r1
#endif
-.globl __ashrdi3
-__ashrdi3:
+.pushsection .text.__ashrdi3, "ax"
+ENTRY(__ashrdi3)
ENTRY(__aeabi_lasr)
subs r3, r2, #32
rsb ip, r2, #32
movmi al, al, lsr r2
movpl al, ah, asr r3
- orrmi al, al, ah, lsl ip
+ ARM( orrmi al, al, ah, lsl ip )
+ THUMB( lslmi r3, ah, ip )
+ THUMB( orrmi al, al, r3 )
mov ah, ah, asr r2
- mov pc, lr
+ ret lr
+
+ENDPROC(__ashrdi3)
ENDPROC(__aeabi_lasr)
+.popsection
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
new file mode 100644
index 0000000..b417db2
--- /dev/null
+++ b/arch/arm/lib/div64.S
@@ -0,0 +1,214 @@
+/*
+ * linux/arch/arm/lib/div64.S
+ *
+ * Optimized computation of 64-bit dividend / 32-bit divisor
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 5, 2003
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#endif
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+/*
+ * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
+ *
+ * Note: Calling convention is totally non standard for optimal code.
+ * This is meant to be used by do_div() from include/asm/div64.h only.
+ *
+ * Input parameters:
+ * xh-xl = dividend (clobbered)
+ * r4 = divisor (preserved)
+ *
+ * Output values:
+ * yh-yl = result
+ * xh = remainder
+ *
+ * Clobbered regs: xl, ip
+ */
+
+.pushsection .text.__do_div64, "ax"
+ENTRY(__do_div64)
+UNWIND(.fnstart)
+
+ @ Test for easy paths first.
+ subs ip, r4, #1
+ bls 9f @ divisor is 0 or 1
+ tst ip, r4
+ beq 8f @ divisor is power of 2
+
+ @ See if we need to handle upper 32-bit result.
+ cmp xh, r4
+ mov yh, #0
+ blo 3f
+
+ @ Align divisor with upper part of dividend.
+ @ The aligned divisor is stored in yl preserving the original.
+ @ The bit position is stored in ip.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz yl, r4
+ clz ip, xh
+ sub yl, yl, ip
+ mov ip, #1
+ mov ip, ip, lsl yl
+ mov yl, r4, lsl yl
+
+#else
+
+ mov yl, r4
+ mov ip, #1
+1: cmp yl, #0x80000000
+ cmpcc yl, xh
+ movcc yl, yl, lsl #1
+ movcc ip, ip, lsl #1
+ bcc 1b
+
+#endif
+
+ @ The division loop for needed upper bit positions.
+ @ Break out early if dividend reaches 0.
+2: cmp xh, yl
+ orrcs yh, yh, ip
+ subscs xh, xh, yl
+ movsne ip, ip, lsr #1
+ mov yl, yl, lsr #1
+ bne 2b
+
+ @ See if we need to handle lower 32-bit result.
+3: cmp xh, #0
+ mov yl, #0
+ cmpeq xl, r4
+ movlo xh, xl
+ retlo lr
+
+ @ The division loop for lower bit positions.
+ @ Here we shift remainer bits leftwards rather than moving the
+ @ divisor for comparisons, considering the carry-out bit as well.
+ mov ip, #0x80000000
+4: movs xl, xl, lsl #1
+ adcs xh, xh, xh
+ beq 6f
+ cmpcc xh, r4
+5: orrcs yl, yl, ip
+ subcs xh, xh, r4
+ movs ip, ip, lsr #1
+ bne 4b
+ ret lr
+
+ @ The top part of remainder became zero. If carry is set
+ @ (the 33th bit) this is a false positive so resume the loop.
+ @ Otherwise, if lower part is also null then we are done.
+6: bcs 5b
+ cmp xl, #0
+ reteq lr
+
+ @ We still have remainer bits in the low part. Bring them up.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz xh, xl @ we know xh is zero here so...
+ add xh, xh, #1
+ mov xl, xl, lsl xh
+ mov ip, ip, lsr xh
+
+#else
+
+7: movs xl, xl, lsl #1
+ mov ip, ip, lsr #1
+ bcc 7b
+
+#endif
+
+ @ Current remainder is now 1. It is worthless to compare with
+ @ divisor at this point since divisor can not be smaller than 3 here.
+ @ If possible, branch for another shift in the division loop.
+ @ If no bit position left then we are done.
+ movs ip, ip, lsr #1
+ mov xh, #1
+ bne 4b
+ ret lr
+
+8: @ Division by a power of 2: determine what that divisor order is
+ @ then simply shift values around
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz ip, r4
+ rsb ip, ip, #31
+
+#else
+
+ mov yl, r4
+ cmp r4, #(1 << 16)
+ mov ip, #0
+ movhs yl, yl, lsr #16
+ movhs ip, #16
+
+ cmp yl, #(1 << 8)
+ movhs yl, yl, lsr #8
+ addhs ip, ip, #8
+
+ cmp yl, #(1 << 4)
+ movhs yl, yl, lsr #4
+ addhs ip, ip, #4
+
+ cmp yl, #(1 << 2)
+ addhi ip, ip, #3
+ addls ip, ip, yl, lsr #1
+
+#endif
+
+ mov yh, xh, lsr ip
+ mov yl, xl, lsr ip
+ rsb ip, ip, #32
+ ARM( orr yl, yl, xh, lsl ip )
+ THUMB( lsl xh, xh, ip )
+ THUMB( orr yl, yl, xh )
+ mov xh, xl, lsl ip
+ mov xh, xh, lsr ip
+ ret lr
+
+ @ eq -> division by 1: obvious enough...
+9: moveq yl, xl
+ moveq yh, xh
+ moveq xh, #0
+ reteq lr
+UNWIND(.fnend)
+
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+Ldiv0_64:
+ @ Division by 0:
+ str lr, [sp, #-8]!
+ bl __div0
+
+ @ as wrong as it could be...
+ mov yl, #0
+ mov yh, #0
+ mov xh, #0
+ ldr pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(__do_div64)
+.popsection
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
new file mode 100644
index 0000000..76968ce
--- /dev/null
+++ b/arch/arm/lib/lib1funcs.S
@@ -0,0 +1,429 @@
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico@fluxnic.net>
+ * - contributed to gcc-3.4 on Sep 30, 2003
+ * - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * U-Boot compatibility bit, define empty UNWIND() macro as, since we
+ * do not support stack unwinding and define CONFIG_AEABI to make all
+ * of the functions available without diverging from Linux code.
+ */
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#define CONFIG_AEABI
+#endif
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \curbit, \divisor
+ clz \result, \dividend
+ sub \result, \curbit, \result
+ mov \curbit, #1
+ mov \divisor, \divisor, lsl \result
+ mov \curbit, \curbit, lsl \result
+ mov \result, #0
+
+#else
+
+ @ Initially shift the divisor left 3 bits if possible,
+ @ set curbit accordingly. This allows for curbit to be located
+ @ at the left end of each 4 bit nibbles in the division loop
+ @ to save one loop in most cases.
+ tst \divisor, #0xe0000000
+ moveq \divisor, \divisor, lsl #3
+ moveq \curbit, #8
+ movne \curbit, #1
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ movlo \curbit, \curbit, lsl #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ movlo \curbit, \curbit, lsl #1
+ blo 1b
+
+ mov \result, #0
+
+#endif
+
+ @ Division loop
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ orrhs \result, \result, \curbit
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ orrhs \result, \result, \curbit, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ orrhs \result, \result, \curbit, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ orrhs \result, \result, \curbit, lsr #3
+ cmp \dividend, #0 @ Early termination?
+ movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
+ movne \divisor, \divisor, lsr #4
+ bne 1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ rsb \order, \order, #31
+
+#else
+
+ cmp \divisor, #(1 << 16)
+ movhs \divisor, \divisor, lsr #16
+ movhs \order, #16
+ movlo \order, #0
+
+ cmp \divisor, #(1 << 8)
+ movhs \divisor, \divisor, lsr #8
+ addhs \order, \order, #8
+
+ cmp \divisor, #(1 << 4)
+ movhs \divisor, \divisor, lsr #4
+ addhs \order, \order, #4
+
+ cmp \divisor, #(1 << 2)
+ addhi \order, \order, #3
+ addls \order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+ clz \order, \divisor
+ clz \spare, \dividend
+ sub \order, \order, \spare
+ mov \divisor, \divisor, lsl \order
+
+#else
+
+ mov \order, #0
+
+ @ Unless the divisor is very big, shift it up in multiples of
+ @ four bits, since this is the amount of unwinding in the main
+ @ division loop. Continue shifting until the divisor is
+ @ larger than the dividend.
+1: cmp \divisor, #0x10000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #4
+ addlo \order, \order, #4
+ blo 1b
+
+ @ For very big divisors, we must shift it a bit at a time, or
+ @ we will be in danger of overflowing.
+1: cmp \divisor, #0x80000000
+ cmplo \divisor, \dividend
+ movlo \divisor, \divisor, lsl #1
+ addlo \order, \order, #1
+ blo 1b
+
+#endif
+
+ @ Perform all needed subtractions to keep only the reminder.
+ @ Do comparisons in batch of 4 first.
+ subs \order, \order, #3 @ yes, 3 is intended here
+ blt 2f
+
+1: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ cmp \dividend, \divisor, lsr #1
+ subhs \dividend, \dividend, \divisor, lsr #1
+ cmp \dividend, \divisor, lsr #2
+ subhs \dividend, \dividend, \divisor, lsr #2
+ cmp \dividend, \divisor, lsr #3
+ subhs \dividend, \dividend, \divisor, lsr #3
+ cmp \dividend, #1
+ mov \divisor, \divisor, lsr #4
+ subsge \order, \order, #4
+ bge 1b
+
+ tst \order, #3
+ teqne \dividend, #0
+ beq 5f
+
+ @ Either 1, 2 or 3 comparison/subtractions are left.
+2: cmn \order, #2
+ blt 4f
+ beq 3f
+ cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+3: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+ mov \divisor, \divisor, lsr #1
+4: cmp \dividend, \divisor
+ subhs \dividend, \dividend, \divisor
+5:
+.endm
+
+
+.pushsection .text.__udivsi3, "ax"
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+UNWIND(.fnstart)
+
+ subs r2, r1, #1
+ reteq lr
+ bcc Ldiv0
+ cmp r0, r1
+ bls 11f
+ tst r1, r2
+ beq 12f
+
+ ARM_DIV_BODY r0, r1, r2, r3
+
+ mov r0, r2
+ ret lr
+
+11: moveq r0, #1
+ movne r0, #0
+ ret lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ mov r0, r0, lsr r2
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+.popsection
+
+.pushsection .text.__umodsi3, "ax"
+ENTRY(__umodsi3)
+UNWIND(.fnstart)
+
+ subs r2, r1, #1 @ compare divisor with 1
+ bcc Ldiv0
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ retls lr
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__umodsi3)
+.popsection
+
+.pushsection .text.__divsi3, "ax"
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+UNWIND(.fnstart)
+
+ cmp r1, #0
+ eor ip, r0, r1 @ save the sign of the result.
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ subs r2, r1, #1 @ division by 1 or -1 ?
+ beq 10f
+ movs r3, r0
+ rsbmi r3, r0, #0 @ positive dividend value
+ cmp r3, r1
+ bls 11f
+ tst r1, r2 @ divisor is power of 2 ?
+ beq 12f
+
+ ARM_DIV_BODY r3, r1, r0, r2
+
+ cmp ip, #0
+ rsbmi r0, r0, #0
+ ret lr
+
+10: teq ip, r0 @ same sign ?
+ rsbmi r0, r0, #0
+ ret lr
+
+11: movlo r0, #0
+ moveq r0, ip, asr #31
+ orreq r0, r0, #1
+ ret lr
+
+12: ARM_DIV2_ORDER r1, r2
+
+ cmp ip, #0
+ mov r0, r3, lsr r2
+ rsbmi r0, r0, #0
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+.popsection
+
+.pushsection .text.__modsi3, "ax"
+ENTRY(__modsi3)
+UNWIND(.fnstart)
+
+ cmp r1, #0
+ beq Ldiv0
+ rsbmi r1, r1, #0 @ loops below use unsigned.
+ movs ip, r0 @ preserve sign of dividend
+ rsbmi r0, r0, #0 @ if negative make positive
+ subs r2, r1, #1 @ compare divisor with 1
+ cmpne r0, r1 @ compare dividend with divisor
+ moveq r0, #0
+ tsthi r1, r2 @ see if divisor is power of 2
+ andeq r0, r0, r2
+ bls 10f
+
+ ARM_MOD_BODY r0, r1, r2, r3
+
+10: cmp ip, #0
+ rsbmi r0, r0, #0
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__modsi3)
+.popsection
+
+#ifdef CONFIG_AEABI
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_uidivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr} )
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_uidiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_uidivmod)
+.popsection
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_idivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr} )
+
+ stmfd sp!, {r0, r1, ip, lr}
+ bl __aeabi_idiv
+ ldmfd sp!, {r1, r2, ip, lr}
+ mul r3, r0, r2
+ sub r1, r1, r3
+ ret lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_idivmod)
+.popsection
+
+#endif
+
+.pushsection .text.Ldiv0, "ax"
+Ldiv0:
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+
+ str lr, [sp, #-8]!
+ bl __div0
+ mov r0, #0 @ About as wrong as it could be.
+ ldr pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(Ldiv0)
+.popsection
+
+/* Thumb-1 specialities */
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
+ENTRY(__gnu_thumb1_case_sqi)
+ push {r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r1, r1, #1
+ ldrsb r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_sqi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_uqi, "ax"
+ENTRY(__gnu_thumb1_case_uqi)
+ push {r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r1, r1, #1
+ ldrb r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_uqi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_shi, "ax"
+ENTRY(__gnu_thumb1_case_shi)
+ push {r0, r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r0, r0, #1
+ lsls r1, r1, #1
+ ldrsh r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r0, r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_shi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_uhi, "ax"
+ENTRY(__gnu_thumb1_case_uhi)
+ push {r0, r1}
+ mov r1, lr
+ lsrs r1, r1, #1
+ lsls r0, r0, #1
+ lsls r1, r1, #1
+ ldrh r1, [r1, r0]
+ lsls r1, r1, #1
+ add lr, lr, r1
+ pop {r0, r1}
+ bx lr
+ENDPROC(__gnu_thumb1_case_uhi)
+.popsection
+#endif
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/lshrdi3.S
similarity index 65%
rename from arch/arm/lib/_lshrdi3.S
rename to arch/arm/lib/lshrdi3.S
index 1f9b916..ead33e5 100644
--- a/arch/arm/lib/_lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -5,6 +5,7 @@
*/
#include <linux/linkage.h>
+#include <asm/assembler.h>
#ifdef __ARMEB__
#define al r1
@@ -14,15 +15,20 @@
#define ah r1
#endif
-.globl __lshrdi3
-__lshrdi3:
+.pushsection .text.__lshldi3, "ax"
+ENTRY(__lshrdi3)
ENTRY(__aeabi_llsr)
subs r3, r2, #32
rsb ip, r2, #32
movmi al, al, lsr r2
movpl al, ah, lsr r3
- orrmi al, al, ah, lsl ip
+ ARM( orrmi al, al, ah, lsl ip )
+ THUMB( lslmi r3, ah, ip )
+ THUMB( orrmi al, al, r3 )
mov ah, ah, lsr r2
- mov pc, lr
+ ret lr
+
+ENDPROC(__lshrdi3)
ENDPROC(__aeabi_llsr)
+.popsection
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 7d9fc0f..00602e9 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,12 +13,6 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
-#define W(instr) instr.w
-#else
-#define W(instr) instr
-#endif
-
#define LDR1W_SHIFT 0
#define STR1W_SHIFT 0
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
new file mode 100644
index 0000000..d7c93e7
--- /dev/null
+++ b/arch/arm/lib/muldi3.S
@@ -0,0 +1,48 @@
+/*
+ * linux/arch/arm/lib/muldi3.S
+ *
+ * Author: Nicolas Pitre
+ * Created: Oct 19, 2005
+ * Copyright: Monta Vista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+.pushsection .text.__muldi3, "ax"
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+ mul xh, yl, xh
+ mla xh, xl, yh, xh
+ mov ip, xl, lsr #16
+ mov yh, yl, lsr #16
+ bic xl, xl, ip, lsl #16
+ bic yl, yl, yh, lsl #16
+ mla xh, yh, ip, xh
+ mul yh, xl, yh
+ mul xl, yl, xl
+ mul ip, yl, ip
+ adds xl, xl, yh, lsl #16
+ adc xh, xh, yh, lsr #16
+ adds xl, xl, ip, lsl #16
+ adc xh, xh, ip, lsr #16
+ ret lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
+.popsection
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/uldivmod.S
similarity index 96%
rename from arch/arm/lib/_uldivmod.S
rename to arch/arm/lib/uldivmod.S
index 426c2f2..7246996 100644
--- a/arch/arm/lib/_uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -9,10 +9,6 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-/* We don't use Thumb instructions for now */
-#define ARM(x...) x
-#define THUMB(x...)
-
/*
* A, Q = r0 + (r1 << 32)
* B, R = r2 + (r3 << 32)
@@ -37,7 +33,9 @@
TMP .req r8
)
+.pushsection .text.__aeabi_uldivmod, "ax"
ENTRY(__aeabi_uldivmod)
+
stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
@ Test if B == 0
orrs ip, B_0, B_1 @ Z set -> B == 0
@@ -226,7 +224,9 @@
@ Shift A to the right by the appropriate amount.
rsb D_1, D_0, #32
mov Q_0, A_0, lsr D_0
- orr Q_0, A_1, lsl D_1
+ ARM( orr Q_0, Q_0, A_1, lsl D_1 )
+ THUMB( lsl A_1, D_1 )
+ THUMB( orr Q_0, A_1 )
mov Q_1, A_1, lsr D_0
@ Move C to R
mov R_0, C_0
@@ -243,3 +243,4 @@
mov R_1, #0
ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
ENDPROC(__aeabi_uldivmod)
+.popsection
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 49238ed..5cc132b 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -60,6 +60,16 @@
ldr pc, _irq
ldr pc, _fiq
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
/*
*************************************************************************
*
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index ca2a119..0f6bf61 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -74,4 +74,16 @@
#define K2G_GPIO_DIR_OFFSET 0x0
#define K2G_GPIO_SETDATA_OFFSET 0x8
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT 0x0
+#define RSTMUX_LOCK8_MASK (0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT 0x1
+#define RSTMUX_OMODE8_MASK (0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET 0x2
+#define RSTMUX_OMODE8_INT 0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4
+
#endif /* __ASM_ARCH_HARDWARE_K2G_H */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 0000000..77d3cfe
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_MESON
+
+config MESON_GXBB
+ bool "Support Meson GXBaby"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ The Amlogic Meson GXBaby (S905) is an ARM SoC with a
+ quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+if MESON_GXBB
+
+config TARGET_ODROID_C2
+ bool "ODROID-C2"
+ help
+ ODROID-C2 is a single board computer based on Meson GXBaby
+ with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
+ slot, eMMC, IR receiver and a 40-pin GPIO header.
+
+endif
+
+config SYS_SOC
+ default "meson"
+
+config SYS_MALLOC_F_LEN
+ default 0x1000
+
+source "board/hardkernel/odroid-c2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 0000000..bf49b8b
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o sm.o
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
new file mode 100644
index 0000000..64fa3c1
--- /dev/null
+++ b/arch/arm/mach-meson/board.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ const fdt64_t *val;
+ int offset;
+ int len;
+
+ offset = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (offset < 0)
+ return -EINVAL;
+
+ val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+ if (len < sizeof(*val) * 2)
+ return -EINVAL;
+
+ /* Use unaligned access since cache is still disabled */
+ gd->ram_size = get_unaligned_be64(&val[1]);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ /* Reserve first 16 MiB of RAM for firmware */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
+ gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset(true);
+}
+
+static struct mm_region gxbb_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = gxbb_mem_map;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
new file mode 100644
index 0000000..1b35a22
--- /dev/null
+++ b/arch/arm/mach-meson/sm.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Secure monitor calls.
+ */
+
+#include <common.h>
+#include <asm/arch/gxbb.h>
+#include <linux/kernel.h>
+
+#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define FN_EFUSE_READ 0x82000030
+#define FN_EFUSE_WRITE 0x82000031
+
+static void *shmem_input;
+static void *shmem_output;
+
+static void meson_init_shmem(void)
+{
+ struct pt_regs regs;
+
+ if (shmem_input && shmem_output)
+ return;
+
+ regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE;
+ smc_call(®s);
+ shmem_input = (void *)regs.regs[0];
+
+ regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE;
+ smc_call(®s);
+ shmem_output = (void *)regs.regs[0];
+
+ debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output);
+}
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ regs.regs[0] = FN_EFUSE_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+
+ smc_call(®s);
+
+ if (regs.regs[0] == 0)
+ return -1;
+
+ memcpy(buffer, shmem_output, min(size, regs.regs[0]));
+
+ return regs.regs[0];
+}
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d3bddb7..2a8afac 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -41,6 +41,9 @@
config DM_GPIO
default y
+config BLK
+ default y
+
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
index fefb568..b3d2113 100644
--- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
@@ -7,24 +7,24 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3036.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
-int rk3036_reset_request(struct udevice *dev, enum reset_t type)
+int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3036_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
- case RESET_WARM:
+ case SYSRESET_WARM:
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
- case RESET_COLD:
+ case SYSRESET_COLD:
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
@@ -34,12 +34,12 @@
return -EINPROGRESS;
}
-static struct reset_ops rk3036_reset = {
- .request = rk3036_reset_request,
+static struct sysreset_ops rk3036_sysreset = {
+ .request = rk3036_sysreset_request,
};
-U_BOOT_DRIVER(reset_rk3036) = {
- .name = "rk3036_reset",
- .id = UCLASS_RESET,
- .ops = &rk3036_reset,
+U_BOOT_DRIVER(sysreset_rk3036) = {
+ .name = "rk3036_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3036_sysreset,
};
diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
index bf7540a..0aad1c2 100644
--- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -7,25 +7,25 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
-int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
struct rk3288_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
- case RESET_WARM:
+ case SYSRESET_WARM:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
- case RESET_COLD:
+ case SYSRESET_COLD:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
@@ -36,12 +36,12 @@
return -EINPROGRESS;
}
-static struct reset_ops rk3288_reset = {
- .request = rk3288_reset_request,
+static struct sysreset_ops rk3288_sysreset = {
+ .request = rk3288_sysreset_request,
};
-U_BOOT_DRIVER(reset_rk3288) = {
- .name = "rk3288_reset",
- .id = UCLASS_RESET,
- .ops = &rk3288_reset,
+U_BOOT_DRIVER(sysreset_rk3288) = {
+ .name = "rk3288_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3288_sysreset,
};
diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c
index 2627eec..a6cabfb 100644
--- a/arch/arm/mach-snapdragon/reset.c
+++ b/arch/arm/mach-snapdragon/reset.c
@@ -9,12 +9,12 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-static int msm_reset_request(struct udevice *dev, enum reset_t type)
+static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
phys_addr_t addr = dev_get_addr(dev);
if (!addr)
@@ -23,18 +23,18 @@
return -EINPROGRESS;
}
-static struct reset_ops msm_reset_ops = {
- .request = msm_reset_request,
+static struct sysreset_ops msm_sysreset_ops = {
+ .request = msm_sysreset_request,
};
-static const struct udevice_id msm_reset_ids[] = {
+static const struct udevice_id msm_sysreset_ids[] = {
{ .compatible = "qcom,pshold" },
{ }
};
U_BOOT_DRIVER(msm_reset) = {
- .name = "msm_reset",
- .id = UCLASS_RESET,
- .of_match = msm_reset_ids,
- .ops = &msm_reset_ops,
+ .name = "msm_sysreset",
+ .id = UCLASS_SYSRESET,
+ .of_match = msm_sysreset_ids,
+ .ops = &msm_sysreset_ops,
};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index dea4ce5..1484607 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -35,6 +35,10 @@
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ bool "samtec VIN|ING FPGA (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -53,12 +57,14 @@
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+ default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -73,5 +79,6 @@
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+ default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index ad3d6c4..25367cf 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -37,6 +37,7 @@
obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 20149da..bd15b9b 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -247,6 +247,15 @@
return -1; /* Never reached */
}
+/*
+ * Properly announce BOOT_DEVICE_BOARD as "FEL".
+ * Overrides weak function from common/spl/spl.c
+ */
+void spl_board_announce_boot_device(void)
+{
+ printf("FEL");
+}
+
/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 5b81a8d..7c57f02 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@
if (!needs_init)
return 0;
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@
return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
#elif defined CONFIG_AXP209_POWER
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
# else
@@ -77,7 +77,7 @@
return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
#elif defined CONFIG_AXP209_POWER
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
# else
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ba6983f..b18a12e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -22,6 +22,7 @@
select SPL
select SUPPORT_SPL
select TEGRA_COMMON
+ select TEGRA_GPIO
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
@@ -50,8 +51,14 @@
config TEGRA210
bool "Tegra210 family"
+ select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+config TEGRA186
+ bool "Tegra186 family"
+ select TEGRA186_GPIO
+ select TEGRA_ARMV8_COMMON
+
endchoice
config TEGRA_DISCONNECT_UDC_ON_BOOT
@@ -75,5 +82,6 @@
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2dbc69..12ee1cd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_TEGRA186
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += cpu.o
@@ -30,9 +31,11 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
+endif
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
new file mode 100644
index 0000000..f4b6152
--- /dev/null
+++ b/arch/arm/mach-tegra/board186.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+ tegra_mmc_init();
+
+ return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
new file mode 100644
index 0000000..97cf23f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -0,0 +1,25 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+ prompt "Tegra186 board select"
+
+config TARGET_P2771_0000
+ bool "NVIDIA Tegra186 P2771-0000 board"
+ help
+ P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
+ combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+ micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
+ expansion headers.
+
+endchoice
+
+config SYS_SOC
+ default "tegra186"
+
+source "board/nvidia/p2771-0000/Kconfig"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
new file mode 100644
index 0000000..ce4610d
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 87d1675..ae763ad 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -23,6 +23,11 @@
bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
select CPU_V7
+config ARCH_UNIPHIER_LD11
+ bool "UniPhier PH1-LD11 SoC"
+ select ARM64
+ select SPL_SEPARATE_BSS
+
config ARCH_UNIPHIER_LD20
bool "UniPhier PH1-LD20 SoC"
select ARM64
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 2a7ae1b..f853701 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -62,6 +62,13 @@
uniphier_pxs2_clk_init();
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ case SOC_UNIPHIER_LD11:
+ uniphier_ld20_pin_init();
+ led_puts("U1");
+ uniphier_ld11_clk_init();
+ break;
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_pin_init();
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f0547c3..ed308f3 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -165,6 +165,23 @@
};
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+static const struct uniphier_board_data uniphier_ld11_data = {
+ .dram_freq = 1600,
+ .dram_nr_ch = 2,
+ .dram_ch[0] = {
+ .base = 0x80000000,
+ .size = 0x20000000,
+ .width = 16,
+ },
+ .dram_ch[1] = {
+ .base = 0xa0000000,
+ .size = 0x20000000,
+ .width = 16,
+ },
+};
+#endif
+
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
@@ -216,6 +233,9 @@
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ { "socionext,ph1-ld11", &uniphier_ld11_data, },
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 6cd096e..d7fefc5 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
index b092c1b..96a1270 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -43,7 +43,7 @@
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
- {BOOT_DEVICE_NOR, "NOR Boot (XECS1)"},
+ {BOOT_DEVICE_NOR, "NOR (XECS1)"},
};
static int get_boot_mode_sel(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
index 0597618..b066ed9 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
@@ -36,14 +36,14 @@
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NOR, "NOR Boot"},
+ {BOOT_DEVICE_NOR, "NOR (XECS0)"},
};
static int get_boot_mode_sel(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
index f9726f1..450c43b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
@@ -37,7 +37,7 @@
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
index 4b06f74..20ff773 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
@@ -32,17 +32,17 @@
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
- {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
- {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS1)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS1)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
{BOOT_DEVICE_NONE, "Reserved"},
};
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
index a4a3c47..ddf8259 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
@@ -12,7 +12,7 @@
#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NOR, "NOR boot"},
+ {BOOT_DEVICE_NOR, "NOR (XECS0)"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index b180f44..4b744da 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -39,7 +39,8 @@
case SOC_UNIPHIER_LD6B:
return uniphier_pxs2_boot_device();
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
return uniphier_ld20_boot_device();
#endif
diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index fa97dc5..a8ee382 100644
--- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -39,7 +39,8 @@
uniphier_pxs2_boot_mode_show();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
uniphier_ld20_boot_mode_show();
break;
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 93e9d91..1428e0c 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -9,4 +9,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
new file mode 100644
index 0000000..92a0733
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld11_clk_init(void)
+{
+ if (readl(SG_PINMON0) & BIT(27)) {
+ /* if booted without stand-by MPU */
+
+ writel(1, SG_ETPHYPSHUT);
+ writel(1, SG_ETPHYCNT);
+
+ udelay(1); /* wait for regulator level 1.1V -> 2.5V */
+
+ writel(3, SG_ETPHYCNT);
+ writel(3, SG_ETPHYPSHUT);
+ writel(7, SG_ETPHYCNT);
+ }
+}
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index f9646c0..6ad4c76 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -45,7 +45,7 @@
puts("PH1-LD6b (MN2WS0320)");
break;
case 0x31:
- puts("PH1-LD11 ()");
+ puts("PH1-LD11 (SC1405AP1)");
break;
case 0x32:
puts("PH1-LD20 (SC1401AJ1)");
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 41aa53b..5b9d892 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -12,6 +12,7 @@
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c
new file mode 100644
index 0000000..1be18a8
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld11.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "umc64-regs.h"
+
+#define CONFIG_DDR_FREQ 1866
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
+static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+ unsigned long size, int ch)
+{
+ writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+ writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+ writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
+ writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
+ writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
+
+ writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+ writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+
+ writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+
+ writel(0x00000003, dc_base + UMC_ACSSETA);
+ writel(0x00000103, dc_base + UMC_FLOWCTLG);
+ writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
+ writel(0x02020200, dc_base + UMC_SPCSETB);
+ writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+ writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base,
+ enum dram_freq freq, unsigned long size, int ch)
+{
+ void __iomem *dc_base = umc_ch_base;
+
+ return umc_dc_init(dc_base, freq, size, ch);
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x00000001, um_base + UMC_SIORST);
+ writel(0x00000001, um_base + UMC_VO0RST);
+ writel(0x00000001, um_base + UMC_VPERST);
+ writel(0x00000001, um_base + UMC_RGLRST);
+ writel(0x00000001, um_base + UMC_A2DRST);
+ writel(0x00000001, um_base + UMC_DMDRST);
+}
+
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5B800000;
+ void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+ enum dram_freq freq;
+ int ch, ret;
+
+ switch (bd->dram_freq) {
+ case 1600:
+ freq = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ unsigned long size = bd->dram_ch[ch].size;
+ unsigned int width = bd->dram_ch[ch].width;
+
+ ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ umc_ch_base += 0x00200000;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 4614dac..186a398 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -15,7 +15,7 @@
#include "../init.h"
#include "ddrphy-ld20-regs.h"
-#include "umc-ld20-regs.h"
+#include "umc64-regs.h"
#define DRAM_CH_NR 3
@@ -200,9 +200,9 @@
writel(umc_dataset[freq], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000003, dc_base + UMC_ACSCTLA);
+ writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
- writel(0x00010200, dc_base + UMC_ACSSETA);
+ writel(0x00010200, dc_base + UMC_ACSSETB);
writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
similarity index 84%
rename from arch/arm/mach-uniphier/dram/umc-ld20-regs.h
rename to arch/arm/mach-uniphier/dram/umc64-regs.h
index 46e513c..860d04e 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -18,13 +18,15 @@
#define UMC_INITSET 0x00000040
#define UMC_INITSTAT 0x00000044
#define UMC_CMDCTLE 0x00000050
+#define UMC_CMDCTLF 0x00000054
+#define UMC_CMDCTLG 0x00000058
#define UMC_SPCSETB 0x00000084
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
-#define UMC_ACSCTLA 0x000000C0
-#define UMC_ACSSETA 0x000000C4
+#define UMC_ACSSETA 0x000000C0
+#define UMC_ACSSETB 0x000000C4
#define UMC_MEMCONF0A 0x00000200
#define UMC_MEMCONF0B 0x00000204
#define UMC_MEMCONFCH 0x00000240
@@ -32,6 +34,7 @@
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
+#define UMC_ACFETCHCTRL 0x00000460
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
@@ -42,6 +45,7 @@
#define UMC_ODTCTL_D1 0x0000061C
#define UMC_RESPCTL 0x00000624
#define UMC_DIRECTBUSCTRLA 0x00000680
+#define UMC_DEBUGC 0x00000718
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
@@ -70,4 +74,12 @@
#define UMC_MBUS9 0x00002478
#define UMC_MBUS10 0x000024F8
+/* UMC1 register */
+#define UMC_SIORST 0x00000728
+#define UMC_VO0RST 0x0000073c
+#define UMC_VPERST 0x00000744
+#define UMC_RGLRST 0x00000750
+#define UMC_A2DRST 0x00000764
+#define UMC_DMDRST 0x00000770
+
#endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 9242b41..755a361 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -9,4 +9,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
new file mode 100644
index 0000000..c94d83c
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL7);
+ tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
+ writel(tmp, SC_RSTCTRL7);
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_PERI;
+ writel(tmp, SC_CLKCTRL4);
+
+ tmp = readl(SC_CLKCTRL7);
+ tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
+ writel(tmp, SC_CLKCTRL7);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index a103902..7177a8c 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -3,4 +3,5 @@
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index ab0a68d..cba0bc9 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -32,6 +32,7 @@
int uniphier_sld8_init(const struct uniphier_board_data *bd);
int uniphier_pro5_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_init(const struct uniphier_board_data *bd);
int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
@@ -81,6 +82,7 @@
int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@@ -91,6 +93,7 @@
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void);
void uniphier_ld4_pin_init(void);
@@ -105,6 +108,7 @@
void uniphier_pro4_clk_init(void);
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
+void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
void cci500_init(int nr_slaves);
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index b58e6c8..dcaa445 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -11,4 +11,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c
new file mode 100644
index 0000000..de2dc62
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld11_init(const struct uniphier_board_data *bd)
+{
+ uniphier_sbc_init_savepin(bd);
+ uniphier_pxs2_sbc_init(bd);
+ uniphier_ld20_early_pin_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld11_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_ld11_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ dcache_disable();
+
+ led_puts("L6");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 660ad45..7f66053 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -51,5 +51,7 @@
led_puts("L5");
+ dcache_disable();
+
return 0;
}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index 15a53ce..77e5b99 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -55,6 +55,11 @@
uniphier_pxs2_init(param);
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ case SOC_UNIPHIER_LD11:
+ uniphier_ld11_init(param);
+ break;
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_init(param);
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index b579cb0..7f4d9f7 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -9,4 +9,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 38da253..ec3c22c 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,4 +9,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 1d71ce8..a179d61 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -59,6 +59,9 @@
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
+#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
+#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
+
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 8b047ec..7d48e9a 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -6,28 +6,8 @@
#ifndef __ASM_U_BOOT_H__
#define __ASM_U_BOOT_H__ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-typedef struct bd_info {
- unsigned char bi_phy_id[4];
- unsigned long bi_board_number;
- void *bi_boot_params;
- struct {
- unsigned long start;
- unsigned long size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
- unsigned long bi_flashstart;
- unsigned long bi_flashsize;
- unsigned long bi_flashoffset;
-} bd_t;
-
-#define bi_memstart bi_dram[0].start
-#define bi_memsize bi_dram[0].size
-
-#endif
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 911c0d3..8203844 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -14,47 +14,8 @@
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_mbar_base; /* base of internal registers */
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#ifdef CONFIG_PCI
- unsigned long bi_pcifreq; /* pci Freq in MHz */
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
- unsigned long bi_inpfreq; /* input Freq in MHz */
- unsigned long bi_vcofreq; /* vco Freq in MHz */
- unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
-#endif
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_M68K
diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
index 11f3dd0..94f0562 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -50,7 +50,7 @@
#define NOP __asm__ __volatile__ ("nop");
/* use machine status registe USE_MSR_REG */
-#if XILINX_USE_MSR_INSTR == 1
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1
#define MSRSET(val) \
__asm__ __volatile__ ("msrset r0," #val );
diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h
index 724f5bd..8f67ec7 100644
--- a/arch/microblaze/include/asm/string.h
+++ b/arch/microblaze/include/asm/string.h
@@ -17,13 +17,11 @@
#define __MICROBLAZE_STRING_H__
#if 0
-#define __HAVE_ARCH_BCOPY
#define __HAVE_ARCH_MEMCPY
#define __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_MEMMOVE
extern void *memcpy (void *, const void *, __kernel_size_t);
-extern void bcopy (const char *, char *, int);
extern void *memset (void *, int, __kernel_size_t);
extern void *memmove (void *, const void *, __kernel_size_t);
#endif
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dc34c18..5c30ae9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -23,12 +23,19 @@
config TARGET_MALTA
bool "Support malta"
+ select DM
+ select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
+ select OF_CONTROL
+ select OF_ISA_BUS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
+ select SUPPORTS_CPU_MIPS64_R1
+ select SUPPORTS_CPU_MIPS64_R2
+ select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
@@ -221,6 +228,9 @@
config MIPS_TUNE_24KC
bool
+config MIPS_TUNE_34KC
+ bool
+
config MIPS_TUNE_74KC
bool
@@ -236,6 +246,40 @@
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config SYS_DCACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 Dcache, if known at compile time.
+
+config SYS_DCACHE_LINE_SIZE
+ hex
+ default 0
+ help
+ The size of L1 Dcache lines, if known at compile time.
+
+config SYS_ICACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 ICache, if known at compile time.
+
+config SYS_ICACHE_LINE_SIZE
+ int
+ default 0
+ help
+ The size of L1 Icache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+ def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+ SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+ help
+ Select this (or let it be auto-selected by not defining any cache
+ sizes) in order to allow U-Boot to automatically detect the sizes
+ of caches at runtime. This has a small cost in code size & runtime
+ so if you know the cache configuration for your system at compile
+ time it would be beneficial to configure it.
+
config MIPS_L1_CACHE_SHIFT_4
bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 655a493..efe7e44 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -4,6 +4,12 @@
head-y := arch/mips/cpu/start.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
@@ -28,6 +34,7 @@
tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
# Include default header files
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 609a998..dcd3460 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -65,7 +65,7 @@
PF_ABICALLS := -mabicalls
PF_PIC := -fpic
PF_PIE := -pie
-PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding
+PF_OBJCOPY := -j .got -j .rel.dyn -j .padding
PF_OBJCOPY += -j .dtb.init.rodata
endif
@@ -74,4 +74,5 @@
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections $(PF_PIE)
-OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY)
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
+OBJCOPYFLAGS += $(PF_OBJCOPY)
diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
new file mode 100644
index 0000000..07004ea
--- /dev/null
+++ b/arch/mips/cpu/u-boot-spl.lds
@@ -0,0 +1,90 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text : {
+ *(.text*)
+ } > .spl_mem
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } > .spl_mem
+
+ . = ALIGN(4);
+ .data : {
+ *(SORT_BY_ALIGNMENT(.data*))
+ *(SORT_BY_ALIGNMENT(.sdata*))
+ } > .spl_mem
+
+#ifdef CONFIG_SPL_DM
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .spl_mem
+#endif
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .bss (NOLOAD) : {
+ __bss_start = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .bss_mem
+
+ .rel.dyn (NOLOAD) : {
+ *(.rel.dyn)
+ }
+
+ .dynsym : {
+ *(.dynsym)
+ }
+
+ .dynbss : {
+ *(.dynbss)
+ }
+
+ .dynstr : {
+ *(.dynstr)
+ }
+
+ .dynamic : {
+ *(.dynamic)
+ }
+
+ .plt : {
+ *(.plt)
+ }
+
+ .interp : {
+ *(.interp)
+ }
+
+ .gnu : {
+ *(.gnu*)
+ }
+
+ .MIPS.stubs : {
+ *(.MIPS.stubs)
+ }
+
+ .hash : {
+ *(.hash)
+ }
+}
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index a94b745..2f04d73 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,6 +4,7 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
index e31f601..a934a58 100644
--- a/arch/mips/dts/ap121.dts
+++ b/arch/mips/dts/ap121.dts
@@ -41,3 +41,8 @@
reg = <0>;
};
};
+
+&gmac0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 00896b2..971f13e 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -75,7 +75,7 @@
};
gmac0: eth@0x19000000 {
- compatible = "qca,ag7240-mac";
+ compatible = "qca,ag933x-mac";
reg = <0x19000000 0x200>;
phy = <&phy0>;
phy-mode = "rmii";
@@ -92,7 +92,7 @@
};
gmac1: eth@0x1a000000 {
- compatible = "qca,ag7240-mac";
+ compatible = "qca,ag933x-mac";
reg = <0x1a000000 0x200>;
phy = <&phy0>;
phy-mode = "rgmii";
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
new file mode 100644
index 0000000..d339229
--- /dev/null
+++ b/arch/mips/dts/mti,malta.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000; /* Exception vectors */
+/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mti,malta";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ isa@0 {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0x1000>;
+
+ uart0: serial@3f8 {
+ compatible = "ns16550a";
+
+ reg = <1 0x3f8 0x40>;
+ reg-shift = <0>;
+
+ clock-frequency = <1843200>;
+
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 806bd26..0cea581 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -12,4 +12,11 @@
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 3f230b0..37f8ed5 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -15,14 +15,6 @@
#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
unsigned long io_port_base;
#endif
-#ifdef CONFIG_JZSOC
- /* There are other clocks in the jz4740 */
- unsigned long per_clk; /* Peripheral bus clock */
- unsigned long dev_clk; /* Device clock */
- unsigned long sys_clk;
- unsigned long tbl;
- unsigned long lastinc;
-#endif
#ifdef CONFIG_ARCH_ATH79
unsigned long id;
unsigned long soc;
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 723a60a..5b86386 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -92,11 +92,8 @@
#ifdef CONFIG_64BIT
if (addr < CKSEG0)
return XPHYSADDR(addr);
-
- return CPHYSADDR(addr);
-#else
- return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
+ return CPHYSADDR(addr);
}
/*
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
deleted file mode 100644
index 7a7cfff..0000000
--- a/arch/mips/include/asm/jz4740.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
- * head file for Ingenic Semiconductor's JZ4740 CPU.
- */
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-/* Boot ROM Specification */
-/* NOR Boot config */
-#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
-#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
-#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
-/* NAND Boot config */
-#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
-#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
-
-/* 1st-level interrupts */
-#define JZ4740_IRQ_I2C 1
-#define JZ4740_IRQ_UHC 3
-#define JZ4740_IRQ_UART0 9
-#define JZ4740_IRQ_SADC 12
-#define JZ4740_IRQ_MSC 14
-#define JZ4740_IRQ_RTC 15
-#define JZ4740_IRQ_SSI 16
-#define JZ4740_IRQ_CIM 17
-#define JZ4740_IRQ_AIC 18
-#define JZ4740_IRQ_ETH 19
-#define JZ4740_IRQ_DMAC 20
-#define JZ4740_IRQ_TCU2 21
-#define JZ4740_IRQ_TCU1 22
-#define JZ4740_IRQ_TCU0 23
-#define JZ4740_IRQ_UDC 24
-#define JZ4740_IRQ_GPIO3 25
-#define JZ4740_IRQ_GPIO2 26
-#define JZ4740_IRQ_GPIO1 27
-#define JZ4740_IRQ_GPIO0 28
-#define JZ4740_IRQ_IPU 29
-#define JZ4740_IRQ_LCD 30
-/* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
-#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
-
-/* Register Definitions */
-#define JZ4740_CPM_BASE 0x10000000
-#define JZ4740_INTC_BASE 0x10001000
-#define JZ4740_TCU_BASE 0x10002000
-#define JZ4740_WDT_BASE 0x10002000
-#define JZ4740_RTC_BASE 0x10003000
-#define JZ4740_GPIO_BASE 0x10010000
-#define JZ4740_AIC_BASE 0x10020000
-#define JZ4740_ICDC_BASE 0x10020000
-#define JZ4740_MSC_BASE 0x10021000
-#define JZ4740_UART0_BASE 0x10030000
-#define JZ4740_I2C_BASE 0x10042000
-#define JZ4740_SSI_BASE 0x10043000
-#define JZ4740_SADC_BASE 0x10070000
-#define JZ4740_EMC_BASE 0x13010000
-#define JZ4740_DMAC_BASE 0x13020000
-#define JZ4740_UHC_BASE 0x13030000
-#define JZ4740_UDC_BASE 0x13040000
-#define JZ4740_LCD_BASE 0x13050000
-#define JZ4740_SLCD_BASE 0x13050000
-#define JZ4740_CIM_BASE 0x13060000
-#define JZ4740_ETH_BASE 0x13100000
-
-/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
-
-/* GPIO (General-Purpose I/O Ports) */
-/* = 0,1,2,3 */
-#define GPIO_PXPIN(n) \
- (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
-#define GPIO_PXDAT(n) \
- (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
-#define GPIO_PXDATS(n) \
- (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
-#define GPIO_PXDATC(n) \
- (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
-#define GPIO_PXIM(n) \
- (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
-#define GPIO_PXIMS(n) \
- (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
-#define GPIO_PXIMC(n) \
- (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
-#define GPIO_PXPE(n) \
- (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
-#define GPIO_PXPES(n) \
- (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
-#define GPIO_PXPEC(n) \
- (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
-#define GPIO_PXFUN(n) \
- (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
-#define GPIO_PXFUNS(n) \
- (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
-#define GPIO_PXFUNC(n) \
- (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
-#define GPIO_PXSEL(n) \
- (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
-#define GPIO_PXSELS(n) \
- (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
-#define GPIO_PXSELC(n) \
- (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
-#define GPIO_PXDIR(n) \
- (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
-#define GPIO_PXDIRS(n) \
- (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
-#define GPIO_PXDIRC(n) \
- (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
-#define GPIO_PXTRG(n) \
- (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
-#define GPIO_PXTRGS(n) \
- (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
-#define GPIO_PXTRGC(n) \
- (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT 24
-#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT 20
-#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT 16
-#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT 12
-#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT 8
-#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT 6
-#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
- #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM (1 << 3)
-#define EMC_SMCR_BL_BIT 1
-#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
- #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT (1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT 8
-#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT 0
-#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3 (1 << 5)
-#define EMC_NFCSR_NFE3 (1 << 4)
-#define EMC_NFCSR_NFCE2 (1 << 3)
-#define EMC_NFCSR_NFE2 (1 << 2)
-#define EMC_NFCSR_NFCE1 (1 << 1)
-#define EMC_NFCSR_NFE1 (1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */
-#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT 16
-#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT 8
-#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT 0
-#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */
-#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */
-#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */
-#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */
-#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT 31
-#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT 26
-#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
- #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE (1 << 25)
-#define EMC_DMCR_RFSH (1 << 24)
-#define EMC_DMCR_MRSET (1 << 23)
-#define EMC_DMCR_RA_BIT 20
-#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
- #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT 19
-#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM (1 << 18)
-#define EMC_DMCR_EPIN (1 << 17)
-#define EMC_DMCR_TRAS_BIT 13
-#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT 11
-#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT 8
-#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT 5
-#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT 2
-#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT 0
-#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF (1 << 7)
-#define EMC_RTCSR_CKS_BIT 0
-#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
- #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT 8
-#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT 0
-#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
-#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
- #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
-#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
- #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT 3 /* Burst Type */
-#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
- #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
- #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT 0 /* Burst Length */
-#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
- #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
- (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
- (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
-#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
-#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
-#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
-#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
-#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT 16
-#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT 0
-#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD (1 << 0) /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT 5
-#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT 5
-#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
-#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
-#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS (1 << 31)
-#define CPM_CPCCR_CLKOEN (1 << 30)
-#define CPM_CPCCR_UCS (1 << 29)
-#define CPM_CPCCR_UDIV_BIT 23
-#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE (1 << 22)
-#define CPM_CPCCR_PCS (1 << 21)
-#define CPM_CPCCR_LDIV_BIT 16
-#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT 12
-#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT 8
-#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT 4
-#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT 0
-#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT 0
-#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT 0
-#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT 0
-#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT 23
-#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT 18
-#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT 16
-#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS (1 << 10)
-#define CPM_CPPCR_PLLBP (1 << 9)
-#define CPM_CPPCR_PLLEN (1 << 8)
-#define CPM_CPPCR_PLLST_BIT 0
-#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT 3
-#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON (1 << 2)
-#define CPM_LCR_LPM_BIT 0
-#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1 (1 << 15)
-#define CPM_CLKGR_UHC (1 << 14)
-#define CPM_CLKGR_IPU (1 << 13)
-#define CPM_CLKGR_DMAC (1 << 12)
-#define CPM_CLKGR_UDC (1 << 11)
-#define CPM_CLKGR_LCD (1 << 10)
-#define CPM_CLKGR_CIM (1 << 9)
-#define CPM_CLKGR_SADC (1 << 8)
-#define CPM_CLKGR_MSC (1 << 7)
-#define CPM_CLKGR_AIC1 (1 << 6)
-#define CPM_CLKGR_AIC2 (1 << 5)
-#define CPM_CLKGR_SSI (1 << 4)
-#define CPM_CLKGR_I2C (1 << 3)
-#define CPM_CLKGR_RTC (1 << 2)
-#define CPM_CLKGR_TCU (1 << 1)
-#define CPM_CLKGR_UART0 (1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT 8
-#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_UDCPHY_ENABLE (1 << 6)
-#define CPM_SCR_USBPHY_DISABLE (1 << 7)
-#define CPM_SCR_OSC_ENABLE (1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD (1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT 0
-#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT 0
-#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW (0 << 2)
-#define CPM_HWCR_WLE_HIGH (1 << 2)
-#define CPM_HWCR_PIN_WAKEUP (1 << 1)
-#define CPM_HWCR_RTC_WAKEUP (1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN (1 << 1)
-#define CPM_HWSR_WSR_RTC (1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR (1 << 2)
-#define CPM_RSR_WR (1 << 1)
-#define CPM_RSR_PR (1 << 0)
-
-/* Register definitions */
-#define TCU_TCSR_PWM_SD (1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
-#define TCU_TCSR_PWM_EN (1 << 7)
-#define TCU_TCSR_PRESCALE_BIT 3
-#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN (1 << 2)
-#define TCU_TCSR_RTC_EN (1 << 1)
-#define TCU_TCSR_PCK_EN (1 << 0)
-
-#define TCU_TER_TCEN5 (1 << 5)
-#define TCU_TER_TCEN4 (1 << 4)
-#define TCU_TER_TCEN3 (1 << 3)
-#define TCU_TER_TCEN2 (1 << 2)
-#define TCU_TER_TCEN1 (1 << 1)
-#define TCU_TER_TCEN0 (1 << 0)
-
-#define TCU_TESR_TCST5 (1 << 5)
-#define TCU_TESR_TCST4 (1 << 4)
-#define TCU_TESR_TCST3 (1 << 3)
-#define TCU_TESR_TCST2 (1 << 2)
-#define TCU_TESR_TCST1 (1 << 1)
-#define TCU_TESR_TCST0 (1 << 0)
-
-#define TCU_TECR_TCCL5 (1 << 5)
-#define TCU_TECR_TCCL4 (1 << 4)
-#define TCU_TECR_TCCL3 (1 << 3)
-#define TCU_TECR_TCCL2 (1 << 2)
-#define TCU_TECR_TCCL1 (1 << 1)
-#define TCU_TECR_TCCL0 (1 << 0)
-
-#define TCU_TFR_HFLAG5 (1 << 21)
-#define TCU_TFR_HFLAG4 (1 << 20)
-#define TCU_TFR_HFLAG3 (1 << 19)
-#define TCU_TFR_HFLAG2 (1 << 18)
-#define TCU_TFR_HFLAG1 (1 << 17)
-#define TCU_TFR_HFLAG0 (1 << 16)
-#define TCU_TFR_FFLAG5 (1 << 5)
-#define TCU_TFR_FFLAG4 (1 << 4)
-#define TCU_TFR_FFLAG3 (1 << 3)
-#define TCU_TFR_FFLAG2 (1 << 2)
-#define TCU_TFR_FFLAG1 (1 << 1)
-#define TCU_TFR_FFLAG0 (1 << 0)
-
-#define TCU_TFSR_HFLAG5 (1 << 21)
-#define TCU_TFSR_HFLAG4 (1 << 20)
-#define TCU_TFSR_HFLAG3 (1 << 19)
-#define TCU_TFSR_HFLAG2 (1 << 18)
-#define TCU_TFSR_HFLAG1 (1 << 17)
-#define TCU_TFSR_HFLAG0 (1 << 16)
-#define TCU_TFSR_FFLAG5 (1 << 5)
-#define TCU_TFSR_FFLAG4 (1 << 4)
-#define TCU_TFSR_FFLAG3 (1 << 3)
-#define TCU_TFSR_FFLAG2 (1 << 2)
-#define TCU_TFSR_FFLAG1 (1 << 1)
-#define TCU_TFSR_FFLAG0 (1 << 0)
-
-#define TCU_TFCR_HFLAG5 (1 << 21)
-#define TCU_TFCR_HFLAG4 (1 << 20)
-#define TCU_TFCR_HFLAG3 (1 << 19)
-#define TCU_TFCR_HFLAG2 (1 << 18)
-#define TCU_TFCR_HFLAG1 (1 << 17)
-#define TCU_TFCR_HFLAG0 (1 << 16)
-#define TCU_TFCR_FFLAG5 (1 << 5)
-#define TCU_TFCR_FFLAG4 (1 << 4)
-#define TCU_TFCR_FFLAG3 (1 << 3)
-#define TCU_TFCR_FFLAG2 (1 << 2)
-#define TCU_TFCR_FFLAG1 (1 << 1)
-#define TCU_TFCR_FFLAG0 (1 << 0)
-
-#define TCU_TMR_HMASK5 (1 << 21)
-#define TCU_TMR_HMASK4 (1 << 20)
-#define TCU_TMR_HMASK3 (1 << 19)
-#define TCU_TMR_HMASK2 (1 << 18)
-#define TCU_TMR_HMASK1 (1 << 17)
-#define TCU_TMR_HMASK0 (1 << 16)
-#define TCU_TMR_FMASK5 (1 << 5)
-#define TCU_TMR_FMASK4 (1 << 4)
-#define TCU_TMR_FMASK3 (1 << 3)
-#define TCU_TMR_FMASK2 (1 << 2)
-#define TCU_TMR_FMASK1 (1 << 1)
-#define TCU_TMR_FMASK0 (1 << 0)
-
-#define TCU_TMSR_HMST5 (1 << 21)
-#define TCU_TMSR_HMST4 (1 << 20)
-#define TCU_TMSR_HMST3 (1 << 19)
-#define TCU_TMSR_HMST2 (1 << 18)
-#define TCU_TMSR_HMST1 (1 << 17)
-#define TCU_TMSR_HMST0 (1 << 16)
-#define TCU_TMSR_FMST5 (1 << 5)
-#define TCU_TMSR_FMST4 (1 << 4)
-#define TCU_TMSR_FMST3 (1 << 3)
-#define TCU_TMSR_FMST2 (1 << 2)
-#define TCU_TMSR_FMST1 (1 << 1)
-#define TCU_TMSR_FMST0 (1 << 0)
-
-#define TCU_TMCR_HMCL5 (1 << 21)
-#define TCU_TMCR_HMCL4 (1 << 20)
-#define TCU_TMCR_HMCL3 (1 << 19)
-#define TCU_TMCR_HMCL2 (1 << 18)
-#define TCU_TMCR_HMCL1 (1 << 17)
-#define TCU_TMCR_HMCL0 (1 << 16)
-#define TCU_TMCR_FMCL5 (1 << 5)
-#define TCU_TMCR_FMCL4 (1 << 4)
-#define TCU_TMCR_FMCL3 (1 << 3)
-#define TCU_TMCR_FMCL2 (1 << 2)
-#define TCU_TMCR_FMCL1 (1 << 1)
-#define TCU_TMCR_FMCL0 (1 << 0)
-
-#define TCU_TSR_WDTS (1 << 16)
-#define TCU_TSR_STOP5 (1 << 5)
-#define TCU_TSR_STOP4 (1 << 4)
-#define TCU_TSR_STOP3 (1 << 3)
-#define TCU_TSR_STOP2 (1 << 2)
-#define TCU_TSR_STOP1 (1 << 1)
-#define TCU_TSR_STOP0 (1 << 0)
-
-#define TCU_TSSR_WDTSS (1 << 16)
-#define TCU_TSSR_STPS5 (1 << 5)
-#define TCU_TSSR_STPS4 (1 << 4)
-#define TCU_TSSR_STPS3 (1 << 3)
-#define TCU_TSSR_STPS2 (1 << 2)
-#define TCU_TSSR_STPS1 (1 << 1)
-#define TCU_TSSR_STPS0 (1 << 0)
-
-#define TCU_TSSR_WDTSC (1 << 16)
-#define TCU_TSSR_STPC5 (1 << 5)
-#define TCU_TSSR_STPC4 (1 << 4)
-#define TCU_TSSR_STPC3 (1 << 3)
-#define TCU_TSSR_STPC2 (1 << 2)
-#define TCU_TSSR_STPC1 (1 << 1)
-#define TCU_TSSR_STPC0 (1 << 0)
-
-/* Register definition */
-#define WDT_TCSR_PRESCALE_BIT 3
-#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
- #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN (1 << 2)
-#define WDT_TCSR_RTC_EN (1 << 1)
-#define WDT_TCSR_PCK_EN (1 << 0)
-#define WDT_TCER_TCEN (1 << 0)
-
-/*
- * Define macros for UART_IER
- * UART Interrupt Enable Register
- */
-#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
-#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
-#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
-#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UART_ISR
- * UART Interrupt Status Register
- */
-#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
-#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
-#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
-#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-/* FIFO mode select, set when UART_FCR.FE is set to 1 */
-#define UART_ISR_FFMS (3 << 6)
-#define UART_ISR_FFMS_NO_FIFO (0 << 6)
-#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
-
-/*
- * Define macros for UART_FCR
- * UART FIFO Control Register
- */
-#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
-#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
-#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
-#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
-#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
-#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
-#define UART_FCR_RTRG_1 (0 << 6)
-#define UART_FCR_RTRG_4 (1 << 6)
-#define UART_FCR_RTRG_8 (2 << 6)
-#define UART_FCR_RTRG_15 (3 << 6)
-
-/*
- * Define macros for UART_LCR
- * UART Line Control Register
- */
-#define UART_LCR_WLEN (3 << 0) /* word length */
-#define UART_LCR_WLEN_5 (0 << 0)
-#define UART_LCR_WLEN_6 (1 << 0)
-#define UART_LCR_WLEN_7 (2 << 0)
-#define UART_LCR_WLEN_8 (3 << 0)
-#define UART_LCR_STOP (1 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_1 (0 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_2 (1 << 2)
- /* 0: 1 stop bit when word length is 5,6,7,8
- 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-
-#define UART_LCR_PE (1 << 3) /* 0: parity disable */
-#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
-#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
-#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
-/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
-#define UART_LCR_DLAB (1 << 7)
-
-/*
- * Define macros for UART_LSR
- * UART Line Status Register
- */
-/* 0: receive FIFO is empty 1: receive data is ready */
-#define UART_LSR_DR (1 << 0)
-/* 0: no overrun error */
-#define UART_LSR_ORER (1 << 1)
-/* 0: no parity error */
-#define UART_LSR_PER (1 << 2)
-/* 0; no framing error */
-#define UART_LSR_FER (1 << 3)
-/* 0: no break detected 1: receive a break signal */
-#define UART_LSR_BRK (1 << 4)
-/* 1: transmit FIFO half "empty" */
-#define UART_LSR_TDRQ (1 << 5)
-/* 1: transmit FIFO and shift registers empty */
-#define UART_LSR_TEMT (1 << 6)
-/* 0: no receive error 1: receive error in FIFO mode */
-#define UART_LSR_RFER (1 << 7)
-
-/*
- * Define macros for UART_MCR
- * UART Modem Control Register
- */
-#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
-#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
-/* 0: UART_MSR.RI is set to 0 and RI_ input high */
-#define UART_MCR_OUT1 (1 << 2)
-/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
-#define UART_MCR_OUT2 (1 << 3)
-#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
-#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UART_MSR
- * UART Modem Status Register
- */
-#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */
-#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */
-#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */
-#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */
-#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
-#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
-#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
-#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
-#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
- 1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-/* MSC Clock and Control Register (MSC_STRPCL) */
-#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
-#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
-#define MSC_STRPCL_START_READWAIT (1 << 5)
-#define MSC_STRPCL_STOP_READWAIT (1 << 4)
-#define MSC_STRPCL_RESET (1 << 3)
-#define MSC_STRPCL_START_OP (1 << 2)
-#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
-#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-
-/* MSC Status Register (MSC_STAT) */
-#define MSC_STAT_IS_RESETTING (1 << 15)
-#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
-#define MSC_STAT_PRG_DONE (1 << 13)
-#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
-#define MSC_STAT_END_CMD_RES (1 << 11)
-#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
-#define MSC_STAT_IS_READWAIT (1 << 9)
-#define MSC_STAT_CLK_EN (1 << 8)
-#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
-#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
-#define MSC_STAT_CRC_RES_ERR (1 << 5)
-#define MSC_STAT_CRC_READ_ERROR (1 << 4)
-#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
-#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No error on transmission of data */
- #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* Card observed erroneous transmission of data */
- #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No CRC status is sent back */
- #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-#define MSC_STAT_TIME_OUT_RES (1 << 1)
-#define MSC_STAT_TIME_OUT_READ (1 << 0)
-
-/* MSC Bus Clock Control Register (MSC_CLKRT) */
-#define MSC_CLKRT_CLK_RATE_BIT 0
-#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT)
- #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
-
-/* MSC Command Sequence Control Register (MSC_CMDAT) */
-#define MSC_CMDAT_IO_ABORT (1 << 11)
-#define MSC_CMDAT_BUS_WIDTH_BIT 9
-#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_DMA_EN (1 << 8)
-#define MSC_CMDAT_INIT (1 << 7)
-#define MSC_CMDAT_BUSY (1 << 6)
-#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
-#define MSC_CMDAT_WRITE (1 << 4)
-#define MSC_CMDAT_READ (0 << 4)
-#define MSC_CMDAT_DATA_EN (1 << 3)
-#define MSC_CMDAT_RESPONSE_BIT 0
-#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
-
-/* MSC Interrupts Mask Register (MSC_IMASK) */
-#define MSC_IMASK_SDIO (1 << 7)
-#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
-#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
-#define MSC_IMASK_END_CMD_RES (1 << 2)
-#define MSC_IMASK_PRG_DONE (1 << 1)
-#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
-
-#ifndef __ASSEMBLY__
-/* INTC (Interrupt Controller) */
-struct jz4740_intc {
- uint32_t isr; /* interrupt source register */
- uint32_t imr; /* interrupt mask register */
- uint32_t imsr; /* interrupt mask set register */
- uint32_t imcr; /* interrupt mask clear register */
- uint32_t ipr; /* interrupt pending register */
-};
-
-/* RTC */
-struct jz4740_rtc {
- uint32_t rcr; /* rtc control register */
- uint32_t rsr; /* rtc second register */
- uint32_t rsar; /* rtc second alarm register */
- uint32_t rgr; /* rtc regulator register */
- uint32_t hcr; /* hibernate control register */
- uint32_t hwfcr; /* hibernate wakeup filter counter reg */
- uint32_t hrcr; /* hibernate reset counter reg */
- uint32_t hwcr; /* hibernate wakeup control register */
- uint32_t hwrsr; /* hibernate wakeup status reg */
- uint32_t hspr; /* scratch pattern register */
-};
-
-/* CPM (Clock reset and Power control Management) */
-struct jz4740_cpm {
- uint32_t cpccr; /* 0x00 clock control reg */
- uint32_t lcr; /* 0x04 low power control reg */
- uint32_t rsr; /* 0x08 reset status reg */
- uint32_t pad00;
- uint32_t cppcr; /* 0x10 pll control reg */
- uint32_t pad01[3];
- uint32_t clkgr; /* 0x20 clock gate reg */
- uint32_t scr; /* 0x24 sleep control reg */
- uint32_t pad02[14];
- uint32_t i2scd; /* 0x60 I2S device clock divider reg */
- uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
- uint32_t msccdr; /* 0x68 MSC device clock divider reg */
- uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
- uint32_t uhcts; /* 0x70 UHC PHY test point reg */
- uint32_t ssicd; /* 0x74 SSI clock divider reg */
-};
-
-/* TCU (Timer Counter Unit) */
-struct jz4740_tcu {
- uint32_t pad00[4];
- uint32_t ter; /* 0x10 Timer Counter Enable Register */
- uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */
- uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */
- uint32_t tsr; /* 0x1C Timer Stop Register */
- uint32_t tfr; /* 0x20 Timer Flag Register */
- uint32_t tfsr; /* 0x24 Timer Flag Set Register */
- uint32_t tfcr; /* 0x28 Timer Flag Clear Register */
- uint32_t tssr; /* 0x2C Timer Stop Set Register */
- uint32_t tmr; /* 0x30 Timer Mask Register */
- uint32_t tmsr; /* 0x34 Timer Mask Set Register */
- uint32_t tmcr; /* 0x38 Timer Mask Clear Register */
- uint32_t tscr; /* 0x3C Timer Stop Clear Register */
- uint32_t tdfr0; /* 0x40 Timer Data Full Register */
- uint32_t tdhr0; /* 0x44 Timer Data Half Register */
- uint32_t tcnt0; /* 0x48 Timer Counter Register */
- uint32_t tcsr0; /* 0x4C Timer Control Register */
- uint32_t tdfr1; /* 0x50 */
- uint32_t tdhr1; /* 0x54 */
- uint32_t tcnt1; /* 0x58 */
- uint32_t tcsr1; /* 0x5C */
- uint32_t tdfr2; /* 0x60 */
- uint32_t tdhr2; /* 0x64 */
- uint32_t tcnt2; /* 0x68 */
- uint32_t tcsr2; /* 0x6C */
- uint32_t tdfr3; /* 0x70 */
- uint32_t tdhr3; /* 0x74 */
- uint32_t tcnt3; /* 0x78 */
- uint32_t tcsr3; /* 0x7C */
- uint32_t tdfr4; /* 0x80 */
- uint32_t tdhr4; /* 0x84 */
- uint32_t tcnt4; /* 0x88 */
- uint32_t tcsr4; /* 0x8C */
- uint32_t tdfr5; /* 0x90 */
- uint32_t tdhr5; /* 0x94 */
- uint32_t tcnt5; /* 0x98 */
- uint32_t tcsr5; /* 0x9C */
-};
-
-/* WDT (WatchDog Timer) */
-struct jz4740_wdt {
- uint16_t tdr; /* 0x00 watchdog timer data reg*/
- uint16_t pad00;
- uint8_t tcer; /* 0x04 watchdog counter enable reg*/
- uint8_t pad01[3];
- uint16_t tcnt; /* 0x08 watchdog timer counter*/
- uint16_t pad02;
- uint16_t tcsr; /* 0x0C watchdog timer control reg*/
- uint16_t pad03;
-};
-
-struct jz4740_uart {
- uint8_t rbr_thr_dllr;
- /* 0x00 R 8b receive buffer reg */
- /* 0x00 W 8b transmit hold reg */
- /* 0x00 RW 8b divisor latch low reg */
- uint8_t pad00[3];
- uint8_t dlhr_ier;
- /* 0x04 RW 8b divisor latch high reg */
- /* 0x04 RW 8b interrupt enable reg */
- uint8_t pad01[3];
- uint8_t iir_fcr;
- /* 0x08 R 8b interrupt identification reg */
- /* 0x08 W 8b FIFO control reg */
- uint8_t pad02[3];
- uint8_t lcr; /* 0x0C RW 8b Line control reg */
- uint8_t pad03[3];
- uint8_t mcr; /* 0x10 RW 8b modem control reg */
- uint8_t pad04[3];
- uint8_t lsr; /* 0x14 R 8b line status reg */
- uint8_t pad05[3];
- uint8_t msr; /* 0x18 R 8b modem status reg */
- uint8_t pad06[3];
- uint8_t spr; /* 0x1C RW 8b scratch pad reg */
- uint8_t pad07[3];
- uint8_t isr; /* 0x20 RW 8b infrared selection reg */
- uint8_t pad08[3];
- uint8_t umr; /* 0x24 RW 8b */
-};
-
-/* MSC */
-struct jz4740_msc {
- uint16_t strpcl;/* 0x00 */
- uint32_t stat; /* 0x04 */
- uint16_t clkrt; /* 0x08 */
- uint32_t cmdat; /* 0x0C */
- uint16_t resto; /* 0x10 */
- uint16_t rdto; /* 0x14 */
- uint16_t blklen;/* 0x18 */
- uint16_t nob; /* 0x1C */
- uint16_t snob; /* 0x20 */
- uint16_t imask; /* 0x24 */
- uint16_t ireg; /* 0x28 */
- uint8_t cmd; /* 0x2C */
- uint32_t arg; /* 0x30 */
- uint16_t res; /* 0x34 */
- uint32_t rxfifo;/* 0x38 */
- uint32_t txfifo;/* 0x3C */
-};
-
-/* External Memory Controller */
-struct jz4740_emc {
- uint32_t bcr; /* 0x00 BCR */
- uint32_t pad00[3];
- uint32_t smcr[5];
- /* x10 Static Memory Control Register 0 */
- /* x14 Static Memory Control Register 1 */
- /* x18 Static Memory Control Register 2 */
- /* x1c Static Memory Control Register 3 */
- /* x20 Static Memory Control Register 4 */
- uint32_t pad01[3];
- uint32_t sacr[5];
- /* x30 Static Memory Bank 0 Addr Config Reg */
- /* x34 Static Memory Bank 1 Addr Config Reg */
- /* x38 Static Memory Bank 2 Addr Config Reg */
- /* x3c Static Memory Bank 3 Addr Config Reg */
- /* x40 Static Memory Bank 4 Addr Config Reg */
- uint32_t pad02[3];
- uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
-
- uint32_t pad03[11];
- uint32_t dmcr; /* x80 DRAM Control Register */
- uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
- uint16_t pad04;
- uint16_t rtcnt; /* x88 Refresh Timer Counter */
- uint16_t pad05;
- uint16_t rtcor; /* x8c Refresh Time Constant Register */
- uint16_t pad06;
- uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
- uint32_t pad07[27];
- uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
- uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
- uint8_t nfpar[12];
- /* x108 NAND Flash RS Parity 0 Register */
- /* x10c NAND Flash RS Parity 1 Register */
- /* x110 NAND Flash RS Parity 2 Register */
- uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
- uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
- uint32_t nferr[4];
- /* x11c NAND Flash RS Error Report 0 Register */
- /* x120 NAND Flash RS Error Report 1 Register */
- /* x124 NAND Flash RS Error Report 2 Register */
- /* x128 NAND Flash RS Error Report 3 Register */
-};
-
-#define __gpio_as_nand() \
-do { \
- writel(0x02018000, GPIO_PXFUNS(1)); \
- writel(0x02018000, GPIO_PXSELC(1)); \
- writel(0x02018000, GPIO_PXPES(1)); \
- writel(0x30000000, GPIO_PXFUNS(2)); \
- writel(0x30000000, GPIO_PXSELC(2)); \
- writel(0x30000000, GPIO_PXPES(2)); \
- writel(0x40000000, GPIO_PXFUNC(2)); \
- writel(0x40000000, GPIO_PXSELC(2)); \
- writel(0x40000000, GPIO_PXDIRC(2)); \
- writel(0x40000000, GPIO_PXPES(2)); \
- writel(0x00400000, GPIO_PXFUNS(1)); \
- writel(0x00400000, GPIO_PXSELC(1)); \
-} while (0)
-
-#define __gpio_as_sdram_16bit_4720() \
-do { \
- writel(0x5442bfaa, GPIO_PXFUNS(0)); \
- writel(0x5442bfaa, GPIO_PXSELC(0)); \
- writel(0x5442bfaa, GPIO_PXPES(0)); \
- writel(0x81f9ffff, GPIO_PXFUNS(1)); \
- writel(0x81f9ffff, GPIO_PXSELC(1)); \
- writel(0x81f9ffff, GPIO_PXPES(1)); \
- writel(0x01000000, GPIO_PXFUNS(2)); \
- writel(0x01000000, GPIO_PXSELC(2)); \
- writel(0x01000000, GPIO_PXPES(2)); \
-} while (0)
-
-#define __gpio_as_lcd_18bit() \
-do { \
- writel(0x003fffff, GPIO_PXFUNS(2)); \
- writel(0x003fffff, GPIO_PXSELC(2)); \
- writel(0x003fffff, GPIO_PXPES(2)); \
-} while (0)
-
-/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
-#define __gpio_as_msc() \
-do { \
- writel(0x00003f00, GPIO_PXFUNS(3)); \
- writel(0x00003f00, GPIO_PXSELC(3)); \
- writel(0x00003f00, GPIO_PXPES(3)); \
-} while (0)
-
-#define __gpio_get_port(p) (readl(GPIO_PXPIN(p)))
-
-#define __gpio_disable_pull(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXPES(p)); \
-} while (0)
-
-#define __gpio_enable_pull(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel(1 << (o), GPIO_PXPEC(p)); \
-} while (0)
-
-#define __gpio_port_as_output(p, o) \
-do { \
- writel(1 << (o), GPIO_PXFUNC(p)); \
- writel(1 << (o), GPIO_PXSELC(p)); \
- writel(1 << (o), GPIO_PXDIRS(p)); \
-} while (0)
-
-#define __gpio_port_as_input(p, o) \
-do { \
- writel(1 << (o), GPIO_PXFUNC(p)); \
- writel(1 << (o), GPIO_PXSELC(p)); \
- writel(1 << (o), GPIO_PXDIRC(p)); \
-} while (0)
-
-#define __gpio_as_output(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- __gpio_port_as_output(p, o); \
-} while (0)
-
-#define __gpio_as_input(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- __gpio_port_as_input(p, o); \
-} while (0)
-
-#define __gpio_set_pin(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXDATS(p)); \
-} while (0)
-
-#define __gpio_clear_pin(n) \
-do { \
- unsigned int p, o; \
- p = (n) / 32; \
- o = (n) % 32; \
- writel((1 << o), GPIO_PXDATC(p)); \
-} while (0)
-
-#define __gpio_get_pin(n) \
-({ \
- unsigned int p, o, v; \
- p = (n) / 32; \
- o = (n) % 32; \
- if (__gpio_get_port(p) & (1 << o)) \
- v = 1; \
- else \
- v = 0; \
- v; \
-})
-
-#define __gpio_as_uart0() \
-do { \
- writel(0x06000000, GPIO_PXFUNS(3)); \
- writel(0x06000000, GPIO_PXSELS(3)); \
- writel(0x06000000, GPIO_PXPES(3)); \
-} while (0)
-
-#define __gpio_jtag_to_uart0() \
-do { \
- writel(0x80000000, GPIO_PXSELS(2)); \
-} while (0)
-
-/* Clock Control Register */
-#define __cpm_get_pllm() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \
- >> CPM_CPPCR_PLLM_BIT)
-#define __cpm_get_plln() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \
- >> CPM_CPPCR_PLLN_BIT)
-#define __cpm_get_pllod() \
- ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \
- >> CPM_CPPCR_PLLOD_BIT)
-#define __cpm_get_hdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \
- >> CPM_CPCCR_HDIV_BIT)
-#define __cpm_get_pdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \
- >> CPM_CPCCR_PDIV_BIT)
-#define __cpm_get_cdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \
- >> CPM_CPCCR_CDIV_BIT)
-#define __cpm_get_mdiv() \
- ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \
- >> CPM_CPCCR_MDIV_BIT)
-
-static inline unsigned int __cpm_get_pllout(void)
-{
- uint32_t m, n, no, pllout;
- uint32_t od[4] = {1, 2, 2, 4};
-
- struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- uint32_t cppcr = readl(&cpm->cppcr);
-
- if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
- m = __cpm_get_pllm() + 2;
- n = __cpm_get_plln() + 2;
- no = od[__cpm_get_pllod()];
- pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
- } else
- pllout = CONFIG_SYS_EXTAL;
-
- return pllout;
-}
-
-extern void pll_init(void);
-extern void sdram_init(void);
-extern void calc_clocks(void);
-extern void rtc_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __JZ4740_H__ */
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index a5b2fc0..1f527bb 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -1,23 +1,8 @@
/*
* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
*/
-static inline unsigned long bss_start(void)
-{
- extern char __bss_start[];
- return (unsigned long) &__bss_start;
-}
-
-static inline unsigned long bss_end(void)
-{
- extern ulong __bss_end;
- return (unsigned long) &__bss_end;
-}
+#ifndef _U_BOOT_MIPS_H_
+#define _U_BOOT_MIPS_H_
-static inline unsigned long image_copy_end(void)
-{
- extern char __image_copy_end[];
- return (unsigned long) &__image_copy_end;
-}
+#endif /* _U_BOOT_MIPS_H_ */
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 4909a2a..af03e8d 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -15,25 +15,9 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
-
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else /* !CONFIG_SYS_GENERIC_BOARD */
-
-typedef struct bd_info {
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_MIPS
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005..5f520c0 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,23 +9,13 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-
static inline unsigned long icache_line_size(void)
{
- return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
- return CONFIG_SYS_CACHELINE_SIZE;
-}
+ unsigned long conf1, il;
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+ return CONFIG_SYS_ICACHE_LINE_SIZE;
-static inline unsigned long icache_line_size(void)
-{
- unsigned long conf1, il;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
@@ -36,6 +26,10 @@
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
+
+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+ return CONFIG_SYS_DCACHE_LINE_SIZE;
+
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
@@ -43,84 +37,59 @@
return 2 << dl;
}
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
+#define cache_loop(start, end, lsize, ops...) do { \
+ const void *addr = (const void *)(start & ~(lsize - 1)); \
+ const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
+ const unsigned int cache_ops[] = { ops }; \
+ unsigned int i; \
+ \
+ for (; addr <= aend; addr += lsize) { \
+ for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
+ mips_cache(cache_ops[i], addr); \
+ } \
+} while (0)
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
- const void *addr, *aend;
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
- addr = (const void *)(start_addr & ~(dlsize - 1));
- aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
if (ilsize == dlsize) {
/* flush I-cache & D-cache simultaneously */
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- mips_cache(HIT_INVALIDATE_I, addr);
- if (addr == aend)
- break;
- addr += dlsize;
- }
+ cache_loop(start_addr, start_addr + size, ilsize,
+ HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
return;
}
/* flush D-cache */
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- if (addr == aend)
- break;
- addr += dlsize;
- }
+ cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
/* flush I-cache */
- addr = (const void *)(start_addr & ~(ilsize - 1));
- aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
- while (1) {
- mips_cache(HIT_INVALIDATE_I, addr);
- if (addr == aend)
- break;
- addr += ilsize;
- }
+ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- const void *addr = (const void *)(start_addr & ~(lsize - 1));
- const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- const void *addr = (const void *)(start_addr & ~(lsize - 1));
- const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
- while (1) {
- mips_cache(HIT_INVALIDATE_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
}
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3a..bc8ab27 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,16 +99,16 @@
*
*/
LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
- li t8, CONFIG_SYS_CACHELINE_SIZE
+ li t8, CONFIG_SYS_ICACHE_LINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
- li t9, CONFIG_SYS_CACHELINE_SIZE
+ li t9, CONFIG_SYS_DCACHE_LINE_SIZE
#else
l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
@@ -116,7 +116,7 @@
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
index 9fcd496..6d98efc 100644
--- a/arch/mips/mach-ath79/ar933x/clk.c
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -17,7 +17,7 @@
{
u32 val;
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 91452bc..2a25e23 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -10,7 +10,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +114,7 @@
writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & AR933X_BOOTSTRAP_DDR2) {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
@@ -268,6 +268,8 @@
dir = 1;
tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
val = tap;
+ upper = tap;
+ lower = tap;
while (!done) {
err = 0;
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9c65184..9b41d3d 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -119,7 +119,7 @@
writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
/* Test for 40MHz XTAL */
- reg = get_bootstrap();
+ reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
xtal_40 = 1;
cpu_srif = 0x41c00000;
@@ -214,7 +214,7 @@
{
u32 val;
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & AR934X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
index 4621d58..2ba1efa 100644
--- a/arch/mips/mach-ath79/ar934x/ddr.c
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -11,7 +11,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,7 +45,7 @@
ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
- reg = get_bootstrap();
+ reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
memtype = AR934X_DDR1;
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a8e51cb..7b48524 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
@@ -660,6 +661,7 @@
#define AR933X_RESET_GE1_MDIO BIT(23)
#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14)
#define AR933X_RESET_GE1_MAC BIT(13)
#define AR933X_RESET_WMAC BIT(11)
#define AR933X_RESET_GE0_MAC BIT(9)
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 17af082..582c028 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -140,6 +140,7 @@
return soc_is_tp9343() || soc_is_qca9561();
}
+u32 ath79_get_bootstrap(void);
int ath79_eth_reset(void);
int ath79_usb_reset(void);
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
deleted file mode 100644
index c383bfe..0000000
--- a/arch/mips/mach-ath79/include/mach/reset.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_MACH_RESET_H
-#define __ASM_MACH_RESET_H
-
-#include <linux/types.h>
-
-u32 get_bootstrap(void);
-
-#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
index ef0a28e..533356c 100644
--- a/arch/mips/mach-ath79/qca953x/clk.c
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -17,7 +17,7 @@
{
u32 val;
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
index ac0130c..c6049d8 100644
--- a/arch/mips/mach-ath79/qca953x/ddr.c
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -10,7 +10,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -226,7 +226,7 @@
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & QCA953X_BOOTSTRAP_DDR1) {
writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
udelay(10);
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb..073a179 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -45,7 +45,7 @@
/* NOP */;
}
-u32 get_bootstrap(void)
+u32 ath79_get_bootstrap(void)
{
void __iomem *base;
u32 reg = 0;
@@ -81,14 +81,15 @@
MAP_NOCACHE);
const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
- AR933X_RESET_ETH_SWITCH;
+ AR933X_RESET_ETH_SWITCH |
+ AR933X_RESET_ETH_SWITCH_ANALOG;
/* Clear MDIO slave EN bit. */
clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
mdelay(10);
/* Get Atheros S26 PHY out of reset. */
- clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
0x1f, 0x10);
mdelay(10);
@@ -135,6 +136,23 @@
return 0;
}
+static int eth_init_qca953x(void)
+{
+ void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+ QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+ QCA953X_RESET_ETH_SWITCH_ANALOG |
+ QCA953X_RESET_ETH_SWITCH;
+
+ setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+ clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+
+ return 0;
+}
+
int ath79_eth_reset(void)
{
/*
@@ -145,6 +163,8 @@
return eth_init_ar933x();
if (soc_is_ar934x())
return eth_init_ar934x();
+ if (soc_is_qca953x())
+ return eth_init_qca953x();
return -EINVAL;
}
@@ -184,6 +204,35 @@
return 0;
}
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+ void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+
+ clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ 0xf00, 0x200);
+ mdelay(10);
+
+ /* Ungate the USB block */
+ setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USBSUS_OVERRIDE);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_ANALOG);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_HOST);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+ mdelay(1);
+
+ return 0;
+}
+
int ath79_usb_reset(void)
{
void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -203,6 +252,8 @@
return usb_reset_ar933x(reset_regs);
if (soc_is_ar934x())
return usb_reset_ar934x(reset_regs);
+ if (soc_is_qca953x())
+ return usb_reset_qca953x(reset_regs);
return -EINVAL;
}
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index 79f72aa..a44f51a 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -12,7 +12,7 @@
#include <common.h>
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
@@ -35,4 +35,4 @@
*/
fdt_fixup_ethernet(blob);
}
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index dfa72d9..3a2f6ec 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -5,6 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += timer.o
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
deleted file mode 100644
index b7fbd2f..0000000
--- a/arch/openrisc/lib/board.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2011
- * Julius Baxter, julius@opencores.org
- *
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <stdio_dev.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#ifdef CONFIG_CMD_NAND
-#include <nand.h> /* cannot even include nand.h if it isnt configured */
-#endif
-
-#include <timestamp.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-extern int cache_init(void);
-
-/*
- * Initialization sequence
- */
-static int (* const init_sequence[])(void) = {
- cache_init,
- timer_init, /* initialize timer */
- env_init,
- serial_init,
- console_init_f,
- display_options,
- checkcpu,
- checkboard,
-};
-
-
-/***********************************************************************/
-void board_init(void)
-{
- bd_t *bd;
- int i;
-
- gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
-
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-
- gd->bd = (bd_t *)(gd+1); /* At end of global data */
- gd->baudrate = CONFIG_BAUDRATE;
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
- bd = gd->bd;
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- WATCHDOG_RESET();
- if (init_sequence[i]())
- hang();
- }
-
- WATCHDOG_RESET();
-
- /* The Malloc area is immediately below the monitor copy in RAM */
- mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
- WATCHDOG_RESET();
- bd->bi_flashsize = flash_init();
-#endif
-
-#ifdef CONFIG_CMD_NAND
- puts("NAND: ");
- nand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
- mmc_initialize(bd);
-#endif
-
- WATCHDOG_RESET();
- env_relocate();
-
- WATCHDOG_RESET();
- stdio_init();
- jumptable_init();
- console_init_r();
-
- WATCHDOG_RESET();
- interrupt_init();
-
-#if defined(CONFIG_BOARD_LATE_INIT)
- board_late_init();
-#endif
-
-#if defined(CONFIG_CMD_NET)
- puts("NET: ");
- eth_initialize();
-#endif
-
- /* main_loop */
- for (;;) {
- WATCHDOG_RESET();
- main_loop();
- }
-}
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
index 6451ea9..68c5f8a 100644
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -70,7 +70,7 @@
mddrc_config = &default_mddrc_config;
if (dram_init_seq == NULL) {
dram_init_seq = default_init_seq;
- seq_sz = sizeof(default_init_seq)/sizeof(u32);
+ seq_sz = ARRAY_SIZE(default_init_seq);
}
/* Initialize IO Control */
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index 7a463b5..84fabbd 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -96,7 +96,7 @@
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup(void *blob, bd_t *bd)
{
int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
@@ -117,7 +117,7 @@
do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
#endif
-#if defined(CONFIG_OF_IDE_FIXUP)
+#ifdef CONFIG_OF_IDE_FIXUP
if (!ide_device_present(0)) {
/* NO CF card detected -> delete ata node in DTS */
int nodeoffset = 0;
@@ -132,10 +132,10 @@
}
}
-#endif
+#endif /* CONFIG_OF_IDE_FIXUP */
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_MPC5xxx_FEC
/* Default initializations for FEC controllers. To override,
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 54793f0..b4c5543 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -83,8 +83,7 @@
* This function is called when the platform is build with SPL
* support from the main (full-blown) U-Boot. And the GD needs
* to get cleared (again) so that the following generic
- * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
- * initializes all variables correctly.
+ * board support code initializes all variables correctly.
*/
mr r3, r2 /* parameter 1: GD pointer */
li r4,0 /* parameter 2: value to fill */
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 6eed6f5..9f2be3c 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -284,7 +284,7 @@
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup (void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@@ -303,7 +303,7 @@
"clock-frequency", bd->bi_intfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
* Initializes on-chip ethernet controllers.
diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c
index a9bb5ad..55130f7 100644
--- a/arch/powerpc/cpu/mpc8260/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8260/cpu_init.c
@@ -253,7 +253,7 @@
RSR_ESRS, "External Soft"}, {
RSR_EHRS, "External Hard"}
};
- static int n = sizeof bits / sizeof bits[0];
+ static int n = ARRAY_SIZE(bits);
ulong rsr = gd->arch.reset_status;
int i;
char *sep;
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index 9bb395e..a11ad1e 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -362,7 +362,7 @@
struct eth_device* dev;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
@@ -432,7 +432,7 @@
{ offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
{ offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
};
-static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
+static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs);
typedef
struct {
@@ -449,7 +449,7 @@
{ offsetof(elbt_txeacc, un), "Underrun" },
{ offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
};
-static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
+static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs);
typedef
struct {
@@ -500,7 +500,7 @@
{ offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
{ offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
};
-static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
+static int epram_ndesc = ARRAY_SIZE(epram_descs);
/*
* given an elbt_prdesc array and an array of base addresses, print
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 0791043..f911275 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -484,7 +484,7 @@
RSR_SRS, "External/Internal Soft"}, {
RSR_HRS, "External/Internal Hard"}
};
- static int n = sizeof bits / sizeof bits[0];
+ static int n = ARRAY_SIZE(bits);
ulong rsr = gd->arch.reset_status;
int i;
char *sep;
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 2e91f51..5498c19 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -412,7 +412,7 @@
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
- if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
+ if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
/* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 14358ae..51f1bee 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -424,7 +424,7 @@
struct eth_device* dev;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 82a151a..4c51225 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -720,16 +720,39 @@
ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
sync
stw r4, 0(r3) /* invalidate L2 */
+ /* Poll till the bits are cleared */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
bne 1b
+
+ /* L2PE must be set before L2 cache is enabled */
+ lis r4, (L2CSR0_L2PE)@h
+ ori r4, r4, (L2CSR0_L2PE)@l
+ sync
+ stw r4, 0(r3) /* enable L2 parity/ECC error checking */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
ori r4, r4, (L2CSR0_L2REP_MODE)@l
sync
stw r4, 0(r3) /* enable L2 */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index ea4ab3a..f1ae358 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -137,7 +137,7 @@
struct ether_fcc_info_s *efis;
int i;
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
dev = malloc(sizeof(*dev));
if (dev == NULL)
@@ -879,7 +879,7 @@
/* Setup the pin configuration of the FEC(s)
*/
- for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
fec_pin_init(ether_fcc_info[i].ether_index);
}
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 5f5c720..4013a0c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -449,13 +449,6 @@
mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
PLB4Ax_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
-
-#ifndef CONFIG_SYS_GENERIC_BOARD
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset((void *)gd, 0, sizeof(gd_t));
-#endif
}
/*
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index eef9c5a..c73509b 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -11,7 +11,7 @@
#include <asm/cache.h>
#include <asm/ppc4xx.h>
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>
@@ -160,4 +160,4 @@
*/
fdt_pcie_setup(blob);
}
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c
index 339d38a..a42327e 100644
--- a/arch/powerpc/cpu/ppc4xx/reginfo.c
+++ b/arch/powerpc/cpu/ppc4xx/reginfo.c
@@ -321,7 +321,7 @@
PRINT_DCR(OPB2PLB40_BCTRL);
PRINT_DCR(P4P3BO0_CFG);
#endif
- n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
+ n = ARRAY_SIZE(ppc4xx_reg);
for (i = 0; i < n; i++) {
value = 0;
type = ppc4xx_reg[i].type;
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index d4ef36d..cd63456 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -33,7 +33,7 @@
sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
#ifdef CONFIG_SYS_SDRAM_CASL
static ulong ns2clks(ulong ns)
@@ -266,7 +266,7 @@
#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
#endif
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
#define NUM_TRIES 64
#define NUM_READS 10
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 137afce..b432b18 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -760,7 +760,6 @@
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
bl board_init_f_alloc_reserve
mr r1, r3
@@ -768,7 +767,6 @@
li r0,0
stwu r0, -4(r1)
stwu r0, -4(r1)
-#endif
li r3, 0
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
@@ -1037,14 +1035,12 @@
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
bl board_init_f_alloc_reserve
mr r1, r3
bl board_init_f_init_reserve
stwu r0, -4(r1)
stwu r0, -4(r1)
-#endif
li r3, 0
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index da7352a..41b6677 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -14,6 +14,8 @@
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
+#ifndef CONFIG_MPC85XX_GPIO
#include <asm/mpc85xx_gpio.h>
+#endif
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 07d2adf..c045a24 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -265,6 +265,7 @@
#define PIWAR_WRITE_SNOOP 0x00005000
#define PIWAR_MEM_2G 0x0000001e
+#ifndef CONFIG_MPC85XX_GPIO
typedef struct ccsr_gpio {
u32 gpdir;
u32 gpodr;
@@ -273,6 +274,7 @@
u32 gpimr;
u32 gpicr;
} ccsr_gpio_t;
+#endif
/* L2 Cache Registers */
typedef struct ccsr_l2cache {
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index a61e998..74b6202 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -14,112 +14,8 @@
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
- || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
- unsigned long bi_immr_base; /* base of IMMR register */
-#endif
-#if defined(CONFIG_MPC5xxx)
- unsigned long bi_mbar_base; /* base of internal registers */
-#endif
-#if defined(CONFIG_MPC83xx)
- unsigned long bi_immrbar;
-#endif
- unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
- unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
- unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
- unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
- unsigned long bi_vco; /* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_MPC512X)
- unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
- unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
- unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
-#endif
-#if defined(CONFIG_405) || \
- defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || \
- defined(CONFIG_440)
- unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
- unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
- unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
- unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
- unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
-#endif
-
-#ifdef CONFIG_HAS_ETH1
- unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH2
- unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH3
- unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH4
- unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH5
- unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */
-#endif
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- unsigned int bi_opbfreq; /* OPB clock in Hz */
- int bi_iic_fast[2]; /* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
- int bi_phynum[4]; /* Determines phy mapping */
- int bi_phymode[4]; /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
- int bi_phynum[2]; /* Determines phy mapping */
- int bi_phymode[2]; /* Determines phy mode */
-#else
- int bi_phynum[1]; /* Determines phy mapping */
- int bi_phymode[1]; /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_PPC
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 05b22bb..3c97476 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -29,11 +29,6 @@
obj-y += reloc.o
obj-$(CONFIG_BAT_RW) += bat_rw.o
-ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
-endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index b96dbc6..66cf02d 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,6 +65,7 @@
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -77,6 +78,7 @@
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
+#endif
blr
/*
@@ -87,6 +89,7 @@
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -100,5 +103,6 @@
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
+#endif
blr
diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S
index 8152ac9..56bb3b8 100644
--- a/arch/powerpc/lib/ppcstring.S
+++ b/arch/powerpc/lib/ppcstring.S
@@ -92,13 +92,6 @@
bdnz 8b
blr
- .globl bcopy
-bcopy:
- mr r6,r3
- mr r3,r4
- mr r4,r6
- b memcpy
-
.globl memmove
memmove:
cmplw 0,r3,r4
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d2a7dc9..2b4dbd3 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -360,8 +360,8 @@
assert(state->ram_buf);
/* No reset yet, so mark it as such. Always allow power reset */
- state->last_reset = RESET_COUNT;
- state->reset_allowed[RESET_POWER] = true;
+ state->last_sysreset = SYSRESET_COUNT;
+ state->sysreset_allowed[SYSRESET_POWER] = true;
/*
* Example of how to use GPIOs:
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8930009..686c215 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -216,6 +216,17 @@
};
};
+ mbox: mbox {
+ compatible = "sandbox,mbox";
+ #mbox-cells = <1>;
+ };
+
+ mbox-test {
+ compatible = "sandbox,mbox-test";
+ mboxes = <&mbox 100>, <&mbox 1>;
+ mbox-names = "other", "test";
+ };
+
mmc {
compatible = "sandbox,mmc";
};
diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index 8317db1..427af2c 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -41,6 +41,26 @@
int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
/**
+ * Set or reset the simulated open drain mode of a GPIO (used only in sandbox
+ * test code)
+ *
+ * @param gp GPIO number
+ * @param value value to set (0 for enabled open drain mode, non-zero for
+ * disabled)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value);
+
+/**
+ * Return the state of the simulated open drain mode of a GPIO (used only in
+ * sandbox test code)
+ *
+ * @param gp GPIO number
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
+
+/**
* Return the simulated direction of a GPIO (used only in sandbox test code)
*
* @param gp GPIO number
diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h
new file mode 100644
index 0000000..2d7b7d0
--- /dev/null
+++ b/arch/sandbox/include/asm/mbox.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_MBOX_H
+#define __SANDBOX_MBOX_H
+
+#include <common.h>
+
+#define SANDBOX_MBOX_PING_XOR 0x12345678
+
+struct udevice;
+
+int sandbox_mbox_test_get(struct udevice *dev);
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg);
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg);
+int sandbox_mbox_test_free(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 11856c2..149f28d 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -7,7 +7,7 @@
#define __SANDBOX_STATE_H
#include <config.h>
-#include <reset.h>
+#include <sysreset.h>
#include <stdbool.h>
#include <linux/stringify.h>
@@ -60,8 +60,8 @@
bool write_state; /* Write sandbox state on exit */
bool ignore_missing_state_on_read; /* No error if state missing */
bool show_lcd; /* Show LCD on start-up */
- enum reset_t last_reset; /* Last reset type */
- bool reset_allowed[RESET_COUNT]; /* Allowed reset types */
+ enum sysreset_t last_sysreset; /* Last system reset type */
+ bool sysreset_allowed[SYSRESET_COUNT]; /* Allowed system reset types */
enum state_terminal_raw term_raw; /* Terminal raw/cooked */
bool skip_delays; /* Ignore any time delays (for test) */
bool show_test_output; /* Don't suppress stdout in tests */
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index a2f856f..9a93cf5 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -83,3 +83,9 @@
{
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index ebf731a..6171edc 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -46,8 +46,9 @@
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
@@ -62,4 +63,4 @@
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
index ea0006a..494f908 100644
--- a/arch/sh/cpu/sh3/cpu.c
+++ b/arch/sh/cpu/sh3/cpu.c
@@ -66,3 +66,9 @@
{
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
index 7a934e2..9ed7198 100644
--- a/arch/sh/cpu/sh3/start.S
+++ b/arch/sh/cpu/sh3/start.S
@@ -45,8 +45,9 @@
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
@@ -61,4 +62,4 @@
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index e8ee0a4..de90ca7 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -75,3 +75,9 @@
#endif
return 0;
}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+ /* TODO(sh maintainer): Implement this */
+ while (1);
+}
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
index 21644b5..77fc221 100644
--- a/arch/sh/cpu/sh4/start.S
+++ b/arch/sh/cpu/sh4/start.S
@@ -42,8 +42,9 @@
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
- mov.l ._sh_generic_init, r0
- jsr @r0
+ #TODO(sh maintainer): Fix this up to call the correct code
+ #mov.l ._sh_generic_init, r0
+ #jsr @r0
nop
loop:
@@ -58,4 +59,4 @@
._bss_end: .long bss_end
._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init: .long sh_generic_init
+#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 30c7a9d..78611c2 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -67,6 +67,7 @@
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index ea37c24..716d8e9 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -12,16 +12,8 @@
#ifndef __ASM_SH_U_BOOT_H_
#define __ASM_SH_U_BOOT_H_
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_boot_params; /* where this board expects params */
-} bd_t;
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_SH
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index f7ae4f8..c5cf89f 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -6,7 +6,6 @@
#
-obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
deleted file mode 100644
index 69cdca3..0000000
--- a/arch/sh/lib/board.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) 2007, 2008, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <watchdog.h>
-#include <net.h>
-#include <mmc.h>
-#include <environment.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int cpu_init(void);
-extern int board_init(void);
-extern int dram_init(void);
-extern int timer_init(void);
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-#ifndef CONFIG_SYS_NO_FLASH
-static int sh_flash_init(void)
-{
- gd->bd->bi_flashsize = flash_init();
-
- if (gd->bd->bi_flashsize >= (1024 * 1024))
- printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
- else
- printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
-
- return 0;
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#if defined(CONFIG_CMD_NAND)
-# include <nand.h>
-# define INIT_FUNC_NAND_INIT nand_init,
-#else
-# define INIT_FUNC_NAND_INIT
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_WATCHDOG)
-extern int watchdog_init(void);
-extern int watchdog_disable(void);
-# undef INIT_FUNC_WATCHDOG_INIT
-# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
-# define WATCHDOG_DISABLE watchdog_disable
-#else
-# define INIT_FUNC_WATCHDOG_INIT
-# define WATCHDOG_DISABLE
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_CMD_IDE)
-# include <ide.h>
-# define INIT_FUNC_IDE_INIT ide_init,
-#else
-# define INIT_FUNC_IDE_INIT
-#endif /* CONFIG_CMD_IDE */
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-static int sh_pci_init(void)
-{
- pci_init();
- return 0;
-}
-# define INIT_FUNC_PCI_INIT sh_pci_init,
-#else
-# define INIT_FUNC_PCI_INIT
-#endif /* CONFIG_PCI */
-
-static int sh_mem_env_init(void)
-{
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
- CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
- env_relocate();
- jumptable_init();
- return 0;
-}
-
-#if defined(CONFIG_CMD_MMC)
-static int sh_mmc_init(void)
-{
- puts("MMC: ");
- mmc_initialize(gd->bd);
- return 0;
-}
-#endif
-
-typedef int (init_fnc_t) (void);
-
-init_fnc_t *init_sequence[] =
-{
- cpu_init, /* basic cpu dependent setup */
- board_init, /* basic board dependent setup */
- interrupt_init, /* set up exceptions */
- env_init, /* event init */
- serial_init, /* SCIF init */
- INIT_FUNC_WATCHDOG_INIT /* watchdog init */
- console_init_f,
- display_options,
- checkcpu,
- checkboard, /* Check support board */
- dram_init, /* SDRAM init */
- timer_init, /* SuperH Timer (TCNT0 only) init */
- sh_mem_env_init,
-#ifndef CONFIG_SYS_NO_FLASH
- sh_flash_init, /* Flash memory init*/
-#endif
- INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
- INIT_FUNC_PCI_INIT /* PCI init */
- stdio_init,
- console_init_r,
- interrupt_init,
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init,
-#endif
-#if defined(CONFIG_CMD_MMC)
- sh_mmc_init,
-#endif
- NULL /* Terminate this list */
-};
-
-void sh_generic_init(void)
-{
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
-
- memset(gd, 0, GENERATED_GBL_DATA_SIZE);
-
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-
- gd->bd = (bd_t *)(gd + 1); /* At end of global data */
- gd->baudrate = CONFIG_BAUDRATE;
-
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
- bd = gd->bd;
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- WATCHDOG_RESET();
- if ((*init_fnc_ptr) () != 0)
- hang();
- }
-
-#ifdef CONFIG_WATCHDOG
- /* disable watchdog if environment is set */
- {
- char *s = getenv("watchdog");
- if (s != NULL)
- if (strncmp(s, "off", 3) == 0)
- WATCHDOG_DISABLE();
- }
-#endif /* CONFIG_WATCHDOG*/
-
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize();
-#endif /* CONFIG_CMD_NET */
-
- while (1) {
- WATCHDOG_RESET();
- main_loop();
- }
-}
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 1d54f7d..5ee4868 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -155,7 +155,7 @@
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- 2, IO_APIC_ADDR, 0);
+ io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
current += acpi_create_madt_irq_overrides(current);
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 6d670d7..93ce412 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -6,3 +6,4 @@
obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
new file mode 100644
index 0000000..8f69829
--- /dev/null
+++ b/arch/x86/cpu/quark/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = &(fadt->header);
+ u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = 4;
+
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+ fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
+ fadt->sci_int = 9;
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0;
+ fadt->acpi_disable = 0;
+ fadt->s4bios_req = 0;
+ fadt->pstate_cnt = 0;
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = 0x0;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
+ fadt->gpe1_blk = 0;
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0x00;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = IO_PORT_RESET;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = SYS_RST | RST_CPU;
+
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+ struct acpi_madt_irqoverride *irqovr;
+ u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+ int length = 0;
+
+ irqovr = (void *)current;
+ length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+ irqovr = (void *)(current + length);
+ length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+ return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+ current += acpi_create_madt_lapics(current);
+
+ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+ io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
similarity index 98%
rename from arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
rename to arch/x86/include/asm/acpi/irq_helper.h
index 2c3585a..f0b3a6b 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -108,4 +108,4 @@
}
/* SoC specific PIRQ route configuration */
-#include "irqroute.h"
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
similarity index 92%
rename from arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
rename to arch/x86/include/asm/acpi/irqlinks.asl
index 0affa23..84c1e53 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -7,26 +7,19 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-Scope (\)
-{
- /* Intel Legacy Block */
- OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
- Field(ILBS, AnyAcc, NoLock, Preserve) {
- Offset (0x8),
- PRTA, 8,
- PRTB, 8,
- PRTC, 8,
- PRTD, 8,
- PRTE, 8,
- PRTF, 8,
- PRTG, 8,
- PRTH, 8,
- Offset (0x88),
- , 3,
- UI3E, 1,
- UI4E, 1
- }
-}
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
Device (LNKA)
{
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
similarity index 100%
rename from arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
rename to arch/x86/include/asm/acpi/irqroute.asl
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 385671c..22f0d68 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -10,6 +10,27 @@
/* Intel LPC Bus Device - 0:1f.0 */
+Scope (\)
+{
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field(ILBS, AnyAcc, NoLock, Preserve) {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ Offset (0x88),
+ , 3,
+ UI3E, 1,
+ UI4E, 1
+ }
+}
+
Device (LPCB)
{
Name(_ADR, 0x001f0000)
@@ -23,7 +44,7 @@
Offset(0x84)
}
- #include "irqlinks.asl"
+ #include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
index 34d3951..e89ff26 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -207,5 +207,5 @@
#include "xhci.asl"
/* IRQ routing for each PCI device */
- #include "irqroute.asl"
+ #include <asm/acpi/irqroute.asl>
}
diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644
index 0000000..5ba31da
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+ PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+ PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+ PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644
index 0000000..c3b0b1d
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ OperationRegion(PRTX, PCI_Config, 0x60, 8)
+ Field(PRTX, AnyAcc, NoLock, Preserve) {
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ }
+
+ #include <asm/acpi/irqlinks.asl>
+
+ /* Firmware Hub */
+ Device (FWH)
+ {
+ Name(_HID, EISAID("INT0800"))
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ /* 8259 Interrupt Controller */
+ Device (PIC)
+ {
+ Name(_HID, EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ /* 8254 timer */
+ Device (TIMR)
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() { 0 }
+ })
+ }
+
+ /* HPET */
+ Device (HPET)
+ {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_CID, 0x010CD041)
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+ })
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+ }
+
+ /* Real Time Clock */
+ Device (RTC)
+ {
+ Name(_HID, EISAID("PNP0B00"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x70, 0x70, 1, 8)
+ IRQNoFlags() { 8 }
+ })
+ }
+
+ /* LPC device: Resource consumption */
+ Device (LDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+ })
+
+ Method(_CRS, 0, NotSerialized)
+ {
+ Return (RBUF)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644
index 0000000..bd72842
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+ Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+ #include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
new file mode 100644
index 0000000..63c82fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644
index 0000000..a89cfaf
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Device (PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) /* PCIe */
+ Name(_CID, EISAID("PNP0A03")) /* PCI */
+
+ Name(_ADR, 0)
+ Name(_BBN, 0)
+
+ Name(MCRS, ResourceTemplate()
+ {
+ /* Bus Numbers */
+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+ /* IO Region 0 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+ /* PCI Config Space */
+ IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000, , , ASEG)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000, , , OPR0)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000, , , OPR1)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000, , , OPR2)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000, , , OPR3)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000, , , OPR4)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000, , , OPR5)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000, , , OPR6)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000, , , OPR7)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000, , , ESG0)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000, , , ESG1)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000, , , ESG2)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000, , , ESG3)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000, , , FSEG)
+
+ /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , PMEM)
+ })
+
+ Method(_CRS, 0, Serialized)
+ {
+ /* Update PCI resource area */
+ CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+ CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+ CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+ /*
+ * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+ *
+ * TODO: for generic usage, read TOLM value from register, or
+ * from global NVS (not implemented by U-Boot yet).
+ */
+ Store(0x80000000, PMIN)
+ Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ Return (MCRS)
+ }
+
+ /* Device Resource Consumption */
+ Device (PDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 1)
+
+ Name(PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+ IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+ IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+ IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+ })
+
+ /* Current Resource Settings */
+ Method(_CRS, 0, Serialized)
+ {
+ Return (PDRS)
+ }
+ }
+
+ Method(_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ /* Unrecognized UUID */
+ CreateDWordField(Arg3, 0, CDW1)
+ Or(CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ /* LPC Bridge 0:1f.0 */
+ #include "lpc.asl"
+
+ /* IRQ routing for each PCI device */
+ #include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 7882f33..4760aa2 100644
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -7,12 +7,17 @@
#ifndef _QUARK_DEVICE_H_
#define _QUARK_DEVICE_H_
-#include <pci.h>
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
-#define QUARK_HOST_BRIDGE_DEV 0
+#define QUARK_HOST_BRIDGE_DEV 0x00
#define QUARK_HOST_BRIDGE_FUNC 0
-#define QUARK_DEV_20 20
+#define QUARK_DEV_20 0x14
#define QUARK_MMC_SDIO_FUNC 0
#define QUARK_UART0_FUNC 1
#define QUARK_USB_DEVICE_FUNC 2
@@ -22,18 +27,21 @@
#define QUARK_EMAC0_FUNC 6
#define QUARK_EMAC1_FUNC 7
-#define QUARK_DEV_21 21
+#define QUARK_DEV_21 0x15
#define QUARK_SPI0_FUNC 0
#define QUARK_SPI1_FUNC 1
#define QUARK_I2C_GPIO_FUNC 2
-#define QUARK_DEV_23 23
+#define QUARK_DEV_23 0x17
#define QUARK_PCIE0_FUNC 0
#define QUARK_PCIE1_FUNC 1
-#define QUARK_LGC_BRIDGE_DEV 31
+#define QUARK_LGC_BRIDGE_DEV 0x1f
#define QUARK_LGC_BRIDGE_FUNC 0
+#ifndef __ASSEMBLY__
+#include <pci.h>
+
#define QUARK_HOST_BRIDGE \
PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
#define QUARK_MMC_SDIO \
@@ -64,5 +72,6 @@
PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
#define QUARK_LEGACY_BRIDGE \
PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
+#endif /* __ASSEMBLY__ */
#endif /* _QUARK_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000..fd1ef98
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE 0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE 0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE 0x10
+
+#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE 0x10
+
+#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE 0x10
+
+#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE 0x80
+
+#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE 0x40
+
+#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
+#define WDT_BASE_SIZE 0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000..21e6830
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+#endif /* _QUARK_IRQ_H_ */
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index ce4acc1..e947e54 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -259,7 +259,7 @@
}
#ifdef CONFIG_NAND
dtbsize = 0x20000;
- rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize,
+ rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
NULL, 0x20000, (u_char *)dtbaddr);
#else
char *dtbname = getenv("dtb");
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
deleted file mode 100644
index 6cae9ea..0000000
--- a/board/Marvell/common/bootseq.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
- b boot_cold
-
-start_warm:
- b boot_warm
-
-
-boot_cold:
-boot_warm:
- clear bats
- init l2 (if enabled)
- init altivec (if enabled)
- invalidate l2 (if enabled)
- setup bats (from defines in config_EVB)
- enable_addr_trans: (if MMU enabled)
- enable MSR_IR and MSR_DR
- jump to in_flash
-
-in_flash:
- enable l1 dcache
- gal_low_init: (board/evb64260/sdram_init.S)
- config SDRAM (CFG, TIMING, DECODE)
- init scratch regs (810 + 814)
-
- detect DIMM0 (bank 0 only)
- config SDRAM_PARA0 to 256/512Mbit
- bl sdram_op_mode
- detect bank0 width
- write scratch reg 810
- config SDRAM_PARA0 with results
- config SDRAM_PARA1 with results
-
- detect DIMM1 (bank 2 only)
- config SDRAM_PARA2 to 256/512Mbit
- detect bank2 width
- write scratch reg 814
- config SDRAM_PARA2 with results
- config SDRAM_PARA3 with results
-
- setup device bus timings/width
- setup boot device timings/width
-
- setup CPU_CONF (0x0)
- setup cpu master control register 0x160
- setup PCI0 TIMEOUT
- setup PCI1 TIMEOUT
- setup PCI0 BAR
- setup PCI1 BAR
-
- setup MPP control 0-3
- setup GPP level control
- setup Serial ports multiplex
-
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f
- debug leds
- board_init_f: (common/board.c)
- board_early_init_f:
- remap gt regs?
- map PCI mem/io
- map device space
- clear out interrupts
- init_timebase
- env_init
- serial_init
- console_init_f
- display_options
- initdram: (board/evb64260/evb64260.c)
- detect memory
- for each bank:
- dram_size()
- setup PCI slave memory mappings
- setup SCS
- setup monitor
- alloc board info struct
- init bd struct
- relocate_code: (cpu/mpc7xxx/start.S)
- copy,got,clearbss
- board_init_r(bd, dest_addr) (common/board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/evb64260/flash.c)
- setup bd flash info
- cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
- nothing
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/evb64260/evb64260.c)
- mpsc_init2
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
deleted file mode 100644
index a879ea9..0000000
--- a/board/Marvell/common/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
deleted file mode 100644
index 5531f95..0000000
--- a/board/Marvell/common/intel_flash.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
-#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
-#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
-#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST 0xFF /* reset flash */
-#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
-#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
-#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
-#define CHIP_CMD_PROG 0x40 /* program word command */
-#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
-#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
-#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
-#define CHIP_STAT_VPPS 0x08 /* VPP Status */
-#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
-#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
- CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
-#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS 128
-#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
-#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS CHIP_NBLOCKS
-#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS 1 /* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
- (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
- (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
- (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
- (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
- BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
- BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o) ((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
deleted file mode 100644
index 610b411..0000000
--- a/board/Marvell/common/memory.c
+++ /dev/null
@@ -1,1374 +0,0 @@
-/*
- * Copyright - Galileo technology.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-
-#include <common.h>
-#include "../include/core.h"
-#include "../include/memory.h"
-
-/*******************************************************************************
-* memoryGetBankBaseAddress - Returns the base address of a memory bank.
-* DESCRIPTION:
-* This function returns the base address of one of the SDRAM's memory
-* banks. There are 4 memory banks and each one represents one DIMM side.
-* INPUT:
-* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Memory bank base address.
-*******************************************************************************/
-static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
-{
- switch (bank) {
- case BANK0:
- return SCS_0_LOW_DECODE_ADDRESS;
- case BANK1:
- return SCS_1_LOW_DECODE_ADDRESS;
- case BANK2:
- return SCS_2_LOW_DECODE_ADDRESS;
- case BANK3:
- return SCS_3_LOW_DECODE_ADDRESS;
-
- }
- return SCS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
-{
- unsigned int base;
- unsigned int regOffset = memoryGetBankRegOffset (bank);
-
- GT_REG_READ (regOffset, &base);
- base = base << 16; /* MV6436x */
- return base;
-}
-
-/*******************************************************************************
-* memoryGetDeviceBaseAddress - Returns the base address of a device.
-* DESCRIPTION:
-* This function returns the base address of a device on the system. There
-* are 5 possible devices (0 - 4 and one boot device) as defined in
-* gtMemory.h. Each of the device parameters is maped to one of the CS
-* (Devices chip selects) base address register.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Device base address.
-*
-*******************************************************************************/
-static unsigned int memoryGetDeviceRegOffset (DEVICE device)
-{
- switch (device) {
- case DEVICE0:
- return CS_0_LOW_DECODE_ADDRESS;
- case DEVICE1:
- return CS_1_LOW_DECODE_ADDRESS;
- case DEVICE2:
- return CS_2_LOW_DECODE_ADDRESS;
- case DEVICE3:
- return CS_3_LOW_DECODE_ADDRESS;
- case BOOT_DEVICE:
- return BOOTCS_LOW_DECODE_ADDRESS;
- }
- return CS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress (DEVICE device)
-{
- unsigned int regBase;
- unsigned int regOffset = memoryGetDeviceRegOffset (device);
-
- GT_REG_READ (regOffset, ®Base);
-
- regBase = regBase << 16; /* MV6436x */
- return regBase;
-}
-
-/*******************************************************************************
-* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
-* DESCRIPTION:
-* This function returns the base address of a PCI window. There are 5
-* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
-* interface as defined in gtMemory.h, used by the CPU's address decoding
-* mechanism.
-* New in MV6436x
-* INPUT:
-* pciWindow - Selects one of the PCI windows as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit PCI window base address.
-*******************************************************************************/
-unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int baseAddrReg, base;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0xffffffff;
- }
- GT_REG_READ (baseAddrReg, &base);
- return (base << 16);
-}
-
-/*******************************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-* DESCRIPTION:
-* This function returns the size of memory bank as described in
-* 'gtMemoryGetBankBaseAddress' function.
-* INPUT:
-* bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size memory bank size or 0 for a closed or non populated bank.
-*
-*******************************************************************************/
-unsigned int memoryGetBankSize (MEMORY_BANK bank)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (bank) {
- case BANK0:
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */
- window = CS_0_WINDOW;
- break;
- case BANK1:
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */
- window = CS_1_WINDOW;
- break;
- case BANK2:
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */
- window = CS_2_WINDOW;
- break;
- case BANK3:
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */
- window = CS_3_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space.
-* DESCRIPTION:
-* This function returns the memory space size of a given device.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a device memory space.
-*******************************************************************************/
-unsigned int memoryGetDeviceSize (DEVICE device)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (device) {
- case DEVICE0:
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
- window = DEVCS_0_WINDOW;
- break;
- case DEVICE1:
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
- window = DEVCS_1_WINDOW;
- break;
- case DEVICE2:
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
- window = DEVCS_2_WINDOW;
- break;
- case DEVICE3:
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
- window = DEVCS_3_WINDOW;
- break;
- case BOOT_DEVICE:
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
- window = BOOT_CS_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
-* DESCRIPTION:
-* This function returns the size of a PCI window.
-* INPUT:
-* pciWindow - Selects one of the PCI memory windows as defined in
-* Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a PCI memory window.
-*******************************************************************************/
-unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int sizeReg, size;
-
- switch (pciWindow) {
- case PCI_0_IO:
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0x0;
- }
- /* If the memory window is disabled, retrun size = 0 */
- if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
- == MEM_WINDOW_DISABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceWidth - Returns the width of a given device.
-* DESCRIPTION:
-* The MV's device interface supports up to 32 Bit wide devices. A device
-* can have a 1, 2, 4 or 8 Bytes data width. This function returns the
-* width of a device as defined by the user or the operating system.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*******************************************************************************/
-unsigned int memoryGetDeviceWidth (DEVICE device)
-{
- unsigned int width;
- unsigned int regValue;
-
- GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value);
- width = (regValue & (BIT20 | BIT21)) >> 20;
- return (BIT0 << width);
-}
-
-/*******************************************************************************
-* memoryMapBank - Set new base address and size for one of the memory
-* banks.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the memory banks
-* (CS0 - CS3). It is the programmer`s responsibility to make sure that
-* there are no conflicts with other memory spaces. When two memory spaces
-* overlap, the MV's behavior is not defined .If a bank needs to be closed,
-* set the 'bankLength' parameter size to 0x0.
-*
-* INPUT:
-* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
-* bankBase - The memory bank base address.
-* bankLength - The memory bank size. This function will decrement the
-* 'bankLength' parameter by one and then check if the size is
-* valid. A valid size must be programed from LSB to MSB as
-* sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* OUTPUT:
-* None.
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR; */
-
- switch (bank) {
- case BANK0:
- baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */
-/* pciBAR = PCI_CS0_BAR; */
- break;
- case BANK1:
- baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */
- /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
- break;
- case BANK2:
- baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */
-/* pciBAR = PCI_CS2_BAR;*/
- break;
- case BANK3:
- baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */
-/* pciBAR = PCI_CS3_BAR; */
- break;
- default:
- return false;
- }
- /* If the size is 0, the window will be disabled */
- if (bankLength == 0) {
- MemoryDisableWindow (CS_0_WINDOW << bank);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((bankBase % bankLength) != 0) {
- return false;
- }
- if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
- newBase = bankBase >> 16;
- newSize = bankLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
-#ifdef DEBUG
- {
- unsigned int oldBase, oldSize;
-
- GT_REG_READ (baseReg, &oldBase);
- GT_REG_READ (sizeReg + 8, &oldSize);
-
- printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
- bank, oldBase, oldSize, newBase, newSize);
- }
-#endif
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- /* Enable back the window */
- MemoryEnableWindow (CS_0_WINDOW << bank);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-
-/*******************************************************************************
-* memoryMapDeviceSpace - Set new base address and size for one of the device
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the device windows
-* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined .If a device window
-* needs to be closed, set the 'deviceLength' parameter size to 0x0.
-*
-* INPUT:
-* device - One of the device windows (DEV_CS0-DEV_CS3) as
-* defined in gtMemory.h.
-* deviceBase - The device window base address.
-* deviceLength - The device window size. This function will decrement
-* the 'deviceLength' parameter by one and then
-* check if the size is valid. A valid size must be
-* programed from LSB to MSB as sequence of '1's
-* followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
- unsigned int deviceLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR;*/
-
- switch (device) {
- case DEVICE0:
- baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
-/* pciBAR = PCI_DEV_CS0_BAR; */
- break;
- case DEVICE1:
- baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
-/* pciBAR = PCI_DEV_CS1_BAR; */
- break;
- case DEVICE2:
- baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
-/* pciBAR = PCI_DEV_CS2_BAR; */
- break;
- case DEVICE3:
- baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
-/* pciBAR = PCI_DEV_CS3_BAR; */
- break;
- case BOOT_DEVICE:
- baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
-/* pciBAR = PCI_BOOT_CS_BAR; */
- break;
- default:
- return false;
- }
- if (deviceLength == 0) {
- MemoryDisableWindow (DEVCS_0_WINDOW << device);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((deviceBase % deviceLength) != 0) {
- return false;
- }
- if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
- newBase = deviceBase >> 16;
- newSize = deviceLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- MemoryEnableWindow (DEVCS_0_WINDOW << device);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* MemorySetPciWindow - Set new base address and size for one of the PCI
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the PCI windows
-* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined. If a PCI window
-* needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
-*
-* INPUT:
-* pciWindow - One of the PCI windows as defined in gtMemory.h.
-* pciWindowBase - The PCI window base address.
-* pciWindowSize - The PCI window size. This function will decrement the
-* 'pciWindowSize' parameter by one and then check if the
-* size is valid. A valid size must be programed from LSB
-* to MSB as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize)
-{
- unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return false;
- }
- if (pciWindowSize == 0) {
- MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- /* The base address must be aligned to the size */
- if ((pciWindowBase % pciWindowSize) != 0) {
- return false;
- }
- if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
- pciWindowBase >>= 16;
- pciWindowSize >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = pciWindowSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE (sizeReg, pciWindowSize - 1);
- GT_REG_READ (baseAddrReg, ¤tLow);
- pciWindowBase =
- (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
- GT_REG_WRITE (baseAddrReg, pciWindowBase);
- MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internal
-* registers memory space.
-*
-* DESCRIPTION:
-* This function set new base address for the internal registers memory
-* space (the size is fixed and cannot be modified). The function does not
-* handle overlapping with other memory spaces, it is the programer's
-* responsibility to ensure that overlapping does not occur.
-* When two memory spaces overlap, the MV's behavior is not defined.
-*
-* INPUT:
-* internalRegBase - new base address for the internal registers memory
-* space.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true on success, false on failure
-*
-*******************************************************************************/
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-* registers.
-*
-* INPUTS: unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
-{
- unsigned int currentValue;
- unsigned int internalValue = internalRegBase;
-
- internalRegBase = (internalRegBase >> 16);
- GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
- internalRegBase = (currentValue & 0xff000000) | internalRegBase;
- GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
- /* initializing also the global variable 'internalRegBaseAddr' */
-/* gtInternalRegBaseAddr = internalValue; */
- INTERNAL_REG_BASE_ADDR = internalValue;
- return true;
-}
-
-/*******************************************************************************
-* memoryGetInternalRegistersSpace - Returns the internal registers Base
-* address.
-*
-* DESCRIPTION:
-* This function returns the base address of the internal registers
-* memory space .
-*
-* INPUT:
-* None.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* 32 bit base address of the internal registers memory space.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalRegistersSpace (void)
-{
- unsigned int currentValue = 0;
-
- GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
- return ((currentValue & 0x000fffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* funcnion return the SRAM's base address.
-* INPUT:
-* None.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit SRAM's base address.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalSramBaseAddr (void)
-{
- return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* function sets a new base address to the SRAM .
-* INPUT:
-* sramBaseAddress - The SRAM's base address.
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
-{
- GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
-}
-
-/*******************************************************************************
-* memorySetProtectRegion - Set protection mode for one of the 8 regions.
-*
-* DESCRIPTION:
-* The CPU interface supports configurable access protection. This includes
-* up to eight address ranges defined to a different protection type :
-* whether the address range is cacheable or not, whether it is writable or
-* not , and whether it is accessible or not. A Low and High registers
-* define each window while the minimum address range of each window is
-* 1Mbyte. An address driven by the CPU, in addition to the address
-* decoding and remapping process, is compared against the eight Access
-* Protection Low/High registers , if an address matches one of the windows
-* , the MV device checks the transaction type against the protection bits
-* defined in CPU Access Protection register, to determine if the access is
-* allowed. This function set a protection mode to one of the 8 possible
-* regions.
-* NOTE:
-* The CPU address windows are restricted to a size of 2 power n and the
-* start address must be aligned to the window size. For example, if using
-* a 16 MB window, the start address bits [23:0] must be 0.The MV's
-* internal registers space is not protected, even if the access protection
-* windows contain this space.
-*
-* INPUT:
-* region - selects which region to be configured. The values defined in
-* gtMemory.h:
-*
-* - MEM_REGION0
-* - MEM_REGION1
-* - etc.
-*
-* memAccess - Allows or forbids access (read or write ) to the region. The
-* values defined in gtMemory.h:
-*
-* - MEM_ACCESS_ALLOWED
-* - MEM_ACCESS_FORBIDEN
-*
-* memWrite - CPU write protection to the region. The values defined in
-* gtMemory.h:
-*
-* - MEM_WRITE_ALLOWED
-* - MEM_WRITE_FORBIDEN
-*
-* cacheProtection - Defines whether caching the region is allowed or not.
-* The values defined in gtMemory.h:
-*
-* - MEM_CACHE_ALLOWED
-* - MEM_CACHE_FORBIDEN
-*
-* baseAddress - the region's base Address.
-* regionSize - The region's size. This function will decrement the
-* 'regionSize' parameter by one and then check if the size
-* is valid. A valid size must be programed from LSB to MSB
-* as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS memAccess,
- MEMORY_ACCESS_WRITE memWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int dataForReg, temp, rShift;
-
- if (size == 0) {
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- 0x0);
- return true;
- }
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size >= MINIMUM_ACCESS_WIN_SIZE) {
- baseAddress = ((baseAddress >> 16) & 0xfffff);
- dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
- ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
- & BIT22) | BIT31;
- GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
- dataForReg);
- size >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = size - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- size - 1);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* gtMemoryDisableProtectRegion - Disable a protected window.
-*
-* DESCRIPTION:
-* This function disable a protected window set by
-* 'gtMemorySetProtectRegion' function.
-*
-* INPUT:
-* window - one of the 4 windows ( defined in gtMemory.h ).
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
-{
- RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
- BIT31);
-}
-
-/*******************************************************************************
-* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
-*
-* DESCRIPTION:
-* In addition to the address decoding mechanism, the CPU has an address
-* remapping mechanism to be used by every PCI decoding window. Each PCI
-* window can be remaped to a desired address target according to the remap
-* value within the remap register. The address remapping is useful when a
-* CPU address range must be reallocated to a different location on the
-* PCI bus. Also, it enables CPU access to a PCI agent located above the
-* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to
-* a defualt value (see CPU interface section in the MV spec for the
-* default values). The remap mechanism does not always produce the desired
-* address on the PCI bus because of the remap mechanism way of working
-* (to fully understand why, please see the 'Address Remapping' section in
-* the MV's spec). Therefor, this function sets a desired remap value to
-* one of the PCI memory windows and return the effective address that
-* should be used when exiting the PCI memory window. You should ALWAYS use
-* the returned value by this function when remapping a PCI window and
-* exiting it. If for example the base address of PCI0 memory 0 is
-* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
-* the function will return the value of 0x91000000 that MUST
-* be used to exit this memory window in order to achive the deisred
-* remapping.
-*
-* INPUT:
-* memoryWindow - One of the PCI memory windows as defined in Memory.h
-* remapValueLow - The low remap value.
-* remapValueHigh - The high remap value.
-* OUTPUT:
-* None.
-*
-* RETURN:
-* The effective base address to exit the PCI, or 0xffffffff if one of the
-* parameters is erroneous or the effective base address is higher the top
-* decode value.
-*
-*******************************************************************************/
-unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow)
-{
- unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
- unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
- unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
-
- /* Initializing the base and size variables of the PCI
- memory windows */
- switch (memoryWindow) {
- case PCI_0_IO:
- pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_IO_SIZE;
- remapRegLow = PCI_0_IO_ADDR_REMAP;
- remapRegHigh = PCI_0_IO_ADDR_REMAP;
- break;
- case PCI_0_MEM0:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
- remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM1:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
- remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM2:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
- remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM3:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
- remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_IO_SIZE;
- remapRegLow = PCI_1_IO_ADDR_REMAP;
- remapRegHigh = PCI_1_IO_ADDR_REMAP;
- break;
- case PCI_1_MEM0:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
- remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM1:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM2:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM3:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
- remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- /* Retrun an invalid effective base address */
- return 0xffffffff;
- }
- /* Writing the remap value to the remap regisers */
- GT_REG_WRITE (remapRegHigh, remapValueHigh);
- GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
- /* Reading the values from the base address and size registers */
- baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
- windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
- /* Start calculating the effective Base Address */
- effectiveBaseAddress = baseAddrValue << 16;
- /* The effective base address will be combined from the chopped (if any)
- remap value (according to the size value and remap mechanism) and the
- window's base address */
- effectiveBaseAddress |=
- (((windowSizeValue << 16) | 0xffff) & remapValueLow);
- /* If the effectiveBaseAddress exceed the window boundaries return an
- invalid value. */
- if (effectiveBaseAddress >
- ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
- return 0xffffffff;
- return effectiveBaseAddress;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-* SNOOP_TYPE snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* unsigned int baseAddress - Base Address of this region.
-* unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-/* evb6260 code */
-#if 0
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
- return false;
- snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
- snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
- GT_REG_WRITE(snoopXtopAddress,0);
- return true;
- }
- baseAddress = baseAddress & 0xffff0000;
- data = (baseAddress >> 16) | snoopType << 16;
- GT_REG_WRITE(snoopXbaseAddress,data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
- return true;
-}
-#endif
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-* remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*
-* Not needed function To_do !!!!
-*********************************************************************/
-bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
-{
- unsigned int valueForReg;
-
- valueForReg = (remapValue & 0xfff00000) >> 20;
- GT_REG_WRITE (remapReg, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* memoryGetDeviceParam - Extract the device parameters from the device bank
-* parameters register.
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register .
-* This function extracts the parameters described from the Device Bank
-* parameters register and fills the given 'deviceParam' (defined in
-* gtMemory.h) structure with the read data.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-
-bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueOfReg;
- unsigned int calcData;
-
- if (deviceNum > 4)
- return false;
- GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
- calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
- deviceParam->turnOff = calcData; /* Turn Off */
-
- calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
- deviceParam->acc2First = calcData; /* Access To First */
-
- calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
- deviceParam->acc2Next = calcData; /* Access To Next */
-
- calcData =
- ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
- deviceParam->ale2Wr = calcData; /* Ale To Write */
-
- calcData = ((0x1c000 & valueOfReg) >> 14) +
- ((BIT26 & valueOfReg) >> 23);
- deviceParam->wrLow = calcData; /* Write Active */
-
- calcData = ((0xe0000 & valueOfReg) >> 17) +
- ((BIT27 & valueOfReg) >> 24);
- deviceParam->wrHigh = calcData; /* Write High */
-
- calcData = ((0x300000 & valueOfReg) >> 20);
- deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */
- calcData = ((0x30000000 & valueOfReg) >> 28);
- deviceParam->badrSkew = calcData; /* Cycles gap between BAdr
- toggle to read data sample. */
- calcData = ((0x40000000 & valueOfReg) >> 30);
- deviceParam->DPEn = calcData; /* Data Parity enable */
- return true;
-}
-
-/*******************************************************************************
-* memorySetDeviceParam - Set new parameters for a device.
-*
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register. This function set new
-* parameters to a device Bank from the delivered structure 'deviceParam'
-* (defined in gtMemory.h). The structure must be initialized with data
-* prior to the use of these function.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueForReg;
-
- if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
- (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
- (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
- (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
- return false;
- }
- valueForReg = (((deviceParam->turnOff) & 0x7) |
- (((deviceParam->turnOff) & 0x8) << 19) |
- (((deviceParam->acc2First) & 0xf) << 3) |
- (((deviceParam->acc2First) & 0x10) << 19) |
- (((deviceParam->acc2Next) & 0xf) << 7) |
- (((deviceParam->acc2Next) & 0x10) << 20) |
- (((deviceParam->ale2Wr) & 0x7) << 11) |
- (((deviceParam->ale2Wr) & 0xf) << 22) |
- (((deviceParam->wrLow) & 0x7) << 14) |
- (((deviceParam->wrLow) & 0xf) << 23) |
- (((deviceParam->wrHigh) & 0x7) << 17) |
- (((deviceParam->wrHigh) & 0xf) << 24) |
- (((deviceParam->badrSkew) & 0x3) << 28) |
- (((deviceParam->DPEn) & 0x1) << 30));
-
- /* insert the device width: */
- switch (deviceParam->deviceWidth) {
- case 1:
- valueForReg = valueForReg | _8BIT;
- break;
- case 2:
- valueForReg = valueForReg | _16BIT;
- break;
- case 4:
- valueForReg = valueForReg | _32BIT;
- break;
- default:
- valueForReg = valueForReg | _8BIT;
- break;
- }
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* MemoryDisableWindow - Disable a memory space by the disable bit.
-* DESCRIPTION:
-* This function disables one of the 21 availiable windows dedicated for
-* the CPU decoding mechanism. Its possible to combine several windows with
-* the OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryDisableWindow (MEMORY_WINDOW window)
-{
- SET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryEnableWindow - Enable a memory space that was disabled by
-* 'MemoryDisableWindow'.
-* DESCRIPTION:
-* This function enables one of the 21 availiable windows dedicated for the
-* CPU decoding mechanism. Its possible to combine several windows with the
-* OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryEnableWindow (MEMORY_WINDOW window)
-{
- RESET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryGetMemWindowStatus - This function check whether the memory window is
-* disabled or not.
-* DESCRIPTION:
-* This function checks if the given memory window is closed .
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* true for a closed window, false otherwise .
-*******************************************************************************/
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
-{
- if (GTREGREAD (BASE_ADDR_ENABLE) & window)
- return MEM_WINDOW_DISABLED;
- return MEM_WINDOW_ENABLED;
-}
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
deleted file mode 100644
index 7839b68..0000000
--- a/board/Marvell/common/ns16550.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
- (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
- volatile struct NS16550 *com_port;
-
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
- return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
- while ((com_port->lsr & LSR_THRE) == 0);
- com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
- while ((com_port->lsr & LSR_DR) == 0);
- return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
- return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
deleted file mode 100644
index 9306381..0000000
--- a/board/Marvell/common/ns16550.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
- wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
- unsigned char rbr; /* 0 = 0-3*/
- int pad1:24;
-
- unsigned char ier; /* 1 = 4-7*/
- int pad2:24;
-
- unsigned char fcr; /* 2 = 8-b*/
- int pad3:24;
-
- unsigned char lcr; /* 3 = c-f*/
- int pad4:24;
-
- unsigned char mcr; /* 4 = 10-13*/
- int pad5:24;
-
- unsigned char lsr; /* 5 = 14-17*/
- int pad6:24;
-
- unsigned char msr; /* 6 =18-1b*/
- int pad7:24;
-
- unsigned char scr; /* 7 =1c-1f*/
- int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*receiver soft reset*/
-#define FCR_TXSR 0x04 /*transmitter soft reset*/
-
-
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DMA_EN 0x04
-#define MCR_TX_DFR 0x08
-
-
-#define LCR_WLS_MSK 0x03 /* character length slect mask*/
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble*/
-#define LCR_EPS 0x10 /* Even Parity Select*/
-#define LCR_STKP 0x20 /* Stick Parity*/
-#define LCR_SBRK 0x40 /* Set Break*/
-#define LCR_BKSE 0x80 /* Bank select enable*/
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1 0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
deleted file mode 100644
index 432aa06..0000000
--- a/board/Marvell/common/serial.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../include/memory.h"
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_MPSC
-static int marvell_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
- int clock_divisor = 230400 / gd->baudrate;
-#endif
-
- mpsc_init (gd->baudrate);
-
- /* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar ('\r');
-
- mpsc_putchar (c);
-}
-
-static int marvell_serial_getc(void)
-{
- return mpsc_getchar ();
-}
-
-static int marvell_serial_tstc(void)
-{
- return mpsc_test_char ();
-}
-
-static void marvell_serial_setbrg(void)
-{
- galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else /* ! CONFIG_MPSC */
-
-static int marvell_serial_init(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void) NS16550_init (1, clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int marvell_serial_getc(void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int marvell_serial_tstc(void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void marvell_serial_setbrg(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device marvell_serial_drv = {
- .name = "marvell_serial",
- .start = marvell_serial_init,
- .stop = NULL,
- .setbrg = marvell_serial_setbrg,
- .putc = marvell_serial_putc,
- .puts = default_serial_puts,
- .getc = marvell_serial_getc,
- .tstc = marvell_serial_tstc,
-};
-
-void marvell_serial_initialize(void)
-{
- serial_register(&marvell_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &marvell_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
deleted file mode 100644
index 0947b6e..0000000
--- a/board/Marvell/include/memory.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY 0xffffffff
-#define PARITY_SUPPORT 0x40000000
-#define MINIMUM_MEM_BANK_SIZE 0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
-#define MINIMUM_PCI_WINDOW_SIZE 0x10000
-#define MINIMUM_ACCESS_WIN_SIZE 0x10000
-
-#define _8BIT 0x00000000
-#define _16BIT 0x00100000
-#define _32BIT 0x00200000
-#define _64BIT 0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{ /* boundary values */
- unsigned int turnOff; /* 0x0 - 0xf */
- unsigned int acc2First; /* 0x0 - 0x1f */
- unsigned int acc2Next; /* 0x0 - 0x1f */
- unsigned int ale2Wr; /* 0x0 - 0xf */
- unsigned int wrLow; /* 0x0 - 0xf */
- unsigned int wrHigh; /* 0x0 - 0xf */
- unsigned int badrSkew; /* 0x0 - 0x2 */
- unsigned int DPEn; /* 0x0 - 0x1 */
- unsigned int deviceWidth; /* in Bytes */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
- MEM_REGION3,MEM_REGION4,MEM_REGION5, \
- MEM_REGION6,MEM_REGION7} \
- MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
- MEM_WINDOW3
- } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
- is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
- MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
- MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
- MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
- MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
- MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
- MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
- devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
- address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
- CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
- DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
- DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
- BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
- PCI_0_MEM0_WINDOW = BIT10,
- PCI_0_MEM1_WINDOW = BIT11,
- PCI_0_MEM2_WINDOW = BIT12,
- PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
- PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
- PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
- INTEGRATED_SRAM_WINDOW = BIT19,
- INTERNAL_SPACE_WINDOW = BIT20,
- ALL_WINDOWS = 0X1FFFFF
- } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
- } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
- ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
- } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS gtMemoryAccess,
- MEMORY_ACCESS_WRITE gtMemoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
- MEMORY_ACCESS memoryAccess,
- MEMORY_ACCESS_WRITE memoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
- address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif /* __INCmemoryh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
deleted file mode 100644
index 572e0d3..0000000
--- a/board/Marvell/include/pci.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
- the PCI to become: MASTER, response to MEMORY transactions , response to
- IO transactions or TWO both MEMORY_IO transactions. Those configuration
- are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define MASTER_ENABLE BIT2
-#define MEMORY_ENABLE BIT1
-#define I_O_ENABLE BIT0
-#define SELF 32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define BAR0 0x10
-#define BAR1 0x14
-#define BAR2 0x18
-#define BAR3 0x1c
-#define BAR4 0x20
-#define BAR5 0x24
-#define BAR_SEL_MEM_IO BIT0
-#define BAR_MEM_TYPE_32_BIT NO_BIT
-#define BAR_MEM_TYPE_BELOW_1M BIT1
-#define BAR_MEM_TYPE_64_BIT BIT2
-#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
-#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
-#define BAR_PREFETCHABLE BIT3
-#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define PREFETCH_ENABLE BIT12
-#define PREFETCH_DISABLE NO_BIT
-#define DELAYED_READ_ENABLE BIT13
-/* #define CACHING_ENABLE BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define AGGRESSIVE_PREFETCH BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
-#define MAX_BURST_4 NO_BIT
-#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
-#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
-#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
-#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
-#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
-#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define PCI_ACCESS_PROTECT BIT28
-#define PCI_WRITE_PROTECT BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
- REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
- PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
- PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
- PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
- PCI_REGION2,PCI_REGION3,
- PCI_IO}
- PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
- PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
- PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
- PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
- PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
- PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
- PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
- unsigned int detectBase;
- unsigned int base;
- unsigned int size;
- unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
- PCI_HOST host;
- char type[40];
- unsigned int deviceNum;
- unsigned int venID;
- unsigned int deviceID;
- PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
- unsigned int SCS0Base;
- unsigned int SCS0Size;
- unsigned int SCS1Base;
- unsigned int SCS1Size;
- unsigned int SCS2Base;
- unsigned int SCS2Size;
- unsigned int SCS3Base;
- unsigned int SCS3Size;
- unsigned int internalMemBase;
- unsigned int internalIOBase;
- unsigned int CS0Base;
- unsigned int CS0Size;
- unsigned int CS1Base;
- unsigned int CS1Size;
- unsigned int CS2Base;
- unsigned int CS2Size;
- unsigned int CS3Base;
- unsigned int CS3Size;
- unsigned int CSBootBase;
- unsigned int CSBootSize;
- unsigned int P2PMem0Base;
- unsigned int P2PMem0Size;
- unsigned int P2PMem1Base;
- unsigned int P2PMem1Size;
- unsigned int P2PIOBase;
- unsigned int P2PIOSize;
- unsigned int CPUBase;
- unsigned int CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
- agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
- unsigned int numberOfElment);
-
-/* Master`s memory space */
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
- unsigned int remapBase,
- unsigned int deviceBase,
- unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/* Slave`s memory space */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
- unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
- unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
- unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
- unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
- unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
- unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
- unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
- unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
- unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
- unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
- unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
- unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
- unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
- unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
- unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
- unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
- unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength);
-
-void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
- unsigned int SecondBusLow,unsigned int SecondBusHigh,
- unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index ee1681b..55d0bc8 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -391,14 +391,14 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_SPL_OS_BOOT
/*
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index c5d161b..20d8b80 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -170,14 +170,14 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
int board_eth_init(bd_t *bis)
{
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index c5cc4ff..dc2e3ba 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -489,7 +489,7 @@
}
#endif /* !defined(CONFIG_ARCHES) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
extern int __ft_board_setup(void *blob, bd_t *bd);
int ft_board_setup(void *blob, bd_t *bd)
@@ -518,4 +518,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 7b7cd2c..6398bcb 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -212,7 +212,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index af68e10..04e5812 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -191,7 +191,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#ifndef CONFIG_SYS_NO_FLASH
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 4c64312..6871916 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -272,7 +272,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index d3555bb..fc4f50d 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -124,7 +124,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 9ef2864..994f246 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -151,7 +151,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index c14df30..b0d440d 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -196,7 +196,7 @@
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index e8ee612..fa90270 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -207,7 +207,7 @@
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index f4eef96..23ec274 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -191,7 +191,7 @@
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index aee6217..72bad23 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -187,7 +187,7 @@
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
index 1704627..106be9b 100644
--- a/board/avionic-design/common/tamonten-ng.c
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -42,12 +42,12 @@
void gpio_early_init(void)
{
/* Turn on the alive signal */
- gpio_request(GPIO_PV2, "ALIVE");
- gpio_direction_output(GPIO_PV2, 1);
+ gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+ gpio_direction_output(TEGRA_GPIO(V, 2), 1);
/* Remove the reset on the external periph */
- gpio_request(GPIO_PI4, "nRST_PERIPH");
- gpio_direction_output(GPIO_PI4, 1);
+ gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+ gpio_direction_output(TEGRA_GPIO(I, 4), 1);
}
void pmu_write(uchar reg, uchar data)
@@ -73,8 +73,8 @@
pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
/* Switch the power on */
- gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
- gpio_direction_output(GPIO_PJ2, 1);
+ gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+ gpio_direction_output(TEGRA_GPIO(J, 2), 1);
}
/*
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 9c86779..4fb36a2 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -23,8 +23,8 @@
#ifdef CONFIG_BOARD_EARLY_INIT_F
void gpio_early_init(void)
{
- gpio_request(GPIO_PI4, NULL);
- gpio_direction_output(GPIO_PI4, 1);
+ gpio_request(TEGRA_GPIO(I, 4), NULL);
+ gpio_direction_output(TEGRA_GPIO(I, 4), 1);
}
#endif
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 5276907..fce998d0 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -237,7 +237,7 @@
}
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#ifdef CONFIG_OF_BOARD_SETUP
/*
* Update 'model' and 'memory' properties in the blob according to the module
* that we are running on.
@@ -255,7 +255,7 @@
printf("ft_blob_update(): cannot set /model property err:%s\n",
fdt_strerror(ret));
}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
@@ -358,7 +358,7 @@
#endif /* CONFIG_LAST_STAGE_INIT */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
@@ -366,4 +366,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index a15a9ed..1b6c40f 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -106,11 +106,11 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index b813adb..448176d 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -9,6 +9,21 @@
config SYS_CONFIG_NAME
default "dbau1x00"
+config SYS_TEXT_BASE
+ default 0xbfc00000
+
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
menu "dbau1x00 board options"
choice
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index f46936c..51ac10c 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -16,7 +16,7 @@
*/
static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index ca9a944..c510ab1 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -471,7 +471,7 @@
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -493,4 +493,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index cda1d7b..656f0fa 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -198,11 +198,11 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 24e4977..31ac728 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -300,7 +300,7 @@
return 1;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -322,7 +322,7 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 7e35c19..0d43505 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -882,7 +882,7 @@
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -903,4 +903,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 0acd2a9..673d2ea 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -5,11 +5,11 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += b4860qds.o
-obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_B4860QDS) += eth_b4860qds.o
+obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index eb10a6f..31b186e 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -179,15 +179,13 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 3f7cc03..fabc783 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -91,6 +91,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index b26d3a1..8027750 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -13,15 +13,11 @@
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
-obj-y += bsc9131rdb.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-#obj-y += bsc9131rdb_mux.o
-
+obj-y += bsc9131rdb.o
+obj-y += ddr.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 2e4170f..5419335 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -13,14 +13,11 @@
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
obj-y += bsc9132qds.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-
-endif
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 818484a..93b3cba 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -11,15 +11,15 @@
endif
ifdef MINIMAL
-obj-y += spl_minimal.o tlb.o law.o
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
-
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 3d31d41..d8d73c7 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -57,6 +57,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index 3d5404e..0abaffb 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -12,9 +12,12 @@
{
void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
+ u32 icid;
- for (i = 0; i < num; i++)
- out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
+ for (i = 0; i < num; i++) {
+ icid = (id[i].stream_id & 0xff) << 24;
+ out_be32((u32 *)(scfg + id[i].offset), icid);
+ }
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..0db0ed6 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
#include <i2c.h>
#include "qixis.h"
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
@@ -27,6 +34,7 @@
}
#endif
+#ifdef QIXIS_BASE
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@
out_8(p + reg, value);
}
+#endif
u16 qixis_read_minor(void)
{
@@ -142,9 +151,9 @@
{
u8 reg;
- reg = QIXIS_READ(brdcfg[0]);
+ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
- QIXIS_WRITE(brdcfg[0], reg);
+ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
}
static void __maybe_unused set_rcw_src(int rcw_src)
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+ default "ls1012afrdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000..842f86f
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012afrdm/
+F: include/configs/ls1012afrdm.h
+F: configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000..dbfa2ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000..181c461
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+ - 2 SGMII 1G PHYs
+ - DDR Controller
+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ operating at 1.35 V
+ - QSPI
+ - Onboard 512 Mbit QSPI flash memory running at speed up
+ to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+ Micro-AB connector.
+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+ as a Micro-AB device.
+ - I2C controller
+ - One I2C bus with connectivity to Arduino headers
+ - UART
+ - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+ - ARM Cortex® 10-pin JTAG connector for LS1012A
+ - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+ - One SAI port, SAI 2 with full duplex support
+ - Clocks
+ - 25 MHz crystal for LS1012A
+ - 8 MHz Crystal for K20
+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+ - 5 V input supply from USB
+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+ other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000..a94a458
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ puts("Board: LS1012AFRDM ");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 0000000..1257ec8
--- /dev/null
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+ default "ls1012aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 0000000..27c4aff
--- /dev/null
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012aqds/
+F: include/configs/ls1012aqds.h
+F: configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 0000000..0b813f9
--- /dev/null
+++ b/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644
index 0000000..dee4b30
--- /dev/null
+++ b/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+ emulator
+ - USB 3.0
+ - One USB 3.0 controller with integrated PHY
+ - One high-speed USB 3.0 port
+ - USB 2.0
+ - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+ - One SAI port with audio codec SGTL5000:
+ • Provides MIC bias
+ • Provides headphone and line output
+ - One SAI port terminated at 2x6 header
+ - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 0000000..71eea82
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+ if (sw & QIXIS_LBMAP_ALTBANK)
+ printf("flash: 2\n");
+ else
+ printf("flash: 1\n");
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ u8 mux_sdhc_cd = 0x80;
+
+ i2c_set_bus_num(0);
+
+ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+ CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to enable barrier
+ * transaction */
+ out_le32(&cci->ctrl_ord,
+ CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 0000000..584f604
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 0000000..3f67c28
--- /dev/null
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+ default "ls1012ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 0000000..79a2a7d
--- /dev/null
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012ardb/
+F: include/configs/ls1012ardb.h
+F: configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 0000000..05fa9d9
--- /dev/null
+++ b/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644
index 0000000..453b432
--- /dev/null
+++ b/board/freescale/ls1012ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory (2 virtual banks)
+ - the QSPI emulator.s
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: Three dual 1:4 mux/demux devices,
+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+ SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 0000000..f69768d
--- /dev/null
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ u8 in1;
+
+ puts("Board: LS1012ARDB ");
+
+ /* Initialize i2c early for Serial flash bank information */
+ i2c_set_bus_num(0);
+
+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ puts("Version");
+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+ puts(": RevA");
+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+ puts(": RevB");
+ else
+ puts(": unknown");
+
+ printf(", boot from QSPI");
+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+ puts(": emu\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+ puts(": bank1\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+ puts(": bank2\n");
+ else
+ puts("unknown\n");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index f819c99..b39b561 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -31,21 +31,21 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
- {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
- {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,},
+ {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
- {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a3..913537d 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043AQDS board Overview
-----------------------
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index d3f4082..ad709ba 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -34,21 +34,21 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
- {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
- {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
+ {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
- {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index ca393e8..7e47ef0 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -238,8 +238,8 @@
out_be32(&scfg->rcwpmuxcr0, 0x3333);
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
usb_pwrfault =
- (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 0556e73..709ddbb 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -8,41 +8,8 @@
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043ARDB board Overview
-----------------------
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index 8ca166b..a77ddf3 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -34,9 +34,9 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
- {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
- {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
+ {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
+ {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
#endif
{}
};
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 6ddad92..5c98866 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@
a complete debugging environment.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080AQDS board Overview
-----------------------
diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b76ea61..eba62c3 100644
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
@@ -28,10 +28,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -42,10 +42,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..897793d 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -282,7 +282,9 @@
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 6708ca9..b1613ba 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -5,48 +5,9 @@
Layerscape Architecture processor.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080ARDB board Overview
-----------------------
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index b3c6306..8d5a490 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -28,10 +28,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
- {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
- {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,},
+ {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,},
+ {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
@@ -42,10 +42,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6..52e5e3f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -156,7 +156,9 @@
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
u32 val;
init_final_memctl_regs();
@@ -178,8 +180,10 @@
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
return 0;
}
@@ -261,7 +265,9 @@
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 8d88bc0..8849681 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -24,7 +24,7 @@
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 92cef2a..a96a599 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -24,7 +24,7 @@
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 40bd55d..7c44282 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -274,11 +274,11 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 660d1bb..86eb694 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -13,18 +13,14 @@
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
-
obj-y += p1010rdb.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-
-endif
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index eb8e567..f858408 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -72,6 +72,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index a582127..9793853 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -13,17 +13,15 @@
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
obj-y += p1022ds.o
obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
obj-$(CONFIG_FSL_DIU_FB) += diu.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 89ef95a..04db767 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -86,6 +86,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a2a1f92..045d409 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -13,17 +13,14 @@
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
-
-obj-y += p1_p2_rdb_pc.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
+obj-y += p1_p2_rdb_pc.o
+obj-y += ddr.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 0142746..76a3cf4 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -83,6 +83,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index c74f4c6..a335ec6 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -7,6 +7,6 @@
#
obj-y += p2041rdb.o
-obj-y += cpld.o
+obj-y += cpld.o
obj-y += ddr.o
obj-y += eth.o
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
index d94f230..afbc914 100644
--- a/board/freescale/t102xqds/Makefile
+++ b/board/freescale/t102xqds/Makefile
@@ -5,7 +5,7 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += t102xqds.o
obj-y += eth_t102xqds.o
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f..c26f350 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -35,18 +35,18 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
@@ -172,14 +172,13 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 073ff2d..d59d343 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -120,6 +120,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 0520066..6452865 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -5,7 +5,7 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += t102xrdb.o
obj-$(CONFIG_T1024RDB) += cpld.o
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5..edfbdbf 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -34,12 +34,12 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};
@@ -234,12 +234,12 @@
puts("Initializing....using SPD\n");
#endif
dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da97c44..bd3cbbf 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -107,6 +107,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
index a6e1673..1e08746 100644
--- a/board/freescale/t1040qds/ddr.h
+++ b/board/freescale/t1040qds/ddr.h
@@ -29,18 +29,18 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index cf79d2d..22d6a5f 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -124,15 +124,12 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index b9c02f7..012991c 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -29,20 +29,20 @@
* ranks| mhz| GB |adjst| start | ctl2
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
+ {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
- {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
- {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 833, 4, 8, 6, 0x06060607, 0x08080807},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807},
+ {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 833, 4, 8, 6, 0x06060607, 0x08080807},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807},
+ {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 81f48c4..4b35af6 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -98,6 +98,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index deda092..d747de3 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -1,5 +1,5 @@
T208XQDS BOARD
-#M: -
+M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
S: Maintained
F: board/freescale/t208xqds/
F: include/configs/T208xQDS.h
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 6cb72c9..ef04a26 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,10 +7,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080QDS) += t208xqds.o
-obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o
-obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f1aff54..f96470f 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -108,13 +108,12 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
return dram_size;
}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9c26fdf..255ab2c 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -28,17 +28,17 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
- {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
- {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
- {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
- {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
- {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
- {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
+ {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
+ {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
+ {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
+ {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
+ {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
+ {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
@@ -49,15 +49,15 @@
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
/* TODO: need tuning these parameters if RDIMM is used */
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 55a0f8f..bb02dab 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -106,6 +106,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 1642879..ccbfbab 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
T208XRDB BOARD
-#M: -
+M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
S: Maintained
F: board/freescale/t208xrdb/
F: include/configs/T208xRDB.h
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 9605f8b..cd8fe09 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -5,11 +5,9 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o
-obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
-obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 053f128..f6c8ca3 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -101,12 +101,12 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
index 08cbb60..175cf56 100644
--- a/board/freescale/t208xrdb/ddr.h
+++ b/board/freescale/t208xrdb/ddr.h
@@ -28,16 +28,16 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
- {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
- {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
- {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
+ {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
+ {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{}
};
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index f63366b..2ff05a2 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -76,6 +76,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index bd2c1f1..731ccb0 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -5,12 +5,12 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o
obj-$(CONFIG_PCI) += pci.o
endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 62d58c5..d533924 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,13 +117,12 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 4d0e3c4..0b0cc9a 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -31,16 +31,16 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -50,15 +50,15 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index d52059a..6ca0f03 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -116,6 +116,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 83b55ee..4f29eea 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,13 +5,14 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T4240RDB) += t4240rdb.o
-obj-y += cpld.o
-obj-y += eth.o
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += cpld.o
+obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 27b37b5..230f031 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -110,13 +110,12 @@
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
return dram_size;
}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
index 7b85476..f01ebb2 100644
--- a/board/freescale/t4rdb/ddr.h
+++ b/board/freescale/t4rdb/ddr.h
@@ -27,16 +27,16 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
{}
};
@@ -46,15 +46,15 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index e563a61..ae2451e 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -77,6 +77,9 @@
puts("Invalid SerDes1 protocol for T4240RDB\n");
}
+ fm_disable_port(FM1_DTSEC5);
+ fm_disable_port(FM1_DTSEC6);
+
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
@@ -115,6 +118,8 @@
puts("Invalid SerDes2 protocol for T4240RDB\n");
}
+ fm_disable_port(FM2_DTSEC5);
+ fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 4c1e0cc..b148a7f 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -80,6 +80,7 @@
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 3b7c82b..e2eeef3 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -738,7 +738,7 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
static int ft_sethdmiinfmt(void *blob, char *mode)
{
@@ -939,7 +939,7 @@
return 0;
}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
static struct mxc_serial_platdata ventana_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART2_BASE,
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index ce23045..d4f0e70 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -16,3 +16,4 @@
obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
obj-$(CONFIG_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
+obj-$(CONFIG_STRIDER_CON_DP) += osd.o
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
index 96f02d6..f72a01e 100644
--- a/board/gdsys/common/ioep-fpga.c
+++ b/board/gdsys/common/ioep-fpga.c
@@ -25,8 +25,9 @@
enum {
COMPRESSION_NONE = 0,
- COMPRESSION_TYPE1_DELTA = 1,
- COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+ COMPRESSION_TYPE_1 = 1,
+ COMPRESSION_TYPE_1_2 = 3,
+ COMPRESSION_TYPE_1_2_3 = 7,
};
enum {
@@ -158,12 +159,16 @@
printf(" no compression");
break;
- case COMPRESSION_TYPE1_DELTA:
- printf(" type1-deltacompression");
+ case COMPRESSION_TYPE_1:
+ printf(" compression type1(delta)");
break;
- case COMPRESSION_TYPE1_TYPE2_DELTA:
- printf(" type1-deltacompression, type2-inlinecompression");
+ case COMPRESSION_TYPE_1_2:
+ printf(" compression type1(delta), type2(inline)");
+ break;
+
+ case COMPRESSION_TYPE_1_2_3:
+ printf(" compression type1(delta), type2(inline), type3(intempo)");
break;
default:
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 4e292f5..add9574 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -469,6 +469,9 @@
}
for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+ if (!(osd_screen_mask & (1 << screen)))
+ continue;
+
OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 8d01d8b..2d7d789 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -203,7 +203,7 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
extern void __ft_board_setup(void *blob, bd_t *bd);
int ft_board_setup(void *blob, bd_t *bd)
@@ -218,4 +218,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index eee582b..121977d 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -133,6 +133,9 @@
unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
+#ifdef CONFIG_STRIDER_CON_DP
+ bool is_dh = pca9698_get_value(0x20, 25);
+#endif
bool ch0_sgmii2_present = false;
/* Turn on Analog Devices ADV7611 */
@@ -140,6 +143,7 @@
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 10, 1);
+ pca9698_direction_output(0x20, 11, 1);
ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
@@ -202,6 +206,14 @@
osd_probe(0);
#endif
+#ifdef CONFIG_STRIDER_CON_DP
+ if (ioep_fpga_has_osd(0)) {
+ osd_probe(0);
+ if (is_dh)
+ osd_probe(4);
+ }
+#endif
+
#ifdef CONFIG_STRIDER_CPU
ch7301_probe(0, false);
dp501_probe(0, false);
@@ -226,6 +238,13 @@
if (ioep_fpga_has_osd(k))
osd_probe(k);
#endif
+#ifdef CONFIG_STRIDER_CON_DP
+ if (ioep_fpga_has_osd(k)) {
+ osd_probe(k);
+ if (is_dh)
+ osd_probe(k + 4);
+ }
+#endif
#ifdef CONFIG_STRIDER_CPU
if (!adv7611_probe(k))
printf(" Advantiv ADV7611 HDMI Receiver\n");
@@ -270,6 +289,24 @@
return val & pin;
}
+#ifdef CONFIG_STRIDER_CON_DP
+void fpga_control_set(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, control, &val);
+ FPGA_SET_REG(bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, control, &val);
+ FPGA_SET_REG(bus, control, val & ~pin);
+}
+#endif
+
void mpc8308_init(void)
{
pca9698_direction_output(0x20, 26, 1);
diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig
new file mode 100644
index 0000000..687d9c6
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_C2
+
+config SYS_BOARD
+ default "odroid-c2"
+
+config SYS_VENDOR
+ default "hardkernel"
+
+config SYS_CONFIG_NAME
+ default "odroid-c2"
+
+endif
diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS
new file mode 100644
index 0000000..23ae1e7
--- /dev/null
+++ b/board/hardkernel/odroid-c2/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID-C2
+M: Beniamino Galvani <b.galvani@gmail.com>
+S: Maintained
+F: board/hardkernel/odroid-c2/
+F: include/configs/odroid-c2.h
+F: configs/odroid-c2_defconfig
diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile
new file mode 100644
index 0000000..571044b6
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := odroid-c2.o
diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README
new file mode 100644
index 0000000..d6d266a
--- /dev/null
+++ b/board/hardkernel/odroid-c2/README
@@ -0,0 +1,60 @@
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-c2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > DIR=odroid-c2
+ > git clone --depth 1 \
+ https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+ $DIR
+ > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \
+ --bl301 $DIR/fip/gxb/bl301.bin \
+ --bl31 $DIR/fip/gxb/bl31.bin \
+ --bl33 u-boot.bin \
+ $DIR/fip.bin
+ > $DIR/fip/fip_create --dump $DIR/fip.bin
+ > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+ > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+ --input $DIR/boot_new.bin \
+ --output $DIR/u-boot.img
+ > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+ > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+ > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+ > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
new file mode 100644
index 0000000..bd72100
--- /dev/null
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <dm/platdata.h>
+#include <phy.h>
+
+#define EFUSE_SN_OFFSET 20
+#define EFUSE_SN_SIZE 16
+#define EFUSE_MAC_OFFSET 52
+#define EFUSE_MAC_SIZE 6
+
+int board_init(void)
+{
+ return 0;
+}
+
+static const struct eth_pdata gxbb_eth_pdata = {
+ .iobase = GXBB_ETH_BASE,
+ .phy_interface = PHY_INTERFACE_MODE_RGMII,
+};
+
+U_BOOT_DEVICE(meson_eth) = {
+ .name = "eth_designware",
+ .platdata = &gxbb_eth_pdata,
+};
+
+int misc_init_r(void)
+{
+ u8 mac_addr[EFUSE_MAC_SIZE];
+ ssize_t len;
+
+ /* Select Ethernet function */
+ setbits_le32(GXBB_PINMUX(6), 0x3fff);
+
+ /* Set RGMII mode */
+ setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+ GXBB_ETH_REG_0_TX_PHASE(1) |
+ GXBB_ETH_REG_0_TX_RATIO(4) |
+ GXBB_ETH_REG_0_PHY_CLK_EN |
+ GXBB_ETH_REG_0_CLK_EN);
+
+ /* Enable power and clock gate */
+ setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+ clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+ /* Reset PHY on GPIOZ_14 */
+ clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
+ clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+ mdelay(10);
+ setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ mac_addr, EFUSE_MAC_SIZE);
+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ return 0;
+}
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 72932ca..75bf1bb 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -607,11 +607,11 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index ca09767..4fc6809 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -303,7 +303,7 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
@@ -383,4 +383,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 4c06d0c..98eb4d1 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -9,4 +9,8 @@
config SYS_CONFIG_NAME
default "malta"
+config SYS_TEXT_BASE
+ default 0xbe000000 if 32BIT
+ default 0xffffffffbe000000 if 64BIT
+
endif
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 534db1d..3d48cdc 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
#include <pci.h>
#include <asm/addrspace.h>
+#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/malta.h>
#include <asm/mipsregs.h>
@@ -34,7 +35,7 @@
mtc0 t0, CP0_CONFIG, 2
/* detect the core card */
- li t0, KSEG1ADDR(MALTA_REVISION)
+ PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
lw t0, 0(t0)
srl t0, t0, MALTA_REVISION_CORID_SHF
andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@
*/
_gt64120:
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
- li t1, KSEG1ADDR(GT_DEF_BASE)
+ PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
li t0, CPU_TO_GT32(0xdf000000)
sw t0, GT_ISD_OFS(t1)
/* setup MEM-to-PCI0 mapping */
- li t1, KSEG1ADDR(MALTA_GT_BASE)
+ PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
/* setup PCI0 io window to 0x18000000-0x181fffff */
li t0, CPU_TO_GT32(0xc0000000)
@@ -100,7 +101,7 @@
*/
_msc01:
/* setup peripheral bus controller clock divide */
- li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
sw t1, MSC01_PBC_CLKCFG_OFS(t0)
@@ -122,7 +123,7 @@
sw t1, MSC01_PBC_CS0CFG_OFS(t0)
/* setup basic address decode */
- li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
li t2, -CONFIG_SYS_MEM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@
sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
/* setup PCI memory */
- li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
li t1, MALTA_MSC01_PCIMEM_BASE
li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
li t3, MALTA_MSC01_PCIMEM_MAP
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 3a9e780..4955043 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -12,7 +12,6 @@
#include <pci_gt64120.h>
#include <pci_msc01.h>
#include <rtc.h>
-#include <serial.h>
#include <asm/addrspace.h>
#include <asm/io.h>
@@ -161,18 +160,6 @@
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- return &eserial1_device;
-
- default:
- case SYSCON_MSC01:
- return &eserial2_device;
- }
-}
-
void pci_init_board(void)
{
pci_dev_t bdf;
diff --git a/board/intel/galileo/.gitignore b/board/intel/galileo/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/galileo/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile
index 8356df1..bbe2f8b 100644
--- a/board/intel/galileo/Makefile
+++ b/board/intel/galileo/Makefile
@@ -5,3 +5,4 @@
#
obj-y += galileo.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/galileo/acpi/mainboard.asl b/board/intel/galileo/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/galileo/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/galileo/dsdt.asl b/board/intel/galileo/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/galileo/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+ /* platform specific */
+ #include <asm/arch/acpi/platform.asl>
+
+ /* board specific */
+ #include "acpi/mainboard.asl"
+}
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 4ab7160..2e52d51 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -378,7 +378,7 @@
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CMD_IDE */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
static void ft_delete_node(void *fdt, const char *compat)
{
int off = -1;
@@ -481,4 +481,4 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index 2078f53..2e62355 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -195,7 +195,7 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
@@ -203,7 +203,7 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
int board_eth_init(bd_t *bis)
{
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 8856393..d56902b 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -282,11 +282,11 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
index 8acb393..4f08e98 100644
--- a/board/microchip/pic32mzda/Kconfig
+++ b/board/microchip/pic32mzda/Kconfig
@@ -10,4 +10,7 @@
config SYS_CONFIG_NAME
default "pic32mzdask"
+config SYS_TEXT_BASE
+ default 0x9d004000
+
endif
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index c518079..df7c029 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -9,6 +9,21 @@
config SYS_CONFIG_NAME
default "vct"
+config SYS_TEXT_BASE
+ default 0x87000000
+
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
menu "vct board options"
choice
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 4d0ebaa..dc237c1 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -184,14 +184,14 @@
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_STATUS_LED)
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 23d0f56..8f292ea 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -145,11 +145,11 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index ba15e2e..f04f843 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -110,11 +110,11 @@
}
/* GPIO: PEX = 3.3V */
- err = gpio_request(GPIO_PL7, "PEX");
+ err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
if (err < 0)
return err;
- gpio_direction_output(GPIO_PL7, 1);
+ gpio_direction_output(TEGRA_GPIO(L, 7), 1);
/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
data[0] = 0x15;
diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
index 7eb1e6c..7955ca5 100644
--- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
+++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
@@ -15,71 +15,71 @@
#ifndef _PINMUX_CONFIG_E2220_1170_H_
#define _PINMUX_CONFIG_E2220_1170_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(A6, IN),
- GPIO_INIT(B4, IN),
- GPIO_INIT(E6, IN),
- GPIO_INIT(G2, OUT0),
- GPIO_INIT(G3, OUT0),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H1, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, OUT0),
- GPIO_INIT(H7, OUT0),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I3, OUT0),
- GPIO_INIT(K0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, OUT0),
- GPIO_INIT(K3, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, OUT0),
- GPIO_INIT(L0, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V3, IN),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y0, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(BB4, IN),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC5, OUT0),
- GPIO_INIT(CC6, IN),
- GPIO_INIT(CC7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(A, 6, IN),
+ GPIO_INIT(B, 4, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 2, OUT0),
+ GPIO_INIT(G, 3, OUT0),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 1, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, OUT0),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 3, OUT0),
+ GPIO_INIT(K, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, OUT0),
+ GPIO_INIT(K, 3, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, OUT0),
+ GPIO_INIT(L, 0, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 3, IN),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 0, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(BB, 4, IN),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 5, OUT0),
+ GPIO_INIT(CC, 6, IN),
+ GPIO_INIT(CC, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index 00e0cdc..01237db 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -15,63 +15,63 @@
#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
#define _PINMUX_CONFIG_JETSON_TK1_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(G4, IN),
- GPIO_INIT(H2, OUT0),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H7, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I6, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(N7, IN),
- GPIO_INIT(O1, IN),
- GPIO_INIT(O4, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q5, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R2, OUT0),
- GPIO_INIT(R4, IN),
- GPIO_INIT(R7, IN),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U0, IN),
- GPIO_INIT(U1, IN),
- GPIO_INIT(U2, IN),
- GPIO_INIT(U3, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(V1, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(BB5, OUT0),
- GPIO_INIT(BB6, OUT0),
- GPIO_INIT(BB7, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC2, IN),
- GPIO_INIT(EE2, OUT1),
+ /* port, pin, init_val */
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(G, 4, IN),
+ GPIO_INIT(H, 2, OUT0),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 7, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(O, 1, IN),
+ GPIO_INIT(O, 4, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 5, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 2, OUT0),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(R, 7, IN),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 0, IN),
+ GPIO_INIT(U, 1, IN),
+ GPIO_INIT(U, 2, IN),
+ GPIO_INIT(U, 3, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(BB, 5, OUT0),
+ GPIO_INIT(BB, 6, OUT0),
+ GPIO_INIT(BB, 7, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 2, IN),
+ GPIO_INIT(EE, 2, OUT1),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ba96401..8f68ae9 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -36,8 +36,9 @@
int tegra_board_id(void)
{
- static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
- GPIO_PX4, -1};
+ static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+ TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+ -1};
gpio_claim_vector(vector, "board_id%d");
return gpio_get_values_as_int(vector);
diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
index dca0171..fd7f1d1 100644
--- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h
+++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -15,59 +15,59 @@
#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
#define _PINMUX_CONFIG_NYAN_BIG_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT1),
- GPIO_INIT(I0, IN),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I5, OUT1),
- GPIO_INIT(I6, IN),
- GPIO_INIT(I7, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(J7, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(K7, IN),
- GPIO_INIT(N7, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q2, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, IN),
- GPIO_INIT(R4, IN),
- GPIO_INIT(R7, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(C, 7, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT1),
+ GPIO_INIT(I, 0, IN),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 5, OUT1),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(I, 7, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 2, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 6, IN),
+ GPIO_INIT(Q, 7, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 1, IN),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(R, 7, IN),
+ GPIO_INIT(S, 3, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(W, 3, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
index 35706b4..24acbcc 100644
--- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
+++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
@@ -15,62 +15,62 @@
#ifndef _PINMUX_CONFIG_P2371_0000_H_
#define _PINMUX_CONFIG_P2371_0000_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(E4, OUT0),
- GPIO_INIT(E6, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G3, OUT0),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, OUT0),
- GPIO_INIT(H7, OUT0),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I3, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, OUT0),
- GPIO_INIT(L0, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(V7, OUT1),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC6, IN),
- GPIO_INIT(CC7, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(E, 4, OUT0),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 3, OUT0),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, OUT0),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 3, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, OUT0),
+ GPIO_INIT(L, 0, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(V, 7, OUT1),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 6, IN),
+ GPIO_INIT(CC, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
index d5be6ec..601728e 100644
--- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
+++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
@@ -15,73 +15,73 @@
#ifndef _PINMUX_CONFIG_P2371_2180_H_
#define _PINMUX_CONFIG_P2371_2180_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(B0, IN),
- GPIO_INIT(B1, IN),
- GPIO_INIT(B2, IN),
- GPIO_INIT(B3, IN),
- GPIO_INIT(C0, IN),
- GPIO_INIT(C1, IN),
- GPIO_INIT(C2, IN),
- GPIO_INIT(C3, IN),
- GPIO_INIT(C4, IN),
- GPIO_INIT(E4, IN),
- GPIO_INIT(E5, IN),
- GPIO_INIT(E6, IN),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H1, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, IN),
- GPIO_INIT(L1, IN),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(U2, IN),
- GPIO_INIT(U3, IN),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V3, IN),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y0, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z2, IN),
- GPIO_INIT(Z3, OUT0),
- GPIO_INIT(BB0, IN),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, IN),
- GPIO_INIT(CC1, IN),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(B, 0, IN),
+ GPIO_INIT(B, 1, IN),
+ GPIO_INIT(B, 2, IN),
+ GPIO_INIT(B, 3, IN),
+ GPIO_INIT(C, 0, IN),
+ GPIO_INIT(C, 1, IN),
+ GPIO_INIT(C, 2, IN),
+ GPIO_INIT(C, 3, IN),
+ GPIO_INIT(C, 4, IN),
+ GPIO_INIT(E, 4, IN),
+ GPIO_INIT(E, 5, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 1, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(K, 4, IN),
+ GPIO_INIT(K, 5, OUT0),
+ GPIO_INIT(K, 6, IN),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(L, 1, IN),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 5, OUT0),
+ GPIO_INIT(S, 6, OUT0),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(T, 1, OUT0),
+ GPIO_INIT(U, 2, IN),
+ GPIO_INIT(U, 3, IN),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 2, OUT0),
+ GPIO_INIT(V, 3, IN),
+ GPIO_INIT(V, 5, OUT0),
+ GPIO_INIT(V, 6, OUT0),
+ GPIO_INIT(X, 0, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 2, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 0, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 2, IN),
+ GPIO_INIT(Z, 3, OUT0),
+ GPIO_INIT(BB, 0, IN),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(BB, 3, IN),
+ GPIO_INIT(CC, 1, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index d80a7d0..7ce656f 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -58,6 +58,6 @@
void start_cpu_fan(void)
{
/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
- gpio_request(GPIO_PE4, "FAN_VDD");
- gpio_direction_output(GPIO_PE4, 1);
+ gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+ gpio_direction_output(TEGRA_GPIO(E, 4), 1);
}
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
index d323301..dd4228f 100644
--- a/board/nvidia/p2571/pinmux-config-p2571.h
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -15,37 +15,37 @@
#ifndef _PINMUX_CONFIG_P2571_H_
#define _PINMUX_CONFIG_P2571_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config p2571_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(A5, IN),
- GPIO_INIT(D4, IN),
- GPIO_INIT(E4, OUT0),
- GPIO_INIT(G0, IN),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V6, OUT1),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC3, IN),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(D, 4, IN),
+ GPIO_INIT(E, 4, OUT0),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(V, 1, OUT0),
+ GPIO_INIT(V, 6, OUT1),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(X, 7, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 4, OUT0),
+ GPIO_INIT(BB, 2, OUT0),
+ GPIO_INIT(CC, 1, IN),
+ GPIO_INIT(CC, 3, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
new file mode 100644
index 0000000..1b1116f
--- /dev/null
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+ default "p2771-0000"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p2771-0000"
+
+endif
diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS
new file mode 100644
index 0000000..4fc4ebd
--- /dev/null
+++ b/board/nvidia/p2771-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P2771-0000 BOARD
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p2771-0000/
+F: include/configs/p2771-0000.h
+F: configs/p2771-0000_defconfig
diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile
new file mode 100644
index 0000000..b28a47d
--- /dev/null
+++ b/board/nvidia/p2771-0000/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += p2771-0000.o
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
new file mode 100644
index 0000000..4ba8ebc
--- /dev/null
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 2d07001..fc9c1c9 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,8 +20,8 @@
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
- gpio_request(GPIO_PI3, "uart_en");
- gpio_direction_output(GPIO_PI3, 0);
+ gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+ gpio_direction_output(TEGRA_GPIO(I, 3), 0);
}
#endif
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index fb444b3..59d53ef 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -15,70 +15,70 @@
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
-#define GPIO_INIT(_gpio, _init) \
+#define GPIO_INIT(_port, _gpio, _init) \
{ \
- .gpio = GPIO_P##_gpio, \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config venice2_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A0, IN),
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, IN),
- GPIO_INIT(G1, IN),
- GPIO_INIT(G2, IN),
- GPIO_INIT(G3, IN),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H4, IN),
- GPIO_INIT(H5, OUT0),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT1),
- GPIO_INIT(I0, IN),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I4, OUT0),
- GPIO_INIT(I5, OUT1),
- GPIO_INIT(I6, IN),
- GPIO_INIT(J0, IN),
- GPIO_INIT(J7, IN),
- GPIO_INIT(K0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, IN),
- GPIO_INIT(K3, IN),
- GPIO_INIT(K4, OUT0),
- GPIO_INIT(K6, OUT0),
- GPIO_INIT(K7, IN),
- GPIO_INIT(N7, IN),
- GPIO_INIT(O2, IN),
- GPIO_INIT(O5, IN),
- GPIO_INIT(O6, OUT0),
- GPIO_INIT(O7, IN),
- GPIO_INIT(P2, OUT0),
- GPIO_INIT(Q0, IN),
- GPIO_INIT(Q2, IN),
- GPIO_INIT(Q3, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
- GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, IN),
- GPIO_INIT(R4, IN),
- GPIO_INIT(S0, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S7, IN),
- GPIO_INIT(T1, IN),
- GPIO_INIT(U4, IN),
- GPIO_INIT(U5, IN),
- GPIO_INIT(U6, IN),
- GPIO_INIT(V0, IN),
- GPIO_INIT(V1, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X7, OUT0),
- GPIO_INIT(CC5, OUT0),
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(C, 7, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 5, OUT0),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT1),
+ GPIO_INIT(I, 0, IN),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(I, 4, OUT0),
+ GPIO_INIT(I, 5, OUT1),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(K, 0, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 3, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(O, 2, IN),
+ GPIO_INIT(O, 5, IN),
+ GPIO_INIT(O, 6, OUT0),
+ GPIO_INIT(O, 7, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 2, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 6, IN),
+ GPIO_INIT(Q, 7, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 1, IN),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(S, 0, IN),
+ GPIO_INIT(S, 3, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(W, 3, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 3, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
+ GPIO_INIT(CC, 5, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 251db6a..ef8905d 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -9,4 +9,19 @@
config SYS_CONFIG_NAME
default "pb1x00"
+config SYS_TEXT_BASE
+ default 0x83800000
+
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
endif
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 81f3024..d91d427 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -429,7 +429,7 @@
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
struct node_info nodes[] = {
{ "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
@@ -529,7 +529,7 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
/*
* If argument is NULL, set the LCD brightness to the
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index ed41de1..8a9de0d 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -163,14 +163,14 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index f7e768a..4fd6a71 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -9,4 +9,19 @@
config SYS_CONFIG_NAME
default "ap121"
+config SYS_TEXT_BASE
+ default 0x9f000000
+
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
endif
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
index d6c60fe..e245faa 100644
--- a/board/qca/ap121/ap121.c
+++ b/board/qca/ap121/ap121.c
@@ -10,6 +10,7 @@
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
+#include <mach/ath79.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,5 +47,6 @@
debug_uart_init();
#endif
ddr_init();
+ ath79_eth_reset();
return 0;
}
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 4cdac0d..74c632a 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -9,4 +9,19 @@
config SYS_CONFIG_NAME
default "ap143"
+config SYS_TEXT_BASE
+ default 0x9f000000
+
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
endif
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
index 1572472..e921ea5 100644
--- a/board/qca/ap143/ap143.c
+++ b/board/qca/ap143/ap143.c
@@ -10,6 +10,7 @@
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
+#include <mach/ath79.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -62,5 +63,6 @@
debug_uart_init();
#endif
ddr_init();
+ ath79_eth_reset();
return 0;
}
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 18d78b5..e696a12 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -7,4 +7,20 @@
default "qemu-mips" if 32BIT
default "qemu-mips64" if 64BIT
+config SYS_TEXT_BASE
+ default 0xbfc00000 if 32BIT
+ default 0xffffffffbfc00000 if 64BIT
+
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
endif
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
index 053df64..6cd4056 100644
--- a/board/renesas/sh7752evb/u-boot.lds
+++ b/board/renesas/sh7752evb/u-boot.lds
@@ -65,6 +65,7 @@
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
index 053df64..6cd4056 100644
--- a/board/renesas/sh7753evb/u-boot.lds
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -65,6 +65,7 @@
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
index 4027fe3..d701367 100644
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -66,6 +66,7 @@
KEEP(*(SORT(.u_boot_list*)));
}
+ PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 3cc01cb..e2cb94e 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -194,7 +194,7 @@
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 276ff80..e9f9b67 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -293,7 +293,7 @@
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
+ nand_size += nand_info[i]->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS
new file mode 100644
index 0000000..c2002fe
--- /dev/null
+++ b/board/samtec/vining_fpga/MAINTAINERS
@@ -0,0 +1,5 @@
+VINING FPGA BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: include/configs/socfpga_vining_fpga.h
+F: configs/socfpga_vining_fpga_defconfig
diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile
new file mode 100644
index 0000000..86f9b78
--- /dev/null
+++ b/board/samtec/vining_fpga/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h
new file mode 100644
index 0000000..fe5cb61
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00000000,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00000000,
+ 0x300C0000,
+ 0x000000C0,
+ 0x00000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x01800000,
+ 0x00000006,
+ 0x00601806,
+ 0x00000400,
+ 0x00000000,
+ 0x00C03000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00601806,
+ 0x00000000,
+ 0x80600000,
+ 0x80000601,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x300C0300,
+ 0x300C0000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x000300C0,
+ 0x00008000,
+ 0x18060180,
+ 0x18060000,
+ 0x00000000,
+ 0x00000000,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x00000030,
+ 0x00000000,
+ 0x0300C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+ 0x0000C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680A28,
+ 0x41034051,
+ 0x12481A00,
+ 0x80A280D0,
+ 0x34051406,
+ 0x01A02490,
+ 0x080D0000,
+ 0x51406802,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680208,
+ 0x49034051,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x5140680A,
+ 0x02490340,
+ 0xD012481A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0x8A28A3D5,
+ 0xF6D1451E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD569A47A,
+ 0x1E8A28A3,
+ 0x48F6D145,
+ 0x00035292,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0x8A28A3D5,
+ 0xF4D1451E,
+ 0x034AD348,
+ 0x821A0186,
+ 0x0000D000,
+ 0x00000680,
+ 0xD569A47A,
+ 0x1EF228A3,
+ 0x48F4D145,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F36080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x0C864000,
+ 0x59647A03,
+ 0xCB2CA3DD,
+ 0xF6D9651E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDD59647A,
+ 0x1E8A28A3,
+ 0x48F6D965,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0x7FFFFFFF,
+ 0x14F16080,
+ 0x1A041404,
+ 0x00D00000,
+ 0x04864000,
+ 0x69A47A01,
+ 0xF228A3D5,
+ 0xF4D1451E,
+ 0x03529248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD559647A,
+ 0x1E8A28A3,
+ 0x48F6D145,
+ 0x00034AD3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h
new file mode 100644
index 0000000..9680365
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 2, /* FLASHIO0 */
+ 2, /* FLASHIO1 */
+ 2, /* FLASHIO2 */
+ 2, /* FLASHIO3 */
+ 2, /* FLASHIO4 */
+ 2, /* FLASHIO5 */
+ 2, /* FLASHIO6 */
+ 2, /* FLASHIO7 */
+ 2, /* FLASHIO8 */
+ 2, /* FLASHIO9 */
+ 2, /* FLASHIO10 */
+ 2, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 2, /* GENERALIO15 */
+ 2, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 2, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 1, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 1, /* SPIS1USEFPGA */
+ 1, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h
new file mode 100644
index 0000000..c8a6e96
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pll_config.h
@@ -0,0 +1,91 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h
new file mode 100644
index 0000000..74cb405
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -0,0 +1,341 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090046,
+ 0x100a0088,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0026,
+ 0x10090110,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
new file mode 100644
index 0000000..f3a92b5
--- /dev/null
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_late_init(void)
+{
+ const unsigned int phy_nrst_gpio = 0;
+ const unsigned int usb_nrst_gpio = 35;
+ int ret;
+
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
+
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
+ if (!ret)
+ gpio_direction_output(phy_nrst_gpio, 1);
+ else
+ printf("Cannot remove PHY from reset!\n");
+
+ ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
+ if (!ret)
+ gpio_direction_output(usb_nrst_gpio, 1);
+ else
+ printf("Cannot remove USB from reset!\n");
+
+ mdelay(50);
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+ uchar data[128];
+ char str[32];
+ u32 serial;
+ int ret;
+
+ /* EEPROM is at bus 0. */
+ ret = i2c_set_bus_num(0);
+ if (ret) {
+ puts("Cannot select EEPROM I2C bus.\n");
+ return 0;
+ }
+
+ /* EEPROM is at address 0x50. */
+ ret = eeprom_read(0x50, 0, data, sizeof(data));
+ if (ret) {
+ puts("Cannot read I2C EEPROM.\n");
+ return 0;
+ }
+
+ /* Check EEPROM signature. */
+ if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
+ puts("Invalid I2C EEPROM signature.\n");
+ setenv("unit_serial", "invalid");
+ setenv("unit_ident", "VINing-xxxx-STD");
+ setenv("hostname", "vining-invalid");
+ return 0;
+ }
+
+ /* If 'unit_serial' is already set, do nothing. */
+ if (!getenv("unit_serial")) {
+ /* This field is Big Endian ! */
+ serial = (data[0x54] << 24) | (data[0x55] << 16) |
+ (data[0x56] << 8) | (data[0x57] << 0);
+ memset(str, 0, sizeof(str));
+ sprintf(str, "%07i", serial);
+ setenv("unit_serial", str);
+ }
+
+ if (!getenv("unit_ident")) {
+ memset(str, 0, sizeof(str));
+ memcpy(str, &data[0x2e], 18);
+ setenv("unit_ident", str);
+ }
+
+ /* Set ethernet address from EEPROM. */
+ if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62]))
+ eth_setenv_enetaddr("ethaddr", &data[0x62]);
+
+ return 0;
+}
+#endif
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index fa1842b..9fe3bf1 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -186,8 +186,7 @@
A wide range of commands is implemented. Filesystems which use a block
device are supported.
-Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
-driver model (CONFIG_DM) and associated commands.
+Also sandbox supports driver model (CONFIG_DM) and associated commands.
Linux RAW Networking Bridge
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 15e6ea6..a67d812 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -48,7 +48,7 @@
static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
for (i = 0; i < len; i++) {
out_be32(this->IO_ADDR_W,
@@ -88,7 +88,7 @@
static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int val;
val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
@@ -105,7 +105,7 @@
*/
static int sc_nand_device_ready(struct mtd_info *mtdinfo)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
return 0; /* busy */
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 953a43f..8b34a80 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -217,7 +217,7 @@
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[12];
@@ -253,7 +253,7 @@
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
#define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31)
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index b8edfcd..f8e9fdd 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <micrel.h>
#include <nand.h>
#include <netdev.h>
#include <phy.h>
@@ -69,27 +70,64 @@
int board_phy_config(struct phy_device *phydev)
{
- /* Extended PHY control 1, select GMII */
- phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+ unsigned short id1, id2;
- /* Software reset necessary after GMII mode selction */
- phy_reset(phydev);
+ /* check whether KSZ9031 or AR8035 has to be configured */
+ id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+ id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
- /* Enable extended page register access */
- phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+ if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+ /* PHY configuration for Micrel KSZ9031 */
+ printf("PHY KSZ9031 detected - ");
- /* 17e: Enhanced LED behavior, needs to be written twice */
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
- phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
- /* 16e: Enhanced LED method select */
- phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ 0x03FF);
+ } else {
+ /* PHY configuration for Vitesse VSC8641 */
+ printf("PHY VSC8641 detected - ");
- /* Disable extended page register access */
- phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
+ /* Extended PHY control 1, select GMII */
+ phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+
+ /* Software reset necessary after GMII mode selction */
+ phy_reset(phydev);
+
+ /* Enable extended page register access */
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+
+ /* 17e: Enhanced LED behavior, needs to be written twice */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+
+ /* 16e: Enhanced LED method select */
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+
+ /* Disable extended page register access */
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
- /* Enable clock output pin */
- phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+ /* Enable clock output pin */
+ phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+ }
if (phydev->drv->config)
phydev->drv->config(phydev);
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index fa78720..c1ae6f5 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -18,7 +18,6 @@
choice
prompt "Sunxi SoC Variant"
- optional
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
@@ -68,6 +67,12 @@
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_A83T
+ bool "sun8i (Allwinner A83T)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
select CPU_V7
@@ -77,22 +82,16 @@
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-config MACH_SUN50I
- bool "sun50i (Allwinner A64)"
- select ARM64
- select SUNXI_GEN_SUN6I
-
-config MACH_SUN8I_A83T
- bool "sun8i (Allwinner A83T)"
- select CPU_V7
- select SUNXI_GEN_SUN6I
- select SUPPORT_SPL
-
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
select SUNXI_GEN_SUN6I
+config MACH_SUN50I
+ bool "sun50i (Allwinner A64)"
+ select ARM64
+ select SUNXI_GEN_SUN6I
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -261,6 +260,7 @@
config MMC0_CD_PIN
string "Card detect pin for mmc0"
+ default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
default ""
---help---
Set the card detect pin for mmc0, leave empty to not use cd. This
@@ -368,6 +368,7 @@
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default n if MACH_SUN6I || MACH_SUN8I
+ select CMD_I2C
---help---
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
its clock and setting up the bus. This is especially useful on devices
@@ -377,12 +378,14 @@
config I2C1_ENABLE
bool "Enable I2C/TWI controller 1"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
config I2C2_ENABLE
bool "Enable I2C/TWI controller 2"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
@@ -390,6 +393,7 @@
config I2C3_ENABLE
bool "Enable I2C/TWI controller 3"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
@@ -399,6 +403,7 @@
bool "Enable the PRCM I2C/TWI controller"
# This is used for the pmic on H3
default y if SY8106A_POWER
+ select CMD_I2C
---help---
Set this to y to enable the I2C controller which is part of the PRCM.
endif
@@ -407,6 +412,7 @@
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
@@ -419,7 +425,7 @@
config VIDEO
boolean "Enable graphical uboot console on HDMI, LCD or VGA"
- depends on !MACH_SUN8I_A83T
+ depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
@@ -535,6 +541,7 @@
bool "LCD panel needs to be configured via i2c"
depends on VIDEO
default n
+ select CMD_I2C
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3cf3614..d09cf6d 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,15 +133,6 @@
return 0;
}
-#ifdef CONFIG_MACH_SUN50I
-void dram_init_banksize(void)
-{
- /* We need to reserve the first 16MB of RAM for ATF */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
- gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024);
-}
-#endif
-
#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
static void nand_pinmux_setup(void)
{
@@ -483,10 +474,12 @@
#endif
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
- defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+ defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+ defined CONFIG_AXP818_POWER
power_failed = axp_init();
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+ defined CONFIG_AXP818_POWER
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
#endif
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
@@ -494,11 +487,13 @@
#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+ defined CONFIG_AXP818_POWER
power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+ defined CONFIG_AXP818_POWER
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
#endif
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
@@ -509,11 +504,14 @@
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
#endif
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
+ defined(CONFIG_AXP818_POWER)
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
+#if !defined CONFIG_AXP809_POWER
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
+#endif
power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
@@ -524,6 +522,10 @@
power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
#endif
+
+#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+ power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
+#endif
#endif
printf("DRAM:");
ramsize = sunxi_dram_init();
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 7dc2b83..c99e06d 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -6,7 +6,6 @@
F: configs/am335x_boneblack_defconfig
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
-F: configs/am335x_gp_evm_defconfig
F: configs/am335x_evm_nor_defconfig
F: configs/am335x_evm_norboot_defconfig
F: configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4330be6..56f4984 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -11,11 +11,13 @@
#include <common.h>
#include <errno.h>
#include <spl.h>
+#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
@@ -37,7 +39,13 @@
DECLARE_GLOBAL_DATA_PTR;
/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
#if defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
@@ -52,6 +60,16 @@
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
}
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+ if (board_is_icev2())
+ return &eserial4_device;
+ else
+ return &eserial1_device;
+}
+#endif
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
@@ -97,6 +115,13 @@
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
};
+static const struct ddr_data ddr3_icev2_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
@@ -130,6 +155,17 @@
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -162,6 +198,17 @@
PHY_EN_DYN_PWRDN,
};
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+ .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+ PHY_EN_DYN_PWRDN,
+};
+
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
@@ -339,7 +386,7 @@
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
- else if (board_is_bone_lt())
+ else if (board_is_bone_lt() || board_is_icev2())
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later())
return &dpll_ddr_evm_sk;
@@ -418,6 +465,11 @@
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
+ if (board_is_icev2()) {
+ gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+ }
+
if (board_is_evm_sk())
config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
@@ -429,12 +481,59 @@
else if (board_is_evm_15_or_later())
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+ else if (board_is_icev2())
+ config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+ &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+ 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void request_and_set_gpio(int gpio, char *name)
+{
+ int ret;
+
+ ret = gpio_request(gpio, name);
+ if (ret < 0) {
+ printf("%s: Unable to request %s\n", __func__, name);
+ return;
+ }
+
+ ret = gpio_direction_output(gpio, 0);
+ if (ret < 0) {
+ printf("%s: Unable to set %s as output\n", __func__, name);
+ goto err_free_gpio;
+ }
+
+ gpio_set_value(gpio, 1);
+
+ return;
+
+err_free_gpio:
+ gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+ .id = 0x81,
+ .capacitor = 0x90,
+ .mux = 0x6d,
+ .pdiv2 = 0x2,
+ .pdiv3 = 0x2,
+};
+#endif
+
/*
* Basic board specific setup. Pinmux has been handled already.
*/
@@ -448,6 +547,23 @@
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
+ int rv;
+
+ if (board_is_icev2()) {
+ REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+
+ rv = setup_clock_synthesizer(&cdce913_data);
+ if (rv) {
+ printf("Clock synthesizer setup failed %d\n", rv);
+ return rv;
+ }
+ }
+#endif
+
return 0;
}
@@ -515,6 +631,12 @@
};
#endif
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
@@ -526,11 +648,6 @@
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
- && defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
@@ -581,6 +698,12 @@
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
+ } else if (board_is_icev2()) {
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[0].phy_addr = 1;
+ cpsw_slaves[1].phy_addr = 3;
} else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -632,3 +755,23 @@
#endif
#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+ return 0;
+ else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+ return 0;
+ else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+ return 0;
+ else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+ return 0;
+ else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+ return 0;
+ else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 062c345..9776df7 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -47,6 +47,11 @@
strncmp("1.5", board_ti_get_rev(), 3) <= 0);
}
+static inline int board_is_icev2(void)
+{
+ return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fdf827f..8afa5f9 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -135,6 +135,11 @@
{-1},
};
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+ {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
+ {-1},
+};
+
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
@@ -169,6 +174,20 @@
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
{-1},
};
@@ -237,6 +256,12 @@
};
#endif
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+ {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
+ {-1},
+};
+
#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
@@ -365,6 +390,12 @@
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ } else if (board_is_icev2()) {
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(gpio0_18_pin_mux);
+ configure_module_pin_mux(uart3_icev2_pin_mux);
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 96ef85b..3d40b17 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -7,5 +7,3 @@
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig
-F: configs/am437x_gp_evm_defconfig
-F: configs/am437x_sk_evm_defconfig
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d208d2f..bde5ac7 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -341,7 +341,7 @@
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
- else if (board_is_gpevm() || board_is_sk())
+ else if (board_is_evm() || board_is_sk())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
@@ -553,7 +553,7 @@
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
- } else if (board_is_gpevm()) {
+ } else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
@@ -678,71 +678,71 @@
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+ ti_usb_phy_uboot_init(&usb_phy1_device);
+ dwc3_uboot_init(&usb_otg_ss1);
}
-
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
}
-
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
@@ -846,3 +846,19 @@
return rv;
}
#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+ return 0;
+ else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+ return 0;
+ else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+ return 0;
+ else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 2cf7a77..3f93d13 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -37,14 +37,24 @@
return board_ti_is("AM43_IDK");
}
+static inline int board_is_hsevm(void)
+{
+ return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+ return board_is_gpevm() || board_is_hsevm();
+}
+
static inline int board_is_evm_14_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
}
static inline int board_is_evm_12_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
}
void enable_uart0_pin_mux(void);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index e03b1bc..f26b21e 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -126,7 +126,7 @@
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mdio_pin_mux);
- if (board_is_gpevm()) {
+ if (board_is_evm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 86b8f6e..ccf97b2 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -63,28 +63,28 @@
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36ab,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x409f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36ab,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x409f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
@@ -127,28 +127,28 @@
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36b3,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x407f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36b3,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x407f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -216,41 +216,77 @@
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data am572x_idk_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
@@ -315,11 +351,18 @@
#endif /* CONFIG_SPL_BUILD */
+void vcores_init(void)
+{
+ if (board_is_am572x_idk())
+ *omap_vcores = &am572x_idk_volts;
+ else
+ *omap_vcores = &beagle_x15_volts;
+}
+
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &beagle_x15_volts;
*ctrl = &dra7xx_ctrl;
}
@@ -439,6 +482,19 @@
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
@@ -448,31 +504,23 @@
printf("port %d can't be used as device\n", index);
disable_usb_clocks(index);
return -EINVAL;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OTG_SS_CLKCTRL_MODULEMODE_HW |
- OPTFCLKEN_REFCLK960M);
}
-
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_DWC3
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
+#endif
} else {
printf("port %d can't be used as host\n", index);
disable_usb_clocks(index);
return -EINVAL;
}
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
@@ -483,31 +531,24 @@
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
@@ -686,3 +727,12 @@
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 3f638d0..46b6e82 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -3,8 +3,5 @@
S: Maintained
F: board/ti/dra7xx/
F: include/configs/dra7xx_evm.h
-F: configs/dra72_evm_defconfig
-F: configs/dra74_evm_defconfig
F: configs/dra7xx_evm_defconfig
-F: configs/dra7xx_evm_qspiboot_defconfig
-F: configs/dra7xx_evm_uart3_defconfig
+F: configs/dra7xx_hs_evm_defconfig
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9bd71d8..3fbbc9b 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -718,3 +718,24 @@
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_dra72x() && !strcmp(name, "dra72-evm"))
+ return 0;
+ else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 9e8ad93..1de7df0 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -131,7 +131,7 @@
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
@@ -273,4 +273,4 @@
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c412..8f16845 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+ /* Unlock the reset mux register */
+ clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+ /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+ clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+ RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+ /* lock the reset mux register to prevent any spurious writes. */
+ setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
int board_early_init_f(void)
{
init_plls();
k2g_mux_config();
+ k2g_reset_mux_config();
+
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 879f25a..68fbf49 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -103,11 +103,11 @@
pinmux_tristate_disable(PMUX_PINGRP_DTE);
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PV4, "LAN_RESET");
- gpio_direction_output(GPIO_PV4, 0);
+ gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(V, 4), 0);
pinmux_tristate_disable(PMUX_PINGRP_GPV);
udelay(5);
- gpio_set_value(GPIO_PV4, 1);
+ gpio_set_value(TEGRA_GPIO(V, 4), 1);
/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 44b5beb..e32362a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -47,8 +47,8 @@
void pin_mux_usb(void)
{
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PDD0, "LAN_RESET");
- gpio_direction_output(GPIO_PDD0, 0);
+ gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
udelay(5);
- gpio_set_value(GPIO_PDD0, 1);
+ gpio_set_value(TEGRA_GPIO(DD, 0), 1);
}
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 902abf5..67a0228 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -12,4 +12,19 @@
config SYS_CONFIG_NAME
default "tplink_wdr4300"
+config SYS_TEXT_BASE
+ default 0xa1000000
+
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_ICACHE_LINE_SIZE
+ default 32
+
endif
diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
index bf896fe..d1f3668 100644
--- a/board/xes/common/actl_nand.c
+++ b/board/xes/common/actl_nand.c
@@ -16,7 +16,7 @@
*/
static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 461d7dc..02ac65c 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -9,4 +9,28 @@
config SYS_CONFIG_NAME
default "microblaze-generic"
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+ int "USE_MSR_INSTR range (0:1)"
+ default 0
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+ int "USE_PCMP_INSTR range (0:1)"
+ default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+ int "USE_BARREL range (0:1)"
+ default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+ int "USE_DIV range (0:1)"
+ default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+ int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+ default 0
+
+config XILINX_MICROBLAZE0_HW_VER
+ string "Core version number"
+ default 7.10.d
+
endif
diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
index 95ef9c0..1dee2d6 100644
--- a/board/xilinx/microblaze-generic/config.mk
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -1,16 +1,20 @@
#
-# (C) Copyright 2007 Michal Simek
+# (C) Copyright 2007 - 2016 Michal Simek
#
-# Michal SIMEK <monstr@monstr.eu>
+# Michal SIMEK <monstr@monstr.eu>
#
# SPDX-License-Identifier: GPL-2.0+
#
-# CAUTION: This file is a faked configuration !!!
-# There is no real target for the microblaze-generic
-# configuration. You have to replace this file with
-# the generated file from your Xilinx design flow.
-#
+
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
-PLATFORM_CPPFLAGS += -mno-xl-soft-mul
-PLATFORM_CPPFLAGS += -mno-xl-soft-div
-PLATFORM_CPPFLAGS += -mxl-barrel-shift
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index dc5645b..ee7d087 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -14,7 +14,6 @@
#define XILINX_BOARD_NAME microblaze-generic
/* Microblaze is microblaze_0 */
-#define XILINX_USE_MSR_INSTR 1
#define XILINX_FSL_NUMBER 3
/* GPIO is LEDs_4Bit*/
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 4623cd4..f15dc5d 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,6 +9,7 @@
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
+#include <malloc.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@@ -214,6 +215,13 @@
{
u32 reg = 0;
u8 bootmode;
+ const char *mode;
+ char *new_targets;
+
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
@@ -222,37 +230,49 @@
switch (bootmode) {
case JTAG_MODE:
puts("JTAG_MODE\n");
- setenv("modeboot", "jtagboot");
+ mode = "pxe dhcp";
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
- setenv("modeboot", "qspiboot");
+ mode = "qspi0";
puts("QSPI_MODE\n");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
- setenv("modeboot", "sdboot");
+ mode = "mmc0";
break;
case SD_MODE:
puts("SD_MODE\n");
- setenv("modeboot", "sdboot");
+ mode = "mmc0";
break;
case SD_MODE1:
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
- setenv("sdbootdev", "1");
+ mode = "mmc1";
+#else
+ mode = "mmc0";
#endif
- setenv("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
- setenv("modeboot", "nandboot");
+ mode = "nand0";
break;
default:
+ mode = "";
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ new_targets = calloc(1, strlen(mode) +
+ strlen(getenv("boot_targets")) + 2);
+
+ sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
+ setenv("boot_targets", new_targets);
+
return 0;
}
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 7f552fc..2169065 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -197,11 +197,22 @@
#ifdef CONFIG_LCD
efi_gop_register();
#endif
+#ifdef CONFIG_NET
+ void *nethandle = loaded_image_info.device_handle;
+ efi_net_register(&nethandle);
- /* Call our payload! */
-#ifdef DEBUG_EFI
- printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
+ if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
+ loaded_image_info.device_handle = nethandle;
#endif
+
+ /* Call our payload! */
+ debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
+
+ if (setjmp(&loaded_image_info.exit_jmp)) {
+ efi_status_t status = loaded_image_info.exit_status;
+ return status == EFI_SUCCESS ? 0 : -EINVAL;
+ }
+
return entry(&loaded_image_info, &systab);
}
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 1bca6fa..f5e91f4 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -372,8 +372,8 @@
#endif
#if defined(CONFIG_CMD_IMLS_NAND)
-static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
- size_t len)
+static int nand_imls_legacyimage(struct mtd_info *mtd, int nand_dev,
+ loff_t off, size_t len)
{
void *imgdata;
int ret;
@@ -386,8 +386,7 @@
return -ENOMEM;
}
- ret = nand_read_skip_bad(nand, off, &len,
- imgdata);
+ ret = nand_read_skip_bad(mtd, off, &len, imgdata);
if (ret < 0 && ret != -EUCLEAN) {
free(imgdata);
return ret;
@@ -413,8 +412,8 @@
return 0;
}
-static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
- size_t len)
+static int nand_imls_fitimage(struct mtd_info *mtd, int nand_dev, loff_t off,
+ size_t len)
{
void *imgdata;
int ret;
@@ -427,8 +426,7 @@
return -ENOMEM;
}
- ret = nand_read_skip_bad(nand, off, &len,
- imgdata);
+ ret = nand_read_skip_bad(mtd, off, &len, imgdata);
if (ret < 0 && ret != -EUCLEAN) {
free(imgdata);
return ret;
@@ -449,7 +447,7 @@
static int do_imls_nand(void)
{
- nand_info_t *nand;
+ struct mtd_info *mtd;
int nand_dev = nand_curr_device;
size_t len;
loff_t off;
@@ -463,20 +461,20 @@
printf("\n");
for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
- nand = &nand_info[nand_dev];
- if (!nand->name || !nand->size)
+ mtd = nand_info[nand_dev];
+ if (!mtd->name || !mtd->size)
continue;
- for (off = 0; off < nand->size; off += nand->erasesize) {
+ for (off = 0; off < mtd->size; off += mtd->erasesize) {
const image_header_t *header;
int ret;
- if (nand_block_isbad(nand, off))
+ if (nand_block_isbad(mtd, off))
continue;
len = sizeof(buffer);
- ret = nand_read(nand, off, &len, (u8 *)buffer);
+ ret = nand_read(mtd, off, &len, (u8 *)buffer);
if (ret < 0 && ret != -EUCLEAN) {
printf("NAND read error %d at offset %08llX\n",
ret, off);
@@ -489,13 +487,13 @@
header = (const image_header_t *)buffer;
len = image_get_image_size(header);
- nand_imls_legacyimage(nand, nand_dev, off, len);
+ nand_imls_legacyimage(mtd, nand_dev, off, len);
break;
#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
len = fit_get_size(buffer);
- nand_imls_fitimage(nand, nand_dev, off, len);
+ nand_imls_fitimage(mtd, nand_dev, off, len);
break;
#endif
}
@@ -655,6 +653,7 @@
{
struct Image_header *ih;
uint64_t dst;
+ uint64_t image_size;
ih = (struct Image_header *)map_sysmem(images->ep, 0);
@@ -665,14 +664,16 @@
if (ih->image_size == 0) {
puts("Image lacks image_size field, assuming 16MiB\n");
- ih->image_size = (16 << 20);
+ image_size = 16 << 20;
+ } else {
+ image_size = le64_to_cpu(ih->image_size);
}
/*
* If we are not at the correct run-time location, set the new
* correct location and then move the image there.
*/
- dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset);
+ dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
unmap_sysmem(ih);
@@ -683,7 +684,7 @@
src = (void *)images->ep;
images->ep = dst;
- memmove((void *)dst, src, le32_to_cpu(ih->image_size));
+ memmove((void *)dst, src, image_size);
}
return 0;
diff --git a/cmd/disk.c b/cmd/disk.c
index fcc4123..92de3af 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -13,7 +13,8 @@
int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
char *const argv[])
{
- int dev, part;
+ __maybe_unused int dev;
+ int part;
ulong addr = CONFIG_SYS_LOAD_ADDR;
ulong cnt;
disk_partition_t info;
diff --git a/cmd/itest.c b/cmd/itest.c
index fb4d797..60626c7 100644
--- a/cmd/itest.c
+++ b/cmd/itest.c
@@ -65,13 +65,13 @@
}
switch (w) {
case 1:
- l = (long)(*(unsigned char *)buf);
+ l = (long)(*(u8 *)buf);
break;
case 2:
- l = (long)(*(unsigned short *)buf);
+ l = (long)(*(u16 *)buf);
break;
case 4:
- l = (long)(*(unsigned long *)buf);
+ l = (long)(*(u32 *)buf);
break;
}
unmap_physmem(buf, w);
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index 0b2eefa..f00d53a 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -167,7 +167,7 @@
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
- *size = nand_info[num].size;
+ *size = nand_info[num]->size;
return 0;
}
@@ -242,11 +242,11 @@
static inline u32 get_part_sector_size_nand(struct mtdids *id)
{
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
- nand_info_t *nand;
+ struct mtd_info *mtd;
- nand = &nand_info[id->num];
+ mtd = nand_info[id->num];
- return nand->erasesize;
+ return mtd->erasesize;
#else
BUG();
return 0;
diff --git a/cmd/mmc.c b/cmd/mmc.c
index eb4a547..b2761e9 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -11,66 +11,6 @@
#include <mmc.h>
static int curr_device = -1;
-#ifndef CONFIG_GENERIC_MMC
-int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int dev;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- if (strcmp(argv[1], "init") == 0) {
- if (argc == 2) {
- if (curr_device < 0)
- dev = 1;
- else
- dev = curr_device;
- } else if (argc == 3) {
- dev = (int)simple_strtoul(argv[2], NULL, 10);
- } else {
- return CMD_RET_USAGE;
- }
-
- if (mmc_legacy_init(dev) != 0) {
- puts("No MMC card found\n");
- return 1;
- }
-
- curr_device = dev;
- printf("mmc%d is available\n", curr_device);
- } else if (strcmp(argv[1], "device") == 0) {
- if (argc == 2) {
- if (curr_device < 0) {
- puts("No MMC device available\n");
- return 1;
- }
- } else if (argc == 3) {
- dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-#ifdef CONFIG_SYS_MMC_SET_DEV
- if (mmc_set_dev(dev) != 0)
- return 1;
-#endif
- curr_device = dev;
- } else {
- return CMD_RET_USAGE;
- }
-
- printf("mmc%d is current device\n", curr_device);
- } else {
- return CMD_RET_USAGE;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- mmc, 3, 1, do_mmc,
- "MMC sub-system",
- "init [dev] - init MMC sub system\n"
- "mmc device [dev] - show or set current device"
-);
-#else /* !CONFIG_GENERIC_MMC */
static void print_mmcinfo(struct mmc *mmc)
{
@@ -881,5 +821,3 @@
"display MMC info",
"- display info of the current MMC device"
);
-
-#endif /* !CONFIG_GENERIC_MMC */
diff --git a/cmd/nand.c b/cmd/nand.c
index a6b67e2..583a18f 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -38,7 +38,8 @@
u8 *part_num, struct part_info **part);
#endif
-static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
+static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
+ int repeat)
{
int i;
u_char *datbuf, *oobbuf, *p;
@@ -46,32 +47,32 @@
int ret = 0;
if (repeat)
- off = last + nand->writesize;
+ off = last + mtd->writesize;
last = off;
- datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+ datbuf = memalign(ARCH_DMA_MINALIGN, mtd->writesize);
if (!datbuf) {
puts("No memory for page buffer\n");
return 1;
}
- oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
+ oobbuf = memalign(ARCH_DMA_MINALIGN, mtd->oobsize);
if (!oobbuf) {
puts("No memory for page buffer\n");
ret = 1;
goto free_dat;
}
- off &= ~(nand->writesize - 1);
+ off &= ~(mtd->writesize - 1);
loff_t addr = (loff_t) off;
struct mtd_oob_ops ops;
memset(&ops, 0, sizeof(ops));
ops.datbuf = datbuf;
ops.oobbuf = oobbuf;
- ops.len = nand->writesize;
- ops.ooblen = nand->oobsize;
+ ops.len = mtd->writesize;
+ ops.ooblen = mtd->oobsize;
ops.mode = MTD_OPS_RAW;
- i = mtd_read_oob(nand, addr, &ops);
+ i = mtd_read_oob(mtd, addr, &ops);
if (i < 0) {
printf("Error (%d) reading page %08lx\n", i, off);
ret = 1;
@@ -80,7 +81,7 @@
printf("Page %08lx dump:\n", off);
if (!only_oob) {
- i = nand->writesize >> 4;
+ i = mtd->writesize >> 4;
p = datbuf;
while (i--) {
@@ -94,7 +95,7 @@
}
puts("OOB:\n");
- i = nand->oobsize >> 3;
+ i = mtd->oobsize >> 3;
p = oobbuf;
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
@@ -115,7 +116,7 @@
static int set_dev(int dev)
{
if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[dev].name) {
+ !nand_info[dev]->name) {
puts("No such device\n");
return -1;
}
@@ -123,12 +124,12 @@
if (nand_curr_device == dev)
return 0;
- printf("Device %d: %s", dev, nand_info[dev].name);
+ printf("Device %d: %s", dev, nand_info[dev]->name);
puts("... is now current device\n");
nand_curr_device = dev;
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
- board_nand_select_device(nand_info[dev].priv, dev);
+ board_nand_select_device(nand_info[dev]->priv, dev);
#endif
return 0;
@@ -152,32 +153,32 @@
((status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
}
-static void do_nand_status(nand_info_t *nand)
+static void do_nand_status(struct mtd_info *mtd)
{
ulong block_start = 0;
ulong off;
int last_status = -1;
- struct nand_chip *nand_chip = nand->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
/* check the WP bit */
- nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1);
+ nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
printf("device is %swrite protected\n",
- (nand_chip->read_byte(nand) & 0x80 ?
- "NOT " : ""));
+ (nand_chip->read_byte(mtd) & 0x80 ?
+ "NOT " : ""));
- for (off = 0; off < nand->size; off += nand->erasesize) {
- int s = nand_get_lock_status(nand, off);
+ for (off = 0; off < mtd->size; off += mtd->erasesize) {
+ int s = nand_get_lock_status(mtd, off);
/* print message only if status has changed */
if (s != last_status && off != 0) {
- print_status(block_start, off, nand->erasesize,
+ print_status(block_start, off, mtd->erasesize,
last_status);
block_start = off;
}
last_status = s;
}
/* Print the last block info */
- print_status(block_start, off, nand->erasesize, last_status);
+ print_status(block_start, off, mtd->erasesize, last_status);
}
#endif
@@ -188,10 +189,10 @@
{
int ret;
uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
- nand_info_t *nand = &nand_info[0];
+ struct mtd_info *mtd = nand_info[0];
char *cmd = argv[1];
- if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+ if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
puts("no devices available\n");
return 1;
}
@@ -199,7 +200,7 @@
set_dev(0);
if (!strcmp(cmd, "get")) {
- ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+ ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
if (ret)
return 1;
@@ -215,7 +216,7 @@
/* We don't care about size, or maxsize. */
if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
- MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+ MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
puts("Offset or partition name expected\n");
return 1;
}
@@ -229,15 +230,15 @@
return 1;
}
- if (nand->oobavail < ENV_OFFSET_SIZE) {
+ if (mtd->oobavail < ENV_OFFSET_SIZE) {
printf("Insufficient available OOB bytes:\n"
"%d OOB bytes available but %d required for "
"env.oob support\n",
- nand->oobavail, ENV_OFFSET_SIZE);
+ mtd->oobavail, ENV_OFFSET_SIZE);
return 1;
}
- if ((addr & (nand->erasesize - 1)) != 0) {
+ if ((addr & (mtd->erasesize - 1)) != 0) {
printf("Environment offset must be block-aligned\n");
return 1;
}
@@ -249,15 +250,15 @@
ops.oobbuf = (void *) oob_buf;
oob_buf[0] = ENV_OOB_MARKER;
- oob_buf[1] = addr / nand->erasesize;
+ oob_buf[1] = addr / mtd->erasesize;
- ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+ ret = mtd->write_oob(mtd, ENV_OFFSET_SIZE, &ops);
if (ret) {
printf("Error writing OOB block 0\n");
return ret;
}
- ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+ ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
if (ret) {
printf("Error reading env offset in OOB\n");
return ret;
@@ -283,29 +284,29 @@
static void nand_print_and_set_info(int idx)
{
- nand_info_t *nand = &nand_info[idx];
- struct nand_chip *chip = nand->priv;
+ struct mtd_info *mtd = nand_info[idx];
+ struct nand_chip *chip = mtd_to_nand(mtd);
printf("Device %d: ", idx);
if (chip->numchips > 1)
printf("%dx ", chip->numchips);
printf("%s, sector size %u KiB\n",
- nand->name, nand->erasesize >> 10);
- printf(" Page size %8d b\n", nand->writesize);
- printf(" OOB size %8d b\n", nand->oobsize);
- printf(" Erase size %8d b\n", nand->erasesize);
+ mtd->name, mtd->erasesize >> 10);
+ printf(" Page size %8d b\n", mtd->writesize);
+ printf(" OOB size %8d b\n", mtd->oobsize);
+ printf(" Erase size %8d b\n", mtd->erasesize);
printf(" subpagesize %8d b\n", chip->subpagesize);
printf(" options 0x%8x\n", chip->options);
printf(" bbt options 0x%8x\n", chip->bbt_options);
/* Set geometry info */
- setenv_hex("nand_writesize", nand->writesize);
- setenv_hex("nand_oobsize", nand->oobsize);
- setenv_hex("nand_erasesize", nand->erasesize);
+ setenv_hex("nand_writesize", mtd->writesize);
+ setenv_hex("nand_oobsize", mtd->oobsize);
+ setenv_hex("nand_erasesize", mtd->erasesize);
}
-static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
- int read)
+static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
+ ulong count, int read)
{
int ret = 0;
@@ -313,18 +314,18 @@
/* Raw access */
mtd_oob_ops_t ops = {
.datbuf = (u8 *)addr,
- .oobbuf = ((u8 *)addr) + nand->writesize,
- .len = nand->writesize,
- .ooblen = nand->oobsize,
+ .oobbuf = ((u8 *)addr) + mtd->writesize,
+ .len = mtd->writesize,
+ .ooblen = mtd->oobsize,
.mode = MTD_OPS_RAW
};
if (read) {
- ret = mtd_read_oob(nand, off, &ops);
+ ret = mtd_read_oob(mtd, off, &ops);
} else {
- ret = mtd_write_oob(nand, off, &ops);
+ ret = mtd_write_oob(mtd, off, &ops);
if (!ret)
- ret = nand_verify_page_oob(nand, &ops, off);
+ ret = nand_verify_page_oob(mtd, &ops, off);
}
if (ret) {
@@ -333,8 +334,8 @@
break;
}
- addr += nand->writesize + nand->oobsize;
- off += nand->writesize;
+ addr += mtd->writesize + mtd->oobsize;
+ off += mtd->writesize;
}
return ret;
@@ -348,18 +349,18 @@
/* We grab the nand info object here fresh because this is usually
* called after arg_off_size() which can change the value of dev.
*/
- nand_info_t *nand = &nand_info[dev];
+ struct mtd_info *mtd = nand_info[dev];
loff_t maxoffset = offset + *size;
int badblocks = 0;
/* count badblocks in NAND from offset to offset + size */
- for (; offset < maxoffset; offset += nand->erasesize) {
- if (nand_block_isbad(nand, offset))
+ for (; offset < maxoffset; offset += mtd->erasesize) {
+ if (nand_block_isbad(mtd, offset))
badblocks++;
}
/* adjust size if any bad blocks found */
if (badblocks) {
- *size -= badblocks * nand->erasesize;
+ *size -= badblocks * mtd->erasesize;
printf("size adjusted to 0x%llx (%d bad blocks)\n",
(unsigned long long)*size, badblocks);
}
@@ -371,7 +372,7 @@
ulong addr;
loff_t off, size, maxsize;
char *cmd, *s;
- nand_info_t *nand;
+ struct mtd_info *mtd;
#ifdef CONFIG_SYS_NAND_QUIET
int quiet = CONFIG_SYS_NAND_QUIET;
#else
@@ -398,7 +399,7 @@
putc('\n');
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (nand_info[i].name)
+ if (nand_info[i]->name)
nand_print_and_set_info(i);
}
return 0;
@@ -433,16 +434,16 @@
* for another device is to be used.
*/
if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[dev].name) {
+ !nand_info[dev]->name) {
puts("\nno devices available\n");
return 1;
}
- nand = &nand_info[dev];
+ mtd = nand_info[dev];
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", dev);
- for (off = 0; off < nand->size; off += nand->erasesize)
- if (nand_block_isbad(nand, off))
+ for (off = 0; off < mtd->size; off += mtd->erasesize)
+ if (nand_block_isbad(mtd, off))
printf(" %08llx\n", (unsigned long long)off);
return 0;
}
@@ -496,13 +497,13 @@
/* skip first two or three arguments, look for offset and size */
if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev].size) != 0)
+ nand_info[dev]->size) != 0)
return 1;
if (set_dev(dev))
return 1;
- nand = &nand_info[dev];
+ mtd = nand_info[dev];
memset(&opts, 0, sizeof(opts));
opts.offset = off;
@@ -524,7 +525,7 @@
}
}
}
- ret = nand_erase_opts(nand, &opts);
+ ret = nand_erase_opts(mtd, &opts);
printf("%s\n", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
@@ -535,7 +536,7 @@
goto usage;
off = (int)simple_strtoul(argv[2], NULL, 16);
- ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
+ ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat);
return ret == 0 ? 1 : 0;
}
@@ -561,30 +562,30 @@
if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev].size))
+ nand_info[dev]->size))
return 1;
if (set_dev(dev))
return 1;
- nand = &nand_info[dev];
+ mtd = nand_info[dev];
if (argc > 4 && !str2long(argv[4], &pagecount)) {
printf("'%s' is not a number\n", argv[4]);
return 1;
}
- if (pagecount * nand->writesize > size) {
+ if (pagecount * mtd->writesize > size) {
puts("Size exceeds partition or device limit\n");
return -1;
}
- rwsize = pagecount * (nand->writesize + nand->oobsize);
+ rwsize = pagecount * (mtd->writesize + mtd->oobsize);
} else {
if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
&size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev].size) != 0)
+ nand_info[dev]->size) != 0)
return 1;
if (set_dev(dev))
@@ -596,16 +597,16 @@
rwsize = size;
}
- nand = &nand_info[dev];
+ mtd = nand_info[dev];
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
- ret = nand_read_skip_bad(nand, off, &rwsize,
+ ret = nand_read_skip_bad(mtd, off, &rwsize,
NULL, maxsize,
(u_char *)addr);
else
- ret = nand_write_skip_bad(nand, off, &rwsize,
+ ret = nand_write_skip_bad(mtd, off, &rwsize,
NULL, maxsize,
(u_char *)addr,
WITH_WR_VERIFY);
@@ -615,7 +616,7 @@
printf("Unknown nand command suffix '%s'\n", s);
return 1;
}
- ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
+ ret = nand_write_skip_bad(mtd, off, &rwsize, NULL,
maxsize, (u_char *)addr,
WITH_DROP_FFS | WITH_WR_VERIFY);
#endif
@@ -628,11 +629,11 @@
};
if (read)
- ret = mtd_read_oob(nand, off, &ops);
+ ret = mtd_read_oob(mtd, off, &ops);
else
- ret = mtd_write_oob(nand, off, &ops);
+ ret = mtd_write_oob(mtd, off, &ops);
} else if (raw) {
- ret = raw_access(nand, addr, off, pagecount, read);
+ ret = raw_access(mtd, addr, off, pagecount, read);
} else {
printf("Unknown nand command suffix '%s'.\n", s);
return 1;
@@ -655,8 +656,8 @@
}
printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
- dev, off, nand->erasesize);
- ret = nand_torture(nand, off);
+ dev, off, mtd->erasesize);
+ ret = nand_torture(mtd, off);
printf(" %s\n", ret ? "Failed" : "Passed");
return ret == 0 ? 0 : 1;
@@ -673,7 +674,7 @@
while (argc > 0) {
addr = simple_strtoul(*argv, NULL, 16);
- if (mtd_block_markbad(nand, addr)) {
+ if (mtd_block_markbad(mtd, addr)) {
printf("block 0x%08lx NOT marked "
"as bad! ERROR %d\n",
addr, ret);
@@ -705,9 +706,9 @@
status = 1;
}
if (status) {
- do_nand_status(nand);
+ do_nand_status(mtd);
} else {
- if (!nand_lock(nand, tight)) {
+ if (!nand_lock(mtd, tight)) {
puts("NAND flash successfully locked\n");
} else {
puts("Error locking NAND flash\n");
@@ -727,13 +728,13 @@
if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev].size) < 0)
+ nand_info[dev]->size) < 0)
return 1;
if (set_dev(dev))
return 1;
- if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
+ if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
@@ -801,7 +802,7 @@
"NAND sub-system", nand_help_text
);
-static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
+static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd,
ulong offset, ulong addr, char *cmd)
{
int r;
@@ -822,11 +823,11 @@
return 1;
}
- printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
+ printf("\nLoading from %s, offset 0x%lx\n", mtd->name, offset);
- cnt = nand->writesize;
- r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
- (u_char *)addr);
+ cnt = mtd->writesize;
+ r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+ (u_char *)addr);
if (r) {
puts("** Read error\n");
bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ);
@@ -860,8 +861,8 @@
}
bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
- r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
- (u_char *)addr);
+ r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+ (u_char *)addr);
if (r) {
puts("** Read error\n");
bootstage_error(BOOTSTAGE_ID_NAND_READ);
@@ -914,7 +915,7 @@
addr = simple_strtoul(argv[1], NULL, 16);
else
addr = CONFIG_SYS_LOAD_ADDR;
- return nand_load_image(cmdtp, &nand_info[dev->id->num],
+ return nand_load_image(cmdtp, nand_info[dev->id->num],
part->offset, addr, argv[0]);
}
}
@@ -957,14 +958,14 @@
idx = simple_strtoul(boot_device, NULL, 16);
- if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
+ if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) {
printf("\n** Device %d not available\n", idx);
bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
return 1;
}
bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
- return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
+ return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
}
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
diff --git a/common/Makefile b/common/Makefile
index 0562d5c..1557a04 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -26,8 +26,8 @@
endif
# boards
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-y += board_f.o
+obj-y += board_r.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
diff --git a/common/board_f.c b/common/board_f.c
index 109025a..d405b5b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -274,7 +274,7 @@
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_NDS32)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
-#else
+#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
#endif
diff --git a/common/bootm_os.c b/common/bootm_os.c
index cb83f4a..9ec84bd 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -484,9 +484,8 @@
state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
return 0;
bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-#ifdef DEBUG
- puts("\n## Control returned to monitor - resetting...\n");
-#endif
+ debug("\n## Control returned to monitor - resetting...\n");
+
return BOOTM_ERR_RESET;
}
diff --git a/common/env_common.c b/common/env_common.c
index af59c72..13db7dc 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -123,6 +123,7 @@
error("Environment import failed: errno = %d\n", errno);
gd->flags |= GD_FLG_ENV_READY;
+ gd->flags |= GD_FLG_ENV_DEFAULT;
}
diff --git a/common/env_mmc.c b/common/env_mmc.c
index c7fef18..16f6a17 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -128,12 +128,12 @@
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ struct blk_desc *desc = mmc_get_blk_desc(mmc);
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
- n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
- blk_cnt, (u_char *)buffer);
+ n = blk_dwrite(desc, blk_start, blk_cnt, (u_char *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
@@ -197,12 +197,12 @@
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ struct blk_desc *desc = mmc_get_blk_desc(mmc);
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
- (uchar *)buffer);
+ n = blk_dread(desc, blk_start, blk_cnt, (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
diff --git a/common/env_nand.c b/common/env_nand.c
index b32eeac..fc99a5e 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -132,15 +132,15 @@
size_t blocksize, len;
u_char *char_ptr;
- blocksize = nand_info[0].erasesize;
+ blocksize = nand_info[0]->erasesize;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(&nand_info[0], offset)) {
+ if (nand_block_isbad(nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_saved];
- if (nand_write(&nand_info[0], offset, &len, char_ptr))
+ if (nand_write(nand_info[0], offset, &len, char_ptr))
return 1;
offset += blocksize;
@@ -164,7 +164,7 @@
int ret = 0;
printf("Erasing %s...\n", location->name);
- if (nand_erase_opts(&nand_info[0], &location->erase_opts))
+ if (nand_erase_opts(nand_info[0], &location->erase_opts))
return 1;
printf("Writing to %s... ", location->name);
@@ -247,20 +247,20 @@
size_t blocksize, len;
u_char *char_ptr;
- blocksize = nand_info[0].erasesize;
+ blocksize = nand_info[0]->erasesize;
if (!blocksize)
return 1;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(&nand_info[0], offset)) {
+ if (nand_block_isbad(nand_info[0], offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
- if (nand_read_skip_bad(&nand_info[0], offset,
+ if (nand_read_skip_bad(nand_info[0], offset,
&len, NULL,
- nand_info[0].size, char_ptr))
+ nand_info[0]->size, char_ptr))
return 1;
offset += blocksize;
@@ -276,7 +276,7 @@
#endif /* #if defined(CONFIG_SPL_BUILD) */
#ifdef CONFIG_ENV_OFFSET_OOB
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result)
{
struct mtd_oob_ops ops;
uint32_t oob_buf[ENV_OFFSET_SIZE / sizeof(uint32_t)];
@@ -288,14 +288,14 @@
ops.ooblen = ENV_OFFSET_SIZE;
ops.oobbuf = (void *)oob_buf;
- ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
+ ret = mtd->read_oob(mtd, ENV_OFFSET_SIZE, &ops);
if (ret) {
printf("error reading OOB block 0\n");
return ret;
}
if (oob_buf[0] == ENV_OOB_MARKER) {
- *result = oob_buf[1] * nand->erasesize;
+ *result = oob_buf[1] * mtd->erasesize;
} else if (oob_buf[0] == ENV_OOB_MARKER_OLD) {
*result = oob_buf[1];
} else {
@@ -387,7 +387,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
- ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+ ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset);
/*
* If unable to read environment offset from NAND OOB then fall through
* to the normal environment reading code below
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 9ca8602..e55ea38 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -19,7 +19,7 @@
static char *response_str;
struct fb_nand_sparse {
- nand_info_t *nand;
+ struct mtd_info *nand;
struct part_info *part;
};
@@ -34,7 +34,7 @@
}
static int fb_nand_lookup(const char *partname, char *response,
- nand_info_t **nand,
+ struct mtd_info **nand,
struct part_info **part)
{
struct mtd_device *dev;
@@ -62,12 +62,12 @@
return -EINVAL;
}
- *nand = &nand_info[dev->id->num];
+ *mtd = nand_info[dev->id->num];
return 0;
}
-static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
+static int _fb_nand_erase(struct mtd_info *mtd, struct part_info *part)
{
nand_erase_options_t opts;
int ret;
@@ -80,7 +80,7 @@
printf("Erasing blocks 0x%llx to 0x%llx\n",
part->offset, part->offset + part->size);
- ret = nand_erase_opts(nand, &opts);
+ ret = nand_erase_opts(mtd, &opts);
if (ret)
return ret;
@@ -90,7 +90,7 @@
return 0;
}
-static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
+static int _fb_nand_write(struct mtd_info *mtd, struct part_info *part,
void *buffer, unsigned int offset,
unsigned int length, size_t *written)
{
@@ -100,7 +100,7 @@
flags |= WITH_DROP_FFS;
#endif
- return nand_write_skip_bad(nand, offset, &length, written,
+ return nand_write_skip_bad(mtd, offset, &length, written,
part->size - (offset - part->offset),
buffer, flags);
}
@@ -131,13 +131,13 @@
char *response)
{
struct part_info *part;
- nand_info_t *nand = NULL;
+ struct mtd_info *mtd = NULL;
int ret;
/* initialize the response buffer */
response_str = response;
- ret = fb_nand_lookup(partname, response, &nand, &part);
+ ret = fb_nand_lookup(partname, response, &mtd, &part);
if (ret) {
error("invalid NAND device");
fastboot_fail(response_str, "invalid NAND device");
@@ -152,10 +152,10 @@
struct fb_nand_sparse sparse_priv;
sparse_storage_t sparse;
- sparse_priv.nand = nand;
+ sparse_priv.nand = mtd;
sparse_priv.part = part;
- sparse.block_sz = nand->writesize;
+ sparse.block_sz = mtd->writesize;
sparse.start = part->offset / sparse.block_sz;
sparse.size = part->size / sparse.block_sz;
sparse.name = part->name;
@@ -167,7 +167,7 @@
printf("Flashing raw image at offset 0x%llx\n",
part->offset);
- ret = _fb_nand_write(nand, part, download_buffer, part->offset,
+ ret = _fb_nand_write(mtd, part, download_buffer, part->offset,
download_bytes, NULL);
printf("........ wrote %u bytes to '%s'\n",
@@ -185,13 +185,13 @@
void fb_nand_erase(const char *partname, char *response)
{
struct part_info *part;
- nand_info_t *nand = NULL;
+ struct mtd_info *mtd = NULL;
int ret;
/* initialize the response buffer */
response_str = response;
- ret = fb_nand_lookup(partname, response, &nand, &part);
+ ret = fb_nand_lookup(partname, response, &mtd, &part);
if (ret) {
error("invalid NAND device");
fastboot_fail(response_str, "invalid NAND device");
@@ -202,9 +202,9 @@
if (ret)
return;
- ret = _fb_nand_erase(nand, part);
+ ret = _fb_nand_erase(mtd, part);
if (ret) {
- error("failed erasing from device %s", nand->name);
+ error("failed erasing from device %s", mtd->name);
fastboot_fail(response_str, "failed erasing from device");
return;
}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42e5d8a..5d8eb12 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -964,10 +964,40 @@
static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
#endif
-/* Callbacks for bus specific translators */
+/**
+ * struct of_bus - Callbacks for bus specific translators
+ * @name: A string used to identify this bus in debug output.
+ * @addresses: The name of the DT property from which addresses are
+ * to be read, typically "reg".
+ * @match: Return non-zero if the node whose parent is at
+ * parentoffset in the FDT blob corresponds to a bus
+ * of this type, otherwise return zero. If NULL a match
+ * is assumed.
+ * @count_cells:Count how many cells (be32 values) a node whose parent
+ * is at parentoffset in the FDT blob will require to
+ * represent its address (written to *addrc) & size
+ * (written to *sizec).
+ * @map: Map the address addr from the address space of this
+ * bus to that of its parent, making use of the ranges
+ * read from DT to an array at range. na and ns are the
+ * number of cells (be32 values) used to hold and address
+ * or size, respectively, for this bus. pna is the number
+ * of cells used to hold an address for the parent bus.
+ * Returns the address in the address space of the parent
+ * bus.
+ * @translate: Update the value of the address cells at addr within an
+ * FDT by adding offset to it. na specifies the number of
+ * cells used to hold the address being translated. Returns
+ * zero on success, non-zero on error.
+ *
+ * Each bus type will include a struct of_bus in the of_busses array,
+ * providing implementations of some or all of the functions used to
+ * match the bus & handle address translation for its children.
+ */
struct of_bus {
const char *name;
const char *addresses;
+ int (*match)(void *blob, int parentoffset);
void (*count_cells)(void *blob, int parentoffset,
int *addrc, int *sizec);
u64 (*map)(fdt32_t *addr, const fdt32_t *range,
@@ -1022,8 +1052,70 @@
return 0;
}
+#ifdef CONFIG_OF_ISA_BUS
+
+/* ISA bus translator */
+static int of_bus_isa_match(void *blob, int parentoffset)
+{
+ const char *name;
+
+ name = fdt_get_name(blob, parentoffset, NULL);
+ if (!name)
+ return 0;
+
+ return !strcmp(name, "isa");
+}
+
+static void of_bus_isa_count_cells(void *blob, int parentoffset,
+ int *addrc, int *sizec)
+{
+ if (addrc)
+ *addrc = 2;
+ if (sizec)
+ *sizec = 1;
+}
+
+static u64 of_bus_isa_map(fdt32_t *addr, const fdt32_t *range,
+ int na, int ns, int pna)
+{
+ u64 cp, s, da;
+
+ /* Check address type match */
+ if ((addr[0] ^ range[0]) & cpu_to_be32(1))
+ return OF_BAD_ADDR;
+
+ cp = of_read_number(range + 1, na - 1);
+ s = of_read_number(range + na + pna, ns);
+ da = of_read_number(addr + 1, na - 1);
+
+ debug("OF: ISA map, cp=%" PRIu64 ", s=%" PRIu64
+ ", da=%" PRIu64 "\n", cp, s, da);
+
+ if (da < cp || da >= (cp + s))
+ return OF_BAD_ADDR;
+ return da - cp;
+}
+
+static int of_bus_isa_translate(fdt32_t *addr, u64 offset, int na)
+{
+ return of_bus_default_translate(addr + 1, offset, na - 1);
+}
+
+#endif /* CONFIG_OF_ISA_BUS */
+
/* Array of bus specific translators */
static struct of_bus of_busses[] = {
+#ifdef CONFIG_OF_ISA_BUS
+ /* ISA */
+ {
+ .name = "isa",
+ .addresses = "reg",
+ .match = of_bus_isa_match,
+ .count_cells = of_bus_isa_count_cells,
+ .map = of_bus_isa_map,
+ .translate = of_bus_isa_translate,
+ },
+#endif /* CONFIG_OF_ISA_BUS */
/* Default */
{
.name = "default",
@@ -1034,6 +1126,28 @@
},
};
+static struct of_bus *of_match_bus(void *blob, int parentoffset)
+{
+ struct of_bus *bus;
+
+ if (ARRAY_SIZE(of_busses) == 1)
+ return of_busses;
+
+ for (bus = of_busses; bus; bus++) {
+ if (!bus->match || bus->match(blob, parentoffset))
+ return bus;
+ }
+
+ /*
+ * We should always have matched the default bus at least, since
+ * it has a NULL match field. If we didn't then it somehow isn't
+ * in the of_busses array or something equally catastrophic has
+ * gone wrong.
+ */
+ assert(0);
+ return NULL;
+}
+
static int of_translate_one(void * blob, int parent, struct of_bus *bus,
struct of_bus *pbus, fdt32_t *addr,
int na, int ns, int pna, const char *rprop)
@@ -1113,7 +1227,7 @@
parent = fdt_parent_offset(blob, node_offset);
if (parent < 0)
goto bail;
- bus = &of_busses[0];
+ bus = of_match_bus(blob, parent);
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
@@ -1142,7 +1256,7 @@
}
/* Get new parent bus and counts */
- pbus = &of_busses[0];
+ pbus = of_match_bus(blob, parent);
pbus->count_cells(blob, parent, &pna, &pns);
if (!OF_CHECK_COUNTS(pna, pns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
diff --git a/common/main.c b/common/main.c
index 42bbb50..2116a9e 100644
--- a/common/main.c
+++ b/common/main.c
@@ -47,12 +47,6 @@
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
-#ifndef CONFIG_SYS_GENERIC_BOARD
- puts("Warning: Your board does not use generic board. Please read\n");
- puts("doc/README.generic-board and take action. Boards not\n");
- puts("upgraded by the late 2014 may break or be removed.\n");
-#endif
-
#ifdef CONFIG_VERSION_VARIABLE
setenv("ver", version_string); /* set version variable */
#endif /* CONFIG_VERSION_VARIABLE */
diff --git a/common/scsi.c b/common/scsi.c
index 8ac28dd..dbbf404 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -584,7 +584,7 @@
};
#else
U_BOOT_LEGACY_BLK(scsi) = {
- .if_typename = "sata",
+ .if_typename = "scsi",
.if_type = IF_TYPE_SCSI,
.max_devs = CONFIG_SYS_SCSI_MAX_DEVICE,
.desc = scsi_dev_desc,
diff --git a/common/spl/spl.c b/common/spl/spl.c
index bdde716..c8dfc14 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -192,6 +192,9 @@
debug("spl_init()\n");
#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+ gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
gd->malloc_ptr = 0;
#endif
@@ -486,9 +489,6 @@
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
- if (!(gd->flags & GD_FLG_SPL_INIT))
- panic_str("spl_init must be called before heap reloc");
-
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 5b0d969..db67618 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -15,6 +15,7 @@
#include <fat.h>
#include <errno.h>
#include <image.h>
+#include <libfdt.h>
static int fat_registered;
@@ -39,6 +40,20 @@
return err;
}
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ loff_t actread;
+ int ret;
+ char *filename = (char *)load->filename;
+
+ ret = fat_read_file(filename, buf, file_offset, size, &actread);
+ if (ret)
+ return ret;
+
+ return actread;
+}
+
int spl_load_image_fat(struct blk_desc *block_dev,
int partition,
const char *filename)
@@ -57,11 +72,24 @@
if (err <= 0)
goto end;
- err = spl_parse_image_header(header);
- if (err)
- goto end;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+ debug("Found FIT\n");
+ load.read = spl_fit_read;
+ load.bl_len = 1;
+ load.filename = (void *)filename;
+ load.priv = NULL;
+
+ return spl_load_simple_fit(&load, 0, header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ goto end;
+
+ err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+ }
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 26842ba..9874708 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -67,9 +67,7 @@
*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("FIT: Selected '%s'\n", name);
-#endif
+ debug("FIT: Selected '%s'\n", name);
return len;
}
@@ -79,7 +77,7 @@
for (node = fdt_first_subnode(fdt, conf);
node >= 0;
node = fdt_next_subnode(fdt, node)) {
- name = fdt_getprop(fdt, node, "name", &len);
+ name = fdt_getprop(fdt, node, "description", &len);
printf(" %s\n", name);
}
#endif
@@ -87,6 +85,42 @@
return -ENOENT;
}
+static int get_aligned_image_offset(struct spl_load_info *info, int offset)
+{
+ /*
+ * If it is a FS read, get the first address before offset which is
+ * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
+ * block number to which offset belongs.
+ */
+ if (info->filename)
+ return offset & ~(ARCH_DMA_MINALIGN - 1);
+
+ return offset / info->bl_len;
+}
+
+static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
+{
+ /*
+ * If it is a FS read, get the difference between the offset and
+ * the first address before offset which is aligned to
+ * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
+ * block.
+ */
+ if (info->filename)
+ return offset & (ARCH_DMA_MINALIGN - 1);
+
+ return offset % info->bl_len;
+}
+
+static int get_aligned_image_size(struct spl_load_info *info, int data_size,
+ int offset)
+{
+ if (info->filename)
+ return data_size + get_aligned_image_overhead(info, offset);
+
+ return (data_size + info->bl_len - 1) / info->bl_len;
+}
+
int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
{
int sectors;
@@ -96,7 +130,7 @@
void *load_ptr;
int fdt_offset, fdt_len;
int data_offset, data_size;
- int base_offset;
+ int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int src_sector;
void *dst;
@@ -122,8 +156,9 @@
* In fact the FIT has its own load address, but we assume it cannot
* be before CONFIG_SYS_TEXT_BASE.
*/
- fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
- sectors = (size + info->bl_len - 1) / info->bl_len;
+ fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
+ align_len) & ~align_len);
+ sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
sector, sectors, fit, count);
@@ -156,19 +191,23 @@
* byte will be at 'load'. This may mean we need to load it starting
* before then, since we can only read whole blocks.
*/
- sectors = (data_size + info->bl_len - 1) / info->bl_len;
data_offset += base_offset;
+ sectors = get_aligned_image_size(info, data_size, data_offset);
load_ptr = (void *)load;
debug("U-Boot size %x, data %p\n", data_size, load_ptr);
- dst = load_ptr - (data_offset % info->bl_len);
+ dst = load_ptr;
/* Read the image */
- src_sector = sector + data_offset / info->bl_len;
- debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
- data_offset, dst, src_sector, sectors);
+ src_sector = sector + get_aligned_image_offset(info, data_offset);
+ debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
+ dst, src_sector, sectors);
count = info->read(info, src_sector, sectors, dst);
if (count != sectors)
return -EIO;
+ debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
+ data_size);
+ memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
+ data_size);
/* Figure out which device tree the board wants to use */
fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
@@ -178,13 +217,15 @@
/*
* Read the device tree and place it after the image. There may be
* some extra data before it since we can only read entire blocks.
+ * And also align the destination address to ARCH_DMA_MINALIGN.
*/
- dst = load_ptr + data_size;
+ dst = (void *)((load + data_size + align_len) & ~align_len);
fdt_offset += base_offset;
- count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
- dst);
- debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
- sectors, spl_image.load_addr, dst, fdt_offset);
+ sectors = get_aligned_image_size(info, fdt_len, fdt_offset);
+ src_sector = sector + get_aligned_image_offset(info, fdt_offset);
+ count = info->read(info, src_sector, sectors, dst);
+ debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n",
+ dst, src_sector, sectors);
if (count != sectors)
return -EIO;
@@ -193,7 +234,10 @@
* After this we will have the U-Boot image and its device tree ready
* for us to start.
*/
- memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len);
+ debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
+ fdt_len);
+ memcpy(load_ptr + data_size,
+ dst + get_aligned_image_overhead(info, fdt_offset), fdt_len);
return 0;
}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 5676acd..ef8583a 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -34,9 +34,8 @@
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(&mmc->block_dev, sector,
- image_size_sectors,
- (void *)(ulong)spl_image.load_addr);
+ count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
+ (void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
if (count != image_size_sectors)
@@ -50,7 +49,7 @@
{
struct mmc *mmc = load->dev;
- return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
+ return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
}
static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
@@ -63,7 +62,7 @@
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
+ count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
debug("hdr read sector %lx, count=%lu\n", sector, count);
if (count == 0) {
ret = -EIO;
@@ -77,6 +76,7 @@
debug("Found FIT\n");
load.dev = mmc;
load.priv = NULL;
+ load.filename = NULL;
load.bl_len = mmc->read_bl_len;
load.read = h_spl_load_read;
ret = spl_load_simple_fit(&load, sector, header);
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index bbd9546..7cf0d1b 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -9,6 +9,8 @@
#include <spl.h>
#include <asm/io.h>
#include <nand.h>
+#include <libfdt_env.h>
+#include <fdt.h>
#if defined(CONFIG_SPL_NAND_RAW_ONLY)
int spl_nand_load_image(void)
@@ -24,6 +26,19 @@
return 0;
}
#else
+
+static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
+ ulong size, void *dst)
+{
+ int ret;
+
+ ret = nand_spl_load_image(offs, size, dst);
+ if (!ret)
+ return size;
+ else
+ return 0;
+}
+
static int spl_nand_load_element(int offset, struct image_header *header)
{
int err;
@@ -32,12 +47,24 @@
if (err)
return err;
- err = spl_parse_image_header(header);
- if (err)
- return err;
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
- return nand_spl_load_image(offset, spl_image.size,
- (void *)(unsigned long)spl_image.load_addr);
+ debug("Found FIT\n");
+ load.dev = NULL;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_nand_fit_read;
+ return spl_load_simple_fit(&load, offset, header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+ return nand_spl_load_image(offset, spl_image.size,
+ (void *)(ulong)spl_image.load_addr);
+ }
}
int spl_nand_load_image(void)
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4f26ea5..5402301 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -14,15 +14,60 @@
#include <xyzModem.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
+#include <libfdt.h>
#define BUF_SIZE 1024
+/*
+ * Information required to load image using ymodem.
+ *
+ * @image_read: Now of bytes read from the image.
+ * @buf: pointer to the previous read block.
+ */
+struct ymodem_fit_info {
+ int image_read;
+ char *buf;
+};
+
static int getcymodem(void) {
if (tstc())
return (getc());
return -1;
}
+static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
+ ulong size, void *addr)
+{
+ int res, err;
+ struct ymodem_fit_info *info = load->priv;
+ char *buf = info->buf;
+
+ while (info->image_read < offset) {
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ return res;
+ info->image_read += res;
+ }
+
+ if (info->image_read > offset) {
+ res = info->image_read - offset;
+ memcpy(addr, &buf[BUF_SIZE - res], res);
+ addr = addr + res;
+ }
+
+ while (info->image_read < offset + size) {
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ return res;
+
+ memcpy(addr, buf, res);
+ info->image_read += res;
+ addr += res;
+ }
+
+ return size;
+}
+
int spl_ymodem_load_image(void)
{
int size = 0;
@@ -31,30 +76,55 @@
int ret;
connection_info_t info;
char buf[BUF_SIZE];
- ulong store_addr = ~0;
ulong addr = 0;
info.mode = xyzModem_ymodem;
ret = xyzModem_stream_open(&info, &err);
+ if (ret) {
+ printf("spl: ymodem err - %s\n", xyzModem_error(err));
+ return ret;
+ }
+
+ res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+ if (res <= 0)
+ goto end_stream;
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+ struct spl_load_info load;
+ struct ymodem_fit_info info;
+
+ debug("Found FIT\n");
+ load.dev = NULL;
+ load.priv = (void *)&info;
+ load.filename = NULL;
+ load.bl_len = 1;
+ info.buf = buf;
+ info.image_read = BUF_SIZE;
+ load.read = ymodem_read_fit;
+ ret = spl_load_simple_fit(&load, 0, (void *)buf);
+ size = info.image_read;
- if (!ret) {
- while ((res =
- xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
- if (addr == 0) {
- ret = spl_parse_image_header((struct image_header *)buf);
- if (ret)
- return ret;
- }
- store_addr = addr + spl_image.load_addr;
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0)
+ size += res;
+ } else {
+ spl_parse_image_header((struct image_header *)buf);
+ ret = spl_parse_image_header((struct image_header *)buf);
+ if (ret)
+ return ret;
+ addr = spl_image.load_addr;
+ memcpy((void *)addr, buf, res);
+ size += res;
+ addr += res;
+
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ memcpy((void *)addr, buf, res);
size += res;
addr += res;
- memcpy((char *)(store_addr), buf, res);
}
- } else {
- printf("spl: ymodem err - %s\n", xyzModem_error(err));
- return ret;
}
+end_stream:
xyzModem_stream_close(&err);
xyzModem_stream_terminate(false, &getcymodem);
diff --git a/common/splash_source.c b/common/splash_source.c
index a09dd4b..f86a78a 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -45,9 +45,9 @@
#ifdef CONFIG_CMD_NAND
static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
{
- return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
+ return nand_read_skip_bad(nand_info[nand_curr_device], offset,
&read_size, NULL,
- nand_info[nand_curr_device].size,
+ nand_info[nand_curr_device]->size,
(u_char *)bmp_load_addr);
}
#else
diff --git a/common/usb.c b/common/usb.c
index 8d9efe5..b3ba487 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1182,7 +1182,7 @@
* with the device. So a get_descriptor will fail before any
* of that is done for XHCI unlike EHCI.
*/
-#ifdef CONFIG_USB_XHCI
+#ifdef CONFIG_USB_XHCI_HCD
do_read = false;
#endif
err = usb_setup_device(dev, do_read, dev->parent);
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index d7725e4..8cb7ac7 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -9,20 +9,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index c39daf1..6a0d815 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -10,19 +10,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 955b6cf..a790856 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -14,19 +14,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 30ea836..d12a3cc 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -16,22 +16,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 546c84c..cc5858e 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -9,20 +9,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 5dc4ba3..7b0309c 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -7,20 +7,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e952562..e4168fa 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -10,19 +10,10 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index cecf4c2..6430606 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -12,20 +12,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 7479f7f..fc1be7d 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,18 +14,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index fde84ac..8262be5 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -16,18 +16,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 45539c1..44f3982 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,19 +8,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 52dfdf2..9d5365d 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,19 +6,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index fd6b8de..d9b1bd6 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -8,20 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index ae38583..496c20e 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -10,20 +10,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index cbbec47..3e8c0a1 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -8,19 +8,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index ab6f329..1cb010d 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -8,19 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 080bfbd..3257aae 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,20 +14,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 6380a22..2ce8cb1 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -18,20 +18,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 683f7f9..4b9d722 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -7,19 +7,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index f8c7107..c884115 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -7,18 +7,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 0d43c53..4e25392 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -12,22 +12,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index b5959ee..725652d 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -15,20 +15,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 7cc162b..5f01760 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -17,18 +17,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index f424557..02bcdbf 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -10,19 +10,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 4ff0a6b..fef3685 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,18 +15,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index f4832a7..cb6dfe4 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -7,19 +7,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 1227994..d2111c6 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -8,19 +8,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 3b0d8cf..378abce 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -9,19 +9,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 28768ec..c3f0421 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -7,19 +7,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 11bb709..9d8d325 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -7,18 +7,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index ca61e5c..49bb26a 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,18 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index a9d5aae..5559444 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,17 +10,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 14db5ae..3d71bf5 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,19 +13,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cb9ca3b..cef9794 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,19 +5,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index bae638f..b3f825e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,19 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 9311799..f076e30 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -7,18 +7,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 831578e..eccf372 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -8,19 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index d628c7c..d72dcc0 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -10,19 +10,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 35df225..0d1ba15 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,19 +9,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 8a4980e..f0b4384 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -8,19 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 842db29..53e023a 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -8,16 +8,6 @@
# CONFIG_VIDEO is not set
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 102b96c..53f9bfe 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,19 +6,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 212f98c..00c671b 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -11,19 +11,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 148b4fa..a865255 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -13,19 +13,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 4136841..ae1f1e8 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -12,19 +12,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 03cef97..013c35e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,16 +6,6 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index dc781db..181e1e2 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -8,19 +8,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 13dbb98..77b0525 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -15,20 +15,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_SW_ON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index 948107c..d36a5dc 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,19 +20,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index d754ccd..5f3d624 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,19 +13,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 4a7dbdb..bfc8cba 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,19 +12,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 0b40b83..fc43cc5 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,18 +7,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index fab74f4..65c1d8e 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,18 +19,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 71f01db..958104e 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,18 +16,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 62f26b5..696024c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,15 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -30,9 +26,14 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
@@ -42,3 +43,9 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_RSA=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index f230671..76a004e 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -38,3 +38,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 3fbc07b..99fc555 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -35,3 +35,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 65d88d8..d5aa3a2 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -38,3 +38,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index eee5e9b..cba5e84 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -38,3 +38,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
deleted file mode 100644
index d7f126e..0000000
--- a/configs/am335x_gp_evm_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_AM335X_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_RSA=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index c227ef4..3cd40e9 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -25,3 +25,4 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_hs_evm_defconfig
similarity index 86%
rename from configs/am437x_gp_evm_defconfig
rename to configs/am437x_hs_evm_defconfig
index f098fd3..3cd39eb 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -1,10 +1,14 @@
CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+# Device tree file can be same on HS evm
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
CONFIG_HUSH_PARSER=y
@@ -38,6 +42,8 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -47,4 +53,3 @@
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
deleted file mode 100644
index 8be0412..0000000
--- a/configs/am437x_sk_evm_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DMA=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index a6ae011..cb3de11 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,7 +1,15 @@
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,12 +31,19 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -38,4 +53,4 @@
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 662556a..3b958d7 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
@@ -28,6 +29,8 @@
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -38,3 +41,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 00fa6be..5264332 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -27,6 +29,8 @@
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -37,3 +41,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index e3d6b57..34c875e 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,6 +1,13 @@
CONFIG_ARM=y
+CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -23,11 +30,18 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -38,3 +52,8 @@
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 8fc3ebb..6743b84 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -32,3 +33,6 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 47d103b..1cf82d2 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -22,4 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
new file mode 100644
index 0000000..c109939
--- /dev/null
+++ b/configs/am57xx_hs_evm_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 7604e2e..91fa734 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -19,8 +19,13 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index b61b15c..1cfb380 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -10,19 +10,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index bfd519e..4404f32 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -22,3 +22,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x18d1
CONFIG_G_DNL_PRODUCT_NUM=0x0d02
CONFIG_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 1911122..60eb328 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -22,3 +22,4 @@
CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
CONFIG_G_DNL_VENDOR_NUM=0x18d1
CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index 85c2a6b..ea4f8e4 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -17,3 +17,4 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index ff797f8..faac28d 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -17,4 +17,5 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index eff2a12..d69b146 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -17,3 +17,4 @@
# CONFIG_NET_TFTP_VARS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 6d398ac..e4fa136 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -16,5 +16,6 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 44ed671..bb5db5c 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -38,3 +38,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 861bdcf..39cc222 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -38,3 +38,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 25ead92..d5bc515 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -47,7 +47,7 @@
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 0fde640..75ea200 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CLEARFOG=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_HUSH_PARSER=y
CONFIG_SPL=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index c926a3a..b80ca0d 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -37,4 +37,7 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 655a0e7..ae67c37 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,19 +16,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO2_VOLT=1800
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 2b6dba8..c76af0e 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -16,18 +16,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
deleted file mode 100644
index 00c6ac3..0000000
--- a/configs/dra72_evm_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b6458ae..756af63 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,11 +1,17 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -25,12 +31,19 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -40,4 +53,7 @@
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
deleted file mode 100644
index 8ebfe49..0000000
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
deleted file mode 100644
index 54c7ba9..0000000
--- a/configs/dra7xx_evm_uart3_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
similarity index 83%
rename from configs/dra74_evm_defconfig
rename to configs/dra7xx_hs_evm_defconfig
index 32ffce7..6933ab5 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_SPI=y
@@ -11,6 +13,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -41,6 +44,8 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
@@ -50,4 +55,7 @@
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_DM_ETH=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 2566ded..37c5ea77 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -23,7 +23,7 @@
CONFIG_PM8916_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_MSM_SDHCI=y
CONFIG_DM_PMIC=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index b0791b9..f8155b2 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -14,18 +14,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 4dd4586..9894fff 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -28,7 +28,7 @@
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0995f9b..4af9120 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -28,7 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -40,7 +40,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 03cdb17..34e74af 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -18,19 +18,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index f8d3c3b8..080c2ed 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -5,6 +5,7 @@
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index c11aed8..a14de0d 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -17,18 +17,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 7c731b3..e04d96b 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -11,19 +11,9 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 266015a..54fa819 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,19 +7,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index e9ec810..7ec54a7 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,18 +14,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 64da00f..5e68769 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,18 +14,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 8b64678..3dea793 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,18 +13,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index d432ff0..548a07e 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -14,19 +14,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index b0f244d..a8b32cb 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,19 +14,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a953795..0b03e16 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,18 +13,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index dace876..27b5019 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -16,18 +16,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 35d9d7c..153450f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,18 +13,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 79f3cfb..9cb8b1d 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,19 +8,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 044a9bf..9fcdfe9 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -32,3 +32,6 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index d0b45ce..8efa58c 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -32,3 +32,6 @@
CONFIG_DM_ETH=y
CONFIG_REMOTEPROC_TI_POWER=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 3975e80..278eaf3 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -32,3 +32,6 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 844dd57..8417e0a 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -32,3 +32,6 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 50fbe65..0ff6c6b 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -28,7 +28,7 @@
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644
index 0000000..04189de
--- /dev/null
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644
index 0000000..935f2fd
--- /dev/null
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
new file mode 100644
index 0000000..5c28bd1
--- /dev/null
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 04ded54..efaa7a9 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -27,3 +27,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 7915200..9fa5cb9 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -27,3 +27,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 9002a01..24b7a15 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -21,6 +21,9 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 30c2ca5..5d2b57d 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -22,6 +22,9 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index a30153a..426a4be 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -26,3 +26,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 217cf88..4f5c1e8 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -27,3 +27,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 15b0b0d..6a791c0 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -33,3 +33,6 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index ef42d3d..33e5c0c 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -25,3 +25,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 69f5b61..45f0f73 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -32,3 +32,6 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 1c0ae06..16243ee 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -22,6 +22,9 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 10cc576..3158340 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -26,3 +26,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index f56f931..bbeb4bf 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -27,3 +27,6 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index bc419fb..6910c4e 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -34,3 +34,6 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index e27758b..f59ad74 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -20,6 +20,9 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 01856d4..90f810a 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -34,3 +34,6 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 346faf4..1fbfd38 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -25,3 +25,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 2c6ac35..6b628d3 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -26,3 +26,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index cc8d8fa..90f870a 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -26,3 +26,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 7d0646c..813c269 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -24,3 +24,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 8ea1416..e665ba4 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -26,3 +26,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 7e5949d..03a263a 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -26,3 +26,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 609fd63..0062f5c 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -27,3 +27,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index cacee2f..bace827 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -21,4 +21,7 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 49d0740..48a89ab 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -21,3 +21,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index d240cde..627a90d 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -22,3 +22,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index f853685..c676a91 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -22,3 +22,6 @@
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index f9b4eac..56922dc 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -25,3 +25,5 @@
# CONFIG_CMD_MISC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 728fa25..f27fbb7 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -28,3 +28,5 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 216559c..49a4a26 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -29,4 +29,8 @@
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 854630a..c305345 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -29,3 +29,7 @@
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 4f385a1..8a6dd14 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -22,4 +22,8 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 41d30a6..a2d88cc 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -29,4 +29,8 @@
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 2b775cd..dc2b872 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -29,3 +29,7 @@
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 0f184c0..dbba8ab 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -22,4 +22,8 @@
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
new file mode 100644
index 0000000..7bef84c
--- /dev/null
+++ b/configs/malta64_defconfig
@@ -0,0 +1,16 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="malta # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
new file mode 100644
index 0000000..47ded9e
--- /dev/null
+++ b/configs/malta64el_defconfig
@@ -0,0 +1,17 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="maltael # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index a16f10b..3c3bb16 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,5 +1,6 @@
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
# CONFIG_CMD_LOADB is not set
@@ -9,5 +10,6 @@
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 5289797..b245d91 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,6 +1,7 @@
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
# CONFIG_CMD_LOADB is not set
@@ -10,5 +11,6 @@
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 8c7e4b7..2ef713f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -2,6 +2,10 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_DM=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_SYS_TEXT_BASE=0x29000000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 9a44466..ce81309 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,19 +9,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 5e545d0..720aefa 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,19 +7,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index a76a699..d38bc7f 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -6,19 +6,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index bdfb597..de1b73f 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,18 +4,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
new file mode 100644
index 0000000..483d490
--- /dev/null
+++ b/configs/odroid-c2_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXBB=y
+CONFIG_TARGET_ODROID_C2=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index c7708f1..c1d0fc3 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -37,6 +37,8 @@
CONFIG_DM_REGULATOR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_PHY_SAMSUNG=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 3226247..e7bf385 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index f33ac36..8b1082c 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -10,19 +10,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index de6e9c8..be8afca 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -9,17 +9,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7bade8f..7eaa795 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -8,19 +8,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 2df5859..9ff4332 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -12,19 +12,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
new file mode 100644
index 0000000..9f2c418
--- /dev/null
+++ b/configs/p2771-0000_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 7f29119..27f681f 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -30,3 +30,4 @@
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index eff099c..b277b3a 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -30,3 +30,4 @@
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index fea8bde..313fb03 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -58,6 +58,8 @@
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 41c3d12..eb5558a 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -58,6 +58,8 @@
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0494a9f..0bf79bf 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -4,17 +4,9 @@
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881915
# CONFIG_VIDEO is not set
-CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index cedbf53..04c99b9 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -17,18 +17,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index aad9619..9aa5280 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,18 +14,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 97232ce..b467b62 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -16,18 +16,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 79dcc33..7391464 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -17,18 +17,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index ff29e81..16f8600 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -17,18 +17,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index d87700c..6378918 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -17,18 +17,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 4e1c393..9d9d4bf 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,19 +6,8 @@
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index fd32fb5..3e16b80 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 9e4a92d..4eb3c22 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -97,7 +97,7 @@
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_SANDBOX_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
@@ -170,3 +170,6 @@
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_MISC=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 93167c2..60c7339 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -94,7 +94,7 @@
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 23b9c1e..43d3389 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -37,4 +37,6 @@
CONFIG_EXYNOS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a662e72..ec40ec7 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b2933f7..8e5c527 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index f197b6d..034a215 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 6624f9e..133a6eb 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index c6414f8..8b1bcfc 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index b47a560..56284a1 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index aab4498..d66f7c6 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_SR1500=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
new file mode 100644
index 0000000..6ce4def
--- /dev/null
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="samtec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
new file mode 100644
index 0000000..b7a16b7
--- /dev/null
+++ b/configs/strider_con_dp_defconfig
@@ -0,0 +1,20 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
new file mode 100644
index 0000000..db75c0d
--- /dev/null
+++ b/configs/strider_cpu_dp_defconfig
@@ -0,0 +1,20 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 3677da7..6d39dec 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,18 +11,7 @@
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index b7078e0..cb33f60 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -22,3 +22,4 @@
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_REGEX=y
+CONFIG_BOOTP_VCI_STRING="Diagnostics"
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index b1af2f6..3eec4c2 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -1,6 +1,7 @@
CONFIG_MIPS=y
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_NS16550=y
CONFIG_DM_SERIAL=y
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
new file mode 100644
index 0000000..ffcac79
--- /dev/null
+++ b/configs/uniphier_ld11_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD11=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 989f068..c0708b2 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index c70851f..5af9f58 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index b0a2f67..379dff2 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 2f141dd..c39faaa 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2"
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index c495ee5..e71d45e 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2"
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index fcd6e26..20100a3 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -24,3 +24,4 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4"
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index ace620b..14977dc 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -22,3 +22,4 @@
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 37b8052..fa380ef 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
@@ -9,6 +9,7 @@
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
@@ -19,6 +20,7 @@
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
@@ -56,6 +58,8 @@
CONFIG_DEBUG_UART_CLOCK=25000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_GADGET=y
@@ -64,3 +68,4 @@
CONFIG_G_DNL_VENDOR_NUM=0x03fd
CONFIG_G_DNL_PRODUCT_NUM=0x0300
# CONFIG_REGEX is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index fa761e5..35226d6 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
@@ -8,6 +9,7 @@
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
@@ -49,6 +51,8 @@
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
@@ -58,3 +62,4 @@
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 2811d4b..cc13179 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
@@ -8,11 +9,13 @@
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
@@ -40,7 +43,14 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
@@ -50,3 +60,4 @@
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
new file mode 100644
index 0000000..6570348
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 3711084..e1fc8b0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
@@ -32,3 +34,4 @@
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_DM_ETH=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 46a5dd0..2829029 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
@@ -47,6 +49,8 @@
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
@@ -56,3 +60,4 @@
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 96a2be1..92633d6 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
@@ -47,6 +49,8 @@
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
@@ -56,3 +60,4 @@
CONFIG_G_DNL_MANUFACTURER="Xilinx"
CONFIG_G_DNL_VENDOR_NUM=0x03FD
CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index fe308d7..0af1e92 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -439,7 +439,7 @@
gpt_e[i].starting_lba = cpu_to_le64(offset);
offset += partitions[i].size;
}
- if (offset >= last_usable_lba) {
+ if (offset > (last_usable_lba + 1)) {
printf("Partitions layout exceds disk size\n");
return -1;
}
diff --git a/doc/README.fdt-control b/doc/README.fdt-control
index 29fd56a..2913fcb 100644
--- a/doc/README.fdt-control
+++ b/doc/README.fdt-control
@@ -33,12 +33,6 @@
generic source base.
To enable this feature, add CONFIG_OF_CONTROL to your board config file.
-It is currently supported on ARM, x86 and Microblaze - other architectures
-will need to add code to their arch/xxx/lib/board.c file to locate the
-FDT. Alternatively you can enable generic board support on your board
-(with CONFIG_SYS_GENERIC_BOARD) if this is available (as it is for
-PowerPC). For ARM, Tegra and Exynos5 have device trees available for
-common devices.
What is a Flat Device Tree?
diff --git a/doc/README.generic-board b/doc/README.generic-board
index 734f1aa..6858c4d 100644
--- a/doc/README.generic-board
+++ b/doc/README.generic-board
@@ -5,29 +5,22 @@
# SPDX-License-Identifier: GPL-2.0+
#
-DEPRECATION NOTICE FOR arch/<arch>/lib/board.c
-
-For board maintainers: Please submit patches for boards you maintain before
-July 2014, to make them use generic board.
-
-For architecture maintainers: Please submit patches to remove your
-architecture-specific board.c file before October 2014.
-
-
Background
----------
-U-Boot has traditionally had a board.c file for each architecture. This has
-introduced quite a lot of duplication, with each architecture tending to do
+U-Boot traditionally had a board.c file for each architecture. This introduced
+quite a lot of duplication, with each architecture tending to do
initialisation slightly differently. To address this, a new 'generic board
-init' feature was introduced a year ago in March 2013 (further motivation is
+init' feature was introduced in March 2013 (further motivation is
provided in the cover letter below).
+All boards and architectures have moved to this as of mid 2016.
+
What has changed?
-----------------
-The main change is that the arch/<arch>/lib/board.c file is being removed in
+The main change is that the arch/<arch>/lib/board.c file is removed in
favour of common/board_f.c (for pre-relocation init) and common/board_r.c
(for post-relocation init).
@@ -36,55 +29,6 @@
have been moved to separate structures.
-Supported Architectures
-------------------------
-
-If you are unlucky then your architecture may not support generic board.
-The following architectures are supported now:
-
- arc
- arm
- avr32
- blackfin
- m68k
- microblaze
- mips
- nios2
- powerpc
- sandbox
- x86
-
-If your architecture is not supported, you need to select
-HAVE_GENERIC_BOARD in arch/Kconfig
-and test it with a suitable board, as follows.
-
-
-Adding Support for your Board
------------------------------
-
-To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in
-your board config header file.
-
-Test that U-Boot still functions correctly on your board, and fix any
-problems you find. Don't be surprised if there are no problems - generic
-board has had a reasonable amount of testing with common boards.
-
-
-DeadLine
---------
-
-Please don't take this the wrong way - there is no intent to make your life
-miserable, and we have the greatest respect and admiration for U-Boot users.
-However, with any migration there has to be a period where the old way is
-deprecated and removed. Every patch to the deprecated code introduces a
-potential breakage in the new unused code. Therefore:
-
-Boards or architectures not converted over to general board by the
-end of 2014 may be forcibly changed over (potentially causing run-time
-breakage) or removed.
-
-
-
Further Background
------------------
@@ -190,3 +134,4 @@
Simon Glass, sjg@chromium.org
March 2014
+Updated after final removal, May 2016
diff --git a/doc/README.nand b/doc/README.nand
index 545d88c..96ffc48 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -136,15 +136,8 @@
Example of new init to be added to the end of an existing driver
init:
- /*
- * devnum is the device number to be used in nand commands
- * and in mtd->name. Must be less than
- * CONFIG_SYS_NAND_MAX_DEVICE.
- */
- mtd = &nand_info[devnum];
-
/* chip is struct nand_chip, and is now provided by the driver. */
- mtd->priv = &chip;
+ mtd = &chip.mtd;
/*
* Fill in appropriate values if this driver uses these fields,
@@ -165,7 +158,11 @@
if (nand_scan_tail(mtd))
error out
- if (nand_register(devnum))
+ /*
+ * devnum is the device number to be used in nand commands
+ * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
+ */
+ if (nand_register(devnum, mtd))
error out
In addition to providing more flexibility to the driver, it reduces
diff --git a/doc/README.ti-secure b/doc/README.ti-secure
new file mode 100644
index 0000000..7fc9b9b
--- /dev/null
+++ b/doc/README.ti-secure
@@ -0,0 +1,91 @@
+README on how boot images are created for secure TI devices
+
+CONFIG_TI_SECURE_DEVICE:
+Secure TI devices require a boot image that is authenticated by ROM
+code to function. Without this, even JTAG remains locked and the
+device is essentially useless. In order to create a valid boot image for
+a secure device from TI, the initial public software image must be signed
+and combined with various headers, certificates, and other binary images.
+
+Information on the details on the complete boot image format can be obtained
+from Texas Instruments. The tools used to generate boot images for secure
+devices are part of a secure development package (SECDEV) that can be
+downloaded from:
+
+ http://www.ti.com/mysecuresoftware (login required)
+
+The secure development package is access controlled due to NDA and export
+control restrictions. Access must be requested and granted by TI before the
+package is viewable and downloadable. Contact TI, either online or by way
+of a local TI representative, to request access.
+
+When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process requires
+the presence and use of these tools in order to create a viable boot image.
+The build process will look for the environment variable TI_SECURE_DEV_PKG,
+which should be the path of the installed SECDEV package. If the
+TI_SECURE_DEV_PKG variable is not defined or if it is defined but doesn't
+point to a valid SECDEV package, a warning is issued during the build to
+indicate that a final secure bootable image was not created.
+
+Within the SECDEV package exists an image creation script:
+
+${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
+
+This is called as part of the SPL/u-boot build process. As the secure boot
+image formats and requirements differ between secure SOC from TI, the
+purpose of this script is to abstract these details as much as possible.
+
+The script is basically the only required interface to the TI SECDEV package
+for secure TI devices.
+
+Invoking the script for AM43xx Secure Devices
+=============================================
+
+create-boot-image.sh <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+<IMAGE_FLAG> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+ SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
+ XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
+ ISSW - Generates an image for all other boot modes
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (depending on the boot media, this is usually either
+u-boot-spl.bin or u-boot.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+ u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
+ u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI flash
+ u-boot-spl_HS_ISSW - boot image for all other boot media
+
+<SPL_LOAD_ADDR> is the address at which SOC ROM should load the <INPUT_FILE>
+
+Invoking the script for DRA7xx/AM57xx Secure Devices
+====================================================
+
+create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
+
+<IMAGE_TYPE> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+ X-LOADER - Generates an image for NOR or QSPI boot modes
+ MLO - Generates an image for SD/MMC/eMMC boot modes
+ ULO - Generates an image for USB/UART peripheral boot modes
+ Note: ULO is not yet used by the u-boot build process
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (for this platform, this is always u-boot-spl.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+ u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC. This image is
+ copied to a file named MLO, which is the name that
+ the device ROM bootloader requires for loading from
+ the FAT partition of an SD card (same as on
+ non-secure devices)
+ u-boot-spl_HS_X-LOADER - boot image for all other flash memories
+ including QSPI and NOR flash
diff --git a/doc/README.x86 b/doc/README.x86
index 4d50feb..a548b54 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -1028,12 +1028,15 @@
those legacy stuff into U-Boot. ACPI spec allows a system that does not
support SMI (a legacy-free system).
-So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+ACPI was initially enabled on BayTrail based boards. Testing was done by booting
a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
devices seem to work correctly and the board can respond a reboot/shutdown
command from the OS.
+For other platform boards, ACPI support status can be checked by examining their
+board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
+
TODO List
---------
- Audio
diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
new file mode 100644
index 0000000..c82a2e2
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
@@ -0,0 +1,161 @@
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+ Array of strings.
+ One of:
+ - "nvidia,tegra186-gpio".
+ - "nvidia,tegra186-gpio-aon".
+- reg-names
+ Array of strings.
+ Contains a list of names for the register spaces described by the reg
+ property. May contain the following entries, in any order:
+ - "gpio": Mandatory. GPIO control registers. This may cover either:
+ a) The single physical alias that this OS should use.
+ b) All physical aliases that exist in the controller. This is
+ appropriate when the OS is responsible for managing assignment of
+ the physical aliases.
+ - "security": Optional. Security configuration registers.
+ Users of this binding MUST look up entries in the reg property by name,
+ using this reg-names property to do so.
+- reg
+ Array of (physical base address, length) tuples.
+ Must contain one entry per entry in the reg-names property, in a matching
+ order.
+- interrupts
+ Array of interrupt specifiers.
+ The interrupt outputs from the HW block, one per set of ports, in the
+ order the HW manual describes them. The number of entries required varies
+ depending on compatible value:
+ - "nvidia,tegra186-gpio": 6 entries.
+ - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+ Boolean.
+ Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's GPIO specifier.
+ In the specifier:
+ - The first cell is the pin number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell contains flags:
+ - Bit 0 specifies polarity
+ - 0: Active-high (normal).
+ - 1: Active-low (inverted).
+- interrupt-controller
+ Boolean.
+ Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's interrupt specifier.
+ In the specifier:
+ - The first cell is the GPIO number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell is contains flags:
+ - Bits [3:0] indicate trigger type and level:
+ - 1: Low-to-high edge triggered.
+ - 2: High-to-low edge triggered.
+ - 4: Active high level-sensitive.
+ - 8: Active low level-sensitive.
+ Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <0 47 IRQ_TYPE_LEVEL_HIGH>,
+ <0 50 IRQ_TYPE_LEVEL_HIGH>,
+ <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ <0 56 IRQ_TYPE_LEVEL_HIGH>,
+ <0 59 IRQ_TYPE_LEVEL_HIGH>,
+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/doc/device-tree-bindings/mailbox/mailbox.txt b/doc/device-tree-bindings/mailbox/mailbox.txt
new file mode 100644
index 0000000..be05b97
--- /dev/null
+++ b/doc/device-tree-bindings/mailbox/mailbox.txt
@@ -0,0 +1,32 @@
+* Generic Mailbox Controller and client driver bindings
+
+Generic binding to provide a way for Mailbox controller drivers to
+assign appropriate mailbox channel to client drivers.
+
+* Mailbox Controller
+
+Required property:
+- #mbox-cells: Must be at least 1. Number of cells in a mailbox
+ specifier.
+
+Example:
+ mailbox: mailbox {
+ ...
+ #mbox-cells = <1>;
+ };
+
+
+* Mailbox Client
+
+Required property:
+- mboxes: List of phandle and mailbox channel specifiers.
+
+Optional property:
+- mbox-names: List of identifier strings for each mailbox channel.
+
+Example:
+ pwr_cntrl: power {
+ ...
+ mbox-names = "pwr-ctrl", "rpc";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ };
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index 7a24552..1b5ccec 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -606,19 +606,24 @@
1. Bind stage
-A device and its driver are bound using one of these two methods:
+U-Boot discovers devices using one of these two methods:
- - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the
-name specified by each, to find the appropriate driver. It then calls
-device_bind() to create a new device and bind' it to its driver. This will
-call the device's bind() method.
+ - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
+by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
+there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
+may provide platdata.
- Scan through the device tree definitions. U-Boot looks at top-level
nodes in the the device tree. It looks at the compatible string in each node
-and uses the of_match part of the U_BOOT_DRIVER() structure to find the
-right driver for each node. It then calls device_bind() to bind the
-newly-created device to its driver (thereby creating a device structure).
-This will also call the device's bind() method.
+and uses the of_match table of the U_BOOT_DRIVER() structure to find the
+right driver for each node. In this case, the of_match table may provide a
+driver_data value, but platdata cannot be provided until later.
+
+For each device that is discovered, U-Boot then calls device_bind() to create a
+new device, initializes various core fields of the device object such as name,
+uclass & driver, initializes any optional fields of the device object that are
+applicable such as of_offset, driver_data & platdata, and finally calls the
+driver's bind() method if one is defined.
At this point all the devices are known, and bound to their drivers. There
is a 'struct udevice' allocated for all devices. However, nothing has been
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 118b66e..f2a137a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -30,6 +30,8 @@
source "drivers/led/Kconfig"
+source "drivers/mailbox/Kconfig"
+
source "drivers/memory/Kconfig"
source "drivers/misc/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 99dd07f..f6295d2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -64,6 +64,7 @@
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-$(CONFIG_U_QE) += qe/
+obj-y += mailbox/
obj-y += memory/
obj-y += pwm/
obj-y += input/
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index bd5f22a..7ec65bd 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -407,7 +407,7 @@
}
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
+ ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
if (ret)
debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 2a85e93..d88893c 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -326,6 +326,17 @@
return 0;
}
+static int rockchip_mac_set_clk(struct rk3288_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(&cru->cru_clksel_con[21],
+ RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+ RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+
+ return 0;
+}
+
static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
int periph, unsigned int rate_hz)
{
@@ -759,6 +770,9 @@
new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
break;
#ifndef CONFIG_SPL_BUILD
+ case SCLK_MAC:
+ new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+ break;
case DCLK_VOP0:
case DCLK_VOP1:
new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
@@ -877,7 +891,7 @@
}
/* The reset driver does not have a device node, so bind it here */
- ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
+ ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
if (ret)
debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index a2b0e80..c6ecd11 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -165,6 +165,10 @@
.data = (ulong)&uniphier_mio_clk_data,
},
{
+ .compatible = "socionext,ph1-ld11-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
.compatible = "socionext,ph1-ld20-mioctrl",
.data = (ulong)&uniphier_mio_clk_data,
},
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c5c9d2a..8749561 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -178,4 +178,27 @@
used for the address translation. This function is faster and
smaller in size than fdt_translate_address().
+config OF_ISA_BUS
+ bool
+ depends on OF_TRANSLATE
+ help
+ Is this option is enabled then support for the ISA bus will
+ be included for addresses read from DT. This is something that
+ should be known to be required or not based upon the board
+ being targetted, and whether or not it makes use of an ISA bus.
+
+ The bus is matched based upon its node name equalling "isa". The
+ busses #address-cells should equal 2, with the first cell being
+ used to hold flags & flag 0x1 indicating that the address range
+ should be accessed using I/O port in/out accessors. The second
+ cell holds the offset into ISA bus address space. The #size-cells
+ property should equal 1, and of course holds the size of the
+ address range used by a device.
+
+ If this option is not enabled then support for the ISA bus is
+ not included and any such busses used in DT will be treated as
+ typical simple-bus compatible busses. This will lead to
+ mistranslation of device addresses, so ensure that this is
+ enabled if your board does include an ISA bus.
+
endmenu
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 45d5e3e..eb75b17 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -26,9 +26,10 @@
DECLARE_GLOBAL_DATA_PTR;
-int device_bind(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, int of_offset,
- struct udevice **devp)
+static int device_bind_common(struct udevice *parent, const struct driver *drv,
+ const char *name, void *platdata,
+ ulong driver_data, int of_offset,
+ struct udevice **devp)
{
struct udevice *dev;
struct uclass *uc;
@@ -56,6 +57,7 @@
INIT_LIST_HEAD(&dev->devres_head);
#endif
dev->platdata = platdata;
+ dev->driver_data = driver_data;
dev->name = name;
dev->of_offset = of_offset;
dev->parent = parent;
@@ -193,6 +195,23 @@
return ret;
}
+int device_bind_with_driver_data(struct udevice *parent,
+ const struct driver *drv, const char *name,
+ ulong driver_data, int of_offset,
+ struct udevice **devp)
+{
+ return device_bind_common(parent, drv, name, NULL, driver_data,
+ of_offset, devp);
+}
+
+int device_bind(struct udevice *parent, const struct driver *drv,
+ const char *name, void *platdata, int of_offset,
+ struct udevice **devp)
+{
+ return device_bind_common(parent, drv, name, platdata, 0, of_offset,
+ devp);
+}
+
int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
const struct driver_info *info, struct udevice **devp)
{
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index a72db13..0c27717 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -170,7 +170,8 @@
}
dm_dbg(" - found match at '%s'\n", entry->name);
- ret = device_bind(parent, entry, name, NULL, offset, &dev);
+ ret = device_bind_with_driver_data(parent, entry, name,
+ id->data, offset, &dev);
if (ret == -ENODEV) {
dm_dbg("Driver '%s' refuses to bind\n", entry->name);
continue;
@@ -180,7 +181,6 @@
ret);
return ret;
} else {
- dev->driver_data = id->data;
found = true;
if (devp)
*devp = dev;
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917..1d5cec6 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
- | ((wr_lat & 0x10) << 14)
+ | ((wr_lat & 0x10) << 18)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
@@ -1835,10 +1835,17 @@
/* Per FSL Application Note: AN2805 */
ss_en = 1;
#endif
- clk_adjust = popts->clk_adjust;
+ if (fsl_ddr_get_version(0) >= 0x40701) {
+ /* clk_adjust in 5-bits on T-series and LS-series */
+ clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+ } else {
+ /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+ clk_adjust = (popts->clk_adjust & 0xF) << 23;
+ }
+
ddr->ddr_sdram_clk_cntl = (0
| ((ss_en & 0x1) << 31)
- | ((clk_adjust & 0xF) << 23)
+ | clk_adjust
);
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 5039f5d..d37e247 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -206,12 +206,14 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
/* part 1 of 2 */
- if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
- ddr_out32(&ddr->ddr_sdram_rcw_2,
- regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+ ddr_out32(&ddr->ddr_sdram_rcw_2,
+ regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ }
+ ddr_out32(&ddr->err_disable, regs->err_disable |
+ DDR_ERR_DISABLE_APED);
}
-
- ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
#else
ddr_out32(&ddr->err_disable, regs->err_disable);
#endif
@@ -395,22 +397,24 @@
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
- /* if it's RDIMM */
- if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
- continue;
- set_wait_for_bits_clear(&ddr->sdram_md_cntl,
- MD_CNTL_MD_EN |
- MD_CNTL_CS_SEL(i) |
- 0x070000ed,
- MD_CNTL_MD_EN);
- udelay(1);
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ /* if it's RDIMM */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+ continue;
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
+ }
}
- }
- ddr_out32(&ddr->err_disable,
- regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ }
#endif
}
#endif
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d0075ff..793d12a 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -886,7 +886,8 @@
} else
popts->ecc_mode = 1;
#endif
- popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+ /* 1 = use memory controler to init data */
+ popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
/*
* Choose DQS config
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index a975492..ab782be 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -25,7 +25,7 @@
loff_t start, lim;
size_t count, actual;
int ret;
- nand_info_t *nand;
+ struct mtd_info *mtd;
/* if buf == NULL return total size of the area */
if (buf == NULL) {
@@ -39,16 +39,16 @@
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- nand = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
if (op == DFU_OP_READ) {
- ret = nand_read_skip_bad(nand, start, &count, &actual,
- lim, buf);
+ ret = nand_read_skip_bad(mtd, start, &count, &actual,
+ lim, buf);
} else {
nand_erase_options_t opts;
@@ -59,12 +59,12 @@
opts.quiet = 1;
opts.lim = lim;
/* first erase */
- ret = nand_erase_opts(nand, &opts);
+ ret = nand_erase_opts(mtd, &opts);
if (ret)
return ret;
/* then write */
- ret = nand_write_skip_bad(nand, start, &count, &actual,
- lim, buf, WITH_WR_VERIFY);
+ ret = nand_write_skip_bad(mtd, start, &count, &actual,
+ lim, buf, WITH_WR_VERIFY);
}
if (ret != 0) {
@@ -142,24 +142,24 @@
/* in case of ubi partition, erase rest of the partition */
if (dfu->data.nand.ubi) {
- nand_info_t *nand;
+ struct mtd_info *mtd;
nand_erase_options_t opts;
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- nand = &nand_info[nand_curr_device];
+ mtd = nand_info[nand_curr_device];
memset(&opts, 0, sizeof(opts));
opts.offset = dfu->data.nand.start + dfu->offset +
dfu->bad_skip;
opts.length = dfu->data.nand.start +
dfu->data.nand.size - opts.offset;
- ret = nand_erase_opts(nand, &opts);
+ ret = nand_erase_opts(mtd, &opts);
if (ret != 0)
printf("Failure erase: %d\n", ret);
}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..73b862d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,6 +109,21 @@
of 'anonymous' GPIOs that do not belong to any device or bank.
Select a suitable value depending on your needs.
+config TEGRA_GPIO
+ bool "Tegra20..210 GPIO driver"
+ depends on DM_GPIO
+ help
+ Support for the GPIO controller contained in NVIDIA Tegra20 through
+ Tegra210.
+
+config TEGRA186_GPIO
+ bool "Tegra186 GPIO driver"
+ depends on DM_GPIO
+ help
+ Support for the GPIO controller contained in NVIDIA Tegra186. This
+ covers both the "main" and "AON" controller instances, even though
+ they have slightly different register layout.
+
config GPIO_UNIPHIER
bool "UniPhier GPIO"
depends on ARCH_UNIPHIER
@@ -173,4 +188,30 @@
Now, max 24 bits chips and PCA953X compatible chips are
supported
+
+config MPC85XX_GPIO
+ bool "Freescale MPC85XX GPIO driver"
+ depends on DM_GPIO
+ help
+ This driver supports the built-in GPIO controller of MPC85XX CPUs.
+ Each GPIO bank is identified by its own entry in the device tree,
+ i.e.
+
+ gpio-controller@fc00 {
+ #gpio-cells = <2>;
+ compatible = "fsl,pq3-gpio";
+ reg = <0xfc00 0x100>
+ }
+
+ By default, each bank is assumed to have 32 GPIOs, but the ngpios
+ setting is honored, so the number of GPIOs for each bank is
+ configurable to match the actual GPIO count of the SoC (e.g. the
+ 32/32/23 banks of the P1022 SoC).
+
+ Aside from the standard functions of input/output mode, and output
+ value setting, the open-drain feature, which can configure individual
+ GPIOs to work as open-drain outputs, is supported.
+
+ The driver has been tested on MPC85XX, but it is likely that other
+ PowerQUICC III devices will work as well.
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..792d191 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -31,10 +31,12 @@
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
+obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+obj-$(CONFIG_MPC85XX_GPIO) += mpc85xx_gpio.o
obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 732b6c2..4559739 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -367,6 +367,38 @@
return 0;
}
+int dm_gpio_get_open_drain(struct gpio_desc *desc)
+{
+ struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+ int ret;
+
+ ret = check_reserved(desc, "get_open_drain");
+ if (ret)
+ return ret;
+
+ if (ops->set_open_drain)
+ return ops->get_open_drain(desc->dev, desc->offset);
+ else
+ return -ENOSYS;
+}
+
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value)
+{
+ struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+ int ret;
+
+ ret = check_reserved(desc, "set_open_drain");
+ if (ret)
+ return ret;
+
+ if (ops->set_open_drain)
+ ret = ops->set_open_drain(desc->dev, desc->offset, value);
+ else
+ return 0; /* feature not supported -> ignore setting */
+
+ return ret;
+}
+
int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
{
struct udevice *dev = desc->dev;
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
new file mode 100644
index 0000000..04773e2
--- /dev/null
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ *
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <mapmem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+};
+
+struct mpc85xx_gpio_data {
+ /* The bank's register base in memory */
+ struct ccsr_gpio __iomem *base;
+ /* The address of the registers; used to identify the bank */
+ ulong addr;
+ /* The GPIO count of the bank */
+ uint gpio_count;
+ /* The GPDAT register cannot be used to determine the value of output
+ * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
+ * for output pins */
+ u32 dat_shadow;
+};
+
+inline u32 gpio_mask(unsigned gpio) {
+ return (1U << (31 - (gpio)));
+}
+
+static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdat) & mask;
+}
+
+static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdir) & mask;
+}
+
+static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 0 -> input */
+ clrbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+{
+ setbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+ gpios)
+{
+ /* GPODR register 1 -> open drain on */
+ setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
+ u32 gpios)
+{
+ /* GPODR register 0 -> open drain off (actively driven) */
+ clrbits_be32(&base->gpodr, gpios);
+}
+
+static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
+ return 0;
+}
+
+static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ if (value) {
+ data->dat_shadow |= gpio_mask(gpio);
+ mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
+ } else {
+ data->dat_shadow &= ~gpio_mask(gpio);
+ mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
+ }
+ return 0;
+}
+
+static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ return mpc85xx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+ /* Output -> use shadowed value */
+ return !!(data->dat_shadow & gpio_mask(gpio));
+ } else {
+ /* Input -> read value from GPDAT register */
+ return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
+ }
+}
+
+static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+ if (value) {
+ mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+ } else {
+ mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+ }
+ return 0;
+}
+
+static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+ int dir;
+
+ dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
+ return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", 0, &size);
+
+ data->addr = addr;
+ data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+ if (!data->base)
+ return -ENOMEM;
+
+ data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "ngpios", 32);
+ data->dat_shadow = 0;
+
+ return 0;
+}
+
+static int mpc85xx_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+ char name[32], *str;
+
+ snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ str = strdup(name);
+
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = data->gpio_count;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc85xx_ops = {
+ .direction_input = mpc85xx_gpio_direction_input,
+ .direction_output = mpc85xx_gpio_direction_output,
+ .get_value = mpc85xx_gpio_get_value,
+ .set_value = mpc85xx_gpio_set_value,
+ .get_open_drain = mpc85xx_gpio_get_open_drain,
+ .set_open_drain = mpc85xx_gpio_set_open_drain,
+ .get_function = mpc85xx_gpio_get_function,
+};
+
+static const struct udevice_id mpc85xx_gpio_ids[] = {
+ { .compatible = "fsl,pq3-gpio" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc85xx) = {
+ .name = "gpio_mpc85xx",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_mpc85xx_ops,
+ .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
+ .of_match = mpc85xx_gpio_ids,
+ .probe = mpc85xx_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
+};
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index b54a10b..c25b4c1 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -8,7 +8,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 987d10e..065b181 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -16,8 +16,8 @@
*
* TODO:
* 1. Support PCA957X_TYPE
- * 2. Support max 40 gpio pins
- * 3. Support Plolarity Inversion
+ * 2. Support 24 gpio pins
+ * 3. Support Polarity Inversion
*/
#include <common.h>
@@ -47,7 +47,7 @@
PCA953X_DIRECTION_OUT,
};
-#define MAX_BANK 3
+#define MAX_BANK 5
#define BANK_SZ 8
DECLARE_GLOBAL_DATA_PTR;
@@ -121,6 +121,9 @@
ret = dm_i2c_read(dev, reg, val, 1);
} else if (info->gpio_count <= 16) {
ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+ } else if (info->gpio_count == 40) {
+ /* Auto increment */
+ ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
} else {
dev_err(dev, "Unsupported now\n");
return -EINVAL;
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fefe3ca..64abcba 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -8,7 +8,6 @@
*/
#include <common.h>
-#include <clk.h>
#include <dm.h>
#include <syscon.h>
#include <asm/errno.h>
diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
index a9b1efcd..f6435a0 100644
--- a/drivers/gpio/sandbox.c
+++ b/drivers/gpio/sandbox.c
@@ -15,6 +15,7 @@
/* Flags for each GPIO */
#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */
#define GPIOF_HIGH (1 << 1) /* Currently set high */
+#define GPIOF_ODR (1 << 2) /* Currently set to open drain mode */
struct gpio_state {
const char *label; /* label given by requester */
@@ -70,6 +71,16 @@
return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
}
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+ return get_gpio_flag(dev, offset, GPIOF_ODR);
+}
+
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+ return set_gpio_flag(dev, offset, GPIOF_ODR, value);
+}
+
int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
{
return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
@@ -124,6 +135,28 @@
return sandbox_gpio_set_value(dev, offset, value);
}
+/* read GPIO ODR value of port 'offset' */
+static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+ debug("%s: offset:%u\n", __func__, offset);
+
+ return sandbox_gpio_get_open_drain(dev, offset);
+}
+
+/* write GPIO ODR value to port 'offset' */
+static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+ debug("%s: offset:%u, value = %d\n", __func__, offset, value);
+
+ if (!sandbox_gpio_get_direction(dev, offset)) {
+ printf("sandbox_gpio: error: set_open_drain on input gpio %u\n",
+ offset);
+ return -1;
+ }
+
+ return sandbox_gpio_set_open_drain(dev, offset, value);
+}
+
static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
{
if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
@@ -154,6 +187,8 @@
.direction_output = sb_gpio_direction_output,
.get_value = sb_gpio_get_value,
.set_value = sb_gpio_set_value,
+ .get_open_drain = sb_gpio_get_open_drain,
+ .set_open_drain = sb_gpio_set_open_drain,
.get_function = sb_gpio_get_function,
.xlate = sb_gpio_xlate,
};
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index a7cec18..94abbeb 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -258,43 +258,30 @@
return 0;
}
+
+struct sunxi_gpio_soc_data {
+ int start;
+ int no_banks;
+};
+
/**
* We have a top-level GPIO device with no actual GPIOs. It has a child
* device for each Sunxi bank.
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
+ struct sunxi_gpio_soc_data *soc_data =
+ (struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
struct sunxi_gpio_platdata *plat = parent->platdata;
struct sunxi_gpio_reg *ctlr;
- int bank, no_banks, ret, start;
+ int bank, ret;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
- if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun6i-a31-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 2; /* L & M */
- } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a23-r-pinctrl") == 0 ||
- fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a83t-r-pinctrl") == 0 ||
- fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-h3-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 1; /* L only */
- } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun9i-a80-r-pinctrl") == 0) {
- start = 'L' - 'A';
- no_banks = 3; /* L, M & N */
- } else {
- start = 0;
- no_banks = SUNXI_GPIO_BANKS;
- }
-
ctlr = (struct sunxi_gpio_reg *)dev_get_addr(parent);
- for (bank = 0; bank < no_banks; bank++) {
+ for (bank = 0; bank < soc_data->no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
@@ -302,7 +289,7 @@
if (!plat)
return -ENOMEM;
plat->regs = &ctlr->gpio_bank[bank];
- plat->bank_name = gpio_bank_name(start + bank);
+ plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
ret = device_bind(parent, parent->driver,
@@ -315,23 +302,46 @@
return 0;
}
+static const struct sunxi_gpio_soc_data soc_data_a_all = {
+ .start = 0,
+ .no_banks = SUNXI_GPIO_BANKS,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_1 = {
+ .start = 'L' - 'A',
+ .no_banks = 1,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_2 = {
+ .start = 'L' - 'A',
+ .no_banks = 2,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_3 = {
+ .start = 'L' - 'A',
+ .no_banks = 3,
+};
+
+#define ID(_compat_, _soc_data_) \
+ { .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
+
static const struct udevice_id sunxi_gpio_ids[] = {
- { .compatible = "allwinner,sun4i-a10-pinctrl" },
- { .compatible = "allwinner,sun5i-a10s-pinctrl" },
- { .compatible = "allwinner,sun5i-a13-pinctrl" },
- { .compatible = "allwinner,sun6i-a31-pinctrl" },
- { .compatible = "allwinner,sun6i-a31s-pinctrl" },
- { .compatible = "allwinner,sun7i-a20-pinctrl" },
- { .compatible = "allwinner,sun8i-a23-pinctrl" },
- { .compatible = "allwinner,sun8i-a33-pinctrl" },
- { .compatible = "allwinner,sun8i-a83t-pinctrl", },
- { .compatible = "allwinner,sun8i-h3-pinctrl" },
- { .compatible = "allwinner,sun9i-a80-pinctrl" },
- { .compatible = "allwinner,sun6i-a31-r-pinctrl" },
- { .compatible = "allwinner,sun8i-a23-r-pinctrl" },
- { .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
- { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
- { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
+ ID("allwinner,sun4i-a10-pinctrl", a_all),
+ ID("allwinner,sun5i-a10s-pinctrl", a_all),
+ ID("allwinner,sun5i-a13-pinctrl", a_all),
+ ID("allwinner,sun6i-a31-pinctrl", a_all),
+ ID("allwinner,sun6i-a31s-pinctrl", a_all),
+ ID("allwinner,sun7i-a20-pinctrl", a_all),
+ ID("allwinner,sun8i-a23-pinctrl", a_all),
+ ID("allwinner,sun8i-a33-pinctrl", a_all),
+ ID("allwinner,sun8i-a83t-pinctrl", a_all),
+ ID("allwinner,sun8i-h3-pinctrl", a_all),
+ ID("allwinner,sun9i-a80-pinctrl", a_all),
+ ID("allwinner,sun6i-a31-r-pinctrl", l_2),
+ ID("allwinner,sun8i-a23-r-pinctrl", l_1),
+ ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
+ ID("allwinner,sun8i-h3-r-pinctrl", l_1),
+ ID("allwinner,sun9i-a80-r-pinctrl", l_3),
{ }
};
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
new file mode 100644
index 0000000..1c68151
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.
+ * (based on tegra_gpio.c)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "tegra186_gpio_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_gpio_port_data {
+ const char *name;
+ uint32_t offset;
+};
+
+struct tegra186_gpio_ctlr_data {
+ const struct tegra186_gpio_port_data *ports;
+ uint32_t port_count;
+};
+
+struct tegra186_gpio_platdata {
+ const char *name;
+ uint32_t *regs;
+};
+
+static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
+ uint32_t gpio)
+{
+ struct tegra186_gpio_platdata *plat = dev->platdata;
+ uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
+
+ return &(plat->regs[index]);
+}
+
+static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
+ bool output)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
+ rval = readl(reg);
+ if (output)
+ rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+ else
+ rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+ writel(rval, reg);
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+ if (output)
+ rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+ else
+ rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+ rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
+ writel(rval, reg);
+
+ return 0;
+}
+
+static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
+ rval = readl(reg);
+ if (val)
+ rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+ else
+ rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+ writel(rval, reg);
+
+ return 0;
+}
+
+static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ return tegra186_gpio_set_out(dev, offset, false);
+}
+
+static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ int ret;
+
+ ret = tegra186_gpio_set_val(dev, offset, value != 0);
+ if (ret)
+ return ret;
+ return tegra186_gpio_set_out(dev, offset, true);
+}
+
+static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+
+ if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
+ offset);
+ else
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
+
+ rval = readl(reg);
+ return !!rval;
+}
+
+static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ return tegra186_gpio_set_val(dev, offset, value != 0);
+}
+
+static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ uint32_t *reg;
+ uint32_t rval;
+
+ reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+ rval = readl(reg);
+ if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ int gpio, port, ret;
+
+ gpio = args->args[0];
+ port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
+ ret = device_get_child(dev, port, &desc->dev);
+ if (ret)
+ return ret;
+ desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops tegra186_gpio_ops = {
+ .direction_input = tegra186_gpio_direction_input,
+ .direction_output = tegra186_gpio_direction_output,
+ .get_value = tegra186_gpio_get_value,
+ .set_value = tegra186_gpio_set_value,
+ .get_function = tegra186_gpio_get_function,
+ .xlate = tegra186_gpio_xlate,
+};
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child device
+ * for each port within the controller.
+ */
+static int tegra186_gpio_bind(struct udevice *parent)
+{
+ struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+ struct tegra186_gpio_ctlr_data *ctlr_data =
+ (struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
+ uint32_t *regs;
+ int port, ret;
+
+ /* If this is a child device, there is nothing to do here */
+ if (parent_plat)
+ return 0;
+
+ regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
+ if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ for (port = 0; port < ctlr_data->port_count; port++) {
+ struct tegra186_gpio_platdata *plat;
+ struct udevice *dev;
+
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ plat->name = ctlr_data->ports[port].name;
+ plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
+
+ ret = device_bind(parent, parent->driver, plat->name, plat,
+ -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static int tegra186_gpio_probe(struct udevice *dev)
+{
+ struct tegra186_gpio_platdata *plat = dev->platdata;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ /* Only child devices have ports */
+ if (!plat)
+ return 0;
+
+ uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
+ uc_priv->bank_name = plat->name;
+
+ return 0;
+}
+
+static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
+ {"A", 0x2000},
+ {"B", 0x3000},
+ {"C", 0x3200},
+ {"D", 0x3400},
+ {"E", 0x2200},
+ {"F", 0x2400},
+ {"G", 0x4200},
+ {"H", 0x1000},
+ {"I", 0x0800},
+ {"J", 0x5000},
+ {"K", 0x5200},
+ {"L", 0x1200},
+ {"M", 0x5600},
+ {"N", 0x0000},
+ {"O", 0x0200},
+ {"P", 0x4000},
+ {"Q", 0x0400},
+ {"R", 0x0a00},
+ {"T", 0x0600},
+ {"X", 0x1400},
+ {"Y", 0x1600},
+ {"BB", 0x2600},
+ {"CC", 0x5400},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
+ .ports = tegra186_gpio_main_ports,
+ .port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
+};
+
+static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
+ {"S", 0x0200},
+ {"U", 0x0400},
+ {"V", 0x0800},
+ {"W", 0x0a00},
+ {"Z", 0x0e00},
+ {"AA", 0x0c00},
+ {"EE", 0x0600},
+ {"FF", 0x0000},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
+ .ports = tegra186_gpio_aon_ports,
+ .port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
+};
+
+static const struct udevice_id tegra186_gpio_ids[] = {
+ {
+ .compatible = "nvidia,tegra186-gpio",
+ .data = (ulong)&tegra186_gpio_main_data,
+ },
+ {
+ .compatible = "nvidia,tegra186-gpio-aon",
+ .data = (ulong)&tegra186_gpio_aon_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tegra186_gpio) = {
+ .name = "tegra186_gpio",
+ .id = UCLASS_GPIO,
+ .of_match = tegra186_gpio_ids,
+ .bind = tegra186_gpio_bind,
+ .probe = tegra186_gpio_probe,
+ .ops = &tegra186_gpio_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/tegra186_gpio_priv.h b/drivers/gpio/tegra186_gpio_priv.h
new file mode 100644
index 0000000..9e85a434
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio_priv.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_PRIV_H_
+#define _TEGRA186_GPIO_PRIV_H_
+
+/*
+ * For each GPIO, there are a set of registers than affect it, all packed
+ * back-to-back.
+ */
+#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
+#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
+#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
+#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
+#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
+
+#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
+
+#define TEGRA186_GPIO_INPUT 0x08
+
+#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
+#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
+
+#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
+#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
+
+#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
+
+/*
+ * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
+ * port's address space.
+ */
+#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
+#define TEGRA186_GPIO_PER_GPIO_COUNT 8
+
+/*
+ * Per-port registers are packed immediately following all of a port's
+ * per-GPIO registers.
+ */
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
+
+/*
+ * The registers for multiple ports are packed together back-to-back to form
+ * the overall controller.
+ */
+#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
+
+#endif
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
new file mode 100644
index 0000000..9087512
--- /dev/null
+++ b/drivers/mailbox/Kconfig
@@ -0,0 +1,20 @@
+menu "Mailbox Controller Support"
+
+config DM_MAILBOX
+ bool "Enable mailbox controllers using Driver Model"
+ depends on DM && OF_CONTROL
+ help
+ Enable support for the mailbox driver class. Mailboxes provide the
+ ability to transfer small messages and/or notifications from one
+ CPU to another CPU, or sometimes to dedicated HW modules. They form
+ the basis of a variety of inter-process/inter-CPU communication
+ protocols.
+
+config SANDBOX_MBOX
+ bool "Enable the sandbox mailbox test driver"
+ depends on DM_MAILBOX && SANDBOX
+ help
+ Enable support for a test mailbox implementation, which simply echos
+ back a modified version of any message that is sent.
+
+endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
new file mode 100644
index 0000000..bbae4de
--- /dev/null
+++ b/drivers/mailbox/Makefile
@@ -0,0 +1,7 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
new file mode 100644
index 0000000..73fa328
--- /dev/null
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <mailbox_client.h>
+#include <mailbox_uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
+{
+ return (struct mbox_ops *)dev->driver->ops;
+}
+
+static int mbox_of_xlate_default(struct mbox_chan *chan,
+ struct fdtdec_phandle_args *args)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (args->args_count != 1) {
+ debug("Invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ chan->id = args->args[0];
+
+ return 0;
+}
+
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan)
+{
+ struct fdtdec_phandle_args args;
+ int ret;
+ struct udevice *dev_mbox;
+ struct mbox_ops *ops;
+
+ debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "mboxes", "#mbox-cells", 0,
+ index, &args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node,
+ &dev_mbox);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ops = mbox_dev_ops(dev_mbox);
+
+ chan->dev = dev_mbox;
+ if (ops->of_xlate)
+ ret = ops->of_xlate(chan, &args);
+ else
+ ret = mbox_of_xlate_default(chan, &args);
+ if (ret) {
+ debug("of_xlate() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = ops->request(chan);
+ if (ret) {
+ debug("ops->request() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int mbox_get_by_name(struct udevice *dev, const char *name,
+ struct mbox_chan *chan)
+{
+ int index;
+
+ debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
+
+ index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
+ name);
+ if (index < 0) {
+ debug("fdt_find_string() failed: %d\n", index);
+ return index;
+ }
+
+ return mbox_get_by_index(dev, index, chan);
+}
+
+int mbox_free(struct mbox_chan *chan)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return ops->free(chan);
+}
+
+int mbox_send(struct mbox_chan *chan, const void *data)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ return ops->send(chan, data);
+}
+
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
+{
+ struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+ ulong start_time;
+ int ret;
+
+ debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data,
+ timeout_us);
+
+ start_time = timer_get_us();
+ /*
+ * Account for partial us ticks, but if timeout_us is 0, ensure we
+ * still don't wait at all.
+ */
+ if (timeout_us)
+ timeout_us++;
+
+ for (;;) {
+ ret = ops->recv(chan, data);
+ if (ret != -ENODATA)
+ return ret;
+ if ((timer_get_us() - start_time) >= timeout_us)
+ return -ETIMEDOUT;
+ }
+}
+
+UCLASS_DRIVER(mailbox) = {
+ .id = UCLASS_MAILBOX,
+ .name = "mailbox",
+};
diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c
new file mode 100644
index 0000000..02d161a
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox-test.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_client.h>
+#include <asm/io.h>
+
+struct sandbox_mbox_test {
+ struct mbox_chan chan;
+};
+
+int sandbox_mbox_test_get(struct udevice *dev)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_get_by_name(dev, "test", &sbmt->chan);
+}
+
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_send(&sbmt->chan, &msg);
+}
+
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_recv(&sbmt->chan, msg, 100);
+}
+
+int sandbox_mbox_test_free(struct udevice *dev)
+{
+ struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+ return mbox_free(&sbmt->chan);
+}
+
+static const struct udevice_id sandbox_mbox_test_ids[] = {
+ { .compatible = "sandbox,mbox-test" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_mbox_test) = {
+ .name = "sandbox_mbox_test",
+ .id = UCLASS_MISC,
+ .of_match = sandbox_mbox_test_ids,
+ .priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+};
diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c
new file mode 100644
index 0000000..1b7ac23
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_uclass.h>
+#include <asm/io.h>
+#include <asm/mbox.h>
+
+#define SANDBOX_MBOX_CHANNELS 2
+
+struct sandbox_mbox_chan {
+ bool rx_msg_valid;
+ uint32_t rx_msg;
+};
+
+struct sandbox_mbox {
+ struct sandbox_mbox_chan chans[SANDBOX_MBOX_CHANNELS];
+};
+
+static int sandbox_mbox_request(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (chan->id >= SANDBOX_MBOX_CHANNELS)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int sandbox_mbox_free(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return 0;
+}
+
+static int sandbox_mbox_send(struct mbox_chan *chan, const void *data)
+{
+ struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+ const uint32_t *pmsg = data;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR;
+ sbm->chans[chan->id].rx_msg_valid = true;
+
+ return 0;
+}
+
+static int sandbox_mbox_recv(struct mbox_chan *chan, void *data)
+{
+ struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+ uint32_t *pmsg = data;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ if (!sbm->chans[chan->id].rx_msg_valid)
+ return -ENODATA;
+
+ *pmsg = sbm->chans[chan->id].rx_msg;
+ sbm->chans[chan->id].rx_msg_valid = false;
+
+ return 0;
+}
+
+static int sandbox_mbox_bind(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static int sandbox_mbox_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_mbox_ids[] = {
+ { .compatible = "sandbox,mbox" },
+ { }
+};
+
+struct mbox_ops sandbox_mbox_mbox_ops = {
+ .request = sandbox_mbox_request,
+ .free = sandbox_mbox_free,
+ .send = sandbox_mbox_send,
+ .recv = sandbox_mbox_recv,
+};
+
+U_BOOT_DRIVER(sandbox_mbox) = {
+ .name = "sandbox_mbox",
+ .id = UCLASS_MAILBOX,
+ .of_match = sandbox_mbox_ids,
+ .bind = sandbox_mbox_bind,
+ .probe = sandbox_mbox_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+ .ops = &sandbox_mbox_mbox_ops,
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c40f6b5..2373037 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -121,13 +121,13 @@
help
The I2C address of the PCA9551 LED controller.
-config RESET
- bool "Enable support for reset drivers"
+config SYSRESET
+ bool "Enable support for system reset drivers"
depends on DM
help
- Enable reset drivers which can be used to reset the CPU or board.
- Each driver can provide a reset method which will be called to
- effect a reset. The uclass will try all available drivers when
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
config WINBOND_W83627
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 98704f2..066639b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -27,7 +27,7 @@
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_SANDBOX) += reset_sandbox.o
+obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
ifdef CONFIG_DM_I2C
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
@@ -40,7 +40,7 @@
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
-obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/reset-uclass.c
deleted file mode 100644
index fdb5c6f..0000000
--- a/drivers/misc/reset-uclass.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <reset.h>
-#include <dm.h>
-#include <errno.h>
-#include <regmap.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
-#include <dm/root.h>
-#include <linux/err.h>
-
-int reset_request(struct udevice *dev, enum reset_t type)
-{
- struct reset_ops *ops = reset_get_ops(dev);
-
- if (!ops->request)
- return -ENOSYS;
-
- return ops->request(dev, type);
-}
-
-int reset_walk(enum reset_t type)
-{
- struct udevice *dev;
- int ret = -ENOSYS;
-
- while (ret != -EINPROGRESS && type < RESET_COUNT) {
- for (uclass_first_device(UCLASS_RESET, &dev);
- dev;
- uclass_next_device(&dev)) {
- ret = reset_request(dev, type);
- if (ret == -EINPROGRESS)
- break;
- }
- type++;
- }
-
- return ret;
-}
-
-void reset_walk_halt(enum reset_t type)
-{
- int ret;
-
- ret = reset_walk(type);
-
- /* Wait for the reset to take effect */
- if (ret == -EINPROGRESS)
- mdelay(100);
-
- /* Still no reset? Give up */
- printf("Reset not supported on this platform\n");
- hang();
-}
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr)
-{
- reset_walk_halt(RESET_WARM);
-}
-
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- reset_walk_halt(RESET_WARM);
-
- return 0;
-}
-
-UCLASS_DRIVER(reset) = {
- .id = UCLASS_RESET,
- .name = "reset",
-};
diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/reset_sandbox.c
deleted file mode 100644
index 2691bb0..0000000
--- a/drivers/misc/reset_sandbox.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type)
-{
- struct sandbox_state *state = state_get_current();
-
- switch (type) {
- case RESET_WARM:
- state->last_reset = type;
- break;
- default:
- return -ENOSYS;
- }
- if (!state->reset_allowed[type])
- return -EACCES;
-
- return -EINPROGRESS;
-}
-
-static int sandbox_reset_request(struct udevice *dev, enum reset_t type)
-{
- struct sandbox_state *state = state_get_current();
-
- /*
- * If we have a device tree, the device we created from platform data
- * (see the U_BOOT_DEVICE() declaration below) should not do anything.
- * If we are that device, return an error.
- */
- if (state->fdt_fname && dev->of_offset == -1)
- return -ENODEV;
-
- switch (type) {
- case RESET_COLD:
- state->last_reset = type;
- break;
- case RESET_POWER:
- state->last_reset = type;
- if (!state->reset_allowed[type])
- return -EACCES;
- sandbox_exit();
- break;
- default:
- return -ENOSYS;
- }
- if (!state->reset_allowed[type])
- return -EACCES;
-
- return -EINPROGRESS;
-}
-
-static struct reset_ops sandbox_reset_ops = {
- .request = sandbox_reset_request,
-};
-
-static const struct udevice_id sandbox_reset_ids[] = {
- { .compatible = "sandbox,reset" },
- { }
-};
-
-U_BOOT_DRIVER(reset_sandbox) = {
- .name = "reset_sandbox",
- .id = UCLASS_RESET,
- .of_match = sandbox_reset_ids,
- .ops = &sandbox_reset_ops,
-};
-
-static struct reset_ops sandbox_warm_reset_ops = {
- .request = sandbox_warm_reset_request,
-};
-
-static const struct udevice_id sandbox_warm_reset_ids[] = {
- { .compatible = "sandbox,warm-reset" },
- { }
-};
-
-U_BOOT_DRIVER(warm_reset_sandbox) = {
- .name = "warm_reset_sandbox",
- .id = UCLASS_RESET,
- .of_match = sandbox_warm_reset_ids,
- .ops = &sandbox_warm_reset_ops,
-};
-
-/* This is here in case we don't have a device tree */
-U_BOOT_DEVICE(reset_sandbox_non_fdt) = {
- .name = "reset_sandbox",
-};
diff --git a/drivers/misc/sysreset-uclass.c b/drivers/misc/sysreset-uclass.c
new file mode 100644
index 0000000..3566d17
--- /dev/null
+++ b/drivers/misc/sysreset-uclass.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <sysreset.h>
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <linux/err.h>
+
+int sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct sysreset_ops *ops = sysreset_get_ops(dev);
+
+ if (!ops->request)
+ return -ENOSYS;
+
+ return ops->request(dev, type);
+}
+
+int sysreset_walk(enum sysreset_t type)
+{
+ struct udevice *dev;
+ int ret = -ENOSYS;
+
+ while (ret != -EINPROGRESS && type < SYSRESET_COUNT) {
+ for (uclass_first_device(UCLASS_SYSRESET, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ ret = sysreset_request(dev, type);
+ if (ret == -EINPROGRESS)
+ break;
+ }
+ type++;
+ }
+
+ return ret;
+}
+
+void sysreset_walk_halt(enum sysreset_t type)
+{
+ int ret;
+
+ ret = sysreset_walk(type);
+
+ /* Wait for the reset to take effect */
+ if (ret == -EINPROGRESS)
+ mdelay(100);
+
+ /* Still no reset? Give up */
+ debug("System reset not supported on this platform\n");
+ hang();
+}
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr)
+{
+ sysreset_walk_halt(SYSRESET_WARM);
+}
+
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ sysreset_walk_halt(SYSRESET_WARM);
+
+ return 0;
+}
+
+UCLASS_DRIVER(sysreset) = {
+ .id = UCLASS_SYSRESET,
+ .name = "sysreset",
+};
diff --git a/drivers/misc/sysreset_sandbox.c b/drivers/misc/sysreset_sandbox.c
new file mode 100644
index 0000000..7ae7f38
--- /dev/null
+++ b/drivers/misc/sysreset_sandbox.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_warm_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ struct sandbox_state *state = state_get_current();
+
+ switch (type) {
+ case SYSRESET_WARM:
+ state->last_sysreset = type;
+ break;
+ default:
+ return -ENOSYS;
+ }
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+
+ return -EINPROGRESS;
+}
+
+static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct sandbox_state *state = state_get_current();
+
+ /*
+ * If we have a device tree, the device we created from platform data
+ * (see the U_BOOT_DEVICE() declaration below) should not do anything.
+ * If we are that device, return an error.
+ */
+ if (state->fdt_fname && dev->of_offset == -1)
+ return -ENODEV;
+
+ switch (type) {
+ case SYSRESET_COLD:
+ state->last_sysreset = type;
+ break;
+ case SYSRESET_POWER:
+ state->last_sysreset = type;
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+ sandbox_exit();
+ break;
+ default:
+ return -ENOSYS;
+ }
+ if (!state->sysreset_allowed[type])
+ return -EACCES;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops sandbox_sysreset_ops = {
+ .request = sandbox_sysreset_request,
+};
+
+static const struct udevice_id sandbox_sysreset_ids[] = {
+ { .compatible = "sandbox,reset" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_sandbox) = {
+ .name = "sysreset_sandbox",
+ .id = UCLASS_SYSRESET,
+ .of_match = sandbox_sysreset_ids,
+ .ops = &sandbox_sysreset_ops,
+};
+
+static struct sysreset_ops sandbox_warm_sysreset_ops = {
+ .request = sandbox_warm_sysreset_request,
+};
+
+static const struct udevice_id sandbox_warm_sysreset_ids[] = {
+ { .compatible = "sandbox,warm-reset" },
+ { }
+};
+
+U_BOOT_DRIVER(warm_sysreset_sandbox) = {
+ .name = "warm_sysreset_sandbox",
+ .id = UCLASS_SYSRESET,
+ .of_match = sandbox_warm_sysreset_ids,
+ .ops = &sandbox_warm_sysreset_ops,
+};
+
+/* This is here in case we don't have a device tree */
+U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = {
+ .name = "sysreset_sandbox",
+};
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7329f40..74a2663 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -454,27 +454,40 @@
.init = dwmci_init,
};
-int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk)
{
- host->cfg.name = host->name;
- host->cfg.ops = &dwmci_ops;
- host->cfg.f_min = min_clk;
- host->cfg.f_max = max_clk;
+ cfg->name = name;
+ cfg->ops = &dwmci_ops;
+ cfg->f_min = min_clk;
+ cfg->f_max = max_clk;
- host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->cfg.host_caps = host->caps;
+ cfg->host_caps = caps;
- if (host->buswidth == 8) {
- host->cfg.host_caps |= MMC_MODE_8BIT;
- host->cfg.host_caps &= ~MMC_MODE_4BIT;
+ if (buswidth == 8) {
+ cfg->host_caps |= MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
} else {
- host->cfg.host_caps |= MMC_MODE_4BIT;
- host->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
}
- host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
- host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+#ifdef CONFIG_BLK
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+ dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
+ max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL)
@@ -482,3 +495,4 @@
return 0;
}
+#endif
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3acf9e8..57ad975 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -308,14 +308,10 @@
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
-#ifdef CONFIG_FSL_LAYERSCAPE
unsigned start = 0;
-#else
- unsigned start = (unsigned)data->dest ;
-#endif
+ unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
- unsigned end = start+size ;
#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
@@ -324,7 +320,10 @@
printf("Error found for upper 32 bits\n");
else
start = lower_32_bits(addr);
+#else
+ start = (unsigned)data->dest;
#endif
+ end = start + size;
invalidate_dcache_range(start, end);
}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 74b3d68..94f19ad 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -984,7 +984,7 @@
/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
* to platforms without floating point.
*/
-static const int multipliers[] = {
+static const u8 multipliers[] = {
0, /* reserved */
10,
12,
@@ -1531,15 +1531,6 @@
return 0;
}
-/* not used any more */
-int __deprecated mmc_register(struct mmc *mmc)
-{
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("%s is deprecated! use mmc_create() instead.\n", __func__);
-#endif
- return -1;
-}
-
#ifdef CONFIG_BLK
int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
{
@@ -1566,7 +1557,7 @@
bdesc->removable = 1;
/* setup initial part type */
- bdesc->part_type = mmc->cfg->part_type;
+ bdesc->part_type = cfg->part_type;
mmc->dev = dev;
return 0;
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 27b9e5f..9f0d5c2 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -37,6 +37,19 @@
/* SPL will never write or erase, declare dummies to reduce code size. */
+#ifdef CONFIG_BLK
+static inline unsigned long mmc_berase(struct udevice *dev,
+ lbaint_t start, lbaint_t blkcnt)
+{
+ return 0;
+}
+
+static inline ulong mmc_bwrite(struct udevice *dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
+{
+ return 0;
+}
+#else
static inline unsigned long mmc_berase(struct blk_desc *block_dev,
lbaint_t start, lbaint_t blkcnt)
{
@@ -48,6 +61,7 @@
{
return 0;
}
+#endif
#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 0a261c5..750ab9f 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -18,6 +18,11 @@
DECLARE_GLOBAL_DATA_PTR;
+struct rockchip_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
struct rockchip_dwmmc_priv {
struct udevice *clk;
int periph;
@@ -62,6 +67,9 @@
static int rockchip_dwmmc_probe(struct udevice *dev)
{
+#ifdef CONFIG_BLK
+ struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+#endif
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
@@ -100,16 +108,37 @@
return ret;
}
#endif
+#ifdef CONFIG_BLK
+ dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
+ minmax[1], minmax[0]);
+ host->mmc = &plat->mmc;
+#else
ret = add_dwmci(host, minmax[1], minmax[0]);
if (ret)
return ret;
+#endif
+ host->mmc->priv = &priv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return 0;
}
+static int rockchip_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+ struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
static const struct udevice_id rockchip_dwmmc_ids[] = {
{ .compatible = "rockchip,rk3288-dw-mshc" },
{ }
@@ -120,8 +149,10 @@
.id = UCLASS_MMC,
.of_match = rockchip_dwmmc_ids,
.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+ .bind = rockchip_dwmmc_bind,
.probe = rockchip_dwmmc_probe,
.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
};
#ifdef CONFIG_PWRSEQ
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ef7e615..5c71ab8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -137,7 +137,7 @@
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
unsigned int time = 0, start_addr = 0;
- int mmc_dev = mmc->block_dev.devnum;
+ int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
unsigned start = get_timer(0);
/* Timeout unit - ms */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 573819a..c9d9432 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -11,8 +11,10 @@
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
+#endif
#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
@@ -357,8 +359,12 @@
*/
if (clock == 0)
goto out;
+#ifndef CONFIG_TEGRA186
clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
&div);
+#else
+ div = (20000000 + clock - 1) / clock;
+#endif
debug("div = %d\n", div);
writew(0, &host->reg->clkcon);
@@ -543,7 +549,9 @@
gpio_get_number(&host->cd_gpio));
host->clock = 0;
+#ifndef CONFIG_TEGRA186
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+#endif
if (dm_gpio_is_valid(&host->pwr_gpio))
dm_gpio_set_value(&host->pwr_gpio, 1);
@@ -568,7 +576,11 @@
* (actually 52MHz)
*/
host->cfg.f_min = 375000;
+#ifndef CONFIG_TEGRA186
host->cfg.f_max = 48000000;
+#else
+ host->cfg.f_max = 375000;
+#endif
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
@@ -600,11 +612,13 @@
return -FDT_ERR_NOTFOUND;
}
+#ifndef CONFIG_TEGRA186
host->mmc_id = clock_decode_periph_id(blob, node);
if (host->mmc_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id\n", __func__);
return -FDT_ERR_NOTFOUND;
}
+#endif
/*
* NOTE: mmc->bus_width is determined by mmc.c dynamically.
@@ -624,7 +638,13 @@
*removablep = !fdtdec_get_bool(blob, node, "non-removable");
debug("%s: found controller at %p, width = %d, periph_id = %d\n",
- __func__, host->reg, host->width, host->mmc_id);
+ __func__, host->reg, host->width,
+#ifndef CONFIG_TEGRA186
+ host->mmc_id
+#else
+ -1
+#endif
+ );
return 0;
}
@@ -668,6 +688,16 @@
const void *blob = gd->fdt_blob;
debug("%s entry\n", __func__);
+ /* See if any Tegra186 MMC controllers are present */
+ count = fdtdec_find_aliases_for_id(blob, "sdhci",
+ COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
+ CONFIG_SYS_MMC_MAX_DEVICE);
+ debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
+ if (process_nodes(blob, node_list, count)) {
+ printf("%s: Error processing T186 mmc node(s)!\n", __func__);
+ return;
+ }
+
/* See if any Tegra210 MMC controllers are present */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6fb3718..837d397 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -13,7 +13,6 @@
obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
-obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
@@ -50,7 +49,6 @@
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
-obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
@@ -68,7 +66,6 @@
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
-obj-$(CONFIG_NAND_DOCG4) += docg4.o
else # minimal SPL drivers
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index bf8b2ee..f8770e0 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -16,7 +16,7 @@
#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-nand_info_t nand_info[1];
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -30,12 +30,12 @@
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
/* Emulate NAND_CMD_READOOB */
@@ -45,11 +45,11 @@
}
/* Begin command latch cycle */
- hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_RESET) {
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&nand_info[0]))
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(mtd))
;
return 0;
}
@@ -60,39 +60,39 @@
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&nand_info[0], offs & 0xff,
+ hwctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
if (cmd != NAND_CMD_RNDOUT) {
- hwctrl(&nand_info[0], (page_addr & 0xff),
+ hwctrl(mtd, (page_addr & 0xff),
NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
}
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
/* Latch in address */
- hwctrl(&nand_info[0], NAND_CMD_READSTART,
+ hwctrl(mtd, NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
} else if (cmd == NAND_CMD_RNDOUT) {
- hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
}
return 0;
@@ -100,7 +100,7 @@
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
NAND_CMD_READOOB);
@@ -121,7 +121,7 @@
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -137,15 +137,15 @@
nand_command(block, page, 0, NAND_CMD_READ0);
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], p, eccsize);
+ this->read_buf(mtd, p, eccsize);
nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], oob, eccbytes);
- this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
+ this->read_buf(mtd, oob, eccbytes);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
data_pos += eccsize;
oob_pos += eccbytes;
@@ -164,7 +164,7 @@
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
@@ -173,7 +173,7 @@
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
unsigned int block, lastblock;
- unsigned int page;
+ unsigned int page, page_offset;
/*
* offs has to be aligned to a page address!
@@ -181,6 +181,7 @@
block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+ page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
@@ -189,6 +190,18 @@
*/
while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
nand_read_page(block, page, dst);
+ /*
+ * When offs is not aligned to page address the
+ * extra offset is copied to dst as well. Copy
+ * the image such that its first byte will be
+ * at the dst.
+ */
+ if (unlikely(page_offset)) {
+ memmove(dst, dst + page_offset,
+ CONFIG_SYS_NAND_PAGE_SIZE);
+ dst = (void *)((int)dst - page_offset);
+ page_offset = 0;
+ }
dst += CONFIG_SYS_NAND_PAGE_SIZE;
page++;
}
@@ -210,13 +223,13 @@
/*
* Init board specific nand support
*/
- nand_info[0].priv = &nand_chip;
+ mtd = &nand_chip.mtd;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], 0);
+ nand_chip.select_chip(mtd, 0);
/* NAND chip may require reset after power-on */
nand_command(0, 0, 0, NAND_CMD_RESET);
@@ -226,5 +239,5 @@
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], -1);
+ nand_chip.select_chip(mtd, -1);
}
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 2d73a05..320cbaa 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -230,7 +230,7 @@
static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
{
u8 addrcycles;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
switch (curr_cmd->addr_cycles) {
case NAND_ADDR_CYCL_NONE:
@@ -264,7 +264,7 @@
static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u32 reg_val, i, pktsize, pktnum;
u32 *bufptr = (u32 *)buf;
u32 timeout;
@@ -433,7 +433,8 @@
}
static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const u8 *buf, int oob_required)
+ struct nand_chip *chip, const u8 *buf, int oob_required,
+ int page)
{
u32 reg_val, i, pktsize, pktnum;
const u32 *bufptr = (const u32 *)buf;
@@ -441,7 +442,7 @@
u32 size = mtd->writesize;
u32 rdcount = 0;
u8 column_addr_cycles;
- struct arasan_nand_info *nand = chip->priv;
+ struct arasan_nand_info *nand = nand_get_controller_data(chip);
if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
pktsize = ARASAN_NAND_PKTSIZE_1K;
@@ -944,7 +945,7 @@
static u8 arasan_nand_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u32 size;
u8 val;
struct nand_onfi_params *p;
@@ -976,8 +977,8 @@
int column, int page_addr)
{
u32 i, ret = 0;
- struct nand_chip *chip = mtd->priv;
- struct arasan_nand_info *nand = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct arasan_nand_info *nand = nand_get_controller_data(chip);
curr_cmd = NULL;
writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
@@ -1033,7 +1034,7 @@
{
int found = -1;
u32 regval, eccpos_start, i;
- struct nand_chip *nand_chip = mtd->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
nand_chip->ecc.mode = NAND_ECC_HW;
nand_chip->ecc.hwctl = NULL;
@@ -1058,20 +1059,20 @@
if (found < 0)
return 1;
- regval = ecc_matrix[i].eccaddr |
- (ecc_matrix[i].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
- (ecc_matrix[i].bch << ARASAN_NAND_ECC_BCH_SHIFT);
+ regval = ecc_matrix[found].eccaddr |
+ (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
+ (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
writel(regval, &arasan_nand_base->ecc_reg);
- if (ecc_matrix[i].bch) {
+ if (ecc_matrix[found].bch) {
regval = readl(&arasan_nand_base->memadr_reg2);
regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
- regval |= (ecc_matrix[i].bchval <<
+ regval |= (ecc_matrix[found].bchval <<
ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
writel(regval, &arasan_nand_base->memadr_reg2);
}
- nand_oob.eccbytes = ecc_matrix[i].eccsize;
+ nand_oob.eccbytes = ecc_matrix[found].eccsize;
eccpos_start = mtd->oobsize - nand_oob.eccbytes;
for (i = 0; i < nand_oob.eccbytes; i++)
@@ -1080,9 +1081,9 @@
nand_oob.oobfree[0].offset = 2;
nand_oob.oobfree[0].length = eccpos_start - 2;
- nand_chip->ecc.size = ecc_matrix[i].ecc_codeword_size;
- nand_chip->ecc.strength = ecc_matrix[i].eccbits;
- nand_chip->ecc.bytes = ecc_matrix[i].eccsize;
+ nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
+ nand_chip->ecc.strength = ecc_matrix[found].eccbits;
+ nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
nand_chip->ecc.layout = &nand_oob;
return 0;
@@ -1101,9 +1102,8 @@
}
nand->nand_base = arasan_nand_base;
- mtd = &nand_info[0];
- nand_chip->priv = nand;
- mtd->priv = nand_chip;
+ mtd = nand_to_mtd(nand_chip);
+ nand_set_controller_data(nand_chip, nand);
/* Set the driver entry points for MTD */
nand_chip->cmdfunc = arasan_nand_cmd_function;
@@ -1134,7 +1134,7 @@
goto fail;
}
- if (nand_register(devnum)) {
+ if (nand_register(devnum, mtd)) {
printf("Nand Register Fail\n");
goto fail;
}
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 7cc1de0..75e8307 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -160,8 +160,8 @@
static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
int i;
uint32_t value;
@@ -177,8 +177,8 @@
static void pmecc_substitute(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
int16_t __iomem *alpha_to = host->pmecc_alpha_to;
int16_t __iomem *index_of = host->pmecc_index_of;
int16_t *partial_syn = host->pmecc_partial_syn;
@@ -227,8 +227,8 @@
*/
static void pmecc_get_sigma(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
int16_t *lmu = host->pmecc_lmu;
int16_t *si = host->pmecc_si;
@@ -383,8 +383,8 @@
static int pmecc_err_location(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
const int cap = host->pmecc_corr_cap;
const int num = 2 * cap + 1;
int sector_size = host->pmecc_sector_size;
@@ -437,8 +437,8 @@
static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
int sector_num, int extra_bytes, int err_nbr)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
int i = 0;
int byte_pos, bit_pos, sector_size, pos;
uint32_t tmp;
@@ -483,8 +483,8 @@
static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
u8 *ecc)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
int i, err_nbr, eccbytes;
uint8_t *buf_pos;
@@ -513,7 +513,7 @@
if (err_nbr == -1) {
dev_err(host->dev, "PMECC: Too many errors\n");
mtd->ecc_stats.failed++;
- return -EIO;
+ return -EBADMSG;
} else {
pmecc_correct_data(mtd, buf_pos, ecc, i,
host->pmecc_bytes_per_sector, err_nbr);
@@ -529,7 +529,7 @@
static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
{
- struct atmel_nand_host *host = chip->priv;
+ struct atmel_nand_host *host = nand_get_controller_data(chip);
int eccsize = chip->ecc.size;
uint8_t *oob = chip->oob_poi;
uint32_t *eccpos = chip->ecc.layout->eccpos;
@@ -562,16 +562,16 @@
stat = pmecc_readl(host->pmecc, isr);
if (stat != 0)
if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
- return -EIO;
+ return -EBADMSG;
return 0;
}
static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
struct nand_chip *chip, const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
- struct atmel_nand_host *host = chip->priv;
+ struct atmel_nand_host *host = nand_get_controller_data(chip);
uint32_t *eccpos = chip->ecc.layout->eccpos;
int i, j;
int timeout = PMECC_MAX_TIMEOUT_US;
@@ -615,8 +615,8 @@
static void atmel_pmecc_core_init(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct atmel_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
uint32_t val = 0;
struct nand_ecclayout *ecc_layout;
@@ -808,7 +808,8 @@
struct atmel_nand_host *host;
int cap, sector_size;
- host = nand->priv = &pmecc_host;
+ host = &pmecc_host;
+ nand_set_controller_data(nand, host);
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.calculate = NULL;
@@ -1080,7 +1081,7 @@
static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *isnull)
{
- struct nand_chip *nand_chip = mtd->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
unsigned int ecc_status;
unsigned int ecc_word, ecc_bit;
@@ -1111,7 +1112,7 @@
* We can't correct so many errors */
dev_warn(host->dev, "atmel_nand : multiple errors detected."
" Unable to correct.\n");
- return -EIO;
+ return -EBADMSG;
}
/* if there's a single bit error : we can correct it */
@@ -1207,7 +1208,7 @@
static void at91_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
@@ -1238,17 +1239,17 @@
#ifdef CONFIG_SPL_BUILD
/* The following code is for SPL */
-static nand_info_t mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
static int nand_command(int block, int page, uint32_t offs, u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
if (cmd == NAND_CMD_READOOB) {
@@ -1256,24 +1257,24 @@
cmd = NAND_CMD_READ0;
}
- hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
- hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
- hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+ hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+ hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+ hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
#endif
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
@@ -1281,7 +1282,7 @@
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
@@ -1304,7 +1305,7 @@
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -1317,11 +1318,11 @@
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
if (this->ecc.mode != NAND_ECC_SOFT)
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
}
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
for (i = 0; i < ECCTOTAL; i++)
ecc_code[i] = oob_data[nand_ecc_pos[i]];
@@ -1330,35 +1331,35 @@
p = dst;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
return 0;
}
int spl_nand_erase_one(int block, int page)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
int page_addr;
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Row address */
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE | NAND_CTRL_CHANGE);
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE | NAND_CTRL_CHANGE);
#endif
- hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
nand_deselect();
@@ -1368,10 +1369,10 @@
#else
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
nand_command(block, page, 0, NAND_CMD_READ0);
- atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+ atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
return 0;
}
@@ -1407,7 +1408,7 @@
int at91_nand_wait_ready(struct mtd_info *mtd)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
udelay(this->chip_delay);
@@ -1438,7 +1439,7 @@
#ifdef CONFIG_ATMEL_NAND_HWECC
#ifdef CONFIG_ATMEL_NAND_HW_PMECC
- ret = atmel_pmecc_nand_init_params(nand, &mtd);
+ ret = atmel_pmecc_nand_init_params(nand, mtd);
#endif
#endif
@@ -1447,9 +1448,9 @@
void nand_init(void)
{
- mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
- mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
+ mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+ mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
@@ -1462,13 +1463,13 @@
#endif
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
}
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, -1);
+ nand_chip.select_chip(mtd, -1);
}
#else
@@ -1482,10 +1483,9 @@
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
int ret;
- struct mtd_info *mtd = &nand_info[devnum];
struct nand_chip *nand = &nand_chip[devnum];
+ struct mtd_info *mtd = nand_to_mtd(nand);
- mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
#ifdef CONFIG_NAND_ECC_BCH
@@ -1521,7 +1521,7 @@
ret = nand_scan_tail(mtd);
if (!ret)
- nand_register(devnum);
+ nand_register(devnum, mtd);
return ret;
}
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index a397074..48a8ca7 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -54,7 +54,7 @@
*/
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
const u32 *nand = chip->IO_ADDR_R;
/* Make sure that buf is 32 bit aligned */
@@ -99,7 +99,7 @@
static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
const u32 *nand = chip->IO_ADDR_W;
/* Make sure that buf is 32 bit aligned */
@@ -144,7 +144,7 @@
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
@@ -223,7 +223,7 @@
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
(read_ecc[2] << 16);
u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
@@ -243,7 +243,7 @@
"%d\n", find_byte, find_bit);
return 1;
} else {
- return -1;
+ return -EBADMSG;
}
} else if (!(diff & (diff - 1))) {
/* Single bit ECC error in the ECC itself,
@@ -254,7 +254,7 @@
} else {
/* Uncorrectable error */
MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
- return -1;
+ return -EBADMSG;
}
}
return 0;
@@ -380,10 +380,13 @@
chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
- if (unlikely(raw))
- status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
- else
- status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+ if (unlikely(raw)) {
+ status = chip->ecc.write_page_raw(mtd, chip, buf,
+ oob_required, page);
+ } else {
+ status = chip->ecc.write_page(mtd, chip, buf,
+ oob_required, page);
+ }
if (status < 0) {
ret = status;
@@ -698,7 +701,7 @@
return 0;
} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
val = __raw_readl(&davinci_emif_regs->nanderrval1);
- return -1;
+ return -EBADMSG;
}
numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 5894fcc..601e744 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -48,7 +48,10 @@
* this macro allows us to convert from an MTD structure to our own
* device context (denali) structure.
*/
-#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand)
+static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
+{
+ return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
+}
/*
* These constants are defined by the driver to enable common driver
@@ -865,7 +868,7 @@
* by write_page above.
*/
static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
@@ -889,7 +892,8 @@
* write_page() function above.
*/
static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
@@ -988,7 +992,7 @@
debug(" ECC error cause by erased block\n");
/* false alarm, return the 0xFF */
} else {
- return -EIO;
+ return -EBADMSG;
}
}
memcpy(buf, denali->buf.dma_buf, mtd->writesize);
@@ -1173,13 +1177,13 @@
static int denali_init(struct denali_nand_info *denali)
{
+ struct mtd_info *mtd = nand_to_mtd(&denali->nand);
int ret;
denali_hw_init(denali);
- denali->mtd->name = "denali-nand";
- denali->mtd->owner = THIS_MODULE;
- denali->mtd->priv = &denali->nand;
+ mtd->name = "denali-nand";
+ mtd->owner = THIS_MODULE;
/* register the driver with the NAND core subsystem */
denali->nand.select_chip = denali_select_chip;
@@ -1193,7 +1197,7 @@
* this is the first stage in a two step process to register
* with the nand subsystem
*/
- if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) {
+ if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto fail;
}
@@ -1239,13 +1243,13 @@
nand_oob.eccbytes = denali->nand.ecc.bytes;
denali->nand.ecc.layout = &nand_oob;
- writel(denali->mtd->erasesize / denali->mtd->writesize,
+ writel(mtd->erasesize / mtd->writesize,
denali->flash_reg + PAGES_PER_BLOCK);
writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
denali->flash_reg + DEVICE_WIDTH);
- writel(denali->mtd->writesize,
+ writel(mtd->writesize,
denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
- writel(denali->mtd->oobsize,
+ writel(mtd->oobsize,
denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
writel(1, denali->flash_reg + DEVICES_CONNECTED);
@@ -1258,12 +1262,12 @@
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
- if (nand_scan_tail(denali->mtd)) {
+ if (nand_scan_tail(mtd)) {
ret = -ENXIO;
goto fail;
}
- ret = nand_register(0);
+ ret = nand_register(0, mtd);
fail:
return ret;
@@ -1278,13 +1282,6 @@
return -ENOMEM;
/*
- * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
- * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
- * still provides a "struct mtd_info nand_info" instance.
- */
- denali->mtd = &nand_info[0];
-
- /*
* In the future, these base addresses should be taken from
* Device Tree or platform data.
*/
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index db1457a..0e098bd 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -436,7 +436,6 @@
#define DT 3
struct denali_nand_info {
- struct mtd_info *mtd;
struct nand_chip nand;
int flash_bank; /* currently selected chip */
int status;
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
index 1587413..c693032 100644
--- a/drivers/mtd/nand/denali_spl.c
+++ b/drivers/mtd/nand/denali_spl.c
@@ -41,7 +41,7 @@
if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
debug("Uncorrected ECC detected\n");
- return -EIO;
+ return -EBADMSG;
}
if (intr_status & irq_mask)
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
deleted file mode 100644
index c1c1ff8..0000000
--- a/drivers/mtd/nand/docg4.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/*
- * drivers/mtd/nand/docg4.c
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * mtd nand driver for M-Systems DiskOnChip G4
- *
- * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
- * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
- * Should work on these as well. Let me know!
- *
- * TODO:
- *
- * Mechanism for management of password-protected areas
- *
- * Hamming ecc when reading oob only
- *
- * According to the M-Sys documentation, this device is also available in a
- * "dual-die" configuration having a 256MB capacity, but no mechanism for
- * detecting this variant is documented. Currently this driver assumes 128MB
- * capacity.
- *
- * Support for multiple cascaded devices ("floors"). Not sure which gadgets
- * contain multiple G4s in a cascaded configuration, if any.
- */
-
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <asm/errno.h>
-#include <malloc.h>
-#include <nand.h>
-#include <linux/bch.h>
-#include <linux/bitrev.h>
-#include <linux/mtd/docg4.h>
-
-/*
- * The device has a nop register which M-Sys claims is for the purpose of
- * inserting precise delays. But beware; at least some operations fail if the
- * nop writes are replaced with a generic delay!
- */
-static inline void write_nop(void __iomem *docptr)
-{
- writew(0, docptr + DOC_NOP);
-}
-
-
-static int poll_status(void __iomem *docptr)
-{
- /*
- * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
- * register. Operations known to take a long time (e.g., block erase)
- * should sleep for a while before calling this.
- */
-
- uint8_t flash_status;
-
- /* hardware quirk requires reading twice initially */
- flash_status = readb(docptr + DOC_FLASHCONTROL);
-
- do {
- flash_status = readb(docptr + DOC_FLASHCONTROL);
- } while (!(flash_status & DOC_CTRL_FLASHREADY));
-
- return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
- /* write the four address bytes packed in docg4_addr to the device */
-
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-/*
- * This is a module parameter in the linux kernel version of this driver. It is
- * hard-coded to 'off' for u-boot. This driver uses oob to mark bad blocks.
- * This can be problematic when dealing with data not intended for the mtd/nand
- * subsystem. For example, on boards that boot from the docg4 and use the IPL
- * to load an spl + u-boot image, the blocks containing the image will be
- * reported as "bad" because the oob of the first page of each block contains a
- * magic number that the IPL looks for, which causes the badblock scan to
- * erroneously add them to the bad block table. To erase such a block, use
- * u-boot's 'nand scrub'. scrub is safe for the docg4. The device does have a
- * factory bad block table, but it is read-only, and is used in conjunction with
- * oob bad block markers that are written by mtd/nand when a block is deemed to
- * be bad. To read data from "bad" blocks, use 'read.raw'. Unfortunately,
- * read.raw does not use ecc, which would still work fine on such misidentified
- * bad blocks. TODO: u-boot nand utilities need the ability to ignore bad
- * blocks.
- */
-static const int ignore_badblocks; /* remains false */
-
-struct docg4_priv {
- int status;
- struct {
- unsigned int command;
- int column;
- int page;
- } last_command;
- uint8_t oob_buf[16];
- uint8_t ecc_buf[7];
- int oob_page;
- struct bch_control *bch;
-};
-/*
- * Oob bytes 0 - 6 are available to the user.
- * Byte 7 is hamming ecc for first 7 bytes. Bytes 8 - 14 are hw-generated ecc.
- * Byte 15 (the last) is used by the driver as a "page written" flag.
- */
-static struct nand_ecclayout docg4_oobinfo = {
- .eccbytes = 9,
- .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
- .oobavail = 7,
- .oobfree = { {0, 7} }
-};
-
-static void reset(void __iomem *docptr)
-{
- /* full device reset */
-
- writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE);
- writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
- docptr + DOC_ASICMODECONFIRM);
- write_nop(docptr);
-
- writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
- docptr + DOC_ASICMODE);
- writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
- docptr + DOC_ASICMODECONFIRM);
-
- writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
-
- poll_status(docptr);
-}
-
-static void docg4_select_chip(struct mtd_info *mtd, int chip)
-{
- /*
- * Select among multiple cascaded chips ("floors"). Multiple floors are
- * not yet supported, so the only valid non-negative value is 0.
- */
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-
- if (chip < 0)
- return; /* deselected */
-
- if (chip > 0)
- printf("multiple floors currently unsupported\n");
-
- writew(0, docptr + DOC_DEVICESELECT);
-}
-
-static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
-{
- /* read the 7 hw-generated ecc bytes */
-
- int i;
- for (i = 0; i < 7; i++) { /* hw quirk; read twice */
- ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
- ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
- }
-}
-
-static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
- /*
- * Called after a page read when hardware reports bitflips.
- * Up to four bitflips can be corrected.
- */
-
- struct nand_chip *nand = mtd->priv;
- struct docg4_priv *doc = nand->priv;
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- int i, numerrs;
- unsigned int errpos[4];
- const uint8_t blank_read_hwecc[8] = {
- 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
-
- read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
-
- /* check if read error is due to a blank page */
- if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
- return 0; /* yes */
-
- /* skip additional check of "written flag" if ignore_badblocks */
- if (!ignore_badblocks) {
- /*
- * If the hw ecc bytes are not those of a blank page, there's
- * still a chance that the page is blank, but was read with
- * errors. Check the "written flag" in last oob byte, which
- * is set to zero when a page is written. If more than half
- * the bits are set, assume a blank page. Unfortunately, the
- * bit flips(s) are not reported in stats.
- */
-
- if (doc->oob_buf[15]) {
- int bit, numsetbits = 0;
- unsigned long written_flag = doc->oob_buf[15];
-
- for (bit = 0; bit < 8; bit++) {
- if (written_flag & 0x01)
- numsetbits++;
- written_flag >>= 1;
- }
- if (numsetbits > 4) { /* assume blank */
- printf("errors in blank page at offset %08x\n",
- page * DOCG4_PAGE_SIZE);
- return 0;
- }
- }
- }
-
- /*
- * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
- * algorithm is used to decode this. However the hw operates on page
- * data in a bit order that is the reverse of that of the bch alg,
- * requiring that the bits be reversed on the result. Thanks to Ivan
- * Djelic for his analysis!
- */
- for (i = 0; i < 7; i++)
- doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
-
- numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
- doc->ecc_buf, NULL, errpos);
-
- if (numerrs == -EBADMSG) {
- printf("uncorrectable errors at offset %08x\n",
- page * DOCG4_PAGE_SIZE);
- return -EBADMSG;
- }
-
- BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
-
- /* undo last step in BCH alg (modulo mirroring not needed) */
- for (i = 0; i < numerrs; i++)
- errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
-
- /* fix the errors */
- for (i = 0; i < numerrs; i++) {
- /* ignore if error within oob ecc bytes */
- if (errpos[i] > DOCG4_USERDATA_LEN * 8)
- continue;
-
- /* if error within oob area preceeding ecc bytes... */
- if (errpos[i] > DOCG4_PAGE_SIZE * 8)
- __change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
- (unsigned long *)doc->oob_buf);
-
- else /* error in page data */
- __change_bit(errpos[i], (unsigned long *)buf);
- }
-
- printf("%d error(s) corrected at offset %08x\n",
- numerrs, page * DOCG4_PAGE_SIZE);
-
- return numerrs;
-}
-
-static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr)
-{
- /*
- * This apparently checks the status of programming. Done after an
- * erasure, and after page data is written. On error, the status is
- * saved, to be later retrieved by the nand infrastructure code.
- */
-
- /* status is read from the I/O reg */
- uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
- uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
- uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n",
- __func__, status1, status2, status3);
-
- if (status1 != DOCG4_PROGSTATUS_GOOD ||
- status2 != DOCG4_PROGSTATUS_GOOD_2 ||
- status3 != DOCG4_PROGSTATUS_GOOD_2) {
- doc->status = NAND_STATUS_FAIL;
- printf("read_progstatus failed: %02x, %02x, %02x\n",
- status1, status2, status3);
- return -EIO;
- }
- return 0;
-}
-
-static int pageprog(struct mtd_info *mtd)
-{
- /*
- * Final step in writing a page. Writes the contents of its
- * internal buffer out to the flash array, or some such.
- */
-
- struct nand_chip *nand = mtd->priv;
- struct docg4_priv *doc = nand->priv;
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- int retval = 0;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__);
-
- writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
- writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
-
- /* Just busy-wait; usleep_range() slows things down noticeably. */
- poll_status(docptr);
-
- writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
- writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
- writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- retval = read_progstatus(doc, docptr);
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
- poll_status(docptr);
- write_nop(docptr);
-
- return retval;
-}
-
-static void sequence_reset(void __iomem *docptr)
-{
- /* common starting sequence for all operations */
-
- writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
- writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
- writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
- poll_status(docptr);
- write_nop(docptr);
-}
-
-static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
- /* first step in reading a page */
-
- sequence_reset(docptr);
-
- writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
- writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
-
- write_addr(docptr, docg4_addr);
-
- write_nop(docptr);
- writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
-
- poll_status(docptr);
-}
-
-static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
- /* first step in writing a page */
-
- sequence_reset(docptr);
- writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
- writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_addr(docptr, docg4_addr);
- write_nop(docptr);
- write_nop(docptr);
- poll_status(docptr);
-}
-
-static uint32_t mtd_to_docg4_address(int page, int column)
-{
- /*
- * Convert mtd address to format used by the device, 32 bit packed.
- *
- * Some notes on G4 addressing... The M-Sys documentation on this device
- * claims that pages are 2K in length, and indeed, the format of the
- * address used by the device reflects that. But within each page are
- * four 512 byte "sub-pages", each with its own oob data that is
- * read/written immediately after the 512 bytes of page data. This oob
- * data contains the ecc bytes for the preceeding 512 bytes.
- *
- * Rather than tell the mtd nand infrastructure that page size is 2k,
- * with four sub-pages each, we engage in a little subterfuge and tell
- * the infrastructure code that pages are 512 bytes in size. This is
- * done because during the course of reverse-engineering the device, I
- * never observed an instance where an entire 2K "page" was read or
- * written as a unit. Each "sub-page" is always addressed individually,
- * its data read/written, and ecc handled before the next "sub-page" is
- * addressed.
- *
- * This requires us to convert addresses passed by the mtd nand
- * infrastructure code to those used by the device.
- *
- * The address that is written to the device consists of four bytes: the
- * first two are the 2k page number, and the second is the index into
- * the page. The index is in terms of 16-bit half-words and includes
- * the preceeding oob data, so e.g., the index into the second
- * "sub-page" is 0x108, and the full device address of the start of mtd
- * page 0x201 is 0x00800108.
- */
- int g4_page = page / 4; /* device's 2K page */
- int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
- return (g4_page << 16) | g4_index; /* pack */
-}
-
-static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
- int page_addr)
-{
- /* handle standard nand commands */
-
- struct nand_chip *nand = mtd->priv;
- struct docg4_priv *doc = nand->priv;
- uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n",
- __func__, command, page_addr, column);
-
- /*
- * Save the command and its arguments. This enables emulation of
- * standard flash devices, and also some optimizations.
- */
- doc->last_command.command = command;
- doc->last_command.column = column;
- doc->last_command.page = page_addr;
-
- switch (command) {
- case NAND_CMD_RESET:
- reset(CONFIG_SYS_NAND_BASE);
- break;
-
- case NAND_CMD_READ0:
- read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
- break;
-
- case NAND_CMD_STATUS:
- /* next call to read_byte() will expect a status */
- break;
-
- case NAND_CMD_SEQIN:
- write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-
- /* hack for deferred write of oob bytes */
- if (doc->oob_page == page_addr)
- memcpy(nand->oob_poi, doc->oob_buf, 16);
- break;
-
- case NAND_CMD_PAGEPROG:
- pageprog(mtd);
- break;
-
- /* we don't expect these, based on review of nand_base.c */
- case NAND_CMD_READOOB:
- case NAND_CMD_READID:
- case NAND_CMD_ERASE1:
- case NAND_CMD_ERASE2:
- printf("docg4_command: unexpected nand command 0x%x\n",
- command);
- break;
- }
-}
-
-static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *nand = mtd->priv;
- uint16_t *p = (uint16_t *)buf;
- len >>= 1;
-
- for (i = 0; i < len; i++)
- p[i] = readw(nand->IO_ADDR_R);
-}
-
-static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
- int page)
-{
- struct docg4_priv *doc = nand->priv;
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- uint16_t status;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page);
-
- /*
- * Oob bytes are read as part of a normal page read. If the previous
- * nand command was a read of the page whose oob is now being read, just
- * copy the oob bytes that we saved in a local buffer and avoid a
- * separate oob read.
- */
- if (doc->last_command.command == NAND_CMD_READ0 &&
- doc->last_command.page == page) {
- memcpy(nand->oob_poi, doc->oob_buf, 16);
- return 0;
- }
-
- /*
- * Separate read of oob data only.
- */
- docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
-
- writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- /* the 1st byte from the I/O reg is a status; the rest is oob data */
- status = readw(docptr + DOC_IOSPACE_DATA);
- if (status & DOCG4_READ_ERROR) {
- printf("docg4_read_oob failed: status = 0x%02x\n", status);
- return -EIO;
- }
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status);
-
- docg4_read_buf(mtd, nand->oob_poi, 16);
-
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
-
- return 0;
-}
-
-static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
- int page)
-{
- /*
- * Writing oob-only is not really supported, because MLC nand must write
- * oob bytes at the same time as page data. Nonetheless, we save the
- * oob buffer contents here, and then write it along with the page data
- * if the same page is subsequently written. This allows user space
- * utilities that write the oob data prior to the page data to work
- * (e.g., nandwrite). The disdvantage is that, if the intention was to
- * write oob only, the operation is quietly ignored. Also, oob can get
- * corrupted if two concurrent processes are running nandwrite.
- */
-
- /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
- struct docg4_priv *doc = nand->priv;
- doc->oob_page = page;
- memcpy(doc->oob_buf, nand->oob_poi, 16);
- return 0;
-}
-
-static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
- /* only called when module_param ignore_badblocks is set */
- return 0;
-}
-
-static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *nand = mtd->priv;
- uint16_t *p = (uint16_t *)buf;
- len >>= 1;
-
- for (i = 0; i < len; i++)
- writew(p[i], nand->IO_ADDR_W);
-}
-
-static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
- const uint8_t *buf, int use_ecc)
-{
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- uint8_t ecc_buf[8];
-
- writew(DOC_ECCCONF0_ECC_ENABLE |
- DOC_ECCCONF0_UNKNOWN |
- DOCG4_BCH_SIZE,
- docptr + DOC_ECCCONF0);
- write_nop(docptr);
-
- /* write the page data */
- docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
-
- /* oob bytes 0 through 5 are written to I/O reg */
- docg4_write_buf16(mtd, nand->oob_poi, 6);
-
- /* oob byte 6 written to a separate reg */
- writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
-
- write_nop(docptr);
- write_nop(docptr);
-
- /* write hw-generated ecc bytes to oob */
- if (likely(use_ecc)) {
- /* oob byte 7 is hamming code */
- uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
- hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
- writew(hamming, docptr + DOCG4_OOB_6_7);
- write_nop(docptr);
-
- /* read the 7 bch bytes from ecc regs */
- read_hw_ecc(docptr, ecc_buf);
- ecc_buf[7] = 0; /* clear the "page written" flag */
- }
-
- /* write user-supplied bytes to oob */
- else {
- writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
- write_nop(docptr);
- memcpy(ecc_buf, &nand->oob_poi[8], 8);
- }
-
- docg4_write_buf16(mtd, ecc_buf, 8);
- write_nop(docptr);
- write_nop(docptr);
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
-
- return 0;
-}
-
-static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
- const uint8_t *buf, int oob_required)
-{
- return write_page(mtd, nand, buf, 0);
-}
-
-static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
- const uint8_t *buf, int oob_required)
-{
- return write_page(mtd, nand, buf, 1);
-}
-
-static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
- uint8_t *buf, int page, int use_ecc)
-{
- struct docg4_priv *doc = nand->priv;
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- uint16_t status, edc_err, *buf16;
-
- writew(DOC_ECCCONF0_READ_MODE |
- DOC_ECCCONF0_ECC_ENABLE |
- DOC_ECCCONF0_UNKNOWN |
- DOCG4_BCH_SIZE,
- docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- /* the 1st byte from the I/O reg is a status; the rest is page data */
- status = readw(docptr + DOC_IOSPACE_DATA);
- if (status & DOCG4_READ_ERROR) {
- printf("docg4_read_page: bad status: 0x%02x\n", status);
- writew(0, docptr + DOC_DATAEND);
- return -EIO;
- }
-
- docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
-
- /* first 14 oob bytes read from I/O reg */
- docg4_read_buf(mtd, nand->oob_poi, 14);
-
- /* last 2 read from another reg */
- buf16 = (uint16_t *)(nand->oob_poi + 14);
- *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
-
- /*
- * Diskonchips read oob immediately after a page read. Mtd
- * infrastructure issues a separate command for reading oob after the
- * page is read. So we save the oob bytes in a local buffer and just
- * copy it if the next command reads oob from the same page.
- */
- memcpy(doc->oob_buf, nand->oob_poi, 16);
-
- write_nop(docptr);
-
- if (likely(use_ecc)) {
- /* read the register that tells us if bitflip(s) detected */
- edc_err = readw(docptr + DOC_ECCCONF1);
- edc_err = readw(docptr + DOC_ECCCONF1);
-
- /* If bitflips are reported, attempt to correct with ecc */
- if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
- int bits_corrected = correct_data(mtd, buf, page);
- if (bits_corrected == -EBADMSG)
- mtd->ecc_stats.failed++;
- else
- mtd->ecc_stats.corrected += bits_corrected;
- }
- }
-
- writew(0, docptr + DOC_DATAEND);
- return 0;
-}
-
-
-static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
- uint8_t *buf, int oob_required, int page)
-{
- return read_page(mtd, nand, buf, page, 0);
-}
-
-static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
- uint8_t *buf, int oob_required, int page)
-{
- return read_page(mtd, nand, buf, page, 1);
-}
-
-static int docg4_erase_block(struct mtd_info *mtd, int page)
-{
- struct nand_chip *nand = mtd->priv;
- struct docg4_priv *doc = nand->priv;
- void __iomem *docptr = CONFIG_SYS_NAND_BASE;
- uint16_t g4_page;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page);
-
- sequence_reset(docptr);
-
- writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
- writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
-
- /* only 2 bytes of address are written to specify erase block */
- g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
- writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
- g4_page >>= 8;
- writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
- write_nop(docptr);
-
- /* start the erasure */
- writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
-
- poll_status(docptr);
- writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
- writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
- writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- read_progstatus(doc, docptr);
-
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
- poll_status(docptr);
- write_nop(docptr);
-
- return nand->waitfunc(mtd, nand);
-}
-
-static int read_factory_bbt(struct mtd_info *mtd)
-{
- /*
- * The device contains a read-only factory bad block table. Read it and
- * update the memory-based bbt accordingly.
- */
-
- struct nand_chip *nand = mtd->priv;
- uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
- uint8_t *buf;
- int i, block, status;
-
- buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
- if (buf == NULL)
- return -ENOMEM;
-
- read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
- status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
- if (status)
- goto exit;
-
- /*
- * If no memory-based bbt was created, exit. This will happen if module
- * parameter ignore_badblocks is set. Then why even call this function?
- * For an unknown reason, block erase always fails if it's the first
- * operation after device power-up. The above read ensures it never is.
- * Ugly, I know.
- */
- if (nand->bbt == NULL) /* no memory-based bbt */
- goto exit;
-
- /*
- * Parse factory bbt and update memory-based bbt. Factory bbt format is
- * simple: one bit per block, block numbers increase left to right (msb
- * to lsb). Bit clear means bad block.
- */
- for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
- int bitnum;
- uint8_t mask;
- for (bitnum = 0, mask = 0x80;
- bitnum < 8; bitnum++, mask >>= 1) {
- if (!(buf[i] & mask)) {
- int badblock = block + bitnum;
- nand->bbt[badblock / 4] |=
- 0x03 << ((badblock % 4) * 2);
- mtd->ecc_stats.badblocks++;
- printf("factory-marked bad block: %d\n",
- badblock);
- }
- }
- }
- exit:
- kfree(buf);
- return status;
-}
-
-static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
- /*
- * Mark a block as bad. Bad blocks are marked in the oob area of the
- * first page of the block. The default scan_bbt() in the nand
- * infrastructure code works fine for building the memory-based bbt
- * during initialization, as does the nand infrastructure function that
- * checks if a block is bad by reading the bbt. This function replaces
- * the nand default because writes to oob-only are not supported.
- */
-
- int ret, i;
- uint8_t *buf;
- struct nand_chip *nand = mtd->priv;
- struct nand_bbt_descr *bbtd = nand->badblock_pattern;
- int block = (int)(ofs >> nand->bbt_erase_shift);
- int page = (int)(ofs >> nand->page_shift);
- uint32_t g4_addr = mtd_to_docg4_address(page, 0);
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs);
-
- if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
- printf("%s: ofs %llx not start of block!\n",
- __func__, ofs);
-
- /* allocate blank buffer for page data */
- buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
- if (buf == NULL)
- return -ENOMEM;
-
- /* update bbt in memory */
- nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
-
- /* write bit-wise negation of pattern to oob buffer */
- memset(nand->oob_poi, 0xff, mtd->oobsize);
- for (i = 0; i < bbtd->len; i++)
- nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
-
- /* write first page of block */
- write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
- docg4_write_page(mtd, nand, buf, 1);
- ret = pageprog(mtd);
- if (!ret)
- mtd->ecc_stats.badblocks++;
-
- kfree(buf);
-
- return ret;
-}
-
-static uint8_t docg4_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *nand = mtd->priv;
- struct docg4_priv *doc = nand->priv;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
-
- if (doc->last_command.command == NAND_CMD_STATUS) {
- int status;
-
- /*
- * Previous nand command was status request, so nand
- * infrastructure code expects to read the status here. If an
- * error occurred in a previous operation, report it.
- */
- doc->last_command.command = 0;
-
- if (doc->status) {
- status = doc->status;
- doc->status = 0;
- }
-
- /* why is NAND_STATUS_WP inverse logic?? */
- else
- status = NAND_STATUS_WP | NAND_STATUS_READY;
-
- return status;
- }
-
- printf("unexpectd call to read_byte()\n");
-
- return 0;
-}
-
-static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
-{
- struct docg4_priv *doc = nand->priv;
- int status = NAND_STATUS_WP; /* inverse logic?? */
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__);
-
- /* report any previously unreported error */
- if (doc->status) {
- status |= doc->status;
- doc->status = 0;
- return status;
- }
-
- status |= poll_status(CONFIG_SYS_NAND_BASE);
- return status;
-}
-
-int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum)
-{
- uint16_t id1, id2;
- struct docg4_priv *docg4;
- int retval;
-
- docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL);
- if (!docg4)
- return -1;
-
- mtd->priv = nand;
- nand->priv = docg4;
-
- /* These must be initialized here because the docg4 is non-standard
- * and doesn't produce an id that the nand code can use to look up
- * these values (nand_scan_ident() not called).
- */
- mtd->size = DOCG4_CHIP_SIZE;
- mtd->name = "Msys_Diskonchip_G4";
- mtd->writesize = DOCG4_PAGE_SIZE;
- mtd->erasesize = DOCG4_BLOCK_SIZE;
- mtd->oobsize = DOCG4_OOB_SIZE;
-
- nand->IO_ADDR_R =
- (void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA;
- nand->IO_ADDR_W = nand->IO_ADDR_R;
- nand->chipsize = DOCG4_CHIP_SIZE;
- nand->chip_shift = DOCG4_CHIP_SHIFT;
- nand->bbt_erase_shift = DOCG4_ERASE_SHIFT;
- nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
- nand->chip_delay = 20;
- nand->page_shift = DOCG4_PAGE_SHIFT;
- nand->pagemask = 0x3ffff;
- nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
- nand->badblockbits = 8;
- nand->ecc.layout = &docg4_oobinfo;
- nand->ecc.mode = NAND_ECC_HW_SYNDROME;
- nand->ecc.size = DOCG4_PAGE_SIZE;
- nand->ecc.prepad = 8;
- nand->ecc.bytes = 8;
- nand->ecc.strength = DOCG4_T;
- nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
- nand->controller = &nand->hwcontrol;
-
- /* methods */
- nand->cmdfunc = docg4_command;
- nand->waitfunc = docg4_wait;
- nand->select_chip = docg4_select_chip;
- nand->read_byte = docg4_read_byte;
- nand->block_markbad = docg4_block_markbad;
- nand->read_buf = docg4_read_buf;
- nand->write_buf = docg4_write_buf16;
- nand->scan_bbt = nand_default_bbt;
- nand->erase = docg4_erase_block;
- nand->ecc.read_page = docg4_read_page;
- nand->ecc.write_page = docg4_write_page;
- nand->ecc.read_page_raw = docg4_read_page_raw;
- nand->ecc.write_page_raw = docg4_write_page_raw;
- nand->ecc.read_oob = docg4_read_oob;
- nand->ecc.write_oob = docg4_write_oob;
-
- /*
- * The way the nand infrastructure code is written, a memory-based bbt
- * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
- * nand->block_bad() is used. So when ignoring bad blocks, we skip the
- * scan and define a dummy block_bad() which always returns 0.
- */
- if (ignore_badblocks) {
- nand->options |= NAND_SKIP_BBTSCAN;
- nand->block_bad = docg4_block_neverbad;
- }
-
- reset(CONFIG_SYS_NAND_BASE);
-
- /* check for presence of g4 chip by reading id registers */
- id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID);
- id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
- id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV);
- id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
- if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE)
- return -1;
-
- /* initialize bch algorithm */
- docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
- if (docg4->bch == NULL)
- return -1;
-
- retval = nand_scan_tail(mtd);
- if (retval)
- return -1;
-
- /*
- * Scan for bad blocks and create bbt here, then add the factory-marked
- * bad blocks to the bbt.
- */
- nand->scan_bbt(mtd);
- nand->options |= NAND_BBT_SCANNED;
- retval = read_factory_bbt(mtd);
- if (retval)
- return -1;
-
- retval = nand_register(devnum);
- if (retval)
- return -1;
-
- return 0;
-}
diff --git a/drivers/mtd/nand/docg4_spl.c b/drivers/mtd/nand/docg4_spl.c
deleted file mode 100644
index 351b75a..0000000
--- a/drivers/mtd/nand/docg4_spl.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * SPL driver for Diskonchip G4 nand flash
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * This driver basically mimics the load functionality of a typical IPL (initial
- * program loader) resident in the 2k NOR-like region of the docg4 that is
- * mapped to the reset vector. It allows the u-boot SPL to continue loading if
- * the IPL loads a fixed number of flash blocks that is insufficient to contain
- * the entire u-boot image. In this case, a concatenated spl + u-boot image is
- * written at the flash offset from which the IPL loads an image, and when the
- * IPL jumps to the SPL, the SPL resumes loading where the IPL left off. See
- * the palmtreo680 for an example.
- *
- * This driver assumes that the data was written to the flash using the device's
- * "reliable" mode, and also assumes that each 512 byte page is stored
- * redundantly in the subsequent page. This storage format is likely to be used
- * by all boards that boot from the docg4. The format compensates for the lack
- * of ecc in the IPL.
- *
- * Reliable mode reduces the capacity of a block by half, and the redundant
- * pages reduce it by half again. As a result, the normal 256k capacity of a
- * block is reduced to 64k for the purposes of the IPL/SPL.
- */
-
-#include <asm/io.h>
-#include <linux/mtd/docg4.h>
-
-/* forward declarations */
-static inline void write_nop(void __iomem *docptr);
-static int poll_status(void __iomem *docptr);
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
- void __iomem *docptr);
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
-
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
-{
- void *load_addr = dst;
- uint32_t flash_offset = offs;
- const unsigned int block_count =
- (size + DOCG4_BLOCK_CAPACITY_SPL - 1)
- / DOCG4_BLOCK_CAPACITY_SPL;
- int i;
-
- for (i = 0; i < block_count; i++) {
- int ret = docg4_load_block_reliable(flash_offset, load_addr);
- if (ret)
- return ret;
- load_addr += DOCG4_BLOCK_CAPACITY_SPL;
- flash_offset += DOCG4_BLOCK_SIZE;
- }
- return 0;
-}
-
-static inline void write_nop(void __iomem *docptr)
-{
- writew(0, docptr + DOC_NOP);
-}
-
-static int poll_status(void __iomem *docptr)
-{
- /*
- * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
- * register. Operations known to take a long time (e.g., block erase)
- * should sleep for a while before calling this.
- */
-
- uint8_t flash_status;
-
- /* hardware quirk requires reading twice initially */
- flash_status = readb(docptr + DOC_FLASHCONTROL);
-
- do {
- flash_status = readb(docptr + DOC_FLASHCONTROL);
- } while (!(flash_status & DOC_CTRL_FLASHREADY));
-
- return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
- /* write the four address bytes packed in docg4_addr to the device */
-
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
- docg4_addr >>= 8;
- writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
- void __iomem *docptr)
-{
- writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
- writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
- write_nop(docptr);
-}
-
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
-{
- void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
- unsigned int g4_page = flash_offset >> 11; /* 2k page */
- const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
- int g4_index = 0;
- uint16_t flash_status;
- uint16_t *buf;
-
- /* flash_offset must be aligned to the start of a block */
- if (flash_offset & 0x3ffff)
- return -1;
-
- writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
- writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
- poll_status(docptr);
- write_nop(docptr);
- writew(0x45, docptr + DOC_FLASHSEQUENCE);
- writew(0xa3, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- writew(0x22, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
-
- /* read 1st 4 oob bytes of first subpage of block */
- address_sequence(g4_page, 0x0100, docptr); /* index at oob */
- write_nop(docptr);
- flash_status = readw(docptr + DOC_FLASHCONTROL);
- flash_status = readw(docptr + DOC_FLASHCONTROL);
- if (flash_status & 0x06) /* sequence or protection errors */
- return -1;
- writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
- poll_status(docptr);
- writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- /*
- * Here we read the first four oob bytes of the first page of the block.
- * The IPL on the palmtreo680 requires that this contain a 32 bit magic
- * number, or the load aborts. We'll ignore it.
- */
- readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
- readw(docptr + 0x103c); /* lower 16 bits of magic number */
- readw(docptr + DOCG4_MYSTERY_REG); /* upper 16 bits of magic number */
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
- write_nop(docptr);
-
- /* load contents of block to memory */
- buf = (uint16_t *)dest_addr;
- do {
- int i;
-
- address_sequence(g4_page, g4_index, docptr);
- writew(DOCG4_CMD_READ2,
- docptr + DOC_FLASHCOMMAND);
- write_nop(docptr);
- write_nop(docptr);
- poll_status(docptr);
- writew(DOC_ECCCONF0_READ_MODE |
- DOC_ECCCONF0_ECC_ENABLE |
- DOCG4_BCH_SIZE,
- docptr + DOC_ECCCONF0);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
- write_nop(docptr);
-
- /* read the 512 bytes of page data, 2 bytes at a time */
- readw(docptr + 0x103c); /* hw quirk */
- for (i = 0; i < 256; i++)
- *buf++ = readw(docptr + 0x103c);
-
- /* read oob, but discard it */
- for (i = 0; i < 7; i++)
- readw(docptr + 0x103c);
- readw(docptr + DOCG4_OOB_6_7);
- readw(docptr + DOCG4_OOB_6_7);
-
- writew(0, docptr + DOC_DATAEND);
- write_nop(docptr);
- write_nop(docptr);
-
- if (!(g4_index & 0x100)) {
- /* not redundant subpage read; check for ecc error */
- write_nop(docptr);
- flash_status = readw(docptr + DOC_ECCCONF1);
- flash_status = readw(docptr + DOC_ECCCONF1);
- if (flash_status & 0x80) { /* ecc error */
- g4_index += 0x108; /* read redundant subpage */
- buf -= 256; /* back up ram ptr */
- continue;
- } else /* no ecc error */
- g4_index += 0x210; /* skip redundant subpage */
- } else /* redundant page was just read; skip ecc error check */
- g4_index += 0x108;
-
- if (g4_index == 0x420) { /* finished with 2k page */
- g4_index = 0;
- g4_page += 2; /* odd-numbered 2k pages skipped */
- }
-
- } while (g4_page != last_g4_page); /* while still on same block */
-
- return 0;
-}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index d457d53..f621f14 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -154,8 +154,8 @@
*/
static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbc_t *lbc = ctrl->regs;
int buf_num;
@@ -194,8 +194,8 @@
*/
static int fsl_elbc_run_command(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbc_t *lbc = ctrl->regs;
u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -246,7 +246,7 @@
static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
{
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbc_t *lbc = ctrl->regs;
@@ -279,8 +279,8 @@
static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbc_t *lbc = ctrl->regs;
@@ -489,8 +489,8 @@
*/
static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
unsigned int bufsize = mtd->writesize + mtd->oobsize;
@@ -526,8 +526,8 @@
*/
static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
/* If there are still bytes in the FCM, then use the next byte. */
@@ -543,8 +543,8 @@
*/
static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
int avail;
@@ -566,7 +566,7 @@
*/
static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
- struct fsl_elbc_mtd *priv = chip->priv;
+ struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbc_t *lbc = ctrl->regs;
@@ -611,7 +611,8 @@
* waitfunc.
*/
static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -626,7 +627,7 @@
*/
static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, uint32_t data_len,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required, int page)
{
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -656,7 +657,7 @@
static int fsl_elbc_chip_init(int devnum, u8 *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *nand;
struct fsl_elbc_mtd *priv;
uint32_t br = 0, or = 0;
@@ -697,7 +698,7 @@
}
nand = &priv->chip;
- mtd->priv = nand;
+ mtd = nand_to_mtd(nand);
elbc_ctrl->chips[priv->bank] = priv;
@@ -719,7 +720,7 @@
nand->bbt_options = NAND_BBT_USE_FLASH;
nand->controller = &elbc_ctrl->controller;
- nand->priv = priv;
+ nand_set_controller_data(nand, priv);
nand->ecc.read_page = fsl_elbc_read_page;
nand->ecc.write_page = fsl_elbc_write_page;
@@ -787,7 +788,7 @@
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, mtd);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 975b0d4..7001cbd 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -222,8 +222,8 @@
*/
static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
int buf_num;
@@ -247,8 +247,8 @@
static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
unsigned int bufnum)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
u32 __iomem *main = (u32 *)addr;
u8 __iomem *oob = addr + mtd->writesize;
@@ -286,8 +286,8 @@
*/
static int fsl_ifc_run_command(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -367,7 +367,7 @@
int oob,
struct mtd_info *mtd)
{
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
@@ -404,8 +404,8 @@
static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
@@ -607,8 +607,8 @@
*/
static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
unsigned int bufsize = mtd->writesize + mtd->oobsize;
@@ -635,8 +635,8 @@
*/
static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
unsigned int offset;
@@ -659,8 +659,8 @@
*/
static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
uint16_t data;
@@ -683,8 +683,8 @@
*/
static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
int avail;
@@ -706,7 +706,7 @@
*/
static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
u32 nand_fsr;
@@ -739,7 +739,7 @@
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- struct fsl_ifc_mtd *priv = chip->priv;
+ struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
fsl_ifc_read_buf(mtd, buf, mtd->writesize);
@@ -755,7 +755,7 @@
* waitfunc.
*/
static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required, int page)
{
fsl_ifc_write_buf(mtd, buf, mtd->writesize);
fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -880,7 +880,7 @@
static int fsl_ifc_chip_init(int devnum, u8 *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *nand;
struct fsl_ifc_mtd *priv;
struct nand_ecclayout *layout;
@@ -925,7 +925,7 @@
}
nand = &priv->chip;
- mtd->priv = nand;
+ mtd = nand_to_mtd(nand);
ifc_ctrl->chips[priv->bank] = priv;
@@ -954,7 +954,7 @@
}
nand->controller = &ifc_ctrl->controller;
- nand->priv = priv;
+ nand_set_controller_data(nand, priv);
nand->ecc.read_page = fsl_ifc_read_page;
nand->ecc.write_page = fsl_ifc_write_page;
@@ -1044,7 +1044,7 @@
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, mtd);
if (ret)
return ret;
return 0;
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 5426c32..d2b3881 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -64,8 +64,8 @@
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_upm_nand *fun = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_upm_nand *fun = nand_get_controller_data(chip);
if (chip_nr >= 0) {
fun->chip_nr = chip_nr;
@@ -79,8 +79,8 @@
static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_upm_nand *fun = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_upm_nand *fun = nand_get_controller_data(chip);
void __iomem *io_addr;
u32 mar;
@@ -123,7 +123,7 @@
static u8 upm_nand_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
return in_8(chip->IO_ADDR_R);
}
@@ -131,8 +131,8 @@
static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
- struct nand_chip *chip = mtd->priv;
- struct fsl_upm_nand *fun = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_upm_nand *fun = nand_get_controller_data(chip);
for (i = 0; i < len; i++) {
out_8(chip->IO_ADDR_W, buf[i]);
@@ -147,7 +147,7 @@
static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
for (i = 0; i < len; i++)
buf[i] = in_8(chip->IO_ADDR_R);
@@ -155,8 +155,8 @@
static int nand_dev_ready(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct fsl_upm_nand *fun = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct fsl_upm_nand *fun = nand_get_controller_data(chip);
return fun->dev_ready(fun->chip_nr);
}
@@ -168,7 +168,7 @@
fun->last_ctrl = NAND_CLE;
- chip->priv = fun;
+ nand_set_controller_data(chip, fun);
chip->chip_delay = fun->chip_delay;
chip->ecc.mode = NAND_ECC_SOFT;
chip->cmd_ctrl = fun_cmd_ctrl;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e0e9e1e..a1f2cba 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -165,7 +165,7 @@
static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
@@ -409,8 +409,8 @@
* Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
* function, as it doesn't need to switch to a different ECC layout.
*/
- mtd = &nand_info[nand_curr_device];
- nand = mtd->priv;
+ mtd = nand_info[nand_curr_device];
+ nand = mtd_to_nand(mtd);
/* Setup the ecc configurations again */
if (eccstrength == 1) {
@@ -443,7 +443,6 @@
{
static int chip_nr;
struct mtd_info *mtd;
- int i;
u32 peripid2 = readl(&fsmc_regs_p->peripid2);
fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
@@ -480,8 +479,7 @@
(void __iomem *)CONFIG_SYS_NAND_BASE;
nand->badblockbits = 7;
- mtd = &nand_info[chip_nr++];
- mtd->priv = nand;
+ mtd = nand_to_mtd(nand);
switch (fsmc_version) {
case FSMC_VER8:
@@ -514,9 +512,8 @@
if (nand_scan_tail(mtd))
return -ENXIO;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- if (nand_register(i))
- return -ENXIO;
+ if (nand_register(chip_nr++, mtd))
+ return -ENXIO;
return 0;
}
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
deleted file mode 100644
index abcedc2..0000000
--- a/drivers/mtd/nand/jz4740_nand.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Platform independend driver for JZ4740.
- *
- * Copyright (c) 2007 Ingenic Semiconductor Inc.
- * Author: <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
-#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
-#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
-
-#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
-#define JZ_NAND_ECC_CTRL_RS BIT(2)
-#define JZ_NAND_ECC_CTRL_RESET BIT(1)
-#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
-
-#define EMC_SMCR1_OPT_NAND 0x094c4400
-/* Optimize the timing of nand */
-
-static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
-
-static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
- .eccbytes = 72,
- .eccpos = {
- 12, 13, 14, 15, 16, 17, 18, 19,
- 20, 21, 22, 23, 24, 25, 26, 27,
- 28, 29, 30, 31, 32, 33, 34, 35,
- 36, 37, 38, 39, 40, 41, 42, 43,
- 44, 45, 46, 47, 48, 49, 50, 51,
- 52, 53, 54, 55, 56, 57, 58, 59,
- 60, 61, 62, 63, 64, 65, 66, 67,
- 68, 69, 70, 71, 72, 73, 74, 75,
- 76, 77, 78, 79, 80, 81, 82, 83 },
- .oobfree = {
- {.offset = 2,
- .length = 10 },
- {.offset = 84,
- .length = 44 } }
-};
-
-static int is_reading;
-
-static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- uint32_t reg;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_ALE)
- this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
- else if (ctrl & NAND_CLE)
- this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
- else
- this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
-
- reg = readl(&emc->nfcsr);
- if (ctrl & NAND_NCE)
- reg |= EMC_NFCSR_NFCE1;
- else
- reg &= ~EMC_NFCSR_NFCE1;
- writel(reg, &emc->nfcsr);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int jz_nand_device_ready(struct mtd_info *mtd)
-{
- return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- /*
- * Don't use "chip" to address the NAND device,
- * generate the cs from the address where it is encoded.
- */
-}
-
-static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
- u_char *ecc_code)
-{
- uint32_t status;
- int i;
-
- if (is_reading)
- return 0;
-
- do {
- status = readl(&emc->nfints);
- } while (!(status & EMC_NFINTS_ENCF));
-
- /* disable ecc */
- writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
- for (i = 0; i < 9; i++)
- ecc_code[i] = readb(&emc->nfpar[i]);
-
- return 0;
-}
-
-static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
-{
- uint32_t reg;
-
- writel(0, &emc->nfints);
- reg = readl(&emc->nfecr);
- reg |= JZ_NAND_ECC_CTRL_RESET;
- reg |= JZ_NAND_ECC_CTRL_ENABLE;
- reg |= JZ_NAND_ECC_CTRL_RS;
-
- switch (mode) {
- case NAND_ECC_READ:
- reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
- is_reading = 1;
- break;
- case NAND_ECC_WRITE:
- reg |= JZ_NAND_ECC_CTRL_ENCODING;
- is_reading = 0;
- break;
- default:
- break;
- }
-
- writel(reg, &emc->nfecr);
-}
-
-/* Correct 1~9-bit errors in 512-bytes data */
-static void jz_rs_correct(unsigned char *dat, int idx, int mask)
-{
- int i;
-
- idx--;
-
- i = idx + (idx >> 3);
- if (i >= 512)
- return;
-
- mask <<= (idx & 0x7);
-
- dat[i] ^= mask & 0xff;
- if (i < 511)
- dat[i + 1] ^= (mask >> 8) & 0xff;
-}
-
-static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int k;
- uint32_t errcnt, index, mask, status;
-
- /* Set PAR values */
- const uint8_t all_ff_ecc[] = {
- 0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
-
- if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
- read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
- read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
- read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
- read_ecc[8] == 0xff) {
- for (k = 0; k < 9; k++)
- writeb(all_ff_ecc[k], &emc->nfpar[k]);
- } else {
- for (k = 0; k < 9; k++)
- writeb(read_ecc[k], &emc->nfpar[k]);
- }
- /* Set PRDY */
- writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
-
- /* Wait for completion */
- do {
- status = readl(&emc->nfints);
- } while (!(status & EMC_NFINTS_DECF));
-
- /* disable ecc */
- writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
- /* Check decoding */
- if (!(status & EMC_NFINTS_ERR))
- return 0;
-
- if (status & EMC_NFINTS_UNCOR) {
- printf("uncorrectable ecc\n");
- return -1;
- }
-
- errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
-
- switch (errcnt) {
- case 4:
- index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
- EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
- EMC_NFERR_MASK_BIT;
- jz_rs_correct(dat, index, mask);
- case 3:
- index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
- EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
- EMC_NFERR_MASK_BIT;
- jz_rs_correct(dat, index, mask);
- case 2:
- index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
- EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
- EMC_NFERR_MASK_BIT;
- jz_rs_correct(dat, index, mask);
- case 1:
- index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
- EMC_NFERR_INDEX_BIT;
- mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
- EMC_NFERR_MASK_BIT;
- jz_rs_correct(dat, index, mask);
- default:
- break;
- }
-
- return errcnt;
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
- uint32_t reg;
-
- reg = readl(&emc->nfcsr);
- reg |= EMC_NFCSR_NFE1; /* EMC setup, Set NFE bit */
- writel(reg, &emc->nfcsr);
-
- writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
-
- nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
- nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
- nand->cmd_ctrl = jz_nand_cmd_ctrl;
- nand->dev_ready = jz_nand_device_ready;
- nand->ecc.hwctl = jz_nand_hwctl;
- nand->ecc.correct = jz_nand_rs_correct_data;
- nand->ecc.calculate = jz_nand_rs_calculate_ecc;
- nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
- nand->ecc.strength = 4;
- nand->ecc.layout = &qi_lb60_ecclayout_2gb;
- nand->chip_delay = 50;
- nand->bbt_options |= NAND_BBT_USE_FLASH;
-
- return 0;
-}
diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c
index 22c5625..e978cf8 100644
--- a/drivers/mtd/nand/kb9202_nand.c
+++ b/drivers/mtd/nand/kb9202_nand.c
@@ -35,7 +35,7 @@
*/
static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index d734113..d0a68bd 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -33,7 +33,7 @@
static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
- struct nand_chip *nc = mtd->priv;
+ struct nand_chip *nc = mtd_to_nand(mtd);
u32 offs;
if (cmd == NAND_CMD_NONE)
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 8156fe9..4262029 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -378,7 +378,8 @@
*/
static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
{
unsigned int i, status, timeout;
struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
@@ -435,7 +436,8 @@
*/
static int lpc32xx_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
{
unsigned int i;
struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
@@ -539,11 +541,7 @@
void board_nand_init(void)
{
- /* we have only one device anyway */
- struct mtd_info *mtd = &nand_info[0];
- /* chip is struct nand_chip, and is now provided by the driver. */
- mtd->priv = &lpc32xx_chip;
- /* to store return status in case we need to print it */
+ struct mtd_info *mtd = &lpc32xx_chip.mtd;
int ret;
/* Set all BOARDSPECIFIC (actually core-specific) fields */
@@ -597,7 +595,7 @@
}
/* chip is good, register it */
- ret = nand_register(0);
+ ret = nand_register(0, mtd);
if (ret)
error("nand_register returned %i", ret);
}
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
index 4e1be36..daa1e7a 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -291,7 +291,7 @@
static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
int len, int read)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u32 config;
int ret;
@@ -486,7 +486,8 @@
/* Reuse the logic from "nand_write_page_hwecc()" */
static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
int i;
uint8_t *ecc_calc = chip->buffers->ecccalc;
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index e621c36..8a8775c 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -100,7 +100,6 @@
#define NFC_WPC_UNLOCK (1 << 2)
struct mpc5121_nfc_prv {
- struct mtd_info mtd;
struct nand_chip chip;
int irq;
void __iomem *regs;
@@ -117,8 +116,8 @@
/* Read NFC register */
static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
{
- struct nand_chip *chip = mtd->priv;
- struct mpc5121_nfc_prv *prv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
return in_be16(prv->regs + reg);
}
@@ -126,8 +125,8 @@
/* Write NFC register */
static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
{
- struct nand_chip *chip = mtd->priv;
- struct mpc5121_nfc_prv *prv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
out_be16(prv->regs + reg, val);
}
@@ -211,7 +210,7 @@
/* Do address cycle(s) */
static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u32 pagemask = chip->pagemask;
if (column != -1) {
@@ -283,8 +282,8 @@
static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
int column, int page)
{
- struct nand_chip *chip = mtd->priv;
- struct mpc5121_nfc_prv *prv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
prv->column = (column >= 0) ? column : 0;
prv->spareonly = 0;
@@ -357,8 +356,8 @@
static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
u8 * buffer, uint size, int wr)
{
- struct nand_chip *nand = mtd->priv;
- struct mpc5121_nfc_prv *prv = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
uint o, s, sbsize, blksize;
/*
@@ -410,8 +409,8 @@
static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
int wr)
{
- struct nand_chip *chip = mtd->priv;
- struct mpc5121_nfc_prv *prv = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
uint c = prv->column;
uint l;
@@ -489,7 +488,7 @@
static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
uint rcw_pagesize = 0;
uint rcw_sparesize = 0;
uint rcw_width;
@@ -549,7 +548,6 @@
int resettime = 0;
int retval = 0;
int rev;
- static int chip_nr = 0;
/*
* Check SoC revision. This driver supports only NFC
@@ -568,9 +566,8 @@
return -ENOMEM;
}
- mtd = &nand_info[chip_nr++];
- mtd->priv = chip;
- chip->priv = prv;
+ mtd = &chip->mtd;
+ nand_set_controller_data(chip, prv);
/* Read NFC configuration from Reset Config Word */
retval = mpc5121_nfc_read_hw_config(mtd);
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index f12b07e..7221d0b 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -19,7 +19,6 @@
#define DRIVER_NAME "mxc_nand"
struct mxc_nand_host {
- struct mtd_info mtd;
struct nand_chip *nand;
struct mxc_nand_regs __iomem *regs;
@@ -351,8 +350,8 @@
static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
uint16_t tmp = readnfc(&host->regs->config1);
@@ -386,7 +385,7 @@
struct nand_chip *chip,
int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
uint8_t *buf = chip->oob_poi;
int length = mtd->oobsize;
int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -441,7 +440,7 @@
int oob_required,
int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -486,7 +485,7 @@
int oob_required,
int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
int n, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -550,7 +549,7 @@
static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip, int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
int length = mtd->oobsize;
int i, len, status, steps = chip->ecc.steps;
@@ -576,9 +575,9 @@
static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -616,9 +615,9 @@
static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
- struct mxc_nand_host *host = chip->priv;
+ struct mxc_nand_host *host = nand_get_controller_data(chip);
int i, n, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -661,8 +660,8 @@
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
uint32_t ecc_status = readl(&host->regs->ecc_status_result);
int subpages = mtd->writesize / nand_chip->subpagesize;
int pg2blk_shift = nand_chip->phys_erase_shift -
@@ -681,7 +680,7 @@
mtd->writesize / nand_chip->subpagesize
- subpages);
}
- return -1;
+ return -EBADMSG;
}
ecc_status >>= 4;
subpages--;
@@ -700,8 +699,8 @@
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
/*
* 1-Bit errors are automatically corrected in HW. No need for
@@ -713,7 +712,7 @@
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
"MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
- return -1;
+ return -EBADMSG;
}
return 0;
@@ -729,8 +728,8 @@
static u_char mxc_nand_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
uint8_t ret = 0;
uint16_t col;
uint16_t __iomem *main_buf =
@@ -769,8 +768,8 @@
static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
uint16_t col, ret;
uint16_t __iomem *p;
@@ -821,8 +820,8 @@
static void mxc_nand_write_buf(struct mtd_info *mtd,
const u_char *buf, int len)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
int n, col, i = 0;
MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -895,8 +894,8 @@
*/
static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
int n, col, i = 0;
MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -955,8 +954,8 @@
*/
static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
switch (chip) {
case -1:
@@ -982,8 +981,8 @@
void mxc_nand_command(struct mtd_info *mtd, unsigned command,
int column, int page_addr)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
MTDDEBUG(MTD_DEBUG_LEVEL3,
"mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
@@ -1164,14 +1163,13 @@
#endif
/* structures must be linked */
- mtd = &host->mtd;
- mtd->priv = this;
+ mtd = &this->mtd;
host->nand = this;
/* 5 us command delay time */
this->chip_delay = 5;
- this->priv = host;
+ nand_set_controller_data(this, host);
this->dev_ready = mxc_nand_dev_ready;
this->cmdfunc = mxc_nand_command;
this->select_chip = mxc_nand_select_chip;
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c
index 6ac2c96..841fb5b 100644
--- a/drivers/mtd/nand/mxc_nand_spl.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -232,7 +232,7 @@
nfc_nand_read_page(page_address);
if (nfc_nand_check_ecc())
- return -1;
+ return -EBADMSG;
src = (u32 *)&nfc->main_area[0][0];
dst = (u32 *)buf;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index b5bbd88..7be1f86 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -264,8 +264,8 @@
*/
static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
@@ -343,8 +343,8 @@
*/
static int mxs_nand_device_ready(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
@@ -360,8 +360,8 @@
*/
static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
nand_info->cur_chip = chip;
}
@@ -410,8 +410,8 @@
*/
static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
@@ -494,8 +494,8 @@
static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int length)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
@@ -559,7 +559,7 @@
uint8_t *buf, int oob_required,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
uint32_t corrected = 0, failed = 0;
@@ -707,9 +707,9 @@
*/
static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
struct nand_chip *nand, const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
@@ -775,8 +775,8 @@
static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
if (ops->mode == MTD_OPS_RAW)
@@ -800,8 +800,8 @@
static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
if (ops->mode == MTD_OPS_RAW)
@@ -824,8 +824,8 @@
*/
static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
nand_info->marking_block_bad = 1;
@@ -884,7 +884,7 @@
static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
/*
* First, fill in the OOB buffer. If we're doing a raw read, we need to
@@ -919,7 +919,7 @@
static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
uint8_t block_mark = 0;
/*
@@ -961,7 +961,7 @@
* Thus, this function is only called when we want *all* blocks to look good,
* so it *always* return success.
*/
-static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
return 0;
}
@@ -982,8 +982,8 @@
*/
static int mxs_nand_scan_bbt(struct mtd_info *mtd)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp;
@@ -1175,7 +1175,7 @@
memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
- nand->priv = nand_info;
+ nand_set_controller_data(nand, nand_info);
nand->options |= NAND_NO_SUBPAGE_WRITE;
nand->cmd_ctrl = mxs_nand_cmd_ctrl;
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index 0e7c364..a8a3084 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -8,13 +8,13 @@
#include <nand.h>
#include <malloc.h>
-static nand_info_t mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
u32 timeo, time_start;
/* write out the command to the device */
@@ -51,7 +51,7 @@
static int mxs_flash_ident(struct mtd_info *mtd)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
int i;
u8 mfg_id, dev_id;
u8 id_data[8];
@@ -111,7 +111,7 @@
static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
int ret;
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
@@ -125,7 +125,7 @@
static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
unsigned int block = offs >> chip->phys_erase_shift;
unsigned int page = offs >> chip->page_shift;
@@ -147,14 +147,14 @@
/* init mxs nand driver */
board_nand_init(&nand_chip);
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
/* set mtd functions */
nand_chip.cmdfunc = mxs_nand_command;
nand_chip.numchips = 1;
/* identify flash device */
puts("NAND : ");
- if (mxs_flash_ident(&mtd)) {
+ if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
}
@@ -162,12 +162,12 @@
/* allocate and initialize buffers */
nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
sizeof(*nand_chip.buffers));
- nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+ nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
/* setup flash layout (does not scan as we override that) */
- mtd.size = nand_chip.chipsize;
- nand_chip.scan_bbt(&mtd);
+ mtd->size = nand_chip.chipsize;
+ nand_chip.scan_bbt(mtd);
- printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+ printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
return 0;
}
@@ -180,20 +180,20 @@
if (mxs_nand_init())
return -ENODEV;
- chip = mtd.priv;
+ chip = mtd_to_nand(mtd);
page = offs >> chip->page_shift;
- nand_page_per_block = mtd.erasesize / mtd.writesize;
+ nand_page_per_block = mtd->erasesize / mtd->writesize;
debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
- size = roundup(size, mtd.writesize);
+ size = roundup(size, mtd->writesize);
while (sz < size) {
- if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+ if (mxs_read_page_ecc(mtd, buf, page) < 0)
return -1;
- sz += mtd.writesize;
- offs += mtd.writesize;
+ sz += mtd->writesize;
+ offs += mtd->writesize;
page++;
- buf += mtd.writesize;
+ buf += mtd->writesize;
/*
* Check if we have crossed a block boundary, and if so
@@ -204,10 +204,10 @@
* Yes, new block. See if this block is good. If not,
* loop until we find a good block.
*/
- while (is_badblock(&mtd, offs, 1)) {
+ while (is_badblock(mtd, offs, 1)) {
page = page + nand_page_per_block;
/* Check i we've reached the end of flash. */
- if (page >= mtd.size >> chip->page_shift)
+ if (page >= mtd->size >> chip->page_shift)
return -ENOMEM;
}
}
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 8f0a921..f449316 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -19,7 +19,7 @@
int nand_curr_device = -1;
-nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#ifndef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -30,15 +30,25 @@
static unsigned long total_nand_size; /* in kiB */
-/* Register an initialized NAND mtd device with the U-Boot NAND command. */
-int nand_register(int devnum)
+int nand_mtd_to_devnum(struct mtd_info *mtd)
{
- struct mtd_info *mtd;
+ int i;
+ for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
+ if (mtd && nand_info[i] == mtd)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+/* Register an initialized NAND mtd device with the U-Boot NAND command. */
+int nand_register(int devnum, struct mtd_info *mtd)
+{
if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
return -EINVAL;
- mtd = &nand_info[devnum];
+ nand_info[devnum] = mtd;
sprintf(dev_name[devnum], "nand%d", devnum);
mtd->name = dev_name[devnum];
@@ -62,15 +72,14 @@
#ifndef CONFIG_SYS_NAND_SELF_INIT
static void nand_init_chip(int i)
{
- struct mtd_info *mtd = &nand_info[i];
struct nand_chip *nand = &nand_chip[i];
+ struct mtd_info *mtd = nand_to_mtd(nand);
ulong base_addr = base_address[i];
int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
if (maxchips < 1)
maxchips = 1;
- mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
if (board_nand_init(nand))
@@ -79,7 +88,7 @@
if (nand_scan(mtd, maxchips))
return;
- nand_register(i);
+ nand_register(i, mtd);
}
#endif
@@ -100,6 +109,7 @@
/*
* Select the chip in the board/cpu specific driver
*/
- board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+ board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
+ nand_curr_device);
#endif
}
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 9e8fc1f..74c563c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1,6 +1,4 @@
/*
- * drivers/mtd/nand.c
- *
* Overview:
* This is the generic MTD driver for NAND flash devices. It should be
* capable of working with almost all NAND chips currently available.
@@ -45,8 +43,6 @@
#include <asm/io.h>
#include <asm/errno.h>
-static bool is_module_text_address(unsigned long addr) {return 0;}
-
/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
.eccbytes = 3,
@@ -105,7 +101,7 @@
static int check_offs_len(struct mtd_info *mtd,
loff_t ofs, uint64_t len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
int ret = 0;
/* Start address must align on block boundary */
@@ -131,7 +127,7 @@
*/
static void nand_release_device(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/* De-select the NAND device */
chip->select_chip(mtd, -1);
@@ -145,7 +141,7 @@
*/
uint8_t nand_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
return readb(chip->IO_ADDR_R);
}
@@ -158,7 +154,7 @@
*/
static uint8_t nand_read_byte16(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
}
@@ -170,7 +166,7 @@
*/
static u16 nand_read_word(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
return readw(chip->IO_ADDR_R);
}
@@ -183,7 +179,7 @@
*/
static void nand_select_chip(struct mtd_info *mtd, int chipnr)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
switch (chipnr) {
case -1:
@@ -206,7 +202,7 @@
*/
static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
chip->write_buf(mtd, &byte, 1);
}
@@ -220,7 +216,7 @@
*/
static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
uint16_t word = byte;
/*
@@ -287,7 +283,7 @@
*/
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
iowrite8_rep(chip->IO_ADDR_W, buf, len);
}
@@ -302,7 +298,7 @@
*/
void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
ioread8_rep(chip->IO_ADDR_R, buf, len);
}
@@ -317,7 +313,7 @@
*/
void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u16 *p = (u16 *) buf;
iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
@@ -333,7 +329,7 @@
*/
void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u16 *p = (u16 *) buf;
ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
@@ -343,14 +339,13 @@
* nand_block_bad - [DEFAULT] Read bad block marker from the chip
* @mtd: MTD device structure
* @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
*
* Check, if the block is bad.
*/
-static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
- int page, chipnr, res = 0, i = 0;
- struct nand_chip *chip = mtd->priv;
+ int page, res = 0, i = 0;
+ struct nand_chip *chip = mtd_to_nand(mtd);
u16 bad;
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
@@ -358,15 +353,6 @@
page = (int)(ofs >> chip->page_shift) & chip->pagemask;
- if (getchip) {
- chipnr = (int)(ofs >> chip->chip_shift);
-
- nand_get_device(mtd, FL_READING);
-
- /* Select the NAND device */
- chip->select_chip(mtd, chipnr);
- }
-
do {
if (chip->options & NAND_BUSWIDTH_16) {
chip->cmdfunc(mtd, NAND_CMD_READOOB,
@@ -391,11 +377,6 @@
i++;
} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
- if (getchip) {
- chip->select_chip(mtd, -1);
- nand_release_device(mtd);
- }
-
return res;
}
@@ -410,7 +391,7 @@
*/
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct mtd_oob_ops ops;
uint8_t buf[2] = { 0, 0 };
int ret = 0, res, i = 0;
@@ -460,7 +441,7 @@
*/
static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
int res, ret = 0;
if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
@@ -501,7 +482,7 @@
*/
static int nand_check_wp(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/* Broken xD cards report WP despite being writable */
if (chip->options & NAND_BROKEN_XD)
@@ -521,7 +502,7 @@
*/
static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
if (!chip->bbt)
return 0;
@@ -533,16 +514,14 @@
* nand_block_checkbad - [GENERIC] Check if a block is marked bad
* @mtd: MTD device structure
* @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
* @allowbbt: 1, if its allowed to access the bbt area
*
* Check, if the block is bad. Either by reading the bad block table or
* calling of the scan function.
*/
-static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
- int allowbbt)
+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
if (!(chip->options & NAND_SKIP_BBTSCAN) &&
!(chip->options & NAND_BBT_SCANNED)) {
@@ -551,17 +530,22 @@
}
if (!chip->bbt)
- return chip->block_bad(mtd, ofs, getchip);
+ return chip->block_bad(mtd, ofs);
/* Return info from the table */
return nand_isbad_bbt(mtd, ofs, allowbbt);
}
-/* Wait for the ready pin, after a command. The timeout is caught later. */
+/**
+ * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
+ * @mtd: MTD device structure
+ *
+ * Wait for the ready pin after a command, and warn if a timeout occurs.
+ */
void nand_wait_ready(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
u32 time_start;
time_start = get_timer(0);
@@ -571,6 +555,9 @@
if (chip->dev_ready(mtd))
break;
}
+
+ if (!chip->dev_ready(mtd))
+ pr_warn("timeout while waiting for chip to become ready\n");
}
EXPORT_SYMBOL_GPL(nand_wait_ready);
@@ -583,7 +570,7 @@
*/
static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
u32 time_start;
timeo = (CONFIG_SYS_HZ * timeo) / 1000;
@@ -608,7 +595,7 @@
static void nand_command(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
/* Write out the command to the device */
@@ -711,7 +698,7 @@
static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- register struct nand_chip *chip = mtd->priv;
+ register struct nand_chip *chip = mtd_to_nand(mtd);
/* Emulate NAND_CMD_READOOB */
if (command == NAND_CMD_READOOB) {
@@ -835,7 +822,7 @@
static int
nand_get_device(struct mtd_info *mtd, int new_state)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
chip->state = new_state;
return 0;
}
@@ -871,15 +858,13 @@
* @mtd: MTD device structure
* @chip: NAND chip structure
*
- * Wait for command done. This applies to erase and program only. Erase can
- * take up to 400ms and program up to 20ms according to general NAND and
- * SmartMedia specs.
+ * Wait for command done. This applies to erase and program only.
*/
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
- int status, state = chip->state;
- unsigned long timeo = (state == FL_ERASING ? 400 : 20);
+ int status;
+ unsigned long timeo = 400;
led_trigger_event(nand_led_trigger, LED_FULL);
@@ -911,6 +896,135 @@
WARN_ON(!(status & NAND_STATUS_READY));
return status;
}
+
+#define BITS_PER_BYTE 8
+
+/**
+ * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
+ * @buf: buffer to test
+ * @len: buffer length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a buffer contains only 0xff, which means the underlying region
+ * has been erased and is ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region is not erased.
+ * Note: The logic of this function has been extracted from the memweight
+ * implementation, except that nand_check_erased_buf function exit before
+ * testing the whole buffer if the number of bitflips exceed the
+ * bitflips_threshold value.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold.
+ */
+static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
+{
+ const unsigned char *bitmap = buf;
+ int bitflips = 0;
+ int weight;
+
+ for (; len && ((uintptr_t)bitmap) % sizeof(long);
+ len--, bitmap++) {
+ weight = hweight8(*bitmap);
+ bitflips += BITS_PER_BYTE - weight;
+ if (unlikely(bitflips > bitflips_threshold))
+ return -EBADMSG;
+ }
+
+ for (; len >= 4; len -= 4, bitmap += 4) {
+ weight = hweight32(*((u32 *)bitmap));
+ bitflips += 32 - weight;
+ if (unlikely(bitflips > bitflips_threshold))
+ return -EBADMSG;
+ }
+
+ for (; len > 0; len--, bitmap++) {
+ weight = hweight8(*bitmap);
+ bitflips += BITS_PER_BYTE - weight;
+ if (unlikely(bitflips > bitflips_threshold))
+ return -EBADMSG;
+ }
+
+ return bitflips;
+}
+
+/**
+ * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
+ * 0xff data
+ * @data: data buffer to test
+ * @datalen: data length
+ * @ecc: ECC buffer
+ * @ecclen: ECC length
+ * @extraoob: extra OOB buffer
+ * @extraooblen: extra OOB length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a data buffer and its associated ECC and OOB data contains only
+ * 0xff pattern, which means the underlying region has been erased and is
+ * ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region as not erased.
+ *
+ * Note:
+ * 1/ ECC algorithms are working on pre-defined block sizes which are usually
+ * different from the NAND page size. When fixing bitflips, ECC engines will
+ * report the number of errors per chunk, and the NAND core infrastructure
+ * expect you to return the maximum number of bitflips for the whole page.
+ * This is why you should always use this function on a single chunk and
+ * not on the whole page. After checking each chunk you should update your
+ * max_bitflips value accordingly.
+ * 2/ When checking for bitflips in erased pages you should not only check
+ * the payload data but also their associated ECC data, because a user might
+ * have programmed almost all bits to 1 but a few. In this case, we
+ * shouldn't consider the chunk as erased, and checking ECC bytes prevent
+ * this case.
+ * 3/ The extraoob argument is optional, and should be used if some of your OOB
+ * data are protected by the ECC engine.
+ * It could also be used if you support subpages and want to attach some
+ * extra OOB data to an ECC chunk.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold. In case of success, the passed buffers are filled with 0xff.
+ */
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+ void *ecc, int ecclen,
+ void *extraoob, int extraooblen,
+ int bitflips_threshold)
+{
+ int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
+
+ data_bitflips = nand_check_erased_buf(data, datalen,
+ bitflips_threshold);
+ if (data_bitflips < 0)
+ return data_bitflips;
+
+ bitflips_threshold -= data_bitflips;
+
+ ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
+ if (ecc_bitflips < 0)
+ return ecc_bitflips;
+
+ bitflips_threshold -= ecc_bitflips;
+
+ extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
+ bitflips_threshold);
+ if (extraoob_bitflips < 0)
+ return extraoob_bitflips;
+
+ if (data_bitflips)
+ memset(data, 0xff, datalen);
+
+ if (ecc_bitflips)
+ memset(ecc, 0xff, ecclen);
+
+ if (extraoob_bitflips)
+ memset(extraoob, 0xff, extraooblen);
+
+ return data_bitflips + ecc_bitflips + extraoob_bitflips;
+}
+EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
/**
* nand_read_page_raw - [INTERN] read raw page data without ecc
@@ -1103,6 +1217,16 @@
stat = chip->ecc.correct(mtd, p,
&chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
+ if (stat == -EBADMSG &&
+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+ /* check for empty pages with bitflips */
+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+ &chip->buffers->ecccode[i],
+ chip->ecc.bytes,
+ NULL, 0,
+ chip->ecc.strength);
+ }
+
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
@@ -1152,6 +1276,15 @@
int stat;
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat == -EBADMSG &&
+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+ /* check for empty pages with bitflips */
+ stat = nand_check_erased_ecc_chunk(p, eccsize,
+ &ecc_code[i], eccbytes,
+ NULL, 0,
+ chip->ecc.strength);
+ }
+
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
@@ -1204,6 +1337,15 @@
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+ if (stat == -EBADMSG &&
+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+ /* check for empty pages with bitflips */
+ stat = nand_check_erased_ecc_chunk(p, eccsize,
+ &ecc_code[i], eccbytes,
+ NULL, 0,
+ chip->ecc.strength);
+ }
+
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
@@ -1231,6 +1373,7 @@
int i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccsteps = chip->ecc.steps;
+ int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
uint8_t *p = buf;
uint8_t *oob = chip->oob_poi;
unsigned int max_bitflips = 0;
@@ -1250,19 +1393,29 @@
chip->read_buf(mtd, oob, eccbytes);
stat = chip->ecc.correct(mtd, p, oob, NULL);
- if (stat < 0) {
- mtd->ecc_stats.failed++;
- } else {
- mtd->ecc_stats.corrected += stat;
- max_bitflips = max_t(unsigned int, max_bitflips, stat);
- }
-
oob += eccbytes;
if (chip->ecc.postpad) {
chip->read_buf(mtd, oob, chip->ecc.postpad);
oob += chip->ecc.postpad;
}
+
+ if (stat == -EBADMSG &&
+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+ /* check for empty pages with bitflips */
+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+ oob - eccpadbytes,
+ eccpadbytes,
+ NULL, 0,
+ chip->ecc.strength);
+ }
+
+ if (stat < 0) {
+ mtd->ecc_stats.failed++;
+ } else {
+ mtd->ecc_stats.corrected += stat;
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
}
/* Calculate remaining oob bytes */
@@ -1332,7 +1485,7 @@
*/
static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
pr_debug("setting READ RETRY mode %d\n", retry_mode);
@@ -1357,12 +1510,11 @@
struct mtd_oob_ops *ops)
{
int chipnr, page, realpage, col, bytes, aligned, oob_required;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
int ret = 0;
uint32_t readlen = ops->len;
uint32_t oobreadlen = ops->ooblen;
- uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
- mtd->oobavail : mtd->oobsize;
+ uint32_t max_oobsize = mtd_oobavail(mtd, ops);
uint8_t *bufpoi, *oob, *buf;
int use_bufpoi;
@@ -1700,7 +1852,7 @@
struct mtd_oob_ops *ops)
{
int page, realpage, chipnr;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct mtd_ecc_stats stats;
int readlen = ops->ooblen;
int len;
@@ -1712,10 +1864,7 @@
stats = mtd->ecc_stats;
- if (ops->mode == MTD_OPS_AUTO_OOB)
- len = chip->ecc.layout->oobavail;
- else
- len = mtd->oobsize;
+ len = mtd_oobavail(mtd, ops);
if (unlikely(ops->ooboffs >= len)) {
pr_debug("%s: attempt to start read outside oob\n",
@@ -1840,11 +1989,12 @@
* @chip: nand chip info structure
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*
* Not for syndrome calculating ECC controllers, which use a special oob layout.
*/
static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required, int page)
{
chip->write_buf(mtd, buf, mtd->writesize);
if (oob_required)
@@ -1859,12 +2009,14 @@
* @chip: nand chip info structure
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*
* We need a special oob layout and handling even when ECC isn't checked.
*/
static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
@@ -1901,9 +2053,11 @@
* @chip: nand chip info structure
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*/
static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
int i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
@@ -1919,7 +2073,7 @@
for (i = 0; i < chip->ecc.total; i++)
chip->oob_poi[eccpos[i]] = ecc_calc[i];
- return chip->ecc.write_page_raw(mtd, chip, buf, 1);
+ return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
}
/**
@@ -1928,9 +2082,11 @@
* @chip: nand chip info structure
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*/
static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
int i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
@@ -1962,11 +2118,12 @@
* @data_len: data length
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*/
static int nand_write_subpage_hwecc(struct mtd_info *mtd,
struct nand_chip *chip, uint32_t offset,
uint32_t data_len, const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
uint8_t *oob_buf = chip->oob_poi;
uint8_t *ecc_calc = chip->buffers->ecccalc;
@@ -2021,13 +2178,15 @@
* @chip: nand chip info structure
* @buf: data buffer
* @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
*
* The hw generator calculates the error syndrome automatically. Therefore we
* need a special oob layout and handling.
*/
static int nand_write_page_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required,
+ int page)
{
int i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
@@ -2091,12 +2250,13 @@
if (unlikely(raw))
status = chip->ecc.write_page_raw(mtd, chip, buf,
- oob_required);
+ oob_required, page);
else if (subpage)
status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
- buf, oob_required);
+ buf, oob_required, page);
else
- status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+ status = chip->ecc.write_page(mtd, chip, buf, oob_required,
+ page);
if (status < 0)
return status;
@@ -2139,7 +2299,7 @@
static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
struct mtd_oob_ops *ops)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/*
* Initialise to all 0xFF, to avoid the possibility of left over OOB
@@ -2199,12 +2359,11 @@
struct mtd_oob_ops *ops)
{
int chipnr, realpage, page, blockmask, column;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
uint32_t writelen = ops->len;
uint32_t oobwritelen = ops->ooblen;
- uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
- mtd->oobavail : mtd->oobsize;
+ uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
uint8_t *oob = ops->oobbuf;
uint8_t *buf = ops->datbuf;
@@ -2328,7 +2487,7 @@
static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const uint8_t *buf)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct mtd_oob_ops ops;
int ret;
@@ -2388,15 +2547,12 @@
struct mtd_oob_ops *ops)
{
int chipnr, page, status, len;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
pr_debug("%s: to = 0x%08x, len = %i\n",
__func__, (unsigned int)to, (int)ops->ooblen);
- if (ops->mode == MTD_OPS_AUTO_OOB)
- len = chip->ecc.layout->oobavail;
- else
- len = mtd->oobsize;
+ len = mtd_oobavail(mtd, ops);
/* Do not allow write past end of page */
if ((ops->ooboffs + ops->ooblen) > len) {
@@ -2513,7 +2669,7 @@
*/
static int single_erase(struct mtd_info *mtd, int page)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/* Send commands to erase a block */
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
@@ -2545,7 +2701,7 @@
int allowbbt)
{
int page, status, pages_per_block, ret, chipnr;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
loff_t len;
pr_debug("%s: start = 0x%012llx, len = %llu\n",
@@ -2586,7 +2742,7 @@
/* Check if we have a bad block, we do not erase bad blocks! */
if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
- chip->page_shift, 0, allowbbt)) {
+ chip->page_shift, allowbbt)) {
pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
__func__, page);
instr->state = MTD_ERASE_FAILED;
@@ -2673,7 +2829,20 @@
*/
static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
{
- return nand_block_checkbad(mtd, offs, 1, 0);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int chipnr = (int)(offs >> chip->chip_shift);
+ int ret;
+
+ /* Select the NAND device */
+ nand_get_device(mtd, FL_READING);
+ chip->select_chip(mtd, chipnr);
+
+ ret = nand_block_checkbad(mtd, offs, 0);
+
+ chip->select_chip(mtd, -1);
+ nand_release_device(mtd);
+
+ return ret;
}
/**
@@ -2745,9 +2914,6 @@
return -EINVAL;
#endif
- /* clear the sub feature parameters */
- memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
-
chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
*subfeature_param++ = chip->read_byte(mtd);
@@ -2908,7 +3074,7 @@
static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
@@ -3480,7 +3646,7 @@
if (find_full_id_nand(mtd, chip, type, id_data, &busw))
goto ident_done;
} else if (*dev_id == type->dev_id) {
- break;
+ break;
}
}
@@ -3503,10 +3669,7 @@
chip->chipsize = (uint64_t)type->chipsize << 20;
- if (!type->pagesize && chip->init_size) {
- /* Set the pagesize, oobsize, erasesize by the driver */
- busw = chip->init_size(mtd, chip, id_data);
- } else if (!type->pagesize) {
+ if (!type->pagesize) {
/* Decode parameters from extended ID */
nand_decode_ext_id(mtd, chip, id_data, &busw);
} else {
@@ -3610,13 +3773,12 @@
* This is the first phase of the normal nand_scan() function. It reads the
* flash ID and sets up MTD fields accordingly.
*
- * The mtd->owner field must be set to the module of the caller.
*/
int nand_scan_ident(struct mtd_info *mtd, int maxchips,
struct nand_flash_dev *table)
{
int i, nand_maf_id, nand_dev_id;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_flash_dev *type;
/* Set the default functions */
@@ -3680,7 +3842,7 @@
*/
static bool nand_ecc_strength_good(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_ecc_ctrl *ecc = &chip->ecc;
int corr, ds_corr;
@@ -3709,7 +3871,7 @@
int nand_scan_tail(struct mtd_info *mtd)
{
int i;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_ecc_ctrl *ecc = &chip->ecc;
struct nand_buffers *nbuf;
@@ -3786,7 +3948,7 @@
ecc->write_oob = nand_write_oob_std;
if (!ecc->read_subpage)
ecc->read_subpage = nand_read_subpage;
- if (!ecc->write_subpage)
+ if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
ecc->write_subpage = nand_write_subpage_hwecc;
case NAND_ECC_HW_SYNDROME:
@@ -3864,10 +4026,8 @@
}
/* See nand_bch_init() for details. */
- ecc->bytes = DIV_ROUND_UP(
- ecc->strength * fls(8 * ecc->size), 8);
- ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
- &ecc->layout);
+ ecc->bytes = 0;
+ ecc->priv = nand_bch_init(mtd);
if (!ecc->priv) {
pr_warn("BCH ECC initialization failed!\n");
BUG();
@@ -3902,11 +4062,11 @@
* The number of bytes available for a client to place data into
* the out of band area.
*/
- ecc->layout->oobavail = 0;
- for (i = 0; ecc->layout->oobfree[i].length
- && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
- ecc->layout->oobavail += ecc->layout->oobfree[i].length;
- mtd->oobavail = ecc->layout->oobavail;
+ mtd->oobavail = 0;
+ if (ecc->layout) {
+ for (i = 0; ecc->layout->oobfree[i].length; i++)
+ mtd->oobavail += ecc->layout->oobfree[i].length;
+ }
/* ECC sanity check: warn if it's too weak */
if (!nand_ecc_strength_good(mtd))
@@ -3991,18 +4151,6 @@
}
EXPORT_SYMBOL(nand_scan_tail);
-/*
- * is_module_text_address() isn't exported, and it's mostly a pointless
- * test if this is a module _anyway_ -- they'd have to try _really_ hard
- * to call us from in-kernel code if the core NAND support is modular.
- */
-#ifdef MODULE
-#define caller_is_module() (1)
-#else
-#define caller_is_module() \
- is_module_text_address((unsigned long)__builtin_return_address(0))
-#endif
-
/**
* nand_scan - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
@@ -4010,19 +4158,12 @@
*
* This fills out all the uninitialized function pointers with the defaults.
* The flash ID is read and the mtd/chip structures are filled with the
- * appropriate values. The mtd->owner field must be set to the module of the
- * caller.
+ * appropriate values.
*/
int nand_scan(struct mtd_info *mtd, int maxchips)
{
int ret;
- /* Many callers got this wrong, so check for it for a while... */
- if (!mtd->owner && caller_is_module()) {
- pr_crit("%s called with NULL mtd->owner!\n", __func__);
- BUG();
- }
-
ret = nand_scan_ident(mtd, maxchips, NULL);
if (!ret)
ret = nand_scan_tail(mtd);
@@ -4030,9 +4171,6 @@
}
EXPORT_SYMBOL(nand_scan);
-module_init(nand_base_init);
-module_exit(nand_base_exit);
-
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 00f28a4..74c4c9a 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -1,6 +1,4 @@
/*
- * drivers/mtd/nand_bbt.c
- *
* Overview:
* Bad block table support for the NAND driver
*
@@ -65,7 +63,6 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/bbm.h>
#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
#include <linux/bitops.h>
#include <linux/string.h>
@@ -173,7 +170,7 @@
struct nand_bbt_descr *td, int offs)
{
int res, ret = 0, i, j, act = 0;
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
size_t retlen, len, totlen;
loff_t from;
int bits = td->options & NAND_BBT_NRBITS_MSK;
@@ -264,7 +261,7 @@
*/
static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int res = 0, i;
if (td->options & NAND_BBT_PERCHIP) {
@@ -389,7 +386,7 @@
static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
struct nand_bbt_descr *td, struct nand_bbt_descr *md)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
/* Read the primary version, if available */
if (td->options & NAND_BBT_VERSION) {
@@ -455,7 +452,7 @@
static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
struct nand_bbt_descr *bd, int chip)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int i, numblocks, numpages;
int startblock;
loff_t from;
@@ -524,7 +521,7 @@
*/
static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int i, chips;
int startblock, block, dir;
int scanlen = mtd->writesize + mtd->oobsize;
@@ -619,7 +616,7 @@
struct nand_bbt_descr *td, struct nand_bbt_descr *md,
int chipsel)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
struct erase_info einfo;
int i, res, chip = 0;
int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
@@ -718,7 +715,7 @@
/* Must we save the block contents? */
if (td->options & NAND_BBT_SAVECONTENT) {
/* Make it block aligned */
- to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1));
+ to &= ~(((loff_t)1 << this->bbt_erase_shift) - 1);
len = 1 << this->bbt_erase_shift;
res = mtd_read(mtd, to, len, &retlen, buf);
if (res < 0) {
@@ -820,7 +817,7 @@
*/
static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
return create_bbt(mtd, this->buffers->databuf, bd, -1);
}
@@ -839,7 +836,7 @@
static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
{
int i, chips, writeops, create, chipsel, res, res2;
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
struct nand_bbt_descr *td = this->bbt_td;
struct nand_bbt_descr *md = this->bbt_md;
struct nand_bbt_descr *rd, *rd2;
@@ -963,7 +960,7 @@
*/
static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int i, j, chips, block, nrblocks, update;
uint8_t oldval;
@@ -1023,7 +1020,7 @@
*/
static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u32 pattern_len;
u32 bits;
u32 table_size;
@@ -1073,15 +1070,15 @@
* The bad block table memory is allocated here. It must be freed by calling
* the nand_free_bbt function.
*/
-int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
{
- struct nand_chip *this = mtd->priv;
- int len, res = 0;
+ struct nand_chip *this = mtd_to_nand(mtd);
+ int len, res;
uint8_t *buf;
struct nand_bbt_descr *td = this->bbt_td;
struct nand_bbt_descr *md = this->bbt_md;
- len = mtd->size >> (this->bbt_erase_shift + 2);
+ len = (mtd->size >> (this->bbt_erase_shift + 2)) ? : 1;
/*
* Allocate memory (2bit per block) and clear the memory bad block
* table.
@@ -1097,10 +1094,9 @@
if (!td) {
if ((res = nand_memory_bbt(mtd, bd))) {
pr_err("nand_bbt: can't scan flash and build the RAM-based BBT\n");
- kfree(this->bbt);
- this->bbt = NULL;
+ goto err;
}
- return res;
+ return 0;
}
verify_bbt_descr(mtd, td);
verify_bbt_descr(mtd, md);
@@ -1110,9 +1106,8 @@
len += (len >> this->page_shift) * mtd->oobsize;
buf = vmalloc(len);
if (!buf) {
- kfree(this->bbt);
- this->bbt = NULL;
- return -ENOMEM;
+ res = -ENOMEM;
+ goto err;
}
/* Is the bbt at a given page? */
@@ -1124,6 +1119,8 @@
}
res = check_create(mtd, buf, bd);
+ if (res)
+ goto err;
/* Prevent the bbt regions from erasing / writing */
mark_bbt_region(mtd, td);
@@ -1131,6 +1128,11 @@
mark_bbt_region(mtd, md);
vfree(buf);
+ return 0;
+
+err:
+ kfree(this->bbt);
+ this->bbt = NULL;
return res;
}
@@ -1143,7 +1145,7 @@
*/
static int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int len, res = 0;
int chip, chipsel;
uint8_t *buf;
@@ -1277,7 +1279,7 @@
*/
int nand_default_bbt(struct mtd_info *mtd)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int ret;
/* Is a flash based bad block table requested? */
@@ -1313,7 +1315,7 @@
*/
int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int block;
block = (int)(offs >> this->bbt_erase_shift);
@@ -1328,7 +1330,7 @@
*/
int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int block, res;
block = (int)(offs >> this->bbt_erase_shift);
@@ -1355,7 +1357,7 @@
*/
int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int block, ret = 0;
block = (int)(offs >> this->bbt_erase_shift);
@@ -1369,5 +1371,3 @@
return ret;
}
-
-EXPORT_SYMBOL(nand_scan_bbt);
diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c
index 35d2140..c145203 100644
--- a/drivers/mtd/nand/nand_bch.c
+++ b/drivers/mtd/nand/nand_bch.c
@@ -41,7 +41,7 @@
int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
unsigned char *code)
{
- const struct nand_chip *chip = mtd->priv;
+ const struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_bch_control *nbc = chip->ecc.priv;
unsigned int i;
@@ -67,7 +67,7 @@
int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
unsigned char *read_ecc, unsigned char *calc_ecc)
{
- const struct nand_chip *chip = mtd->priv;
+ const struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_bch_control *nbc = chip->ecc.priv;
unsigned int *errloc = nbc->errloc;
int i, count;
@@ -86,7 +86,7 @@
}
} else if (count < 0) {
printk(KERN_ERR "ecc unrecoverable error\n");
- count = -1;
+ count = -EBADMSG;
}
return count;
}
@@ -94,9 +94,6 @@
/**
* nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
* @mtd: MTD block structure
- * @eccsize: ecc block size in bytes
- * @eccbytes: ecc length in bytes
- * @ecclayout: output default layout
*
* Returns:
* a pointer to a new NAND BCH control structure, or NULL upon failure
@@ -110,14 +107,21 @@
* @eccsize = 512 (thus, m=13 is the smallest integer such that 2^m-1 > 512*8)
* @eccbytes = 7 (7 bytes are required to store m*t = 13*4 = 52 bits)
*/
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
- struct nand_ecclayout **ecclayout)
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
{
+ struct nand_chip *nand = mtd_to_nand(mtd);
unsigned int m, t, eccsteps, i;
- struct nand_ecclayout *layout;
+ struct nand_ecclayout *layout = nand->ecc.layout;
struct nand_bch_control *nbc = NULL;
unsigned char *erased_page;
+ unsigned int eccsize = nand->ecc.size;
+ unsigned int eccbytes = nand->ecc.bytes;
+ unsigned int eccstrength = nand->ecc.strength;
+
+ if (!eccbytes && eccstrength) {
+ eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8);
+ nand->ecc.bytes = eccbytes;
+ }
if (!eccsize || !eccbytes) {
printk(KERN_WARNING "ecc parameters not supplied\n");
@@ -145,7 +149,7 @@
eccsteps = mtd->writesize/eccsize;
/* if no ecc placement scheme was provided, build one */
- if (!*ecclayout) {
+ if (!layout) {
/* handle large page devices only */
if (mtd->oobsize < 64) {
@@ -171,7 +175,7 @@
layout->oobfree[0].offset = 2;
layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
- *ecclayout = layout;
+ nand->ecc.layout = layout;
}
/* sanity checks */
@@ -179,7 +183,7 @@
printk(KERN_WARNING "eccsize %u is too large\n", eccsize);
goto fail;
}
- if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) {
+ if (layout->eccbytes != (eccsteps*eccbytes)) {
printk(KERN_WARNING "invalid ecc layout\n");
goto fail;
}
@@ -203,6 +207,9 @@
for (i = 0; i < eccbytes; i++)
nbc->eccmask[i] ^= 0xff;
+ if (!eccstrength)
+ nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize);
+
return nbc;
fail:
nand_bch_free(nbc);
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index fdd0074..561d2cd 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -1,6 +1,4 @@
/*
- * drivers/mtd/nandids.c
- *
* Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
*
* This program is free software; you can redistribute it and/or modify
@@ -41,6 +39,10 @@
* listed by full ID. We list them first so that we can easily identify
* the most specific match.
*/
+ {"TC58NVG0S3E 1G 3.3V 8-bit",
+ { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
+ SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
+ 2 },
{"TC58NVG2S0F 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
@@ -58,8 +60,8 @@
SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
- SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
- 4 },
+ SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+ NAND_ECC_INFO(40, SZ_1K), 4 },
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c
index 37a0206..335c3e3 100644
--- a/drivers/mtd/nand/nand_plat.c
+++ b/drivers/mtd/nand/nand_plat.c
@@ -25,7 +25,7 @@
static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
if (cmd == NAND_CMD_NONE)
return;
@@ -39,7 +39,7 @@
#ifdef NAND_PLAT_DEV_READY
static int plat_dev_ready(struct mtd_info *mtd)
{
- return NAND_PLAT_DEV_READY((struct nand_chip *)mtd->priv);
+ return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd));
}
#else
# define plat_dev_ready NULL
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index e69f662..b023e00 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -11,7 +11,7 @@
#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static nand_info_t mtd;
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -26,32 +26,32 @@
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
/* Begin command latch cycle */
- this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
- this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
+ this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+ this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
/* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[28:25] */
#endif
/* Latch in address */
- this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
@@ -63,12 +63,12 @@
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
/* Emulate NAND_CMD_READOOB */
@@ -82,30 +82,30 @@
offs >>= 1;
/* Begin command latch cycle */
- hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&mtd, offs & 0xff,
- NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, offs & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
+ NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
/* Latch in address */
- hwctrl(&mtd, NAND_CMD_READSTART,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_READSTART,
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&mtd))
+ while (!this->dev_ready(mtd))
;
return 0;
@@ -114,7 +114,7 @@
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_char bb_data[2];
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -124,11 +124,11 @@
* Read one byte (or two if it's a 16 bit chip).
*/
if (this->options & NAND_BUSWIDTH_16) {
- this->read_buf(&mtd, bb_data, 2);
+ this->read_buf(mtd, bb_data, 2);
if (bb_data[0] != 0xff || bb_data[1] != 0xff)
return 1;
} else {
- this->read_buf(&mtd, bb_data, 1);
+ this->read_buf(mtd, bb_data, 1);
if (bb_data[0] != 0xff)
return 1;
}
@@ -139,7 +139,7 @@
#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
static int nand_read_page(int block, int page, uchar *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -150,7 +150,7 @@
uint8_t *p = dst;
nand_command(block, page, 0, NAND_CMD_READOOB);
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
nand_command(block, page, 0, NAND_CMD_READ0);
/* Pick the ECC bytes out of the oob data */
@@ -159,10 +159,10 @@
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
@@ -170,7 +170,7 @@
#else
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = mtd.priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -184,11 +184,11 @@
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
if (this->ecc.mode != NAND_ECC_SOFT)
- this->ecc.hwctl(&mtd, NAND_ECC_READ);
- this->read_buf(&mtd, p, eccsize);
- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
+ this->read_buf(mtd, p, eccsize);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
}
- this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
/* Pick the ECC bytes out of the oob data */
for (i = 0; i < ECCTOTAL; i++)
@@ -202,7 +202,7 @@
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
@@ -249,7 +249,7 @@
/*
* Init board specific nand support
*/
- mtd.priv = &nand_chip;
+ mtd = &nand_chip.mtd;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
@@ -262,12 +262,12 @@
#endif
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, 0);
+ nand_chip.select_chip(mtd, 0);
}
/* Unselect after operation */
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&mtd, -1);
+ nand_chip.select_chip(mtd, -1);
}
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 71285b6..5bba66a 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -42,25 +42,26 @@
* nand_erase_opts: - erase NAND flash with support for various options
* (jffs2 formatting)
*
- * @param meminfo NAND device to erase
+ * @param mtd nand mtd instance to erase
* @param opts options, @see struct nand_erase_options
* @return 0 in case of success
*
* This code is ported from flash_eraseall.c from Linux mtd utils by
* Arcom Control System Ltd.
*/
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+int nand_erase_opts(struct mtd_info *mtd,
+ const nand_erase_options_t *opts)
{
struct jffs2_unknown_node cleanmarker;
erase_info_t erase;
unsigned long erase_length, erased_length; /* in blocks */
int result;
int percent_complete = -1;
- const char *mtd_device = meminfo->name;
+ const char *mtd_device = mtd->name;
struct mtd_oob_ops oob_opts;
- struct nand_chip *chip = meminfo->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
- if ((opts->offset & (meminfo->erasesize - 1)) != 0) {
+ if ((opts->offset & (mtd->erasesize - 1)) != 0) {
printf("Attempt to erase non block-aligned data\n");
return -1;
}
@@ -68,11 +69,11 @@
memset(&erase, 0, sizeof(erase));
memset(&oob_opts, 0, sizeof(oob_opts));
- erase.mtd = meminfo;
- erase.len = meminfo->erasesize;
+ erase.mtd = mtd;
+ erase.len = mtd->erasesize;
erase.addr = opts->offset;
- erase_length = lldiv(opts->length + meminfo->erasesize - 1,
- meminfo->erasesize);
+ erase_length = lldiv(opts->length + mtd->erasesize - 1,
+ mtd->erasesize);
cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK);
cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER);
@@ -97,7 +98,7 @@
for (erased_length = 0;
erased_length < erase_length;
- erase.addr += meminfo->erasesize) {
+ erase.addr += mtd->erasesize) {
WATCHDOG_RESET();
@@ -106,7 +107,7 @@
return -EFBIG;
}
if (!opts->scrub) {
- int ret = mtd_block_isbad(meminfo, erase.addr);
+ int ret = mtd_block_isbad(mtd, erase.addr);
if (ret > 0) {
if (!opts->quiet)
printf("\rSkipping bad block at "
@@ -129,7 +130,7 @@
erased_length++;
- result = mtd_erase(meminfo, &erase);
+ result = mtd_erase(mtd, &erase);
if (result != 0) {
printf("\n%s: MTD Erase failure: %d\n",
mtd_device, result);
@@ -145,9 +146,7 @@
ops.ooboffs = 0;
ops.mode = MTD_OPS_AUTO_OOB;
- result = mtd_write_oob(meminfo,
- erase.addr,
- &ops);
+ result = mtd_write_oob(mtd, erase.addr, &ops);
if (result != 0) {
printf("\n%s: MTD writeoob failure: %d\n",
mtd_device, result);
@@ -218,7 +217,7 @@
{
int ret = 0;
int status;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/* select the NAND device */
chip->select_chip(mtd, 0);
@@ -268,7 +267,7 @@
int ret = 0;
int chipnr;
int page;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/* select the NAND device */
chipnr = (int)(offset >> chip->chip_shift);
@@ -303,7 +302,7 @@
* @param mtd nand mtd instance
* @param start start byte address
* @param length number of bytes to unlock (must be a multiple of
- * page size nand->writesize)
+ * page size mtd->writesize)
* @param allexcept if set, unlock everything not selected
*
* @return 0 on success, -1 in case of error
@@ -315,7 +314,7 @@
int chipnr;
int status;
int page;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
debug("nand_unlock%s: start: %08llx, length: %zd!\n",
allexcept ? " (allexcept)" : "", start, length);
@@ -399,7 +398,7 @@
* Check if there are any bad blocks, and whether length including bad
* blocks fits into device
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param offset offset in flash
* @param length image length
* @param used length of flash needed for the requested length
@@ -407,8 +406,8 @@
* 1 if the image fits, but there are bad blocks
* -1 if the image does not fit
*/
-static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
- size_t *used)
+static int check_skip_len(struct mtd_info *mtd, loff_t offset, size_t length,
+ size_t *used)
{
size_t len_excl_bad = 0;
int ret = 0;
@@ -417,14 +416,14 @@
size_t block_len, block_off;
loff_t block_start;
- if (offset >= nand->size)
+ if (offset >= mtd->size)
return -1;
- block_start = offset & ~(loff_t)(nand->erasesize - 1);
- block_off = offset & (nand->erasesize - 1);
- block_len = nand->erasesize - block_off;
+ block_start = offset & ~(loff_t)(mtd->erasesize - 1);
+ block_off = offset & (mtd->erasesize - 1);
+ block_len = mtd->erasesize - block_off;
- if (!nand_block_isbad(nand, block_start))
+ if (!nand_block_isbad(mtd, block_start))
len_excl_bad += block_len;
else
ret = 1;
@@ -441,7 +440,7 @@
}
#ifdef CONFIG_CMD_NAND_TRIMFFS
-static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
+static size_t drop_ffs(const struct mtd_info *mtd, const u_char *buf,
const size_t *len)
{
size_t l = *len;
@@ -453,8 +452,8 @@
/* The resulting length must be aligned to the minimum flash I/O size */
l = i + 1;
- l = (l + nand->writesize - 1) / nand->writesize;
- l *= nand->writesize;
+ l = (l + mtd->writesize - 1) / mtd->writesize;
+ l *= mtd->writesize;
/*
* since the input length may be unaligned, prevent access past the end
@@ -471,16 +470,17 @@
* Reads page of NAND and verifies the contents and OOB against the
* values in ops.
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param ops MTD operations, including data to verify
* @param ofs offset in flash
* @return 0 in case of success
*/
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+ loff_t ofs)
{
int rval;
struct mtd_oob_ops vops;
- size_t verlen = nand->writesize + nand->oobsize;
+ size_t verlen = mtd->writesize + mtd->oobsize;
memcpy(&vops, ops, sizeof(vops));
@@ -489,9 +489,9 @@
if (!vops.datbuf)
return -ENOMEM;
- vops.oobbuf = vops.datbuf + nand->writesize;
+ vops.oobbuf = vops.datbuf + mtd->writesize;
- rval = mtd_read_oob(nand, ofs, &vops);
+ rval = mtd_read_oob(mtd, ofs, &vops);
if (!rval)
rval = memcmp(ops->datbuf, vops.datbuf, vops.len);
if (!rval)
@@ -510,17 +510,17 @@
* the contents of a buffer. The offset into the NAND must be
* page-aligned, and the function doesn't handle skipping bad blocks.
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param ofs offset in flash
* @param len buffer length
* @param buf buffer to read from
* @return 0 in case of success
*/
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf)
{
int rval = 0;
size_t verofs;
- size_t verlen = nand->writesize;
+ size_t verlen = mtd->writesize;
uint8_t *verbuf = memalign(ARCH_DMA_MINALIGN, verlen);
if (!verbuf)
@@ -529,8 +529,8 @@
/* Read the NAND back in page-size groups to limit malloc size */
for (verofs = ofs; verofs < ofs + len;
verofs += verlen, buf += verlen) {
- verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs));
- rval = nand_read(nand, verofs, &verlen, verbuf);
+ verlen = min(mtd->writesize, (uint32_t)(ofs + len - verofs));
+ rval = nand_read(mtd, verofs, &verlen, verbuf);
if (!rval || (rval == -EUCLEAN))
rval = memcmp(buf, verbuf, verlen);
@@ -558,7 +558,7 @@
* beyond the limit we are passed, length is set to 0 and actual is set
* to the required length.
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param offset offset in flash
* @param length buffer length
* @param actual set to size required to write length worth of
@@ -569,8 +569,8 @@
* @param flags flags modifying the behaviour of the write to NAND
* @return 0 in case of success
*/
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
- size_t *actual, loff_t lim, u_char *buffer, int flags)
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+ size_t *actual, loff_t lim, u_char *buffer, int flags)
{
int rval = 0, blocksize;
size_t left_to_write = *length;
@@ -581,7 +581,7 @@
if (actual)
*actual = 0;
- blocksize = nand->erasesize;
+ blocksize = mtd->erasesize;
/*
* nand_write() handles unaligned, partial page writes.
@@ -594,13 +594,13 @@
* you should only start a block skipping access at a
* partition boundary). So don't try to handle that.
*/
- if ((offset & (nand->writesize - 1)) != 0) {
+ if ((offset & (mtd->writesize - 1)) != 0) {
printf("Attempt to write non page-aligned data\n");
*length = 0;
return -EINVAL;
}
- need_skip = check_skip_len(nand, offset, *length, &used_for_write);
+ need_skip = check_skip_len(mtd, offset, *length, &used_for_write);
if (actual)
*actual = used_for_write;
@@ -618,10 +618,10 @@
}
if (!need_skip && !(flags & WITH_DROP_FFS)) {
- rval = nand_write(nand, offset, length, buffer);
+ rval = nand_write(mtd, offset, length, buffer);
if ((flags & WITH_WR_VERIFY) && !rval)
- rval = nand_verify(nand, offset, *length, buffer);
+ rval = nand_verify(mtd, offset, *length, buffer);
if (rval == 0)
return 0;
@@ -633,15 +633,15 @@
}
while (left_to_write > 0) {
- size_t block_offset = offset & (nand->erasesize - 1);
+ size_t block_offset = offset & (mtd->erasesize - 1);
size_t write_size, truncated_write_size;
WATCHDOG_RESET();
- if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+ if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
printf("Skip bad block 0x%08llx\n",
- offset & ~(nand->erasesize - 1));
- offset += nand->erasesize - block_offset;
+ offset & ~(mtd->erasesize - 1));
+ offset += mtd->erasesize - block_offset;
continue;
}
@@ -653,15 +653,15 @@
truncated_write_size = write_size;
#ifdef CONFIG_CMD_NAND_TRIMFFS
if (flags & WITH_DROP_FFS)
- truncated_write_size = drop_ffs(nand, p_buffer,
+ truncated_write_size = drop_ffs(mtd, p_buffer,
&write_size);
#endif
- rval = nand_write(nand, offset, &truncated_write_size,
+ rval = nand_write(mtd, offset, &truncated_write_size,
p_buffer);
if ((flags & WITH_WR_VERIFY) && !rval)
- rval = nand_verify(nand, offset,
+ rval = nand_verify(mtd, offset,
truncated_write_size, p_buffer);
offset += write_size;
@@ -693,7 +693,7 @@
* the limit we are passed, length is set to 0 and actual is set to the
* required length.
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param offset offset in flash
* @param length buffer length, on return holds number of read bytes
* @param actual set to size required to read length worth of buffer or 0
@@ -703,8 +703,8 @@
* @param buffer buffer to write to
* @return 0 in case of success
*/
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
- size_t *actual, loff_t lim, u_char *buffer)
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+ size_t *actual, loff_t lim, u_char *buffer)
{
int rval;
size_t left_to_read = *length;
@@ -712,7 +712,7 @@
u_char *p_buffer = buffer;
int need_skip;
- if ((offset & (nand->writesize - 1)) != 0) {
+ if ((offset & (mtd->writesize - 1)) != 0) {
printf("Attempt to read non page-aligned data\n");
*length = 0;
if (actual)
@@ -720,7 +720,7 @@
return -EINVAL;
}
- need_skip = check_skip_len(nand, offset, *length, &used_for_read);
+ need_skip = check_skip_len(mtd, offset, *length, &used_for_read);
if (actual)
*actual = used_for_read;
@@ -738,7 +738,7 @@
}
if (!need_skip) {
- rval = nand_read(nand, offset, length, buffer);
+ rval = nand_read(mtd, offset, length, buffer);
if (!rval || rval == -EUCLEAN)
return 0;
@@ -749,24 +749,24 @@
}
while (left_to_read > 0) {
- size_t block_offset = offset & (nand->erasesize - 1);
+ size_t block_offset = offset & (mtd->erasesize - 1);
size_t read_length;
WATCHDOG_RESET();
- if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+ if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
printf("Skipping bad block 0x%08llx\n",
- offset & ~(nand->erasesize - 1));
- offset += nand->erasesize - block_offset;
+ offset & ~(mtd->erasesize - 1));
+ offset += mtd->erasesize - block_offset;
continue;
}
- if (left_to_read < (nand->erasesize - block_offset))
+ if (left_to_read < (mtd->erasesize - block_offset))
read_length = left_to_read;
else
- read_length = nand->erasesize - block_offset;
+ read_length = mtd->erasesize - block_offset;
- rval = nand_read(nand, offset, &read_length, p_buffer);
+ rval = nand_read(mtd, offset, &read_length, p_buffer);
if (rval && rval != -EUCLEAN) {
printf("NAND read from offset %llx failed %d\n",
offset, rval);
@@ -812,57 +812,57 @@
* This is useful to determine if a block that caused a write error is still
* good or should be marked as bad.
*
- * @param nand NAND device
+ * @param mtd nand mtd instance
* @param offset offset in flash
* @return 0 if the block is still good
*/
-int nand_torture(nand_info_t *nand, loff_t offset)
+int nand_torture(struct mtd_info *mtd, loff_t offset)
{
u_char patterns[] = {0xa5, 0x5a, 0x00};
struct erase_info instr = {
.mtd = nand,
.addr = offset,
- .len = nand->erasesize,
+ .len = mtd->erasesize,
};
size_t retlen;
int err, ret = -1, i, patt_count;
u_char *buf;
- if ((offset & (nand->erasesize - 1)) != 0) {
+ if ((offset & (mtd->erasesize - 1)) != 0) {
puts("Attempt to torture a block at a non block-aligned offset\n");
return -EINVAL;
}
- if (offset + nand->erasesize > nand->size) {
+ if (offset + mtd->erasesize > mtd->size) {
puts("Attempt to torture a block outside the flash area\n");
return -EINVAL;
}
patt_count = ARRAY_SIZE(patterns);
- buf = malloc_cache_aligned(nand->erasesize);
+ buf = malloc_cache_aligned(mtd->erasesize);
if (buf == NULL) {
puts("Out of memory for erase block buffer\n");
return -ENOMEM;
}
for (i = 0; i < patt_count; i++) {
- err = nand->erase(nand, &instr);
+ err = mtd_erase(mtd, &instr);
if (err) {
printf("%s: erase() failed for block at 0x%llx: %d\n",
- nand->name, instr.addr, err);
+ mtd->name, instr.addr, err);
goto out;
}
/* Make sure the block contains only 0xff bytes */
- err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
- if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+ err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
+ if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
printf("%s: read() failed for block at 0x%llx: %d\n",
- nand->name, instr.addr, err);
+ mtd->name, instr.addr, err);
goto out;
}
- err = check_pattern(buf, 0xff, nand->erasesize);
+ err = check_pattern(buf, 0xff, mtd->erasesize);
if (!err) {
printf("Erased block at 0x%llx, but a non-0xff byte was found\n",
offset);
@@ -871,22 +871,22 @@
}
/* Write a pattern and check it */
- memset(buf, patterns[i], nand->erasesize);
- err = nand->write(nand, offset, nand->erasesize, &retlen, buf);
- if (err || retlen != nand->erasesize) {
+ memset(buf, patterns[i], mtd->erasesize);
+ err = mtd_write(mtd, offset, mtd->erasesize, &retlen, buf);
+ if (err || retlen != mtd->erasesize) {
printf("%s: write() failed for block at 0x%llx: %d\n",
- nand->name, instr.addr, err);
+ mtd->name, instr.addr, err);
goto out;
}
- err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
- if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+ err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
+ if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
printf("%s: read() failed for block at 0x%llx: %d\n",
- nand->name, instr.addr, err);
+ mtd->name, instr.addr, err);
goto out;
}
- err = check_pattern(buf, patterns[i], nand->erasesize);
+ err = check_pattern(buf, patterns[i], mtd->erasesize);
if (!err) {
printf("Pattern 0x%.2x checking failed for block at "
"0x%llx\n", patterns[i], offset);
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 8a68cb0..0a9849e 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -1,6 +1,6 @@
/*
* Overview:
- * Platform independend driver for NDFC (NanD Flash Controller)
+ * Platform independent driver for NDFC (NanD Flash Controller)
* integrated into IBM/AMCC PPC4xx cores
*
* (C) Copyright 2006-2009
@@ -37,7 +37,7 @@
static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
if (cmd == NAND_CMD_NONE)
@@ -51,7 +51,7 @@
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
@@ -59,7 +59,7 @@
static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
u32 ccr;
@@ -71,7 +71,7 @@
static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
const u_char *dat, u_char *ecc_code)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
u32 ecc;
u8 *p = (u8 *)&ecc;
@@ -96,7 +96,7 @@
*/
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
uint32_t *p = (uint32_t *) buf;
@@ -110,7 +110,7 @@
*/
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
uint32_t *p = (uint32_t *) buf;
@@ -124,7 +124,7 @@
static uint8_t ndfc_read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
return (uint8_t) readw(chip->IO_ADDR_R);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 6a45d28..37c4341 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -58,8 +58,8 @@
static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
uint32_t ctrl)
{
- register struct nand_chip *this = mtd->priv;
- struct omap_nand_info *info = this->priv;
+ register struct nand_chip *this = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(this);
int cs = info->cs;
/*
@@ -85,8 +85,8 @@
/* Check wait pin as dev ready indicator */
static int omap_dev_ready(struct mtd_info *mtd)
{
- register struct nand_chip *this = mtd->priv;
- struct omap_nand_info *info = this->priv;
+ register struct nand_chip *this = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(this);
return gpmc_cfg->status & (1 << (8 + info->ws));
}
@@ -163,7 +163,7 @@
return 0;
printf("Error: Bad compare! failed\n");
/* detected 2 bit error */
- return -1;
+ return -EBADMSG;
}
}
return 0;
@@ -177,8 +177,8 @@
__maybe_unused
static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
- struct nand_chip *nand = mtd->priv;
- struct omap_nand_info *info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(nand);
unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned int ecc_algo = 0;
unsigned int bch_type = 0;
@@ -262,8 +262,8 @@
static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
uint8_t *ecc_code)
{
- struct nand_chip *chip = mtd->priv;
- struct omap_nand_info *info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(chip);
uint32_t *ptr, val = 0;
int8_t i = 0, j;
@@ -392,7 +392,7 @@
{
int ret;
uint32_t cnt;
- struct omap_nand_info *info = chip->priv;
+ struct omap_nand_info *info = nand_get_controller_data(chip);
ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
if (ret < 0)
@@ -417,7 +417,7 @@
static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
if (chip->options & NAND_BUSWIDTH_16)
nand_read_buf16(mtd, buf, len);
@@ -429,7 +429,7 @@
{
int ret;
uint32_t head, tail;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
/*
* If the destination buffer is unaligned, start with reading
@@ -491,8 +491,8 @@
static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
- struct nand_chip *chip = mtd->priv;
- struct omap_nand_info *info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
uint32_t error_count = 0, error_max;
uint32_t error_loc[ELM_MAX_ERROR_COUNT];
@@ -652,8 +652,8 @@
int i, count;
/* cannot correct more than 8 errors */
unsigned int errloc[8];
- struct nand_chip *chip = mtd->priv;
- struct omap_nand_info *info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(chip);
count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
NULL, errloc);
@@ -691,8 +691,8 @@
*/
static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct omap_nand_info *info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(chip);
if (info->control) {
free_bch(info->control);
@@ -710,7 +710,7 @@
*/
static int omap_select_ecc_scheme(struct nand_chip *nand,
enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
- struct omap_nand_info *info = nand->priv;
+ struct omap_nand_info *info = nand_get_controller_data(nand);
struct nand_ecclayout *ecclayout = &omap_ecclayout;
int eccsteps = pagesize / SECTOR_BYTES;
int i;
@@ -898,13 +898,13 @@
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ !nand_info[nand_curr_device]->name) {
printf("nand: error: no NAND devices found\n");
return -ENODEV;
}
- mtd = &nand_info[nand_curr_device];
- nand = mtd->priv;
+ mtd = nand_info[nand_curr_device];
+ nand = mtd_to_nand(mtd);
nand->options |= NAND_OWN_BUFFERS;
nand->options &= ~NAND_SUBPAGE_READ;
/* Setup the ecc configurations again */
@@ -994,7 +994,7 @@
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
omap_nand_info[cs].ws = wscfg[cs];
- nand->priv = &omap_nand_info[cs];
+ nand_set_controller_data(nand, &omap_nand_info[cs]);
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
nand->chip_delay = 100;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d529467..d3ac539 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -900,7 +900,8 @@
static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
int column, int page_addr)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
int exec_cmd;
@@ -960,7 +961,8 @@
const unsigned command,
int column, int page_addr)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
int exec_cmd, ext_cmd_type;
@@ -1079,7 +1081,8 @@
}
static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
{
chip->write_buf(mtd, buf, mtd->writesize);
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -1091,7 +1094,7 @@
struct nand_chip *chip, uint8_t *buf, int oob_required,
int page)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
chip->read_buf(mtd, buf, mtd->writesize);
@@ -1117,7 +1120,8 @@
static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
char retval = 0xFF;
@@ -1130,7 +1134,8 @@
static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
u16 retval = 0xFFFF;
@@ -1143,7 +1148,8 @@
static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
@@ -1154,7 +1160,8 @@
static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
const uint8_t *buf, int len)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
@@ -1169,7 +1176,8 @@
static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
if (info->need_wait) {
@@ -1210,7 +1218,7 @@
{
struct pxa3xx_nand_host *host = info->host[info->cs];
struct mtd_info *mtd = host->mtd;
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
@@ -1262,7 +1270,7 @@
int ret;
mtd = info->host[info->cs]->mtd;
- chip = mtd->priv;
+ chip = mtd_to_nand(mtd);
/* configure default flash values */
info->reg_ndcr = 0x0; /* enable all interrupts */
@@ -1354,10 +1362,10 @@
static int pxa3xx_nand_scan(struct mtd_info *mtd)
{
- struct pxa3xx_nand_host *host = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
struct pxa3xx_nand_info *info = host->info_data;
struct pxa3xx_nand_platform_data *pdata = info->pdata;
- struct nand_chip *chip = mtd->priv;
int ret;
uint16_t ecc_strength, ecc_step;
@@ -1477,16 +1485,15 @@
info->variant = pxa3xx_nand_get_variant();
for (cs = 0; cs < pdata->num_cs; cs++) {
- mtd = &nand_info[cs];
chip = (struct nand_chip *)
((u8 *)&info[1] + sizeof(*host) * cs);
+ mtd = nand_to_mtd(chip);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
host->mtd = mtd;
host->cs = cs;
host->info_data = info;
host->read_id_bytes = 4;
- mtd->priv = host;
mtd->owner = THIS_MODULE;
chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
@@ -1573,8 +1580,10 @@
continue;
}
+ if (nand_register(cs, mtd))
+ continue;
+
- if (!ret)
- probe_success = 1;
+ probe_success = 1;
}
if (!probe_success)
@@ -1601,6 +1610,4 @@
ret = pxa3xx_nand_probe(info);
if (ret)
return;
-
- nand_register(0);
}
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index b3a2a60..dd742a6 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -31,7 +31,7 @@
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
- struct nand_chip *this = mtd->priv;
+ struct nand_chip *this = mtd_to_nand(mtd);
for (i = 0; i < len; i++)
buf[i] = readb(this->IO_ADDR_R);
@@ -40,7 +40,7 @@
static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
@@ -104,7 +104,7 @@
return 0;
printf("s3c24x0_nand_correct_data: not implemented\n");
- return -1;
+ return -EBADMSG;
}
#endif
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index a77db7b..2032f65 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -143,10 +143,10 @@
*/
static uint8_t read_byte(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_drv *info;
- info = (struct nand_drv *)chip->priv;
+ info = (struct nand_drv *)nand_get_controller_data(chip);
writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
&info->reg->command);
@@ -169,8 +169,8 @@
{
int i, s;
unsigned int reg;
- struct nand_chip *chip = mtd->priv;
- struct nand_drv *info = (struct nand_drv *)chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
for (i = 0; i < len; i += 4) {
s = (len - i) > 4 ? 4 : len - i;
@@ -194,11 +194,11 @@
*/
static int nand_dev_ready(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
int reg_val;
struct nand_drv *info;
- info = (struct nand_drv *)chip->priv;
+ info = (struct nand_drv *)nand_get_controller_data(chip);
reg_val = readl(&info->reg->status);
if (reg_val & STATUS_RBSY0)
@@ -245,10 +245,10 @@
static void nand_command(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
- struct nand_chip *chip = mtd->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_drv *info;
- info = (struct nand_drv *)chip->priv;
+ info = (struct nand_drv *)nand_get_controller_data(chip);
/*
* Write out the command to the device.
@@ -512,7 +512,7 @@
return -EINVAL;
}
- info = (struct nand_drv *)chip->priv;
+ info = (struct nand_drv *)nand_get_controller_data(chip);
config = &info->config;
if (set_bus_width_page_size(config, ®_val))
return -EINVAL;
@@ -657,16 +657,9 @@
* @param buf data buffer
*/
static int nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
{
- int page;
- struct nand_drv *info;
-
- info = (struct nand_drv *)chip->priv;
-
- page = (readl(&info->reg->addr_reg1) >> 16) |
- (readl(&info->reg->addr_reg2) << 16);
-
nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
return 0;
}
@@ -697,15 +690,9 @@
* @param buf data buffer
*/
static int nand_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
+ struct nand_chip *chip, const uint8_t *buf,
+ int oob_required, int page)
{
- int page;
- struct nand_drv *info;
-
- info = (struct nand_drv *)chip->priv;
- page = (readl(&info->reg->addr_reg1) >> 16) |
- (readl(&info->reg->addr_reg2) << 16);
-
nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
return 0;
}
@@ -734,7 +721,7 @@
if (((int)chip->oob_poi) & 0x03)
return -EINVAL;
- info = (struct nand_drv *)chip->priv;
+ info = (struct nand_drv *)nand_get_controller_data(chip);
if (set_bus_width_page_size(&info->config, ®_val))
return -EINVAL;
@@ -963,7 +950,7 @@
nand->ecc.strength = 1;
nand->select_chip = nand_select_chip;
nand->dev_ready = nand_dev_ready;
- nand->priv = &nand_ctrl;
+ nand_set_controller_data(nand, &nand_ctrl);
/* Disable subpage writes as we do not provide ecc->hwctl */
nand->options |= NAND_NO_SUBPAGE_WRITE;
@@ -976,8 +963,7 @@
dm_gpio_set_value(&config->wp_gpio, 1);
- our_mtd = &nand_info[devnum];
- our_mtd->priv = nand;
+ our_mtd = nand_to_mtd(nand);
ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
if (ret)
return ret;
@@ -989,7 +975,7 @@
if (ret)
return ret;
- ret = nand_register(devnum);
+ ret = nand_register(devnum, our_mtd);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 1faec5e..f99bdaf 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -146,7 +146,6 @@
};
struct vf610_nfc {
- struct mtd_info *mtd;
struct nand_chip chip;
void __iomem *regs;
uint buf_offset;
@@ -155,8 +154,7 @@
enum vf610_nfc_alt_buf alt_buf;
};
-#define mtd_to_nfc(_mtd) \
- (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
+#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
#define ECC_HW_MODE ECC_45_BYTE
@@ -608,7 +606,7 @@
* ECC will be calculated automatically
*/
static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf, int oob_required, int page)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
@@ -630,7 +628,7 @@
static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
{
- struct mtd_info *mtd = &nand_info[devnum];
+ struct mtd_info *mtd;
struct nand_chip *chip;
struct vf610_nfc *nfc;
int err = 0;
@@ -653,8 +651,8 @@
chip = &nfc->chip;
nfc->regs = addr;
- mtd->priv = chip;
- chip->priv = nfc;
+ mtd = nand_to_mtd(chip);
+ nand_set_controller_data(chip, nfc);
if (cfg.width == 16)
chip->options |= NAND_BUSWIDTH_16;
@@ -753,7 +751,7 @@
if (err)
return err;
- err = nand_register(devnum);
+ err = nand_register(devnum, mtd);
if (err)
return err;
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..c577d9e 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -67,6 +67,7 @@
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index fa0e799..64d4e0f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1072,7 +1072,8 @@
* sector that is not overlaid by the parameter sectors.
* The uniform sector erase command has no effect on parameter sectors.
*/
- if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+ (ext_jedec & 0xff00) == 0x4d00) {
int ret;
u8 id[6];
@@ -1146,7 +1147,7 @@
* have 256b pages.
*/
if (ext_jedec == 0x4d00) {
- if ((jedec == 0x0215) || (jedec == 0x216))
+ if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
flash->page_size = 256;
else
flash->page_size = 512;
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 46c98a9..bac1e85 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -48,6 +48,18 @@
}
#endif
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ struct spi_flash *flash = load->dev;
+ ulong ret;
+
+ ret = spi_flash_read(flash, sector, count, buf);
+ if (!ret)
+ return count;
+ else
+ return 0;
+}
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
@@ -85,11 +97,26 @@
if (err)
return err;
- err = spl_parse_image_header(header);
- if (err)
- return err;
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.dev = flash;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_spi_fit_read;
+ err = spl_load_simple_fit(&load,
+ CONFIG_SYS_SPI_U_BOOT_OFFS,
+ header);
+ } else {
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ spl_image.size,
+ (void *)spl_image.load_addr);
+ }
}
return err;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 91b7690..c1cb689 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -46,6 +46,15 @@
if NETDEVICES
+config AG7XXX
+ bool "Atheros AG7xxx Ethernet MAC support"
+ depends on DM_ETH && ARCH_ATH79
+ select PHYLIB
+ help
+ This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
+ present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.
+
+
config ALTERA_TSE
bool "Altera Triple-Speed Ethernet MAC support"
depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d5e4a97..5702592 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
+obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
new file mode 100644
index 0000000..346f138
--- /dev/null
+++ b/drivers/net/ag7xxx.c
@@ -0,0 +1,980 @@
+/*
+ * Atheros AR71xx / AR9xxx GMAC driver
+ *
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/mii.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+#include <mach/ath79.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ag7xxx_model {
+ AG7XXX_MODEL_AG933X,
+ AG7XXX_MODEL_AG934X,
+};
+
+#define AG7XXX_ETH_CFG1 0x00
+#define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
+#define AG7XXX_ETH_CFG1_RX_RST BIT(19)
+#define AG7XXX_ETH_CFG1_TX_RST BIT(18)
+#define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
+#define AG7XXX_ETH_CFG1_RX_EN BIT(2)
+#define AG7XXX_ETH_CFG1_TX_EN BIT(0)
+
+#define AG7XXX_ETH_CFG2 0x04
+#define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
+#define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
+#define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
+#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
+#define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
+#define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
+#define AG7XXX_ETH_CFG2_FDX BIT(0)
+
+#define AG7XXX_ETH_MII_MGMT_CFG 0x20
+#define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
+
+#define AG7XXX_ETH_MII_MGMT_CMD 0x24
+#define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
+
+#define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
+#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
+
+#define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
+
+#define AG7XXX_ETH_MII_MGMT_STATUS 0x30
+
+#define AG7XXX_ETH_MII_MGMT_IND 0x34
+#define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
+#define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
+
+#define AG7XXX_ETH_ADDR1 0x40
+#define AG7XXX_ETH_ADDR2 0x44
+
+#define AG7XXX_ETH_FIFO_CFG_0 0x48
+#define AG7XXX_ETH_FIFO_CFG_1 0x4c
+#define AG7XXX_ETH_FIFO_CFG_2 0x50
+#define AG7XXX_ETH_FIFO_CFG_3 0x54
+#define AG7XXX_ETH_FIFO_CFG_4 0x58
+#define AG7XXX_ETH_FIFO_CFG_5 0x5c
+
+#define AG7XXX_ETH_DMA_TX_CTRL 0x180
+#define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
+
+#define AG7XXX_ETH_DMA_TX_DESC 0x184
+
+#define AG7XXX_ETH_DMA_TX_STATUS 0x188
+
+#define AG7XXX_ETH_DMA_RX_CTRL 0x18c
+#define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
+
+#define AG7XXX_ETH_DMA_RX_DESC 0x190
+
+#define AG7XXX_ETH_DMA_RX_STATUS 0x194
+
+/* Custom register at 0x18070000 */
+#define AG7XXX_GMAC_ETH_CFG 0x00
+#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
+#define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
+#define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
+#define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
+
+#define CONFIG_TX_DESCR_NUM 8
+#define CONFIG_RX_DESCR_NUM 8
+#define CONFIG_ETH_BUFSIZE 2048
+#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+/* DMA descriptor. */
+struct ag7xxx_dma_desc {
+ u32 data_addr;
+#define AG7XXX_DMADESC_IS_EMPTY BIT(31)
+#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
+#define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
+#define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
+ u32 config;
+ u32 next_desc;
+ u32 _pad[5];
+};
+
+struct ar7xxx_eth_priv {
+ struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+ struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+ char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+ char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+ void __iomem *regs;
+ void __iomem *phyregs;
+
+ struct eth_device *dev;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+
+ u32 interface;
+ u32 tx_currdescnum;
+ u32 rx_currdescnum;
+ enum ag7xxx_model model;
+};
+
+/*
+ * Switch and MDIO access
+ */
+static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
+{
+ struct ar7xxx_eth_priv *priv = bus->priv;
+ void __iomem *regs = priv->phyregs;
+ int ret;
+
+ writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+ writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+ regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+ writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
+ regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+ ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+ if (ret)
+ return ret;
+
+ *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
+ writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+ return 0;
+}
+
+static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
+{
+ struct ar7xxx_eth_priv *priv = bus->priv;
+ void __iomem *regs = priv->phyregs;
+ int ret;
+
+ writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+ regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+ writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
+
+ ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+ AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+
+ return ret;
+}
+
+static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
+{
+ struct ar7xxx_eth_priv *priv = bus->priv;
+ u32 phy_addr;
+ u32 reg_addr;
+ u32 phy_temp;
+ u32 reg_temp;
+ u16 rv = 0;
+ int ret;
+
+ if (priv->model == AG7XXX_MODEL_AG933X) {
+ phy_addr = 0x1f;
+ reg_addr = 0x10;
+ } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ phy_addr = 0x18;
+ reg_addr = 0x00;
+ } else
+ return -EINVAL;
+
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (ret)
+ return ret;
+
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+ *val = 0;
+
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
+ if (ret < 0)
+ return ret;
+ *val |= rv;
+
+ ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
+ if (ret < 0)
+ return ret;
+ *val |= (rv << 16);
+
+ return 0;
+}
+
+static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
+{
+ struct ar7xxx_eth_priv *priv = bus->priv;
+ u32 phy_addr;
+ u32 reg_addr;
+ u32 phy_temp;
+ u32 reg_temp;
+ int ret;
+
+ if (priv->model == AG7XXX_MODEL_AG933X) {
+ phy_addr = 0x1f;
+ reg_addr = 0x10;
+ } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ phy_addr = 0x18;
+ reg_addr = 0x00;
+ } else
+ return -EINVAL;
+
+ ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+ if (ret)
+ return ret;
+
+ phy_temp = ((reg >> 6) & 0x7) | 0x10;
+ reg_temp = (reg >> 1) & 0x1e;
+
+ /*
+ * The switch on AR933x has some special register behavior, which
+ * expects particular write order of their nibbles:
+ * 0x40 ..... MSB first, LSB second
+ * 0x50 ..... MSB first, LSB second
+ * 0x98 ..... LSB first, MSB second
+ * others ... don't care
+ */
+ if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+ if (ret < 0)
+ return ret;
+
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+ if (ret < 0)
+ return ret;
+
+ ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
+{
+ u32 data;
+
+ /* Dummy read followed by PHY read/write command. */
+ ag7xxx_switch_reg_read(bus, 0x98, &data);
+ data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
+ ag7xxx_switch_reg_write(bus, 0x98, data);
+
+ /* Wait for operation to finish */
+ do {
+ ag7xxx_switch_reg_read(bus, 0x98, &data);
+ } while (data & BIT(31));
+
+ return data & 0xffff;
+}
+
+static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
+}
+
+static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ ag7xxx_mdio_rw(bus, addr, reg, val);
+ return 0;
+}
+
+/*
+ * DMA ring handlers
+ */
+static void ag7xxx_dma_clean_tx(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct ag7xxx_dma_desc *curr, *next;
+ u32 start, end;
+ int i;
+
+ for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+ curr = &priv->tx_mac_descrtable[i];
+ next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
+
+ curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
+ curr->config = AG7XXX_DMADESC_IS_EMPTY;
+ curr->next_desc = virt_to_phys(next);
+ }
+
+ priv->tx_currdescnum = 0;
+
+ /* Cache: Flush descriptors, don't care about buffers. */
+ start = (u32)(&priv->tx_mac_descrtable[0]);
+ end = start + sizeof(priv->tx_mac_descrtable);
+ flush_dcache_range(start, end);
+}
+
+static void ag7xxx_dma_clean_rx(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct ag7xxx_dma_desc *curr, *next;
+ u32 start, end;
+ int i;
+
+ for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+ curr = &priv->rx_mac_descrtable[i];
+ next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
+
+ curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
+ curr->config = AG7XXX_DMADESC_IS_EMPTY;
+ curr->next_desc = virt_to_phys(next);
+ }
+
+ priv->rx_currdescnum = 0;
+
+ /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
+ start = (u32)(&priv->rx_mac_descrtable[0]);
+ end = start + sizeof(priv->rx_mac_descrtable);
+ flush_dcache_range(start, end);
+ invalidate_dcache_range(start, end);
+
+ start = (u32)&priv->rxbuffs;
+ end = start + sizeof(priv->rxbuffs);
+ invalidate_dcache_range(start, end);
+}
+
+/*
+ * Ethernet I/O
+ */
+static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct ag7xxx_dma_desc *curr;
+ u32 start, end;
+
+ curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
+
+ /* Cache: Invalidate descriptor. */
+ start = (u32)curr;
+ end = start + sizeof(*curr);
+ invalidate_dcache_range(start, end);
+
+ if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
+ printf("ag7xxx: Out of TX DMA descriptors!\n");
+ return -EPERM;
+ }
+
+ /* Copy the packet into the data buffer. */
+ memcpy(phys_to_virt(curr->data_addr), packet, length);
+ curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+ /* Cache: Flush descriptor, Flush buffer. */
+ start = (u32)curr;
+ end = start + sizeof(*curr);
+ flush_dcache_range(start, end);
+ start = (u32)phys_to_virt(curr->data_addr);
+ end = start + length;
+ flush_dcache_range(start, end);
+
+ /* Load the DMA descriptor and start TX DMA. */
+ writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
+ priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+
+ /* Switch to next TX descriptor. */
+ priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
+
+ return 0;
+}
+
+static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct ag7xxx_dma_desc *curr;
+ u32 start, end, length;
+
+ curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+ /* Cache: Invalidate descriptor. */
+ start = (u32)curr;
+ end = start + sizeof(*curr);
+ invalidate_dcache_range(start, end);
+
+ /* No packets received. */
+ if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
+ return -EAGAIN;
+
+ length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+ /* Cache: Invalidate buffer. */
+ start = (u32)phys_to_virt(curr->data_addr);
+ end = start + length;
+ invalidate_dcache_range(start, end);
+
+ /* Receive one packet and return length. */
+ *packetp = phys_to_virt(curr->data_addr);
+ return length;
+}
+
+static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct ag7xxx_dma_desc *curr;
+ u32 start, end;
+
+ curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+ curr->config = AG7XXX_DMADESC_IS_EMPTY;
+
+ /* Cache: Flush descriptor. */
+ start = (u32)curr;
+ end = start + sizeof(*curr);
+ flush_dcache_range(start, end);
+
+ /* Switch to next RX descriptor. */
+ priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
+
+ return 0;
+}
+
+static int ag7xxx_eth_start(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+ /* FIXME: Check if link up */
+
+ /* Clear the DMA rings. */
+ ag7xxx_dma_clean_tx(dev);
+ ag7xxx_dma_clean_rx(dev);
+
+ /* Load DMA descriptors and start the RX DMA. */
+ writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
+ priv->regs + AG7XXX_ETH_DMA_TX_DESC);
+ writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
+ priv->regs + AG7XXX_ETH_DMA_RX_DESC);
+ writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
+ priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+
+ return 0;
+}
+
+static void ag7xxx_eth_stop(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+ /* Stop the TX DMA. */
+ writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+ wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+ 1000, 0);
+
+ /* Stop the RX DMA. */
+ writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+ wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+ 1000, 0);
+}
+
+/*
+ * Hardware setup
+ */
+static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ unsigned char *mac = pdata->enetaddr;
+ u32 macid_lo, macid_hi;
+
+ macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
+ macid_lo = (mac[5] << 16) | (mac[4] << 24);
+
+ writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
+ writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
+
+ return 0;
+}
+
+static void ag7xxx_hw_setup(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ u32 speed;
+
+ setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
+ AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
+ AG7XXX_ETH_CFG1_SOFT_RST);
+
+ mdelay(10);
+
+ writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
+ priv->regs + AG7XXX_ETH_CFG1);
+
+ if (priv->interface == PHY_INTERFACE_MODE_RMII)
+ speed = AG7XXX_ETH_CFG2_IF_10_100;
+ else
+ speed = AG7XXX_ETH_CFG2_IF_1000;
+
+ clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
+ AG7XXX_ETH_CFG2_IF_SPEED_MASK,
+ speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
+ AG7XXX_ETH_CFG2_LEN_CHECK);
+
+ writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+ writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+
+ writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
+ setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
+ writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+ writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+ writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
+ writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
+}
+
+static int ag7xxx_mii_get_div(void)
+{
+ ulong freq = get_bus_freq(0);
+
+ switch (freq / 1000000) {
+ case 150: return 0x7;
+ case 175: return 0x5;
+ case 200: return 0x4;
+ case 210: return 0x9;
+ case 220: return 0x9;
+ default: return 0x7;
+ }
+}
+
+static int ag7xxx_mii_setup(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int i, ret, div = ag7xxx_mii_get_div();
+ u32 reg;
+
+ if (priv->model == AG7XXX_MODEL_AG933X) {
+ /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
+ if (priv->interface == PHY_INTERFACE_MODE_RMII)
+ return 0;
+ }
+
+ if (priv->model == AG7XXX_MODEL_AG934X) {
+ writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4,
+ priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+ writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+ return 0;
+ }
+
+ for (i = 0; i < 10; i++) {
+ writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
+ priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+ writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+
+ /* Check the switch */
+ ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®);
+ if (ret)
+ continue;
+
+ if (reg != 0x18007fff)
+ continue;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int ag933x_phy_setup_wan(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+ /* Configure switch port 4 (GMAC0) */
+ return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
+}
+
+static int ag933x_phy_setup_lan(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int i, ret;
+ u32 reg;
+
+ /* Reset the switch */
+ ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
+ if (ret)
+ return ret;
+ reg |= BIT(31);
+ ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
+ if (ret)
+ return ret;
+
+ do {
+ ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
+ if (ret)
+ return ret;
+ } while (reg & BIT(31));
+
+ /* Configure switch ports 0...3 (GMAC1) */
+ for (i = 0; i < 4; i++) {
+ ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
+ if (ret)
+ return ret;
+ }
+
+ /* Enable CPU port */
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 4; i++) {
+ ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
+ if (ret)
+ return ret;
+ }
+
+ /* QM Control */
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
+ if (ret)
+ return ret;
+
+ /* Disable Atheros header */
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
+ if (ret)
+ return ret;
+
+ /* Tag priority mapping */
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
+ if (ret)
+ return ret;
+
+ /* Enable ARP packets to the CPU */
+ ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
+ if (ret)
+ return ret;
+ reg |= 0x100000;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
+ ADVERTISE_PAUSE_ASYM);
+ if (ret)
+ return ret;
+
+ if (priv->model == AG7XXX_MODEL_AG934X) {
+ ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
+ ADVERTISE_1000FULL);
+ if (ret)
+ return ret;
+ }
+
+ return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
+ BMCR_ANENABLE | BMCR_RESET);
+}
+
+static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ do {
+ ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ mdelay(10);
+ } while (ret & BMCR_RESET);
+
+ return 0;
+}
+
+static int ag933x_phy_setup_common(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int i, ret, phymax;
+
+ if (priv->model == AG7XXX_MODEL_AG933X)
+ phymax = 4;
+ else if (priv->model == AG7XXX_MODEL_AG934X)
+ phymax = 5;
+ else
+ return -EINVAL;
+
+ if (priv->interface == PHY_INTERFACE_MODE_RMII) {
+ ret = ag933x_phy_setup_reset_set(dev, phymax);
+ if (ret)
+ return ret;
+
+ ret = ag933x_phy_setup_reset_fin(dev, phymax);
+ if (ret)
+ return ret;
+
+ /* Read out link status */
+ ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+ }
+
+ /* Switch ports */
+ for (i = 0; i < phymax; i++) {
+ ret = ag933x_phy_setup_reset_set(dev, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < phymax; i++) {
+ ret = ag933x_phy_setup_reset_fin(dev, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < phymax; i++) {
+ /* Read out link status */
+ ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ag934x_phy_setup(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int i, ret;
+ u32 reg;
+
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
+ if (ret)
+ return ret;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
+ if (ret)
+ return ret;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
+ if (ret)
+ return ret;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
+ if (ret)
+ return ret;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
+ if (ret)
+ return ret;
+
+ /* AR8327/AR8328 v1.0 fixup */
+ ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
+ if (ret)
+ return ret;
+ if ((reg & 0xffff) == 0x1201) {
+ for (i = 0; i < 5; i++) {
+ ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
+ if (ret)
+ return ret;
+ ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
+ if (ret)
+ return ret;
+ ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
+ if (ret)
+ return ret;
+ ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
+ if (ret)
+ return ret;
+ }
+ }
+
+ ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®);
+ if (ret)
+ return ret;
+ reg &= ~0x70000;
+ ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int ag7xxx_mac_probe(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ag7xxx_hw_setup(dev);
+ ret = ag7xxx_mii_setup(dev);
+ if (ret)
+ return ret;
+
+ ag7xxx_eth_write_hwaddr(dev);
+
+ if (priv->model == AG7XXX_MODEL_AG933X) {
+ if (priv->interface == PHY_INTERFACE_MODE_RMII)
+ ret = ag933x_phy_setup_wan(dev);
+ else
+ ret = ag933x_phy_setup_lan(dev);
+ } else if (priv->model == AG7XXX_MODEL_AG934X) {
+ ret = ag934x_phy_setup(dev);
+ } else {
+ return -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ return ag933x_phy_setup_common(dev);
+}
+
+static int ag7xxx_mdio_probe(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = ag7xxx_mdio_read;
+ bus->write = ag7xxx_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+
+ bus->priv = (void *)priv;
+
+ return mdio_register(bus);
+}
+
+static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
+{
+ int offset;
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy");
+ if (offset <= 0) {
+ debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
+ return -EINVAL;
+ }
+
+ offset = fdt_parent_offset(gd->fdt_blob, offset);
+ if (offset <= 0) {
+ debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
+ __func__, offset);
+ return -EINVAL;
+ }
+
+ offset = fdt_parent_offset(gd->fdt_blob, offset);
+ if (offset <= 0) {
+ debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
+ __func__, offset);
+ return -EINVAL;
+ }
+
+ return offset;
+}
+
+static int ag7xxx_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+ void __iomem *iobase, *phyiobase;
+ int ret, phyreg;
+
+ /* Decoding of convoluted PHY wiring on Atheros MIPS. */
+ ret = ag7xxx_get_phy_iface_offset(dev);
+ if (ret <= 0)
+ return ret;
+ phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
+
+ iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
+ phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
+
+ debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
+ __func__, iobase, phyiobase, priv);
+ priv->regs = iobase;
+ priv->phyregs = phyiobase;
+ priv->interface = pdata->phy_interface;
+ priv->model = dev_get_driver_data(dev);
+
+ ret = ag7xxx_mdio_probe(dev);
+ if (ret)
+ return ret;
+
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ ret = ag7xxx_mac_probe(dev);
+ debug("%s, ret=%d\n", __func__, ret);
+
+ return ret;
+}
+
+static int ag7xxx_eth_remove(struct udevice *dev)
+{
+ struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ return 0;
+}
+
+static const struct eth_ops ag7xxx_eth_ops = {
+ .start = ag7xxx_eth_start,
+ .send = ag7xxx_eth_send,
+ .recv = ag7xxx_eth_recv,
+ .free_pkt = ag7xxx_eth_free_pkt,
+ .stop = ag7xxx_eth_stop,
+ .write_hwaddr = ag7xxx_eth_write_hwaddr,
+};
+
+static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+ int ret;
+
+ pdata->iobase = dev_get_addr(dev);
+ pdata->phy_interface = -1;
+
+ /* Decoding of convoluted PHY wiring on Atheros MIPS. */
+ ret = ag7xxx_get_phy_iface_offset(dev);
+ if (ret <= 0)
+ return ret;
+
+ phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id ag7xxx_eth_ids[] = {
+ { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
+ { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
+ { }
+};
+
+U_BOOT_DRIVER(eth_ag7xxx) = {
+ .name = "eth_ag7xxx",
+ .id = UCLASS_ETH,
+ .of_match = ag7xxx_eth_ids,
+ .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
+ .probe = ag7xxx_eth_probe,
+ .remove = ag7xxx_eth_remove,
+ .ops = &ag7xxx_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ca58f34..8858f07 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -24,7 +24,12 @@
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
+#ifdef CONFIG_DM_ETH
+ struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
struct eth_mac_regs *mac_p = bus->priv;
+#endif
ulong start;
u16 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
@@ -47,7 +52,12 @@
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
+#ifdef CONFIG_DM_ETH
+ struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
struct eth_mac_regs *mac_p = bus->priv;
+#endif
ulong start;
u16 miiaddr;
int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
@@ -69,8 +79,42 @@
return ret;
}
+
+#if CONFIG_DM_ETH
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ struct dw_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ /* reset the phy */
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[2]);
+
+ return 0;
+}
+#endif
-static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
+static int dw_mdio_init(const char *name, void *priv)
{
struct mii_dev *bus = mdio_alloc();
@@ -82,8 +126,11 @@
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
snprintf(bus->name, sizeof(bus->name), "%s", name);
+#ifdef CONFIG_DM_ETH
+ bus->reset = dw_mdio_reset;
+#endif
- bus->priv = (void *)mac_regs_p;
+ bus->priv = priv;
return mdio_register(bus);
}
@@ -98,8 +145,8 @@
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p->dmamac_next = &desc_table_p[idx + 1];
+ desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
@@ -117,11 +164,11 @@
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = &desc_table_p[0];
+ desc_p->dmamac_next = (ulong)&desc_table_p[0];
/* Flush all Tx buffer descriptors at once */
- flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
- (unsigned int)priv->tx_mac_descrtable +
+ flush_dcache_range((ulong)priv->tx_mac_descrtable,
+ (ulong)priv->tx_mac_descrtable +
sizeof(priv->tx_mac_descrtable));
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
@@ -142,13 +189,12 @@
* Otherwise there's a chance to get some of them flushed in RAM when
* GMAC is already pushing data to RAM via DMA. This way incoming from
* GMAC data will be corrupted. */
- flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
- RX_TOTAL_BUFSIZE);
+ flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
- desc_p->dmamac_next = &desc_table_p[idx + 1];
+ desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
@@ -158,11 +204,11 @@
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = &desc_table_p[0];
+ desc_p->dmamac_next = (ulong)&desc_table_p[0];
/* Flush all Rx buffer descriptors at once */
- flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
- (unsigned int)priv->rx_mac_descrtable +
+ flush_dcache_range((ulong)priv->rx_mac_descrtable,
+ (ulong)priv->rx_mac_descrtable +
sizeof(priv->rx_mac_descrtable));
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
@@ -290,12 +336,11 @@
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
- uint32_t data_end = data_start +
- roundup(length, ARCH_DMA_MINALIGN);
+ ulong data_start = desc_p->dmamac_addr;
+ ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the "txrx_status" field
* for the following check, but on some platforms we cannot
@@ -312,7 +357,7 @@
return -EPERM;
}
- memcpy(desc_p->dmamac_addr, packet, length);
+ memcpy((void *)data_start, packet, length);
/* Flush data to be sent */
flush_dcache_range(data_start, data_end);
@@ -352,11 +397,11 @@
u32 status, desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
int length = -EAGAIN;
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
- uint32_t data_end;
+ ulong data_start = desc_p->dmamac_addr;
+ ulong data_end;
/* Invalidate entire buffer descriptor */
invalidate_dcache_range(desc_start, desc_end);
@@ -372,7 +417,7 @@
/* Invalidate received data */
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
invalidate_dcache_range(data_start, data_end);
- *packetp = desc_p->dmamac_addr;
+ *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
}
return length;
@@ -382,8 +427,8 @@
{
u32 desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
- uint32_t desc_start = (uint32_t)desc_p;
- uint32_t desc_end = desc_start +
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
/*
@@ -488,6 +533,11 @@
return -ENOMEM;
}
+ if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
+ printf("designware: buffers are outside DMA memory\n");
+ return -EINVAL;
+ }
+
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
@@ -583,6 +633,7 @@
struct eth_pdata *pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
u32 iobase = pdata->iobase;
+ ulong ioaddr;
int ret;
#ifdef CONFIG_DM_PCI
@@ -601,12 +652,13 @@
#endif
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
- priv->mac_regs_p = (struct eth_mac_regs *)iobase;
- priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
+ ioaddr = iobase;
+ priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
+ priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
- dw_mdio_init(dev->name, priv->mac_regs_p);
+ dw_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
ret = dw_phy_init(priv, dev);
@@ -637,9 +689,13 @@
static int designware_eth_ofdata_to_platdata(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = &dw_pdata->eth_pdata;
const char *phy_mode;
const fdt32_t *cell;
+ int reset_flags = GPIOD_IS_OUT;
+ int ret = 0;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
@@ -656,7 +712,20 @@
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
- return 0;
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &priv->reset_gpio, reset_flags);
+ if (ret == 0) {
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "snps,reset-delays-us", dw_pdata->reset_delays, 3);
+ } else if (ret == -ENOENT) {
+ ret = 0;
+ }
+
+ return ret;
}
static const struct udevice_id designware_eth_ids[] = {
@@ -675,7 +744,7 @@
.remove = designware_eth_remove,
.ops = &designware_eth_ops,
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ed6344c..51ba769 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -8,6 +8,8 @@
#ifndef _DW_ETH_H
#define _DW_ETH_H
+#include <asm/gpio.h>
+
#define CONFIG_TX_DESCR_NUM 16
#define CONFIG_RX_DESCR_NUM 16
#define CONFIG_ETH_BUFSIZE 2048
@@ -110,8 +112,8 @@
struct dmamacdescr {
u32 txrx_status;
u32 dmamac_cntl;
- void *dmamac_addr;
- struct dmamacdescr *dmamac_next;
+ u32 dmamac_addr;
+ u32 dmamac_next;
} __aligned(ARCH_DMA_MINALIGN);
/*
@@ -232,8 +234,16 @@
#ifndef CONFIG_DM_ETH
struct eth_device *dev;
#endif
+ struct gpio_desc reset_gpio;
struct phy_device *phydev;
struct mii_dev *bus;
};
+
+#ifdef CONFIG_DM_ETH
+struct dw_eth_pdata {
+ struct eth_pdata eth_pdata;
+ u32 reset_delays[3];
+};
+#endif
#endif
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index e2a8ed3..00cdfd4 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -360,7 +360,7 @@
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+ rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index ae5aca4..70887fa 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -74,7 +74,7 @@
if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
- return PHY_INTERFACE_MODE_XGMII;
+ return PHY_INTERFACE_MODE_NONE;
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 16a7512..1da9996 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -135,14 +135,11 @@
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
- void *addr, bool uncached)
+ void *addr)
{
- pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+ pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
void *virt_addr = addr;
- if (uncached)
- virt_addr = (void *)CKSEG0ADDR(addr);
-
return pci_virt_to_mem(devbusfn, virt_addr);
}
@@ -158,6 +155,7 @@
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
+ u32 bar;
PCNET_DEBUG1("\npcnet_initialize...\n");
@@ -179,19 +177,18 @@
break;
}
memset(dev, 0, sizeof(*dev));
- dev->priv = (void *)devbusfn;
+ dev->priv = (void *)(unsigned long)devbusfn;
sprintf(dev->name, "pcnet#%d", dev_nr);
/*
* Setup the PCI device.
*/
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
- (unsigned int *)&dev->iobase);
- dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
+ dev->iobase = pci_io_to_phys(devbusfn, bar);
dev->iobase &= ~0xf;
- PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
- dev->name, devbusfn, dev->iobase);
+ PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
+ dev->name, devbusfn, (unsigned long)dev->iobase);
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, command);
@@ -298,7 +295,7 @@
{
struct pcnet_uncached_priv *uc;
int i, val;
- u32 addr;
+ unsigned long addr;
PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
@@ -336,16 +333,18 @@
* must be aligned on 16-byte boundaries.
*/
if (lp == NULL) {
- addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
+ addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
addr = (addr + 0xf) & ~0xf;
lp = (pcnet_priv_t *)addr;
- addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
+ addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+ sizeof(*lp->uc));
flush_dcache_range(addr, addr + sizeof(*lp->uc));
addr = UNCACHED_SDRAM(addr);
lp->uc = (struct pcnet_uncached_priv *)addr;
- addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
+ addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+ sizeof(*lp->rx_buf));
flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
lp->rx_buf = (void *)addr;
}
@@ -361,7 +360,7 @@
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+ addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
@@ -393,9 +392,9 @@
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+ addr = pcnet_virt_to_mem(dev, uc->rx_ring);
uc->init_block.rx_ring = cpu_to_le32(addr);
- addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+ addr = pcnet_virt_to_mem(dev, uc->tx_ring);
uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
@@ -406,7 +405,7 @@
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
+ addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
pcnet_write_csr(dev, 1, addr & 0xffff);
pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
@@ -464,7 +463,7 @@
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
- addr = pcnet_virt_to_mem(dev, packet, false);
+ addr = pcnet_virt_to_mem(dev, packet);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
writel(addr, &entry->base);
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index f975fd8..fd130d5 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -139,8 +139,8 @@
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
- ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
- &fw_length, (u_char *)addr);
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+ &fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
CONFIG_CORTINA_FW_ADDR, ret);
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0ba960e..2e6b986 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -569,7 +569,7 @@
unsigned char header_type;
int index;
u32 streamid;
- pci_dev_t dev;
+ pci_dev_t dev, bdf;
int bus;
unsigned short id;
struct pci_controller *hose;
@@ -611,12 +611,15 @@
continue;
}
+ /* the DT fixup must be relative to the hose first_busno */
+ bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
+
/* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
streamid);
}
}
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 7c769bd..1fa1daa 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -623,7 +623,7 @@
{
const void *blob = gd->fdt_blob;
int pcfg_node, ret, flags, count, i;
- u32 cell[40], *ptr;
+ u32 cell[60], *ptr;
debug("%s: %s %s\n", __func__, dev->name, config->name);
ret = fdtdec_get_int_array_count(blob, config->of_offset,
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3c41bca..3c44167 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -41,9 +41,17 @@
Select this to enable support for the axp221/axp223 pmic found on most
A23 and A31 boards.
+config AXP809_POWER
+ boolean "axp809 pmic support"
+ depends on MACH_SUN9I
+ select CMD_POWEROFF
+ ---help---
+ Say y here to enable support for the axp809 pmic found on A80 boards.
+
config AXP818_POWER
boolean "axp818 pmic support"
depends on MACH_SUN8I_A83T
+ select CMD_POWEROFF
---help---
Say y here to enable support for the axp818 pmic found on
A83T dev board.
@@ -59,36 +67,39 @@
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 3300 if AXP818_POWER
- default 3000 if MACH_SUN6I || MACH_SUN8I
+ default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for
generic 3.3V IO voltage for external devices like the lcd-panal and
sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
- safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
- dcdc1 is used for VCC-IO, nand, usb0, sd , etc.
+ save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
+ dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally
+ powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG.
config AXP_DCDC2_VOLT
int "axp pmic dcdc2 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
default 900 if AXP818_POWER
default 1400 if AXP152_POWER || AXP209_POWER
default 1200 if MACH_SUN6I
default 1100 if MACH_SUN8I
+ default 0 if MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to
disable dcdc2.
On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
+ On A80 boards dcdc2 powers the GPU and can be left off.
On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
config AXP_DCDC3_VOLT
int "axp pmic dcdc3 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
- default 900 if AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default 900 if AXP809_POWER || AXP818_POWER
default 1500 if AXP152_POWER
default 1250 if AXP209_POWER
default 1200 if MACH_SUN6I || MACH_SUN8I
@@ -99,51 +110,55 @@
should be 1.25V.
On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
+ On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
config AXP_DCDC4_VOLT
int "axp pmic dcdc4 voltage"
- depends on AXP152_POWER || AXP221_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
default 1250 if AXP152_POWER
default 1200 if MACH_SUN6I
default 0 if MACH_SUN8I
+ default 900 if MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to
disable dcdc4.
On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V.
On A23 / A33 boards dcdc4 is unused and should be disabled.
+ On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V.
On A83T boards dcdc4 is used for VDD-GPU.
config AXP_DCDC5_VOLT
int "axp pmic dcdc5 voltage"
- depends on AXP221_POWER || AXP818_POWER
- default 1500 if MACH_SUN6I || MACH_SUN8I
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
disable dcdc5.
- On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
- 1.35V if DDR3L is used.
+ On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and
+ should be 1.5V, 1.35V if DDR3L is used.
config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 0 if MACH_SUN6I
default 1800 if MACH_SUN8I_A83T
- default 3000 if MACH_SUN8I
+ default 3000 if MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
disable aldo1.
On A31 boards aldo1 is often used to power the wifi module.
On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
+ On A80 boards aldo1 powers the USB hosts and should be 3.0V.
On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
should be 1.8V.
config AXP_ALDO2_VOLT
int "axp pmic (a)ldo2 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
default 3000 if AXP152_POWER || AXP209_POWER
- default 0 if MACH_SUN6I
+ default 0 if MACH_SUN6I || MACH_SUN9I
default 1800 if MACH_SUN8I_A83T
default 2500 if MACH_SUN8I
---help---
@@ -153,19 +168,21 @@
On A31 boards aldo2 is typically unused and should be disabled.
On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
+ On A80 boards aldo2 powers PB pingroup and camera IO and can be left off.
On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
LPDDR2, and the codec. It should be 1.8V.
config AXP_ALDO3_VOLT
int "axp pmic (a)ldo3 voltage"
- depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
- default 0 if AXP209_POWER
+ depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default 0 if AXP209_POWER || MACH_SUN9I
default 3000 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
disable aldo3.
On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
+ On A80 boards aldo3 is normally not used.
On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
3.0V.
@@ -180,21 +197,23 @@
config AXP_DLDO1_VOLT
int "axp pmic dldo1 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used
- to power the ethernet phy. On sun8i (A23) boards this is often used to
- power the wifi.
+ to power the ethernet phy. On A23, A33 and A80 boards this is often
+ used to power the wifi.
config AXP_DLDO2_VOLT
int "axp pmic dldo2 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default 3000 if MACH_SUN9I
default 0
---help---
Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to
disable dldo2.
+ On A80 boards dldo2 normally powers the PL pins and should be 3.0V.
config AXP_DLDO3_VOLT
int "axp pmic dldo3 voltage"
@@ -214,7 +233,7 @@
config AXP_ELDO1_VOLT
int "axp pmic eldo1 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
@@ -222,7 +241,7 @@
config AXP_ELDO2_VOLT
int "axp pmic eldo2 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -230,13 +249,15 @@
config AXP_ELDO3_VOLT
int "axp pmic eldo3 voltage"
- depends on AXP221_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+ default 3000 if MACH_SUN9I
default 0
---help---
Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to
disable eldo3. On some A31(s) tablets it might be used to supply
1.2V for the SSD2828 chip (converter of parallel LCD interface
into MIPI DSI).
+ On A80 boards it powers the PM pingroup and should be 3.0V.
config AXP_FLDO1_VOLT
int "axp pmic fldo1 voltage"
@@ -249,7 +270,7 @@
used.
config AXP_FLDO2_VOLT
- int "axp pmic eldo2 voltage"
+ int "axp pmic fldo2 voltage"
depends on AXP818_POWER
default 900 if MACH_SUN8I_A83T
---help---
@@ -265,6 +286,13 @@
Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to
disable fldo3.
+config AXP_SW_ON
+ bool "axp pmic sw on"
+ depends on AXP809_POWER || AXP818_POWER
+ default n
+ ---help---
+ Enable to turn on axp pmic sw.
+
config SY8106A_VOUT1_VOLT
int "SY8106A pmic VOUT1 voltage"
depends on SY8106A_POWER
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 690faa0..b43523e 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
+obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index cb1f88b..727ab09 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -191,33 +191,20 @@
{
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- u8 addr, bits;
- switch (eldo_num) {
- case 3:
- addr = AXP221_ELDO3_CTRL;
- bits = AXP221_OUTPUT_CTRL2_ELDO3_EN;
- break;
- case 2:
- addr = AXP221_ELDO2_CTRL;
- bits = AXP221_OUTPUT_CTRL2_ELDO2_EN;
- break;
- case 1:
- addr = AXP221_ELDO1_CTRL;
- bits = AXP221_OUTPUT_CTRL2_ELDO1_EN;
- break;
- default:
+ if (eldo_num < 1 || eldo_num > 3)
return -EINVAL;
- }
if (mvolt == 0)
- return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
- ret = pmic_bus_write(addr, cfg);
+ ret = pmic_bus_write(AXP221_ELDO1_CTRL + (eldo_num - 1), cfg);
if (ret)
return ret;
- return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
}
int axp_init(void)
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
new file mode 100644
index 0000000..c8b76cf
--- /dev/null
+++ b/drivers/power/axp809.c
@@ -0,0 +1,238 @@
+/*
+ * AXP809 driver based on AXP221 driver
+ *
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on axp221.c
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+static u8 axp809_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp_set_dcdc1(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC1_EN);
+
+ ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_DC1SW_EN);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC1_EN);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC2_EN);
+
+ ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC2_EN);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC3_EN);
+
+ ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC3_EN);
+}
+
+int axp_set_dcdc4(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+ if (mvolt >= 1540)
+ cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC4_EN);
+
+ ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC4_EN);
+}
+
+int axp_set_dcdc5(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 1000, 2550, 50);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC5_EN);
+
+ ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_DCDC5_EN);
+}
+
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg;
+
+ if (aldo_num < 1 || aldo_num > 3)
+ return -EINVAL;
+
+ if (mvolt == 0 && aldo_num == 3)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_ALDO3_EN);
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+
+ cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ ret = pmic_bus_write(AXP809_ALDO1_CTRL + (aldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ if (aldo_num == 3)
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_ALDO3_EN);
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers to consolidate ALDO functions. */
+int axp_set_aldo1(unsigned int mvolt)
+{
+ return axp_set_aldo(1, mvolt);
+}
+
+int axp_set_aldo2(unsigned int mvolt)
+{
+ return axp_set_aldo(2, mvolt);
+}
+
+int axp_set_aldo3(unsigned int mvolt)
+{
+ return axp_set_aldo(3, mvolt);
+}
+
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ int ret;
+
+ if (dldo_num < 1 || dldo_num > 2)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+ if (dldo_num == 1 && mvolt > 3300)
+ cfg += 1 + axp809_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+ ret = pmic_bus_write(AXP809_DLDO1_CTRL + (dldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ if (eldo_num < 1 || eldo_num > 3)
+ return -EINVAL;
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+ ret = pmic_bus_write(AXP809_ELDO1_CTRL + (eldo_num - 1), cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
+int axp_set_sw(bool on)
+{
+ if (on)
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_SWOUT_EN);
+
+ return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+ AXP809_OUTPUT_CTRL2_SWOUT_EN);
+}
+
+int axp_init(void)
+{
+ int ret;
+
+ ret = pmic_bus_init();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF);
+
+ /* infinite loop during shutdown */
+ while (1) {}
+
+ /* not reached */
+ return 0;
+}
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 3ac05ff..af4d7a6 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -225,6 +225,16 @@
AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
}
+int axp_set_sw(bool on)
+{
+ if (on)
+ return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_SW_EN);
+
+ return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+ AXP818_OUTPUT_CTRL2_SW_EN);
+}
+
int axp_init(void)
{
u8 axp_chip_id;
@@ -243,5 +253,16 @@
else
return ret;
+ return 0;
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF);
+
+ /* infinite loop during shutdown */
+ while (1) {}
+
+ /* not reached */
return 0;
}
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2497ae9..0e38903 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -121,6 +121,14 @@
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_MESON
+ bool "Amlogic Meson"
+ depends on MESON_SERIAL
+ help
+ Select this to enable a debug UART using the serial_meson driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_UARTLITE
bool "Xilinx Uartlite"
help
@@ -338,6 +346,13 @@
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.
+config MESON_SERIAL
+ bool "Support for Amlogic Meson UART"
+ depends on DM_SERIAL && ARCH_MESON
+ help
+ If you have an Amlogic Meson based board and want to use the on-chip
+ serial ports, say Y to this option. If unsure, say N.
+
config MSM_SERIAL
bool "Qualcomm on-chip UART"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9def128..e1e28de 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -27,6 +27,7 @@
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
+obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 28da9dd..c6cb3eb 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -54,12 +54,6 @@
#define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */
-#ifdef CONFIG_DM_SERIAL
-
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK 0
-#endif
-
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
@@ -94,13 +88,20 @@
#endif
}
+#ifdef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
struct ns16550_platdata *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+ addr = (unsigned char *)plat->base + offset;
+
/*
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
@@ -114,7 +115,7 @@
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+ addr = (unsigned char *)plat->base + offset;
return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
}
@@ -128,27 +129,13 @@
(unsigned char *)addr - (unsigned char *)com_port)
#endif
-static inline int calc_divisor(NS16550_t port, int clock, int baudrate)
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
{
const unsigned int mode_x_div = 16;
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
}
-int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
-{
-#ifdef CONFIG_OMAP1510
- /* If can't cleanly clock 115200 set div to 1 */
- if ((clock == 12000000) && (baudrate == 115200)) {
- port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
- return 1; /* return 1 for base divisor */
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
-#endif
-
- return calc_divisor(port, clock, baudrate);
-}
-
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
@@ -271,8 +258,8 @@
* feasible. The better fix is to move all users of this driver to
* driver model.
*/
- baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
- CONFIG_BAUDRATE);
+ baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCRVAL);
@@ -400,7 +387,12 @@
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = addr;
+#else
+ plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+
plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-offset", 0);
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
new file mode 100644
index 0000000..1b49426
--- /dev/null
+++ b/drivers/serial/serial_meson.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct meson_uart {
+ u32 wfifo;
+ u32 rfifo;
+ u32 control;
+ u32 status;
+ u32 misc;
+};
+
+struct meson_serial_platdata {
+ struct meson_uart *reg;
+};
+
+/* AML_UART_STATUS bits */
+#define AML_UART_PARITY_ERR BIT(16)
+#define AML_UART_FRAME_ERR BIT(17)
+#define AML_UART_TX_FIFO_WERR BIT(18)
+#define AML_UART_RX_EMPTY BIT(20)
+#define AML_UART_TX_FULL BIT(21)
+#define AML_UART_TX_EMPTY BIT(22)
+#define AML_UART_XMIT_BUSY BIT(25)
+#define AML_UART_ERR (AML_UART_PARITY_ERR | \
+ AML_UART_FRAME_ERR | \
+ AML_UART_TX_FIFO_WERR)
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TX_EN BIT(12)
+#define AML_UART_RX_EN BIT(13)
+#define AML_UART_TX_RST BIT(22)
+#define AML_UART_RX_RST BIT(23)
+#define AML_UART_CLR_ERR BIT(24)
+
+static void meson_serial_init(struct meson_uart *uart)
+{
+ u32 val;
+
+ val = readl(&uart->control);
+ val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+ writel(val, &uart->control);
+ val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+ writel(val, &uart->control);
+ val |= (AML_UART_RX_EN | AML_UART_TX_EN);
+ writel(val, &uart->control);
+}
+
+static int meson_serial_probe(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ meson_serial_init(uart);
+
+ return 0;
+}
+
+static int meson_serial_getc(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ if (readl(&uart->status) & AML_UART_RX_EMPTY)
+ return -EAGAIN;
+
+ return readl(&uart->rfifo) & 0xff;
+}
+
+static int meson_serial_putc(struct udevice *dev, const char ch)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+
+ if (readl(&uart->status) & AML_UART_TX_FULL)
+ return -EAGAIN;
+
+ writel(ch, &uart->wfifo);
+
+ return 0;
+}
+
+static int meson_serial_pending(struct udevice *dev, bool input)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_uart *const uart = plat->reg;
+ uint32_t status = readl(&uart->status);
+
+ if (input)
+ return !(status & AML_UART_RX_EMPTY);
+ else
+ return !(status & AML_UART_TX_FULL);
+}
+
+static int meson_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct meson_serial_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->reg = (struct meson_uart *)addr;
+
+ return 0;
+}
+
+static const struct dm_serial_ops meson_serial_ops = {
+ .putc = meson_serial_putc,
+ .pending = meson_serial_pending,
+ .getc = meson_serial_getc,
+};
+
+static const struct udevice_id meson_serial_ids[] = {
+ { .compatible = "amlogic,meson-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_meson) = {
+ .name = "serial_meson",
+ .id = UCLASS_SERIAL,
+ .of_match = meson_serial_ids,
+ .probe = meson_serial_probe,
+ .ops = &meson_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .ofdata_to_platdata = meson_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
+};
+
+#ifdef CONFIG_DEBUG_UART_MESON
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+
+ while (readl(®s->status) & AML_UART_TX_FULL)
+ ;
+
+ writel(ch, ®s->wfifo);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 0cd7302..2964bae 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -6,7 +6,7 @@
dwc3-y := core.o
-dwc3-y += gadget.o ep0.o
+obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d2363c8..89580cc 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -9,12 +9,6 @@
The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
"SuperSpeed" host controller hardware.
-config USB_XHCI
- bool
- default USB_XHCI_HCD
- ---help---
- TODO: rename after most boards switch to Kconfig
-
if USB_XHCI_HCD
config USB_XHCI_UNIPHIER
@@ -24,6 +18,12 @@
---help---
Enables support for the on-chip xHCI controller on UniPhier SoCs.
+config USB_XHCI_DWC3
+ bool "DesignWare USB3 DRD Core Support"
+ help
+ Say Y or if your system has a Dual Role SuperSpeed
+ USB controller based on the DesignWare USB3 IP Core.
+
endif
config USB_OHCI_GENERIC
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 507519e..620d114 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,7 +54,7 @@
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
-obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f9069c7..1993da1 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -23,7 +23,7 @@
#include "../host/xhci.h"
#ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb_dpll_params {
+struct usb3_dpll_params {
u16 m;
u8 n;
u8 freq:3;
@@ -31,17 +31,39 @@
u32 mf;
};
-#define NUM_USB_CLKS 6
+struct usb3_dpll_map {
+ unsigned long rate;
+ struct usb3_dpll_params params;
+ struct usb3_dpll_map *dpll_map;
+};
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
- {1250, 5, 4, 20, 0}, /* 12 MHz */
- {3125, 20, 4, 20, 0}, /* 16.8 MHz */
- {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
- {1250, 12, 4, 20, 0}, /* 26 MHz */
- {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
- {1000, 7, 4, 10, 0}, /* 20 MHz */
+static struct usb3_dpll_map dpll_map_usb[] = {
+ {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
+ {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
+ {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
+ {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
+ {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
+ {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { }, /* Terminator */
};
+static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
+{
+ unsigned long rate;
+ struct usb3_dpll_map *dpll_map = dpll_map_usb;
+
+ rate = get_sys_clk_freq();
+
+ for (; dpll_map->rate; dpll_map++) {
+ if (rate == dpll_map->rate)
+ return &dpll_map->params;
+ }
+
+ dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
+ return NULL;
+}
+
static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
{
u32 val;
@@ -56,32 +78,36 @@
static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
{
- u32 clk_index = get_sys_clk_index();
+ struct usb3_dpll_params *dpll_params;
u32 val;
+ dpll_params = omap_usb3_get_dpll_params();
+ if (!dpll_params)
+ return;
+
val = readl(&phy_regs->pll_config_1);
val &= ~PLL_REGN_MASK;
- val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+ val |= dpll_params->n << PLL_REGN_SHIFT;
writel(val, &phy_regs->pll_config_1);
val = readl(&phy_regs->pll_config_2);
val &= ~PLL_SELFREQDCO_MASK;
- val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+ val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
writel(val, &phy_regs->pll_config_2);
val = readl(&phy_regs->pll_config_1);
val &= ~PLL_REGM_MASK;
- val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+ val |= dpll_params->m << PLL_REGM_SHIFT;
writel(val, &phy_regs->pll_config_1);
val = readl(&phy_regs->pll_config_4);
val &= ~PLL_REGM_F_MASK;
- val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+ val |= dpll_params->mf << PLL_REGM_F_SHIFT;
writel(val, &phy_regs->pll_config_4);
val = readl(&phy_regs->pll_config_3);
val &= ~PLL_SD_MASK;
- val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+ val |= dpll_params->sd << PLL_SD_SHIFT;
writel(val, &phy_regs->pll_config_3);
omap_usb_dpll_relock(phy_regs);
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index a54af17..db09d9a 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -326,6 +326,7 @@
if (!ret)
break;
}
+ video_set_flush_dcache(dev, 1);
return ret;
}
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index ba038b1..f771e94 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -195,7 +195,7 @@
}
retlen = NAND_CACHE_SIZE;
- if (nand_read(&nand_info[id->num], nand_cache_off,
+ if (nand_read(nand_info[id->num], nand_cache_off,
&retlen, nand_cache) != 0 ||
retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 740f787..d94c48f 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -23,7 +23,7 @@
# define DEBUGF(fmt,args...)
#endif
-static nand_info_t *nand;
+static struct mtd_info *mtd;
/* Compression names */
static char *compr_names[] = {
@@ -304,7 +304,7 @@
len = sizeof(struct jffs2_raw_inode);
if (dest)
len += jNode->csize;
- nand_read(nand, jNode->offset, &len, inode);
+ nand_read(mtd, jNode->offset, &len, inode);
/* ignore data behind latest known EOF */
if (inode->offset > totalSize)
continue;
@@ -450,7 +450,7 @@
if(!d || !i) return -1;
len = d->nsize;
- nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent),
+ nand_read(mtd, d->offset + sizeof(struct jffs2_raw_dirent),
&len, &fname);
fname[d->nsize] = '\0';
@@ -592,7 +592,9 @@
for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
if (jNode->ino == jDirFoundIno) {
size_t len = jNode->csize;
- nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp);
+ nand_read(mtd,
+ jNode->offset + sizeof(struct jffs2_raw_inode),
+ &len, &tmp);
tmp[jNode->csize] = '\0';
break;
}
@@ -760,14 +762,14 @@
#endif
static int
-jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf,
+jffs2_fill_scan_buf(struct mtd_info *mtd, unsigned char *buf,
unsigned ofs, unsigned len)
{
int ret;
unsigned olen;
olen = len;
- ret = nand_read(nand, ofs, &olen, buf);
+ ret = nand_read(mtd, ofs, &olen, buf);
if (ret) {
printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret);
return ret;
@@ -794,7 +796,7 @@
u32 counterN = 0;
struct mtdids *id = part->dev->id;
- nand = nand_info + id->num;
+ mtd = nand_info[id->num];
/* if we are building a list we need to refresh the cache. */
jffs_init_1pass_list(part);
@@ -802,7 +804,7 @@
pL->partOffset = part->offset;
puts ("Scanning JFFS2 FS: ");
- sectorsize = nand->erasesize;
+ sectorsize = mtd->erasesize;
nr_blocks = part->size / sectorsize;
buf = malloc(sectorsize);
if (!buf)
@@ -813,10 +815,10 @@
offset = part->offset + i * sectorsize;
- if (nand_block_isbad(nand, offset))
+ if (nand_block_isbad(mtd, offset))
continue;
- if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE))
+ if (jffs2_fill_scan_buf(mtd, buf, offset, EMPTY_SCAN_SIZE))
return 0;
ofs = 0;
@@ -826,7 +828,7 @@
if (ofs == EMPTY_SCAN_SIZE)
continue;
- if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
+ if (jffs2_fill_scan_buf(mtd, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
return 0;
offset += ofs;
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index 50000a1..25aa6d1 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -141,8 +141,6 @@
}
}
-extern nand_info_t nand_info[];
-
void cmd_yaffs_tracemask(unsigned set, unsigned mask)
{
if (set)
@@ -171,7 +169,7 @@
dev = calloc(1, sizeof(*dev));
mp = strdup(_mp);
- mtd = &nand_info[flash_dev];
+ mtd = nand_info[flash_dev];
if (!dev || !mp) {
/* Alloc error */
@@ -192,7 +190,7 @@
goto err;
}
- chip = mtd->priv;
+ chip = mtd_to_nand(mtd);
/* Check for any conflicts */
yaffs_dev_rewind();
@@ -260,9 +258,7 @@
dev = yaffs_next_dev();
if (!dev)
return;
- flash_dev =
- ((unsigned) dev->driver_context - (unsigned) nand_info)/
- sizeof(nand_info[0]);
+ flash_dev = nand_mtd_to_devnum(dev->driver_context);
printf("%-10s %5d 0x%05x 0x%05x %s",
dev->param.name, flash_dev,
dev->param.start_block, dev->param.end_block,
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index f2810a1..0abcbe4 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -141,5 +141,6 @@
#define GD_FLG_SPL_INIT 0x00400 /* spl_init() has been called */
#define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */
#define GD_FLG_RECORD 0x01000 /* Record console */
+#define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */
#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 2500c10..4aa0004 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -251,6 +251,8 @@
int value);
int (*get_value)(struct udevice *dev, unsigned offset);
int (*set_value)(struct udevice *dev, unsigned offset, int value);
+ int (*get_open_drain)(struct udevice *dev, unsigned offset);
+ int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
/**
* get_function() Get the GPIO function
*
@@ -550,6 +552,38 @@
int dm_gpio_set_value(const struct gpio_desc *desc, int value);
/**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc: GPIO description containing device, offset and flags,
+ * previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ * -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc: GPIO description containing device, offset and flags,
+ * previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
* dm_gpio_set_dir() - Set the direction for a GPIO
*
* This sets up the direction according tot the provided flags. It will do
diff --git a/include/axp809.h b/include/axp809.h
new file mode 100644
index 0000000..d27fb97
--- /dev/null
+++ b/include/axp809.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * X-Powers AXP809 Power Management IC driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define AXP809_CHIP_ID 0x03
+
+#define AXP809_OUTPUT_CTRL1 0x10
+#define AXP809_OUTPUT_CTRL1_DC5LDO_EN (1 << 0)
+#define AXP809_OUTPUT_CTRL1_DCDC1_EN (1 << 1)
+#define AXP809_OUTPUT_CTRL1_DCDC2_EN (1 << 2)
+#define AXP809_OUTPUT_CTRL1_DCDC3_EN (1 << 3)
+#define AXP809_OUTPUT_CTRL1_DCDC4_EN (1 << 4)
+#define AXP809_OUTPUT_CTRL1_DCDC5_EN (1 << 5)
+#define AXP809_OUTPUT_CTRL1_ALDO1_EN (1 << 6)
+#define AXP809_OUTPUT_CTRL1_ALDO2_EN (1 << 7)
+#define AXP809_OUTPUT_CTRL2 0x12
+#define AXP809_OUTPUT_CTRL2_ELDO1_EN (1 << 0)
+#define AXP809_OUTPUT_CTRL2_ELDO2_EN (1 << 1)
+#define AXP809_OUTPUT_CTRL2_ELDO3_EN (1 << 2)
+#define AXP809_OUTPUT_CTRL2_DLDO1_EN (1 << 3)
+#define AXP809_OUTPUT_CTRL2_DLDO2_EN (1 << 4)
+#define AXP809_OUTPUT_CTRL2_ALDO3_EN (1 << 5)
+#define AXP809_OUTPUT_CTRL2_SWOUT_EN (1 << 6)
+#define AXP809_OUTPUT_CTRL2_DC1SW_EN (1 << 7)
+
+#define AXP809_DLDO1_CTRL 0x15
+#define AXP809_DLDO2_CTRL 0x16
+#define AXP809_ELDO1_CTRL 0x19
+#define AXP809_ELDO2_CTRL 0x1a
+#define AXP809_ELDO3_CTRL 0x1b
+#define AXP809_DC5LDO_CTRL 0x1c
+#define AXP809_DCDC1_CTRL 0x21
+#define AXP809_DCDC2_CTRL 0x22
+#define AXP809_DCDC3_CTRL 0x23
+#define AXP809_DCDC4_CTRL 0x24
+#define AXP809_DCDC5_CTRL 0x25
+#define AXP809_ALDO1_CTRL 0x28
+#define AXP809_ALDO2_CTRL 0x29
+#define AXP809_ALDO3_CTRL 0x2a
+#define AXP809_SHUTDOWN 0x32
+#define AXP809_SHUTDOWN_POWEROFF (1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
+#define AXP_GPIO0_CTRL 0x90
+#define AXP_GPIO1_CTRL 0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
+#define AXP_GPIO_STATE 0x94
+#define AXP_GPIO_STATE_OFFSET 0
diff --git a/include/axp818.h b/include/axp818.h
index 5630eed..959774c 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -24,6 +24,7 @@
#define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4)
#define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5)
#define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6)
+#define AXP818_OUTPUT_CTRL2_SW_EN (1 << 7)
#define AXP818_OUTPUT_CTRL3 0x13
#define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2)
#define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3)
@@ -54,6 +55,9 @@
#define AXP818_ALDO2_CTRL 0x29
#define AXP818_ALDO3_CTRL 0x2a
+#define AXP818_SHUTDOWN 0x32
+#define AXP818_SHUTDOWN_POWEROFF (1 << 7)
+
/* For axp_gpio.c */
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index b203cc8..d789ad8 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -16,6 +16,9 @@
#ifdef CONFIG_AXP221_POWER
#include <axp221.h>
#endif
+#ifdef CONFIG_AXP809_POWER
+#include <axp809.h>
+#endif
#ifdef CONFIG_AXP818_POWER
#include <axp818.h>
#endif
@@ -32,6 +35,7 @@
int axp_set_dldo(int dldo_num, unsigned int mvolt);
int axp_set_eldo(int eldo_num, unsigned int mvolt);
int axp_set_fldo(int fldo_num, unsigned int mvolt);
+int axp_set_sw(bool on);
int axp_init(void);
int axp_get_sid(unsigned int *sid);
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 5a8d7f2..4db6faa 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -230,13 +230,58 @@
#endif
#if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+#if defined(CONFIG_ARM64)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86)
+/* Always assume we're running 64bit */
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+ "setenv efi_fdtfile ${fdtfile}; " \
+ BOOTENV_EFI_SET_FDTFILE_FALLBACK \
+ "setenv efi_old_vci ${bootp_vci};" \
+ "setenv efi_old_arch ${bootp_arch};" \
+ "setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";" \
+ "setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";" \
+ "if dhcp ${kernel_addr_r}; then " \
+ "tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};" \
+ "if fdt addr ${fdt_addr_r}; then " \
+ "bootefi ${kernel_addr_r} ${fdt_addr_r}; " \
+ "else " \
+ "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
+ "fi;" \
+ "fi;" \
+ "setenv bootp_vci ${efi_old_vci};" \
+ "setenv bootp_arch ${efi_old_arch};" \
+ "setenv efi_fdtfile;" \
+ "setenv efi_old_arch;" \
+ "setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
"bootcmd_dhcp=" \
BOOTENV_RUN_NET_USB_START \
BOOTENV_RUN_NET_PCI_ENUM \
"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
"source ${scriptaddr}; " \
- "fi\0"
+ "fi;" \
+ BOOTENV_EFI_RUN_DHCP \
+ "\0"
#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
"dhcp "
#else
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 766a212..dfc2cbc 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,27 +20,6 @@
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#if defined(__arm__) || defined(__aarch64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
-#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7"
-#endif
-#elif defined(__aarch64__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8"
-#endif
-#else
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.arm"
-#endif
-#endif
-#elif defined(__i386__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x0
-#elif defined(__x86_64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x9
-#endif
-
#ifdef CONFIG_ARM64
#define CONFIG_CMD_BOOTI
#endif
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f398b37..4d08555 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -822,14 +822,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index d8c57a8..f48697c 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -291,6 +291,10 @@
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_RCW_SRC_NAND 0x104
+#define QIXIS_RCW_SRC_SD 0x040
#define QIXIS_RST_CTL_RESET 0x83
#define QIXIS_RST_FORCE_MEM 0x1
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index bcf6942..f0b5b3e 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -449,14 +449,6 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 16935a1..ba4c215 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -91,6 +91,7 @@
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run init_console; " \
"run envboot; " \
"run distro_bootcmd"
@@ -169,8 +170,16 @@
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
"setenv fdtfile am335x-evmsk.dtb; fi; " \
+ "if test $board_name = A335_ICE; then " \
+ "setenv fdtfile am335x-icev2.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
+ "init_console=" \
+ "if test $board_name = A335_ICE; then "\
+ "setenv console ttyO3,115200n8;" \
+ "else " \
+ "setenv console ttyO0,115200n8;" \
+ "fi;\0" \
NANDARGS \
NETARGS \
DFUARGS \
@@ -249,11 +258,6 @@
"8m(NAND.kernel)," \
"-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_AM33XX_BCH
@@ -415,7 +419,6 @@
"128k(u-boot-env2),3464k(kernel)," \
"-(rootfs)"
#elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
@@ -423,6 +426,27 @@
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#elif defined(CONFIG_NOR_BOOT)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#elif !defined(CONFIG_ENV_IS_NOWHERE)
+/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
#endif
/* SPI flash. */
@@ -458,19 +482,11 @@
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
- "512k(u-boot)," \
- "128k(u-boot-env1)," \
- "128k(u-boot-env2)," \
- "4m(kernel),-(rootfs)"
-#endif
#endif /* NOR support */
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
#endif /* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5b49988..361704b 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_AM43XX_EVM_H
#define __CONFIG_AM43XX_EVM_H
-#define CONFIG_AM43XX
-
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
@@ -39,17 +37,10 @@
#define CONFIG_POWER_TPS62362
/* SPL defines. */
-#ifdef CONFIG_SPL_USB_HOST_SUPPORT
-/*
- * For USB host boot, ROM uses DMA for copying MLO from USB storage
- * and ARM internal ram is not accessible for DMA, so SPL text base
- * should be in OCMC ram
- */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#else
-#define CONFIG_SPL_TEXT_BASE 0x402F4000
-#endif
-#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
+#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
+#define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \
+ CONFIG_PUB_ROM_DATA_SIZE - \
+ CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
@@ -108,8 +99,6 @@
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
@@ -192,7 +181,9 @@
#endif
#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x30000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
+#endif
#undef CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
@@ -296,6 +287,8 @@
"setenv fdtfile am43x-epos-evm.dtb; fi; " \
"if test $board_name = AM43__GP; then " \
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+ "if test $board_name = AM43XXHS; then " \
+ "setenv fdtfile am437x-gp-evm.dtb; fi; " \
"if test $board_name = AM43__SK; then " \
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
"if test $board_name = AM43_IDK; then " \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d53b0fd..2db199d 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -64,8 +64,6 @@
/* USB xHCI HOST */
#define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 2beffa4..b01031c 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0x9f000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
@@ -47,13 +40,13 @@
"rootfstype=squashfs"
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
- "bootm 0x9f300000"
+ "bootm 0x9f650000"
#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
"256k(u-boot),64k(u-boot-env)," \
- "2752k(rootfs),896k(uImage)," \
+ "6144k(rootfs),1600k(uImage)," \
"64k(NVRAM),64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 7b69e10..0fa73a7 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0x9f000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
@@ -51,14 +44,14 @@
"rootfstype=squashfs"
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
- "bootm 0x9f300000"
+ "bootm 0x9f680000"
#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
"256k(u-boot),64k(u-boot-env)," \
- "2752k(rootfs),896k(uImage)," \
- "64k(NVRAM),64k(ART)"
+ "6336k(rootfs),1472k(uImage)," \
+ "64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 74c3464..cf8ef8a 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -125,7 +125,6 @@
* USB Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
#define CONFIG_USB_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index e268473..c958a94 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -128,7 +128,6 @@
* USB Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
#define CONFIG_USB_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 6830e4d..be28ea3 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -151,7 +151,6 @@
* USB Settings
*/
#if !defined(__ADSPBF544__)
-#define CONFIG_USB
#define CONFIG_USB_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index c2dbd31..5076540 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -61,9 +61,7 @@
/* USB support */
#define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index eb0a87c..68ff025 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -139,12 +139,6 @@
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-#define CONFIG_SYS_TEXT_BASE 0xbfc00000
-/* RAM version */
-/* #define CONFIG_SYS_TEXT_BASE 0x80100000 */
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
@@ -208,11 +202,4 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif /* CONFIG_DBAU1550 */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8a0cd66..0d51aeb 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -211,8 +211,6 @@
/* USB xHCI HOST */
#define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 64c546c..23373cd 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -71,12 +71,11 @@
* - USB init fails, controller does not respond in time */
#if 0
#undef CONFIG_DM_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_PCI
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
-#if !defined(CONFIG_USB_XHCI)
+#if !defined(CONFIG_USB_XHCI_HCD)
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 061cac4..f2ed798 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -155,7 +155,6 @@
/* USB */
#define CONFIG_USB_STORAGE
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index cd86e06..16153eb 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -48,7 +48,6 @@
*/
#define CONFIG_CORE_COUNT 0x8
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
#endif /* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index f3361d0..e6b7953 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -14,7 +14,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 94eb7ac..956c0e2 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -15,7 +15,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index dcb72c9..908d545 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -13,7 +13,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 3e81f0d..6a88901 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -13,7 +13,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index ab1e11d..0ebded6 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/*
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 07f975b..7eaab87 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -21,7 +21,7 @@
"addr_mon=0x0c140000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
- "name_fdt=k2e-evm.dtb\0" \
+ "name_fdt=keystone-k2e-evm.dtb\0" \
"name_mon=skern-k2e.bin\0" \
"name_ubi=k2e-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2e-evm.gph\0" \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 3f98510..f8bba67 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -26,7 +26,7 @@
"addr_mon=0x0c040000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
- "name_fdt=k2g-evm.dtb\0" \
+ "name_fdt=keystone-k2g-evm.dtb\0" \
"name_mon=skern-k2g.bin\0" \
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index a268a86..0256f0e 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -21,7 +21,7 @@
"addr_mon=0x0c5f0000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
- "name_fdt=k2hk-evm.dtb\0" \
+ "name_fdt=keystone-k2hk-evm.dtb\0" \
"name_mon=skern-k2hk.bin\0" \
"name_ubi=k2hk-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2hk-evm.gph\0" \
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index f366e67..2322ab2 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -21,7 +21,7 @@
"addr_mon=0x0c140000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \
- "name_fdt=k2l-evm.dtb\0" \
+ "name_fdt=keystone-k2l-evm.dtb\0" \
"name_mon=skern-k2l.bin\0" \
"name_ubi=k2l-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2l-evm.gph\0" \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000..ccd94ec
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE 0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE 0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
+#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "initrd_high=0xffffffff\0" \
+ "verify=no\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+#define CONFIG_BOOTDELAY 10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000..ad81142
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000..fcf402c
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_BRDCFG_REG 0x04
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0xf7
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x08
+#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0 1
+
+#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644
index 0000000..6046ab7
--- /dev/null
+++ b/include/configs/ls1012ardb.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR 0x24
+#define __SW_BOOT_MASK 0xFC
+#define __SW_BOOT_EMU 0x10
+#define __SW_BOOT_BANK1 0x00
+#define __SW_BOOT_BANK2 0x01
+#define __SW_REV_MASK 0x07
+#define __SW_REV_A 0xF8
+#define __SW_REV_B 0xF0
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f605ca6..1edf798 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -450,8 +450,6 @@
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 32d2acc..30f5655 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -57,8 +57,6 @@
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index af1f73d..a19eaee 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -388,9 +388,7 @@
/* USB */
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index aca8d95..94ddfb1 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -278,9 +278,7 @@
/* USB */
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index f4ace85..16e37bf 100644
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -10,7 +10,6 @@
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2080A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-EMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index bc0d678..7563aaf 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -10,7 +10,6 @@
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.LS2080A-SIMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..b44066c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -383,9 +383,7 @@
* USB
*/
#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 3baca64..86a49a5 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -316,9 +316,7 @@
* USB
*/
#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 04dca71..fc4baba 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -37,17 +37,20 @@
/*
* Memory map
*/
-#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE 0x80000000
+#endif
#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x80800000
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
@@ -65,18 +68,16 @@
* Serial driver
*/
#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (115200 * 16)
-#define CONFIG_SYS_NS16550_COM1 0xb80003f8
-#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_PORT_MAPPED
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE 0xbe000000
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
+#else
+# define CONFIG_SYS_FLASH_BASE 0xbe000000
+#endif
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
new file mode 100644
index 0000000..37a5671
--- /dev/null
+++ b/include/configs/odroid-c2.h
@@ -0,0 +1,51 @@
+/*
+ * Configuration for ODROID-C2
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_TEXT_BASE 0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xc4301000
+#define GICC_BASE 0xc4302000
+
+#define CONFIG_IDENT_STRING " odroid-c2"
+
+/* Serial setup */
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index dfb8d3a..913256a 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -10,7 +10,6 @@
/*
* BOARD/CPU
*/
-
#define CONFIG_SYS_CLK_FREQ 50000000
#define CONFIG_SYS_RESET_ADDR 0x00000100
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
new file mode 100644
index 0000000..257283f
--- /dev/null
+++ b/include/configs/p2771-0000.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#endif
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index caf75a6..b907419 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -80,12 +80,6 @@
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-/* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */
-/* SDRAM version */
-#define CONFIG_SYS_TEXT_BASE 0x83800000
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
@@ -150,12 +144,6 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* BOOTP options
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 108c6a2..319e3b5 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -10,7 +10,6 @@
#define __PIC32MZDASK_CONFIG_H
/* System Configuration */
-#define CONFIG_SYS_TEXT_BASE 0x9d004000 /* .text */
#define CONFIG_DISPLAY_BOARDINFO
/*--------------------------------------------
@@ -101,7 +100,6 @@
* USB Configuration
*/
#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* File System Configuration
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 702967c..f58fc4c 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -107,7 +107,6 @@
* FLASH and environment organization
*/
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
@@ -133,11 +132,4 @@
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 2394549..2190d16 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -107,7 +107,6 @@
* FLASH and environment organization
*/
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
@@ -133,11 +132,4 @@
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8a81397..9d50d83 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -69,7 +69,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_PINCTRL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_RAM_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index af58182..9ef5eae 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -106,6 +106,7 @@
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
#define CONFIG_MISC_INIT_R
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 5fe21d9..a46ca74 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -35,7 +35,6 @@
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* USB */
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
/* DRAM Memory Banks */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f657766..1f8b7b3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -324,9 +324,6 @@
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -349,9 +346,9 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#define CONFIG_SPL_LIBDISK_SUPPORT
#else
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */
+#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#endif
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index efa9e42..c097f47 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -22,7 +22,7 @@
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
new file mode 100644
index 0000000..1ccde1a
--- /dev/null
+++ b/include/configs/socfpga_vining_fpga.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
+#define __CONFIG_SAMTEC_VINING_FPGA_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_LED
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run selboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
+#endif
+
+/*
+ * Status LEDs:
+ * 0 ... Top Green
+ * 1 ... Top Red
+ * 2 ... Bottom Green
+ * 3 ... Bottom Red
+ */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT 48
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1 53
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2 54
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT3 65
+#define STATUS_LED_STATE3 STATUS_LED_OFF
+#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_vining_fpga
+
+/*
+ * Active LOW GPIO buttons:
+ * A: GPIO 77 ... the button between USB B and ethernet
+ * B: GPIO 78 ... the button between USB A ports
+ *
+ * The logic:
+ * if button B is not pressed, boot normal Linux system immediatelly
+ * if button B is pressed, wait $bootdelay and boot recovery system
+ */
+#define CONFIG_PREBOOT \
+ "setenv hostname vining-${unit_serial} ; " \
+ "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
+ "if gpio input 78 ; then " \
+ "setenv bootdelay 10 ; " \
+ "setenv boottype rcvr ; " \
+ "else " \
+ "setenv bootdelay 5 ; " \
+ "setenv boottype norm ; " \
+ "fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "consdev=ttyS0\0" \
+ "baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
+ "ubimtdnr=5\0" \
+ "ubimtd=rootfs\0" \
+ "ubipart=ubi0:rootfs\0" \
+ "ubisfcs=1\0" /* Default is flash at CS#1 */ \
+ "netdev=eth0\0" \
+ "hostname=vining_fpga\0" \
+ "kernel_addr_r=0x10000000\0" \
+ "mtdparts_0=ff705000.spi.0:" \
+ "1m(u-boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "256k(samtec1)," \
+ "256k(samtec2)," \
+ "-(rcvrfs)\0" /* Recovery */ \
+ "mtdparts_1=ff705000.spi.1:" \
+ "32m(rootfs)," \
+ "-(userfs)\0" \
+ "update_filename=u-boot-with-spl-dtb.sfp\0" \
+ "update_qspi_offset=0x0\0" \
+ "update_qspi=" /* Update the QSPI firmware */ \
+ "if sf probe ; then " \
+ "if tftp ${update_filename} ; then " \
+ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+ "fi ; " \
+ "fi\0" \
+ "fpga_filename=output_file.rbf\0" \
+ "load_fpga=" /* Load FPGA bitstream */ \
+ "if tftp ${fpga_filename} ; then " \
+ "fpga load 0 $loadaddr $filesize ; " \
+ "bridge enable ; " \
+ "fi\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addmtd=" \
+ "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \
+ "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
+ "addargs=run addcons addmtd addmisc\0" \
+ "ubiload=" \
+ "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
+ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "ubiargs=" \
+ "setenv bootargs ubi.mtd=${ubimtdnr} " \
+ "root=${ubipart} rootfstype=ubifs\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "ubi_sfsel=" \
+ "if test \"${boottype}\" = \"rcvr\" ; then " \
+ "setenv ubisfcs 0 ; " \
+ "setenv ubimtd rcvrfs ; " \
+ "setenv ubimtdnr 5 ; " \
+ "setenv mtdparts mtdparts=${mtdparts_0} ; " \
+ "setenv mtdids nor0=ff705000.spi.0 ; " \
+ "setenv ubipart ubi0:rootfs ; " \
+ "else " \
+ "setenv ubisfcs 1 ; " \
+ "setenv ubimtd rootfs ; " \
+ "setenv ubimtdnr 6 ; " \
+ "setenv mtdparts mtdparts=${mtdparts_1} ; " \
+ "setenv mtdids nor0=ff705000.spi.1 ; " \
+ "setenv ubipart ubi0:rootfs ; " \
+ "fi ; " \
+ "sf probe 0:${ubisfcs}\0" \
+ "ubi_ubi=" \
+ "run ubi_sfsel ubiload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_nfs=" \
+ "run ubiload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_ubi=" \
+ "run netload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "selboot=" /* Select from where to boot. */ \
+ "if test \"${bootmode}\" = \"qspi\" ; then " \
+ "led all off ; " \
+ "if test \"${boottype}\" = \"rcvr\" ; then " \
+ "echo \"Booting recovery system\" ; " \
+ "led 3 on ; " /* Bottom RED */ \
+ "fi ; " \
+ "led 1 on ; " /* Top RED */ \
+ "run ubi_ubi ; " \
+ "else echo \"Unsupported boot mode: \"${bootmode} ; " \
+ "fi\0" \
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT \
+ "mtdparts=ff705000.spi.0:" \
+ "1m(u-boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "256k(samtec1)," \
+ "256k(samtec2)," \
+ "-(rcvrfs);" /* Recovery */ \
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/* Enable DFU to SF and RAM */
+#define CONFIG_DFU_RAM
+#define CONFIG_DFU_SF
+
+/* Support changing the prompt string */
+#define CONFIG_CMDLINE_PS_SUPPORT
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 5803b66..90492f4 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -20,8 +20,12 @@
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#ifdef CONFIG_STRIDER_CPU
+#ifdef CONFIG_STRIDER_CPU_DP
+#define CONFIG_IDENT_STRING " strider cpu dp 0.01"
+#elif defined(CONFIG_STRIDER_CPU)
#define CONFIG_IDENT_STRING " strider cpu 0.01"
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_IDENT_STRING " strider con dp 0.01"
#else
#define CONFIG_IDENT_STRING " strider con 0.01"
#endif
@@ -225,15 +229,11 @@
/*
* FLASH on the Local Bus
*/
-#if 1
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#else
-#define CONFIG_SYS_NO_FLASH
-#endif
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
@@ -341,6 +341,22 @@
#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
+#endif
+
/*
* Software (bit-bang) I2C driver configuration
*/
@@ -357,7 +373,7 @@
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
-#ifdef CONFIG_STRIDER_CON
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
#define I2C_SOFT_DECLARATIONS5
#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
@@ -371,6 +387,20 @@
#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
#endif
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
+#endif
#ifdef CONFIG_STRIDER_CON
#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
@@ -379,6 +409,19 @@
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
{12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
+#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
+#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
+ {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CPU_DP)
+#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
+ {8, 0x4c} }
#else
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
@@ -391,6 +434,8 @@
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
#endif
#ifdef CONFIG_STRIDER_CON
@@ -398,12 +443,28 @@
#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
#else
#define I2C_SDA_GPIO 0x0040
#define I2C_SCL_GPIO 0x0020
#define I2C_FPGA_IDX I2C_ADAP_HWNR
#endif
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_ACTIVE \
+ do { \
+ if (I2C_ADAP_HWNR > 7) \
+ fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+ else \
+ fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+ } while (0)
+#else
#define I2C_ACTIVE { }
+#endif
+
#define I2C_TRISTATE { }
#define I2C_READ \
(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
@@ -436,6 +497,10 @@
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_OSD_DH
+#endif
+
/*
* General PCI
* Addresses are mapped 1-1.
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ac2d931..b33cfb8 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -189,14 +189,14 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#if defined(CONFIG_MACH_SUN9I)
-#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */
+#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */
#elif defined(CONFIG_MACH_SUN50I)
-#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */
+#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */
#else
-#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
+#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */
#endif
#define CONFIG_SPL_LIBDISK_SUPPORT
@@ -390,6 +390,23 @@
#define CONFIG_PRE_CONSOLE_BUFFER
#define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */
+#ifdef CONFIG_ARM64
+/*
+ * Boards seem to come with at least 512MB of DRAM.
+ * The kernel should go at 512K, which is the default text offset (that will
+ * be adjusted at runtime if needed).
+ * There is no compression for arm64 kernels (yet), so leave some space
+ * for really big kernels, say 256MB for now.
+ * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
+ * Align the initrd to a 2MB page.
+ */
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000))
+
+#else
/*
* 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
@@ -401,6 +418,7 @@
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0xa000000\0" \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 92d4dd8..7b0940a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -111,7 +111,6 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_ENTERRCM
/* Defines for SPL */
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000..aa7b9d0
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE 0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#endif
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 7c35d8c..e43a7fd 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -17,7 +17,6 @@
#define CONFIG_IDENT_STRING \
" for Cavium Thunder CN88XX ARM v8 Multi-Core"
-#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
#define MEM_BASE 0x00500000
@@ -62,7 +61,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 7db0881..ba7cf15 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -59,7 +59,7 @@
#define DEFAULT_MMC_TI_ARGS \
"mmcdev=0\0" \
"mmcrootfstype=ext4 rootwait\0" \
- "finduuid=part uuid mmc 0:2 uuid\0" \
+ "finduuid=part uuid mmc ${bootpart} uuid\0" \
"args_mmc=run finduuid;setenv bootargs console=${console} " \
"${optargs} " \
"root=PARTUUID=${uuid} rw " \
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2c9028c..707106f 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -191,8 +191,6 @@
"-(ubifs)"
/* USB Configuration */
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 2135af0..5c5a12d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -130,13 +130,35 @@
/*
* SPL related defines. The Public RAM memory map the ROM defines the
- * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
- * (dra7xx is larger, but we do not need to be larger at this time). We
- * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
+ * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
+ * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
* print some information.
*/
-#define CONFIG_SPL_TEXT_BASE 0x40300000
-#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_TI_SECURE_DEVICE
+/*
+ * For memory booting on HS parts, the first 4KB of the internal RAM is
+ * reserved for secure world use and the flash loader image is
+ * preceded by a secure certificate. The SPL will therefore run in internal
+ * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
+ */
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
+#define CONFIG_SPL_TEXT_BASE 0x40301350
+#else
+/*
+ * For all booting on GP parts, the flash loader image is
+ * downloaded into internal RAM at address 0x40300000.
+ */
+#define CONFIG_SPL_TEXT_BASE 0x40300000
+#endif
+
+/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#define TI_ROM_BOOT_LOAD_END 0x4037E000
+#else
+#define TI_ROM_BOOT_LOAD_END 0x4031E000
+#endif
+#define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 2b9e92e..abe1da2 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_TEXT_BASE 0xa1000000
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
@@ -85,8 +78,6 @@
#define CONFIG_SYS_MEMTEST_END 0x83f00000
#define CONFIG_CMD_MEMTEST
-#define CONFIG_USE_PRIVATE_LIBGCC
-
#define CONFIG_CMD_MII
#define CONFIG_PHY_GIGE
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 18cb963..10fd8c2 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -104,7 +104,11 @@
#define COUNTER_FREQUENCY 50000000
#define CONFIG_GICV3
#define GICD_BASE 0x5fe00000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define GICR_BASE 0x5fe40000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE 0x5fe80000
+#endif
#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
@@ -270,7 +274,9 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_STACK (0x30014c00)
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK (0x3001c000)
#else
#define CONFIG_SPL_STACK (0x00100000)
@@ -301,7 +307,11 @@
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_BSS_START_ADDR 0x30012000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR 0x30016000
+#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 6489e08..cc5e354 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -32,7 +32,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
-#define CONFIG_SYS_TEXT_BASE 0x87000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
@@ -205,13 +204,6 @@
#endif /* CONFIG_VCT_ONENAND */
/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
* I2C/EEPROM
*/
#define CONFIG_SYS_I2C
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 1b5fc2e..6a37582 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -23,7 +23,6 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_IDENT_STRING " vexpress_aemv8a"
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv8.vexpress_aemv8a"
/* Link Definitions */
#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
@@ -146,7 +145,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index 883e58e..b509a9c 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -12,7 +12,6 @@
#define __VEXPRESS_CA15X2_TC2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca15x2_tc2"
#include "vexpress_common.h"
#define CONFIG_SYSFLAGS_ADDR 0x1c010030
diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h
index 4385027..20b92dc 100644
--- a/include/configs/vexpress_ca5x2.h
+++ b/include/configs/vexpress_ca5x2.h
@@ -12,7 +12,6 @@
#define __VEXPRESS_CA5X2_h
#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca5x2"
#include "vexpress_common.h"
#endif /* __VEXPRESS_CA5X2_h */
diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h
index 99be50a..993398c 100644
--- a/include/configs/vexpress_ca9x4.h
+++ b/include/configs/vexpress_ca9x4.h
@@ -12,7 +12,6 @@
#define __VEXPRESS_CA9X4_H
#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7.vexpress_ca9x4"
#include "vexpress_common.h"
#endif /* VEXPRESS_CA9X4_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 5fdd2be..07c8abe 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -80,6 +80,8 @@
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
#define CONFIG_SPEAR_GPIO
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index b2fa164..b848150 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -76,11 +76,9 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
-#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
/* Diff from config_distro_defaults.h */
#define CONFIG_SUPPORT_RAW_INITRD
@@ -106,7 +104,6 @@
#endif
#ifdef CONFIG_NAND_ARASAN
-# define CONFIG_CMD_NAND
# define CONFIG_CMD_NAND_LOCK_UNLOCK
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_SELF_INIT
@@ -118,8 +115,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
@@ -149,21 +144,6 @@
# define DFU_ALT_INFO
#endif
-/* Initial environment variables */
-#ifndef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr=0x80000\0" \
- "fdt_addr=0x7000000\0" \
- "fdt_high=0x10000000\0" \
- CONFIG_KERNEL_FDT_OFST_SIZE \
- "sdbootdev=0\0"\
- "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
- "load mmc $sdbootdev:$partid $kernel_addr Image && " \
- "booti $kernel_addr - $fdt_addr\0" \
- DFU_ALT_INFO
-#endif
-
-#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOARD_LATE_INIT
@@ -191,6 +171,8 @@
# define CONFIG_PHY_NATSEMI
# define CONFIG_PHY_TI
# define CONFIG_PHY_GIGE
+# define CONFIG_PHY_VITESSE
+# define CONFIG_PHY_REALTEK
# define PHY_ANEG_TIMEOUT 20000
#endif
@@ -211,7 +193,8 @@
# define CONFIG_SYS_EEPROM_SIZE (64 * 1024)
#endif
-#ifdef CONFIG_AHCI
+#ifdef CONFIG_SATA_CEVA
+#define CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
@@ -230,6 +213,50 @@
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_high=10000000\0" \
+ "initrd_high=10000000\0" \
+ "fdt_addr_r=0x40000000\0" \
+ "pxefile_addr_r=0x10000000\0" \
+ "kernel_addr_r=0x18000000\0" \
+ "scriptaddr=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0" \
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_SATA_CEVA)
+# define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
+#else
+# define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_USB)
+# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
+#else
+# define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ BOOT_TARGET_DEVICES_SCSI(func) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV \
+ DFU_ALT_INFO
+#endif
+
#define CONFIG_SPL_TEXT_BASE 0xfffc0000
#define CONFIG_SPL_MAX_SIZE 0x20000
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 9506355..c5bd5da 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -22,13 +22,6 @@
#define COUNTER_FREQUENCY 4000000
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
- "kernel_offset=0x400000\0" \
- "fdt_offset=0x2400000\0" \
- "kernel_size=0x2000000\0" \
- "fdt_size=0x80000\0" \
- "board=ep108\0"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_EP_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 3c0ba88..c9f4432 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -17,13 +17,6 @@
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
- "kernel_offset=0x400000\0" \
- "fdt_offset=0x2400000\0" \
- "kernel_size=0x2000000\0" \
- "fdt_size=0x80000\0" \
- "board=zc1751-dc1\0"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 83ea624..526d0bb 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -14,13 +14,6 @@
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
- "kernel_offset=0x400000\0" \
- "fdt_offset=0x2400000\0" \
- "kernel_size=0x2000000\0" \
- "fdt_size=0x80000\0" \
- "board=zc1751-dc2\0"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
new file mode 100644
index 0000000..65277a6
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
@@ -0,0 +1,17 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM018 DC4
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+
+#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 4f8f5c1..76350d9 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -15,13 +15,6 @@
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
- "kernel_offset=0x400000\0" \
- "fdt_offset=0x2400000\0" \
- "kernel_size=0x2000000\0" \
- "fdt_size=0x80000\0" \
- "board=zc1751-dc5\0"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 81079fe..7ceab32 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -41,7 +41,6 @@
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_AHCI
#define CONFIG_SATA_CEVA
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
@@ -54,13 +53,6 @@
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
- "kernel_offset=0x180000\0" \
- "fdt_offset=0x100000\0" \
- "kernel_size=0x1e00000\0" \
- "fdt_size=0x80000\0" \
- "board=zcu102\0"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZCU102_H */
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index b348ad5..0bf8707 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -39,6 +39,30 @@
struct udevice **devp);
/**
+ * device_bind_with_driver_data() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver, in the case where the
+ * driver was matched to the device by means of a match table that provides
+ * driver_data.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @driver_data: The driver_data field from the driver's match table.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_with_driver_data(struct udevice *parent,
+ const struct driver *drv, const char *name,
+ ulong driver_data, int of_offset,
+ struct udevice **devp);
+
+/**
* device_bind_by_name: Create a device and bind it to a driver
*
* This is a helper function used to bind devices which do not use device
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a5cf6e2..0777cbe 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -44,6 +44,7 @@
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
+ UCLASS_MAILBOX, /* Mailbox controller */
UCLASS_MASS_STORAGE, /* Mass storage device */
UCLASS_MISC, /* Miscellaneous device */
UCLASS_MMC, /* SD / MMC card or chip */
@@ -61,7 +62,6 @@
UCLASS_PWM, /* Pulse-width modulator */
UCLASS_PWRSEQ, /* Power sequence device */
UCLASS_REGULATOR, /* Regulator device */
- UCLASS_RESET, /* Reset device */
UCLASS_REMOTEPROC, /* Remote Processor device */
UCLASS_RTC, /* Real time clock device */
UCLASS_SERIAL, /* Serial UART */
@@ -70,6 +70,7 @@
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SYSCON, /* System configuration device */
+ UCLASS_SYSRESET, /* System reset device */
UCLASS_THERMAL, /* Thermal sensor */
UCLASS_TIMER, /* Timer device */
UCLASS_TPM, /* Trusted Platform Module TIS interface */
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28..a1c09e8 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
#include <dt-bindings/gpio/gpio.h>
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
-#define TEGRA_GPIO(bank, offset) \
- ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+ ((TEGRA_GPIO_PORT_##port * 8) + offset)
#endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 0000000..7e6fb95
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+ ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+ ((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
index 7203687..292c2eb 100644
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -30,4 +30,10 @@
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (INPUT_EN)
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val)
+
#endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 1dd7636..672a136 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -53,5 +53,42 @@
#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX 0x152
+#define OMAP3_UART2_RX 0x14a
+#define OMAP3_UART3_RX 0x16e
+#define OMAP4_UART2_RX 0xdc
+#define OMAP4_UART3_RX 0x104
+#define OMAP4_UART4_RX 0x11c
+
#endif
diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
new file mode 100644
index 0000000..f5cb772
--- /dev/null
+++ b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
@@ -0,0 +1,8 @@
+#ifndef __DT_TLV320AIC31XX_MICBIAS_H
+#define __DT_TLV320AIC31XX_MICBIAS_H
+
+#define MICBIAS_2_0V 1
+#define MICBIAS_2_5V 2
+#define MICBIAS_AVDDV 3
+
+#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 09ff8a7..7af2ad1 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -13,7 +13,7 @@
#include <linux/usb/otg.h>
struct dwc3_device {
- int base;
+ unsigned long base;
enum usb_dr_mode dr_mode;
u32 maximum_speed;
unsigned tx_fifo_resize:1;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 05b0817..335af51 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -180,8 +180,9 @@
* @freq: Frequency the host is trying to achieve
*/
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
-
+#ifndef CONFIG_BLK
struct mmc_config cfg;
+#endif
/* use fifo mode to read and write data */
bool fifo_mode;
@@ -223,5 +224,9 @@
return readb(host->ioaddr + reg);
}
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk);
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
#endif /* __DWMMC_HW_H */
diff --git a/include/efi_api.h b/include/efi_api.h
index 51d7586..f572b88 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -17,6 +17,10 @@
#include <efi.h>
+#ifdef CONFIG_EFI_LOADER
+#include <asm/setjmp.h>
+#endif
+
/* Types and defines for EFI CreateEvent */
enum efi_event_type {
EFI_TIMER_STOP = 0,
@@ -239,6 +243,12 @@
unsigned int image_code_type;
unsigned int image_data_type;
unsigned long unload;
+
+ /* Below are efi loader private fields */
+#ifdef CONFIG_EFI_LOADER
+ efi_status_t exit_status;
+ struct jmp_buf_data exit_jmp;
+#endif
};
#define DEVICE_PATH_GUID \
@@ -412,4 +422,123 @@
struct efi_gop_mode *mode;
};
+#define EFI_SIMPLE_NETWORK_GUID \
+ EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
+ 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_mac_address {
+ char mac_addr[32];
+};
+
+struct efi_ip_address {
+ u8 ip_addr[16];
+};
+
+enum efi_simple_network_state {
+ EFI_NETWORK_STOPPED,
+ EFI_NETWORK_STARTED,
+ EFI_NETWORK_INITIALIZED,
+};
+
+struct efi_simple_network_mode {
+ enum efi_simple_network_state state;
+ u32 hwaddr_size;
+ u32 media_header_size;
+ u32 max_packet_size;
+ u32 nvram_size;
+ u32 nvram_access_size;
+ u32 receive_filter_mask;
+ u32 receive_filter_setting;
+ u32 max_mcast_filter_count;
+ u32 mcast_filter_count;
+ struct efi_mac_address mcast_filter[16];
+ struct efi_mac_address current_address;
+ struct efi_mac_address broadcast_address;
+ struct efi_mac_address permanent_address;
+ u8 if_type;
+ u8 mac_changeable;
+ u8 multitx_supported;
+ u8 media_present_supported;
+ u8 media_present;
+};
+
+#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01,
+#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02,
+#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10,
+
+struct efi_simple_network
+{
+ u64 revision;
+ efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this,
+ ulong extra_rx, ulong extra_tx);
+ efi_status_t (EFIAPI *reset)(struct efi_simple_network *this,
+ int extended_verification);
+ efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this);
+ efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this,
+ u32 enable, u32 disable, int reset_mcast_filter,
+ ulong mcast_filter_count,
+ struct efi_mac_address *mcast_filter);
+ efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this,
+ int reset, struct efi_mac_address *new_mac);
+ efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this,
+ int reset, ulong *stat_size, void *stat_table);
+ efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this,
+ int ipv6, struct efi_ip_address *ip,
+ struct efi_mac_address *mac);
+ efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this,
+ int read_write, ulong offset, ulong buffer_size,
+ char *buffer);
+ efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this,
+ u32 *int_status, void **txbuf);
+ efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this,
+ ulong header_size, ulong buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol);
+ efi_status_t (EFIAPI *receive)(struct efi_simple_network *this,
+ ulong *header_size, ulong *buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol);
+ void (EFIAPI *waitforpacket)(void);
+ struct efi_simple_network_mode *mode;
+};
+
+#define EFI_PXE_GUID \
+ EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
+ 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_pxe_packet {
+ u8 packet[1472];
+};
+
+struct efi_pxe_mode
+{
+ u8 unused[52];
+ struct efi_pxe_packet dhcp_discover;
+ struct efi_pxe_packet dhcp_ack;
+ struct efi_pxe_packet proxy_offer;
+ struct efi_pxe_packet pxe_discover;
+ struct efi_pxe_packet pxe_reply;
+};
+
+struct efi_pxe {
+ u64 rev;
+ void (EFIAPI *start)(void);
+ void (EFIAPI *stop)(void);
+ void (EFIAPI *dhcp)(void);
+ void (EFIAPI *discover)(void);
+ void (EFIAPI *mftp)(void);
+ void (EFIAPI *udpwrite)(void);
+ void (EFIAPI *udpread)(void);
+ void (EFIAPI *setipfilter)(void);
+ void (EFIAPI *arp)(void);
+ void (EFIAPI *setparams)(void);
+ void (EFIAPI *setstationip)(void);
+ void (EFIAPI *setpackets)(void);
+ struct efi_pxe_mode *mode;
+};
+
#endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 88b8149..9738835 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -15,18 +15,10 @@
#include <linux/list.h>
-/* #define DEBUG_EFI */
-
-#ifdef DEBUG_EFI
#define EFI_ENTRY(format, ...) do { \
efi_restore_gd(); \
- printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
+ debug("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
} while(0)
-#else
-#define EFI_ENTRY(format, ...) do { \
- efi_restore_gd(); \
- } while(0)
-#endif
#define EFI_EXIT(ret) efi_exit_func(ret);
@@ -91,6 +83,12 @@
int efi_disk_register(void);
/* Called by bootefi to make GOP (graphical) interface available */
int efi_gop_register(void);
+/* Called by bootefi to make the network interface available */
+int efi_net_register(void **handle);
+
+/* Called by networking code to memorize the dhcp ack package */
+void efi_net_set_dhcp_ack(void *pkt, int len);
+
/*
* Stub implementation for a protocol opener that just returns the handle as
* interface
@@ -133,8 +131,13 @@
/* Called by board init to initialize the EFI memory map */
int efi_memory_init(void);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+extern void *efi_bounce_buffer;
+#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
+#endif
+
/* Convert strings from normal C strings to uEFI strings */
-static inline void ascii2unicode(u16 *unicode, char *ascii)
+static inline void ascii2unicode(u16 *unicode, const char *ascii)
{
while (*ascii)
*(unicode++) = *(ascii++);
@@ -157,5 +160,6 @@
static inline void efi_restore_gd(void) { }
static inline void efi_set_bootdev(const char *dev, const char *devnr,
const char *path) { }
+static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 37d482a..54e3d81 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -123,6 +123,7 @@
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */
COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644
index 0000000..281a819
--- /dev/null
+++ b/include/fsl_mmdc.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
+
+#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN 0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN 0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN 0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
+
+#define START_REFRESH 0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
+
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+
+#define DISABLE_CFG_REQ 0x0
+#define CONFIGURATION_REQ (0x1 << 15)
+#define WL_EN (0x1 << 9)
+
+#define CMD_NORMAL (0x0 << 4)
+#define CMD_PRECHARGE (0x1 << 4)
+#define CMD_AUTO_REFRESH (0x2 << 4)
+#define CMD_LOAD_MODE_REG (0x3 << 4)
+#define CMD_ZQ_CALIBRATION (0x4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
+#define CMD_MRR (0x6 << 4)
+
+#define CMD_BANK_ADDR_0 0x0
+#define CMD_BANK_ADDR_1 0x1
+#define CMD_BANK_ADDR_2 0x2
+#define CMD_BANK_ADDR_3 0x3
+#define CMD_BANK_ADDR_4 0x4
+#define CMD_BANK_ADDR_5 0x5
+#define CMD_BANK_ADDR_6 0x6
+#define CMD_BANK_ADDR_7 0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 mdmrr;
+ u32 mdcfg3lp;
+ u32 mdmr4;
+ u32 mdasp;
+ u32 res2[239];
+ u32 maarcr;
+ u32 mapsr;
+ u32 maexidr0;
+ u32 maexidr1;
+ u32 madpcr0;
+ u32 madpcr1;
+ u32 madpsr0;
+ u32 madpsr1;
+ u32 madpsr2;
+ u32 madpsr3;
+ u32 madpsr4;
+ u32 madpsr5;
+ u32 masbs0;
+ u32 masbs1;
+ u32 res3[2];
+ u32 magenp;
+ u32 res4[239];
+ u32 mpzqhwctrl;
+ u32 mpzqswctrl;
+ u32 mpwlgcr;
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 mpwldlst;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res5[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 mpdgdlst0;
+ u32 mprddlctl;
+ u32 mprddlst;
+ u32 mpwrdlctl;
+ u32 mpwrdlst;
+ u32 mpsdctrl;
+ u32 mpzqlp2ctl;
+ u32 mprddlhwctl;
+ u32 mpwrdlhwctl;
+ u32 mprddlhwst0;
+ u32 mprddlhwst1;
+ u32 mpwrdlhwst0;
+ u32 mpwrdlhwst1;
+ u32 mpwlhwerr;
+ u32 mpdghwst0;
+ u32 mpdghwst1;
+ u32 mpdghwst2;
+ u32 mpdghwst3;
+ u32 mppdcmpr1;
+ u32 mppdcmpr2;
+ u32 mpswdar0;
+ u32 mpswdrdr0;
+ u32 mpswdrdr1;
+ u32 mpswdrdr2;
+ u32 mpswdrdr3;
+ u32 mpswdrdr4;
+ u32 mpswdrdr5;
+ u32 mpswdrdr6;
+ u32 mpswdrdr7;
+ u32 mpmur0;
+ u32 mpwrcadl;
+ u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 3b8762d..e1b9c64 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -163,7 +163,7 @@
};
#endif
-#ifdef CONFIG_HRCON
+#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
diff --git a/include/linux/mtd/docg4.h b/include/linux/mtd/docg4.h
deleted file mode 100644
index 741fc0d..0000000
--- a/include/linux/mtd/docg4.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DOCG4_H__
-#define __DOCG4_H__
-
-#include <common.h>
-#include <linux/mtd/nand.h>
-
-extern int docg4_nand_init(struct mtd_info *mtd,
- struct nand_chip *nand, int devnum);
-
-/* SPL-related definitions */
-#define DOCG4_IPL_LOAD_BLOCK_COUNT 2 /* number of blocks that IPL loads */
-#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
-
-#define DOC_IOSPACE_DATA 0x0800
-
-/* register offsets */
-#define DOC_CHIPID 0x1000
-#define DOC_DEVICESELECT 0x100a
-#define DOC_ASICMODE 0x100c
-#define DOC_DATAEND 0x101e
-#define DOC_NOP 0x103e
-
-#define DOC_FLASHSEQUENCE 0x1032
-#define DOC_FLASHCOMMAND 0x1034
-#define DOC_FLASHADDRESS 0x1036
-#define DOC_FLASHCONTROL 0x1038
-#define DOC_ECCCONF0 0x1040
-#define DOC_ECCCONF1 0x1042
-#define DOC_HAMMINGPARITY 0x1046
-#define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
-
-#define DOC_ASICMODECONFIRM 0x1072
-#define DOC_CHIPID_INV 0x1074
-#define DOC_POWERMODE 0x107c
-
-#define DOCG4_MYSTERY_REG 0x1050
-
-/* apparently used only to write oob bytes 6 and 7 */
-#define DOCG4_OOB_6_7 0x1052
-
-/* DOC_FLASHSEQUENCE register commands */
-#define DOC_SEQ_RESET 0x00
-#define DOCG4_SEQ_PAGE_READ 0x03
-#define DOCG4_SEQ_FLUSH 0x29
-#define DOCG4_SEQ_PAGEWRITE 0x16
-#define DOCG4_SEQ_PAGEPROG 0x1e
-#define DOCG4_SEQ_BLOCKERASE 0x24
-
-/* DOC_FLASHCOMMAND register commands */
-#define DOCG4_CMD_PAGE_READ 0x00
-#define DOC_CMD_ERASECYCLE2 0xd0
-#define DOCG4_CMD_FLUSH 0x70
-#define DOCG4_CMD_READ2 0x30
-#define DOC_CMD_PROG_BLOCK_ADDR 0x60
-#define DOCG4_CMD_PAGEWRITE 0x80
-#define DOC_CMD_PROG_CYCLE2 0x10
-#define DOC_CMD_RESET 0xff
-
-/* DOC_POWERMODE register bits */
-#define DOC_POWERDOWN_READY 0x80
-
-/* DOC_FLASHCONTROL register bits */
-#define DOC_CTRL_CE 0x10
-#define DOC_CTRL_UNKNOWN 0x40
-#define DOC_CTRL_FLASHREADY 0x01
-
-/* DOC_ECCCONF0 register bits */
-#define DOC_ECCCONF0_READ_MODE 0x8000
-#define DOC_ECCCONF0_UNKNOWN 0x2000
-#define DOC_ECCCONF0_ECC_ENABLE 0x1000
-#define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
-
-/* DOC_ECCCONF1 register bits */
-#define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
-#define DOC_ECCCONF1_ECC_ENABLE 0x07
-#define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
-
-/* DOC_ASICMODE register bits */
-#define DOC_ASICMODE_RESET 0x00
-#define DOC_ASICMODE_NORMAL 0x01
-#define DOC_ASICMODE_POWERDOWN 0x02
-#define DOC_ASICMODE_MDWREN 0x04
-#define DOC_ASICMODE_BDETCT_RESET 0x08
-#define DOC_ASICMODE_RSTIN_RESET 0x10
-#define DOC_ASICMODE_RAM_WE 0x20
-
-/* good status values read after read/write/erase operations */
-#define DOCG4_PROGSTATUS_GOOD 0x51
-#define DOCG4_PROGSTATUS_GOOD_2 0xe0
-
-/*
- * On read operations (page and oob-only), the first byte read from I/O reg is a
- * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
- * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
- */
-#define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
-
-/* anatomy of the device */
-#define DOCG4_CHIP_SIZE 0x8000000
-#define DOCG4_PAGE_SIZE 0x200
-#define DOCG4_PAGES_PER_BLOCK 0x200
-#define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
-#define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
-#define DOCG4_OOB_SIZE 0x10
-#define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
-#define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
-#define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
-
-/* all but the last byte is included in ecc calculation */
-#define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
-
-#define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
-
-/* expected values from the ID registers */
-#define DOCG4_IDREG1_VALUE 0x0400
-#define DOCG4_IDREG2_VALUE 0xfbff
-
-/* primitive polynomial used to build the Galois field used by hw ecc gen */
-#define DOCG4_PRIMITIVE_POLY 0x4443
-
-#define DOCG4_M 14 /* Galois field is of order 2^14 */
-#define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
-
-#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
-
-#endif /* __DOCG4_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 9da77ec..cf20674 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -278,6 +278,11 @@
int usecount;
};
+static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
+{
+ return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+}
+
int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
#ifndef __UBOOT__
int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 23072fd..b5a02c3 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -25,6 +25,8 @@
struct mtd_info;
struct nand_flash_dev;
+struct device_node;
+
/* Scan and identify a NAND device */
extern int nand_scan(struct mtd_info *mtd, int max_chips);
/*
@@ -144,6 +146,14 @@
/* Enable Hardware ECC before syndrome is read back from flash */
#define NAND_ECC_READSYN 2
+/*
+ * Enable generic NAND 'page erased' check. This check is only done when
+ * ecc.correct() returns -EBADMSG.
+ * Set this flag if your implementation does not fix bitflips in erased
+ * pages and you want to rely on the default implementation.
+ */
+#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
+
/* Bit mask for flags passed to do_nand_read_ecc */
#define NAND_GET_DEVICE 0x80
@@ -179,6 +189,12 @@
/* Device supports subpage reads */
#define NAND_SUBPAGE_READ 0x00001000
+/*
+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
+ * patterns.
+ */
+#define NAND_NEED_SCRAMBLING 0x00002000
+
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
@@ -203,6 +219,11 @@
* before calling nand_scan_tail.
*/
#define NAND_BUSWIDTH_AUTO 0x00080000
+/*
+ * This option could be defined by controller drivers to protect against
+ * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
+ */
+#define NAND_USE_BOUNCE_BUFFER 0x00100000
/* Options set by nand scan */
/* bbt has already been read */
@@ -292,15 +313,15 @@
__le16 t_r;
__le16 t_ccs;
__le16 src_sync_timing_mode;
- __le16 src_ssync_features;
+ u8 src_ssync_features;
__le16 clk_pin_capacitance_typ;
__le16 io_pin_capacitance_typ;
__le16 input_pin_capacitance_typ;
u8 input_pin_capacitance_max;
u8 driver_strength_support;
__le16 t_int_r;
- __le16 t_ald;
- u8 reserved4[7];
+ __le16 t_adl;
+ u8 reserved4[8];
/* vendor */
__le16 vendor_revision;
@@ -423,7 +444,7 @@
__le16 input_pin_capacitance_typ;
__le16 clk_pin_capacitance_typ;
u8 driver_strength_support;
- __le16 t_ald;
+ __le16 t_adl;
u8 reserved4[36];
/* ECC and endurance block */
@@ -466,12 +487,19 @@
* @total: total number of ECC bytes per page
* @prepad: padding information for syndrome based ECC generators
* @postpad: padding information for syndrome based ECC generators
+ * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
* @layout: ECC layout control struct pointer
* @priv: pointer to private ECC control data
* @hwctl: function to control hardware ECC generator. Must only
* be provided if an hardware ECC is available
* @calculate: function for ECC calculation or readback from ECC hardware
- * @correct: function for ECC correction, matching to ECC generator (sw/hw)
+ * @correct: function for ECC correction, matching to ECC generator (sw/hw).
+ * Should return a positive number representing the number of
+ * corrected bitflips, -EBADMSG if the number of bitflips exceed
+ * ECC strength, or any other error code if the error is not
+ * directly related to correction.
+ * If -EBADMSG is returned the input buffers should be left
+ * untouched.
* @read_page_raw: function to read a raw page without ECC. This function
* should hide the specific layout used by the ECC
* controller and always return contiguous in-band and
@@ -509,6 +537,7 @@
int strength;
int prepad;
int postpad;
+ unsigned int options;
struct nand_ecclayout *layout;
void *priv;
void (*hwctl)(struct mtd_info *mtd, int mode);
@@ -519,16 +548,16 @@
int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page);
int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required);
+ const uint8_t *buf, int oob_required, int page);
int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page);
int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offs, uint32_t len, uint8_t *buf, int page);
int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, uint32_t data_len,
- const uint8_t *data_buf, int oob_required);
+ const uint8_t *data_buf, int oob_required, int page);
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required);
+ const uint8_t *buf, int oob_required, int page);
int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
int page);
int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
@@ -556,6 +585,7 @@
/**
* struct nand_chip - NAND Private Flash Chip Data
+ * @mtd: MTD device registered to the MTD framework
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
* flash device
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
@@ -571,10 +601,6 @@
* @block_markbad: [REPLACEABLE] mark a block bad
* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
* ALE/CLE/nCE. Also used to write command and address
- * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
- * mtd->oobsize, mtd->writesize and so on.
- * @id_data contains the 8 bytes values of NAND_CMD_READID.
- * Return with the bus width.
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
* device ready/busy line. If set to NULL no access to
* ready/busy is available and the ready/busy information
@@ -659,6 +685,7 @@
*/
struct nand_chip {
+ struct mtd_info mtd;
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
@@ -668,11 +695,9 @@
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
void (*select_chip)(struct mtd_info *mtd, int chip);
- int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+ int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
- int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
- u8 *id_data);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
int page_addr);
@@ -739,6 +764,26 @@
void *priv;
};
+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
+{
+ return container_of(mtd, struct nand_chip, mtd);
+}
+
+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
+{
+ return &chip->mtd;
+}
+
+static inline void *nand_get_controller_data(struct nand_chip *chip)
+{
+ return chip->priv;
+}
+
+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
+{
+ chip->priv = priv;
+}
+
/*
* NAND Flash Manufacturer ID Codes
*/
@@ -852,7 +897,6 @@
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
-extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_default_bbt(struct mtd_info *mtd);
extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
@@ -877,7 +921,6 @@
* @chip_delay: R/B delay value in us
* @options: Option flags, e.g. 16bit buswidth
* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
- * @ecclayout: ECC layout info structure
* @part_probe_types: NULL-terminated array of probe types
*/
struct platform_nand_chip {
@@ -885,7 +928,6 @@
int chip_offset;
int nr_partitions;
struct mtd_partition *partitions;
- struct nand_ecclayout *ecclayout;
int chip_delay;
unsigned int options;
unsigned int bbt_options;
@@ -934,15 +976,6 @@
struct platform_nand_ctrl ctrl;
};
-/* Some helpers to access the data structures */
-static inline
-struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- return chip->priv;
-}
-
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
/* return the supported features. */
static inline int onfi_feature(struct nand_chip *chip)
@@ -1060,4 +1093,9 @@
/* get timing characteristics from ONFI timing mode. */
const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
+
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+ void *ecc, int ecclen,
+ void *extraoob, int extraooblen,
+ int threshold);
#endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h
index d8754dd..8ea6b04 100644
--- a/include/linux/mtd/nand_bch.h
+++ b/include/linux/mtd/nand_bch.h
@@ -32,9 +32,7 @@
/*
* Initialize BCH encoder/decoder
*/
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
- unsigned int eccbytes, struct nand_ecclayout **ecclayout);
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
/*
* Release BCH encoder/decoder resources
*/
@@ -55,12 +53,10 @@
nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
unsigned char *read_ecc, unsigned char *calc_ecc)
{
- return -1;
+ return -ENOTSUPP;
}
-static inline struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
- unsigned int eccbytes, struct nand_ecclayout **ecclayout)
+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
{
return NULL;
}
diff --git a/include/linux/string.h b/include/linux/string.h
index c7047ba..091ccab 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -20,10 +20,6 @@
*/
#include <asm/string.h>
-#ifndef __HAVE_ARCH_BCOPY
-char *bcopy(const char *src, char *dest, int count);
-#endif
-
#ifndef __HAVE_ARCH_STRCPY
extern char * strcpy(char *,const char *);
#endif
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index c5e42e6..253eddf 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -59,10 +59,14 @@
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
diff --git a/include/mailbox_client.h b/include/mailbox_client.h
new file mode 100644
index 0000000..8345ea0
--- /dev/null
+++ b/include/mailbox_client.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_CLIENT_H
+#define _MAILBOX_CLIENT_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox_uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+ struct udevice *dev;
+ /*
+ * Written by of_xlate. We assume a single id is enough for now. In the
+ * future, we might add more fields here.
+ */
+ unsigned long id;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev: The client device.
+ * @index: The index of the mailbox channel to request, within the
+ * client's list of channels.
+ * @chan A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev: The client device.
+ * @name: The name of the mailbox channel to request, within the client's
+ * list of channels.
+ * @chan A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+ struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @data: A pointer to the message to transfer. The format and size of
+ * the memory region pointed at by @data is determined by the
+ * mailbox provider. Providers that solely transfer notifications
+ * will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan: A channel object that was previously successfully requested by
+ * calling mbox_get_by_*().
+ * @data: A pointer to the buffer to receive the message. The format and
+ * size of the memory region pointed at by @data is determined by
+ * the mailbox provider. Providers that solely transfer
+ * notifications will ignore this parameter.
+ * @timeout_us: The maximum time to wait for a message to be available, in
+ * micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
diff --git a/include/mailbox_uclass.h b/include/mailbox_uclass.h
new file mode 100644
index 0000000..6a2994c
--- /dev/null
+++ b/include/mailbox_uclass.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox_client.h for background documentation. */
+
+#include <mailbox_client.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+ /**
+ * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+ *
+ * The mailbox core calls this function as the first step in
+ * implementing a client's mbox_get_by_*() call.
+ *
+ * If this function pointer is set to NULL, the mailbox core will use
+ * a default implementation, which assumes #mbox-cells = <1>, and that
+ * the DT cell contains a simple integer channel ID.
+ *
+ * At present, the mailbox API solely supports device-tree. If this
+ * changes, other xxx_xlate() functions may be added to support those
+ * other mechanisms.
+ *
+ * @chan: The channel to hold the translation result.
+ * @args: The mailbox specifier values from device tree.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*of_xlate)(struct mbox_chan *chan,
+ struct fdtdec_phandle_args *args);
+ /**
+ * request - Request a translated channel.
+ *
+ * The mailbox core calls this function as the second step in
+ * implementing a client's mbox_get_by_*() call, following a successful
+ * xxx_xlate() call.
+ *
+ * @chan: The channel to request; this has been filled in by a
+ * previoux xxx_xlate() function call.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*request)(struct mbox_chan *chan);
+ /**
+ * free - Free a previously requested channel.
+ *
+ * This is the implementation of the client mbox_free() API.
+ *
+ * @chan: The channel to free.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*free)(struct mbox_chan *chan);
+ /**
+ * send - Send a message over a mailbox channel
+ *
+ * @chan: The channel to send to the message to.
+ * @data: A pointer to the message to send.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*send)(struct mbox_chan *chan, const void *data);
+ /**
+ * recv - Receive any available message from the channel.
+ *
+ * This function does not block. If not message is immediately
+ * available, the function should return an error.
+ *
+ * @chan: The channel to receive to the message from.
+ * @data: A pointer to the buffer to hold the received message.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative
+ * error code.
+ */
+ int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
diff --git a/include/mmc.h b/include/mmc.h
index a5c6573..7fdfc32 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -411,7 +411,6 @@
MMC_HWPART_CONF_COMPLETE,
};
-int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
/**
@@ -492,16 +491,12 @@
*/
void mmc_set_preinit(struct mmc *mmc, int preinit);
-#ifdef CONFIG_GENERIC_MMC
#ifdef CONFIG_MMC_SPI
#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
#else
#define mmc_host_is_spi(mmc) 0
#endif
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
-#else
-int mmc_legacy_init(int verbose);
-#endif
void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
diff --git a/include/nand.h b/include/nand.h
index 7cbbbd3..a4f0f92 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -33,34 +33,36 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
+int nand_mtd_to_devnum(struct mtd_info *mtd);
+
#ifdef CONFIG_SYS_NAND_SELF_INIT
void board_nand_init(void);
-int nand_register(int devnum);
+int nand_register(int devnum, struct mtd_info *mtd);
#else
extern int board_nand_init(struct nand_chip *nand);
#endif
-typedef struct mtd_info nand_info_t;
-
extern int nand_curr_device;
-extern nand_info_t nand_info[];
+extern struct mtd_info *nand_info[];
-static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
+ u_char *buf)
{
return mtd_read(info, ofs, *len, (size_t *)len, buf);
}
-static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_write(struct mtd_info *info, loff_t ofs, size_t *len,
+ u_char *buf)
{
return mtd_write(info, ofs, *len, (size_t *)len, buf);
}
-static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
+static inline int nand_block_isbad(struct mtd_info *info, loff_t ofs)
{
return mtd_block_isbad(info, ofs);
}
-static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
+static inline int nand_erase(struct mtd_info *info, loff_t off, size_t size)
{
struct erase_info instr;
@@ -96,27 +98,28 @@
typedef struct nand_erase_options nand_erase_options_t;
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
size_t *actual, loff_t lim, u_char *buffer);
#define WITH_DROP_FFS (1 << 0) /* drop trailing all-0xff pages */
#define WITH_WR_VERIFY (1 << 1) /* verify data was written correctly */
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
size_t *actual, loff_t lim, u_char *buffer, int flags);
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
-int nand_torture(nand_info_t *nand, loff_t offset);
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops,
- loff_t ofs);
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf);
+int nand_erase_opts(struct mtd_info *mtd,
+ const nand_erase_options_t *opts);
+int nand_torture(struct mtd_info *mtd, loff_t offset);
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+ loff_t ofs);
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf);
#define NAND_LOCK_STATUS_TIGHT 0x01
#define NAND_LOCK_STATUS_UNLOCK 0x04
-int nand_lock(nand_info_t *meminfo, int tight);
-int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length,
- int allexcept);
-int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
+int nand_lock(struct mtd_info *mtd, int tight);
+int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
+ int allexcept);
+int nand_get_lock_status(struct mtd_info *mtd, loff_t offset);
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
void nand_deselect(void);
@@ -135,6 +138,6 @@
#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
stored as byte number */
#define ENV_OFFSET_SIZE 8
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result);
#endif
int spl_nand_erase_one(int block, int page);
diff --git a/include/net.h b/include/net.h
index 05800c4..5ee5929 100644
--- a/include/net.h
+++ b/include/net.h
@@ -269,7 +269,7 @@
int eth_init(void); /* Initialize the device */
int eth_send(void *packet, int length); /* Send a packet */
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
int eth_receive(void *packet, int length); /* Receive a packet*/
extern void (*push_packet)(void *packet, int length);
#endif
diff --git a/include/reset.h b/include/reset.h
deleted file mode 100644
index 383761e..0000000
--- a/include/reset.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RESET_H
-#define __RESET_H
-
-enum reset_t {
- RESET_WARM, /* Reset CPU, keep GPIOs active */
- RESET_COLD, /* Reset CPU and GPIOs */
- RESET_POWER, /* Reset PMIC (remove and restore power) */
-
- RESET_COUNT,
-};
-
-struct reset_ops {
- /**
- * request() - request a reset of the given type
- *
- * Note that this function may return before the reset takes effect.
- *
- * @type: Reset type to request
- * @return -EINPROGRESS if the reset has been started and
- * will complete soon, -EPROTONOSUPPORT if not supported
- * by this device, 0 if the reset has already happened
- * (in which case this method will not actually return)
- */
- int (*request)(struct udevice *dev, enum reset_t type);
-};
-
-#define reset_get_ops(dev) ((struct reset_ops *)(dev)->driver->ops)
-
-/**
- * reset_request() - request a reset
- *
- * @type: Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
- */
-int reset_request(struct udevice *dev, enum reset_t type);
-
-/**
- * reset_walk() - cause a reset
- *
- * This works through the available reset devices until it finds one that can
- * perform a reset. If the provided reset type is not available, the next one
- * will be tried.
- *
- * If this function fails to reset, it will display a message and halt
- *
- * @type: Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
- */
-int reset_walk(enum reset_t type);
-
-/**
- * reset_walk_halt() - try to reset, otherwise halt
- *
- * This calls reset_walk(). If it returns, indicating that reset is not
- * supported, it prints a message and halts.
- */
-void reset_walk_halt(enum reset_t type);
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr);
-
-#endif
diff --git a/include/serial.h b/include/serial.h
index e490f9a..47332c5 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -40,6 +40,10 @@
extern struct serial_device eserial1_device;
extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+extern struct serial_device eserial5_device;
+extern struct serial_device eserial6_device;
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
diff --git a/include/spl.h b/include/spl.h
index 335b76a..0ae1605 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -35,16 +35,28 @@
* @dev: Pointer to the device, e.g. struct mmc *
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
+ * @filename: Name of the fit image file.
* @read: Function to call to read from the device
*/
struct spl_load_info {
void *dev;
void *priv;
int bl_len;
+ const char *filename;
ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
void *buf);
};
+/**
+ * spl_load_simple_fit() - Loads a fit image from a device.
+ * @info: Structure containing the information required to load data.
+ * @sector: Sector number where FIT image is located in the device
+ * @fdt: Pointer to the copied FIT header.
+ *
+ * Reads the FIT image @sector in the device. Loads u-boot image to
+ * specified load address and copies the dtb to end of u-boot image.
+ * Returns 0 on success.
+ */
int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
diff --git a/include/sysreset.h b/include/sysreset.h
new file mode 100644
index 0000000..393c7be
--- /dev/null
+++ b/include/sysreset.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SYSRESET_H
+#define __SYSRESET_H
+
+enum sysreset_t {
+ SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
+ SYSRESET_COLD, /* Reset CPU and GPIOs */
+ SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
+
+ SYSRESET_COUNT,
+};
+
+struct sysreset_ops {
+ /**
+ * request() - request a sysreset of the given type
+ *
+ * Note that this function may return before the reset takes effect.
+ *
+ * @type: Reset type to request
+ * @return -EINPROGRESS if the reset has been started and
+ * will complete soon, -EPROTONOSUPPORT if not supported
+ * by this device, 0 if the reset has already happened
+ * (in which case this method will not actually return)
+ */
+ int (*request)(struct udevice *dev, enum sysreset_t type);
+};
+
+#define sysreset_get_ops(dev) ((struct sysreset_ops *)(dev)->driver->ops)
+
+/**
+ * sysreset_request() - request a sysreset
+ *
+ * @type: Reset type to request
+ * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ */
+int sysreset_request(struct udevice *dev, enum sysreset_t type);
+
+/**
+ * sysreset_walk() - cause a system reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If this function fails to reset, it will display a message and halt
+ *
+ * @type: Reset type to request
+ * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ */
+int sysreset_walk(enum sysreset_t type);
+
+/**
+ * sysreset_walk_halt() - try to reset, otherwise halt
+ *
+ * This calls sysreset_walk(). If it returns, indicating that reset is not
+ * supported, it prints a message and halts.
+ */
+void sysreset_walk_halt(enum sysreset_t type);
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr);
+
+#endif
diff --git a/include/watchdog.h b/include/watchdog.h
index 9273fa1..174c894 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -21,8 +21,7 @@
int init_func_watchdog_reset(void);
#endif
-#if defined(CONFIG_SYS_GENERIC_BOARD) && \
- (defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG))
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
#else
diff --git a/lib/Kconfig b/lib/Kconfig
index 2b97c2b..02ca405 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -14,6 +14,7 @@
config USE_PRIVATE_LIBGCC
bool "Use private libgcc"
depends on HAVE_PRIVATE_LIBGCC
+ default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
help
This option allows you to use the built-in libgcc implementation
of U-Boot instead of the one provided by the compiler.
diff --git a/lib/Makefile b/lib/Makefile
index 02dfa29..f77befe 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -42,7 +42,6 @@
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
obj-$(CONFIG_SHA256) += sha256.o
-obj-y += strmhz.o
obj-$(CONFIG_TPM) += tpm.o
obj-$(CONFIG_RBTREE) += rbtree.o
obj-$(CONFIG_BITREVERSE) += bitrev.o
@@ -85,11 +84,11 @@
ifdef CONFIG_USE_TINY_PRINTF
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
endif
else
# Main U-Boot always uses the full printf support
-obj-y += vsprintf.o panic.o strto.o
+obj-y += vsprintf.o panic.o strto.o strmhz.o
endif
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 14c99ec..37a0dd6 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -7,3 +7,12 @@
on top of U-Boot. If this option is enabled, U-Boot will expose EFI
interfaces to a loaded EFI application, enabling it to reuse U-Boot's
device drivers.
+
+config EFI_LOADER_BOUNCE_BUFFER
+ bool "EFI Applications use bounce buffers for DMA operations"
+ depends on EFI_LOADER && ARM64
+ default n
+ help
+ Some hardware does not support DMA to full 64bit addresses. For this
+ hardware we can create a bounce buffer so that payloads don't have to
+ worry about platform details.
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 83e31f6..2a3849e 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -11,3 +11,4 @@
obj-y += efi_memory.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
+obj-$(CONFIG_NET) += efi_net.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 9daca50..be6f5e8 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -6,8 +6,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-/* #define DEBUG_EFI */
-
#include <common.h>
#include <efi_loader.h>
#include <malloc.h>
@@ -76,9 +74,7 @@
static efi_status_t efi_unsupported(const char *funcname)
{
-#ifdef DEBUG_EFI
- printf("EFI: App called into unimplemented function %s\n", funcname);
-#endif
+ debug("EFI: App called into unimplemented function %s\n", funcname);
return EFI_EXIT(EFI_UNSUPPORTED);
}
@@ -458,19 +454,30 @@
efi_is_direct_boot = false;
/* call the image! */
+ if (setjmp(&info->exit_jmp)) {
+ /* We returned from the child image */
+ return EFI_EXIT(info->exit_status);
+ }
+
entry(image_handle, &systab);
/* Should usually never get here */
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t EFIAPI efi_exit(void *image_handle, long exit_status,
- unsigned long exit_data_size,
- uint16_t *exit_data)
+static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
+ efi_status_t exit_status, unsigned long exit_data_size,
+ int16_t *exit_data)
{
+ struct efi_loaded_image *loaded_image_info = (void*)image_handle;
+
EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
exit_data_size, exit_data);
- return EFI_EXIT(efi_unsupported(__func__));
+
+ loaded_image_info->exit_status = exit_status;
+ longjmp(&loaded_image_info->exit_jmp);
+
+ panic("EFI application exited");
}
static struct efi_object *efi_search_obj(void *handle)
@@ -746,7 +753,7 @@
.install_configuration_table = efi_install_configuration_table,
.load_image = efi_load_image,
.start_image = efi_start_image,
- .exit = (void*)efi_exit,
+ .exit = efi_exit,
.unload_image = efi_unload_image,
.exit_boot_services = efi_exit_boot_services,
.get_next_monotonic_count = efi_get_next_monotonic_count,
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 075fd34..c434c92 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <blk.h>
+#include <dm.h>
#include <efi_loader.h>
#include <inttypes.h>
#include <part.h>
@@ -76,9 +77,6 @@
int blocks;
unsigned long n;
- EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
- buffer_size, buffer);
-
diskobj = container_of(this, struct efi_disk_obj, ops);
if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index)))
return EFI_EXIT(EFI_DEVICE_ERROR);
@@ -86,26 +84,23 @@
blocks = buffer_size / blksz;
lba += diskobj->offset;
-#ifdef DEBUG_EFI
- printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
- __LINE__, blocks, lba, blksz, direction);
-#endif
+ debug("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
+ __LINE__, blocks, lba, blksz, direction);
/* We only support full block access */
if (buffer_size & (blksz - 1))
return EFI_EXIT(EFI_DEVICE_ERROR);
if (direction == EFI_DISK_READ)
- n = desc->block_read(desc, lba, blocks, buffer);
+ n = blk_dread(desc, lba, blocks, buffer);
else
- n = desc->block_write(desc, lba, blocks, buffer);
+ n = blk_dwrite(desc, lba, blocks, buffer);
/* We don't do interrupts, so check for timers cooperatively */
efi_timer_check();
-#ifdef DEBUG_EFI
- printf("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
-#endif
+ debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
+
if (n != blocks)
return EFI_EXIT(EFI_DEVICE_ERROR);
@@ -116,16 +111,70 @@
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
- return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
- EFI_DISK_READ);
+ void *real_buffer = buffer;
+ efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+ r = efi_disk_read_blocks(this, media_id, lba,
+ EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+ if (r != EFI_SUCCESS)
+ return r;
+ return efi_disk_read_blocks(this, media_id, lba +
+ EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+ buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+ buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+ }
+
+ real_buffer = efi_bounce_buffer;
+#endif
+
+ EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ buffer_size, buffer);
+
+ r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+ EFI_DISK_READ);
+
+ /* Copy from bounce buffer to real buffer if necessary */
+ if ((r == EFI_SUCCESS) && (real_buffer != buffer))
+ memcpy(buffer, real_buffer, buffer_size);
+
+ return EFI_EXIT(r);
}
static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
- return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
- EFI_DISK_WRITE);
+ void *real_buffer = buffer;
+ efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+ r = efi_disk_write_blocks(this, media_id, lba,
+ EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+ if (r != EFI_SUCCESS)
+ return r;
+ return efi_disk_write_blocks(this, media_id, lba +
+ EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+ buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+ buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+ }
+
+ real_buffer = efi_bounce_buffer;
+#endif
+
+ EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+ buffer_size, buffer);
+
+ /* Populate bounce buffer if necessary */
+ if (real_buffer != buffer)
+ memcpy(real_buffer, buffer, buffer_size);
+
+ r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+ EFI_DISK_WRITE);
+
+ return EFI_EXIT(r);
}
static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
@@ -142,8 +191,8 @@
.flush_blocks = &efi_disk_flush_blocks,
};
-static void efi_disk_add_dev(char *name,
- const struct blk_driver *cur_drvr,
+static void efi_disk_add_dev(const char *name,
+ const char *if_typename,
const struct blk_desc *desc,
int dev_index,
lbaint_t offset)
@@ -161,7 +210,7 @@
diskobj->parent.protocols[1].open = efi_disk_open_dp;
diskobj->parent.handle = diskobj;
diskobj->ops = block_io_disk_template;
- diskobj->ifname = cur_drvr->if_typename;
+ diskobj->ifname = if_typename;
diskobj->dev_index = dev_index;
diskobj->offset = offset;
@@ -190,7 +239,7 @@
}
static int efi_disk_create_eltorito(struct blk_desc *desc,
- const struct blk_driver *cur_drvr,
+ const char *if_typename,
int diskid)
{
int disks = 0;
@@ -203,9 +252,10 @@
return 0;
while (!part_get_info(desc, part, &info)) {
- snprintf(devname, sizeof(devname), "%s%d:%d",
- cur_drvr->if_typename, diskid, part);
- efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+ snprintf(devname, sizeof(devname), "%s%d:%d", if_typename,
+ diskid, part);
+ efi_disk_add_dev(devname, if_typename, desc, diskid,
+ info.start);
part++;
disks++;
}
@@ -219,21 +269,49 @@
* EFI payload, we scan through all of the potentially available ones and
* store them in our object pool.
*
+ * TODO(sjg@chromium.org): Actually with CONFIG_BLK, U-Boot does have this.
+ * Consider converting the code to look up devices as needed. The EFI device
+ * could be a child of the UCLASS_BLK block device, perhaps.
+ *
* This gets called from do_bootefi_exec().
*/
int efi_disk_register(void)
{
- const struct blk_driver *cur_drvr;
- int i, if_type;
int disks = 0;
+#ifdef CONFIG_BLK
+ struct udevice *dev;
+
+ for (uclass_first_device(UCLASS_BLK, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ const char *if_typename = dev->driver->name;
+
+ printf("Scanning disk %s...\n", dev->name);
+ efi_disk_add_dev(dev->name, if_typename, desc, desc->devnum, 0);
+ disks++;
+
+ /*
+ * El Torito images show up as block devices in an EFI world,
+ * so let's create them here
+ */
+ disks += efi_disk_create_eltorito(desc, if_typename,
+ desc->devnum);
+ }
+#else
+ int i, if_type;
/* Search for all available disk devices */
for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+ const struct blk_driver *cur_drvr;
+ const char *if_typename;
+
cur_drvr = blk_driver_lookup_type(if_type);
if (!cur_drvr)
continue;
- printf("Scanning disks on %s...\n", cur_drvr->if_typename);
+ if_typename = cur_drvr->if_typename;
+ printf("Scanning disks on %s...\n", if_typename);
for (i = 0; i < 4; i++) {
struct blk_desc *desc;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
@@ -245,17 +323,18 @@
continue;
snprintf(devname, sizeof(devname), "%s%d",
- cur_drvr->if_typename, i);
- efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
+ if_typename, i);
+ efi_disk_add_dev(devname, if_typename, desc, i, 0);
disks++;
/*
* El Torito images show up as block devices
* in an EFI world, so let's create them here
*/
- disks += efi_disk_create_eltorito(desc, cur_drvr, i);
+ disks += efi_disk_create_eltorito(desc, if_typename, i);
}
}
+#endif
printf("Found %d disks\n", disks);
return 0;
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index bdd62bc..33a3d71 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -7,10 +7,12 @@
*/
#include <common.h>
+#include <dm.h>
#include <efi_loader.h>
#include <inttypes.h>
#include <lcd.h>
#include <malloc.h>
+#include <video.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -24,6 +26,8 @@
/* The only mode we support */
struct efi_gop_mode_info info;
struct efi_gop_mode mode;
+ /* Fields we only have acces to during init */
+ u32 bpix;
};
static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
@@ -57,6 +61,7 @@
unsigned long dy, unsigned long width,
unsigned long height, unsigned long delta)
{
+ struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
int i, j, line_len16, line_len32;
void *fb;
@@ -67,13 +72,17 @@
return EFI_EXIT(EFI_INVALID_PARAMETER);
fb = (void*)gd->fb_base;
- line_len16 = panel_info.vl_col * sizeof(u16);
- line_len32 = panel_info.vl_col * sizeof(u32);
+ line_len16 = gopobj->info.width * sizeof(u16);
+ line_len32 = gopobj->info.width * sizeof(u32);
/* Copy the contents line by line */
- switch (panel_info.vl_bpix) {
+ switch (gopobj->bpix) {
+#ifdef CONFIG_DM_VIDEO
+ case VIDEO_BPP32:
+#else
case LCD_COLOR32:
+#endif
for (i = 0; i < height; i++) {
u32 *dest = fb + ((i + dy) * line_len32) +
(dx * sizeof(u32));
@@ -84,7 +93,11 @@
memcpy(dest, src, width * sizeof(u32));
}
break;
+#ifdef CONFIG_DM_VIDEO
+ case VIDEO_BPP16:
+#else
case LCD_COLOR16:
+#endif
for (i = 0; i < height; i++) {
u16 *dest = fb + ((i + dy) * line_len16) +
(dx * sizeof(u16));
@@ -102,7 +115,11 @@
break;
}
+#ifdef CONFIG_DM_VIDEO
+ video_sync_all();
+#else
lcd_sync();
+#endif
return EFI_EXIT(EFI_SUCCESS);
}
@@ -111,11 +128,34 @@
int efi_gop_register(void)
{
struct efi_gop_obj *gopobj;
- int line_len;
+ u32 bpix, col, row;
- switch (panel_info.vl_bpix) {
+#ifdef CONFIG_DM_VIDEO
+ struct udevice *vdev;
+
+ /* We only support a single video output device for now */
+ if (uclass_first_device(UCLASS_VIDEO, &vdev))
+ return -1;
+
+ struct video_priv *priv = dev_get_uclass_priv(vdev);
+ bpix = priv->bpix;
+ col = video_get_xsize(vdev);
+ row = video_get_ysize(vdev);
+#else
+
+ bpix = panel_info.vl_bpix;
+ col = panel_info.vl_col;
+ row = panel_info.vl_row;
+#endif
+
+ switch (bpix) {
+#ifdef CONFIG_DM_VIDEO
+ case VIDEO_BPP16:
+ case VIDEO_BPP32:
+#else
case LCD_COLOR32:
case LCD_COLOR16:
+#endif
break;
default:
/* So far, we only work in 16 or 32 bit mode */
@@ -136,14 +176,14 @@
gopobj->mode.max_mode = 1;
gopobj->mode.info = &gopobj->info;
gopobj->mode.info_size = sizeof(gopobj->info);
- gopobj->mode.fb_base = gd->fb_base;
- gopobj->mode.fb_size = lcd_get_size(&line_len);
gopobj->info.version = 0;
- gopobj->info.width = panel_info.vl_col;
- gopobj->info.height = panel_info.vl_row;
+ gopobj->info.width = col;
+ gopobj->info.height = row;
gopobj->info.pixel_format = EFI_GOT_RGBA8;
- gopobj->info.pixels_per_scanline = panel_info.vl_col;
+ gopobj->info.pixels_per_scanline = col;
+
+ gopobj->bpix = bpix;
/* Hook up to the device list */
list_add_tail(&gopobj->parent.link, &efi_obj_list);
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 71a3d19..df2381e 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -6,8 +6,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-/* #define DEBUG_EFI */
-
#include <common.h>
#include <efi_loader.h>
#include <malloc.h>
@@ -24,9 +22,17 @@
struct efi_mem_desc desc;
};
+#define EFI_CARVE_NO_OVERLAP -1
+#define EFI_CARVE_LOOP_AGAIN -2
+#define EFI_CARVE_OVERLAPS_NONRAM -3
+
/* This list contains all memory map items */
LIST_HEAD(efi_mem);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+void *efi_bounce_buffer;
+#endif
+
/*
* Sorts the memory list from highest address to lowest address
*
@@ -74,11 +80,11 @@
/* check whether we're overlapping */
if ((carve_end <= map_start) || (carve_start >= map_end))
- return 0;
+ return EFI_CARVE_NO_OVERLAP;
/* We're overlapping with non-RAM, warn the caller if desired */
if (overlap_only_ram && (map_desc->type != EFI_CONVENTIONAL_MEMORY))
- return -1;
+ return EFI_CARVE_OVERLAPS_NONRAM;
/* Sanitize carve_start and carve_end to lie within our bounds */
carve_start = max(carve_start, map_start);
@@ -93,7 +99,7 @@
map_desc->physical_start = carve_end;
map_desc->num_pages = (map_end - carve_end) >> EFI_PAGE_SHIFT;
- return 1;
+ return (carve_end - carve_start) >> EFI_PAGE_SHIFT;
}
/*
@@ -113,7 +119,7 @@
/* Shrink the map to [ map_start ... carve_start ] */
map_desc->num_pages = (carve_start - map_start) >> EFI_PAGE_SHIFT;
- return 1;
+ return EFI_CARVE_LOOP_AGAIN;
}
uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
@@ -121,7 +127,8 @@
{
struct list_head *lhandle;
struct efi_mem_list *newlist;
- bool do_carving;
+ bool carve_again;
+ uint64_t carved_pages = 0;
if (!pages)
return start;
@@ -148,7 +155,7 @@
/* Add our new map */
do {
- do_carving = false;
+ carve_again = false;
list_for_each(lhandle, &efi_mem) {
struct efi_mem_list *lmem;
int r;
@@ -156,14 +163,44 @@
lmem = list_entry(lhandle, struct efi_mem_list, link);
r = efi_mem_carve_out(lmem, &newlist->desc,
overlap_only_ram);
- if (r < 0) {
+ switch (r) {
+ case EFI_CARVE_OVERLAPS_NONRAM:
+ /*
+ * The user requested to only have RAM overlaps,
+ * but we hit a non-RAM region. Error out.
+ */
return 0;
- } else if (r) {
- do_carving = true;
+ case EFI_CARVE_NO_OVERLAP:
+ /* Just ignore this list entry */
+ break;
+ case EFI_CARVE_LOOP_AGAIN:
+ /*
+ * We split an entry, but need to loop through
+ * the list again to actually carve it.
+ */
+ carve_again = true;
+ break;
+ default:
+ /* We carved a number of pages */
+ carved_pages += r;
+ carve_again = true;
+ break;
+ }
+
+ if (carve_again) {
+ /* The list changed, we need to start over */
break;
}
}
- } while (do_carving);
+ } while (carve_again);
+
+ if (overlap_only_ram && (carved_pages != pages)) {
+ /*
+ * The payload wanted to have RAM overlaps, but we overlapped
+ * with an unallocated region. Error out.
+ */
+ return 0;
+ }
/* Add our new map */
list_add_tail(&newlist->link, &efi_mem);
@@ -349,5 +386,17 @@
efi_add_memory_map(runtime_start, runtime_pages,
EFI_RUNTIME_SERVICES_CODE, false);
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ /* Request a 32bit 64MB bounce buffer region */
+ uint64_t efi_bounce_buffer_addr = 0xffffffff;
+
+ if (efi_allocate_pages(1, EFI_LOADER_DATA,
+ (64 * 1024 * 1024) >> EFI_PAGE_SHIFT,
+ &efi_bounce_buffer_addr) != EFI_SUCCESS)
+ return -1;
+
+ efi_bounce_buffer = (void*)(uintptr_t)efi_bounce_buffer_addr;
+#endif
+
return 0;
}
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
new file mode 100644
index 0000000..dd3b485
--- /dev/null
+++ b/lib/efi_loader/efi_net.c
@@ -0,0 +1,291 @@
+/*
+ * EFI application network access support
+ *
+ * Copyright (c) 2016 Alexander Graf
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <lcd.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
+static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
+static struct efi_pxe_packet *dhcp_ack;
+static bool new_rx_packet;
+static void *new_tx_packet;
+
+struct efi_net_obj {
+ /* Generic EFI object parent class data */
+ struct efi_object parent;
+ /* EFI Interface callback struct for network */
+ struct efi_simple_network net;
+ struct efi_simple_network_mode net_mode;
+ /* Device path to the network adapter */
+ struct efi_device_path_file_path dp[2];
+ /* PXE struct to transmit dhcp data */
+ struct efi_pxe pxe;
+ struct efi_pxe_mode pxe_mode;
+};
+
+static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
+ ulong extra_rx, ulong extra_tx)
+{
+ EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
+
+ eth_init();
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
+ int extended_verification)
+{
+ EFI_ENTRY("%p, %x", this, extended_verification);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
+{
+ EFI_ENTRY("%p", this);
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_receive_filters(
+ struct efi_simple_network *this, u32 enable, u32 disable,
+ int reset_mcast_filter, ulong mcast_filter_count,
+ struct efi_mac_address *mcast_filter)
+{
+ EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable,
+ reset_mcast_filter, mcast_filter_count, mcast_filter);
+
+ /* XXX Do we care? */
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_station_address(
+ struct efi_simple_network *this, int reset,
+ struct efi_mac_address *new_mac)
+{
+ EFI_ENTRY("%p, %x, %p", this, reset, new_mac);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this,
+ int reset, ulong *stat_size,
+ void *stat_table)
+{
+ EFI_ENTRY("%p, %x, %p, %p", this, reset, stat_size, stat_table);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this,
+ int ipv6,
+ struct efi_ip_address *ip,
+ struct efi_mac_address *mac)
+{
+ EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this,
+ int read_write, ulong offset,
+ ulong buffer_size, char *buffer)
+{
+ EFI_ENTRY("%p, %x, %lx, %lx, %p", this, read_write, offset, buffer_size,
+ buffer);
+
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
+ u32 *int_status, void **txbuf)
+{
+ EFI_ENTRY("%p, %p, %p", this, int_status, txbuf);
+
+ /* We send packets synchronously, so nothing is outstanding */
+ if (int_status)
+ *int_status = 0;
+ if (txbuf)
+ *txbuf = new_tx_packet;
+
+ new_tx_packet = NULL;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this,
+ ulong header_size, ulong buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol)
+{
+ EFI_ENTRY("%p, %lx, %lx, %p, %p, %p, %p", this, header_size,
+ buffer_size, buffer, src_addr, dest_addr, protocol);
+
+ if (header_size) {
+ /* We would need to create the header if header_size != 0 */
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ }
+
+ net_send_packet(buffer, buffer_size);
+ new_tx_packet = buffer;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_net_push(void *pkt, int len)
+{
+ new_rx_packet = true;
+}
+
+static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this,
+ ulong *header_size, ulong *buffer_size, void *buffer,
+ struct efi_mac_address *src_addr,
+ struct efi_mac_address *dest_addr, u16 *protocol)
+{
+ EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size,
+ buffer_size, buffer, src_addr, dest_addr, protocol);
+
+ push_packet = efi_net_push;
+ eth_rx();
+ push_packet = NULL;
+
+ if (!new_rx_packet)
+ return EFI_EXIT(EFI_NOT_READY);
+
+ if (*buffer_size < net_rx_packet_len) {
+ /* Packet doesn't fit, try again with bigger buf */
+ *buffer_size = net_rx_packet_len;
+ return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ }
+
+ memcpy(buffer, net_rx_packet, net_rx_packet_len);
+ *buffer_size = net_rx_packet_len;
+ new_rx_packet = false;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_simple_network *net = handle;
+ struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+ *protocol_interface = netobj->dp;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol,
+ void **protocol_interface, void *agent_handle,
+ void *controller_handle, uint32_t attributes)
+{
+ struct efi_simple_network *net = handle;
+ struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+ *protocol_interface = &netobj->pxe;
+
+ return EFI_SUCCESS;
+}
+
+void efi_net_set_dhcp_ack(void *pkt, int len)
+{
+ int maxsize = sizeof(*dhcp_ack);
+
+ if (!dhcp_ack)
+ dhcp_ack = malloc(maxsize);
+
+ memcpy(dhcp_ack, pkt, min(len, maxsize));
+}
+
+/* This gets called from do_bootefi_exec(). */
+int efi_net_register(void **handle)
+{
+ struct efi_net_obj *netobj;
+ struct efi_device_path_file_path dp_net = {
+ .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ .dp.length = sizeof(dp_net),
+ .str = { 'N', 'e', 't' },
+ };
+ struct efi_device_path_file_path dp_end = {
+ .dp.type = DEVICE_PATH_TYPE_END,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+ .dp.length = sizeof(dp_end),
+ };
+
+ if (!eth_get_dev()) {
+ /* No eth device active, don't expose any */
+ return 0;
+ }
+
+ /* We only expose the "active" eth device, so one is enough */
+ netobj = calloc(1, sizeof(*netobj));
+
+ /* Fill in object data */
+ netobj->parent.protocols[0].guid = &efi_net_guid;
+ netobj->parent.protocols[0].open = efi_return_handle;
+ netobj->parent.protocols[1].guid = &efi_guid_device_path;
+ netobj->parent.protocols[1].open = efi_net_open_dp;
+ netobj->parent.protocols[2].guid = &efi_pxe_guid;
+ netobj->parent.protocols[2].open = efi_net_open_pxe;
+ netobj->parent.handle = &netobj->net;
+ netobj->net.start = efi_net_start;
+ netobj->net.stop = efi_net_stop;
+ netobj->net.initialize = efi_net_initialize;
+ netobj->net.reset = efi_net_reset;
+ netobj->net.shutdown = efi_net_shutdown;
+ netobj->net.receive_filters = efi_net_receive_filters;
+ netobj->net.station_address = efi_net_station_address;
+ netobj->net.statistics = efi_net_statistics;
+ netobj->net.mcastiptomac = efi_net_mcastiptomac;
+ netobj->net.nvdata = efi_net_nvdata;
+ netobj->net.get_status = efi_net_get_status;
+ netobj->net.transmit = efi_net_transmit;
+ netobj->net.receive = efi_net_receive;
+ netobj->net.mode = &netobj->net_mode;
+ netobj->net_mode.state = EFI_NETWORK_STARTED;
+ netobj->dp[0] = dp_net;
+ netobj->dp[1] = dp_end;
+ memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
+ netobj->net_mode.max_packet_size = PKTSIZE;
+
+ netobj->pxe.mode = &netobj->pxe_mode;
+ if (dhcp_ack)
+ netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+
+ /* Hook net up to the device list */
+ list_add_tail(&netobj->parent.link, &efi_obj_list);
+
+ if (handle)
+ *handle = &netobj->net;
+
+ return 0;
+}
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 3ee27ca..99b5ef1 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -125,6 +125,22 @@
/* RTC accessors are gone */
.ptr = &efi_runtime_services.get_time,
.patchto = &efi_device_error,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.con_in,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.con_out,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.std_err,
+ .patchto = NULL,
+ }, {
+ /* Clean up system table */
+ .ptr = &systab.boottime,
+ .patchto = NULL,
},
};
@@ -149,9 +165,7 @@
ulong *p = efi_runtime_detach_list[i].ptr;
ulong newaddr = patchto ? (patchto + patchoff) : 0;
-#ifdef DEBUG_EFI
- printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
+ debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
*p = newaddr;
}
}
@@ -166,10 +180,7 @@
static ulong lastoff = CONFIG_SYS_TEXT_BASE;
#endif
-#ifdef DEBUG_EFI
- printf("%s: Relocating to offset=%lx\n", __func__, offset);
-#endif
-
+ debug("%s: Relocating to offset=%lx\n", __func__, offset);
for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) {
ulong base = CONFIG_SYS_TEXT_BASE;
ulong *p;
@@ -196,10 +207,7 @@
continue;
}
-#ifdef DEBUG_EFI
- printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
-
+ debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
*p = newaddr;
flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1),
ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE));
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 70acc29..ab002e9 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -30,6 +30,7 @@
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
diff --git a/lib/string.c b/lib/string.c
index 87c9a40..67d5f6a 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -461,30 +461,6 @@
}
#endif
-#ifndef __HAVE_ARCH_BCOPY
-/**
- * bcopy - Copy one area of memory to another
- * @src: Where to copy from
- * @dest: Where to copy to
- * @count: The size of the area.
- *
- * Note that this is the same as memcpy(), with the arguments reversed.
- * memcpy() is the standard, bcopy() is a legacy BSD function.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-char * bcopy(const char * src, char * dest, int count)
-{
- char *tmp = dest;
-
- while (count--)
- *tmp++ = *src++;
-
- return dest;
-}
-#endif
-
#ifndef __HAVE_ARCH_MEMCPY
/**
* memcpy - Copy one area of memory to another
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index a06abed..5ea2555 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -16,6 +16,9 @@
static char *bf;
static char zs;
+/* Current position in sprintf() output string */
+static char *outstr;
+
static void out(char c)
{
*bf++ = c;
@@ -40,7 +43,7 @@
out_dgt(dgt);
}
-int vprintf(const char *fmt, va_list va)
+int _vprintf(const char *fmt, va_list va, void (*putc)(const char ch))
{
char ch;
char *p;
@@ -52,8 +55,8 @@
if (ch != '%') {
putc(ch);
} else {
- char lz = 0;
- char w = 0;
+ bool lz = false;
+ int width = 0;
ch = *(fmt++);
if (ch == '0') {
@@ -62,9 +65,9 @@
}
if (ch >= '0' && ch <= '9') {
- w = 0;
+ width = 0;
while (ch >= '0' && ch <= '9') {
- w = (w * 10) + ch - '0';
+ width = (width * 10) + ch - '0';
ch = *fmt++;
}
}
@@ -73,7 +76,7 @@
zs = 0;
switch (ch) {
- case 0:
+ case '\0':
goto abort;
case 'u':
case 'd':
@@ -112,9 +115,9 @@
*bf = 0;
bf = p;
- while (*bf++ && w > 0)
- w--;
- while (w-- > 0)
+ while (*bf++ && width > 0)
+ width--;
+ while (width-- > 0)
putc(lz ? '0' : ' ');
if (p) {
while ((ch = *p++))
@@ -133,7 +136,39 @@
int ret;
va_start(va, fmt);
+ ret = _vprintf(fmt, va, putc);
+ va_end(va);
+
+ return ret;
+}
+
+static void putc_outstr(char ch)
+{
+ *outstr++ = ch;
+}
+
+int sprintf(char *buf, const char *fmt, ...)
+{
+ va_list va;
+ int ret;
+
+ va_start(va, fmt);
+ outstr = buf;
+ ret = _vprintf(fmt, va, putc_outstr);
+ va_end(va);
+ *outstr = '\0';
+
+ return ret;
+}
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+ va_list va;
+ int ret;
+
+ va_start(va, fmt);
- ret = vprintf(fmt, va);
+ ret = sprintf(buf, fmt, va);
va_end(va);
return ret;
diff --git a/net/Kconfig b/net/Kconfig
index a44a783..c393269 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -32,4 +32,20 @@
If unset, timeout and maximum are hard-defined as 1 second
and 10 timouts per TFTP transfer.
+config BOOTP_PXE_CLIENTARCH
+ hex
+ default 0x16 if ARM64
+ default 0x15 if ARM
+ default 0 if X86
+
+config BOOTP_VCI_STRING
+ string
+ default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+ default "U-Boot.armv8" if ARM64
+ default "U-Boot.arm" if ARM
+ default "U-Boot"
+
+config SPL_NET_VCI_STRING
+ string
+
endif # if NET
diff --git a/net/bootp.c b/net/bootp.c
index d7852db..aa6cdf0 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <command.h>
+#include <efi_loader.h>
#include <net.h>
#include <net/tftp.h>
#include "bootp.h"
@@ -410,6 +411,26 @@
e += vci_strlen; \
} while (0)
+static u8 *add_vci(u8 *e)
+{
+ char *vci = NULL;
+ char *env_vci = getenv("bootp_vci");
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
+ vci = CONFIG_SPL_NET_VCI_STRING;
+#elif defined(CONFIG_BOOTP_VCI_STRING)
+ vci = CONFIG_BOOTP_VCI_STRING;
+#endif
+
+ if (env_vci)
+ vci = env_vci;
+
+ if (vci)
+ put_vci(e, vci);
+
+ return e;
+}
+
/*
* Initialize BOOTP extension fields in the request.
*/
@@ -419,10 +440,10 @@
{
u8 *start = e;
u8 *cnt;
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_LIB_UUID
char *uuid;
- u16 clientarch;
#endif
+ int clientarch = -1;
#if defined(CONFIG_BOOTP_VENDOREX)
u8 *x;
@@ -478,12 +499,19 @@
}
#endif
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_BOOTP_PXE_CLIENTARCH
clientarch = CONFIG_BOOTP_PXE_CLIENTARCH;
- *e++ = 93; /* Client System Architecture */
- *e++ = 2;
- *e++ = (clientarch >> 8) & 0xff;
- *e++ = clientarch & 0xff;
+#endif
+
+ if (getenv("bootp_arch"))
+ clientarch = getenv_ulong("bootp_arch", 16, clientarch);
+
+ if (clientarch > 0) {
+ *e++ = 93; /* Client System Architecture */
+ *e++ = 2;
+ *e++ = (clientarch >> 8) & 0xff;
+ *e++ = clientarch & 0xff;
+ }
*e++ = 94; /* Client Network Interface Identifier */
*e++ = 3;
@@ -491,6 +519,7 @@
*e++ = 0; /* major revision */
*e++ = 0; /* minor revision */
+#ifdef CONFIG_LIB_UUID
uuid = getenv("pxeuuid");
if (uuid) {
@@ -507,11 +536,7 @@
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
- put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#elif defined(CONFIG_BOOTP_VCI_STRING)
- put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
+ e = add_vci(e);
#if defined(CONFIG_BOOTP_VENDOREX)
x = dhcp_vendorex_prep(e);
@@ -597,14 +622,7 @@
*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
#endif
-#if defined(CONFIG_BOOTP_VCI_STRING) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
-#ifdef CONFIG_SPL_BUILD
- put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#else
- put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
-#endif
+ add_vci(e);
#if defined(CONFIG_BOOTP_SUBNETMASK)
*e++ = 1; /* Subnet mask request */
@@ -1025,6 +1043,7 @@
strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
#endif /* CONFIG_SYS_BOOTFILE_PREFIX */
dhcp_packet_process_options(bp);
+ efi_net_set_dhcp_ack(pkt, len);
debug("TRANSITIONING TO REQUESTING STATE\n");
dhcp_state = REQUESTING;
diff --git a/net/net.c b/net/net.c
index fba111e..1e1d23d 100644
--- a/net/net.c
+++ b/net/net.c
@@ -146,7 +146,7 @@
/* Ethernet bcast address */
const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const u8 net_null_ethaddr[6];
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
void (*push_packet)(void *, int len) = 0;
#endif
/* Network loop state */
@@ -1054,7 +1054,7 @@
if (len < ETHER_HDR_SIZE)
return;
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
if (push_packet) {
(*push_packet)(in_packet, len);
return;
diff --git a/net/tftp.c b/net/tftp.c
index f2889fe..ced45ec 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
+#include <efi_loader.h>
#include <mapmem.h>
#include <net.h>
#include <net/tftp.h>
@@ -804,6 +805,7 @@
printf("Load address: 0x%lx\n", load_addr);
puts("Loading: *\b");
tftp_state = STATE_SEND_RRQ;
+ efi_set_bootdev("Net", "", tftp_filename);
}
time_start = get_timer(0);
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 97a09a2..e720562 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -325,7 +325,7 @@
# ---------------------------------------------------------------------------
quiet_cmd_acpi_c_asl= ASL $<
cmd_acpi_c_asl= \
- $(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+ $(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
mv $(patsubst %.asl,%.hex,$<) $@
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 6d2017d..0997fd9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -158,11 +158,8 @@
ALL-y += boot.bin
endif
-ifdef CONFIG_ARCH_ZYNQ
-ALL-y += $(obj)/boot.bin
-endif
-
-ALL-(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
all: $(ALL-y)
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 9a11ae0..9eaf04b 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,12 +21,13 @@
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_LED) += led.o
+obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
obj-$(CONFIG_DM_PCI) += pci.o
obj-$(CONFIG_RAM) += ram.o
obj-y += regmap.o
obj-$(CONFIG_REMOTEPROC) += remoteproc.o
-obj-$(CONFIG_RESET) += reset.o
+obj-$(CONFIG_SYSRESET) += sysreset.o
obj-$(CONFIG_DM_RTC) += rtc.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
obj-$(CONFIG_DM_SPI) += spi.o
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 727db18..b994523 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -75,6 +75,13 @@
ut_assertok(ops->set_value(dev, offset, 1));
ut_asserteq(1, ops->get_value(dev, offset));
+ /* Make it an open drain output, and reset it */
+ ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+ ut_assertok(ops->set_open_drain(dev, offset, 1));
+ ut_asserteq(1, sandbox_gpio_get_open_drain(dev, offset));
+ ut_assertok(ops->set_open_drain(dev, offset, 0));
+ ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+
/* Make it an input */
ut_assertok(ops->direction_input(dev, offset));
ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c
new file mode 100644
index 0000000..be7bd6d
--- /dev/null
+++ b/test/dm/mailbox.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/mbox.h>
+#include <test/ut.h>
+
+static int dm_test_mailbox(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ uint32_t msg;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "mbox-test", &dev));
+ ut_assertok(sandbox_mbox_test_get(dev));
+
+ ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+ ut_assertok(sandbox_mbox_test_send(dev, 0xaaff9955UL));
+ ut_assertok(sandbox_mbox_test_recv(dev, &msg));
+ ut_asserteq(msg, 0xaaff9955UL ^ SANDBOX_MBOX_PING_XOR);
+ ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+
+ ut_assertok(sandbox_mbox_test_free(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_mailbox, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/reset.c b/test/dm/reset.c
deleted file mode 100644
index 5d53f25..0000000
--- a/test/dm/reset.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-#include <dm/test.h>
-#include <test/ut.h>
-
-/* Test that we can use particular reset devices */
-static int dm_test_reset_base(struct unit_test_state *uts)
-{
- struct sandbox_state *state = state_get_current();
- struct udevice *dev;
-
- /* Device 0 is the platform data device - it should never respond */
- ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD));
- ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER));
-
- /* Device 1 is the warm reset device */
- ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev));
- ut_asserteq(-EACCES, reset_request(dev, RESET_WARM));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER));
-
- state->reset_allowed[RESET_WARM] = true;
- ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM));
- state->reset_allowed[RESET_WARM] = false;
-
- /* Device 2 is the cold reset device */
- ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev));
- ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM));
- ut_asserteq(-EACCES, reset_request(dev, RESET_COLD));
- state->reset_allowed[RESET_POWER] = false;
- ut_asserteq(-EACCES, reset_request(dev, RESET_POWER));
- state->reset_allowed[RESET_POWER] = true;
-
- return 0;
-}
-DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-
-/* Test that we can walk through the reset devices */
-static int dm_test_reset_walk(struct unit_test_state *uts)
-{
- struct sandbox_state *state = state_get_current();
-
- /* If we generate a power reset, we will exit sandbox! */
- state->reset_allowed[RESET_POWER] = false;
- ut_asserteq(-EACCES, reset_walk(RESET_WARM));
- ut_asserteq(-EACCES, reset_walk(RESET_COLD));
- ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-
- /*
- * Enable cold reset - this should make cold reset work, plus a warm
- * reset should be promoted to cold, since this is the next step
- * along.
- */
- state->reset_allowed[RESET_COLD] = true;
- ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM));
- ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD));
- ut_asserteq(-EACCES, reset_walk(RESET_POWER));
- state->reset_allowed[RESET_COLD] = false;
- state->reset_allowed[RESET_POWER] = true;
-
- return 0;
-}
-DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
new file mode 100644
index 0000000..5e94c07
--- /dev/null
+++ b/test/dm/sysreset.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that we can use particular sysreset devices */
+static int dm_test_sysreset_base(struct unit_test_state *uts)
+{
+ struct sandbox_state *state = state_get_current();
+ struct udevice *dev;
+
+ /* Device 0 is the platform data device - it should never respond */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER));
+
+ /* Device 1 is the warm sysreset device */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+
+ state->sysreset_allowed[SYSRESET_WARM] = true;
+ ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
+ state->sysreset_allowed[SYSRESET_WARM] = false;
+
+ /* Device 2 is the cold sysreset device */
+ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
+ ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
+ state->sysreset_allowed[SYSRESET_POWER] = false;
+ ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER));
+ state->sysreset_allowed[SYSRESET_POWER] = true;
+
+ return 0;
+}
+DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can walk through the sysreset devices */
+static int dm_test_sysreset_walk(struct unit_test_state *uts)
+{
+ struct sandbox_state *state = state_get_current();
+
+ /* If we generate a power sysreset, we will exit sandbox! */
+ state->sysreset_allowed[SYSRESET_POWER] = false;
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+
+ /*
+ * Enable cold system reset - this should make cold system reset work,
+ * plus a warm system reset should be promoted to cold, since this is
+ * the next step along.
+ */
+ state->sysreset_allowed[SYSRESET_COLD] = true;
+ ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM));
+ ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD));
+ ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+ state->sysreset_allowed[SYSRESET_COLD] = false;
+ state->sysreset_allowed[SYSRESET_POWER] = true;
+
+ return 0;
+}
+DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index f743436..815fa64 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -56,6 +56,22 @@
self.console.disable_check_count[self.check_type] -= 1
self.console.eval_bad_patterns()
+class ConsoleSetupTimeout(object):
+ """Context manager (for Python's with statement) that temporarily sets up
+ timeout for specific command. This is useful when execution time is greater
+ then default 30s."""
+
+ def __init__(self, console, timeout):
+ self.p = console.p
+ self.orig_timeout = self.p.timeout
+ self.p.timeout = timeout
+
+ def __enter__(self):
+ return self
+
+ def __exit__(self, extype, value, traceback):
+ self.p.timeout = self.orig_timeout
+
class ConsoleBase(object):
"""The interface through which test functions interact with the U-Boot
console. This primarily involves executing shell commands, capturing their
@@ -391,3 +407,18 @@
"""
return ConsoleDisableCheck(self, check_type)
+
+ def temporary_timeout(self, timeout):
+ """Temporarily set up different timeout for commands.
+
+ Create a new context manager (for use with the "with" statement) which
+ temporarily change timeout.
+
+ Args:
+ timeout: Time in milliseconds.
+
+ Returns:
+ A context manager object.
+ """
+
+ return ConsoleSetupTimeout(self, timeout)
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9d243e0..6a6b2ec 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -10,6 +10,7 @@
import pytest
import sys
import time
+import pytest
def md5sum_data(data):
"""Calculate the MD5 hash of some data.
diff --git a/tools/.gitignore b/tools/.gitignore
index ff07680..cb1e722 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -1,4 +1,5 @@
/atmel_pmecc_params
+/bin2header
/bmp_logo
/envcrc
/fdtgrep
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 06cf63d..692abda 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -35,9 +35,11 @@
#include "fw_env.h"
-struct common_args common_args;
-struct printenv_args printenv_args;
-struct setenv_args setenv_args;
+struct env_opts default_opts = {
+#ifdef CONFIG_FILE
+ .config_file = CONFIG_FILE
+#endif
+};
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
@@ -75,7 +77,8 @@
#define CUR_ENVSIZE ENVSIZE(dev_current)
-#define ENV_SIZE getenvsize()
+static unsigned long usable_envsize;
+#define ENV_SIZE usable_envsize
struct env_image_single {
uint32_t crc; /* CRC32 over data bytes */
@@ -106,7 +109,7 @@
.flag_scheme = FLAG_NONE,
};
-static int env_aes_cbc_crypt(char *data, const int enc);
+static int env_aes_cbc_crypt(char *data, const int enc, uint8_t *key);
static int HaveRedundEnv = 0;
@@ -119,23 +122,11 @@
static int flash_io (int mode);
static char *envmatch (char * s1, char * s2);
-static int parse_config (void);
+static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
static int get_config (char *);
#endif
-static inline ulong getenvsize (void)
-{
- ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
-
- if (HaveRedundEnv)
- rc -= sizeof (char);
-
- if (common_args.aes_flag)
- rc &= ~(AES_KEY_LENGTH - 1);
-
- return rc;
-}
static char *skip_chars(char *s)
{
@@ -239,12 +230,15 @@
* Print the current definition of one, or more, or all
* environment variables
*/
-int fw_printenv (int argc, char *argv[])
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
{
char *env, *nxt;
int i, rc = 0;
+ if (!opts)
+ opts = &default_opts;
+
- if (fw_env_open())
+ if (fw_env_open(opts))
return -1;
if (argc == 0) { /* Print all env variables */
@@ -262,7 +256,7 @@
return 0;
}
- if (printenv_args.name_suppress && argc != 1) {
+ if (value_only && argc != 1) {
fprintf(stderr,
"## Error: `-n' option requires exactly one argument\n");
return -1;
@@ -283,7 +277,7 @@
}
val = envmatch (name, env);
if (val) {
- if (!printenv_args.name_suppress) {
+ if (!value_only) {
fputs (name, stdout);
putc ('=', stdout);
}
@@ -300,11 +294,16 @@
return rc;
}
-int fw_env_close(void)
+int fw_env_close(struct env_opts *opts)
{
int ret;
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(environment.data, 1);
+
+ if (!opts)
+ opts = &default_opts;
+
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 1,
+ opts->aes_key);
if (ret) {
fprintf(stderr,
"Error: can't encrypt env for flash\n");
@@ -457,7 +456,7 @@
* modified or deleted
*
*/
-int fw_setenv(int argc, char *argv[])
+int fw_setenv(int argc, char *argv[], struct env_opts *opts)
{
int i;
size_t len;
@@ -465,13 +464,16 @@
char *value = NULL;
int valc;
+ if (!opts)
+ opts = &default_opts;
+
if (argc < 1) {
fprintf(stderr, "## Error: variable name missing\n");
errno = EINVAL;
return -1;
}
- if (fw_env_open()) {
+ if (fw_env_open(opts)) {
fprintf(stderr, "Error: environment not initialized\n");
return -1;
}
@@ -507,7 +509,7 @@
free(value);
- return fw_env_close();
+ return fw_env_close(opts);
}
/*
@@ -527,7 +529,7 @@
* 0 - OK
* -1 - Error
*/
-int fw_parse_script(char *fname)
+int fw_parse_script(char *fname, struct env_opts *opts)
{
FILE *fp;
char dump[1024]; /* Maximum line length in the file */
@@ -537,7 +539,10 @@
int len;
int ret = 0;
- if (fw_env_open()) {
+ if (!opts)
+ opts = &default_opts;
+
+ if (fw_env_open(opts)) {
fprintf(stderr, "Error: environment not initialized\n");
return -1;
}
@@ -625,10 +630,9 @@
if (strcmp(fname, "-") != 0)
fclose(fp);
- ret |= fw_env_close();
+ ret |= fw_env_close(opts);
return ret;
-
}
/*
@@ -949,15 +953,15 @@
}
/* Encrypt or decrypt the environment before writing or reading it. */
-static int env_aes_cbc_crypt(char *payload, const int enc)
+static int env_aes_cbc_crypt(char *payload, const int enc, uint8_t *key)
{
uint8_t *data = (uint8_t *)payload;
- const int len = getenvsize();
+ const int len = usable_envsize;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
/* First we expand the key. */
- aes_expand_key(common_args.aes_key, key_exp);
+ aes_expand_key(key, key_exp);
/* Calculate the number of AES blocks to encrypt. */
aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
@@ -1138,7 +1142,7 @@
/*
* Prevent confusion if running from erased flash memory
*/
-int fw_env_open(void)
+int fw_env_open(struct env_opts *opts)
{
int crc0, crc0_ok;
unsigned char flag0;
@@ -1153,7 +1157,10 @@
struct env_image_single *single;
struct env_image_redundant *redundant;
+ if (!opts)
+ opts = &default_opts;
+
- if (parse_config ()) /* should fill envdevices */
+ if (parse_config(opts)) /* should fill envdevices */
return -1;
addr0 = calloc(1, CUR_ENVSIZE);
@@ -1185,8 +1192,9 @@
crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(environment.data, 0);
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 0,
+ opts->aes_key);
if (ret)
return ret;
}
@@ -1242,8 +1250,9 @@
crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
- if (common_args.aes_flag) {
- ret = env_aes_cbc_crypt(redundant->data, 0);
+ if (opts->aes_flag) {
+ ret = env_aes_cbc_crypt(redundant->data, 0,
+ opts->aes_key);
if (ret)
return ret;
}
@@ -1320,18 +1329,18 @@
}
-static int parse_config ()
+static int parse_config(struct env_opts *opts)
{
struct stat st;
-#if defined(CONFIG_FILE)
- if (!common_args.config_file)
- common_args.config_file = CONFIG_FILE;
+ if (!opts)
+ opts = &default_opts;
+#if defined(CONFIG_FILE)
/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
- if (get_config(common_args.config_file)) {
+ if (get_config(opts->config_file)) {
fprintf(stderr, "Cannot parse config file '%s': %m\n",
- common_args.config_file);
+ opts->config_file);
return -1;
}
#else
@@ -1379,6 +1388,21 @@
DEVNAME (1), strerror (errno));
return -1;
}
+
+ if (HaveRedundEnv && ENVSIZE(0) != ENVSIZE(1)) {
+ ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
+ fprintf(stderr,
+ "Redundant environments have inequal size, set to 0x%08lx\n",
+ ENVSIZE(1));
+ }
+
+ usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
+ if (HaveRedundEnv)
+ usable_envsize -= sizeof(char);
+
+ if (opts->aes_flag)
+ usable_envsize &= ~(AES_KEY_LENGTH - 1);
+
return 0;
}
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 57149e7..dac964d 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -57,33 +57,22 @@
"bootm"
#endif
-struct common_args {
+struct env_opts {
#ifdef CONFIG_FILE
char *config_file;
#endif
- uint8_t aes_key[AES_KEY_LENGTH];
int aes_flag; /* Is AES encryption used? */
-};
-extern struct common_args common_args;
-
-struct printenv_args {
- int name_suppress;
-};
-extern struct printenv_args printenv_args;
-
-struct setenv_args {
- char *script_file;
+ uint8_t aes_key[AES_KEY_LENGTH];
};
-extern struct setenv_args setenv_args;
int parse_aes_key(char *key, uint8_t *bin_key);
-extern int fw_printenv(int argc, char *argv[]);
-extern char *fw_getenv (char *name);
-extern int fw_setenv (int argc, char *argv[]);
-extern int fw_parse_script(char *fname);
-extern int fw_env_open(void);
-extern int fw_env_write(char *name, char *value);
-extern int fw_env_close(void);
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
+char *fw_getenv(char *name);
+int fw_setenv(int argc, char *argv[], struct env_opts *opts);
+int fw_parse_script(char *fname, struct env_opts *opts);
+int fw_env_open(struct env_opts *opts);
+int fw_env_write(char *name, char *value);
+int fw_env_close(struct env_opts *opts);
-extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned);
+unsigned long crc32(unsigned long, const unsigned char *, unsigned);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 3706d8f..7a17b28 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -49,6 +49,14 @@
{NULL, 0, NULL, 0}
};
+static struct env_opts env_opts;
+
+/* setenv options */
+static int noheader;
+
+/* getenv options */
+static char *script_file;
+
void usage_printenv(void)
{
@@ -108,22 +116,22 @@
int c;
#ifdef CONFIG_FILE
- common_args.config_file = CONFIG_FILE;
+ env_opts.config_file = CONFIG_FILE;
#endif
while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) !=
EOF) {
switch (c) {
case 'a':
- if (parse_aes_key(optarg, common_args.aes_key)) {
+ if (parse_aes_key(optarg, env_opts.aes_key)) {
fprintf(stderr, "AES key parse error\n");
exit(EXIT_FAILURE);
}
- common_args.aes_flag = 1;
+ env_opts.aes_flag = 1;
break;
#ifdef CONFIG_FILE
case 'c':
- common_args.config_file = optarg;
+ env_opts.config_file = optarg;
break;
#endif
case 'h':
@@ -151,7 +159,7 @@
EOF) {
switch (c) {
case 'n':
- printenv_args.name_suppress = 1;
+ noheader = 1;
break;
case 'a':
case 'c':
@@ -177,7 +185,7 @@
EOF) {
switch (c) {
case 's':
- setenv_args.script_file = optarg;
+ script_file = optarg;
break;
case 'a':
case 'c':
@@ -240,14 +248,14 @@
}
if (do_printenv) {
- if (fw_printenv(argc, argv) != 0)
+ if (fw_printenv(argc, argv, noheader, &env_opts) != 0)
retval = EXIT_FAILURE;
} else {
- if (!setenv_args.script_file) {
- if (fw_setenv(argc, argv) != 0)
+ if (!script_file) {
+ if (fw_setenv(argc, argv, &env_opts) != 0)
retval = EXIT_FAILURE;
} else {
- if (fw_parse_script(setenv_args.script_file) != 0)
+ if (fw_parse_script(script_file, &env_opts) != 0)
retval = EXIT_FAILURE;
}
}
diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 23c956b..c2efad5 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -21,7 +21,6 @@
import multiprocessing
import optparse
import os
-import subprocess
import sys
import tempfile
import time
diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c
deleted file mode 100644
index 832d3fe..0000000
--- a/tools/palmtreo680/flash_u-boot.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- *
- * This is a userspace Linux utility that, when run on the Treo 680, will
- * program u-boot to flash. The docg4 driver *must* be loaded with the
- * reliable_mode and ignore_badblocks parameters enabled:
- *
- * modprobe docg4 ignore_badblocks=1 reliable_mode=1
- *
- * This utility writes the concatenated spl + u-boot image to the start of the
- * mtd device in the format expected by the IPL/SPL. The image file and mtd
- * device node are passed to the utility as arguments. The blocks must have
- * been erased beforehand.
- *
- * When you compile this, note that it links to libmtd from mtd-utils, so ensure
- * that your include and lib paths include this.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <errno.h>
-#include <mtd/mtd-user.h>
-#include "libmtd.h"
-
-#define RELIABLE_BLOCKSIZE 0x10000 /* block capacity in reliable mode */
-#define STANDARD_BLOCKSIZE 0x40000 /* block capacity in normal mode */
-#define PAGESIZE 512
-#define PAGES_PER_BLOCK 512
-#define OOBSIZE 7 /* available to user (16 total) */
-
-uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
-/* this is the magic number the IPL looks for (ASCII "BIPO") */
-uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff};
-
-int main(int argc, char * const argv[])
-{
- int devfd, datafd, num_blocks, block;
- off_t file_size;
- libmtd_t mtd_desc;
- struct mtd_dev_info devinfo;
- uint8_t *blockbuf;
- char response[8];
-
- if (argc != 3) {
- printf("usage: %s <image file> <mtd dev node>\n", argv[0]);
- return -EINVAL;
- }
-
- mtd_desc = libmtd_open();
- if (mtd_desc == NULL) {
- int errsv = errno;
- fprintf(stderr, "can't initialize libmtd\n");
- return -errsv;
- }
-
- /* open the spl image file and mtd device */
- datafd = open(argv[1], O_RDONLY);
- if (datafd == -1) {
- int errsv = errno;
- perror(argv[1]);
- return -errsv;
- }
- devfd = open(argv[2], O_WRONLY);
- if (devfd == -1) {
- int errsv = errno;
- perror(argv[2]);
- return -errsv;
- }
- if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) {
- int errsv = errno;
- perror(argv[2]);
- return -errsv;
- }
-
- /* determine the number of blocks needed by the image */
- file_size = lseek(datafd, 0, SEEK_END);
- if (file_size == (off_t)-1) {
- int errsv = errno;
- perror("lseek");
- return -errsv;
- }
- num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE;
- file_size = lseek(datafd, 0, SEEK_SET);
- if (file_size == (off_t)-1) {
- int errsv = errno;
- perror("lseek");
- return -errsv;
- }
- printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt);
- printf("U-Boot will occupy %d blocks\n", num_blocks);
- if (num_blocks > devinfo.eb_cnt) {
- fprintf(stderr, "Insufficient blocks on partition\n");
- return -EINVAL;
- }
-
- printf("IMPORTANT: These blocks must be in an erased state!\n");
- printf("Do you want to proceed?\n");
- scanf("%s", response);
- if ((response[0] != 'y') && (response[0] != 'Y')) {
- printf("Exiting\n");
- close(devfd);
- close(datafd);
- return 0;
- }
-
- blockbuf = calloc(RELIABLE_BLOCKSIZE, 1);
- if (blockbuf == NULL) {
- int errsv = errno;
- perror("calloc");
- return -errsv;
- }
-
- for (block = 0; block < num_blocks; block++) {
- int ofs, page;
- uint8_t *pagebuf = blockbuf, *buf = blockbuf;
- uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */
- size_t len = RELIABLE_BLOCKSIZE;
- int ret;
-
- /* read data for one block from file */
- while (len) {
- ssize_t read_ret = read(datafd, buf, len);
- if (read_ret == -1) {
- int errsv = errno;
- if (errno == EINTR)
- continue;
- perror("read");
- return -errsv;
- } else if (read_ret == 0) {
- break; /* EOF */
- }
- len -= read_ret;
- buf += read_ret;
- }
-
- printf("Block %d: writing\r", block + 1);
- fflush(stdout);
-
- for (page = 0, ofs = 0;
- page < PAGES_PER_BLOCK;
- page++, ofs += PAGESIZE) {
- if (page & 0x04) /* Odd-numbered 2k page */
- continue; /* skipped in reliable mode */
-
- ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs,
- pagebuf, PAGESIZE, oobbuf, OOBSIZE,
- MTD_OPS_PLACE_OOB);
- if (ret) {
- fprintf(stderr,
- "\nmtd_write returned %d on block %d, ofs %x\n",
- ret, block + 1, ofs);
- return -EIO;
- }
- oobbuf = ff_oob; /* oob for subsequent pages */
-
- if (page & 0x01) /* odd-numbered subpage */
- pagebuf += PAGESIZE;
- }
- }
-
- printf("\nDone\n");
-
- close(devfd);
- close(datafd);
- free(blockbuf);
- return 0;
-}
diff --git a/tools/rkimage.c b/tools/rkimage.c
index f9fdcfa..ef31cb6 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -13,11 +13,6 @@
static uint32_t header;
-static int rkimage_check_params(struct image_tool_params *params)
-{
- return 0;
-}
-
static int rkimage_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
{
@@ -56,7 +51,7 @@
"Rockchip Boot Image support",
4,
&header,
- rkimage_check_params,
+ rkcommon_check_params,
rkimage_verify_header,
rkimage_print_header,
rkimage_set_header,