rockchip: rk3328: add clock driver
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
new file mode 100644
index 0000000..948706e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3328_H_
+#define __ASM_ARCH_CRU_RK3328_H_
+
+#include <common.h>
+
+struct rk3328_clk_priv {
+ struct rk3328_cru *cru;
+ ulong rate;
+};
+
+struct rk3328_cru {
+ u32 apll_con[5];
+ u32 reserved1[3];
+ u32 dpll_con[5];
+ u32 reserved2[3];
+ u32 cpll_con[5];
+ u32 reserved3[3];
+ u32 gpll_con[5];
+ u32 reserved4[3];
+ u32 mode_con;
+ u32 misc;
+ u32 reserved5[2];
+ u32 glb_cnt_th;
+ u32 glb_rst_st;
+ u32 glb_srst_snd_value;
+ u32 glb_srst_fst_value;
+ u32 npll_con[5];
+ u32 reserved6[(0x100 - 0xb4) / 4];
+ u32 clksel_con[53];
+ u32 reserved7[(0x200 - 0x1d4) / 4];
+ u32 clkgate_con[29];
+ u32 reserved8[3];
+ u32 ssgtbl[32];
+ u32 softrst_con[12];
+ u32 reserved9[(0x380 - 0x330) / 4];
+ u32 sdmmc_con[2];
+ u32 sdio_con[2];
+ u32 emmc_con[2];
+ u32 sdmmc_ext_con[2];
+};
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (576 * MHz)
+#define CPLL_HZ (594 * MHz)
+
+#define CLK_CORE_HZ (600 * MHz)
+#define ACLKM_CORE_HZ (300 * MHz)
+#define PCLK_DBG_HZ (300 * MHz)
+
+#define PERIHP_ACLK_HZ (144000 * KHz)
+#define PERIHP_HCLK_HZ (72000 * KHz)
+#define PERIHP_PCLK_HZ (72000 * KHz)
+
+#define PWM_CLOCK_HZ (74 * MHz)
+
+enum apll_frequencies {
+ APLL_816_MHZ,
+ APLL_600_MHZ,
+};
+
+#endif /* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile
index 8ecf8ee..bbab036 100644
--- a/arch/arm/mach-rockchip/rk3328/Makefile
+++ b/arch/arm/mach-rockchip/rk3328/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += clk_rk3328.o
obj-y += rk3328.o
obj-y += syscon_rk3328.o
diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c
new file mode 100644
index 0000000..1205516
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3328.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3328_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3328_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_addr_ptr(dev);
+
+ return priv->cru;
+}