Merge patch series "U-boot: arm: Refine the booting on Total Compute"
Leo Yan <leo.yan@arm.com> says:
This patch series is to refine the booting on Arm Total Compuate
platform.
It changes to use the info passed in DTB for initialization DRAM info,
and dynamically initializes the booting envoironment variables.
Another big change is to use an envoironment file for boot commands,
based on it, the series extends to support multiple block devices
(MMC and virtio). And the env file is extended for booting Debian.
The last commit is to update memory mapping info based on the DRAM info
passed via DT binding.
Link: https://lore.kernel.org/r/20241025171821.624702-1-leo.yan@arm.com
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 11f1d5a..4ecf76e 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -1,7 +1,7 @@
variables:
- windows_vm: windows-2019
- ubuntu_vm: ubuntu-22.04
- macos_vm: macOS-12
+ windows_vm: windows-2022
+ ubuntu_vm: ubuntu-24.04
+ macos_vm: macOS-14
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
@@ -239,6 +239,10 @@
cd \${WORK_DIR}
git config --global --add safe.directory \${WORK_DIR}
git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+ # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
+ # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
+ ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
+ ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
@@ -251,6 +255,11 @@
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
+ if [[ "\${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
+ wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
+ wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
+ export BINMAN_INDIRS=/tmp
+ fi
# the below corresponds to .gitlab-ci.yml "script"
cd \${WORK_DIR}
export UBOOT_TRAVIS_BUILD_DIR=/tmp/\${TEST_PY_BD}
@@ -419,6 +428,12 @@
qemu_arm64:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
+ qemu_arm64_lwip:
+ TEST_PY_BD: "qemu_arm64_lwip"
+ TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
+ qemu_arm_sbsa_ref:
+ TEST_PY_BD: "qemu-arm-sbsa"
+ TEST_PY_TEST_SPEC: "not sleep"
qemu_m68k:
TEST_PY_BD: "M5208EVBE"
TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d938c7f..0aeda53 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -27,6 +27,9 @@
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+ # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
+ # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
+ - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
@@ -39,6 +42,11 @@
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
+ - if [[ "${TEST_PY_BD}" == "qemu-arm-sbsa" ]]; then
+ wget -O /tmp/bl1.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/bl1.bin;
+ wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
+ export BINMAN_INDIRS=/tmp;
+ fi
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -348,6 +356,18 @@
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
+qemu_arm64_lwip test.py:
+ variables:
+ TEST_PY_BD: "qemu_arm64_lwip"
+ TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
+ <<: *buildman_and_testpy_dfn
+
+qemu_arm_sbsa test.py:
+ variables:
+ TEST_PY_BD: "qemu-arm-sbsa"
+ TEST_PY_TEST_SPEC: "not sleep"
+ <<: *buildman_and_testpy_dfn
+
qemu_m68k test.py:
variables:
TEST_PY_BD: "M5208EVBE"
diff --git a/.mailmap b/.mailmap
index 952e1da..005e965 100644
--- a/.mailmap
+++ b/.mailmap
@@ -38,7 +38,8 @@
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Dirk Behme <dirk.behme@googlemail.com>
Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
-Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
+Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
@@ -88,6 +89,7 @@
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
+Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
diff --git a/.readthedocs.yml b/.readthedocs.yml
index 7c6c255..16418f2 100644
--- a/.readthedocs.yml
+++ b/.readthedocs.yml
@@ -6,11 +6,11 @@
version: 2
build:
- os: "ubuntu-20.04"
+ os: "ubuntu-24.04"
apt_packages:
- python3-six
tools:
- python: "3.9"
+ python: "3.12"
# Build documentation in the docs/ directory with Sphinx
sphinx:
diff --git a/Kconfig b/Kconfig
index 74e8ce5..eb55f25 100644
--- a/Kconfig
+++ b/Kconfig
@@ -599,7 +599,6 @@
bool
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
- default y if TARGET_TRICORDER
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
@@ -609,14 +608,12 @@
hex
default 0x80000000 if TARGET_PIC32MZDASK
default 0x40200000 if TARGET_DEVKIT8000
- default 0x40200000 if TARGET_TRICORDER
default 0x0
config SYS_SRAM_SIZE
hex
default 0x00080000 if TARGET_PIC32MZDASK
default 0x10000 if TARGET_DEVKIT8000
- default 0x10000 if TARGET_TRICORDER
default 0x0
config SYS_MONITOR_LEN
@@ -647,6 +644,8 @@
config TEXT_BASE
depends on HAVE_TEXT_BASE
default 0x0 if POSITION_INDEPENDENT
+ default 0x17800000 if ARCH_MX6
+ default 0x87800000 if ARCH_MX7
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
default 0x81700000 if MACH_SUNIV
default 0x2a000000 if MACH_SUN9I
@@ -758,8 +757,37 @@
source "env/Kconfig"
+menu Networking
+
+choice
+ prompt "Networking stack"
+ default NET
+
+config NO_NET
+ bool "No networking support"
+
+config NET
+ bool "Legacy U-Boot networking stack"
+ imply NETDEVICES
+
+config NET_LWIP
+ bool "Use lwIP for networking stack"
+ imply NETDEVICES
+ help
+ Include networking support based on the lwIP (lightweight IP)
+ TCP/IP stack (https://nongnu.org/lwip). This is a replacement for
+ the default U-Boot network stack and applications located in net/
+ and enabled via CONFIG_NET as well as other pieces of code that
+ depend on CONFIG_NET (such as cmd/net.c enabled via CONFIG_CMD_NET).
+ Therefore the two symbols CONFIG_NET and CONFIG_NET_LWIP are mutually
+ exclusive.
+
+endchoice
+
source "net/Kconfig"
+endmenu
+
source "drivers/Kconfig"
source "fs/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
index 09298e6..0399ed1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -58,6 +58,13 @@
F: include/acpi/
F: lib/acpi/
+ALIST:
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: include/alist.h
+F: lib/alist.c
+F: test/lib/alist.c
+
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
@@ -65,7 +72,6 @@
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: boot/android_ab.c
-F: cmd/ab_select.c
F: doc/android/ab.rst
F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
@@ -356,7 +362,7 @@
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
-F: drivers/ata/ahci_mvebu.c
+F: drivers/ata/ahci_generic.c
F: drivers/clk/mvebu/
F: drivers/ddr/marvell/
F: drivers/gpio/mvebu_gpio.c
@@ -748,6 +754,7 @@
F: drivers/memory/ti-aemif.c
F: drivers/misc/k3_avs.c
F: drivers/mailbox/k3-sec-procy.c
+F: drivers/pci/pcie_cdns_ti.c
F: drivers/pci/pcie_dw_ti.c
F: drivers/phy/keystone-usb-phy.c
F: drivers/phy/omap-usb2-phy.c
@@ -916,6 +923,7 @@
M: Simon Glass <sjg@chromium.org>
M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
S: Maintained
+F: doc/develop/binman_tests.rst
F: tools/binman/
BLKMAP
@@ -1359,6 +1367,17 @@
F: include/net.h
F: net/
+NETWORK (LWIP)
+M: Jerome Forissier <jerome.forissier@linaro.org>
+S: Maintained
+F: cmd/net-lwip.c
+F: configs/qemu_arm64_lwip_defconfig
+F: drivers/net/sandbox-lwip.c
+F: include/net-lwip.h
+F: lib/lwip/Makefile
+F: lib/lwip/u-boot/
+F: net/lwip/
+
NIOS
M: Thomas Chou <thomas@wytron.com.tw>
S: Maintained
@@ -1592,6 +1611,7 @@
SPI-NOR
M: Jagan Teki <jagan@amarulasolutions.com>
M: Vignesh R <vigneshr@ti.com>
+R: Tudor Ambarus <tudor.ambarus@linaro.org>
S: Maintained
F: drivers/mtd/spi/
F: include/spi_flash.h
@@ -1743,6 +1763,15 @@
F: common/usb_storage.c
F: include/usb.h
+USB TCPM
+M: Sebastian Reichel <sebastian.reichel@collabora.com>
+S: Maintained
+F: cmd/tcpm.c
+F: doc/usage/cmd/tcpm.rst
+F: drivers/usb/tcpm/
+F: include/usb/pd.h
+F: include/usb/tcpm.h
+
USB xHCI
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
diff --git a/Makefile b/Makefile
index 3267fb1..7275a02 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
-VERSION = 2024
-PATCHLEVEL = 10
+VERSION = 2025
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -842,7 +842,9 @@
-I$(srctree)/arch/arm/thumb1/include)) \
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h \
- -I$(srctree)/dts/upstream/include
+ -I$(srctree)/dts/upstream/include \
+ $(if $(CONFIG_NET_LWIP), -I$(srctree)/lib/lwip/lwip/src/include \
+ -I$(srctree)/lib/lwip/u-boot)
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -865,7 +867,7 @@
libs-y += env/
libs-y += lib/
libs-y += fs/
-libs-y += net/
+libs-$(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)) += net/
libs-y += disk/
libs-y += drivers/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
@@ -885,6 +887,7 @@
libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/isp1760/
libs-y += drivers/usb/phy/
+libs-y += drivers/usb/tcpm/
libs-y += drivers/usb/ulpi/
ifdef CONFIG_POST
libs-y += post/
@@ -1381,7 +1384,11 @@
of_list_dirs := $(dir $(EXT_DTB))
else
of_list := $(CONFIG_OF_LIST)
+ifneq ($(CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS),)
+of_list_dirs := $(dt_dir) arch/$(ARCH)/dts
+else
of_list_dirs := $(dt_dir)
+endif
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
endif
@@ -1423,18 +1430,12 @@
# or a generator script
# NOTE: Please do not use this. We are migrating away from Makefile rules to use
# binman instead.
-ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
-U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
- $(call if_changed,copy)
-else
ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
$(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
endif
-endif
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4ce884..7282c41 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -113,6 +113,13 @@
config GICV3
bool
+config DRIVER_GICV2
+ bool "ARM GICV2 driver"
+ select IRQ
+ help
+ ARM GICV2 driver.
+ Basic support for parsing the GICV2 node and generate ACPI tables.
+
config GIC_V3_ITS
bool "ARM GICV3 ITS"
select IRQ
@@ -644,6 +651,7 @@
config ARCH_BCM283X
bool "Broadcom BCM283X family"
+ select CPU
select DM
select DM_GPIO
select DM_SERIAL
@@ -1047,7 +1055,7 @@
imply DM_RNG
imply DM_RTC
imply RTC_PL031
- imply OF_HAS_PRIOR_STAGE
+ imply OF_HAS_PRIOR_STAGE if !TARGET_QEMU_ARM_SBSA
imply VIDEO
imply VIDEO_BOCHS
imply SYS_WHITE_ON_BLACK
@@ -2376,6 +2384,7 @@
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
+source "board/emulation/qemu-sbsa/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 8747d2e..2e71ff2 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -29,6 +29,7 @@
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
+obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += acpi_park_v8.o
else
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv8/acpi_park_v8.S b/arch/arm/cpu/armv8/acpi_park_v8.S
new file mode 100644
index 0000000..0bc605d
--- /dev/null
+++ b/arch/arm/cpu/armv8/acpi_park_v8.S
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 9elements GmbH
+ * Author: Patrick Rudolph <patrick.rudolph@9elements.com>
+ *
+ * This file provides ARMv8 specific code for the generic part of the
+ * ACPI parking protocol implementation. It contains the spinning code
+ * that will be installed into the parking protocol and it points the
+ * secondary CPUs to their own parking protocol page once it has been
+ * set up by the generic part.
+ */
+
+#include <asm/acpi_table.h>
+#include <linux/linkage.h>
+
+/* Filled by C code */
+.global acpi_pp_tables
+acpi_pp_tables:
+ .quad 0
+
+.global acpi_pp_etables
+acpi_pp_etables:
+ .quad 0
+
+/* Read by C code */
+.global acpi_pp_code_size
+acpi_pp_code_size:
+ .word __secondary_pp_code_end - __secondary_pp_code_start
+
+.global acpi_pp_secondary_jump
+ENTRY(acpi_pp_secondary_jump)
+0:
+ /*
+ * Cannot use atomic operations since the MMU and D-cache
+ * might be off. Use the MPIDR instead to find the spintable.
+ */
+
+ /* Check if parking protocol table is ready */
+ ldr x1, =acpi_pp_tables
+ ldr x0, [x1]
+ cbnz x0, 0f
+ wfe
+ b 0b
+
+0: /* Get end of page tables in x3 */
+ ldr x1, =acpi_pp_etables
+ ldr x3, [x1]
+
+ /* Get own CPU ID in w2 */
+ mrs x2, mpidr_el1
+ lsr x9, x2, #32
+ bfi x2, x9, #24, #8 /* w2 is aff3:aff2:aff1:aff0 */
+
+0: /* Loop over all parking protocol pages */
+ cmp x0, x3
+ b.ge hlt
+
+ /* Fetch CPU_ID from current page */
+ ldr x1, [x0, #ACPI_PP_CPU_ID_OFFSET]
+ lsr x9, x1, #32
+ bfi x1, x9, #24, #8 /* w1 is aff3:aff2:aff1:aff0 */
+
+ /* Compare CPU_IDs */
+ cmp w1, w2
+ b.eq 0f
+
+ add x0, x0, #ACPI_PP_PAGE_SIZE
+ b 0b
+
+hlt: wfi
+ b hlt /* Should never happen. */
+
+0: /* x0 points to the 4K-aligned, parking protocol page */
+ add x2, x0, #ACPI_PP_CPU_CODE_OFFSET
+
+ /* Jump to spin code in own parking protocol page */
+ br x2
+ENDPROC(acpi_pp_secondary_jump)
+
+.align 8
+__secondary_pp_code_start:
+.global acpi_pp_code_start
+ENTRY(acpi_pp_code_start)
+ /* x0 points to the 4K-aligned, parking protocol page */
+
+ /* Prepare defines for spinning code */
+ mov w3, #ACPI_PP_CPU_ID_INVALID
+ mov x2, #ACPI_PP_JMP_ADR_INVALID
+
+ /* Mark parking protocol page as ready */
+ str w3, [x0, #ACPI_PP_CPU_ID_OFFSET]
+ dsb sy
+
+0: wfe
+ ldr w1, [x0, #ACPI_PP_CPU_ID_OFFSET]
+
+ /* Check CPU ID is valid */
+ cmp w1, w3
+ b.eq 0b
+
+ /* Check jump address valid */
+ ldr x1, [x0, #ACPI_PP_CPU_JMP_OFFSET]
+ cmp x1, x2
+ b.eq 0b
+
+ /* Clear jump address before jump */
+ str x2, [x0, #ACPI_PP_CPU_JMP_OFFSET]
+ dsb sy
+
+ br x1
+ENDPROC(acpi_pp_code_start)
+ /* Secondary Boot Code ends here */
+__secondary_pp_code_end:
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4a3b9f6..d3a8a7c 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -178,6 +178,18 @@
branch_if_master x0, master_cpu
b spin_table_secondary_jump
/* never return */
+#elif defined(CONFIG_ACPI_PARKING_PROTOCOL) && !defined(CONFIG_SPL_BUILD)
+ branch_if_master x0, master_cpu
+ /*
+ * Waits for ACPI parking protocol memory to be allocated and the spin-table
+ * code to be written. Once ready the secondary CPUs will jump and spin in
+ * their own 4KiB memory region, which is also used as mailbox, until released
+ * by the OS.
+ * The mechanism is similar to the DT enable-method = "spin-table", but works
+ * with ACPI enabled platforms.
+ */
+ b acpi_pp_secondary_jump
+ /* never return */
#elif defined(CONFIG_ARMV8_MULTIENTRY)
branch_if_master x0, master_cpu
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8cbb5d8..aeccfa9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -327,6 +327,7 @@
zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo
zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo
zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo
+zynqmp-sc-vm-p-b1369-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vm-p-m1369-00-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb
@@ -335,6 +336,7 @@
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vm-p-b1369-00-revA.dtb
zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
@@ -961,8 +963,6 @@
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-dhcom-drc02.dtb \
- imx8mp-dhcom-pdk2.dtb \
- imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-dhcom-picoitx.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
@@ -1142,7 +1142,6 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
- stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
@@ -1158,13 +1157,7 @@
stm32mp157c-ed1-scmi.dtb \
stm32mp157c-ev1.dtb \
stm32mp157c-ev1-scmi.dtb \
- stm32mp157c-odyssey.dtb \
- stm32mp15xx-dhcom-drc02.dtb \
- stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcom-picoitx.dtb \
- stm32mp15xx-dhcor-avenger96.dtb \
- stm32mp15xx-dhcor-drc-compact.dtb \
- stm32mp15xx-dhcor-testbench.dtb
+ stm32mp157c-odyssey.dtb
dtb-$(CONFIG_STM32MP25X) += \
stm32mp257f-ev1.dtb
@@ -1172,14 +1165,6 @@
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
- k3-am65-iot2050-spl.dtb \
- k3-am6528-iot2050-basic.dtb \
- k3-am6528-iot2050-basic-pg2.dtb \
- k3-am6548-iot2050-advanced.dtb \
- k3-am6548-iot2050-advanced-pg2.dtb \
- k3-am6548-iot2050-advanced-m2.dtb \
- k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
- k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index d481ead..9a5037d 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -129,3 +129,8 @@
reg = <0x4d>;
};
};
+
+&sgpio {
+ status = "okay";
+ ngpios = <80>;
+};
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 320d2e5..d677705 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -255,6 +255,21 @@
interrupt-controller;
};
+ sgpio: sgpio@1e780200 {
+ compatible = "aspeed,ast2500-sgpio";
+ reg = <0x1e780200 0x100>;
+ interrupts = <40>;
+ clocks = <&scu ASPEED_CLK_APB>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm_default>;
+ status = "disabled";
+ };
+
timer: timer@1e782000 {
/* This timer is a Faraday FTTMR010 derivative */
compatible = "aspeed,ast2400-timer";
@@ -1445,4 +1460,9 @@
function = "WDTRST2";
groups = "WDTRST2";
};
+
+ pinctrl_sgpm_default: sgpm_default {
+ function = "SGPM";
+ groups = "SGPM";
+ };
};
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index 9aac0e2..570ba61 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -266,3 +266,13 @@
bootph-all;
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+};
+
+&sgpiom1 {
+ status = "okay";
+ ngpios = <80>;
+};
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 43db80e..cb8ce8b 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -501,6 +501,36 @@
ngpios = <208>;
};
+ sgpiom0: sgpiom@1e780500 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780500 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm1_default>;
+ status = "disabled";
+ };
+
+ sgpiom1: sgpiom@1e780600 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780600 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm2_default>;
+ status = "disabled";
+ };
+
gpio1: gpio@1e780800 {
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780800 0x800>;
@@ -2167,4 +2197,14 @@
function = "PCIE1RC";
groups = "PCIE1RC";
};
+
+ pinctrl_sgpm1_default: sgpm1_default {
+ function = "SGPM1";
+ groups = "SGPM1";
+ };
+
+ pinctrl_sgpm2_default: sgpm2_default {
+ function = "SGPM2";
+ groups = "SGPM2";
+ };
};
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 6e5379e..38925d5 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -7,21 +7,51 @@
&{/imx8qm-pm} {
+ bootph-some-ram;
bootph-pre-ram;
};
&mu {
+ bootph-some-ram;
bootph-pre-ram;
};
&clk {
+ bootph-some-ram;
bootph-pre-ram;
};
&iomuxc {
+ bootph-some-ram;
bootph-pre-ram;
};
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_lpuart0 {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+ bootph-pre-ram;
+};
+
&pd_lsio {
bootph-pre-ram;
};
@@ -75,10 +105,12 @@
};
&pd_dma {
+ bootph-some-ram;
bootph-pre-ram;
};
&pd_dma_lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
@@ -131,6 +163,7 @@
};
&lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts
index 63908ba..6cf7ce3 100644
--- a/arch/arm/dts/fsl-imx8qm-mek.dts
+++ b/arch/arm/dts/fsl-imx8qm-mek.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 591eb66..e670214 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -6,22 +6,35 @@
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
-
+ bootph-some-ram;
bootph-pre-ram;
};
&mu {
+ bootph-some-ram;
bootph-pre-ram;
};
&clk {
+ bootph-some-ram;
bootph-pre-ram;
};
&iomuxc {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-mek} {
+ bootph-some-ram;
bootph-pre-ram;
};
+&pinctrl_lpuart0 {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
&pd_lsio {
bootph-pre-ram;
};
@@ -75,10 +88,12 @@
};
&pd_dma {
+ bootph-some-ram;
bootph-pre-ram;
};
&pd_dma_lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
@@ -131,6 +146,7 @@
};
&lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 6a987f0..983b918 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
-#include "fsl-imx8qxp-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
deleted file mode 100644
index 8f4eff3..0000000
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ /dev/null
@@ -1,158 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- *
- * DHCOM iMX8MP variant:
- * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
- * DHCOM PCB number: 660-100 or newer
- * PDK2 PCB number: 516-400 or newer
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mp-dhcom-som.dtsi"
-
-/ {
- model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
- compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
- "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart1;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-0 {
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
- label = "TA1-GPIO-A";
- linux,code = <KEY_A>;
- pinctrl-0 = <&pinctrl_dhcom_a>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-1 {
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
- label = "TA2-GPIO-B";
- linux,code = <KEY_B>;
- pinctrl-0 = <&pinctrl_dhcom_b>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-2 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
- label = "TA3-GPIO-C";
- linux,code = <KEY_C>;
- pinctrl-0 = <&pinctrl_dhcom_c>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-3 {
- gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
- label = "TA4-GPIO-D";
- linux,code = <KEY_D>;
- pinctrl-0 = <&pinctrl_dhcom_d>;
- pinctrl-names = "default";
- wakeup-source;
- };
- };
-
- led {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
- pinctrl-0 = <&pinctrl_dhcom_e>;
- pinctrl-names = "default";
- };
-
- led-1 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
- pinctrl-0 = <&pinctrl_dhcom_f>;
- pinctrl-names = "default";
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
- pinctrl-0 = <&pinctrl_dhcom_h>;
- pinctrl-names = "default";
- };
-
- led-3 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
- pinctrl-0 = <&pinctrl_dhcom_i>;
- pinctrl-names = "default";
- };
- };
-};
-
-&fec { /* Second ethernet */
- pinctrl-0 = <&pinctrl_fec_rgmii>;
- phy-handle = <ðphypdk>;
- phy-mode = "rgmii";
-
- mdio {
- ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
- compatible = "ethernet-phy-ieee802.3-c22";
- pinctrl-0 = <&pinctrl_ethphy1>;
- pinctrl-names = "default";
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- max-speed = <100>;
- reg = <7>;
- reset-assert-us = <1000>;
- reset-deassert-us = <1000>;
- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- rxdv-skew-ps = <0>;
- txc-skew-ps = <3000>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- };
- };
-};
-
-&flexcan1 {
- status = "okay";
-};
-
-&usb3_1 {
- fsl,over-current-active-low;
-};
-
-&iomuxc {
- /*
- * GPIO_A,B,C,D are connected to buttons.
- * GPIO_E,F,H,I are connected to LEDs.
- * GPIO_M is connected to CLKOUT2.
- */
- pinctrl-0 = <&pinctrl_hog_base
- &pinctrl_dhcom_g &pinctrl_dhcom_j
- &pinctrl_dhcom_k &pinctrl_dhcom_l
- &pinctrl_dhcom_int>;
-};
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts
deleted file mode 100644
index 867d238..0000000
--- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts
+++ /dev/null
@@ -1,317 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Marek Vasut <marex@denx.de>
- *
- * DHCOM iMX8MP variant:
- * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
- * DHCOM PCB number: 660-100 or newer
- * PDK3 PCB number: 669-100 or newer
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mp-dhcom-som.dtsi"
-
-/ {
- model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)";
- compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
- "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart1;
- };
-
- clk_ext_audio_codec: clock-codec {
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- compatible = "fixed-clock";
- };
-
- clk_xtal25: clk-xtal25 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usb_c_0_hs_ep: endpoint {
- remote-endpoint = <&dwc3_0_hs_ep>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usb_c_0_ss_ep: endpoint {
- remote-endpoint = <&ptn5150_in_ep>;
- };
- };
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-0 {
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
- label = "TA1-GPIO-A";
- linux,code = <KEY_A>;
- pinctrl-0 = <&pinctrl_dhcom_a>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-1 {
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
- label = "TA2-GPIO-B";
- linux,code = <KEY_B>;
- pinctrl-0 = <&pinctrl_dhcom_b>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-2 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
- label = "TA3-GPIO-C";
- linux,code = <KEY_C>;
- pinctrl-0 = <&pinctrl_dhcom_c>;
- pinctrl-names = "default";
- wakeup-source;
- };
-
- button-3 {
- gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */
- label = "TA4-GPIO-E";
- linux,code = <KEY_E>;
- pinctrl-0 = <&pinctrl_dhcom_e>;
- pinctrl-names = "default";
- wakeup-source;
- };
- };
-
- led {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <0>;
- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */
- pinctrl-0 = <&pinctrl_dhcom_d>;
- pinctrl-names = "default";
- };
-
- led-1 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
- pinctrl-0 = <&pinctrl_dhcom_f>;
- pinctrl-names = "default";
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
- pinctrl-0 = <&pinctrl_dhcom_g>;
- pinctrl-names = "default";
- };
-
- led-3 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "off";
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <3>;
- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
- pinctrl-0 = <&pinctrl_dhcom_i>;
- pinctrl-names = "default";
- };
- };
-
- reg_avdd: regulator-avdd { /* AUDIO_VDD */
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "AUDIO_VDD";
- };
-};
-
-&i2c5 {
- i2cmux@70 {
- compatible = "nxp,pca9540";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2cmuxed0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- typec@3d {
- compatible = "nxp,ptn5150";
- reg = <0x3d>;
- interrupt-parent = <&gpio4>;
- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ptn5150>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- ptn5150_in_ep: endpoint {
- remote-endpoint = <&usb_c_0_ss_ep>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- ptn5150_out_ep: endpoint {
- remote-endpoint = <&dwc3_0_ss_ep>;
- };
- };
- };
- };
-
- power-sensor@40 {
- compatible = "ti,ina238";
- reg = <0x40>;
- shunt-resistor = <20000>; /* 0.02 R */
- ti,shunt-gain = <1>; /* Drop cca. 40mV */
- };
-
- eeprom_board: eeprom@54 {
- compatible = "atmel,24c04";
- pagesize = <16>;
- reg = <0x54>;
- };
-
- pcieclk: clk@6b {
- compatible = "skyworks,si52144";
- reg = <0x6b>;
- clocks = <&clk_xtal25>;
- #clock-cells = <1>;
- };
- };
-
- i2cmuxed1: i2c@1 { /* HDMI DDC I2C */
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
-};
-
-&fec { /* Second ethernet */
- pinctrl-0 = <&pinctrl_fec_rgmii>;
- phy-handle = <ðphypdk>;
- phy-mode = "rgmii-id";
-
- mdio {
- ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */
- compatible = "ethernet-phy-id0022.1642",
- "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pinctrl_ethphy1>;
- pinctrl-names = "default";
- reg = <7>;
- reset-assert-us = <1000>;
- /* RESET_N signal rise time ~100ms */
- reset-deassert-us = <120000>;
- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- };
-};
-
-&flexcan1 {
- status = "okay";
-};
-
-&pcie_phy {
- clocks = <&pcieclk 1>;
- clock-names = "ref";
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- status = "okay";
-};
-
-&pcie {
- fsl,max-link-speed = <3>;
- reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&usb_dwc3_0 {
- usb-role-switch;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dwc3_0_hs_ep: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usb_c_0_hs_ep>;
- };
-
- dwc3_0_ss_ep: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ptn5150_out_ep>;
- };
- };
-};
-
-&usb3_1 {
- fsl,disable-port-power-control;
- fsl,permanently-attached;
-};
-
-&usb_dwc3_1 {
- /* This port has USB5734 Hub connected to it, PWR/OC pins are unused */
- /delete-property/ pinctrl-names;
- /delete-property/ pinctrl-0;
-};
-
-&iomuxc {
- /*
- * GPIO_A,B,C,E are connected to buttons.
- * GPIO_D,F,G,I are connected to LEDs.
- * GPIO_H is connected to USB Hub RESET_N.
- * GPIO_M is connected to CLKOUT2.
- */
- pinctrl-0 = <&pinctrl_hog_base
- &pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k
- &pinctrl_dhcom_l
- &pinctrl_dhcom_int>;
-
- pinctrl_ptn5150: ptn5150grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-navqp-u-boot.dtsi b/arch/arm/dts/imx8mp-navqp-u-boot.dtsi
new file mode 100644
index 0000000..fe41d81
--- /dev/null
+++ b/arch/arm/dts/imx8mp-navqp-u-boot.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-all;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-all;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&i2c1 {
+ bootph-all;
+};
+
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+ bootph-pre-ram;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&uart2 {
+ bootph-pre-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+};
+
+&usdhc3 {
+ bootph-pre-ram;
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi
new file mode 100644
index 0000000..27b4b2e
--- /dev/null
+++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx93-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ðphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&s4muap {
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 03e6a85..a25eae9 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -87,7 +87,7 @@
reg = <0x402c0000 0x4000>;
interrupts = <110>;
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_AHB_PODF>,
<&clks IMXRT1050_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
index c2fd0c0..0d8e701 100644
--- a/arch/arm/dts/imxrt1170-evk.dts
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -20,6 +20,8 @@
};
memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
device_type = "memory";
reg = <0x20240000 0xf0000 0x80000000 0x4000000>;
diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts
index ec5d3f4..b8e5f49 100644
--- a/arch/arm/dts/k3-am62-r5-lp-sk.dts
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -25,7 +25,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index f0b66f0..9e0a6ed 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -24,7 +24,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1250000000>;
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 0912b95..d2dd754 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -25,7 +25,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index bc05dcb..464227b 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -23,7 +23,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts
index 658f2cf..baf1a83 100644
--- a/arch/arm/dts/k3-am62p5-r5-sk.dts
+++ b/arch/arm/dts/k3-am62p5-r5-sk.dts
@@ -26,7 +26,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index be85969..933f750 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -22,7 +22,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 2186152..6e31dfd 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -22,7 +22,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 3a6db91..f49d6f2 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -84,12 +84,12 @@
};
fdt-0 {
- description = "k3-am65-iot2050-spl.dtb";
+ description = "ti/k3-am6528-iot2050-basic.dtb";
type = "flat_dt";
arch = "arm";
compression = "none";
blob-ext {
- filename = "spl/dts/k3-am65-iot2050-spl.dtb";
+ filename = "spl/dts/ti/k3-am6528-iot2050-basic.dtb";
};
};
};
@@ -205,10 +205,10 @@
};
fit@380000 {
- fit,fdt-list-val = "k3-am6528-iot2050-basic", "k3-am6548-iot2050-advanced";
+ fit,fdt-list-val = "ti/k3-am6528-iot2050-basic", "ti/k3-am6548-iot2050-advanced";
configurations {
- default = "k3-am6528-iot2050-basic";
+ default = "ti/k3-am6528-iot2050-basic";
@config-SEQ {
loadables =
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
@@ -229,7 +229,10 @@
};
fit@380000 {
- fit,fdt-list-val = "k3-am6528-iot2050-basic-pg2", "k3-am6548-iot2050-advanced-pg2", "k3-am6548-iot2050-advanced-m2";
+ fit,fdt-list-val = "ti/k3-am6528-iot2050-basic-pg2",
+ "ti/k3-am6548-iot2050-advanced-pg2",
+ "ti/k3-am6548-iot2050-advanced-m2",
+ "ti/k3-am6548-iot2050-advanced-sm";
images {
bkey-usb3-overlay {
@@ -239,7 +242,7 @@
arch = "arm64";
compression = "none";
blob-ext {
- filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo";
+ filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo";
};
hash {
algo = "sha256";
@@ -253,7 +256,7 @@
arch = "arm64";
compression = "none";
blob-ext {
- filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo";
+ filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo";
};
hash {
algo = "sha256";
@@ -262,7 +265,7 @@
};
configurations {
- default = "k3-am6528-iot2050-basic-pg2";
+ default = "ti/k3-am6528-iot2050-basic-pg2";
@config-SEQ {
loadables =
#ifdef CONFIG_WDT_K3_RTI_FW_FILE
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi
deleted file mode 100644
index 51f902f..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2021
- *
- * Authors:
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG1
- */
-
-&dss {
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
-
-&serdes0 {
- status = "disabled";
-};
-
-&sdhci1 {
- no-1-8-v;
-};
-
-&tx_pru0_0 {
- status = "disabled";
-};
-
-&tx_pru0_1 {
- status = "disabled";
-};
-
-&tx_pru1_0 {
- status = "disabled";
-};
-
-&tx_pru1_1 {
- status = "disabled";
-};
-
-&tx_pru2_0 {
- status = "disabled";
-};
-
-&tx_pru2_1 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
deleted file mode 100644
index e9419c4..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2021
- *
- * Authors:
- * Chao Zeng <chao.zeng@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG2
- */
-
-&main_pmx0 {
- cp2102n_reset_pin_default: cp2102n-reset-default-pins {
- pinctrl-single,pins = <
- /* (AF12) GPIO1_24, used as cp2102 reset */
- AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
- >;
- };
-};
-
-&main_gpio1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp2102n_reset_pin_default>;
- gpio-line-names =
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "CP2102N-RESET";
-};
-
-&dss {
- /* Workaround needed to get DP clock of 154Mhz */
- assigned-clocks = <&k3_clks 67 0>;
-};
-
-&serdes0 {
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
-};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
- phys = <&serdes0 PHY_TYPE_USB3 0>;
- phy-names = "usb3-phy";
-};
-
-&usb0 {
- maximum-speed = "super-speed";
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi
deleted file mode 100644
index fa71781..0000000
--- a/arch/arm/dts/k3-am65-iot2050-common.dtsi
+++ /dev/null
@@ -1,738 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
- */
-
-#include "k3-am654.dtsi"
-#include <dt-bindings/phy/phy.h>
-
-/ {
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- i2c5 = &main_i2c3;
- spi0 = &mcu_spi0;
- mmc0 = &sdhci1;
- mmc1 = &sdhci0;
- };
-
- chosen {
- stdout-path = "serial3:115200n8";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: secure-ddr@9e800000 {
- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0100000 0 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1100000 0 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a2000000 {
- reg = <0x00 0xa2000000 0x00 0x00200000>;
- alignment = <0x1000>;
- no-map;
- };
-
- /* To reserve the power-on(PON) reason for watchdog reset */
- wdt_reset_memory_region: wdt-memory@a2200000 {
- reg = <0x00 0xa2200000 0x00 0x00001000>;
- no-map;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>;
-
- status-led-red {
- gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- status-led-green {
- gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
- };
-
- user-led1-red {
- gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
- };
-
- user-led1-green {
- gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
- };
-
- user-led2-red {
- gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
- };
-
- user-led2-green {
- gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
- };
- };
-
- dp_refclk: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- };
-};
-
-&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
- /* (AD6) WKUP_I2C0_SDA */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
- >;
- };
-
- mcu_i2c0_pins_default: mcu-i2c0-default-pins {
- pinctrl-single,pins = <
- /* (AD8) MCU_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
- /* (AD7) MCU_I2C0_SDA */
- AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
- >;
- };
-
- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
- pinctrl-single,pins = <
- /* (R2) WKUP_GPIO0_21 */
- AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
- >;
- };
-
- push_button_pins_default: push-button-default-pins {
- pinctrl-single,pins = <
- /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
- AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
- >;
- };
-
- arduino_uart_pins_default: arduino-uart-default-pins {
- pinctrl-single,pins = <
- /* (P4) MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
- /* (P5) MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
- >;
- };
-
- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
- pinctrl-single,pins = <
- /* (P1) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
- >;
- };
-
- arduino_io_oe_pins_default: arduino-io-oe-default-pins {
- pinctrl-single,pins = <
- /* (N4) WKUP_GPIO0_34 */
- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
- /* (M2) WKUP_GPIO0_36 */
- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
- /* (M3) WKUP_GPIO0_37 */
- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
- /* (M4) WKUP_GPIO0_38 */
- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
- /* (M1) WKUP_GPIO0_41 */
- AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
- /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
- /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
- /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
- /* (R4) MCU_OSPI0_CSn0 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
- >;
- };
-
- db9_com_mode_pins_default: db9-com-mode-default-pins {
- pinctrl-single,pins = <
- /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
- AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
- /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
- AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
- /* (AC1) WKUP_GPIO0_7, used as uart0 term */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
- /* (AC2) WKUP_GPIO0_6, used as uart0 en */
- AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
- >;
- };
-
- leds_pins_default: leds-default-pins {
- pinctrl-single,pins = <
- /* (T2) WKUP_GPIO0_17, used as user led1 red */
- AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
- /* (R3) WKUP_GPIO0_22, used as user led1 green */
- AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
- /* (R5) WKUP_GPIO0_24, used as status led red */
- AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
- /* (N2) WKUP_GPIO0_32, used as status led green */
- AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
- >;
- };
-
- mcu_spi0_pins_default: mcu-spi0-default-pins {
- pinctrl-single,pins = <
- /* (Y1) MCU_SPI0_CLK */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
- /* (Y3) MCU_SPI0_D0 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
- /* (Y2) MCU_SPI0_D1 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
- /* (Y4) MCU_SPI0_CS0 */
- AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
- >;
- };
-
- minipcie_pins_default: minipcie-default-pins {
- pinctrl-single,pins = <
- /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
- AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
- >;
- };
-};
-
-&main_pmx0 {
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
- AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
- AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
- AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
- AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
- >;
- };
-
- usb0_pins_default: usb0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- };
-
- usb1_pins_default: usb1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
- >;
- };
-
- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
- >;
- };
-
- dss_vout1_pins_default: dss-vout1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
- AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
- AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
- AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
- AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
- AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
- AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
- AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
- AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
- AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
- AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
- AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
- AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
- AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
- AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
- AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
- AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
- AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
- AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
- AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
- AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
- AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
- AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
- AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
- AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
- AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
- AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
- AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
- >;
- };
-
- dp_pins_default: dp-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
- AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
- >;
- };
-};
-
-&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
- AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
- AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
- >;
- };
-
- ecap0_pins_default: ecap0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
-};
-
-&main_uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_uart_pins_default>;
-};
-
-&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
- gpio-line-names =
- "main_gpio0-base", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "IO4", "", "IO5", "", "", "IO6", "",
- "", "", "", "IO7", "", "", "", "", "IO8", "",
- "", "IO9";
-};
-
-&wkup_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&arduino_io_d2_to_d3_pins_default>,
- <&arduino_i2c_aio_switch_pins_default>,
- <&arduino_io_oe_pins_default>,
- <&push_button_pins_default>,
- <&db9_com_mode_pins_default>;
- gpio-line-names =
- /* 0..9 */
- "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
- "UART0-enable", "UART0-terminate", "", "WIFI-disable",
- /* 10..19 */
- "", "", "", "", "", "", "", "", "", "",
- /* 20..29 */
- "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
- /* 30..39 */
- "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
- "IO16-direction", "IO15-direction", "IO14-direction", "A3",
- /* 40..49 */
- "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
- "IO11",
- /* 50..51 */
- "IO12", "IO10";
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
-&mcu_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- psu: regulator@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "tps62363-vout";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- ti,enable-vout-discharge;
- };
-
- /* D4200 */
- pcal9535_1: gpio@20 {
- compatible = "nxp,pcal9535";
- reg = <0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
- "A5-pull", "", "",
- "IO14-enable", "IO15-enable", "IO16-enable",
- "IO17-enable", "IO18-enable", "IO19-enable";
- };
-
- /* D4201 */
- pcal9535_2: gpio@21 {
- compatible = "nxp,pcal9535";
- reg = <0x21>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-direction", "IO1-direction", "IO2-direction",
- "IO3-direction", "IO4-direction", "IO5-direction",
- "IO6-direction", "IO7-direction",
- "IO8-direction", "IO9-direction", "IO10-direction",
- "IO11-direction", "IO12-direction", "IO13-direction",
- "IO19-direction";
- };
-
- /* D4202 */
- pcal9535_3: gpio@25 {
- compatible = "nxp,pcal9535";
- reg = <0x25>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
- "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
- "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
- "IO12-pull", "IO13-pull";
- };
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-
- eeprom: eeprom@54 {
- compatible = "atmel,24c08";
- reg = <0x54>;
- pagesize = <16>;
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c3_pins_default>;
- clock-frequency = <400000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp-bridge@f {
- compatible = "toshiba,tc358767";
- reg = <0x0f>;
- pinctrl-names = "default";
- pinctrl-0 = <&dp_pins_default>;
- reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
-
- clock-names = "ref";
- clocks = <&dp_refclk>;
-
- toshiba,hpd-pin = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- bridge_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
- };
-};
-
-&mcu_cpsw {
- status = "disabled";
-};
-
-&ecap0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ecap0_pins_default>;
-};
-
-&sdhci1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "host";
-};
-
-&usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_default>;
- dr_mode = "host";
-};
-
-&mcu_spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_spi0_pins_default>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- ti,pindir-d0-out-d1-in;
-};
-
-&tscadc1 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5>;
- };
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- seboot@0 {
- label = "seboot";
- reg = <0x0 0x180000>; /* 1.5M */
- };
-
- tispl@180000 {
- label = "tispl";
- reg = <0x180000 0x200000>; /* 2M */
- };
-
- u-boot@380000 {
- label = "u-boot";
- reg = <0x380000 0x300000>; /* 3M */
- };
-
- env@680000 {
- label = "env";
- reg = <0x680000 0x20000>; /* 128K */
- };
-
- env-backup@6a0000 {
- label = "env.backup";
- reg = <0x6a0000 0x20000>; /* 128K */
- };
-
- otpcmd@6c0000 {
- label = "otpcmd";
- reg = <0x6c0000 0x10000>; /* 64K */
- };
-
- unused@6d0000 {
- label = "unused";
- reg = <0x6d0000 0x7b0000>; /* 7872K */
- };
-
- seboot-backup@e80000 {
- label = "seboot.backup";
- reg = <0xe80000 0x180000>; /* 1.5M */
- };
- };
- };
-};
-
-&dss {
- pinctrl-names = "default";
- pinctrl-0 = <&dss_vout1_pins_default>;
-
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
-
- dpi_out: endpoint {
- remote-endpoint = <&bridge_in>;
- };
- };
-};
-
-&pcie1_rc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_pins_default>;
-
- num-lanes = <1>;
- phys = <&serdes1 PHY_TYPE_PCIE 0>;
- phy-names = "pcie-phy0";
- reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
-};
-
-&mcu_r5fss0_core1 {
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
-};
-
-&mcu_rti1 {
- memory-region = <&wdt_reset_memory_region>;
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-spl.dts b/arch/arm/dts/k3-am65-iot2050-spl.dts
deleted file mode 100644
index 4e668fa..0000000
--- a/arch/arm/dts/k3-am65-iot2050-spl.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Jan Kiszka <jan.kiszka@siemens.com>
- */
-
-/dts-v1/;
-
-#include "k3-am65-iot2050-common.dtsi"
-#include "k3-am65-iot2050-common-u-boot.dtsi"
-
-/ {
- compatible = "siemens,iot2050", "ti,am654";
- model = "Siemens IOT2050";
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
deleted file mode 100644
index 5ab434c..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Basic variant, PG1 and PG2
- */
-
-#include "k3-am65-iot2050-common.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 1G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
- };
-
- cpus {
- cpu-map {
- /delete-node/ cluster1;
- };
- /delete-node/ cpu@100;
- /delete-node/ cpu@101;
- };
-
- /delete-node/ l2-cache1;
-};
-
-/* eMMC */
-&sdhci0 {
- status = "disabled";
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
- AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
- AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
- AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
- >;
- };
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on Basic boards */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts b/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts
deleted file mode 100644
index c62549a..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
- * 1 GB RAM, no eMMC, main_uart0 on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6528-iot2050-basic-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-basic-pg2", "ti,am654";
- model = "SIMATIC IOT2050 Basic PG2";
-};
diff --git a/arch/arm/dts/k3-am6528-iot2050-basic.dts b/arch/arm/dts/k3-am6528-iot2050-basic.dts
deleted file mode 100644
index 87928ff..0000000
--- a/arch/arm/dts/k3-am6528-iot2050-basic.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
- * 1 GB RAM, no eMMC, main_uart0 on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6528-iot2050-basic-common.dtsi"
-#include "k3-am65-iot2050-common-pg1.dtsi"
-
-/ {
- compatible = "siemens,iot2050-basic", "ti,am654";
- model = "SIMATIC IOT2050 Basic";
-};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index dea2ba8..ab5195e 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -22,7 +22,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
ti,sci = <&dmsc>;
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
deleted file mode 100644
index be55494..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * Common bits of the IOT2050 Advanced variant, PG1 and PG2
- */
-
-/dts-v1/;
-
-#include "k3-am65-iot2050-common.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-};
-
-&main_pmx0 {
- main_mmc0_pins_default: main-mmc0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-};
-
-/* eMMC */
-&sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
deleted file mode 100644
index 774eb14..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2023
- *
- * Authors:
- * Chao Zeng <chao.zeng@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
- * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced-m2", "ti,am654";
- model = "SIMATIC IOT2050 Advanced M2";
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
-
-&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
- >;
- };
-
- main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
- >;
- };
-
- main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
- AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
- >;
- };
-
- main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
- AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
- AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
- >;
- };
-};
-
-&main_pmx1 {
- main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
- AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
- >;
- };
-};
-
-&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&main_m2_pcie_mux_control>,
- <&arduino_io_d4_to_d9_pins_default>;
-};
-
-&main_gpio1 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&main_m2_enable_pins_default>,
- <&main_pmx0_m2_config_pins_default>,
- <&main_pmx1_m2_config_pins_default>,
- <&cp2102n_reset_pin_default>;
-};
-
-/*
- * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
- * Firmware switches to other modes via device tree overlays.
- */
-
-&serdes0 {
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
-};
-
-&pcie0_rc {
- pinctrl-names = "default";
- pinctrl-0 = <&main_bkey_pcie_reset>;
-
- num-lanes = <2>;
- phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
- phy-names = "pcie-phy0","pcie-phy1";
- reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
- /delete-property/ phys;
- /delete-property/ phy-names;
-};
-
-&usb0 {
- maximum-speed = "high-speed";
- /delete-property/ snps,dis-u1-entry-quirk;
- /delete-property/ snps,dis-u2-entry-quirk;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts
deleted file mode 100644
index f00dc86..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg2.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
- model = "SIMATIC IOT2050 Advanced PG2";
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi
new file mode 120000
index 0000000..859776d
--- /dev/null
+++ b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi
@@ -0,0 +1 @@
+k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced.dts b/arch/arm/dts/k3-am6548-iot2050-advanced.dts
deleted file mode 100644
index 077f165..0000000
--- a/arch/arm/dts/k3-am6548-iot2050-advanced.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) Siemens AG, 2018-2021
- *
- * Authors:
- * Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszka@siemens.com>
- *
- * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
- *
- * Product homepage:
- * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
- */
-
-/dts-v1/;
-
-#include "k3-am6548-iot2050-advanced-common.dtsi"
-#include "k3-am65-iot2050-common-pg1.dtsi"
-
-/ {
- compatible = "siemens,iot2050-advanced", "ti,am654";
- model = "SIMATIC IOT2050 Advanced";
-};
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
index 4d6aab5..9c6e324 100644
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -9,104 +9,4 @@
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-am69-sk-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 0>;
- assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- status = "okay";
- bootph-pre-ram;
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>,
- <&secure_proxy_mcu 5>,
- <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
- bootph-pre-ram;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- bootph-pre-ram;
- status = "okay";
-};
-
-&ospi0 {
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
-};
-
-&ospi1 {
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x0 0x58000000 0x0 0x8000000>;
-};
-
-&fss {
- /* enable ranges missing from the FSS node */
- ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
- <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j784s4-r5.dtsi"
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index fac108c..f096b10 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -23,7 +23,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
+ clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>;
diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi
index fd0d921..688a6cf 100644
--- a/arch/arm/dts/k3-j721e-r5.dtsi
+++ b/arch/arm/dts/k3-j721e-r5.dtsi
@@ -20,7 +20,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
+ clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index e92b191..506ad9b 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -10,3 +10,12 @@
#include "k3-j721s2-ddr.dtsi"
#include "k3-j721s2-common-proc-board-u-boot.dtsi"
#include "k3-j721s2-r5.dtsi"
+
+&tps659411 {
+ bootph-pre-ram;
+};
+
+&wkup_vtm0 {
+ bootph-pre-ram;
+ vdd-supply-2 = <&bucka1234>;
+};
diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi
index caf696c..634676c 100644
--- a/arch/arm/dts/k3-j721s2-r5.dtsi
+++ b/arch/arm/dts/k3-j721s2-r5.dtsi
@@ -20,7 +20,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
+ clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 3>;
assigned-clock-rates = <200000000>, <2000000000>;
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi
index 28087a3..6b52116 100644
--- a/arch/arm/dts/k3-j722s-binman.dtsi
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -8,6 +8,56 @@
#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM)
&binman {
+ tiboot3-j722s-hs-evm.bin {
+ filename = "tiboot3-j722s-hs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl>;
+ content-sysfw = <&ti_fs_enc>;
+ content-sysfw-data = <&combined_tifs_cfg>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert>;
+ content-dm-data = <&combined_dm_cfg>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c7a800>;
+ };
+
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
tiboot3-j722s-hs-fs-evm.bin {
filename = "tiboot3-j722s-hs-fs-evm.bin";
symlink = "tiboot3.bin";
diff --git a/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi b/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi
new file mode 100644
index 0000000..8cd121a
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi
@@ -0,0 +1,2797 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ * - SysConfig: Revision 1.21.1+3772
+ * - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * This file was generated on Mon Sep 23 2024 00:17:01 GMT+0530 (IST)
+ */
+
+#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS_PLL_FREQUENCY_0 25000000
+#define DDRSS_PLL_FREQUENCY_1 1000000000
+#define DDRSS_PLL_FREQUENCY_2 1000000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x00061A80
+#define DDRSS_CTL_12_DATA 0x003D0900
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000FA0
+#define DDRSS_CTL_15_DATA 0x00061A80
+#define DDRSS_CTL_16_DATA 0x003D0900
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000FA0
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00005050
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000800
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000204
+#define DDRSS_CTL_50_DATA 0x00820014
+#define DDRSS_CTL_51_DATA 0x0915005A
+#define DDRSS_CTL_52_DATA 0x00003E28
+#define DDRSS_CTL_53_DATA 0x00820014
+#define DDRSS_CTL_54_DATA 0x0915005A
+#define DDRSS_CTL_55_DATA 0x09003E28
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x0400036D
+#define DDRSS_CTL_58_DATA 0x09102005
+#define DDRSS_CTL_59_DATA 0x00001C14
+#define DDRSS_CTL_60_DATA 0x0F00891C
+#define DDRSS_CTL_61_DATA 0x09102010
+#define DDRSS_CTL_62_DATA 0x00001C14
+#define DDRSS_CTL_63_DATA 0x0F00891C
+#define DDRSS_CTL_64_DATA 0x03042010
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x26292629
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x044E4E08
+#define DDRSS_CTL_69_DATA 0x042E2E04
+#define DDRSS_CTL_70_DATA 0x00002E2E
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x00130803
+#define DDRSS_CTL_75_DATA 0x00000059
+#define DDRSS_CTL_76_DATA 0x000002F8
+#define DDRSS_CTL_77_DATA 0x00000F34
+#define DDRSS_CTL_78_DATA 0x000002F8
+#define DDRSS_CTL_79_DATA 0x00000F34
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x0000000A
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x0000017C
+#define DDRSS_CTL_84_DATA 0x000003C8
+#define DDRSS_CTL_85_DATA 0x0000017C
+#define DDRSS_CTL_86_DATA 0x000003C8
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000F0005
+#define DDRSS_CTL_90_DATA 0x2C08000F
+#define DDRSS_CTL_91_DATA 0x0A05052C
+#define DDRSS_CTL_92_DATA 0x1C0F0A03
+#define DDRSS_CTL_93_DATA 0x1C0F0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x00140014
+#define DDRSS_CTL_97_DATA 0x03070307
+#define DDRSS_CTL_98_DATA 0x03070307
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041E04
+#define DDRSS_CTL_103_DATA 0x0F0A0F0A
+#define DDRSS_CTL_104_DATA 0x0A04041E
+#define DDRSS_CTL_105_DATA 0x030F0A0F
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x0003CD00
+#define DDRSS_CTL_127_DATA 0x0003CD00
+#define DDRSS_CTL_128_DATA 0x0003CD00
+#define DDRSS_CTL_129_DATA 0x0003CD00
+#define DDRSS_CTL_130_DATA 0x0003CD00
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00006A6C
+#define DDRSS_CTL_133_DATA 0x0003CD00
+#define DDRSS_CTL_134_DATA 0x0003CD00
+#define DDRSS_CTL_135_DATA 0x0003CD00
+#define DDRSS_CTL_136_DATA 0x0003CD00
+#define DDRSS_CTL_137_DATA 0x0003CD00
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00006A6C
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x07010A09
+#define DDRSS_CTL_162_DATA 0x000E0A09
+#define DDRSS_CTL_163_DATA 0x010A0900
+#define DDRSS_CTL_164_DATA 0x0E0A0907
+#define DDRSS_CTL_165_DATA 0x0A090000
+#define DDRSS_CTL_166_DATA 0x0A090701
+#define DDRSS_CTL_167_DATA 0x0000000E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00C80190
+#define DDRSS_CTL_199_DATA 0x0F0F01F4
+#define DDRSS_CTL_200_DATA 0x000001F4
+#define DDRSS_CTL_201_DATA 0x00C80190
+#define DDRSS_CTL_202_DATA 0x0F0F01F4
+#define DDRSS_CTL_203_DATA 0x000001F4
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000084
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x000000E4
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x000000E4
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000084
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x000000E4
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x000000E4
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x000000B3
+#define DDRSS_CTL_228_DATA 0x000000B3
+#define DDRSS_CTL_229_DATA 0x000000B3
+#define DDRSS_CTL_230_DATA 0x000000B3
+#define DDRSS_CTL_231_DATA 0x000000B3
+#define DDRSS_CTL_232_DATA 0x000000B3
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x35000000
+#define DDRSS_CTL_257_DATA 0x35353535
+#define DDRSS_CTL_258_DATA 0x00002735
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x0000000F
+#define DDRSS_CTL_270_DATA 0x0000000F
+#define DDRSS_CTL_271_DATA 0x0000000F
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00001600
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000016
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x07D00040
+#define DDRSS_CTL_316_DATA 0x0002003C
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x003C07D0
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x00640064
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000101
+#define DDRSS_CTL_324_DATA 0x1FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0x3FFF2000
+#define DDRSS_CTL_327_DATA 0x000FFF00
+#define DDRSS_CTL_328_DATA 0x0B000001
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C03
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000001
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0F081B1B
+#define DDRSS_CTL_389_DATA 0x0009040F
+#define DDRSS_CTL_390_DATA 0x0B0D040F
+#define DDRSS_CTL_391_DATA 0x0B0D0406
+#define DDRSS_CTL_392_DATA 0x0D0D0906
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x08030801
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x000000B2
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000321
+#define DDRSS_CTL_403_DATA 0x000006F4
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x39200201
+#define DDRSS_CTL_406_DATA 0x00001E68
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x000088D4
+#define DDRSS_CTL_412_DATA 0x00013010
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x39200C09
+#define DDRSS_CTL_415_DATA 0x00001E68
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x000088D4
+#define DDRSS_CTL_421_DATA 0x00013010
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x000F0001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x000F0F00
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x0000170F
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010F00
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x01010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F12
+#define DDRSS_PI_101_DATA 0x08111413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x012C012C
+#define DDRSS_PI_178_DATA 0x00282801
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x00000060
+#define DDRSS_PI_181_DATA 0x00020060
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x00000013
+#define DDRSS_PI_188_DATA 0x00000059
+#define DDRSS_PI_189_DATA 0x000002F8
+#define DDRSS_PI_190_DATA 0x00000F34
+#define DDRSS_PI_191_DATA 0x000002F8
+#define DDRSS_PI_192_DATA 0x04000F34
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00290029
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001D0045
+#define DDRSS_PI_210_DATA 0x001D0045
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301F4
+#define DDRSS_PI_214_DATA 0x010001F4
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01F50100
+#define DDRSS_PI_217_DATA 0x010001F5
+#define DDRSS_PI_218_DATA 0x01F501F5
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1D12090D
+#define DDRSS_PI_223_DATA 0x1D120913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0022000D
+#define DDRSS_PI_231_DATA 0x002201F4
+#define DDRSS_PI_232_DATA 0x000001F4
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000301
+#define DDRSS_PI_236_DATA 0x00310204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000301
+#define DDRSS_PI_239_DATA 0x00310C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000301
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05040900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x00000315
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x2E100000
+#define DDRSS_PI_249_DATA 0x26150029
+#define DDRSS_PI_250_DATA 0x00007B66
+#define DDRSS_PI_251_DATA 0x2008005A
+#define DDRSS_PI_252_DATA 0x1C141C1E
+#define DDRSS_PI_253_DATA 0x2E100000
+#define DDRSS_PI_254_DATA 0x26150029
+#define DDRSS_PI_255_DATA 0x00007B66
+#define DDRSS_PI_256_DATA 0x2008005A
+#define DDRSS_PI_257_DATA 0x1C141C1E
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x000000B2
+#define DDRSS_PI_260_DATA 0x000006F4
+#define DDRSS_PI_261_DATA 0x00001E68
+#define DDRSS_PI_262_DATA 0x00013010
+#define DDRSS_PI_263_DATA 0x00001E68
+#define DDRSS_PI_264_DATA 0x00013010
+#define DDRSS_PI_265_DATA 0x03070014
+#define DDRSS_PI_266_DATA 0x03030307
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x00000014
+#define DDRSS_PI_276_DATA 0x00061A80
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000FA0
+#define DDRSS_PI_280_DATA 0x00000307
+#define DDRSS_PI_281_DATA 0x00061A80
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000FA0
+#define DDRSS_PI_285_DATA 0x01000307
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x07D00040
+#define DDRSS_PI_289_DATA 0x0001003C
+#define DDRSS_PI_290_DATA 0x07D00040
+#define DDRSS_PI_291_DATA 0x0000033C
+#define DDRSS_PI_292_DATA 0x00280064
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13100A18
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000084
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x000000B3
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x35000000
+#define DDRSS_PI_335_DATA 0x20160F27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x000000E4
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x000000B3
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x35000000
+#define DDRSS_PI_343_DATA 0x20160F27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x000000E4
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x000000B3
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x35000000
+#define DDRSS_PI_351_DATA 0x20160F27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000084
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x000000B3
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x35000000
+#define DDRSS_PI_359_DATA 0x20160F27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x000000E4
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x000000B3
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x35000000
+#define DDRSS_PI_367_DATA 0x20160F27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x000000E4
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x000000B3
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x35000000
+#define DDRSS_PI_375_DATA 0x20160F27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000084
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x000000B3
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x35000000
+#define DDRSS_PI_383_DATA 0x20160F27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x000000E4
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x000000B3
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x35000000
+#define DDRSS_PI_391_DATA 0x20160F27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x000000E4
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x000000B3
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x35000000
+#define DDRSS_PI_399_DATA 0x20160F27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000084
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x000000B3
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x35000000
+#define DDRSS_PI_407_DATA 0x20160F27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x000000E4
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x000000B3
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x35000000
+#define DDRSS_PI_415_DATA 0x20160F27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x000000E4
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x000000B3
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x35000000
+#define DDRSS_PI_423_DATA 0x20160F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000301
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071040
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02000010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06001
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C083E
+#define DDRSS_PHY_102_DATA 0x000F0C35
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x01330120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x00000300
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x04800480
+#define DDRSS_PHY_114_DATA 0x04800480
+#define DDRSS_PHY_115_DATA 0x04800480
+#define DDRSS_PHY_116_DATA 0x04800480
+#define DDRSS_PHY_117_DATA 0x00000480
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x011900A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000301
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071040
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02000010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06001
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C083E
+#define DDRSS_PHY_358_DATA 0x000F0C35
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x01330120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x00000300
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x04800480
+#define DDRSS_PHY_370_DATA 0x04800480
+#define DDRSS_PHY_371_DATA 0x04800480
+#define DDRSS_PHY_372_DATA 0x04800480
+#define DDRSS_PHY_373_DATA 0x00000480
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x011900A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000301
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071040
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02000010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06001
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C083E
+#define DDRSS_PHY_614_DATA 0x000F0C35
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x01330120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x00000300
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x04800480
+#define DDRSS_PHY_626_DATA 0x04800480
+#define DDRSS_PHY_627_DATA 0x04800480
+#define DDRSS_PHY_628_DATA 0x04800480
+#define DDRSS_PHY_629_DATA 0x00000480
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x011900A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000301
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071040
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02000010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06001
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C083E
+#define DDRSS_PHY_870_DATA 0x000F0C35
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x01330120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x00000300
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x04800480
+#define DDRSS_PHY_882_DATA 0x04800480
+#define DDRSS_PHY_883_DATA 0x04800480
+#define DDRSS_PHY_884_DATA 0x04800480
+#define DDRSS_PHY_885_DATA 0x00000480
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x011900A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1822_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x02010804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00004201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts
index aff83cd..5e5c2e3 100644
--- a/arch/arm/dts/k3-j722s-r5-evm.dts
+++ b/arch/arm/dts/k3-j722s-r5-evm.dts
@@ -7,7 +7,7 @@
#include "k3-j722s-evm.dts"
#include "k3-j722s-evm-u-boot.dtsi"
-#include "k3-j722s-ddr-lp4-50-3733.dtsi"
+#include "k3-j722s-ddr-lp4-50-4000.dtsi"
#include "k3-am62a-ddr.dtsi"
/ {
@@ -25,10 +25,11 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
- clocks = <&k3_clks 61 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <1200000000>;
+ assigned-clock-rates = <200000000>, <1400000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index d2c7522..0eeffa7 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -9,104 +9,4 @@
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-j784s4-evm-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 0>;
- assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- status = "okay";
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- status = "okay";
- bootph-pre-ram;
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>,
- <&secure_proxy_mcu 5>,
- <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
- bootph-pre-ram;
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- bootph-pre-ram;
- status = "okay";
-};
-
-&ospi0 {
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x0 0x50000000 0x0 0x8000000>;
-};
-
-&ospi1 {
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x0 0x58000000 0x0 0x8000000>;
-};
-
-&fss {
- /* enable ranges missing from the FSS node */
- ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
- <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j784s4-r5.dtsi"
diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi
new file mode 100644
index 0000000..0cd0ccc
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-r5.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ clock-names = "gtc", "core";
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&mcu_timer0 {
+ status = "okay";
+ clock-frequency = <250000000>;
+ bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>,
+ <&secure_proxy_mcu 5>,
+ <&secure_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&sms {
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ bootph-pre-ram;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&ospi0 {
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&ospi1 {
+ reg = <0x0 0x47050000 0x0 0x100>,
+ <0x0 0x58000000 0x0 0x8000000>;
+};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/dts/qemu-sbsa.dts b/arch/arm/dts/qemu-sbsa.dts
new file mode 100644
index 0000000..ed00e50
--- /dev/null
+++ b/arch/arm/dts/qemu-sbsa.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Devicetree with onboard devices for qemu_sbsa-ref for internal use only!
+ * DO NOT PASS TO THE OS!
+ *
+ * As QEMU provides only a minimal devicetree this one is merged with
+ * it and then fixed at runtime.
+ *
+ * Copyright 2024 9elements GmbH
+ */
+#include "configs/qemu-sbsa.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&intc>;
+ compatible = "linux,sbsa-ref";
+
+ binman: binman {
+ multiple-images;
+ };
+
+ cpus {
+ /* Filled by fdtdec_board_setup() */
+ };
+
+ memory {
+ /* Filled by fdtdec_board_setup() */
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cfi_flash {
+ compatible = "cfi-flash";
+ reg = /bits/ 64 <SBSA_FLASH_BASE_ADDR
+ SBSA_FLASH_LENGTH>;
+ status = "okay";
+ };
+
+ uart0 {
+ compatible = "arm,pl011";
+ status = "okay";
+ reg = /bits/ 64 <SBSA_UART_BASE_ADDR
+ SBSA_UART_LENGTH>;
+ };
+
+ ahci {
+ compatible = "generic-ahci";
+ status = "okay";
+ reg = /bits/ 64 <0x60100000 0x00010000>;
+ };
+
+ xhci {
+ compatible = "generic-xhci";
+ status = "okay";
+ reg = /bits/ 64 <0x60110000 0x00010000>;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ status = "okay";
+ reg = /bits/ 64 <0xf0000000 0x10000000>;
+ bus-range = <0 0xff>;
+ ranges = /bits/ 32 <0x01000000>,
+ /bits/ 64 <0
+ SBSA_PIO_BASE_ADDR
+ SBSA_PIO_LENGTH>,
+ /bits/ 32 <0x02000000>,
+ /bits/ 64 <SBSA_PCIE_MMIO_BASE_ADDR
+ SBSA_PCIE_MMIO_BASE_ADDR
+ SBSA_PCIE_MMIO_LENGTH>,
+ /bits/ 32 <0x43000000>,
+ /bits/ 64 <SBSA_PCIE_MMIO_HIGH_BASE_ADDR
+ SBSA_PCIE_MMIO_HIGH_BASE_ADDR
+ SBSA_PCIE_MMIO_HIGH_LENGTH>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ status = "okay";
+ interrupt-controller;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = /bits/ 64 <SBSA_GIC_DIST_BASE_ADDR SBSA_GIC_DIST_LENGTH>,
+ /bits/ 64 <SBSA_GIC_REDIST_BASE_ADDR SBSA_GIC_REDIST_LENGTH>,
+ /bits/ 64 <0 0>,
+ /bits/ 64 <SBSA_GIC_HBASE_ADDR SBSA_GIC_HBASE_LENGTH>,
+ /bits/ 64 <SBSA_GIC_VBASE_ADDR SBSA_GIC_VBASE_LENGTH>;
+ };
+
+ its {
+ compatible = "arm,gic-v3-its";
+ status = "disabled";
+ };
+};
+
+&binman {
+ secure-world {
+ filename = "secure-world.rom";
+ size = <SBSA_SECURE_FLASH_LENGTH>;
+
+ bl1 {
+ offset = <0x0>;
+ description = "ARM Trusted Firmware BL1";
+ filename = "bl1.bin";
+ type = "blob-ext";
+ };
+
+ fip {
+ offset = <0x12000>;
+ description = "ARM Trusted Firmware FIP";
+ filename = "fip.bin";
+ type = "blob-ext";
+ };
+ };
+
+ unsecure-world {
+ filename = "unsecure-world.rom";
+ size = <SBSA_FLASH_LENGTH>;
+
+ u-boot {
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index 39bb66c..a30adb0 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -6,6 +6,12 @@
#include "rk3328-u-boot.dtsi"
/ {
+ leds {
+ led-0 {
+ default-state = "on";
+ };
+ };
+
smbios {
compatible = "u-boot,sysinfo-smbios";
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index 037cec1..7438bec 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -15,13 +15,8 @@
};
&spi1 {
- status = "okay";
-
flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
bootph-pre-ram;
bootph-some-ram;
- spi-max-frequency = <10000000>;
};
};
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 5ec15a8..7a6af43 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -1,8 +1,22 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
* Copyright (c) 2023 Radxa Limited
*/
-#include "rk3399-rock-pi-4-u-boot.dtsi"
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ leds {
+ led-0 {
+ default-state = "on";
+ };
+
+ led-1 {
+ default-state = "on";
+ };
+ };
+};
&pcfg_pull_none_18ma {
bootph-pre-ram;
@@ -14,6 +28,12 @@
bootph-some-ram;
};
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+};
+
&spi1 {
status = "okay";
@@ -25,3 +45,7 @@
spi-max-frequency = <10000000>;
};
};
+
+&vdd_log {
+ regulator-init-microvolt = <950000>;
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index b3bfc77..4861574 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,14 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+/ {
+ leds {
+ led-0 {
+ default-state = "on";
+ };
+ };
+};
+
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi
new file mode 100644
index 0000000..fa3fbe6
--- /dev/null
+++ b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
+ };
+
+ /*
+ * Adding fixed regulator to work around driver regulator
+ * requirements. Note that the correct regulator is on by
+ * default at boot and that saradc regulator gets corrected
+ * when proper device-tree is loaded.
+ */
+ vcc_1v8_dummy: vcc-1v8-dummy {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_dummy";
+ status = "okay";
+ };
+};
+
+&saradc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ vref-supply = <&vcc_1v8_dummy>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
deleted file mode 100644
index c7e8498..0000000
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include "rk356x-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = &sdmmc0, &sdhci;
- };
-};
-
-&dsi_dphy0 {
- status = "okay";
-};
-
-&dsi0 {
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2m1_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pmucru {
- assigned-clocks = <&pmucru SCLK_32K_IOE>;
- assigned-clock-parents = <&pmucru CLK_RTC_32K>;
-};
-
-/*
- * We don't need the clocks, but if they are present they may cause
- * probing to fail so we remove them for U-Boot.
- */
-&rk817 {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ clocks;
- /delete-property/ clock-names;
-};
-
-&sdhci {
- pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
- <&emmc_datastrobe>, <&emmc_rstnout>;
- pinctrl-names = "default";
- bus-width = <8>;
- max-frequency = <200000000>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
deleted file mode 100644
index c393c8d..0000000
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-anbernic-rgxx3.dtsi"
-
-/ {
-
-/*
- * Note this is a pseudo-model that doesn't exist in mainline Linux.
- * This model is used for all RGXX3 devices and the board.c file will
- * set the correct dtb name for loading mainline Linux automatically.
- */
- model = "RGXX3";
- compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s",
- "anbernic,rg353m", "anbernic,rg353p",
- "anbernic,rg353ps", "anbernic,rg353v",
- "anbernic,rg353vs", "anbernic,rg503",
- "powkiddy,rgb10max3", "powkiddy,rgb30",
- "powkiddy,rk2023", "rockchip,rk3566";
-};
-
-&cru {
- assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
- <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
- assigned-clock-rates = <32768>, <1200000000>,
- <200000000>, <241500000>;
-};
diff --git a/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi
new file mode 100644
index 0000000..6e8307e
--- /dev/null
+++ b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index e0e501d..412f9e0 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,6 +5,14 @@
#include "rk356x-u-boot.dtsi"
+/ {
+ leds {
+ led-1 {
+ default-state = "on";
+ };
+ };
+};
+
&sdhci {
cap-mmc-highspeed;
};
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a4..efeab62 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -2,6 +2,29 @@
#include "rk356x-u-boot.dtsi"
+/ {
+ gpio-leds {
+ led-0 {
+ default-state = "on";
+ };
+
+ led-red {
+ default-state = "on";
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-green {
+ default-state = "on";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-blue {
+ default-state = "on";
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
&pcie3x1 {
pinctrl-0 = <&pcie30x1_reset_h>;
};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 0da3d9c..29c18f5 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,6 +6,14 @@
#include "rk356x-u-boot.dtsi"
+/ {
+ leds {
+ led-0 {
+ default-state = "on";
+ };
+ };
+};
+
&pcie3x2 {
pinctrl-0 = <&pcie3x2_reset_h>;
};
diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
index 9683856..8465dcd 100644
--- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
@@ -11,20 +11,14 @@
bootph-some-ram;
};
-&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspim1_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
+&saradc {
+ bootph-pre-ram;
+ vdd-microvolts = <1800000>;
+};
+&sfc {
flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
bootph-pre-ram;
bootph-some-ram;
- spi-max-frequency = <24000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
};
};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 4dd17ff..d51fbf5 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -3,31 +3,58 @@
* Copyright (c) 2023 Collabora Ltd.
*/
+#include <dt-bindings/usb/pd.h>
#include "rk3588-u-boot.dtsi"
+/ {
+ leds {
+ led_rgb_b {
+ default-state = "on";
+ };
+ };
+};
+
&fspim2_pins {
bootph-pre-ram;
bootph-some-ram;
};
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m1_xfer>;
+ status = "okay";
+
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "sink";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
+ <PDO_VAR(5000, 20000, 5000)>;
+ };
+ };
+};
+
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
};
&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspim2_pins>;
- status = "okay";
-
flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
bootph-pre-ram;
bootph-some-ram;
- spi-max-frequency = <24000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
};
};
diff --git a/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi b/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi
new file mode 100644
index 0000000..853ed58
--- /dev/null
+++ b/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
index efba0c3..a75ae29 100644
--- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -5,6 +5,14 @@
#include "rk3588s-u-boot.dtsi"
+/ {
+ leds {
+ io-led {
+ default-state = "on";
+ };
+ };
+};
+
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
deleted file mode 100644
index fc1c48a..0000000
--- a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
+++ /dev/null
@@ -1,383 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2024 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP13 variant:
- * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
- * DHCOR PCB number: 718-100 or newer
- * DHSBC PCB number: 719-100 or newer
- */
-
-/dts-v1/;
-
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp135.dtsi"
-#include "stm32mp13xf.dtsi"
-#include "stm32mp13xx-dhcor-som.dtsi"
-
-/ {
- model = "DH electronics STM32MP135F DHCOR DHSBC";
- compatible = "dh,stm32mp135f-dhcor-dhsbc",
- "dh,stm32mp135f-dhcor-som",
- "st,stm32mp135";
-
- aliases {
- ethernet0 = ð1;
- ethernet1 = ð2;
- serial2 = &usart1;
- serial3 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&adc_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
- vdda-supply = <&vdd_adc>;
- vref-supply = <&vdd_adc>;
- status = "okay";
-
- adc1: adc@0 {
- status = "okay";
-
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
- * Use arbitrary margin here (e.g. 5us).
- *
- * The pinmux pins must be set as ANALOG, use datasheet
- * DS13483 Table 7. STM32MP135C/F ball definitions to
- * find out which 'pin name' maps to which 'additional
- * functions', which lists the mapping between pin and
- * ADC channel. In this case, PA5 maps to ADC1_INP2 and
- * PF13 maps to ADC1_INP11 .
- */
- channel@2 {
- reg = <2>;
- st,min-sample-time-ns = <5000>;
- };
-
- channel@11 {
- reg = <11>;
- st,min-sample-time-ns = <5000>;
- };
-
- /* Expansion connector: INP12:pin29 */
- channel@12 {
- reg = <12>;
- st,min-sample-time-ns = <5000>;
- };
- };
-};
-
-ð1 {
- status = "okay";
- pinctrl-0 = <ð1_rgmii_pins_a>;
- pinctrl-1 = <ð1_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- st,ext-phyclk;
- nvmem-cells = <ðernet_mac1_address>;
- nvmem-cell-names = "mac-address";
-
- mdio1 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- ethphy1: ethernet-phy@1 {
- /* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpiog>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- reg = <1>;
- reset-assert-us = <15000>;
- reset-deassert-us = <55000>;
- reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-ð2 {
- status = "okay";
- pinctrl-0 = <ð2_rgmii_pins_a>;
- pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- phy-handle = <ðphy2>;
- st,ext-phyclk;
- nvmem-cells = <ðernet_mac2_address>;
- nvmem-cell-names = "mac-address";
-
- mdio1 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- ethphy2: ethernet-phy@1 {
- /* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpiog>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- reg = <1>;
- reset-assert-us = <15000>;
- reset-deassert-us = <55000>;
- reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gpioa {
- gpio-line-names = "", "", "", "",
- "", "DHSBC_USB_PWR_CC1", "", "",
- "", "", "", "DHSBC_nETH1_RST",
- "", "DHCOR_HW-CODING_0", "", "";
-};
-
-&gpiob {
- gpio-line-names = "", "", "", "",
- "", "", "", "DHCOR_BT_HOST_WAKE",
- "", "", "", "",
- "", "DHSBC_nTPM_CS", "", "";
-};
-
-&gpioc {
- gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiod {
- gpio-line-names = "", "", "", "",
- "", "DHCOR_RAM-CODING_0", "", "",
- "", "DHCOR_RAM-CODING_1", "", "",
- "", "", "", "";
-};
-
-&gpioe {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "DHSBC_nTPM_RST", "", "",
- "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
-};
-
-&gpiof {
- gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
- "", "", "", "",
- "", "", "", "",
- "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
-};
-
-&gpiog {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
- "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
-};
-
-&gpioi {
- gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
- "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
- "DHSBC_BOOT0", "DHSBC_BOOT1",
- "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
-};
-
-&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_sleep_pins_a>;
- i2c-scl-rising-time-ns = <96>;
- i2c-scl-falling-time-ns = <3>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_b>;
- pinctrl-1 = <&i2c5_sleep_pins_b>;
- i2c-scl-rising-time-ns = <96>;
- i2c-scl-falling-time-ns = <3>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>;
- status = "okay";
-};
-
-&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can2_pins_a>;
- pinctrl-1 = <&m_can2_sleep_pins_a>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
- status = "okay";
-};
-
-&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
- clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
- pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
-};
-
-&scmi_voltd {
- status = "disabled";
-};
-
-&spi2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi2_pins_a>;
- pinctrl-1 = <&spi2_sleep_pins_a>;
- cs-gpios = <&gpiob 13 0>;
- status = "okay";
-
- st33htph: tpm@0 {
- compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi3_pins_a>;
- pinctrl-1 = <&spi3_sleep_pins_a>;
- cs-gpios = <&gpiof 3 0>;
- status = "disabled";
-};
-
-&timers5 { /* Expansion connector: CH3:pin31 */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm5_pins_a>;
- pinctrl-1 = <&pwm5_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@4 {
- status = "okay";
- };
-};
-
-&timers13 { /* Expansion connector: CH1:pin32 */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm13_pins_a>;
- pinctrl-1 = <&pwm13_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@12 {
- status = "okay";
- };
-};
-
-&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-1 = <&usart1_sleep_pins_b>;
- pinctrl-2 = <&usart1_idle_pins_b>;
- status = "okay";
-};
-
-&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart2_pins_b>;
- pinctrl-1 = <&usart2_sleep_pins_b>;
- pinctrl-2 = <&usart2_idle_pins_b>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbh_ohci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "peripheral";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- usb33d-supply = <&usb33>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
- connector {
- compatible = "usb-a-connector";
- vbus-supply = <&vbus_sw>;
- };
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
- label = "Type-C";
- self-powered;
- type = "micro";
- };
-};
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index fe56f05..66d4c40 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -56,6 +56,24 @@
status = "okay";
};
};
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ bootph-pre-ram;
+ opp-650000000 {
+ bootph-pre-ram;
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ bootph-pre-ram;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ };
};
&bsec {
@@ -82,14 +100,10 @@
bootph-all;
};
-&cpu0_opp_table {
- bootph-pre-ram;
- opp-650000000 {
- bootph-pre-ram;
- };
- opp-800000000 {
- bootph-pre-ram;
- };
+&cpu0 {
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ operating-points-v2 = <&cpu0_opp_table>;
};
&gpioa {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi
rename to arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
rename to arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi
rename to arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
rename to arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
rename to arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi
rename to arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
deleted file mode 100644
index 90625bf..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-drc02.dtsi"
-
-/ {
- model = "DH Electronics STM32MP15xx DHCOM DRC02";
- compatible = "dh,stm32mp15xx-dhcom-drc02",
- "dh,stm32mp15xx-dhcom-som",
- "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
deleted file mode 100644
index 35b1034..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&adc {
- status = "disabled";
-};
-
-&dac {
- status = "disabled";
-};
-
-&gpiob {
- /*
- * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
- * GPIO line, however the STM32 UART driver assumes RX happens
- * during TX anyway and that it only controls drive enable DE
- * line. Hence, the RX is always enabled here.
- */
- rs485-rx-en-hog {
- gpio-hog;
- gpios = <8 0>;
- output-low;
- line-name = "rs485-rx-en";
- };
-};
-
-&gpiod {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-B", "",
- "", "", "", "DRC02-Out1",
- "DRC02-Out2", "", "", "";
-};
-
-&gpioi {
- gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
- "DHCOM-R", "DHCOM-M", "", "",
- "DRC02-In2", "", "", "",
- "", "", "", "";
-
- /*
- * NOTE: The USB Hub on the DRC02 needs a reset signal to be
- * pulled high in order to be detected by the USB Controller.
- * This signal should be handled by USB power sequencing in
- * order to reset the Hub when USB bus is powered down, but
- * so far there is no such functionality.
- */
- usb-hub-hog {
- gpio-hog;
- gpios = <2 0>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
-
-&i2c4 {
- touchscreen@49 {
- status = "disabled";
- };
-};
-
-&i2c5 { /* TP7/TP8 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&sdmmc3 {
- /*
- * On DRC02, the SoM does not have SDIO WiFi. The pins
- * are used for on-board microSD slot instead.
- */
- /delete-property/broken-cd;
- cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
- disable-wp;
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- cs-gpios = <&gpioz 3 0>;
- /* Use PIO for the display */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled"; /* Enable once there is display driver */
- /*
- * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
- * also connected to the display board connector.
- */
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/*
- * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
- * however the STM32MP1 pinmux cannot map them to UART4 .
- */
-
-&uart8 { /* RS485 */
- linux,rs485-enabled-at-boot-time;
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a>;
- rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
deleted file mode 100644
index b2e450a..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-pdk2.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
- compatible = "dh,stm32mp15xx-dhcom-pdk2",
- "dh,stm32mp15xx-dhcom-som",
- "st,stm32mp15x";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
deleted file mode 100644
index 5f586f0..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- clk_ext_audio_codec: clock-codec {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- display_bl: display-bl {
- compatible = "pwm-backlight";
- pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
- brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
- default-brightness-level = <8>;
- enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
- power-supply = <®_panel_bl>;
- status = "okay";
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- /*
- * The EXTi IRQ line 3 is shared with ethernet,
- * so mark this as polled GPIO key.
- */
- button-0 {
- label = "TA1-GPIO-A";
- linux,code = <KEY_A>;
- gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * The EXTi IRQ line 6 is shared with touchscreen,
- * so mark this as polled GPIO key.
- */
- button-1 {
- label = "TA2-GPIO-B";
- linux,code = <KEY_B>;
- gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * The EXTi IRQ line 0 is shared with PMIC,
- * so mark this as polled GPIO key.
- */
- button-2 {
- label = "TA3-GPIO-C";
- linux,code = <KEY_C>;
- gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-3 {
- label = "TA4-GPIO-D";
- linux,code = <KEY_D>;
- gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
- wakeup-source;
- };
- };
-
- led {
- compatible = "gpio-leds";
-
- led-0 {
- label = "green:led5";
- gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- status = "disabled";
- };
-
- led-1 {
- label = "green:led6";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-2 {
- label = "green:led7";
- gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-3 {
- label = "green:led8";
- gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- panel {
- compatible = "edt,etm0700g0edh6";
- backlight = <&display_bl>;
- power-supply = <®_panel_bl>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
- reg_panel_bl: regulator-panel-bl {
- compatible = "regulator-fixed";
- regulator-name = "panel_backlight";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <®_panel_supply>;
- };
-
- reg_panel_supply: regulator-panel-supply {
- compatible = "regulator-fixed";
- regulator-name = "panel_supply";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- };
-
- sound {
- compatible = "audio-graph-card";
- routing =
- "MIC_IN", "Capture",
- "Capture", "Mic Bias",
- "Playback", "HP_OUT";
- dais = <&sai2a_port &sai2b_port>;
- status = "okay";
- };
-};
-
-&cec {
- pinctrl-names = "default";
- pinctrl-0 = <&cec_pins_a>;
- status = "okay";
-};
-
-&i2c2 { /* Header X22 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&i2c5 { /* Header X21 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- clocks = <&clk_ext_audio_codec>;
- VDDA-supply = <&v3v3>;
- VDDIO-supply = <&vdd>;
-
- sgtl5000_port: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sgtl5000_tx_endpoint: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sai2a_endpoint>;
- frame-master = <&sgtl5000_tx_endpoint>;
- bitclock-master = <&sgtl5000_tx_endpoint>;
- };
-
- sgtl5000_rx_endpoint: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sai2b_endpoint>;
- frame-master = <&sgtl5000_rx_endpoint>;
- bitclock-master = <&sgtl5000_rx_endpoint>;
- };
- };
-
- };
-
- touchscreen@38 {
- compatible = "edt,edt-ft5406";
- reg = <0x38>;
- interrupt-parent = <&gpioc>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
- };
-};
-
-<dc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-1 = <<dc_sleep_pins_b>;
- status = "okay";
-
- port {
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>;
- pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>;
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&sgtl5000_tx_endpoint>;
- format = "i2s";
- mclk-fs = <512>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <16>;
- };
- };
- };
-
- sai2b: audio-controller@4400b024 {
- dma-names = "rx";
- st,sync = <&sai2a 2>;
- clocks = <&rcc SAI2_K>, <&sai2a>;
- clock-names = "sai_ck", "MCLK";
- status = "okay";
-
- sai2b_port: port {
- sai2b_endpoint: endpoint {
- remote-endpoint = <&sgtl5000_rx_endpoint>;
- format = "i2s";
- mclk-fs = <512>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <16>;
- };
- };
- };
-};
-
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
- pwm2: pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-names = "default";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
- uart-has-rtscts;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phy-names = "usb2-phy";
- phys = <&usbphyc_port1 0>;
- vbus-supply = <&vbus_otg>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
deleted file mode 100644
index 3e90810..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcom-som.dtsi"
-#include "stm32mp15xx-dhcom-picoitx.dtsi"
-
-/ {
- model = "DH Electronics STM32MP15xx DHCOM PicoITX";
- compatible = "dh,stm32mp15xx-dhcom-picoitx",
- "dh,stm32mp15xx-dhcom-som",
- "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
deleted file mode 100644
index abc5953..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- led {
- compatible = "gpio-leds";
-
- led-0 {
- label = "yellow:led";
- gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-};
-
-&adc {
- status = "disabled";
-};
-
-&dac {
- status = "disabled";
-};
-
-&fmc {
- status = "disabled";
-};
-
-&gpioa {
- /*
- * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
- * port power. This signal should be handled by USB power sequencing
- * in order to turn on port power when USB bus is powered up, but so
- * far there is no such functionality.
- */
- usb-port-power-hog {
- gpio-hog;
- gpios = <13 0>;
- output-low;
- line-name = "usb-port-power";
- };
-};
-
-&gpioc {
- gpio-line-names = "", "", "", "",
- "", "", "PicoITX-In1", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiod {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-B", "",
- "", "", "", "PicoITX-Out1",
- "PicoITX-Out2", "", "", "";
-};
-
-&gpiog {
- gpio-line-names = "PicoITX-In2", "", "", "",
- "", "", "", "",
- "DHCOM-L", "", "", "",
- "", "", "", "";
-};
-
-&i2c2 { /* On board-to-board connector (optional) */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c5 { /* On board-to-board connector */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&ksz8851 {
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbh_ohci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phy-names = "usb2-phy";
- phys = <&usbphyc_port1 0>;
- vbus-supply = <&vbus_otg>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
deleted file mode 100644
index d3b85a8..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
+++ /dev/null
@@ -1,544 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
- */
-
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- aliases {
- ethernet0 = ðernet0;
- ethernet1 = &ksz8851;
- rtc0 = &hwrtc;
- rtc1 = &rtc;
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x40000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- ethernet_vio: vioregulator {
- compatible = "regulator-fixed";
- regulator-name = "vio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd>;
- };
-};
-
-&adc {
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
-
- adc1: adc@0 {
- st,min-sample-time-nsecs = <5000>;
- st,adc-channels = <0>;
- status = "okay";
- };
-
- adc2: adc@100 {
- st,adc-channels = <1>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-};
-
-&crc1 {
- status = "okay";
-};
-
-&dac {
- pinctrl-names = "default";
- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
- vref-supply = <&vdda>;
- status = "okay";
-
- dac1: dac@1 {
- status = "okay";
- };
- dac2: dac@2 {
- status = "okay";
- };
-};
-
-&dts {
- status = "okay";
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>;
- pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rmii";
- max-speed = <100>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy0: ethernet-phy@1 {
- reg = <1>;
- /* LAN8710Ai */
- compatible = "ethernet-phy-id0007.c0f0",
- "ethernet-phy-ieee802.3-c22";
- clocks = <&rcc CK_MCO2>;
- reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
- reset-assert-us = <500>;
- reset-deassert-us = <500>;
- smsc,disable-energy-detect;
- interrupt-parent = <&gpioi>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_b>;
- pinctrl-1 = <&fmc_sleep_pins_b>;
- status = "okay";
-
- ksz8851: ethernet@1,0 {
- compatible = "micrel,ks8851-mll";
- reg = <1 0x0 0x2>, <1 0x2 0x20000>;
- interrupt-parent = <&gpioc>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- bank-width = <2>;
-
- /* Timing values are in nS */
- st,fmc2-ebi-cs-mux-enable;
- st,fmc2-ebi-cs-transaction-type = <4>;
- st,fmc2-ebi-cs-buswidth = <16>;
- st,fmc2-ebi-cs-address-setup-ns = <5>;
- st,fmc2-ebi-cs-address-hold-ns = <5>;
- st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
- st,fmc2-ebi-cs-data-setup-ns = <45>;
- st,fmc2-ebi-cs-data-hold-ns = <1>;
- st,fmc2-ebi-cs-write-address-setup-ns = <5>;
- st,fmc2-ebi-cs-write-address-hold-ns = <5>;
- st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
- st,fmc2-ebi-cs-write-data-setup-ns = <45>;
- st,fmc2-ebi-cs-write-data-hold-ns = <1>;
- };
-};
-
-&gpioa {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-K", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiob {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "DHCOM-Q", "", "", "",
- "", "", "", "";
-};
-
-&gpioc {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-E", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiod {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-B", "",
- "", "", "", "DHCOM-F",
- "DHCOM-D", "", "", "";
-};
-
-&gpioe {
- gpio-line-names = "", "", "", "",
- "", "", "DHCOM-P", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiof {
- gpio-line-names = "", "", "", "DHCOM-A",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiog {
- gpio-line-names = "DHCOM-C", "", "", "",
- "", "", "", "",
- "DHCOM-L", "", "", "",
- "", "", "", "";
-};
-
-&gpioh {
- gpio-line-names = "", "", "", "",
- "", "", "", "DHCOM-N",
- "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
- "DHCOM-T", "", "DHCOM-S", "";
-};
-
-&gpioi {
- gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I",
- "DHCOM-R", "DHCOM-M", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- hwrtc: rtc@32 {
- compatible = "microcrystal,rv8803";
- reg = <0x32>;
- };
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-always-on;
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-
- touchscreen@49 {
- compatible = "ti,tsc2004";
- reg = <0x49>;
- vio-supply = <&v3v3>;
- interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a
- &qspi_bk1_pins_a
- &qspi_cs1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a
- &qspi_bk1_sleep_pins_a
- &qspi_cs1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&rcc {
- /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
- clocks = <&rcc CK_MCO2>;
- clock-names = "ETH_RX_CLK/ETH_REF_CLK";
-
- /*
- * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
- * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
- * so that MCO2 behaves as a divider for the ETHRX clock here.
- */
- assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
- assigned-clock-parents = <&rcc PLL4_P>;
- assigned-clock-rates = <50000000>, <100000000>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep", "init";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>;
- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- st,cmd-gpios = <&gpiod 2 0>;
- st,ck-gpios = <&gpioc 12 0>;
- st,ckin-gpios = <&gpioe 4 0>;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- status = "okay";
-};
-
-&sdmmc1_b4_pins_a {
- /*
- * SD bus pull-up resistors:
- * - optional on SoMs with SD voltage translator
- * - mandatory on SoMs without SD voltage translator
- */
- pins1 {
- bias-pull-up;
- };
- pins2 {
- bias-pull-up;
- };
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index d7b78cd..dd67e96 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -8,6 +8,7 @@
#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-dhsom-u-boot.dtsi"
/ {
aliases {
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
deleted file mode 100644
index dd8fcec..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-avenger96.dtsi"
-
-/ {
- model = "Arrow Electronics STM32MP15xx Avenger96 board";
- compatible = "arrow,stm32mp15xx-avenger96",
- "dh,stm32mp15xx-dhcor-som",
- "st,stm32mp15x";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
deleted file mode 100644
index 61e17f4..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ /dev/null
@@ -1,437 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
-#include "stm32mp15xx-dhcor-io1v8.dtsi"
-
-/ {
- aliases {
- ethernet0 = ðernet0;
- mmc0 = &sdmmc1;
- serial0 = &uart4;
- serial1 = &uart7;
- serial2 = &usart2;
- spi0 = &qspi;
- };
-
- /* XTal Q1 */
- cec_clock: clk-cec-fixed {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7513_out>;
- };
- };
- };
-
- led {
- compatible = "gpio-leds";
- led1 {
- label = "green:user0";
- gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led2 {
- label = "green:user1";
- gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led3 {
- label = "green:user2";
- gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
-
- led4 {
- label = "green:user3";
- gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- default-state = "off";
- panic-indicator;
- };
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "STM32MP1-AV96-HDMI";
- dais = <&sai2a_port>;
- status = "okay";
- };
-
- wlan_pwr: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_b>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
-
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-
- adc2: adc@100 {
- st,adc-channels = <0 1 2>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_c>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
-
- phy0: ethernet-phy@7 {
- reg = <7>;
-
- rxc-skew-ps = <1500>;
- rxdv-skew-ps = <540>;
- rxd0-skew-ps = <420>;
- rxd1-skew-ps = <420>;
- rxd2-skew-ps = <420>;
- rxd3-skew-ps = <420>;
-
- txc-skew-ps = <1440>;
- txen-skew-ps = <540>;
- txd0-skew-ps = <420>;
- txd1-skew-ps = <420>;
- txd2-skew-ps = <420>;
- txd3-skew-ps = <420>;
- };
- };
-};
-
-&gpioa {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "", "", "AV96-K",
- "AV96-I", "", "AV96-A", "";
-};
-
-&gpiob {
- gpio-line-names = "", "", "", "",
- "", "AV96-J", "", "",
- "", "", "", "AV96-B",
- "", "AV96-L", "", "";
-};
-
-&gpioc {
- gpio-line-names = "", "", "", "AV96-C",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiod {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "AV96-D", "", "", "",
- "", "", "AV96-E", "AV96-F";
-};
-
-&gpiof {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "AV96-G", "AV96-H", "", "";
-};
-
-&i2c1 { /* X6 I2C1 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c2 { /* X6 I2C2 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_c>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c4 {
- hdmi-transmitter@3d {
- compatible = "adi,adv7513";
- reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
- reg-names = "main", "edid", "cec", "packet";
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- avdd-supply = <&v3v3>;
- dvdd-supply = <&v3v3>;
- pvdd-supply = <&v3v3>;
- dvdd-3v-supply = <&v3v3>;
- bgvdd-supply = <&v3v3>;
-
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpiog>;
-
- status = "okay";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7513_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7513_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7513_i2s0: endpoint {
- remote-endpoint = <&sai2a_endpoint>;
- };
- };
- };
- };
-};
-
-<dc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_d>;
- pinctrl-1 = <<dc_sleep_pins_d>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&adv7513_in>;
- };
- };
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_c>;
- pinctrl-1 = <&sai2a_sleep_pins_c>;
- clock-names = "pclk", "x8k", "x11k";
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&adv7513_i2s0>;
- format = "i2s";
- mclk-fs = <256>;
- };
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd_io>;
- status = "okay";
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_b>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
- broken-cd;
- non-removable;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&wlan_pwr>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- brcmf: bcrmf@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- cs-gpios = <&gpioi 0 0>;
- status = "disabled";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- uart-has-rtscts;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/* Bluetooth */
-&usart2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-1 = <&usart2_sleep_pins_a>;
- st,hw-flow-ctrl;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <3000000>;
- shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phy-names = "usb2-phy";
- phys = <&usbphyc_port1 0>;
- status = "okay";
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
deleted file mode 100644
index c1f99c1..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-drc-compact.dtsi"
-
-/ {
- model = "DH electronics STM32MP15xx DHCOR DRC Compact";
- compatible = "dh,stm32mp15xx-dhcor-drc-compact",
- "dh,stm32mp15xx-dhcor-som",
- "st,stm32mp1xx";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi
deleted file mode 100644
index bedccf0..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi
+++ /dev/null
@@ -1,326 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-
-/ {
- aliases {
- ethernet0 = ðernet0;
- ethernet1 = &ksz8851;
- mmc0 = &sdmmc1;
- rtc0 = &hwrtc;
- rtc1 = &rtc;
- serial0 = &uart4;
- serial1 = &uart8;
- serial2 = &usart3;
- serial3 = &uart5;
- spi0 = &qspi;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- led {
- compatible = "gpio-leds";
- led1 {
- label = "yellow:user0";
- gpios = <&gpioz 6 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- label = "red:user1";
- gpios = <&gpioz 3 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- ethernet_vio: vioregulator {
- compatible = "regulator-fixed";
- regulator-name = "vio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd>;
- };
-};
-
-&adc { /* X11 ADC inputs */
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_b>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
-
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-
- adc2: adc@100 {
- st,adc-channels = <0 1 2>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_c>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- reset-post-delay-us = <1000>;
-
- phy0: ethernet-phy@7 {
- reg = <7>;
-
- rxc-skew-ps = <1500>;
- rxdv-skew-ps = <540>;
- rxd0-skew-ps = <420>;
- rxd1-skew-ps = <420>;
- rxd2-skew-ps = <420>;
- rxd3-skew-ps = <420>;
-
- txc-skew-ps = <1440>;
- txen-skew-ps = <540>;
- txd0-skew-ps = <420>;
- txd1-skew-ps = <420>;
- txd2-skew-ps = <420>;
- txd3-skew-ps = <420>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_b>;
- pinctrl-1 = <&fmc_sleep_pins_b>;
- status = "okay";
-
- ksz8851: ethernet@1,0 {
- compatible = "micrel,ks8851-mll";
- reg = <1 0x0 0x2>, <1 0x2 0x20000>;
- interrupt-parent = <&gpioc>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- bank-width = <2>;
-
- /* Timing values are in nS */
- st,fmc2-ebi-cs-mux-enable;
- st,fmc2-ebi-cs-transaction-type = <4>;
- st,fmc2-ebi-cs-buswidth = <16>;
- st,fmc2-ebi-cs-address-setup-ns = <5>;
- st,fmc2-ebi-cs-address-hold-ns = <5>;
- st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
- st,fmc2-ebi-cs-data-setup-ns = <45>;
- st,fmc2-ebi-cs-data-hold-ns = <1>;
- st,fmc2-ebi-cs-write-address-setup-ns = <5>;
- st,fmc2-ebi-cs-write-address-hold-ns = <5>;
- st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
- st,fmc2-ebi-cs-write-data-setup-ns = <45>;
- st,fmc2-ebi-cs-write-data-hold-ns = <1>;
- };
-};
-
-&gpioa {
- gpio-line-names = "", "", "", "",
- "DRCC-VAR2", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpioe {
- gpio-line-names = "", "", "", "",
- "", "DRCC-GPIO0", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpiog {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "DRCC-GPIO5", "", "", "";
-};
-
-&gpioh {
- gpio-line-names = "", "", "", "DRCC-HW2",
- "DRCC-GPIO4", "", "", "",
- "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1",
- "DRCC-VAR0", "", "", "DRCC-GPIO6";
-};
-
-&gpioi {
- gpio-line-names = "", "", "", "",
- "", "", "", "DRCC-GPIO2",
- "", "DRCC-GPIO1", "", "",
- "", "", "", "";
-};
-
-&i2c1 { /* X11 I2C1 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c4 {
- hwrtc: rtc@32 {
- compatible = "microcrystal,rv8803";
- reg = <0x32>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
-
-&sdmmc1 { /* MicroSD */
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&vdd>;
- vqmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&sdmmc2 { /* eMMC */
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&sdmmc3 { /* SDIO Wi-Fi */
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- bus-width = <4>;
- mmc-ddr-3_3v;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&spi2 { /* X11 SPI */
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_b>;
- cs-gpios = <&gpioi 0 0>;
- status = "disabled";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&uart4 {
- label = "UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_d>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart5 { /* X11 UART */
- label = "X11-UART5";
- pinctrl-names = "default";
- pinctrl-0 = <&uart5_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart8 {
- label = "RS485-1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
- uart-has-rtscts;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usart3 { /* RS485 or RS232 */
- label = "RS485-2";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&usart3_pins_e>;
- pinctrl-1 = <&usart3_sleep_pins_e>;
- uart-has-rtscts;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbh_ohci {
- phys = <&usbphyc_port0>;
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phy-names = "usb2-phy";
- phys = <&usbphyc_port1 0>;
- vbus-supply = <&vbus_otg>;
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
- connector {
- compatible = "usb-a-connector";
- vbus-supply = <&vbus_sw>;
- };
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
deleted file mode 100644
index e209178..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-/ {
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
- compatible = "regulator-fixed";
- regulator-name = "buck-io";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd>;
- };
-};
-
-&vdd {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd_io>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
deleted file mode 100644
index f36eec1..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- */
-
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- aliases {
- spi0 = &qspi;
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x40000000>;
- };
-};
-
-&crc1 {
- status = "okay";
-};
-
-&dts {
- status = "okay";
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
-
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- regulator-enable-ramp-delay = <300000>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge = <1>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
- interrupt-names = "onkey-falling", "onkey-rising";
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a
- &qspi_bk1_pins_a
- &qspi_cs1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a
- &qspi_bk1_sleep_pins_a
- &qspi_cs1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <50000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
deleted file mode 100644
index 5fdd762..0000000
--- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- */
-/dts-v1/;
-
-#include "stm32mp151.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-
-/ {
- model = "DH electronics STM32MP15xx DHCOR Testbench";
- compatible = "dh,stm32mp15xx-dhcor-testbench",
- "dh,stm32mp15xx-dhcor-som",
- "st,stm32mp1xx";
-
- aliases {
- ethernet0 = ðernet0;
- mmc0 = &sdmmc1;
- mmc1 = &sdmmc2;
- serial0 = &uart4;
- serial1 = &uart7;
- spi0 = &qspi;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_b>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
-
- adc1: adc@0 {
- st,adc-channels = <0 1 6>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-
- adc2: adc@100 {
- st,adc-channels = <0 1 2>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_c>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
-
- phy0: ethernet-phy@7 {
- reg = <7>;
-
- rxc-skew-ps = <1500>;
- rxdv-skew-ps = <540>;
- rxd0-skew-ps = <420>;
- rxd1-skew-ps = <420>;
- rxd2-skew-ps = <420>;
- rxd3-skew-ps = <420>;
-
- txc-skew-ps = <1440>;
- txen-skew-ps = <540>;
- txd0-skew-ps = <420>;
- txd1-skew-ps = <420>;
- txd2-skew-ps = <420>;
- txd3-skew-ps = <420>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart7 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- uart-has-rtscts;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phy-names = "usb2-phy";
- phys = <&usbphyc_port1 0>;
- status = "okay";
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
-
-&vdd {
- /delete-property/ regulator-always-on;
- regulator-min-microvolt = <1200000>;
-};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index ba84db6..0843934 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -12,6 +12,7 @@
#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-dhsom-u-boot.dtsi"
/ {
bootph-all;
diff --git a/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi
new file mode 100644
index 0000000..386c605
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+&binman {
+ u-boot {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "U-Boot mainline";
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm";
+ compression = "none";
+ description = "U-Boot (32-bit)";
+ entry = <CONFIG_TEXT_BASE>;
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index b98ed16..179060c 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -40,6 +40,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
reg = <0x0 0xf1040000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index e6a5c2b..ffcc333 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -40,6 +40,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
reg = <0x0 0xf1050000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts
index e200fb6..20e4e29 100644
--- a/arch/arm/dts/versal-net-mini-emmc.dts
+++ b/arch/arm/dts/versal-net-mini-emmc.dts
@@ -54,6 +54,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
reg = <0 0xf1050000 0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts
index 9365efb..f98f95a 100644
--- a/arch/arm/dts/versal-net-mini.dts
+++ b/arch/arm/dts/versal-net-mini.dts
@@ -60,7 +60,6 @@
clock-names = "uartclk", "apb_pclk";
clocks = <&clk1>, <&clk1>;
clock = <1000000>;
- current-speed = <115200>;
skip-init;
};
};
diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts
index 8d00737..8031488 100644
--- a/arch/arm/dts/zynq-dlc20-rev1.0.dts
+++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts
@@ -83,6 +83,9 @@
bootph-all;
status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */
non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <4>;
};
diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
index 96d2937..a8f3450 100644
--- a/arch/arm/dts/zynq-minized.dts
+++ b/arch/arm/dts/zynq-minized.dts
@@ -92,6 +92,9 @@
&sdhci1 {
status = "okay";
non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <4>;
max-frequency = <12000000>;
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 293d8e9..d540f33 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -60,6 +60,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index c439f77..6ef8b14 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -68,6 +68,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index d6cd193..c597adb 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -88,6 +88,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>; /* FIXME tap delay */
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 902fdd4..eefe5ab 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -84,6 +84,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>; /* FIXME tap delay */
};
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index f3994bc..7ea4eab 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -84,6 +84,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>; /* FIXME tap delay */
};
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index cf22197..ad4b3c5 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -52,6 +52,9 @@
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 4c9f56a..fd421b4 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -52,6 +52,9 @@
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index ae52e8e..fce0d8d 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -60,6 +60,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
@@ -155,7 +158,7 @@
reg = <0>;
/* On connector J98 */
reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x7>;
regulator-name = "reg_vcc_fmc";
regulator-min-microvolt = <1800000>;
@@ -163,15 +166,15 @@
/* enable-gpio = <&gpio0 23 0x4>; optional */
};
reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x8>;
};
reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x9>;
};
reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0xa>;
};
reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
@@ -212,75 +215,75 @@
reg = <2>;
/* On connector J104 */
reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0xd>;
};
reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0xe>;
};
reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0xf>;
};
reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x10>;
};
reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x11>;
};
reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x12>;
};
reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x13>;
};
reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x14>;
};
reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x15>;
};
reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x16>;
};
reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x17>;
};
reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x19>;
};
reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1a>;
};
reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1b>;
};
reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1c>;
};
reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1d>;
};
reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1e>;
};
reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
- compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */
reg = <0x1f>;
};
};
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 1fcb5bf..1af3f64 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -288,6 +288,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
new file mode 100644
index 0000000..8412aec
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VM-P-M1369-00
+ *
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vm-p-m1369-revA",
+ "xlnx,zynqmp-sc-vm-p-m1369", "xlnx,zynqmp";
+
+ ina226-u19 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>;
+ };
+ ina226-u287 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
+ };
+ ina226-u288 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>;
+ };
+ ina226-u289 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
+ };
+ ina226-u290 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>;
+ };
+ ina226-u291 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
+ };
+ ina226-u292 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
+ };
+ ina226-u293 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
+ };
+ ina226-u294 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
+ };
+ ina226-u295 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>;
+ };
+ ina226-u298 {
+ compatible = "iio-hwmon";
+ io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>;
+ };
+ ina226-u296 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>;
+ };
+ ina226-u299 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>;
+ };
+ ina226-u300 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>;
+ };
+ ina226-u301 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>;
+ };
+ ina226-u297 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>;
+ };
+};
+
+&i2c1 { /* i2c_main bus */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
+
+ /* i2c_main_1 - u72 - j108 - disable translation, add 8 */
+ /* J133 - OE for u91@55 + 8 - 161,132813MHz - QSFP56G_0 */
+ qsfp56g_0_clk: clock-controller@5d {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5d>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_0_clk";
+ };
+
+ /* J134 - OE for u92@57 + 8 - 322,265625MHz - QSFP56G_1 */
+ qsfp56g_1_clk: clock-controller@5f {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5f>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_1_clk";
+ };
+
+ /* i2c_main_2 - u74 - j110 - disable translation, add 9 */
+ /* J210 - OE for u164@50 + 9 - 320MHz - CH2_LP5 */
+ ch2_lpddr5_refclk: clock-controller@59 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x59>;
+ #clock-cells = <0>;
+ clock-output-names = "ch2_lpddr5_refclk";
+ };
+
+ /* i2c_main_3 - u76 - j112 - disable translation, add 6 */
+ /* J231 - OE for u165@50 + 6 - 320MHz - _RDIMM */
+ ddr5_dimm1_refclk: clock-controller@56 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x56>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr5_udimm_refclk";
+ };
+
+ /* i2c_main_4 - u73 - j109 - disable translation, add 5 */
+ /* J117 - OE for u82@50 + 5 - 33,3333MHz - PS_REFCLK */
+ ps_refclk: clock-controller@55 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x55>;
+ #clock-cells = <0>;
+ clock-output-names = "ps_refclk";
+ };
+
+ /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
+ /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
+ /* this should be SW controlable too */
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* u134 tps544b25 but connected to J178 connector */
+ /* u48/IMx3112/0x77 - 1:2 multiplexer - also accessed from Versal NET */
+ /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
+ /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
+ /* Access to i2c_pmc bus via u49 with OE j100 or via SYSCTLR_I2C_PMC_EN */
+
+ /* ina226_pmbus - J103 - disable INA226_PMBUS */
+ vcc_soc_ina: power-monitor@40 { /* u19 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x40>;
+ shunt-resistor = <1000>; /* R222 */
+ };
+
+ vcc_ram_ina: power-monitor@41 { /* u287 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x41>;
+ shunt-resistor = <1000>; /* R32981 */
+ };
+
+ vcc_pslp_ina: power-monitor@42 { /* u288 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x42>;
+ shunt-resistor = <1000>; /* R32984 */
+ };
+
+ vccaux_ina: power-monitor@43 { /* u289 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x43>;
+ shunt-resistor = <1000>; /* R32987 */
+ };
+
+ vccaux_pmc_ina: power-monitor@44 { /* u290 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x44>;
+ shunt-resistor = <1000>; /* R32990 */
+ };
+
+ vcco_500_ina: power-monitor@45 { /* u291 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x45>;
+ shunt-resistor = <1000>; /* R32993 */
+ };
+
+ vcco_501_ina: power-monitor@46 { /* u292 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x46>;
+ shunt-resistor = <1000>; /* R32996 */
+ };
+
+ vcco_502_ina: power-monitor@47 { /* u293 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x47>;
+ shunt-resistor = <1000>; /* R32999 */
+ };
+
+ vcco_503_ina: power-monitor@48 { /* u294 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x48>;
+ shunt-resistor = <1000>; /* R33002 */
+ };
+
+ vcc_ddr5_rdimm_ina: power-monitor@49 { /* u295 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x49>;
+ shunt-resistor = <1000>; /* R33005 */
+ };
+
+ lp5_1v0_ina: power-monitor@4a { /* u298 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4a>;
+ shunt-resistor = <1000>; /* R33014 */
+ };
+
+ vcc_fmc_ina: power-monitor@4b { /* u296 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4b>;
+ shunt-resistor = <1000>; /* R33008 */
+ };
+
+ gtm_avcc_ina: power-monitor@4c { /* u299 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4c>;
+ shunt-resistor = <1000>; /* R33017 */
+ };
+
+ gtm_avtt_ina: power-monitor@4d { /* u300 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4d>;
+ shunt-resistor = <1000>; /* R33020 */
+ };
+
+ gtm_avccaux_ina: power-monitor@4e { /* u301 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4e>;
+ shunt-resistor = <1000>; /* R33023 */
+ };
+
+ vcc_mipi_ina: power-monitor@4f { /* u297 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4f>;
+ shunt-resistor = <1000>; /* R33011 */
+ };
+
+ /* pmbus - j105 - disable main PMBUS - also going to j102 connector */
+ vcc_pslp: regulator@15 { /* u24 */
+ compatible = "ti,tps546b24a";
+ reg = <0x15>;
+ };
+
+ vccaux_pmc: regulator@17 { /* u26 */
+ compatible = "ti,tps546b24a";
+ reg = <0x17>;
+ };
+
+ vcco_500: regulator@18 { /* u27 */
+ compatible = "ti,tps546b24a";
+ reg = <0x18>;
+ };
+
+ vcco_501: regulator@19 { /* u28 */
+ compatible = "ti,tps546b24a";
+ reg = <0x19>;
+ };
+
+ vcco_502: regulator@1a { /* u29 */
+ compatible = "ti,tps546b24a";
+ reg = <0x1a>;
+ };
+
+ vcco_503: regulator@1b { /* u30 */
+ compatible = "ti,tps546b24a";
+ reg = <0x1b>;
+ };
+
+ vcc_ddr5_rdimm: regulator@1c { /* u31 */
+ compatible = "ti,tps546b24a";
+ reg = <0x1c>;
+ };
+
+ gtm_avcc: regulator@22 { /* u37 */
+ compatible = "ti,tps546b24a";
+ reg = <0x22>;
+ };
+
+ gtm_avtt: regulator@20 { /* u38 */
+ compatible = "ti,tps546b24a";
+ reg = <0x20>;
+ };
+
+ gtm_avccaux: regulator@21 { /* u39 */
+ compatible = "ti,tps546b24a";
+ reg = <0x21>;
+ };
+
+ vccint_gt: regulator@2a { /* u44 */
+ compatible = "ti,tps546b24a";
+ reg = <0x2a>;
+ };
+
+ util_1v8: regulator@2b { /* u1839 */
+ compatible = "ti,tps546b24a";
+ reg = <0x2b>;
+ };
+
+ vcc_pmc: regulator@2c { /* u46 */
+ compatible = "ti,tps546b24a";
+ reg = <0x2c>;
+ };
+
+ /* pmbus via U62 as ext_pmbus - disable via j104 */
+ vccint: regulator@10 { /* u18 */
+ compatible = "ti,tps546b24";
+ reg = <0x10>;
+ };
+
+ vccsoc: regulator@11 { /* u20 */
+ compatible = "ti,tps546b24";
+ reg = <0x11>;
+ };
+
+ vcc_io: regulator@12 { /* u21 */
+ compatible = "ti,tps546b24";
+ reg = <0x12>;
+ };
+
+ vcc_psfp: regulator@13 { /* u22 */
+ compatible = "ti,tps546b24";
+ reg = <0x13>;
+ };
+
+ vcc_ram: regulator@14 { /* u23 */
+ compatible = "ti,tps546b24";
+ reg = <0x14>;
+ };
+
+ vccaux: regulator@16 { /* u25 */
+ compatible = "ti,tps546b24";
+ reg = <0x16>;
+ };
+
+ lp5_1v0: regulator@1d { /* u32 */
+ compatible = "ti,tps546b24";
+ reg = <0x1d>;
+ };
+
+ vcc_fmc: regulator@1e { /* u33 */
+ compatible = "ti,tps546b24";
+ reg = <0x1e>;
+ };
+
+ lp5_vdd1: regulator@25 { /* u40 */
+ compatible = "ti,tps546b24";
+ reg = <0x25>;
+ };
+
+ lp5_vdd2: regulator@26 { /* u41 */
+ compatible = "ti,tps546b24";
+ reg = <0x26>;
+ };
+
+ lp5_vddq: regulator@27 { /* u42 */
+ compatible = "ti,tps546b24";
+ reg = <0x27>;
+ };
+
+ vcco_hdio: regulator@29 { /* u43 */
+ compatible = "ti,tps546b24";
+ reg = <0x29>;
+ };
+
+ vcc_mipi: regulator@1f { /* u47 */
+ compatible = "ti,tps546b24";
+ reg = <0x1f>;
+ };
+
+ /* connected via J425 connector
+ ucd90320: power-sequencer@73 { // u16
+ compatible = "ti,ucd90320";
+ reg = <0x73>;
+ };*/
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index d95a05e..8056f6b 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -247,6 +247,9 @@
pinctrl-0 = <&pinctrl_sdhci0_default>;
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
assigned-clock-rates = <187498123>;
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 0d96c6f..2037686 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -93,6 +93,9 @@
status = "okay";
non-removable;
disable-wp; /* We don't have a write-protect detection */
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index 4768fac..f281c7f 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -105,6 +105,9 @@
status = "okay";
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index c594506..c905136 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -509,6 +509,9 @@
xlnx,mio-bank = <0>;
non-removable;
disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
cap-power-off-card;
mmc-pwrseq = <&sdio_pwrseq>;
vqmmc-supply = <&wmmcsdio_fixed>;
diff --git a/arch/arm/include/asm/acpi_table.h b/arch/arm/include/asm/acpi_table.h
index e69de29..7386f55 100644
--- a/arch/arm/include/asm/acpi_table.h
+++ b/arch/arm/include/asm/acpi_table.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+#ifndef __ACPI__
+#ifndef __ASSEMBLY__
+
+#include <acpi/acpi_table.h>
+
+/**
+ * acpi_write_madt_gicc() - Write out a MADT GICC sub-table
+ *
+ * Write out the GIC CPU Interface sub-table.
+ *
+ * @gicc: Pointer to place to put the sub-table
+ * @cpu_num: GIC's CPU Interface Number
+ * @perf_gsiv: The GSIV used for Performance Monitoring Interrupts
+ * @phys_base: Address at which the processor can access this
+ * GIC CPU Interface
+ * @gicv: Address of the GIC virtual CPU interface registers
+ * @gich: Address of the GIC virtual interface control block
+ * registers
+ * @vgic_maint_irq: GSIV for Virtual GIC maintenance interrupt
+ * @gicr_base: Physical address of the associated Redistributor
+ * @mpidr: MPIDR as defined by ARM architecture
+ * @efficiency: Describes the relative power efficiency
+ */
+void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,
+ uint perf_gsiv, ulong phys_base, ulong gicv,
+ ulong gich, uint vgic_maint_irq, u64 gicr_base,
+ ulong mpidr, uint efficiency);
+
+/**
+ * acpi_write_madt_gicd() - Write out a MADT GICD sub-table
+ *
+ * Write out the GIC Distributor sub-table.
+ *
+ * @gicd: Pointer to place to put the sub-table
+ * @gic_id: This GIC Distributor's hardware ID
+ * @phys_base: The 64-bit physical address for this Distributor
+ * @gic_version: GIC version
+ */
+void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,
+ ulong phys_base, uint gic_version);
+
+/**
+ * acpi_write_madt_gicr() - Write out a MADT GICR sub-table
+ *
+ * Write out the GIC Redistributor sub-table.
+ *
+ * @gicr: Pointer to place to put the sub-table
+ * @discovery_range_base_address: Physical address of a page range
+ * containing all GIC Redistributors
+ * @discovery_range_length: Length of the GIC Redistributor
+ * Discovery page range
+ */
+void acpi_write_madt_gicr(struct acpi_madt_gicr *gicr,
+ u64 discovery_range_base_address,
+ u32 discovery_range_length);
+
+/**
+ * acpi_write_madt_its() - Write out a MADT ITS sub-table
+ *
+ * Write out the GIC Interrupt Translation Service sub-table.
+ *
+ * @its: Pointer to place to put the sub-table
+ * @its_id: Uniqueue GIC ITS ID
+ * @physical_base_address: Physical address for the Interrupt
+ * Translation Service
+ */
+void acpi_write_madt_its(struct acpi_madt_its *its,
+ u32 its_id,
+ u64 physical_base_address);
+
+/**
+ * acpi_pptt_add_proc() - Write out a PPTT processor sub-table
+ *
+ * Write out the Processor Properties Topology Table processor sub-table.
+ *
+ * @ctx: ACPI context pointer
+ * @flags: Processor Structure Flags
+ * @parent: Reference to parent processor
+ * @proc_id: ACPI processor ID as defined in MADT
+ * @num_resources: Number of resource structure references
+ * @resource_list: References to other PPTT structures
+ * Return: offset from start of PPTT in bytes
+ */
+int acpi_pptt_add_proc(struct acpi_ctx *ctx, const u32 flags, const u32 parent,
+ const u32 proc_id, const u32 num_resources,
+ const u32 *resource_list);
+
+/**
+ * acpi_pptt_add_cache() - Write out a PPTT cache sub-table
+ *
+ * Write out the Processor Properties Topology Table cache sub-table.
+ *
+ * @ctx: ACPI context pointer
+ * @flags: Cache Structure Flags
+ * @next_cache_level: Reference to next level of cache
+ * @size: Size of the cache in bytes
+ * @sets: Number of sets in the cache
+ * @assoc: Integer number of ways
+ * @attributes: Allocation type, Cache type, policy
+ * @line_size: Line size in bytes
+ * Return: offset from start of PPTT in bytes
+ */
+int acpi_pptt_add_cache(struct acpi_ctx *ctx, const u32 flags,
+ const u32 next_cache_level, const u32 size,
+ const u32 sets, const u8 assoc, const u8 attributes,
+ const u16 line_size);
+
+/* Multi-processor Startup for ARM Platforms */
+/**
+ * struct acpi_pp_page - MP startup handshake mailbox
+ *
+ * Defines a 4096 byte memory region that is used for starting secondary CPUs on
+ * an Arm system that follows the "Multi-processor Startup for ARM Platforms" spec.
+ *
+ * @cpu_id: MPIDR as returned by the Multiprocessor Affinity Register.
+ * On 32bit Arm systems the upper bits are unused.
+ * @jumping_address: On 32bit Arm systems the address must be below 4 GiB
+ * @os_reserved: Reserved for OS use. Firmware must not access this memory.
+ * @spinning_code: Reserved for firmware use. OS must not access this memory.
+ * The spinning code will be installed by firmware and the secondary
+ * CPUs will enter it before the control is handed over to the OS.
+ */
+struct acpi_pp_page {
+ u64 cpu_id;
+ u64 jumping_address;
+ u8 os_reserved[2032];
+ u8 spinning_code[2048];
+} __packed;
+
+#endif /* !__ASSEMBLY__ */
+#endif /* !__ACPI__ */
+
+/* Multi-processor Startup for ARM Platforms defines */
+#define ACPI_PP_CPU_ID_INVALID 0xffffffff
+#define ACPI_PP_JMP_ADR_INVALID 0
+#define ACPI_PP_PAGE_SIZE 4096
+#define ACPI_PP_CPU_ID_OFFSET 0
+#define ACPI_PP_CPU_JMP_OFFSET 8
+#define ACPI_PP_CPU_CODE_OFFSET 2048
+#define ACPI_PP_VERSION 1
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index f1b7526..95a8cc1 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -15,7 +15,7 @@
#define MCU_BOOTROM_BASE_ADDR 0x007E0000
-#define GPIO1_BASE_ADDR 0X30200000
+#define GPIO1_BASE_ADDR 0x30200000
#define GPIO2_BASE_ADDR 0x30210000
#define GPIO3_BASE_ADDR 0x30220000
#define GPIO4_BASE_ADDR 0x30230000
diff --git a/arch/arm/include/asm/arch-qemu-sbsa/boot0.h b/arch/arm/include/asm/arch-qemu-sbsa/boot0.h
new file mode 100644
index 0000000..4a1a254
--- /dev/null
+++ b/arch/arm/include/asm/arch-qemu-sbsa/boot0.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sbsa-ref starts U-Boot in XIP memory. Need to relocate U-Boot
+ * to DRAM which is already up. Instead of using SPL this simple loader
+ * is being used.
+ */
+relocate_check:
+ /* x0 contains the pointer to FDT provided by ATF */
+ adr x1, _start /* x1 <- Runtime value of _start */
+ ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
+ subs x9, x1, x2 /* x9 <- Run-vs-link offset */
+ beq reset
+
+ adrp x1, __image_copy_start /* x2 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x2 <- address bits [11:00] */
+ adrp x3, __image_copy_end /* x3 <- address bits [31:12] */
+ add x3, x3, :lo12:__image_copy_end /* x3 <- address bits [11:00] */
+ add x3, x3, #0x100000 /* 1 MiB for the DTB found at _end */
+
+copy_loop:
+ ldp x10, x11, [x1], #16 /* copy from source address [x1] */
+ stp x10, x11, [x2], #16 /* copy to target address [x2] */
+ cmp x1, x3 /* until source end address [x3] */
+ b.lo copy_loop
+
+ isb
+ ldr x2, _TEXT_BASE /* x2 <- Linked value of _start */
+ br x2 /* Jump to linked address */
+ /* Never reaches this point */
+1:
+ wfi
+ b 1b
+
+relocate_done:
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index b66277f..504459b 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -464,5 +464,12 @@
UART0_CLK_SEL_UART0_FRAC,
UART0_DIVNP5_SHIFT = 0,
UART0_DIVNP5_MASK = 0x1f << UART0_DIVNP5_SHIFT,
+
+ /* CRU_PMU_CLKSEL5_CON */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << CLK_UART_FRAC_NUMERATOR_SHIFT,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK =
+ 0xffff << CLK_UART_FRAC_DENOMINATOR_SHIFT,
};
#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2237d7d..52f6c9b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -394,6 +394,15 @@
#define wfi()
#endif
+static inline unsigned long read_mpidr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+ return val;
+}
+
static inline unsigned long get_cpsr(void)
{
unsigned long cpsr;
@@ -656,22 +665,6 @@
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-/**
- * noncached_init() - Initialize non-cached memory region
- *
- * Initialize non-cached memory area. This memory region will be typically
- * located right below the malloc() area and mapped uncached in the MMU.
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int noncached_init(void);
-
-phys_addr_t noncached_alloc(size_t size, size_t align);
-#endif /* CONFIG_SYS_NONCACHED_MEMORY */
-
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h
index a775386..11a7384 100644
--- a/arch/arm/include/asm/ti-common/ti-aemif.h
+++ b/arch/arm/include/asm/ti-common/ti-aemif.h
@@ -16,6 +16,7 @@
#define AEMIF_PRESERVE -1
struct aemif_config {
+ void *base;
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f254186..1c95dd6 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -68,6 +68,7 @@
ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
obj-y += gic_64.o
endif
+obj-$(CONFIG_DRIVER_GICV2) += gic-v2.o
obj-$(CONFIG_GIC_V3_ITS) += gic-v3-its.o
obj-y += interrupts_64.o
else
@@ -86,6 +87,7 @@
obj-$(CONFIG_DEBUG_LL) += debug.o
obj-$(CONFIG_BLOBLIST) += xferlist.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
# For EABI conformant tool chains, provide eabi_compat()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
diff --git a/arch/arm/lib/acpi_table.c b/arch/arm/lib/acpi_table.c
new file mode 100644
index 0000000..f760b7f
--- /dev/null
+++ b/arch/arm/lib/acpi_table.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on acpi.c from coreboot
+ *
+ * Copyright (C) 2024 9elements GmbH
+ */
+
+#define LOG_CATEGORY LOGC_ACPI
+
+#include <bloblist.h>
+#include <cpu_func.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <string.h>
+#include <tables_csum.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_table.h>
+#include <asm-generic/io.h>
+#include <dm/acpi.h>
+#include <dm/uclass.h>
+#include <linux/log2.h>
+#include <linux/sizes.h>
+
+/* defined in assembly file */
+/**
+ * acpi_pp_code_size - Spinloop code size *
+ */
+extern u16 acpi_pp_code_size;
+
+/**
+ * acpi_pp_tables - Start of ACPI PP tables.
+ */
+extern ulong acpi_pp_tables;
+
+/**
+ * acpi_pp_etables - End of ACPI PP tables.
+ */
+extern ulong acpi_pp_etables;
+
+/**
+ * acpi_pp_code_start() - Spinloop code
+ *
+ * Architectural spinloop code to be installed in each parking protocol
+ * page. The spinloop code must be less than 2048 bytes.
+ *
+ * The spinloop code will be entered after calling
+ * acpi_parking_protocol_install().
+ *
+ */
+void acpi_pp_code_start(void);
+
+void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,
+ uint perf_gsiv, ulong phys_base, ulong gicv,
+ ulong gich, uint vgic_maint_irq, u64 gicr_base,
+ ulong mpidr, uint efficiency)
+{
+ memset(gicc, '\0', sizeof(struct acpi_madt_gicc));
+ gicc->type = ACPI_APIC_GICC;
+ gicc->length = sizeof(struct acpi_madt_gicc);
+ gicc->cpu_if_num = cpu_num;
+ gicc->processor_id = cpu_num;
+ gicc->flags = ACPI_MADTF_ENABLED;
+ gicc->perf_gsiv = perf_gsiv;
+ gicc->phys_base = phys_base;
+ gicc->gicv = gicv;
+ gicc->gich = gich;
+ gicc->vgic_maint_irq = vgic_maint_irq;
+ gicc->gicr_base = gicr_base;
+ gicc->mpidr = mpidr;
+ gicc->efficiency = efficiency;
+}
+
+void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,
+ ulong phys_base, uint gic_version)
+{
+ memset(gicd, '\0', sizeof(struct acpi_madt_gicd));
+ gicd->type = ACPI_APIC_GICD;
+ gicd->length = sizeof(struct acpi_madt_gicd);
+ gicd->gic_id = gic_id;
+ gicd->phys_base = phys_base;
+ gicd->gic_version = gic_version;
+}
+
+void acpi_write_madt_gicr(struct acpi_madt_gicr *gicr,
+ u64 discovery_range_base_address,
+ u32 discovery_range_length)
+{
+ memset(gicr, '\0', sizeof(struct acpi_madt_gicr));
+ gicr->type = ACPI_APIC_GICR;
+ gicr->length = sizeof(struct acpi_madt_gicr);
+ gicr->discovery_range_base_address = discovery_range_base_address;
+ gicr->discovery_range_length = discovery_range_length;
+}
+
+void acpi_write_madt_its(struct acpi_madt_its *its,
+ u32 its_id,
+ u64 physical_base_address)
+{
+ memset(its, '\0', sizeof(struct acpi_madt_its));
+ its->type = ACPI_APIC_ITS;
+ its->length = sizeof(struct acpi_madt_its);
+ its->gic_its_id = its_id;
+ its->physical_base_address = physical_base_address;
+}
+
+int acpi_pptt_add_proc(struct acpi_ctx *ctx, const u32 flags, const u32 parent,
+ const u32 proc_id, const u32 num_resources,
+ const u32 *resource_list)
+{
+ struct acpi_pptt_proc *proc = ctx->current;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+ proc->hdr.type = ACPI_PPTT_TYPE_PROC;
+ proc->flags = flags;
+ proc->parent = parent;
+ proc->proc_id = proc_id;
+ proc->num_resources = num_resources;
+ proc->hdr.length = sizeof(struct acpi_pptt_proc) +
+ sizeof(u32) * num_resources;
+
+ if (resource_list)
+ memcpy(proc + 1, resource_list, sizeof(u32) * num_resources);
+
+ acpi_inc(ctx, proc->hdr.length);
+
+ return offset;
+}
+
+int acpi_pptt_add_cache(struct acpi_ctx *ctx, const u32 flags,
+ const u32 next_cache_level, const u32 size,
+ const u32 sets, const u8 assoc, const u8 attributes,
+ const u16 line_size)
+{
+ struct acpi_pptt_cache *cache = ctx->current;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+ cache->hdr.type = ACPI_PPTT_TYPE_CACHE;
+ cache->hdr.length = sizeof(struct acpi_pptt_cache);
+ cache->flags = flags;
+ cache->next_cache_level = next_cache_level;
+ cache->size = size;
+ cache->sets = sets;
+ cache->assoc = assoc;
+ cache->attributes = attributes;
+ cache->line_size = line_size;
+ acpi_inc(ctx, cache->hdr.length);
+
+ return offset;
+}
+
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
+{
+ uclass_probe_all(UCLASS_CPU);
+ uclass_probe_all(UCLASS_IRQ);
+
+ /* All SoCs must use the driver model */
+ acpi_fill_madt_subtbl(ctx);
+
+ return ctx->current;
+}
+
+/**
+ * acpi_write_pp_setup_one_page() - Fill out one page used by the PP
+ *
+ * Fill out the struct acpi_pp_page to contain the spin-loop
+ * code and the mailbox area. After this function the page is ready for
+ * the secondary core's to enter the spin-loop code.
+ *
+ * @page: Pointer to current parking protocol page
+ * @gicc: Pointer to corresponding GICC sub-table
+ */
+static void acpi_write_pp_setup_one_page(struct acpi_pp_page *page,
+ struct acpi_madt_gicc *gicc)
+{
+ void *reloc;
+
+ /* Update GICC. Mark parking protocol as available. */
+ gicc->parking_proto = ACPI_PP_VERSION;
+ gicc->parked_addr = virt_to_phys(page);
+
+ /* Prepare parking protocol page */
+ memset(page, '\0', sizeof(struct acpi_pp_page));
+
+ /* Init mailbox. Set MPIDR so core's will find their page. */
+ page->cpu_id = gicc->mpidr;
+ page->jumping_address = ACPI_PP_JMP_ADR_INVALID;
+
+ /* Relocate spinning code */
+ reloc = &page->spinning_code[0];
+
+ log_debug("Relocating spin table from %lx to %lx (size %x)\n",
+ (ulong)&acpi_pp_code_start, (ulong)reloc, acpi_pp_code_size);
+ memcpy(reloc, &acpi_pp_code_start, acpi_pp_code_size);
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_range((unsigned long)page,
+ (unsigned long)(page + 1));
+}
+
+void acpi_write_park(struct acpi_madt *madt)
+{
+ struct acpi_pp_page *start, *page;
+ struct acpi_madt_gicc *gicc;
+ int ret, i, ncpus = 0;
+
+ /*
+ * According to the "Multi-processor Startup for ARM Platforms":
+ * - Every CPU as specified by MADT GICC has it's own 4K page
+ * - Every page is divided into two sections: OS and FW reserved
+ * - Memory occupied by "Parking Protocol" must be marked 'Reserved'
+ * - Spinloop code should reside in FW reserved 2048 bytes
+ * - Spinloop code will check the mailbox in OS reserved area
+ */
+
+ if (acpi_pp_code_size > sizeof(page->spinning_code)) {
+ log_err("Spinning code too big to fit: %d\n",
+ acpi_pp_code_size);
+ return;
+ }
+
+ /* Count all MADT GICCs including BSP */
+ for (i = sizeof(struct acpi_madt); i < madt->header.length;
+ i += gicc->length) {
+ gicc = (struct acpi_madt_gicc *)((void *)madt + i);
+ if (gicc->type != ACPI_APIC_GICC)
+ continue;
+ ncpus++;
+ }
+ log_debug("Found %#x GICCs in MADT\n", ncpus);
+
+ /* Allocate pages linearly due to assembly code requirements */
+ start = bloblist_add(BLOBLISTT_ACPI_PP, ACPI_PP_PAGE_SIZE * ncpus,
+ ilog2(SZ_4K));
+ if (!start) {
+ log_err("Failed to allocate memory for ACPI-parking-protocol pages\n");
+ return;
+ }
+ log_debug("Allocated parking protocol at %p\n", start);
+ page = start;
+
+ if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+ /* Default mapping is 'BOOT CODE'. Mark as reserved instead. */
+ ret = efi_add_memory_map((u64)(uintptr_t)start,
+ ncpus * ACPI_PP_PAGE_SIZE,
+ EFI_RESERVED_MEMORY_TYPE);
+
+ if (ret)
+ log_err("Reserved memory mapping failed addr %p size %x\n",
+ start, ncpus * ACPI_PP_PAGE_SIZE);
+ }
+
+ /* Prepare the parking protocol pages */
+ for (i = sizeof(struct acpi_madt); i < madt->header.length;
+ i += gicc->length) {
+ gicc = (struct acpi_madt_gicc *)((void *)madt + i);
+ if (gicc->type != ACPI_APIC_GICC)
+ continue;
+
+ acpi_write_pp_setup_one_page(page++, gicc);
+ }
+
+ acpi_pp_etables = virt_to_phys(start) +
+ ACPI_PP_PAGE_SIZE * ncpus;
+ acpi_pp_tables = virt_to_phys(start);
+
+ /* Make sure other cores see written value in memory */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_all();
+
+ /* Send an event to wake up the secondary CPU. */
+ asm("dsb ishst\n"
+ "sev");
+}
diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c
new file mode 100644
index 0000000..b70434a
--- /dev/null
+++ b/arch/arm/lib/gic-v2.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+#include <dm.h>
+#include <irq.h>
+#include <asm/gic.h>
+#include <asm/acpi_table.h>
+#include <cpu_func.h>
+#include <dm/acpi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gicv2_fill_madt() - Fill out the body of the MADT
+ *
+ * Write GICD and GICR tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicd *gicd;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GICD address\n", __func__);
+ return -EINVAL;
+ }
+
+ gicd = ctx->current;
+ acpi_write_madt_gicd(gicd, dev_seq(dev), addr, 2);
+ acpi_inc(ctx, gicd->length);
+
+ return 0;
+}
+
+static struct acpi_ops gic_v2_acpi_ops = {
+ .fill_madt = acpi_gicv2_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v2_ids[] = {
+ { .compatible = "arm,arm11mp-gic" },
+ { .compatible = "arm,cortex-a15-gic" },
+ { .compatible = "arm,cortex-a7-gic" },
+ { .compatible = "arm,cortex-a5-gic" },
+ { .compatible = "arm,cortex-a9-gic" },
+ { .compatible = "arm,eb11mp-gic" },
+ { .compatible = "arm,gic-400" },
+ { .compatible = "arm,pl390" },
+ { .compatible = "arm,tc11mp-gic" },
+ { .compatible = "qcom,msm-8660-qgic" },
+ { .compatible = "qcom,msm-qgic2" },
+ {}
+};
+
+static int arm_gic_v2_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 3) {
+ log_debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ /* ARM Generic Interrupt Controller v1 and v2 */
+ if (args->args[0] == GIC_SPI)
+ irq->id = args->args[1] + 32;
+ else
+ irq->id = args->args[1] + 16;
+
+ irq->flags = args->args[2];
+
+ return 0;
+}
+
+static const struct irq_ops arm_gic_v2_ops = {
+ .of_xlate = arm_gic_v2_of_xlate,
+};
+
+U_BOOT_DRIVER(arm_gic_v2) = {
+ .name = "gic-v2",
+ .id = UCLASS_IRQ,
+ .of_match = gic_v2_ids,
+ .ops = &arm_gic_v2_ops,
+ ACPI_OPS_PTR(&gic_v2_acpi_ops)
+};
diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c
index 2cc0a32..51cc239 100644
--- a/arch/arm/lib/gic-v3-its.c
+++ b/arch/arm/lib/gic-v3-its.c
@@ -4,9 +4,13 @@
*/
#include <cpu_func.h>
#include <dm.h>
+#include <irq.h>
+#include <asm/acpi_table.h>
#include <asm/gic.h>
#include <asm/gic-v3.h>
#include <asm/io.h>
+#include <dm/acpi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <linux/sizes.h>
@@ -26,19 +30,21 @@
struct gic_v3_its_priv {
ulong gicd_base;
ulong gicr_base;
+ ulong gicr_length;
};
static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
int ret;
ret = uclass_get_device_by_driver(UCLASS_IRQ,
- DM_DRIVER_GET(arm_gic_v3_its), &dev);
+ DM_DRIVER_GET(arm_gic_v3), &dev);
if (ret) {
pr_err("%s: failed to get %s irq device\n", __func__,
- DM_DRIVER_GET(arm_gic_v3_its)->name);
+ DM_DRIVER_GET(arm_gic_v3)->name);
return ret;
}
@@ -49,12 +55,13 @@
}
priv->gicd_base = addr;
- addr = dev_read_addr_index(dev, 1);
+ addr = dev_read_addr_size_index(dev, 1, &size);
if (addr == FDT_ADDR_T_NONE) {
pr_err("%s: failed to get GICR address\n", __func__);
return -EINVAL;
}
priv->gicr_base = addr;
+ priv->gicr_length = size;
return 0;
}
@@ -158,13 +165,117 @@
return 0;
}
-static const struct udevice_id gic_v3_its_ids[] = {
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gicv3_fill_madt() - Fill out the body of the MADT
+ *
+ * Write GICD and GICR tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicd *gicd;
+ struct acpi_madt_gicr *gicr;
+
+ struct gic_v3_its_priv priv;
+
+ if (gic_v3_its_get_gic_addr(&priv))
+ return -EINVAL;
+
+ gicd = ctx->current;
+ acpi_write_madt_gicd(gicd, dev_seq(dev), priv.gicd_base, 3);
+ acpi_inc(ctx, gicd->length);
+
+ gicr = ctx->current;
+ acpi_write_madt_gicr(gicr, priv.gicr_base, priv.gicr_length);
+ acpi_inc(ctx, gicr->length);
+
+ return 0;
+}
+
+struct acpi_ops gic_v3_acpi_ops = {
+ .fill_madt = acpi_gicv3_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v3_ids[] = {
{ .compatible = "arm,gic-v3" },
{}
};
-U_BOOT_DRIVER(arm_gic_v3_its) = {
+static int arm_gic_v3_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
+{
+ if (args->args_count < 3) {
+ log_debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] == GIC_SPI)
+ irq->id = args->args[1] + 32;
+ else
+ irq->id = args->args[1] + 16;
+
+ irq->flags = args->args[2];
+
+ return 0;
+}
+
+static const struct irq_ops arm_gic_v3_ops = {
+ .of_xlate = arm_gic_v3_of_xlate,
+};
+
+U_BOOT_DRIVER(arm_gic_v3) = {
.name = "gic-v3",
.id = UCLASS_IRQ,
+ .of_match = gic_v3_ids,
+ .ops = &arm_gic_v3_ops,
+ ACPI_OPS_PTR(&gic_v3_acpi_ops)
+};
+
+#ifdef CONFIG_ACPIGEN
+/**
+ * acpi_gic_its_fill_madt() - Fill out the body of the MADT
+ *
+ * Write ITS tables based on collected devicetree data.
+ *
+ * @dev: Device to write ACPI tables for
+ * @ctx: ACPI context to write MADT sub-tables to
+ * Return: 0 if OK
+ */
+static int acpi_gic_its_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_its *its;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s: failed to get GIC ITS address\n", __func__);
+ return -EINVAL;
+ }
+
+ its = ctx->current;
+ acpi_write_madt_its(its, dev_seq(dev), addr);
+ acpi_inc(ctx, its->length);
+
+ return 0;
+}
+
+struct acpi_ops gic_v3_its_acpi_ops = {
+ .fill_madt = acpi_gic_its_fill_madt,
+};
+#endif
+
+static const struct udevice_id gic_v3_its_ids[] = {
+ { .compatible = "arm,gic-v3-its" },
+ {}
+};
+
+U_BOOT_DRIVER(arm_gic_v3_its) = {
+ .name = "gic-v3-its",
+ .id = UCLASS_IRQ,
.of_match = gic_v3_its_ids,
+ ACPI_OPS_PTR(&gic_v3_its_acpi_ops)
};
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index c1d9273..09b8f05 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -11,6 +11,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#define GCK_CSS_SLOW_CLK 0
#define GCK_CSS_MAIN_CLK 1
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index b3287ce..d9303e8 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -24,7 +24,13 @@
bool "Broadcom BCM2837 SoC 64-bit support"
depends on ARCH_BCM283X
select BCM2837
+ select DRIVER_GICV2
select ARM64
+ select CPU_ARMV8
+ select ARMV8_MULTIENTRY if GENERATE_ACPI_TABLE
+ select BLOBLIST if GENERATE_ACPI_TABLE
+ select BLOBLIST_ALLOC if GENERATE_ACPI_TABLE
+ select BLOBLIST_TABLES if GENERATE_ACPI_TABLE
config BCM2711
bool "Broadcom BCM2711 SoC support"
@@ -42,11 +48,16 @@
bool "Broadcom BCM2711 SoC 64-bit support"
depends on ARCH_BCM283X
select BCM2711
+ select DRIVER_GICV2
select ARM64
+ select CPU_ARMV8
+ select ARMV8_MULTIENTRY if GENERATE_ACPI_TABLE
+ select BLOBLIST if GENERATE_ACPI_TABLE
+ select BLOBLIST_ALLOC if GENERATE_ACPI_TABLE
+ select BLOBLIST_TABLES if GENERATE_ACPI_TABLE
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
-
choice
prompt "Broadcom BCM283X board select"
optional
@@ -210,6 +221,9 @@
config SYS_CONFIG_NAME
default "rpi"
+config BLOBLIST_SIZE_RELOC
+ default 0x20000
+
source "board/raspberrypi/rpi/Kconfig"
endmenu
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index 7cd0688..38e3203 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -4,3 +4,7 @@
obj-$(CONFIG_BCM2835) += lowlevel_init.o
obj-y += init.o reset.o mbox.o msg.o phys2bus.o
+
+ifeq ($(CONFIG_GENERATE_ACPI_TABLE),y)
+obj-$(CONFIG_BCM2711) += bcm2711_acpi.o
+endif
\ No newline at end of file
diff --git a/arch/arm/mach-bcm283x/bcm2711_acpi.c b/arch/arm/mach-bcm283x/bcm2711_acpi.c
new file mode 100644
index 0000000..79b2833
--- /dev/null
+++ b/arch/arm/mach-bcm283x/bcm2711_acpi.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024 9elements GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include <string.h>
+#include <tables_csum.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_table.h>
+#include <asm/armv8/sec_firmware.h>
+#include <asm/arch/acpi/bcm2711.h>
+#include <dm/uclass.h>
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->flags = ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0;
+
+ if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) &&
+ sec_firmware_support_psci_version() != PSCI_INVALID_VER)
+ fadt->arm_boot_arch = ACPI_ARM_PSCI_COMPLIANT;
+}
+
+#define L3_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_UNIFIED << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L3_SIZE 0x100000
+#define L3_SETS 0x400
+#define L3_WAYS 0x10
+
+#define L1D_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_DATA << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1D_SIZE 0x8000
+#define L1D_SETS 0x100
+#define L1D_WAYS 2
+
+#define L1I_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_INSTR << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1I_SIZE 0xc000
+#define L1I_SETS 0x100
+#define L1I_WAYS 3
+
+static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ int cluster_offset, l3_offset;
+ u32 offsets[2];
+
+ header = ctx->current;
+ ctx->tab_start = ctx->current;
+
+ memset(header, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(header, "PPTT");
+ header->revision = acpi_get_table_revision(ACPITAB_PPTT);
+ acpi_inc(ctx, sizeof(*header));
+
+ l3_offset = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L3_SIZE,
+ L3_SETS, L3_WAYS, L3_ATTRIBUTES, 64);
+
+ cluster_offset = acpi_pptt_add_proc(ctx, ACPI_PPTT_PHYSICAL_PACKAGE |
+ ACPI_PPTT_CHILDREN_IDENTICAL,
+ 0, 0, 1, &l3_offset);
+
+ offsets[0] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L1D_SIZE,
+ L1D_SETS, L1D_WAYS, L1D_ATTRIBUTES, 64);
+
+ offsets[1] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_BUT_WRITE_POL, 0,
+ L1I_SIZE, L1I_SETS, L1I_WAYS,
+ L1I_ATTRIBUTES, 64);
+
+ for (int i = 0; i < uclass_id_count(UCLASS_CPU); i++) {
+ acpi_pptt_add_proc(ctx, ACPI_PPTT_CHILDREN_IDENTICAL |
+ ACPI_PPTT_NODE_IS_LEAF |
+ ACPI_PPTT_PROC_ID_VALID,
+ cluster_offset, i, 2, offsets);
+ }
+
+ header->length = ctx->current - ctx->tab_start;
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_inc(ctx, header->length);
+ acpi_add_table(ctx, header);
+
+ return 0;
+};
+
+ACPI_WRITER(5pptt, "PPTT", acpi_write_pptt, 0);
+
+static int rpi_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_gtdt *gtdt;
+
+ gtdt = ctx->current;
+ header = >dt->header;
+
+ memset(gtdt, '\0', sizeof(struct acpi_gtdt));
+
+ acpi_fill_header(header, "GTDT");
+ header->length = sizeof(struct acpi_gtdt);
+ header->revision = acpi_get_table_revision(ACPITAB_GTDT);
+
+ gtdt->cnt_ctrl_base = BCM2711_ARM_LOCAL_BASE_ADDRESS + 0x1c;
+ gtdt->sec_el1_gsiv = 29;
+ gtdt->sec_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el1_gsiv = 30;
+ gtdt->el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->virt_el1_gsiv = 27;
+ gtdt->virt_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el2_gsiv = 26;
+ gtdt->el2_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->cnt_read_base = 0xffffffffffffffff;
+
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_add_table(ctx, gtdt);
+
+ acpi_inc(ctx, sizeof(struct acpi_gtdt));
+
+ return 0;
+};
+
+ACPI_WRITER(5gtdt, "GTDT", rpi_write_gtdt, 0);
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
new file mode 100644
index 0000000..a86875b
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2019, Jeremy Linton
+ * Copyright (c) 2019, Pete Batard <pete@akeo.ie>.
+ *
+ **/
+
+#ifndef BCM2711_H__
+#define BCM2711_H__
+
+#define BCM2711_SOC_REGISTERS 0xfc000000
+#define BCM2711_SOC_REGISTER_LENGTH 0x02000000
+
+#define BCM2711_ARM_LOCAL_REGISTERS 0xfe000000
+#define BCM2711_ARM_LOCAL_REGISTER_LENGTH 0x02000000
+
+/* arm local addresses */
+#define BCM2711_ARMC_OFFSET 0x0000b000
+#define BCM2711_ARMC_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARMC_OFFSET)
+#define BCM2711_ARMC_LENGTH 0x00000400
+
+#define BCM2711_ARM_LOCAL_OFFSET 0x01800000
+#define BCM2711_ARM_LOCAL_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARM_LOCAL_OFFSET)
+#define BCM2711_ARM_LOCAL_LENGTH 0x00000080
+
+#define BCM2711_GIC400_OFFSET 0x01840000
+#define BCM2711_GIC400_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_GIC400_OFFSET)
+#define BCM2711_GIC400_LENGTH 0x00008000
+
+/* Generic PCI addresses */
+#define PCIE_TOP_OF_MEM_WIN 0xf8000000
+#define PCIE_CPU_MMIO_WINDOW 0x600000000
+#define PCIE_BRIDGE_MMIO_LEN 0x3ffffff
+
+/* PCI root bridge control registers location */
+#define PCIE_REG_BASE 0xfd500000
+#define PCIE_REG_LIMIT 0x9310
+
+/* PCI root bridge control registers */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
+
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MEM_WIN0_LO(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+
+#define PCIE_MEM_WIN0_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define STATUS_PCIE_PORT_MASK 0x80
+#define STATUS_PCIE_PORT_SHIFT 7
+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
+#define STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define STATUS_PCIE_PHYLINKUP_SHIFT 4
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MEM_WIN0_BASE_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MEM_WIN0_LIMIT_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+#define PCIE_INTR2_CPU_STATUS 0x4300
+#define PCIE_INTR2_CPU_SET 0x4304
+#define PCIE_INTR2_CPU_CLR 0x4308
+#define PCIE_INTR2_CPU_MASK_STATUS 0x430c
+#define PCIE_INTR2_CPU_MASK_SET 0x4310
+#define PCIE_INTR2_CPU_MASK_CLR 0x4314
+
+#define PCIE_MSI_INTR2_CLR 0x4508
+#define PCIE_MSI_INTR2_MASK_SET 0x4510
+
+#define PCIE_RGR1_SW_INIT_1 0x9210
+#define PCIE_EXT_CFG_INDEX 0x9000
+/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
+#define PCIE_EXT_CFG_DATA 0x8000
+
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc
+
+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
+
+#define BURST_SIZE_128 0
+#define BURST_SIZE_256 1
+#define BURST_SIZE_512 2
+
+#define BCM2711_THERM_SENSOR_OFFSET 0x015d2200
+#define BCM2711_THERM_SENSOR_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_THERM_SENSOR_OFFSET)
+#define BCM2711_THERM_SENSOR_LENGTH 0x00000008
+
+#define BCM2711_GENET_BASE_OFFSET 0x01580000
+#define BCM2711_GENET_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_GENET_BASE_OFFSET)
+#define BCM2711_GENET_LENGTH 0x10000
+
+#endif /* BCM2711_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
new file mode 100644
index 0000000..64cec36
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ **/
+
+#ifndef __BCM2836_H__
+#define __BCM2836_H__
+
+/*
+ * Both "core" and SoC perpherals (1M each).
+ */
+#define BCM2836_SOC_REGISTERS 0xfe000000
+#define BCM2836_SOC_REGISTER_LENGTH 0x02000000
+
+/*
+ * Offset between the CPU's view and the VC's view of system memory.
+ */
+#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000
+
+/* watchdog constants */
+#define BCM2836_WDOG_OFFSET 0x00100000
+#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET)
+#define BCM2836_WDOG_PASSWORD 0x5a000000
+#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c
+#define BCM2836_WDOG_WDOG_OFFSET 0x00000024
+#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030
+#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
+
+/* clock manager constants */
+#define BCM2836_CM_OFFSET 0x00101000
+#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET)
+#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000
+#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004
+#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008
+#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c
+#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010
+#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014
+#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028
+#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c
+#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0
+#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4
+#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0
+#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4
+#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8
+#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac
+#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0
+#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4
+#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0
+#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4
+
+/* mailbox interface constants */
+#define BCM2836_MBOX_OFFSET 0x0000b880
+#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)
+#define BCM2836_MBOX_LENGTH 0x00000024
+#define BCM2836_MBOX_READ_OFFSET 0x00000000
+#define BCM2836_MBOX_STATUS_OFFSET 0x00000018
+#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c
+#define BCM2836_MBOX_WRITE_OFFSET 0x00000020
+
+#define BCM2836_MBOX_STATUS_FULL 0x1f
+#define BCM2836_MBOX_STATUS_EMPTY 0x1e
+
+#define BCM2836_MBOX_NUM_CHANNELS 16
+
+/* interrupt controller constants */
+#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040
+#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060
+
+/* usb constants */
+#define BCM2836_USB_OFFSET 0x00980000
+#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)
+#define BCM2836_USB_LENGTH 0x00010000
+
+/* serial based protocol constants */
+#define BCM2836_PL011_UART_OFFSET 0x00201000
+#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)
+#define BCM2836_PL011_UART_LENGTH 0x00001000
+
+#define BCM2836_MINI_UART_OFFSET 0x00215000
+#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET)
+#define BCM2836_MINI_UART_LENGTH 0x00000070
+
+#define BCM2836_I2C0_OFFSET 0x00205000
+#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)
+#define BCM2836_I2C0_LENGTH 0x00000020
+
+#define BCM2836_I2C1_OFFSET 0x00804000
+#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)
+#define BCM2836_I2C1_LENGTH 0x00000020
+
+#define BCM2836_I2C2_OFFSET 0x00805000
+#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)
+#define BCM2836_I2C2_LENGTH 0x00000020
+
+#define BCM2836_SPI0_OFFSET 0x00204000
+#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)
+#define BCM2836_SPI0_LENGTH 0x00000020
+
+#define BCM2836_SPI1_OFFSET 0x00215080
+#define BCM2836_SPI1_LENGTH 0x00000040
+#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)
+
+#define BCM2836_SPI2_OFFSET 0x002150C0
+#define BCM2836_SPI2_LENGTH 0x00000040
+#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
+
+#define BCM2836_SYSTEM_TIMER_OFFSET 0x00003000
+#define BCM2836_SYSTEM_TIMER_LENGTH 0x00000020
+#define BCM2836_SYSTEM_TIMER_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SYSTEM_TIMER_OFFSET)
+
+/* dma constants */
+#define BCM2836_DMA0_OFFSET 0x00007000
+#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
+
+#define BCM2836_DMA15_OFFSET 0x00E05000
+#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)
+
+#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0
+#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)
+
+#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100
+
+#endif /*__BCM2836_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
new file mode 100644
index 0000000..c5b858b
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPIO_H__
+#define __BCM2836_GPIO_H__
+
+#define GPIO_OFFSET 0x00200000
+#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET)
+#define GPIO_LENGTH 0x000000B4
+
+#endif /* __BCM2836_GPIO_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
new file mode 100644
index 0000000..5857d75
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPU_H__
+#define __BCM2836_GPU_H__
+
+/* VideoCore constants */
+
+#define BCM2836_VCHIQ_OFFSET 0x0000B840
+#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET)
+#define BCM2836_VCHIQ_LENGTH 0x00000010
+
+#define BCM2836_V3D_BUS_OFFSET 0x00C00000
+#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET)
+#define BCM2836_V3D_BUS_LENGTH 0x00001000
+
+#define BCM2836_HVS_OFFSET 0x00400000
+#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET)
+#define BCM2836_HVS_LENGTH 0x00006000
+
+#define BCM2836_PV0_OFFSET 0x00206000
+#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET)
+#define BCM2836_PV0_LENGTH 0x00000100
+
+#define BCM2836_PV1_OFFSET 0x00207000
+#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET)
+#define BCM2836_PV1_LENGTH 0x00000100
+
+#define BCM2836_PV2_OFFSET 0x00807000
+#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET)
+#define BCM2836_PV2_LENGTH 0x00000100
+
+#define BCM2836_HDMI0_OFFSET 0x00902000
+#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET)
+#define BCM2836_HDMI0_LENGTH 0x00000600
+
+#define BCM2836_HDMI1_OFFSET 0x00808000
+#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET)
+#define BCM2836_HDMI1_LENGTH 0x00000100
+
+#endif /* __BCM2836_MISC_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
new file mode 100644
index 0000000..78a8486
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_PWM_H__
+#define __BCM2836_PWM_H__
+
+/* PWM controller constants */
+
+#define BCM2836_PWM_DMA_OFFSET 0x00007B00
+#define BCM2836_PWM_DMA_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_DMA_OFFSET)
+#define BCM2836_PWM_DMA_LENGTH 0x00000100
+
+#define BCM2836_PWM_CLK_OFFSET 0x001010A0
+#define BCM2836_PWM_CLK_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CLK_OFFSET)
+#define BCM2836_PWM_CLK_LENGTH 0x00000008
+
+#define BCM2836_PWM_CTRL_OFFSET 0x0020C000
+#define BCM2836_PWM_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CTRL_OFFSET)
+#define BCM2836_PWM_CTRL_LENGTH 0x00000028
+
+#define BCM2836_PWM_BUS_BASE_ADDRESS 0x7E20C000
+#define BCM2836_PWM_BUS_LENGTH 0x00000028
+
+#define BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS 0xFF20C000
+#define BCM2836_PWM_CTRL_UNCACHED_LENGTH 0x00000028
+
+#endif /* __BCM2836_PWM_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
new file mode 100644
index 0000000..9b1afe8
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDHOST_H__
+#define __BCM2836_SDHOST_H__
+
+#define SDHOST_OFFSET 0x00202000
+#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET)
+#define SDHOST_LENGTH 0x00000100
+
+#endif /*__BCM2836_SDHOST_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
new file mode 100644
index 0000000..48d073d
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-2-Clause-Patent */
+/**
+ *
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDIO_H__
+#define __BCM2836_SDIO_H__
+
+// MMC/SD/SDIO1 register definitions.
+#define MMCHS1_OFFSET 0x00300000
+#define MMCHS2_OFFSET 0x00340000
+#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)
+#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)
+#define MMCHS1_LENGTH 0x00000100
+#define MMCHS2_LENGTH 0x00000100
+
+#endif /* __BCM2836_SDIO_H__ */
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 1b45970..7a1de22 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -50,7 +50,7 @@
}, {
.virt = 0xfc000000UL,
.phys = 0xfc000000UL,
- .size = 0x03800000UL,
+ .size = 0x04000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9d1fabe..b254a50 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -228,6 +228,13 @@
select SPL_CRYPTO if SPL
imply OF_UPSTREAM
+config TARGET_IMX8MP_NAVQP
+ bool "Emcraft Systems i.MX8M Plus NavQ+ board"
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+ imply OF_UPSTREAM
+
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
select IMX8MP
@@ -358,6 +365,7 @@
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/data_modul/imx8mp_edm_sbc/Kconfig"
source "board/dhelectronics/dh_imx8mp/Kconfig"
+source "board/emcraft/imx8mp_navqp/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/engicam/imx8mp/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 4d32c28..5c10541 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -23,6 +23,13 @@
prompt "NXP i.MX9 board select"
optional
+config TARGET_IMX93_9X9_QSB
+ bool "imx93_qsb"
+ select OF_BOARD_FIXUP
+ select IMX93
+ select IMX9_LPDDR4X
+ imply OF_UPSTREAM
+
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
select OF_BOARD_FIXUP
@@ -42,6 +49,7 @@
endchoice
source "board/freescale/imx93_evk/Kconfig"
+source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index dda57ed..c00be19 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -35,6 +35,7 @@
static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+ FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
index 47106ff..5dbc398 100644
--- a/arch/arm/mach-imx/imx9/clock_root.c
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -7,9 +7,10 @@
#include <config.h>
#include <command.h>
+#include <asm/arch/ccm_regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/ccm_regs.h>
#include <asm/global_data.h>
#include <linux/iopoll.h>
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 2e68557..4e0e8ed 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -17,13 +17,6 @@
select ROM_UNIFIED_SECTIONS
imply CMD_FUSE
-config TEXT_BASE
- default 0x87800000
-
-config SPL_TEXT_BASE
- depends on SPL
- default 0x00912000
-
choice
prompt "MX7 board select"
optional
diff --git a/arch/arm/mach-k3/am62x/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c
index 8fe200a..ab9b573 100644
--- a/arch/arm/mach-k3/am62x/am625_fdt.c
+++ b/arch/arm/mach-k3/am62x/am625_fdt.c
@@ -5,6 +5,7 @@
#include <asm/hardware.h>
#include <fdt_support.h>
+#include <fdtdec.h>
#include "../common_fdt.h"
@@ -75,12 +76,47 @@
}
}
+static void fdt_fixup_thermal_cooling_device_cpus_am625(void *blob, int core_nr)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/main0-thermal/cooling-maps/map0",
+ "/thermal-zones/main1-thermal/cooling-maps/map0"
+ };
+
+ int node, cnt, i, ret;
+ u32 cooling_dev[12];
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ int new_count = core_nr * 3; /* Each CPU has 3 entries */
+ int j;
+
+ node = fdt_path_offset(blob, thermal_path[i]);
+ if (node < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, node, "cooling-device",
+ cooling_dev, ARRAY_SIZE(cooling_dev));
+ if (cnt < 0)
+ continue;
+
+ for (j = 0; j < new_count; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, node, "cooling-device", cooling_dev,
+ new_count * sizeof(u32));
+ if (ret < 0)
+ printf("Error %s, cooling-device setprop failed %d\n",
+ thermal_path[i], ret);
+ }
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
fdt_fixup_cores_nodes_am625(blob, k3_get_core_nr());
fdt_fixup_gpu_nodes_am625(blob, k3_has_gpu());
fdt_fixup_pru_node_am625(blob, k3_has_pru());
fdt_fixup_thermal_zone_nodes_am625(blob, k3_get_max_temp());
+ fdt_fixup_thermal_cooling_device_cpus_am625(blob, k3_get_core_nr());
fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index f2086cb..fa8cd93 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,8 @@
#include <env.h>
#include <elf.h>
#include <soc.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
#include <asm/arch/k3-qos.h>
@@ -246,12 +248,32 @@
#endif
}
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+static __maybe_unused void k3_dma_remove(void)
+{
+ struct udevice *dev;
+ int rc;
+
+ rc = uclass_find_device(UCLASS_DMA, 0, &dev);
+ if (!rc && dev) {
+ rc = device_remove(dev, DM_REMOVE_NORMAL);
+ if (rc)
+ pr_warn("Cannot remove dma device '%s' (err=%d)\n",
+ dev->name, rc);
+ } else
+ pr_warn("DMA Device not found (err=%d)\n", rc);
+}
+
void spl_board_prepare_for_boot(void)
{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
dcache_disable();
+#endif
+#if IS_ENABLED(CONFIG_SPL_DMA) && IS_ENABLED(CONFIG_SPL_DM_DEVICE_REMOVE)
+ k3_dma_remove();
+#endif
}
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
void spl_board_prepare_for_linux(void)
{
dcache_disable();
diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c
index 64c34d3..6ce3eb8 100644
--- a/arch/arm/mach-k3/j721s2/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2/j721s2_init.c
@@ -315,6 +315,9 @@
#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
+ struct udevice *dev;
+ int ret;
+
k3_spl_init();
#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
do_dt_magic();
@@ -325,6 +328,13 @@
setup_navss_nb();
setup_qos();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
+ &dev);
+ if (ret)
+ printf("AVS init failed: %d\n", ret);
+ }
}
#endif
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 793bcac..97d9692 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -67,6 +67,16 @@
"gluelogic_hfosc0_clkout",
};
+static const char * const wkup_usart_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_usart_mcupll_bypass_out0_parents[] = {
+ "wkup_usart_clksel_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
@@ -206,7 +216,7 @@
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
- CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0, 96000000),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
@@ -216,6 +226,8 @@
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
+ CLK_MUX("wkup_usart_mcupll_bypass_out0", wkup_usart_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
@@ -409,6 +421,10 @@
DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(397, 0, "wkup_usart_mcupll_bypass_out0"),
+ DEV_CLK(397, 1, "wkup_usart_clksel_out0"),
+ DEV_CLK(397, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(397, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),
diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index d66ba8b..b32b4ba 100644
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -62,6 +62,7 @@
PSC_DEV(149, &soc_lpsc_list[0]),
PSC_DEV(167, &soc_lpsc_list[1]),
PSC_DEV(279, &soc_lpsc_list[1]),
+ PSC_DEV(397, &soc_lpsc_list[1]),
PSC_DEV(161, &soc_lpsc_list[2]),
PSC_DEV(162, &soc_lpsc_list[3]),
PSC_DEV(160, &soc_lpsc_list[4]),
diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig
index 186c358..9c06c6a 100644
--- a/arch/arm/mach-qemu/Kconfig
+++ b/arch/arm/mach-qemu/Kconfig
@@ -3,12 +3,6 @@
config SYS_VENDOR
default "emulation"
-config SYS_BOARD
- default "qemu-arm"
-
-config SYS_CONFIG_NAME
- default "qemu-arm"
-
choice
prompt "QEMU ARM architecture"
default TARGET_QEMU_ARM_64BIT
@@ -25,6 +19,36 @@
select ARM64
select BOARD_LATE_INIT
+config TARGET_QEMU_ARM_SBSA
+ bool "SBSA Reference"
+ select ARM64
+ select BINMAN
+ select BOARD_LATE_INIT
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ select MISC_INIT_R
endchoice
+if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT
+
+config SYS_BOARD
+ default "qemu-arm"
+
+config SYS_CONFIG_NAME
+ default "qemu-arm"
+
+endif
+
+if TARGET_QEMU_ARM_SBSA
+
+config SYS_BOARD
+ default "qemu-sbsa"
+
+config SYS_CONFIG_NAME
+ default "qemu-sbsa"
+
+config SYS_SOC
+ default "qemu-sbsa"
+
+endif
+
endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index fc1b638..269c219 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -257,7 +257,6 @@
select SPL_SYSCON if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
- select SPL_SERIAL
select CLK
select FIT
select PINCTRL
@@ -288,6 +287,7 @@
imply SPL_DM_SEQ_ALIAS
imply SPL_FIT_SIGNATURE
imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SERIAL
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
imply TPL_CLK
imply TPL_DM
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 3fadf7e..75d6693 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -472,9 +472,18 @@
__weak int board_rng_seed(struct abuf *buf)
{
struct udevice *dev;
- size_t len = 0x8;
+ ulong len = env_get_ulong("rng_seed_size", 10, 64);
u64 *data;
+ if (len < 64) {
+ /*
+ * rng_seed_size should be at least 32 bytes for Linux 5.19+,
+ * or 64 for older Linux kernel versions
+ */
+ log_warning("Value for rng_seed_size (%lu) too low, Linux kernel RNG may fail to initialize early\n",
+ len);
+ }
+
data = malloc(len);
if (!data) {
printf("Out of memory\n");
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index 899cf90..e646f71 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_ODROID_M1S_RK3566
+ bool "ODROID-M1S"
+ help
+ Hardkernel ODROID-M1S single board computer with a RK3566 SoC.
+
config TARGET_POWKIDDY_X55_RK3566
bool "Powkiddy X55"
help
@@ -62,6 +67,7 @@
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
+source "board/hardkernel/odroid_m1s/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
source "board/powkiddy/x55/Kconfig"
source "board/radxa/zero3-rk3566/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 768a373..c9a3228 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -26,6 +26,8 @@
#define PMU_BASE_ADDR 0xfdd90000
#define PMU_NOC_AUTO_CON0 (0x70)
#define PMU_NOC_AUTO_CON1 (0x74)
+#define PMU_PWR_GATE_SFTCON (0xa0)
+#define PMU_PD_VO_DWN_ENA BIT(7)
#define EDP_PHY_GRF_BASE 0xfdcb0000
#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
@@ -130,6 +132,10 @@
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+
+ /* Enable VO power domain for display */
+ writel((PMU_PD_VO_DWN_ENA << 16),
+ PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
#endif
return 0;
}
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index a76a470..6f28a31 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -134,6 +134,12 @@
includes socket for eMMC storage, an SDMMC slot, and a 40-pin
GPIO header for expansion.
+config TARGET_ODROID_M2_RK3588S
+ bool "Hardkernel ODROID-M2"
+ select BOARD_LATE_INIT
+ help
+ Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -366,6 +372,7 @@
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
+source "board/hardkernel/odroid_m2/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d5934a9..25663a9 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -39,6 +39,7 @@
config STM32MP13X
bool "Support STMicroelectronics STM32MP13x Soc"
+ select ARCH_EARLY_INIT_R
select ARM_SMCCC
select CPU_V7A
select CPU_V7_HAS_NONSEC
@@ -57,6 +58,7 @@
config STM32MP15X
bool "Support STMicroelectronics STM32MP15x Soc"
+ select ARCH_EARLY_INIT_R
select ARCH_SUPPORT_PSCI
select BINMAN
select CPU_V7A
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 3698fc4..b061057 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -25,8 +25,11 @@
ofnode node;
node = ofnode_path("/reserved-memory/optee");
- if (!ofnode_valid(node))
- return -ENOENT;
+ if (!ofnode_valid(node)) {
+ node = ofnode_path("/reserved-memory/optee_core");
+ if (!ofnode_valid(node))
+ return -ENOENT;
+ }
fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
*start = fdt_start;
@@ -62,7 +65,6 @@
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
- int ret;
phys_size_t size;
phys_addr_t reg;
u32 optee_start, optee_size;
@@ -75,10 +77,17 @@
* if the effective available memory is bigger
*/
gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
+ /* add 8M for U-Boot reserved memory: display, fdt, gd,... */
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
- ret = optee_get_reserved_memory(&optee_start, &optee_size);
- reg = (!ret ? optee_start : gd->ram_top) - size;
+ reg = gd->ram_top - size;
+
+ /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
+ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
+ if (!optee_get_reserved_memory(&optee_start, &optee_size))
+ reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
+ }
/* before relocation, mark the U-Boot memory as cacheable by default */
if (!(gd->flags & GD_FLG_RELOC))
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 26c073f..62cc989 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -143,6 +143,11 @@
{
/* I-cache is already enabled in start.S: icache_enable() not needed */
+ /* keep D-cache configuration done before relocation, wait arch_early_init_r*/
+}
+
+int arch_early_init_r(void)
+{
/* deactivate the data cache, early enabled in arch_cpu_init() */
dcache_disable();
/*
@@ -150,6 +155,8 @@
* warning: the TLB location udpated in board_f.c::reserve_mmu
*/
dcache_enable();
+
+ return 0;
}
static void setup_boot_mode(void)
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 24fd575..960ffac 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -112,19 +112,32 @@
return 0x14000;
}
-#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(u8 mode)
{
- puts("WARNING: Initializing TCM overwrites TCM content\n");
- initialize_tcm(mode);
- memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+ int ret;
+
+ ret = check_tcm_mode(mode);
+ if (!ret) {
+ puts("WARNING: Initializing TCM overwrites TCM content\n");
+ initialize_tcm(mode);
+ memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+ }
+
+ if (ret == -EACCES)
+ printf("ERROR: Split to lockstep mode required reset/disable cpu\n");
+
+ /* Ignore if ret is -EAGAIN, trying to initialize same mode again */
}
#endif
#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
int arm_reserve_mmu(void)
{
- tcm_init(TCM_LOCK);
+ puts("WARNING: Initializing TCM overwrites TCM content\n");
+ initialize_tcm(TCM_LOCK);
+ memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 15b69e7..9af3ab5 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -48,9 +48,10 @@
unsigned int zynqmp_get_silicon_version(void);
+int check_tcm_mode(bool mode);
void initialize_tcm(bool mode);
void mem_map_fill(void);
-#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(u8 mode);
#endif
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 9b46a25..6e6da80 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -12,7 +12,9 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <linux/bitfield.h>
#include <linux/delay.h>
+#include <linux/errno.h>
#include <linux/string.h>
#define LOCK 0
@@ -264,6 +266,28 @@
}
}
+int check_tcm_mode(bool mode)
+{
+ u32 tmp, cpu_state;
+ bool mode_prev;
+
+ tmp = readl(&rpu_base->rpu_glbl_ctrl);
+ mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp);
+
+ tmp = readl(&crlapb_base->rst_lpd_top);
+ cpu_state = FIELD_GET(ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
+ ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp);
+ cpu_state = cpu_state ? false : true;
+
+ if ((mode_prev == SPLIT && mode == LOCK) && cpu_state)
+ return -EACCES;
+
+ if (mode_prev == mode)
+ return -EAGAIN;
+
+ return 0;
+}
+
static void mark_r5_used(u32 nr, u8 mode)
{
u32 mask = 0;
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index 3b4d9c6..8ee25e4 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -151,14 +151,12 @@
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;
- if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) {
- printf("mode param should be lockstep or split\n");
- return CMD_RET_FAILURE;
- }
-
- mode = hextoul(argv[2], NULL);
- if (mode != TCM_LOCK && mode != TCM_SPLIT) {
- printf("Mode should be either 0(lock)/1(split)\n");
+ if (!strcmp(argv[2], "lockstep") || !strcmp(argv[2], "0")) {
+ mode = TCM_LOCK;
+ } else if (!strcmp(argv[2], "split") || !strcmp(argv[2], "1")) {
+ mode = TCM_SPLIT;
+ } else {
+ printf("Mode should be either lockstep/split\n");
return CMD_RET_FAILURE;
}
@@ -429,7 +427,7 @@
" initialized before accessing to avoid ECC\n"
" errors. mode specifies in which mode TCM has\n"
" to be initialized. Supported modes will be\n"
- " lock(0)/split(1)\n"
+ " lockstep(0)/split(1)\n"
#endif
"zynqmp pmufw address size - load PMU FW configuration object\n"
"zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n"
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h
index d419824..5decf73 100644
--- a/arch/m68k/include/asm/ptrace.h
+++ b/arch/m68k/include/asm/ptrace.h
@@ -9,6 +9,8 @@
*/
#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
struct pt_regs {
ulong d0;
ulong d1;
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 89a2ac2..00699c4 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -286,20 +286,6 @@
/* 1MB granularity */
#define MMU_SECTION_SHIFT 20
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
-
-/**
- * noncached_init() - Initialize non-cached memory region
- *
- * Initialize non-cached memory area. This memory region will be typically
- * located right below the malloc() area and be accessed from KSEG1.
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int noncached_init(void);
-
-phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
#endif /* _ASM_SYSTEM_H */
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa37102..043d963 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -21,7 +21,7 @@
bool "Support RISC-V cores on OpenPiton SoC"
config TARGET_QEMU_VIRT
- bool "Support QEMU Virt Board"
+ bool "Support QEMU Virt & RVVM Boards"
select BOARD_LATE_INIT
config TARGET_SIFIVE_UNLEASHED
@@ -319,6 +319,10 @@
help
Adds "A" to the ISA string passed to the compiler.
+config RISCV_ISA_ZICBOM
+ bool "Zicbom support"
+ depends on !SYS_DISABLE_DCACHE_OPS
+
config DMA_ADDR_T_64BIT
bool
default y if 64BIT
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f3dfd75..bf32ead 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
-dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
deleted file mode 100644
index 1069134..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-/ {
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
- core_pwm0: pwm@40000000 {
- compatible = "microchip,corepwm-rtl-v4";
- reg = <0x0 0x40000000 0x0 0xF0>;
- microchip,sync-update-mask = /bits/ 32 <0>;
- #pwm-cells = <3>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
- status = "disabled";
- };
-
- i2c2: i2c@40000200 {
- compatible = "microchip,corei2c-rtl-v7";
- reg = <0x0 0x40000200 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
- interrupt-parent = <&plic>;
- interrupts = <122>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- pcie: pcie@3000000000 {
- compatible = "microchip,pcie-host-1.0";
- #address-cells = <0x3>;
- #interrupt-cells = <0x1>;
- #size-cells = <0x2>;
- device_type = "pci";
- reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
- bus-range = <0x0 0x7f>;
- interrupt-parent = <&plic>;
- interrupts = <119>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- interrupt-map-mask = <0 0 0 7>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
- clock-names = "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
- dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
- msi-parent = <&pcie>;
- msi-controller;
- status = "disabled";
- pcie_intc: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- refclk_ccc: cccrefclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-};
-
-&ccc_nw {
- clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
- <&refclk_ccc>, <&refclk_ccc>;
- clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
- "dll0_ref", "dll1_ref";
- status = "okay";
-};
diff --git a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
deleted file mode 100644
index f60283f..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2020 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
- */
-
-/ {
- aliases {
- cpu1 = &cpu1;
- cpu2 = &cpu2;
- cpu3 = &cpu3;
- cpu4 = &cpu4;
- };
-};
diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts
deleted file mode 100644
index 8aa5fb1..0000000
--- a/arch/riscv/dts/mpfs-icicle-kit.dts
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2021-2022 Microchip Technology Inc.
- * Padmarao Begari <padmarao.begari@microchip.com>
- */
-
-/dts-v1/;
-
-#include "mpfs.dtsi"
-#include "mpfs-icicle-kit-fabric.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ 1000000
-
-/ {
- model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
- aliases {
- ethernet0 = &mac1;
- serial0 = &mmuart0;
- serial1 = &mmuart1;
- serial2 = &mmuart2;
- serial3 = &mmuart3;
- serial4 = &mmuart4;
- };
-
- chosen {
- stdout-path = "serial1:115200n8";
- };
-
- cpus {
- timebase-frequency = <RTCCLK_FREQ>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led1";
- };
-
- led-2 {
- gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led2";
- };
-
- led-3 {
- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led3";
- };
-
- led-4 {
- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led4";
- };
- };
-
- ddrc_cache_lo: memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
- status = "okay";
- };
-
- ddrc_cache_hi: memory@1040000000 {
- device_type = "memory";
- reg = <0x10 0x40000000 0x0 0x40000000>;
- status = "okay";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hss_payload: region@BFC00000 {
- reg = <0x0 0xBFC00000 0x0 0x400000>;
- no-map;
- };
- };
-};
-
-&core_pwm0 {
- status = "okay";
-};
-
-&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&mac0 {
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
- status = "enabled";
-};
-
-&mac1 {
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
- status = "okay";
-
- phy1: ethernet-phy@9 {
- reg = <9>;
- };
-
- phy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-&mbox {
- status = "okay";
-};
-
-&mmc {
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&mmuart1 {
- status = "okay";
-};
-
-&mmuart2 {
- status = "okay";
-};
-
-&mmuart3 {
- status = "okay";
-};
-
-&mmuart4 {
- status = "okay";
-};
-
-&pcie {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-};
-
-&refclk {
- clock-frequency = <125000000>;
-};
-
-&refclk_ccc {
- clock-frequency = <50000000>;
-};
-
-&rtc {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&syscontroller {
- status = "okay";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi
deleted file mode 100644
index 6012a28..0000000
--- a/arch/riscv/dts/mpfs.dtsi
+++ /dev/null
@@ -1,511 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-#include "dt-bindings/clock/microchip-mpfs-clock.h"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "Microchip PolarFire SoC";
- compatible = "microchip,mpfs";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- clocks = <&clkcfg CLK_CPU>;
- status = "disabled";
-
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu1: cpu@1 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu2: cpu@2 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <2>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu3: cpu@3 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <3>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
-
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu4: cpu@4 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <4>;
- riscv,isa = "rv64imafdc";
- clocks = <&clkcfg CLK_CPU>;
- tlb-split;
- next-level-cache = <&cctrllr>;
- status = "okay";
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
-
- core4 {
- cpu = <&cpu4>;
- };
- };
- };
- };
-
- refclk: mssrefclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-
- syscontroller: syscontroller {
- compatible = "microchip,mpfs-sys-controller";
- mboxes = <&mbox 0>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
-
- cctrllr: cache-controller@2010000 {
- compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
- reg = <0x0 0x2010000 0x0 0x1000>;
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <1024>;
- cache-size = <2097152>;
- cache-unified;
- interrupt-parent = <&plic>;
- interrupts = <1>, <3>, <4>, <2>;
- };
-
- clint: clint@2000000 {
- compatible = "sifive,fu540-c000-clint", "sifive,clint0";
- reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>,
- <&cpu4_intc 3>, <&cpu4_intc 7>;
- };
-
- plic: interrupt-controller@c000000 {
- compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
- reg = <0x0 0xc000000 0x0 0x4000000>;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>;
- riscv,ndev = <186>;
- };
-
- pdma: dma-controller@3000000 {
- compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
- dma-channels = <4>;
- #dma-cells = <1>;
- };
-
- clkcfg: clkcfg@20002000 {
- compatible = "microchip,mpfs-clkcfg";
- reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
- clocks = <&refclk>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- ccc_se: clock-controller@38010000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
- <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_ne: clock-controller@38040000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
- <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_nw: clock-controller@38100000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
- <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- ccc_sw: clock-controller@38400000 {
- compatible = "microchip,mpfs-ccc";
- reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
- <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
- #clock-cells = <1>;
- status = "disabled";
- };
-
- mmuart0: serial@20000000 {
- compatible = "ns16550a";
- reg = <0x0 0x20000000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <90>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled"; /* Reserved for the HSS */
- };
-
- mmuart1: serial@20100000 {
- compatible = "ns16550a";
- reg = <0x0 0x20100000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <91>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART1>;
- status = "disabled";
- };
-
- mmuart2: serial@20102000 {
- compatible = "ns16550a";
- reg = <0x0 0x20102000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <92>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART2>;
- status = "disabled";
- };
-
- mmuart3: serial@20104000 {
- compatible = "ns16550a";
- reg = <0x0 0x20104000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <93>;
- current-speed = <115200>;
- clocks = <&clkcfg CLK_MMUART3>;
- status = "disabled";
- };
-
- mmuart4: serial@20106000 {
- compatible = "ns16550a";
- reg = <0x0 0x20106000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <94>;
- clocks = <&clkcfg CLK_MMUART4>;
- current-speed = <115200>;
- status = "disabled";
- };
-
- /* Common node entry for emmc/sd */
- mmc: mmc@20008000 {
- compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
- reg = <0x0 0x20008000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <88>;
- clocks = <&clkcfg CLK_MMC>;
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- spi0: spi@20108000 {
- compatible = "microchip,mpfs-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20108000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <54>;
- clocks = <&clkcfg CLK_SPI0>;
- status = "disabled";
- };
-
- spi1: spi@20109000 {
- compatible = "microchip,mpfs-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20109000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <55>;
- clocks = <&clkcfg CLK_SPI1>;
- status = "disabled";
- };
-
- qspi: spi@21000000 {
- compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x21000000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <85>;
- clocks = <&clkcfg CLK_QSPI>;
- status = "disabled";
- };
-
- i2c0: i2c@2010a000 {
- compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
- reg = <0x0 0x2010a000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <58>;
- clocks = <&clkcfg CLK_I2C0>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- i2c1: i2c@2010b000 {
- compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
- reg = <0x0 0x2010b000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <61>;
- clocks = <&clkcfg CLK_I2C1>;
- clock-frequency = <100000>;
- status = "disabled";
- };
-
- can0: can@2010c000 {
- compatible = "microchip,mpfs-can";
- reg = <0x0 0x2010c000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN0>;
- interrupt-parent = <&plic>;
- interrupts = <56>;
- status = "disabled";
- };
-
- can1: can@2010d000 {
- compatible = "microchip,mpfs-can";
- reg = <0x0 0x2010d000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN1>;
- interrupt-parent = <&plic>;
- interrupts = <57>;
- status = "disabled";
- };
-
- mac0: ethernet@20110000 {
- compatible = "microchip,mpfs-macb", "cdns,macb";
- reg = <0x0 0x20110000 0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC0>;
- status = "disabled";
- };
-
- mac1: ethernet@20112000 {
- compatible = "microchip,mpfs-macb", "cdns,macb";
- reg = <0x0 0x20112000 0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC1>;
- status = "disabled";
- };
-
- gpio0: gpio@20120000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20120000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- gpio1: gpio@20121000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20121000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- gpio2: gpio@20122000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20122000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupt-controller;
- #interrupt-cells = <1>;
- clocks = <&clkcfg CLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- rtc: rtc@20124000 {
- compatible = "microchip,mpfs-rtc";
- reg = <0x0 0x20124000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <80>, <81>;
- clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
- clock-names = "rtc", "rtcref";
- status = "disabled";
- };
-
- usb: usb@20201000 {
- compatible = "microchip,mpfs-musb";
- reg = <0x0 0x20201000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <86>, <87>;
- clocks = <&clkcfg CLK_USB>;
- interrupt-names = "dma","mc";
- status = "disabled";
- };
-
- mbox: mailbox@37020000 {
- compatible = "microchip,mpfs-mailbox";
- reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
- <0x0 0x37020800 0x0 0x100>;
- interrupt-parent = <&plic>;
- interrupts = <96>;
- #mbox-cells = <1>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 48ee115..4050ce2 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -20,7 +20,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
- timebase-frequency = <102000000>;
+ timebase-frequency = <100000000>;
cpu_0: cpu@0 {
compatible = "amd,mbv32", "riscv";
device_type = "cpu";
@@ -28,7 +28,7 @@
riscv,isa = "rv32imafdc";
i-cache-size = <32768>;
d-cache-size = <32768>;
- clock-frequency = <102000000>;
+ clock-frequency = <100000000>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
@@ -46,15 +46,15 @@
stdout-path = "serial0:115200n8";
};
- memory@20000000 {
+ memory@80000000 {
device_type = "memory";
- reg = <0x20000000 0x20000000>;
+ reg = <0x80000000 0x40000000>;
};
- clk102: clock {
+ clk100: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <102000000>;
+ clock-frequency = <100000000>;
};
axi: axi {
@@ -77,30 +77,20 @@
compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c00000 0x1000>;
interrupt-parent = <&axi_intc>;
- interrupts = <1 2>;
- bootph-all;
- xlnx,one-timer-only = <0>;
- clock-names = "s_axi_aclk";
- clocks = <&clk102>;
- };
-
- xlnx_timer1: timer@41c20000 {
- compatible = "xlnx,xps-timer-1.00.a";
- reg = <0x41c20000 0x1000>;
- interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
+ bootph-all;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
- clocks = <&clk102>;
+ clocks = <&clk100>;
};
uart0: serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x40600000 0x1000>;
interrupt-parent = <&axi_intc>;
- interrupts = <2 2>;
+ interrupts = <1 2>;
bootph-all;
- clocks = <&clk102>;
+ clocks = <&clk100>;
current-speed = <115200>;
xlnx,data-bits = <8>;
xlnx,use-parity = <0>;
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 593d927..d356752 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -42,6 +42,7 @@
#ifdef CONFIG_SMBIOS
ulong smbios_start; /* Start address of SMBIOS table */
#endif
+ struct resume_data *resume;
};
#include <asm-generic/global_data.h>
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
new file mode 100644
index 0000000..19a10ca
--- /dev/null
+++ b/arch/riscv/include/asm/insn-def.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Ventana Micro Systems Ltd.
+ *
+ * Ported from linux insn-def.h.
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#define INSN_I_SIMM12_SHIFT 20
+#define INSN_I_RS1_SHIFT 15
+#define INSN_I_FUNC3_SHIFT 12
+#define INSN_I_RD_SHIFT 7
+#define INSN_I_OPCODE_SHIFT 0
+
+#define RV_OPCODE(v) __ASM_STR(v)
+#define RV_FUNC3(v) __ASM_STR(v)
+#define RV_FUNC7(v) __ASM_STR(v)
+#define RV_SIMM12(v) __ASM_STR(v)
+#define RV_RD(v) __ASM_STR(v)
+#define RV_RS1(v) __ASM_STR(v)
+#define RV_RS2(v) __ASM_STR(v)
+#define __RV_REG(v) __ASM_STR(x ## v)
+#define RV___RD(v) __RV_REG(v)
+#define RV___RS1(v) __RV_REG(v)
+#define RV___RS2(v) __RV_REG(v)
+
+#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
+#define RV_OPCODE_SYSTEM RV_OPCODE(115)
+
+#define __INSN_I(opcode, func3, rd, rs1, simm12) \
+ ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
+
+#define INSN_I(opcode, func3, rd, rs1, simm12) \
+ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
+ RV_##rs1, RV_##simm12)
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index ad32ded..47124db 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -33,8 +33,10 @@
SBI_EXT_CPPC = 0x43505043,
SBI_EXT_NACL = 0x4E41434C,
SBI_EXT_STA = 0x535441,
- SBI_EXT_DBTR = 0x44425452,
SBI_EXT_SSE = 0x535345,
+ SBI_EXT_FWFT = 0x46574654,
+ SBI_EXT_DBTR = 0x44425452,
+ SBI_EXT_MPXY = 0x4D505859,
};
enum sbi_ext_base_fid {
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index afad7e1..e184d5e 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -5,6 +5,98 @@
*/
#include <cpu_func.h>
+#include <dm.h>
+#include <asm/insn-def.h>
+#include <linux/const.h>
+
+#define CBO_INVAL(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(0))
+#define CBO_CLEAN(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(1))
+#define CBO_FLUSH(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(2))
+enum {
+ CBO_CLEAN,
+ CBO_FLUSH,
+ CBO_INVAL
+} riscv_cbo_ops;
+static int zicbom_block_size;
+
+static inline void do_cbo_clean(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_flush(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_inval(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) ::
+ "r"(base) : "memory");
+}
+
+static void cbo_op(int op_type, unsigned long start,
+ unsigned long end)
+{
+ unsigned long op_size = end - start, size = 0;
+ void (*fn)(unsigned long base);
+
+ switch (op_type) {
+ case CBO_CLEAN:
+ fn = do_cbo_clean;
+ break;
+ case CBO_FLUSH:
+ fn = do_cbo_flush;
+ break;
+ case CBO_INVAL:
+ fn = do_cbo_inval;
+ break;
+ }
+ start &= ~(UL(zicbom_block_size - 1));
+ while (size < op_size) {
+ fn(start + size);
+ size += zicbom_block_size;
+ }
+}
+
+void cbo_flush(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_FLUSH, start, end);
+}
+
+void cbo_inval(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_INVAL, start, end);
+}
+
+static int riscv_zicbom_init(void)
+{
+ struct udevice *dev;
+
+ if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || zicbom_block_size)
+ return 1;
+
+ uclass_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ log_debug("Failed to get cpu device!\n");
+ return 0;
+ }
+
+ if (dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size))
+ log_debug("riscv,cbom-block-size DT property not present\n");
+
+ return zicbom_block_size;
+}
void invalidate_icache_all(void)
{
@@ -17,6 +109,7 @@
__weak void flush_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_flush(start, end);
}
__weak void invalidate_icache_range(unsigned long start, unsigned long end)
@@ -30,6 +123,7 @@
__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_inval(start, end);
}
void cache_flush(void)
@@ -72,4 +166,6 @@
__weak void enable_caches(void)
{
+ if (!riscv_zicbom_init())
+ log_info("Zicbom not initialized.\n");
}
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index c658e72..6dfd1a2 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -142,7 +142,7 @@
size = fdt_totalsize(blob);
err = fdt_open_into(blob, blob, size + 32);
if (err < 0) {
- log_err("Device Tree can't be expanded to accommodate new node");
+ log_err("Device-tree can't be expanded to accommodate new node\n");
return err;
}
chosen_offset = fdt_path_offset(blob, "/chosen");
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 714cc92..ef1056e 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -22,11 +22,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct resume_data *resume;
-
void set_resume(struct resume_data *data)
{
- resume = data;
+ gd->arch.resume = data;
}
static void show_efi_loaded_images(uintptr_t epc)
@@ -138,9 +136,9 @@
"Store/AMO page fault",
};
- if (resume) {
- resume->code = code;
- longjmp(resume->jump, 1);
+ if (gd->arch.resume) {
+ gd->arch.resume->code = code;
+ longjmp(gd->arch.resume->jump, 1);
}
if (code < ARRAY_SIZE(exception_code))
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 06f8c13..d1c4dcf 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -253,6 +253,19 @@
return mentry->tag;
}
+void sandbox_map_list(void)
+{
+ struct sandbox_mapmem_entry *mentry;
+ struct sandbox_state *state = state_get_current();
+
+ printf("Sandbox memory-mapping\n");
+ printf("%8s %16s %6s\n", "Addr", "Mapping", "Refcnt");
+ list_for_each_entry(mentry, &state->mapmem_head, sibling_node) {
+ printf("%8lx %p %6d\n", mentry->tag, mentry->ptr,
+ mentry->refcnt);
+ }
+}
+
unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size)
{
struct sandbox_state *state = state_get_current();
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index c50df5f..7056cfd 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -55,9 +55,10 @@
void board_boot_order(u32 *spl_boot_list)
{
+ struct sandbox_state *state = state_get_current();
+
spl_boot_list[0] = BOOT_DEVICE_VBE;
- spl_boot_list[1] = BOOT_DEVICE_UPL;
- spl_boot_list[2] = BOOT_DEVICE_BOARD;
+ spl_boot_list[1] = state->upl ? BOOT_DEVICE_UPL : BOOT_DEVICE_BOARD;
}
static int spl_board_load_file(struct spl_image_info *spl_image,
diff --git a/arch/sandbox/dts/cedit.dtsi b/arch/sandbox/dts/cedit.dtsi
index 9bd84e6..facd7a4 100644
--- a/arch/sandbox/dts/cedit.dtsi
+++ b/arch/sandbox/dts/cedit.dtsi
@@ -39,6 +39,9 @@
/* IDs for the menu items */
item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
ID_CPU_SPEED_3>;
+
+ /* values for the menu items */
+ item-value = <0 3 6>;
};
power-loss {
diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi
index 565c382..ff2cb42 100644
--- a/arch/sandbox/dts/sandbox_pmic.dtsi
+++ b/arch/sandbox/dts/sandbox_pmic.dtsi
@@ -10,6 +10,7 @@
&sandbox_pmic {
compatible = "sandbox,pmic";
+ sandbox,emul = <&emul_pmic0>;
buck1 {
regulator-name = "SUPPLY_1.2V";
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9bf44ae..3017b33 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -527,6 +527,9 @@
};
f-test {
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irq>;
+ interrupts = <4 0>;
compatible = "denx,u-boot-fdt-test";
};
diff --git a/arch/sandbox/include/asm/cpu.h b/arch/sandbox/include/asm/cpu.h
index c97ac7b..682bb33 100644
--- a/arch/sandbox/include/asm/cpu.h
+++ b/arch/sandbox/include/asm/cpu.h
@@ -8,4 +8,7 @@
void cpu_sandbox_set_current(const char *name);
+/* show the mapping of sandbox addresses to pointers */
+void sandbox_map_list(void);
+
#endif /* __SANDBOX_CPU_H */
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index a23bd64..3d09170 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -235,7 +235,7 @@
* nomap_sysmem() - pass through an address unchanged
*
* This is used to indicate an address which should NOT be mapped, e.g. in
- * SMBIOS tables. Using this function instead of a case shows that the sandbox
+ * SMBIOS tables. Using this function instead of a cast shows that the sandbox
* conversion has been done
*/
static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len)
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index d7d15a5..5d7beb2 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,8 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += fdt_fixup.o interrupts.o
-obj-$(CONFIG_PCI) += pci_io.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-$(CONFIG_CMD_BOOTZ) += bootm.o
+obj-y += fdt_fixup.o interrupts.o
+obj-$(CONFIG_PCI) += pci_io.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTZ) += bootm.o
+obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o
diff --git a/arch/sandbox/lib/acpi_table.c b/arch/sandbox/lib/acpi_table.c
new file mode 100644
index 0000000..90bb96d
--- /dev/null
+++ b/arch/sandbox/lib/acpi_table.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <acpi/acpi_table.h>
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+}
+
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
+{
+ return ctx->current;
+}
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c
index 76230ae..93040e7 100644
--- a/arch/x86/cpu/apollolake/acpi.c
+++ b/arch/x86/cpu/apollolake/acpi.c
@@ -128,8 +128,10 @@
return MP_IRQ_POLARITY_LOW;
}
-void fill_fadt(struct acpi_fadt *fadt)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
+ intel_acpi_fill_fadt(fadt);
+
fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
@@ -143,23 +145,9 @@
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
-}
-
-static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- acpi_fadt_common(fadt, ctx->facs, ctx->dsdt);
- intel_acpi_fill_fadt(fadt);
- fill_fadt(fadt);
- header = &fadt->header;
- header->checksum = table_compute_checksum(fadt, header->length);
- return acpi_add_fadt(ctx, fadt);
+ fadt->preferred_pm_profile = ACPI_PM_MOBILE;
}
-ACPI_WRITER(5fadt, "FADT", apl_write_fadt, 0);
int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
{
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 7821964..7e1c2de 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -15,20 +15,13 @@
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int baytrail_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
struct acpi_table_header *header;
- struct acpi_fadt *fadt;
- fadt = ctx->current;
header = &fadt->header;
u16 pmbase = ACPI_BASE_ADDRESS;
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
header->revision = 4;
fadt->preferred_pm_profile = ACPI_PM_MOBILE;
@@ -77,9 +70,6 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
@@ -135,12 +125,7 @@
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 8746374..8127d31 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -88,18 +88,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- char processor_name[CPU_MAX_NAME_LEN];
- const char *name;
-
- /* Print processor name */
- name = cpu_get_name(processor_name);
- printf("CPU: %s\n", name);
-
- return 0;
-}
-
void board_debug_uart_init(void)
{
/* com1 / com2 decode range */
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c3d7442..fa7430b 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -38,16 +38,6 @@
return 0;
}
-int checkcpu(void)
-{
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return default_print_cpuinfo();
-}
-
static void board_final_init(void)
{
/*
@@ -82,6 +72,8 @@
static int last_stage_init(void)
{
+ timestamp_add_to_bootstage();
+
if (IS_ENABLED(CONFIG_XPL_BUILD))
return 0;
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index ec4003c..681191d 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -6,13 +6,12 @@
*/
#include <bootstage.h>
+#include <errno.h>
#include <asm/arch/timestamp.h>
#include <asm/cb_sysinfo.h>
#include <asm/u-boot-x86.h>
#include <linux/compiler.h>
-static struct timestamp_table *ts_table __section(".data");
-
void timestamp_init(void)
{
timestamp_add_now(TS_U_BOOT_INITTED);
@@ -20,6 +19,8 @@
void timestamp_add(enum timestamp_id id, uint64_t ts_time)
{
+ const struct sysinfo_t *info = cb_get_sysinfo();
+ struct timestamp_table *ts_table = info->tstamp_table;
struct timestamp_entry *tse;
if (!ts_table || (ts_table->num_entries == ts_table->max_entries))
@@ -37,13 +38,15 @@
int timestamp_add_to_bootstage(void)
{
+ const struct sysinfo_t *info = cb_get_sysinfo();
+ const struct timestamp_table *ts_table = info->tstamp_table;
uint i;
if (!ts_table)
- return -1;
+ return -ENOENT;
for (i = 0; i < ts_table->num_entries; i++) {
- struct timestamp_entry *tse = &ts_table->entries[i];
+ const struct timestamp_entry *tse = &ts_table->entries[i];
const char *name = NULL;
switch (tse->entry_id) {
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ea11b09..a8b2140 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -163,8 +163,11 @@
return ptr;
}
-int default_print_cpuinfo(void)
+#if !CONFIG_IS_ENABLED(CPU)
+int print_cpuinfo(void)
{
+ post_code(POST_CPU_INFO);
+
printf("CPU: %s, vendor %s, device %xh\n",
cpu_has_64bit() ? "x86_64" : "x86",
cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
@@ -176,6 +179,7 @@
return 0;
}
+#endif
#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
void show_boot_progress(int val)
@@ -336,7 +340,7 @@
}
#endif
-long detect_coreboot_table_at(ulong start, ulong size)
+static long detect_coreboot_table_at(ulong start, ulong size)
{
u32 *ptr, *end;
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
index 6c53f0e..6c32ae4 100644
--- a/arch/x86/cpu/cpu_x86.c
+++ b/arch/x86/cpu/cpu_x86.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <errno.h>
#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c
index 218a68c..84fe50e 100644
--- a/arch/x86/cpu/efi/app.c
+++ b/arch/x86/cpu/efi/app.c
@@ -19,11 +19,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- return default_print_cpuinfo();
-}
-
void board_final_init(void)
{
}
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 642a87a..6845ce7 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -144,11 +144,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- return default_print_cpuinfo();
-}
-
/* Find any available tables and copy them to a safe place */
int reserve_arch(void)
{
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index d837fb9..a51a244 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -263,6 +263,49 @@
}
#endif
+int x86_cpu_vendor_info(char *name)
+{
+ uint cpu_device;
+
+ cpu_device = 0;
+
+ /* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
+#ifndef CONFIG_TPL_BUILD
+ *name = '\0'; /* Unset */
+
+ /* Find the id and vendor_name */
+ if (!has_cpuid()) {
+ /* Its a 486 if we can modify the AC flag */
+ if (flag_is_changeable_p(X86_EFLAGS_AC))
+ cpu_device = 0x00000400; /* 486 */
+ else
+ cpu_device = 0x00000300; /* 386 */
+ if (cpu_device == 0x00000400 && test_cyrix_52div()) {
+ /* If we ever care we can enable cpuid here */
+ memcpy(name, "CyrixInstead", 13);
+
+ /* Detect NexGen with old hypercode */
+ } else if (deep_magic_nexgen_probe()) {
+ memcpy(name, "NexGenDriven", 13);
+ }
+ } else {
+ int cpuid_level;
+
+ cpuid_level = build_vendor_name(name);
+ name[12] = '\0';
+
+ /* Intel-defined flags: level 0x00000001 */
+ if (cpuid_level >= 0x00000001)
+ cpu_device = cpuid_eax(0x00000001);
+ else
+ /* Have CPUID level 0 only unheard of */
+ cpu_device = 0x00000400;
+ }
+#endif /* CONFIG_TPL_BUILD */
+
+ return cpu_device;
+}
+
static void identify_cpu(struct cpu_device_id *cpu)
{
cpu->device = 0; /* fix gcc 4.4.4 warning */
@@ -289,48 +332,21 @@
return;
}
-/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
- char vendor_name[16];
- int i;
+ {
+ char vendor_name[16];
+ int i;
- vendor_name[0] = '\0'; /* Unset */
+ cpu->device = x86_cpu_vendor_info(vendor_name);
- /* Find the id and vendor_name */
- if (!has_cpuid()) {
- /* Its a 486 if we can modify the AC flag */
- if (flag_is_changeable_p(X86_EFLAGS_AC))
- cpu->device = 0x00000400; /* 486 */
- else
- cpu->device = 0x00000300; /* 386 */
- if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
- memcpy(vendor_name, "CyrixInstead", 13);
- /* If we ever care we can enable cpuid here */
- }
- /* Detect NexGen with old hypercode */
- else if (deep_magic_nexgen_probe())
- memcpy(vendor_name, "NexGenDriven", 13);
- } else {
- int cpuid_level;
-
- cpuid_level = build_vendor_name(vendor_name);
- vendor_name[12] = '\0';
-
- /* Intel-defined flags: level 0x00000001 */
- if (cpuid_level >= 0x00000001) {
- cpu->device = cpuid_eax(0x00000001);
- } else {
- /* Have CPUID level 0 only unheard of */
- cpu->device = 0x00000400;
+ cpu->vendor = X86_VENDOR_UNKNOWN;
+ for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
+ if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
+ cpu->vendor = x86_vendors[i].vendor;
+ break;
+ }
}
}
- cpu->vendor = X86_VENDOR_UNKNOWN;
- for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
- if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
- cpu->vendor = x86_vendors[i].vendor;
- break;
- }
- }
#endif
}
@@ -485,6 +501,11 @@
return 0;
}
+void x86_get_identity_for_timer(void)
+{
+ setup_identity();
+}
+
void x86_enable_caches(void)
{
unsigned long cr0;
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index b3f4214..6f78b07 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -237,7 +237,7 @@
return &idt_ptr;
}
-void __do_irq(int irq)
+static void __do_irq(int irq)
{
printf("Unhandled IRQ : %d\n", irq);
}
diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c
index 29676b4..982149b 100644
--- a/arch/x86/cpu/intel_common/acpi.c
+++ b/arch/x86/cpu/intel_common/acpi.c
@@ -19,6 +19,7 @@
#include <asm/global_data.h>
#include <asm/intel_acpi.h>
#include <asm/ioapic.h>
+#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/smm.h>
#include <asm/turbo.h>
@@ -80,33 +81,40 @@
return sci_irq;
}
-static unsigned long acpi_madt_irq_overrides(unsigned long current)
+static void *acpi_madt_irq_overrides(void *current)
{
int sci = acpi_sci_irq();
u16 flags = MP_IRQ_TRIGGER_LEVEL;
- if (sci < 0)
- return log_msg_ret("sci irq", sci);
+ if (sci < 0) {
+ log_err("sci irq %d", sci);
+ return current;
+ }
/* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride(current, 0, 0, 2, 0);
flags |= arch_madt_sci_irq_polarity(sci);
/* SCI */
current +=
- acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
+ acpi_create_madt_irqoverride(current, 0, sci, sci, flags);
return current;
}
-u32 acpi_fill_madt(u32 current)
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
/* Local APICs */
current += acpi_create_madt_lapics(current);
/* IOAPIC */
- current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic(current, 2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 05691a3..d299068 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -182,20 +182,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- char processor_name[CPU_MAX_NAME_LEN];
- const char *name;
-
- /* Print processor name */
- name = cpu_get_name(processor_name);
- printf("CPU: %s\n", name);
-
- post_code(POST_CPU_INFO);
-
- return 0;
-}
-
void board_debug_uart_init(void)
{
/* This enables the debug UART */
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 50cba5f..07ea891 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -87,7 +87,7 @@
}
}
-void mtrr_write_all(struct mtrr_info *info)
+static void mtrr_write_all(struct mtrr_info *info)
{
int reg_count = mtrr_get_var_count();
struct mtrr_state state;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 262584d..563f63e 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -109,12 +109,6 @@
{
return 0;
}
-
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
#endif
int arch_early_init_r(void)
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 80e9460..0fe5f2b 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -11,23 +11,14 @@
#include <asm/arch/iomap.h>
#include <linux/string.h>
-static int quark_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
u16 pmbase = ACPI_PM1_BASE_ADDRESS;
struct acpi_table_header *header;
- struct acpi_fadt *fadt;
- fadt = ctx->current;
header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
header->revision = 4;
- fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->acpi_enable = 0;
@@ -73,9 +64,6 @@
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
@@ -131,12 +119,7 @@
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", quark_write_fadt, 0);
int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index fdf92b2..07504fa 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -266,12 +266,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
static void quark_pcie_init(void)
{
u32 val;
diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c
index 142c934..8a5c785 100644
--- a/arch/x86/cpu/slimbootloader/slimbootloader.c
+++ b/arch/x86/cpu/slimbootloader/slimbootloader.c
@@ -54,8 +54,3 @@
{
return 0;
}
-
-int print_cpuinfo(void)
-{
- return default_print_cpuinfo();
-}
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index d4d0ef6..8ea764f 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -10,27 +10,15 @@
#include <mapmem.h>
#include <acpi/acpi_table.h>
#include <asm/ioapic.h>
+#include <asm/lapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
#include <dm/uclass-internal.h>
-static int tangier_write_fadt(struct acpi_ctx *ctx,
- const struct acpi_writer *entry)
+void acpi_fill_fadt(struct acpi_fadt *fadt)
{
- struct acpi_table_header *header;
- struct acpi_fadt *fadt;
-
- fadt = ctx->current;
- header = &fadt->header;
-
- memset(fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
- header->revision = 6;
-
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
@@ -40,20 +28,15 @@
ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_HEADLESS |
ACPI_FADT_HW_REDUCED_ACPI;
-
- fadt->minor_revision = 2;
-
- fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
- fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
-
- header->checksum = table_compute_checksum(fadt, header->length);
-
- return acpi_add_fadt(ctx, fadt);
}
-ACPI_WRITER(5fadt, "FADT", tangier_write_fadt, 0);
-u32 acpi_fill_madt(u32 current)
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c
index 8a8f7d2..b005bc7 100644
--- a/arch/x86/cpu/tangier/tangier.c
+++ b/arch/x86/cpu/tangier/tangier.c
@@ -19,8 +19,3 @@
{
return 0;
}
-
-int print_cpuinfo(void)
-{
- return default_print_cpuinfo();
-}
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 80eab71..71bc07f 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -75,3 +75,9 @@
/* this was already done in SPL */
}
#endif
+
+void x86_get_identity_for_timer(void)
+{
+ /* set the vendor to Intel so that native_calibrate_tsc() works */
+ gd->arch.x86_vendor = X86_VENDOR_INTEL;
+}
diff --git a/arch/x86/cpu/x86_64/misc.c b/arch/x86/cpu/x86_64/misc.c
index 294511e..fc449ca 100644
--- a/arch/x86/cpu/x86_64/misc.c
+++ b/arch/x86/cpu/x86_64/misc.c
@@ -32,9 +32,4 @@
{
return 0;
}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
#endif
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index b867468..39d1d32 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -54,6 +54,13 @@
menu-inset = <3>;
menuitem-gap-y = <1>;
};
+
+ cedit-theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ menu-title-margin-x = <30>;
+ };
};
sysinfo {
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 57e4165..ff60384 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -24,16 +24,13 @@
/* These can be used by the target port */
-int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_lapics(void *current);
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
u32 addr, u32 gsi_base);
int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
u8 bus, u8 source, u32 gsirq, u16 flags);
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
-u32 acpi_fill_madt(u32 current);
-int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
- u16 seg_nr, u8 start, u8 end);
/**
* acpi_write_hpet() - Write out a HPET table
@@ -46,17 +43,6 @@
int acpi_write_hpet(struct acpi_ctx *ctx);
/**
- * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
- *
- * @ctx: Current ACPI context
- * @dev: Debug UART device to describe
- * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
- * Return: 0 if OK, -ve on error
- */
-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
- uint access_size);
-
-/**
* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
*
* @gnvs: Table to fill in
@@ -180,18 +166,6 @@
pci_dev_t bdf);
/**
- * acpi_fadt_common() - Handle common parts of filling out an FADT
- *
- * This sets up the Fixed ACPI Description Table
- *
- * @fadt: Pointer to place to put FADT
- * @facs: Pointer to the FACS
- * @dsdt: Pointer to the DSDT
- */
-void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt);
-
-/**
* intel_acpi_fill_fadt() - Set up the contents of the FADT
*
* This sets up parts of the Fixed ACPI Description Table that are common to
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 87e0c6f..8c1ef4c 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -293,4 +293,11 @@
*/
int cpu_phys_address_size(void);
+void board_final_init(void);
+void board_final_cleanup(void);
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void);
+#endif
+
#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 3acc58a..ed2f6aa 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -44,6 +44,15 @@
int x86_cpu_init_tpl(void);
/**
+ * x86_get_identity_for_timer() - Set up CPU identity for use by the early timer
+ *
+ * The timer can be needed early in board_f if bootstage is enabled. This
+ * function can be called from the TSC timer to make sure that the CPU-identity
+ * info has been set up
+ */
+void x86_get_identity_for_timer(void);
+
+/**
* cpu_reinit_fpu() - Reinit the FPU if something is wrong with it
*
* The FSP-M code can leave registers in use in the FPU. This functions reinits
@@ -51,6 +60,14 @@
*/
void cpu_reinit_fpu(void);
+/**
+ * x86_cpu_vendor_info() - Get the CPU-vendor name and device number
+ *
+ * @name: 13-byte area to hold the returned string
+ * Return: CPU device number read from cpuid
+ */
+int x86_cpu_vendor_info(char *name);
+
int cpu_init_f(void);
void setup_gdt(struct global_data *id, u64 *gdt_addr);
/*
@@ -78,7 +95,6 @@
void x86_disable_caches(void);
int x86_init_cache(void);
phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
-int default_print_cpuinfo(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
int setup_internal_uart(int enable);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 7677c0c..43e6a1d 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -97,7 +97,7 @@
else
ifndef CONFIG_XPL_BUILD
-ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_BOOTEFI_HELLO_COMPILE),)
extra-y += $(EFI_CRT0) $(EFI_RELOC)
endif
endif
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index e38ce19..3186e48 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -40,7 +40,7 @@
return lapic->length;
}
-int acpi_create_madt_lapics(u32 current)
+int acpi_create_madt_lapics(void *current)
{
struct udevice *dev;
int total_length = 0;
@@ -100,23 +100,28 @@
return lapic_nmi->length;
}
-static int acpi_create_madt_irq_overrides(u32 current)
+static int acpi_create_madt_irq_overrides(void *current)
{
struct acpi_madt_irqoverride *irqovr;
u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
int length = 0;
- irqovr = (void *)current;
+ irqovr = current;
length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
- irqovr = (void *)(current + length);
+ irqovr = current + length;
length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
return length;
}
-__weak u32 acpi_fill_madt(u32 current)
+__weak void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx)
{
+ void *current = ctx->current;
+
+ madt->lapic_addr = LAPIC_DEFAULT_BASE;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
+
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
@@ -127,39 +132,6 @@
return current;
}
-int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct acpi_table_header *header;
- struct acpi_madt *madt;
- u32 current;
-
- madt = ctx->current;
-
- memset(madt, '\0', sizeof(struct acpi_madt));
- header = &madt->header;
-
- /* Fill out header fields */
- acpi_fill_header(header, "APIC");
- header->length = sizeof(struct acpi_madt);
- header->revision = ACPI_MADT_REV_ACPI_3_0;
-
- madt->lapic_addr = LAPIC_DEFAULT_BASE;
- madt->flags = ACPI_MADT_PCAT_COMPAT;
-
- current = (u32)madt + sizeof(struct acpi_madt);
- current = acpi_fill_madt(current);
-
- /* (Re)calculate length and checksum */
- header->length = current - (u32)madt;
-
- header->checksum = table_compute_checksum((void *)madt, header->length);
- acpi_add_table(ctx, madt);
- acpi_inc(ctx, madt->header.length);
-
- return 0;
-}
-ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
-
/**
* acpi_create_tcpa() - Create a TCPA table
*
@@ -279,140 +251,6 @@
}
ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
-int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
-{
- struct serial_device_info serial_info = {0};
- ulong serial_address, serial_offset;
- struct acpi_table_header *header;
- struct acpi_spcr *spcr;
- struct udevice *dev;
- uint serial_config;
- uint serial_width;
- int access_size;
- int space_id;
- int ret = -ENODEV;
-
- spcr = ctx->current;
- header = &spcr->header;
-
- memset(spcr, '\0', sizeof(struct acpi_spcr));
-
- /* Fill out header fields */
- acpi_fill_header(header, "SPCR");
- header->length = sizeof(struct acpi_spcr);
- header->revision = 2;
-
- /* Read the device once, here. It is reused below */
- dev = gd->cur_serial_dev;
- if (dev)
- ret = serial_getinfo(dev, &serial_info);
- if (ret)
- serial_info.type = SERIAL_CHIP_UNKNOWN;
-
- /* Encode chip type */
- switch (serial_info.type) {
- case SERIAL_CHIP_16550_COMPATIBLE:
- spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
- break;
- case SERIAL_CHIP_UNKNOWN:
- default:
- spcr->interface_type = ACPI_DBG2_UNKNOWN;
- break;
- }
-
- /* Encode address space */
- switch (serial_info.addr_space) {
- case SERIAL_ADDRESS_SPACE_MEMORY:
- space_id = ACPI_ADDRESS_SPACE_MEMORY;
- break;
- case SERIAL_ADDRESS_SPACE_IO:
- default:
- space_id = ACPI_ADDRESS_SPACE_IO;
- break;
- }
-
- serial_width = serial_info.reg_width * 8;
- serial_offset = serial_info.reg_offset << serial_info.reg_shift;
- serial_address = serial_info.addr + serial_offset;
-
- /* Encode register access size */
- switch (serial_info.reg_shift) {
- case 0:
- access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- break;
- case 1:
- access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
- break;
- case 2:
- access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
- break;
- case 3:
- access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
- break;
- default:
- access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- break;
- }
-
- debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
-
- /* Fill GAS */
- spcr->serial_port.space_id = space_id;
- spcr->serial_port.bit_width = serial_width;
- spcr->serial_port.bit_offset = 0;
- spcr->serial_port.access_size = access_size;
- spcr->serial_port.addrl = lower_32_bits(serial_address);
- spcr->serial_port.addrh = upper_32_bits(serial_address);
-
- /* Encode baud rate */
- switch (serial_info.baudrate) {
- case 9600:
- spcr->baud_rate = 3;
- break;
- case 19200:
- spcr->baud_rate = 4;
- break;
- case 57600:
- spcr->baud_rate = 6;
- break;
- case 115200:
- spcr->baud_rate = 7;
- break;
- default:
- spcr->baud_rate = 0;
- break;
- }
-
- serial_config = SERIAL_DEFAULT_CONFIG;
- if (dev)
- ret = serial_getconfig(dev, &serial_config);
-
- spcr->parity = SERIAL_GET_PARITY(serial_config);
- spcr->stop_bits = SERIAL_GET_STOP(serial_config);
-
- /* No PCI devices for now */
- spcr->pci_device_id = 0xffff;
- spcr->pci_vendor_id = 0xffff;
-
- /*
- * SPCR has no clue if the UART base clock speed is different
- * to the default one. However, the SPCR 1.04 defines baud rate
- * 0 as a preconfigured state of UART and OS is supposed not
- * to touch the configuration of the serial device.
- */
- if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
- spcr->baud_rate = 0;
-
- /* Fix checksum */
- header->checksum = table_compute_checksum((void *)spcr, header->length);
-
- acpi_add_table(ctx, spcr);
- acpi_inc(ctx, spcr->header.length);
-
- return 0;
-}
-ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
-
int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
{
ulong addr;
@@ -515,69 +353,6 @@
return 0;
}
-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
- uint access_size)
-{
- struct acpi_dbg2_header *dbg2 = ctx->current;
- char path[ACPI_PATH_MAX];
- struct acpi_gen_regaddr address;
- phys_addr_t addr;
- int ret;
-
- if (!device_active(dev)) {
- log_info("Device not enabled\n");
- return -EACCES;
- }
- /*
- * PCI devices don't remember their resource allocation information in
- * U-Boot at present. We assume that MMIO is used for the UART and that
- * the address space is 32 bytes: ns16550 uses 8 registers of up to
- * 32-bits each. This is only for debugging so it is not a big deal.
- */
- addr = dm_pci_read_bar32(dev, 0);
- log_debug("UART addr %lx\n", (ulong)addr);
-
- memset(&address, '\0', sizeof(address));
- address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- address.addrl = (uint32_t)addr;
- address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
- address.access_size = access_size;
-
- ret = acpi_device_path(dev, path, sizeof(path));
- if (ret)
- return log_msg_ret("path", ret);
- acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
- ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
-
- acpi_inc_align(ctx, dbg2->header.length);
- acpi_add_table(ctx, dbg2);
-
- return 0;
-}
-
-void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
-{
- struct acpi_table_header *header = &fadt->header;
-
- memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
-
- acpi_fill_header(header, "FACP");
- header->length = sizeof(struct acpi_fadt);
- header->revision = 4;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
- memcpy(header->creator_id, ASLC_ID, 4);
-
- fadt->x_firmware_ctrl = map_to_sysmem(facs);
- fadt->x_dsdt = map_to_sysmem(dsdt);
-
- fadt->preferred_pm_profile = ACPI_PM_MOBILE;
-
- /* Use ACPI 3.0 revision */
- fadt->header.revision = 4;
-}
-
void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
u64 bar)
{
diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c
index 165e8ab..2a78f57 100644
--- a/arch/x86/lib/bdinfo.c
+++ b/arch/x86/lib/bdinfo.c
@@ -19,7 +19,12 @@
bdinfo_print_num_l("clock_rate", gd->arch.clock_rate);
bdinfo_print_num_l("tsc_base", gd->arch.tsc_base);
bdinfo_print_num_l("vendor", gd->arch.x86_vendor);
- bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor));
+ if (!IS_ENABLED(CONFIG_X86_64)) {
+ char vendor_name[16];
+
+ x86_cpu_vendor_info(vendor_name);
+ bdinfo_print_str(" name", vendor_name);
+ }
bdinfo_print_num_l("model", gd->arch.x86_model);
bdinfo_print_num_l("phys_addr in bits", cpu_phys_address_size());
bdinfo_print_num_l("table start", gd->arch.table_start);
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index c47e6ca..7e4c147 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -26,12 +26,6 @@
return 0;
}
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
int fsp_init_phase_pci(void)
{
u32 status;
diff --git a/board/anbernic/rgxx3_rk3566/MAINTAINERS b/board/anbernic/rgxx3_rk3566/MAINTAINERS
index 7970e5a..75a1e80 100644
--- a/board/anbernic/rgxx3_rk3566/MAINTAINERS
+++ b/board/anbernic/rgxx3_rk3566/MAINTAINERS
@@ -4,6 +4,4 @@
F: board/anbernic/rgxx3_rk3566
F: include/configs/anbernic-rgxx3-rk3566.h
F: configs/anbernic-rgxx3-rk3566_defconfig
-F: arch/arm/dts/rk3566-anbernic-rgxx3.dts
-F: arch/arm/dts/rk3566-anbernic-rgxx3.dtsi
-F: arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+F: arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index 5c57b90..c1d1826 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -11,6 +11,7 @@
#include <dm/lists.h>
#include <env.h>
#include <fdt_support.h>
+#include <i2c.h>
#include <linux/delay.h>
#include <mipi_dsi.h>
#include <mmc.h>
@@ -19,6 +20,8 @@
#include <stdlib.h>
#include <video_bridge.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define GPIO0_BASE 0xfdd60000
#define GPIO4_BASE 0xfe770000
#define GPIO_SWPORT_DR_L 0x0000
@@ -40,10 +43,12 @@
const char *board_name;
const char *fdtfile;
const bool detect_panel;
+ const bool detect_regulator;
+ const bool uart_con;
};
enum rgxx3_device_id {
- RG353M,
+ RG353M = 1,
RG353P,
RG353V,
RG503,
@@ -61,45 +66,57 @@
[RG353M] = {
.adc_value = 517, /* Observed average from device */
.board = "rk3566-anbernic-rg353m",
- .board_name = "RG353M",
+ .board_name = "Anbernic RG353M",
/* Device is identical to RG353P. */
.fdtfile = DTB_DIR "rk3566-anbernic-rg353p.dtb",
.detect_panel = 1,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RG353P] = {
.adc_value = 860, /* Documented value of 860 */
.board = "rk3566-anbernic-rg353p",
- .board_name = "RG353P",
+ .board_name = "Anbernic RG353P",
.fdtfile = DTB_DIR "rk3566-anbernic-rg353p.dtb",
.detect_panel = 1,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RG353V] = {
.adc_value = 695, /* Observed average from device */
.board = "rk3566-anbernic-rg353v",
- .board_name = "RG353V",
+ .board_name = "Anbernic RG353V",
.fdtfile = DTB_DIR "rk3566-anbernic-rg353v.dtb",
.detect_panel = 1,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RG503] = {
.adc_value = 1023, /* Observed average from device */
.board = "rk3566-anbernic-rg503",
- .board_name = "RG503",
+ .board_name = "Anbernic RG503",
.fdtfile = DTB_DIR "rk3566-anbernic-rg503.dtb",
.detect_panel = 0,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RGB30] = {
.adc_value = 383, /* Gathered from second hand information */
.board = "rk3566-powkiddy-rgb30",
- .board_name = "RGB30",
+ .board_name = "Powkiddy RGB30",
.fdtfile = DTB_DIR "rk3566-powkiddy-rgb30.dtb",
.detect_panel = 0,
+ .detect_regulator = 1,
+ .uart_con = 0,
},
[RK2023] = {
.adc_value = 635, /* Observed average from device */
.board = "rk3566-powkiddy-rk2023",
- .board_name = "RK2023",
+ .board_name = "Powkiddy RK2023",
.fdtfile = DTB_DIR "rk3566-powkiddy-rk2023.dtb",
.detect_panel = 0,
+ .detect_regulator = 1,
+ .uart_con = 0,
},
[RGARCD] = {
.adc_value = 183, /* Observed average from device */
@@ -107,6 +124,8 @@
.board_name = "Anbernic RG ARC-D",
.fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-d.dtb",
.detect_panel = 0,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RGB10MAX3] = {
.adc_value = 765, /* Observed average from device */
@@ -114,21 +133,27 @@
.board_name = "Powkiddy RGB10MAX3",
.fdtfile = DTB_DIR "rk3566-powkiddy-rgb10max3.dtb",
.detect_panel = 0,
+ .detect_regulator = 1,
+ .uart_con = 0,
},
/* Devices with duplicate ADC value */
[RG353PS] = {
.adc_value = 860, /* Observed average from device */
.board = "rk3566-anbernic-rg353ps",
- .board_name = "RG353PS",
+ .board_name = "Anbernic RG353PS",
.fdtfile = DTB_DIR "rk3566-anbernic-rg353ps.dtb",
.detect_panel = 1,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RG353VS] = {
.adc_value = 695, /* Gathered from second hand information */
.board = "rk3566-anbernic-rg353vs",
- .board_name = "RG353VS",
+ .board_name = "Anbernic RG353VS",
.fdtfile = DTB_DIR "rk3566-anbernic-rg353vs.dtb",
.detect_panel = 1,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
[RGARCS] = {
.adc_value = 183, /* Observed average from device */
@@ -136,6 +161,8 @@
.board_name = "Anbernic RG ARC-S",
.fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-s.dtb",
.detect_panel = 0,
+ .detect_regulator = 0,
+ .uart_con = 1,
},
};
@@ -157,6 +184,22 @@
},
};
+struct powkiddy_regulators {
+ const u8 addr;
+ const char *regulator_compat;
+};
+
+static const struct powkiddy_regulators regulator_details[] = {
+ {
+ .addr = 0x1c,
+ .regulator_compat = "tcs,tcs4525",
+ },
+ {
+ .addr = 0x40,
+ .regulator_compat = "fcs,fan53555",
+ },
+};
+
/*
* Start LED very early so user knows device is on. Set color
* to red.
@@ -164,7 +207,7 @@
void spl_board_init(void)
{
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
- writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
+ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) |
(GPIO_C7 | GPIO_C6 | GPIO_C5),
(GPIO0_BASE + GPIO_SWPORT_DDR_H));
/* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */
@@ -174,16 +217,22 @@
/*
* Buzz the buzzer so the user knows something is going on. Make it
- * optional in case PWM is disabled.
+ * optional in case PWM is disabled or if CONFIG_DM_PWM is not
+ * enabled.
*/
void __maybe_unused startup_buzz(void)
{
struct udevice *dev;
int err;
- err = uclass_get_device(UCLASS_PWM, 0, &dev);
+ if (!IS_ENABLED(CONFIG_DM_PWM))
+ return;
+
+ /* Probe the PWM controller. */
+ err = uclass_get_device_by_name(UCLASS_PWM,
+ "pwm@fe6e0010", &dev);
if (err)
- printf("pwm not found\n");
+ return;
pwm_set_enable(dev, 0, 1);
mdelay(200);
@@ -245,6 +294,13 @@
.plat_auto = sizeof(struct mipi_dsi_panel_plat),
};
+/*
+ * The Anbernic 353 series shipped with 2 distinct displays requiring
+ * 2 distinct drivers, with no way for a user to know which panel is
+ * which. This function queries the DSI panel for the panel ID to
+ * determine which panel is present so the device-tree can be corrected
+ * automatically.
+ */
int rgxx3_detect_display(void)
{
struct udevice *dev;
@@ -333,17 +389,48 @@
return 0;
}
-/* Detect which Anbernic RGXX3 device we are using so as to load the
- * correct devicetree for Linux. Set an environment variable once
- * found. The detection depends on the value of ADC channel 1, the
- * presence of an eMMC on mmc0, and querying the DSI panel.
+/*
+ * Some of the Powkiddy devices switched the CPU regulator, but users
+ * are not able to determine this by looking at their hardware.
+ * Attempt to auto-detect this situation and fixup the device-tree.
*/
-int rgxx3_detect_device(void)
+int rgxx3_detect_regulator(void)
+{
+ struct udevice *bus;
+ struct udevice *chip;
+ u8 val;
+ int ret;
+
+ /* Get the correct i2c bus (i2c0). */
+ ret = uclass_get_device_by_name(UCLASS_I2C,
+ "i2c@fdd40000", &bus);
+ if (ret)
+ return ret;
+
+ /*
+ * Check for all vdd_cpu regulators and read an arbitrary
+ * register to confirm it's present.
+ */
+ for (int i = 0; i < ARRAY_SIZE(regulator_details); i++) {
+ ret = i2c_get_chip(bus, regulator_details[i].addr,
+ 1, &chip);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_read(chip, 0, &val, 1);
+ if (!ret) {
+ env_set("vdd_cpu", regulator_details[i].regulator_compat);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int rgxx3_read_board_id(void)
{
u32 adc_info;
- int ret, i;
- int board_id = -ENXIO;
- struct mmc *mmc;
+ int ret;
ret = adc_channel_single_shot("saradc@fe720000", 1, &adc_info);
if (ret) {
@@ -357,16 +444,32 @@
* design calls for no more than a 1% variance on the
* resistor, so assume a +- value of 15 should be enough.
*/
- for (i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) {
+ for (int i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) {
u32 adc_min = rg3xx_model_details[i].adc_value - 15;
u32 adc_max = rg3xx_model_details[i].adc_value + 15;
- if (adc_min < adc_info && adc_max > adc_info) {
- board_id = i;
- break;
- }
+ if (adc_min < adc_info && adc_max > adc_info)
+ return i;
}
+ return -ENODEV;
+}
+
+/* Detect which Anbernic RGXX3 device we are using so as to load the
+ * correct devicetree for Linux. Set an environment variable once
+ * found. The detection depends on the value of ADC channel 1 and the
+ * presence of an eMMC on mmc0.
+ */
+int rgxx3_detect_device(void)
+{
+ int ret;
+ int board_id;
+ struct mmc *mmc;
+
+ board_id = rgxx3_read_board_id();
+ if (board_id < 0)
+ return board_id;
+
/*
* Try to access the eMMC on an RG353V, RG353P, or RG Arc D.
* If it's missing, it's an RG353VS, RG353PS, or RG Arc S.
@@ -387,67 +490,97 @@
}
}
- if (board_id < 0)
- return board_id;
+ return board_id;
+}
- env_set("board", rg3xx_model_details[board_id].board);
- env_set("board_name",
- rg3xx_model_details[board_id].board_name);
- env_set("fdtfile", rg3xx_model_details[board_id].fdtfile);
+/*
+ * Check the loaded device tree to set the correct gd->board_type.
+ * Disable the console if the board doesn't support a console.
+ */
+int set_gd_value(void)
+{
+ const char *model;
- /* Skip panel detection for when it is not needed. */
- if (!rg3xx_model_details[board_id].detect_panel)
- return 0;
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- /* Warn but don't fail for errors in auto-detection of the panel. */
- ret = rgxx3_detect_display();
- if (ret)
- printf("Failed to detect panel type\n");
+ for (int i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) {
+ if (strcmp(rg3xx_model_details[i].board_name, model) == 0) {
+ gd->board_type = i;
+ if (!rg3xx_model_details[i].uart_con)
+ gd->flags |= GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE;
+ return 0;
+ }
+ }
- return 0;
+ return -ENODEV;
}
int rk_board_late_init(void)
{
int ret;
- ret = rgxx3_detect_device();
+ ret = set_gd_value();
if (ret) {
- printf("Unable to detect device type: %d\n", ret);
- return ret;
+ printf("Unable to auto-detect device\n");
+ goto end;
+ }
+
+ /*
+ * Change the model number on the RG353M since it uses the same
+ * tree as the RG353P.
+ */
+ if (gd->board_type == RG353P) {
+ ret = rgxx3_read_board_id();
+ if (ret > 0)
+ gd->board_type = ret;
+ }
+
+ env_set("board", rg3xx_model_details[gd->board_type].board);
+ env_set("board_name",
+ rg3xx_model_details[gd->board_type].board_name);
+ env_set("fdtfile", rg3xx_model_details[gd->board_type].fdtfile);
+
+ /*
+ * Skip panel detection if not needed. Warn but don't fail for
+ * errors in auto-detection of the panel.
+ */
+ if (rg3xx_model_details[gd->board_type].detect_panel) {
+ ret = rgxx3_detect_display();
+ if (ret)
+ printf("Failed to detect panel type\n");
+ }
+
+ /*
+ * Skip vdd_cpu regulator detection if not needed. Warn but
+ * don't fail for errors in auto-detection of regulator.
+ */
+ if (rg3xx_model_details[gd->board_type].detect_regulator) {
+ ret = rgxx3_detect_regulator();
+ if (ret)
+ printf("Unable to detect vdd_cpu regulator\n");
}
+end:
/* Turn off red LED and turn on orange LED. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C6,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
- if (IS_ENABLED(CONFIG_DM_PWM))
- startup_buzz();
+ startup_buzz();
return 0;
}
-int ft_board_setup(void *blob, struct bd_info *bd)
+int rgxx3_panel_fixup(void *blob)
{
const struct rg353_panel *panel = NULL;
- int node, ret, i;
+ int node, ret;
char *env;
- /* No fixups necessary for the RG503 */
- env = env_get("board_name");
- if (env && (!strcmp(env, rg3xx_model_details[RG503].board_name)))
- return 0;
-
- /* Change the model name of the RG353M */
- if (env && (!strcmp(env, rg3xx_model_details[RG353M].board_name)))
- fdt_setprop(blob, 0, "model",
- rg3xx_model_details[RG353M].board_name,
- sizeof(rg3xx_model_details[RG353M].board_name));
-
env = env_get("panel");
if (!env) {
printf("Can't get panel env\n");
- return 0;
+ return -EINVAL;
}
/*
@@ -469,7 +602,7 @@
return 0;
/* Panels don't match, search by first compatible value. */
- for (i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) {
+ for (int i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) {
if (!strcmp(env, rg353_panel_details[i].panel_compat[0])) {
panel = &rg353_panel_details[i];
break;
@@ -489,3 +622,109 @@
return 0;
}
+
+int rgxx3_regulator_fixup(void *blob)
+{
+ const struct powkiddy_regulators *vdd_cpu = NULL;
+ int node, ret, i;
+ char path[] = "/i2c@fdd40000/regulator@00";
+ char name[] = "regulator@00";
+ char *env;
+
+ env = env_get("vdd_cpu");
+ if (!env) {
+ printf("Can't get vdd_cpu env\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Find the device we have in our tree, which may or may not
+ * be present.
+ */
+ for (i = 0; i < ARRAY_SIZE(regulator_details); i++) {
+ sprintf(path, "/i2c@fdd40000/regulator@%02x",
+ regulator_details[i].addr);
+ node = fdt_path_offset(blob, path);
+ if (node > 0)
+ break;
+
+ printf("Unable to find vdd_cpu\n");
+ return -ENODEV;
+ }
+
+ node = fdt_path_offset(blob, path);
+ if (!(node > 0)) {
+ printf("Can't find the vdd_cpu node\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_node_check_compatible(blob, node, env);
+ if (ret < 0)
+ return -ENODEV;
+
+ /* vdd_cpu regulators match, return 0. */
+ if (!ret)
+ return 0;
+
+ /* Regulators don't match, search by first compatible value. */
+ for (i = 0; i < ARRAY_SIZE(regulator_details); i++) {
+ if (!strcmp(env, regulator_details[i].regulator_compat)) {
+ vdd_cpu = ®ulator_details[i];
+ break;
+ }
+ }
+
+ if (!vdd_cpu) {
+ printf("Unable to identify vdd_cpu by compat string\n");
+ return -ENODEV;
+ }
+
+ /* Set the compatible and reg with the auto-detected values */
+ fdt_setprop_string(blob, node, "compatible", vdd_cpu->regulator_compat);
+ fdt_setprop_u32(blob, node, "reg", vdd_cpu->addr);
+ sprintf(name, "regulator@%02x", vdd_cpu->addr);
+ fdt_set_name(blob, node, name);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+
+ if (gd->board_type == RG353M)
+ fdt_setprop(blob, 0, "model",
+ rg3xx_model_details[RG353M].board_name,
+ sizeof(rg3xx_model_details[RG353M].board_name));
+
+ if (rg3xx_model_details[gd->board_type].detect_panel) {
+ ret = rgxx3_panel_fixup(blob);
+ if (ret)
+ printf("Unable to update panel compat\n");
+ }
+
+ if (rg3xx_model_details[gd->board_type].detect_regulator) {
+ ret = rgxx3_regulator_fixup(blob);
+ if (ret)
+ printf("Unable to update vdd_cpu compat\n");
+ }
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ int ret;
+
+ if (gd->board_type == 0) {
+ ret = rgxx3_detect_device();
+ if (ret < 0)
+ return ret;
+ gd->board_type = ret;
+ }
+
+ if (strcmp(name, rg3xx_model_details[gd->board_type].fdtfile) == 0)
+ return 0;
+
+ return -ENXIO;
+}
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
index 865588f..fdd5790 100644
--- a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
+++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
@@ -2,8 +2,5 @@
M: Marek Vasut <marex@denx.de>
L: u-boot@dh-electronics.com
S: Maintained
-F: arch/arm/dts/stm32mp15xx-dhcom*
-F: board/dhelectronics/dh_stm32mp1/
-F: configs/stm32mp15_dhcom_basic_defconfig
-F: configs/stm32mp15_dhcor_basic_defconfig
-F: include/configs/stm32mp15_dh_dhsom.h
+N: stm32mp.*dh[cs]o
+N: dh_stm32
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index a975fd2..d30171f 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -276,15 +276,26 @@
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
+ char *cdevice, *ndevice;
const char *compat;
- char test[128];
compat = ofnode_get_property(ofnode_root(), "compatible", NULL);
+ if (!compat)
+ return -EINVAL;
- snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
- compat, somcode, brdcode);
+ cdevice = strchr(compat, ',');
+ if (!cdevice)
+ return -ENODEV;
+
+ cdevice++; /* Move past the comma right after vendor prefix. */
+
+ ndevice = strchr(name, '/');
+ if (!ndevice)
+ return -ENODEV;
+
+ ndevice++; /* Move past the last slash in DT path */
- if (!strcmp(name, test))
+ if (!strcmp(cdevice, ndevice))
return 0;
return -EINVAL;
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
deleted file mode 100644
index 8eed9d0..0000000
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
+++ /dev/null
@@ -1,91 +0,0 @@
-/dts-v1/;
-
-/ {
- description = "U-Boot mainline";
- #address-cells = <1>;
-
- images {
- uboot {
- description = "U-Boot (32-bit)";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "arm";
- compression = "none";
- load = <0xc0100000>;
- entry = <0xc0100000>;
- };
-
- fdt-1 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
-
- fdt-2 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-drc02.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
-
- fdt-3 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
- };
-
- configurations {
- default = "config-1";
-
- config-1 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-pdk2_somrev0_boardrev0";
- firmware = "uboot";
- fdt = "fdt-1";
- };
-
- config-2 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-pdk2_somrev1_boardrev0";
- firmware = "uboot";
- fdt = "fdt-1";
- };
-
- config-3 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-drc02_somrev0_boardrev0";
- firmware = "uboot";
- fdt = "fdt-2";
- };
-
- config-4 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-drc02_somrev1_boardrev0";
- firmware = "uboot";
- fdt = "fdt-2";
- };
-
- config-5 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-picoitx_somrev0_boardrev0";
- loadables = "uboot";
- fdt = "fdt-3";
- };
-
- config-6 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcom-picoitx_somrev1_boardrev0";
- loadables = "uboot";
- fdt = "fdt-3";
- };
-
- /* Add 587-100..587-400 with fdt-2..fdt-4 here */
- };
-};
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
deleted file mode 100644
index f9c1075..0000000
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
+++ /dev/null
@@ -1,70 +0,0 @@
-/dts-v1/;
-
-/ {
- description = "U-Boot mainline";
- #address-cells = <1>;
-
- images {
- uboot {
- description = "U-Boot (32-bit)";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "arm";
- compression = "none";
- load = <0xc0100000>;
- entry = <0xc0100000>;
- };
-
- fdt-1 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
-
- fdt-2 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
-
- fdt-3 {
- description = ".dtb";
- data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb");
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- };
- };
-
- configurations {
- default = "config-1";
-
- config-1 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1";
- firmware = "uboot";
- fdt = "fdt-1";
- };
-
- config-2 {
- /* DT+SoM+board model */
- description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
- firmware = "uboot";
- fdt = "fdt-2";
- };
-
- config-3 {
- /* DT+SoM+board model */
- description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0";
- firmware = "uboot";
- fdt = "fdt-3";
- };
-
- /* Add 586-200..586-400 with fdt-2..fdt-4 here */
- };
-};
diff --git a/board/emcraft/imx8mp_navqp/Kconfig b/board/emcraft/imx8mp_navqp/Kconfig
new file mode 100644
index 0000000..20b09b6
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MP_NAVQP
+
+config SYS_BOARD
+ default "imx8mp_navqp"
+
+config SYS_VENDOR
+ default "emcraft"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_navqp"
+
+config IMX_CONFIG
+ default "board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg"
+
+endif
diff --git a/board/emcraft/imx8mp_navqp/MAINTAINERS b/board/emcraft/imx8mp_navqp/MAINTAINERS
new file mode 100644
index 0000000..d91605e
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/MAINTAINERS
@@ -0,0 +1,8 @@
+Emcraft Systems NavQ+ board (i.MX8M Plus)
+M: Gilles Talis <gilles.talis@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx8mp-navqp-u-boot.dtsi
+F: board/emcraft/imx8mp_navqp/
+F: configs/imx8mp_navqp_defconfig
+F: doc/board/emcraft/
+F: include/configs/imx8mp_navqp.h
diff --git a/board/emcraft/imx8mp_navqp/Makefile b/board/emcraft/imx8mp_navqp/Makefile
new file mode 100644
index 0000000..a5890b0
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2019 NXP
+# Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mp_navqp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c
new file mode 100644
index 0000000..219efdd
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env
new file mode 100644
index 0000000..c19fe08
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <config_distro_bootcmd.h>
+
+scriptaddr=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200
+fdt_addr_r=0x43000000
+boot_fdt=try
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+initrd_addr=0x43800000
+bootm_size=0x10000000
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
diff --git a/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg b/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg
new file mode 100644
index 0000000..0a23408
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/imximage-8mp-lpddr4.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021, 2024 NXP
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
diff --git a/board/emcraft/imx8mp_navqp/lpddr4_timing.c b/board/emcraft/imx8mp_navqp/lpddr4_timing.c
new file mode 100644
index 0000000..039ea3e
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/lpddr4_timing.c
@@ -0,0 +1,1842 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019, 2024 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1223 },
+ { 0x3d400024, 0x16e3600 },
+ { 0x3d400064, 0x5b011d },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x123 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x18 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x27 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0xa },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
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+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x34b },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x70 },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x1c },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/emcraft/imx8mp_navqp/spl.c b/board/emcraft/imx8mp_navqp/spl.c
new file mode 100644
index 0000000..7f30f3a
--- /dev/null
+++ b/board/emcraft/imx8mp_navqp/spl.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2018-2019, 2021 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("Failed to get PMIC\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * Increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85V for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+
+ /* Set DVS1 to 0.85v for suspend. */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+ /*
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /*
+ * Kernel uses OD/OD freq for SOC.
+ * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+ * voltage 0.95V.
+ */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ if (is_imx8mp() &&
+ !strcmp(name, "imx8mp-navqp"))
+ return 0;
+
+ return -EINVAL;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS
index 5154262..7bc0ee6 100644
--- a/board/emulation/qemu-arm/MAINTAINERS
+++ b/board/emulation/qemu-arm/MAINTAINERS
@@ -4,5 +4,7 @@
F: board/emulation/qemu-arm/
F: board/emulation/common/
F: include/configs/qemu-arm.h
+F: include/configs/qemu-sbsa.h
F: configs/qemu_arm_defconfig
F: configs/qemu_arm64_defconfig
+F: configs/qemu-arm-sbsa_defconfig
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 9538c66..012ac14 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -58,6 +58,8 @@
imply E1000
imply PCI
imply NVME_PCI
+ imply VIDEO
+ imply VIDEO_SIMPLE
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply DM_RTC
diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig
new file mode 100644
index 0000000..72c76b3
--- /dev/null
+++ b/board/emulation/qemu-sbsa/Kconfig
@@ -0,0 +1,59 @@
+if TARGET_QEMU_ARM_SBSA
+
+config SYS_SOC
+ default "qemu-sbsa"
+
+config TEXT_BASE
+ default 0x10000100000
+
+config SYS_LOAD_ADDR
+ default 0x10000100000
+
+config PRE_CON_BUF_ADDR
+ default 0x100000FF000
+
+config DEFAULT_DEVICE_TREE
+ default "qemu-sbsa"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select AHCI
+ select ACPIGEN
+ select ACPI
+ select BLOBLIST
+ select CPU
+ select CPU_ARMV8
+ select DM
+ select DM_USB
+ select DM_MTD
+ select GENERATE_ACPI_TABLE
+ select HAS_ROM
+ select MTD
+ select OF_LIBFDT_OVERLAY
+ select OF_SEPARATE
+ select PCI
+ select PCIE_ECAM_GENERIC
+ select USB
+ select GIC_V3
+ select GIC_V3_ITS
+ select SYS_FLASH_CFI_WIDTH_16BIT
+ imply AHCI_GENERIC
+ imply USB_XHCI_HCD
+ imply USB_XHCI_GENERIC
+ imply USB_STORAGE
+ imply E1000
+ imply E1000_NO_NVM
+ imply NET_RANDOM_ETHADDR
+ imply VIDEO_BOCHS
+ imply CFI_FLASH
+ imply SYS_MTDPARTS_RUNTIME
+ imply SET_DFU_ALT_INFO
+
+if DEBUG_UART
+
+config DEBUG_UART_BASE
+ default 0x60000000
+endif
+
+source "board/emulation/common/Kconfig"
+endif
diff --git a/board/emulation/qemu-sbsa/Makefile b/board/emulation/qemu-sbsa/Makefile
new file mode 100644
index 0000000..bacae32
--- /dev/null
+++ b/board/emulation/qemu-sbsa/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += qemu-sbsa.o
+obj-y += lowlevel_init.o
+obj-y += smc.o
+
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/board/emulation/qemu-sbsa/acpi.c b/board/emulation/qemu-sbsa/acpi.c
new file mode 100644
index 0000000..ba85e08
--- /dev/null
+++ b/board/emulation/qemu-sbsa/acpi.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <tables_csum.h>
+#include <string.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_table.h>
+#include <asm/armv8/sec_firmware.h>
+#include <configs/qemu-sbsa.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include "qemu-sbsa.h"
+
+#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000
+#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000
+#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
+
+#define SBSA_PLATFORM_WATCHDOG_COUNT 1
+#define SBSA_PLATFORM_TIMER_COUNT (SBSA_PLATFORM_WATCHDOG_COUNT)
+
+#define L2_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_UNIFIED << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L2_SIZE 0x80000
+#define L2_SETS 0x400
+#define L2_WAYS 8
+
+#define L1D_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | ACPI_PPTT_WRITE_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_DATA << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1D_SIZE 0x8000
+#define L1D_SETS 0x100
+#define L1D_WAYS 2
+
+#define L1I_ATTRIBUTES (ACPI_PPTT_READ_ALLOC | \
+ (ACPI_PPTT_CACHE_TYPE_INSTR << \
+ ACPI_PPTT_CACHE_TYPE_SHIFT))
+#define L1I_SIZE 0x8000
+#define L1I_SETS 0x100
+#define L1I_WAYS 2
+
+int acpi_fill_iort(struct acpi_ctx *ctx)
+{
+ u32 its_offset, smmu_offset;
+ u64 gic_its_base = 0;
+
+ smc_get_gic_its_base(&gic_its_base);
+ if (gic_its_base == 0)
+ return 0;
+
+ u32 identifiers[] = { 0 };
+
+ its_offset = acpi_iort_add_its_group(ctx, ARRAY_SIZE(identifiers),
+ identifiers);
+
+ struct acpi_iort_id_mapping map_smmu[] = {{
+ 0, 0xffff, 0, its_offset, 0
+ }};
+
+ smmu_offset = acpi_iort_add_smmu_v3(ctx,
+ SBSA_SMMU_BASE_ADDR, // Base address
+ ACPI_IORT_SMMU_V3_COHACC_OVERRIDE, // Flags
+ 0, // VATOS address
+ 0, // SMMUv3 Model
+ 74, // Event
+ 75, // Pri
+ 77, // Gerror
+ 76, // Sync
+ 0, // Proximity domain
+ 1, // DevIDMappingIndex
+ ARRAY_SIZE(map_smmu),
+ map_smmu);
+
+ struct acpi_iort_id_mapping map_rc[] = {{
+ 0, 0xffff, 0, smmu_offset, 0
+ }};
+
+ acpi_iort_add_rc(ctx,
+ BIT(0) | BIT(56), // CacheCoherent + CPM
+ 0, // AtsAttribute
+ 0, // PciSegmentNumber
+ 64, // MemoryAddressSizeLimit
+ ARRAY_SIZE(map_rc),
+ map_rc);
+ return 0;
+}
+
+void acpi_fill_fadt(struct acpi_fadt *fadt)
+{
+ fadt->flags = ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0;
+ fadt->preferred_pm_profile = ACPI_PM_PERFORMANCE_SERVER;
+ fadt->arm_boot_arch = ACPI_ARM_PSCI_COMPLIANT;
+}
+
+int acpi_fill_mcfg(struct acpi_ctx *ctx)
+{
+ size_t size;
+
+ /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+ size = acpi_create_mcfg_mmconfig((void *)ctx->current,
+ SBSA_PCIE_ECAM_BASE_ADDR, 0, 0, 255);
+ acpi_inc(ctx, size);
+
+ return 0;
+}
+
+static int sbsa_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_gtdt *gtdt;
+
+ gtdt = ctx->current;
+ header = >dt->header;
+
+ memset(gtdt, '\0', sizeof(struct acpi_gtdt));
+
+ acpi_fill_header(header, "GTDT");
+ header->length = sizeof(struct acpi_gtdt);
+ header->revision = acpi_get_table_revision(ACPITAB_GTDT);
+
+ gtdt->cnt_ctrl_base = 0xFFFFFFFFFFFFFFFF;
+ gtdt->sec_el1_gsiv = 29;
+ gtdt->sec_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el1_gsiv = 30;
+ gtdt->el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->virt_el1_gsiv = 27;
+ gtdt->virt_el1_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->el2_gsiv = 26;
+ gtdt->el2_flags = GTDT_FLAG_INT_ACTIVE_LOW;
+ gtdt->cnt_read_base = 0xffffffffffffffff;
+
+ // FIXME: VirtualPL2Timer
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_add_table(ctx, gtdt);
+
+ acpi_inc(ctx, sizeof(struct acpi_gtdt));
+
+ return 0;
+};
+
+ACPI_WRITER(5gtdt, "GTDT", sbsa_write_gtdt, 0);
+
+static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ int cluster_offset, l2_offset;
+ u32 offsets[2];
+
+ header = ctx->current;
+ ctx->tab_start = ctx->current;
+
+ memset(header, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(header, "PPTT");
+ header->revision = acpi_get_table_revision(ACPITAB_PPTT);
+ acpi_inc(ctx, sizeof(*header));
+
+ cluster_offset = acpi_pptt_add_proc(ctx, ACPI_PPTT_PHYSICAL_PACKAGE |
+ ACPI_PPTT_CHILDREN_IDENTICAL,
+ 0, 0, 0, NULL);
+
+ l2_offset = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, 0, L2_SIZE,
+ L2_SETS, L2_WAYS, L2_ATTRIBUTES, 64);
+
+ offsets[0] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_VALID, l2_offset,
+ L1D_SIZE, L1D_SETS, L1D_WAYS,
+ L1D_ATTRIBUTES, 64);
+
+ offsets[1] = acpi_pptt_add_cache(ctx, ACPI_PPTT_ALL_BUT_WRITE_POL,
+ l2_offset, L1I_SIZE, L1I_SETS,
+ L1I_WAYS, L1I_ATTRIBUTES, 64);
+
+ for (int i = 0; i < uclass_id_count(UCLASS_CPU); i++) {
+ acpi_pptt_add_proc(ctx, ACPI_PPTT_CHILDREN_IDENTICAL |
+ ACPI_PPTT_NODE_IS_LEAF | ACPI_PPTT_PROC_ID_VALID,
+ cluster_offset, i, 2, offsets);
+ }
+
+ header->length = ctx->current - ctx->tab_start;
+ header->checksum = table_compute_checksum(header, header->length);
+
+ acpi_inc(ctx, header->length);
+ acpi_add_table(ctx, header);
+
+ return 0;
+};
+
+ACPI_WRITER(5pptt, "PPTT", acpi_write_pptt, 0);
diff --git a/board/emulation/qemu-sbsa/dsdt.asl b/board/emulation/qemu-sbsa/dsdt.asl
new file mode 100644
index 0000000..f12cca0
--- /dev/null
+++ b/board/emulation/qemu-sbsa/dsdt.asl
@@ -0,0 +1,483 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT).
+*
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <configs/qemu-sbsa.h>
+
+#define LINK_DEVICE(Uid, LinkName, Irq) \
+ Device (LinkName) { \
+ Name (_HID, EISAID("PNP0C0F")) \
+ Name (_UID, Uid) \
+ Name (_PRS, ResourceTemplate() { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
+ }) \
+ Method (_STA) { \
+ Return (0xF) \
+ } \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, Pin, Link, Zero \
+ }
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "U-Boot", "SBSAQEMU", 2) {
+ Scope (_SB) {
+ // UART PL011
+ Device (COM0) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, Zero)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite,
+ SBSA_UART_BASE_ADDR,
+ SBSA_UART_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+ // AHCI Host Controller
+ Device (AHC0) {
+ Name (_HID, "LNRO001E")
+ Name (_CLS, Package (3) {
+ 0x01,
+ 0x06,
+ 0x01,
+ })
+ Name (_CCA, 1)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite,
+ SBSA_AHCI_BASE_ADDR,
+ SBSA_AHCI_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+
+ // USB XHCI Host Controller
+ Device (USB0) {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (XHCI, 0xF) // will be set using AcpiLib
+ Method (_STA) {
+ Return (XHCI)
+ }
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite,
+ SBSA_XHCI_BASE_ADDR,
+ SBSA_XHCI_LENGTH)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+ })
+
+ // Root Hub
+ Device (RHUB) {
+ Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ // Ports connected to Root Hub
+ Device (HUB1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0x00, // Port is NOT connectable
+ 0xFF, // Don't care
+ 0x00000000, // Reserved 0 must be zero
+ 0x00000000 // Reserved 1 must be zero
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ Device (PRT1) {
+ Name (_ADR, 0x00000001)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT1
+ Device (PRT2) {
+ Name (_ADR, 0x00000002)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x00, // Port connector is A
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer(0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT2
+
+ Device (PRT3) {
+ Name (_ADR, 0x00000003)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x09, // Type C connector - USB2 and SS with Switch
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10) {
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT3
+
+ Device (PRT4) {
+ Name (_ADR, 0x00000004)
+ Name (_UPC, Package() {
+ 0xFF, // Port is connectable
+ 0x09, // Type C connector - USB2 and SS with Switch
+ 0x00000000,
+ 0x00000000
+ })
+ Name (_PLD, Package() {
+ Buffer (0x10){
+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ } // USB0_RHUB_HUB1_PRT4
+ } // USB0_RHUB_HUB1
+ } // USB0_RHUB
+ } // USB0
+
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_UID, "PCI0")
+ Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
+
+ Method (_STA) {
+ Return (0xF)
+ }
+
+ Method (_CBA, 0, NotSerialized) {
+ return (SBSA_PCIE_ECAM_BASE_ADDR)
+ }
+
+ LINK_DEVICE(0, GSI0, 0x23)
+ LINK_DEVICE(1, GSI1, 0x24)
+ LINK_DEVICE(2, GSI2, 0x25)
+ LINK_DEVICE(3, GSI3, 0x26)
+
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ PRT_ENTRY(0x0000FFFF, 0, GSI0),
+ PRT_ENTRY(0x0000FFFF, 0, GSI1),
+ PRT_ENTRY(0x0000FFFF, 0, GSI2),
+ PRT_ENTRY(0x0000FFFF, 0, GSI3),
+
+ PRT_ENTRY(0x0001FFFF, 0, GSI1),
+ PRT_ENTRY(0x0001FFFF, 1, GSI2),
+ PRT_ENTRY(0x0001FFFF, 2, GSI3),
+ PRT_ENTRY(0x0001FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0002FFFF, 0, GSI2),
+ PRT_ENTRY(0x0002FFFF, 1, GSI3),
+ PRT_ENTRY(0x0002FFFF, 2, GSI0),
+ PRT_ENTRY(0x0002FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0003FFFF, 0, GSI3),
+ PRT_ENTRY(0x0003FFFF, 1, GSI0),
+ PRT_ENTRY(0x0003FFFF, 2, GSI1),
+ PRT_ENTRY(0x0003FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0004FFFF, 0, GSI0),
+ PRT_ENTRY(0x0004FFFF, 1, GSI1),
+ PRT_ENTRY(0x0004FFFF, 2, GSI2),
+ PRT_ENTRY(0x0004FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0005FFFF, 0, GSI1),
+ PRT_ENTRY(0x0005FFFF, 1, GSI2),
+ PRT_ENTRY(0x0005FFFF, 2, GSI3),
+ PRT_ENTRY(0x0005FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0006FFFF, 0, GSI2),
+ PRT_ENTRY(0x0006FFFF, 1, GSI3),
+ PRT_ENTRY(0x0006FFFF, 2, GSI0),
+ PRT_ENTRY(0x0006FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0007FFFF, 0, GSI3),
+ PRT_ENTRY(0x0007FFFF, 1, GSI0),
+ PRT_ENTRY(0x0007FFFF, 2, GSI1),
+ PRT_ENTRY(0x0007FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0008FFFF, 0, GSI0),
+ PRT_ENTRY(0x0008FFFF, 1, GSI1),
+ PRT_ENTRY(0x0008FFFF, 2, GSI2),
+ PRT_ENTRY(0x0008FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0009FFFF, 0, GSI1),
+ PRT_ENTRY(0x0009FFFF, 1, GSI2),
+ PRT_ENTRY(0x0009FFFF, 2, GSI3),
+ PRT_ENTRY(0x0009FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000AFFFF, 0, GSI2),
+ PRT_ENTRY(0x000AFFFF, 1, GSI3),
+ PRT_ENTRY(0x000AFFFF, 2, GSI0),
+ PRT_ENTRY(0x000AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000BFFFF, 0, GSI3),
+ PRT_ENTRY(0x000BFFFF, 1, GSI0),
+ PRT_ENTRY(0x000BFFFF, 2, GSI1),
+ PRT_ENTRY(0x000BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x000CFFFF, 0, GSI0),
+ PRT_ENTRY(0x000CFFFF, 1, GSI1),
+ PRT_ENTRY(0x000CFFFF, 2, GSI2),
+ PRT_ENTRY(0x000CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x000DFFFF, 0, GSI1),
+ PRT_ENTRY(0x000DFFFF, 1, GSI2),
+ PRT_ENTRY(0x000DFFFF, 2, GSI3),
+ PRT_ENTRY(0x000DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x000EFFFF, 0, GSI2),
+ PRT_ENTRY(0x000EFFFF, 1, GSI3),
+ PRT_ENTRY(0x000EFFFF, 2, GSI0),
+ PRT_ENTRY(0x000EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x000FFFFF, 0, GSI3),
+ PRT_ENTRY(0x000FFFFF, 1, GSI0),
+ PRT_ENTRY(0x000FFFFF, 2, GSI1),
+ PRT_ENTRY(0x000FFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0010FFFF, 0, GSI0),
+ PRT_ENTRY(0x0010FFFF, 1, GSI1),
+ PRT_ENTRY(0x0010FFFF, 2, GSI2),
+ PRT_ENTRY(0x0010FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0011FFFF, 0, GSI1),
+ PRT_ENTRY(0x0011FFFF, 1, GSI2),
+ PRT_ENTRY(0x0011FFFF, 2, GSI3),
+ PRT_ENTRY(0x0011FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0012FFFF, 0, GSI2),
+ PRT_ENTRY(0x0012FFFF, 1, GSI3),
+ PRT_ENTRY(0x0012FFFF, 2, GSI0),
+ PRT_ENTRY(0x0012FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0013FFFF, 0, GSI3),
+ PRT_ENTRY(0x0013FFFF, 1, GSI0),
+ PRT_ENTRY(0x0013FFFF, 2, GSI1),
+ PRT_ENTRY(0x0013FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0014FFFF, 0, GSI0),
+ PRT_ENTRY(0x0014FFFF, 1, GSI1),
+ PRT_ENTRY(0x0014FFFF, 2, GSI2),
+ PRT_ENTRY(0x0014FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0015FFFF, 0, GSI1),
+ PRT_ENTRY(0x0015FFFF, 1, GSI2),
+ PRT_ENTRY(0x0015FFFF, 2, GSI3),
+ PRT_ENTRY(0x0015FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x0016FFFF, 0, GSI2),
+ PRT_ENTRY(0x0016FFFF, 1, GSI3),
+ PRT_ENTRY(0x0016FFFF, 2, GSI0),
+ PRT_ENTRY(0x0016FFFF, 3, GSI1),
+
+ PRT_ENTRY(0x0017FFFF, 0, GSI3),
+ PRT_ENTRY(0x0017FFFF, 1, GSI0),
+ PRT_ENTRY(0x0017FFFF, 2, GSI1),
+ PRT_ENTRY(0x0017FFFF, 3, GSI2),
+
+ PRT_ENTRY(0x0018FFFF, 0, GSI0),
+ PRT_ENTRY(0x0018FFFF, 1, GSI1),
+ PRT_ENTRY(0x0018FFFF, 2, GSI2),
+ PRT_ENTRY(0x0018FFFF, 3, GSI3),
+
+ PRT_ENTRY(0x0019FFFF, 0, GSI1),
+ PRT_ENTRY(0x0019FFFF, 1, GSI2),
+ PRT_ENTRY(0x0019FFFF, 2, GSI3),
+ PRT_ENTRY(0x0019FFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001AFFFF, 0, GSI2),
+ PRT_ENTRY(0x001AFFFF, 1, GSI3),
+ PRT_ENTRY(0x001AFFFF, 2, GSI0),
+ PRT_ENTRY(0x001AFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001BFFFF, 0, GSI3),
+ PRT_ENTRY(0x001BFFFF, 1, GSI0),
+ PRT_ENTRY(0x001BFFFF, 2, GSI1),
+ PRT_ENTRY(0x001BFFFF, 3, GSI2),
+
+ PRT_ENTRY(0x001CFFFF, 0, GSI0),
+ PRT_ENTRY(0x001CFFFF, 1, GSI1),
+ PRT_ENTRY(0x001CFFFF, 2, GSI2),
+ PRT_ENTRY(0x001CFFFF, 3, GSI3),
+
+ PRT_ENTRY(0x001DFFFF, 0, GSI1),
+ PRT_ENTRY(0x001DFFFF, 1, GSI2),
+ PRT_ENTRY(0x001DFFFF, 2, GSI3),
+ PRT_ENTRY(0x001DFFFF, 3, GSI0),
+
+ PRT_ENTRY(0x001EFFFF, 0, GSI2),
+ PRT_ENTRY(0x001EFFFF, 1, GSI3),
+ PRT_ENTRY(0x001EFFFF, 2, GSI0),
+ PRT_ENTRY(0x001EFFFF, 3, GSI1),
+
+ PRT_ENTRY(0x001FFFFF, 0, GSI3),
+ PRT_ENTRY(0x001FFFFF, 1, GSI0),
+ PRT_ENTRY(0x001FFFFF, 2, GSI1),
+ PRT_ENTRY(0x001FFFFF, 3, GSI2),
+ })
+
+ // Root complex resources
+ Name (_CRS, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 0xff,// AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // IO to mmio window
+ QWordIO (
+ ResourceProducer, MinFixed,
+ MaxFixed, PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x0000, // Min Base Address
+ 0xffff, // Max Base Address
+ SBSA_PIO_BASE_ADDR, // Translate
+ SBSA_PIO_LENGTH // Length
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SBSA_PCIE_MMIO_BASE_ADDR, // Min Base Address
+ SBSA_PCIE_MMIO_END, // Max Base Address
+ 0, // Translate
+ SBSA_PCIE_MMIO_LENGTH // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SBSA_PCIE_MMIO_HIGH_BASE_ADDR, // Min Base Address
+ SBSA_PCIE_MMIO_HIGH_END, // Max Base Address
+ 0, // Translate
+ SBSA_PCIE_MMIO_HIGH_LENGTH // Length
+ )
+ }) // Name(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ SBSA_PCIE_ECAM_BASE_ADDR, // Range Minimum
+ SBSA_PCIE_ECAM_END, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ SBSA_PCIE_ECAM_LENGTH, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Method (_STA) {
+ Return (0xF)
+ }
+ }
+
+ // OS Control Handoff
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ * See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC,4) {
+ // Check for proper UUID
+ If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3,0,CDW1)
+ CreateDWordField (Arg3,4,CDW2)
+ CreateDWordField (Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2,SUPP)
+ Store (CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If ((SUPP & 0x16) != 0x16) {
+ CTRL &= 0x1E // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ CTRL &= 0x1D
+
+ If (Arg1 != One) { // Unknown revision
+ CDW1 |= 0x08
+ }
+
+ If (CDW3 != CTRL) { // Capabilities bits were masked
+ CDW1 |= 0x10
+ }
+
+ // Update DWORD3 in the buffer
+ Store (CTRL,CDW3)
+ Return (Arg3)
+ } Else {
+ CDW1 |= 4 // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+ }
+ } // Scope (_SB)
+}
diff --git a/board/emulation/qemu-sbsa/lowlevel_init.S b/board/emulation/qemu-sbsa/lowlevel_init.S
new file mode 100644
index 0000000..c997721
--- /dev/null
+++ b/board/emulation/qemu-sbsa/lowlevel_init.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ */
+
+#include <config.h>
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x8, fw_dtb_pointer
+ str x0, [x8]
+
+
+ /* Returns */
+ b save_boot_params_ret
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.c b/board/emulation/qemu-sbsa/qemu-sbsa.c
new file mode 100644
index 0000000..3943c92
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.c
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Tuomas Tynkkynen
+ */
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <log.h>
+#include <usb.h>
+#include <asm/armv8/mmu.h>
+
+#include "qemu-sbsa.h"
+
+/* Assigned in lowlevel_init.S
+ * Push the variable into the .data section so that it
+ * does not get cleared later.
+ */
+unsigned long __section(".data") fw_dtb_pointer;
+
+static struct mm_region qemu_sbsa_mem_map[] = {
+ {
+ /* Secure flash */
+ .virt = SBSA_SECURE_FLASH_BASE_ADDR,
+ .phys = SBSA_SECURE_FLASH_BASE_ADDR,
+ .size = SBSA_SECURE_FLASH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Flash */
+ .virt = SBSA_FLASH_BASE_ADDR,
+ .phys = SBSA_FLASH_BASE_ADDR,
+ .size = SBSA_FLASH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Lowmem peripherals */
+ .virt = SBSA_PERIPH_BASE_ADDR,
+ .phys = SBSA_PERIPH_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_BASE_ADDR - SBSA_PERIPH_BASE_ADDR,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* 32-bit address PCIE MMIO space */
+ .virt = SBSA_PCIE_MMIO_BASE_ADDR,
+ .phys = SBSA_PCIE_MMIO_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCI-E ECAM memory area */
+ .virt = SBSA_PCIE_ECAM_BASE_ADDR,
+ .phys = SBSA_PCIE_ECAM_BASE_ADDR,
+ .size = SBSA_PCIE_ECAM_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Highmem PCI-E MMIO memory area */
+ .virt = SBSA_PCIE_MMIO_HIGH_BASE_ADDR,
+ .phys = SBSA_PCIE_MMIO_HIGH_BASE_ADDR,
+ .size = SBSA_PCIE_MMIO_HIGH_LENGTH,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DRAM */
+ .virt = SBSA_MEM_BASE_ADDR,
+ .phys = SBSA_MEM_BASE_ADDR,
+ .size = 0x800000000000ULL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qemu_sbsa_mem_map;
+
+int board_late_init(void)
+{
+ /* start usb so that usb keyboard can be used as input device */
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+/**
+ * dtb_dt_qemu - Return the address of the QEMU provided FDT.
+ *
+ * @return: Pointer to FDT or NULL on failure
+ */
+static void *dtb_dt_qemu(void)
+{
+ /* FDT might be at start of DRAM */
+ if (fdt_magic(SBSA_MEM_BASE_ADDR) == FDT_MAGIC)
+ return (void *)(u64)SBSA_MEM_BASE_ADDR;
+
+ /* When ARM_LINUX_KERNEL_AS_BL33 is enabled in ATF, it's passed in x0 */
+ if (fw_dtb_pointer >= SBSA_MEM_BASE_ADDR &&
+ fdt_magic(fw_dtb_pointer) == FDT_MAGIC) {
+ return (void *)fw_dtb_pointer;
+ }
+
+ return NULL;
+}
+
+/*
+ * QEMU doesn't set compatible on cpus.
+ * Add them to make sure the U-Boot driver properly bind.
+ */
+static int fdtdec_fix_cpus(void *fdt_blob)
+{
+ int cpus_offset, off, ret;
+ u64 mpidr, i = 0;
+
+ cpus_offset = fdt_path_offset(fdt_blob, "/cpus");
+ if (cpus_offset < 0) {
+ puts("couldn't find /cpus node\n");
+ return cpus_offset;
+ }
+
+ fdt_for_each_subnode(off, fdt_blob, cpus_offset) {
+ if (strncmp(fdt_get_name(fdt_blob, off, NULL), "cpu@", 4))
+ continue;
+
+ mpidr = 0;
+ ret = smc_get_mpidr(i, &mpidr);
+ if (ret) {
+ log_warning("Failed to get MPIDR for processor %lld from SMC: %d\n",
+ i, ret);
+ mpidr = i;
+ }
+
+ ret = fdt_setprop_string(fdt_blob, off, "compatible", "arm,armv8");
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt_blob, off, "device_type", "cpu");
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u64(fdt_blob, off, "reg", mpidr);
+ if (ret < 0)
+ return ret;
+ i++;
+ }
+ return 0;
+}
+
+/*
+ * Update the GIC node when necessary and add optional ITS when it has a
+ * non zero base-address.
+ */
+static int fdtdec_fix_gic(void *fdt)
+{
+ u64 gic_dist_base = SBSA_GIC_DIST_BASE_ADDR;
+ u64 gic_redist_base = SBSA_GIC_REDIST_BASE_ADDR;
+ u64 gic_its_base = 0;
+ int offs, ret;
+ u64 reg[10];
+
+ /* Invoke SMC to get real base-address */
+ smc_get_gic_dist_base(&gic_dist_base);
+ smc_get_gic_redist_base(&gic_redist_base);
+
+ if ((gic_dist_base != SBSA_GIC_DIST_BASE_ADDR) ||
+ (gic_redist_base != SBSA_GIC_REDIST_BASE_ADDR)) {
+ offs = fdt_path_offset(fdt, "/interrupt-controller");
+ if (offs < 0) {
+ puts("couldn't find /interrupt-controller node\n");
+ return offs;
+ }
+
+ reg[0] = cpu_to_fdt64(gic_dist_base);
+ reg[1] = cpu_to_fdt64((u64)SBSA_GIC_DIST_LENGTH);
+ reg[2] = cpu_to_fdt64(gic_redist_base);
+ reg[3] = cpu_to_fdt64((u64)SBSA_GIC_REDIST_LENGTH);
+ reg[4] = cpu_to_fdt64(0);
+ reg[5] = cpu_to_fdt64(0);
+ reg[6] = cpu_to_fdt64(SBSA_GIC_HBASE_ADDR);
+ reg[7] = cpu_to_fdt64((u64)SBSA_GIC_HBASE_LENGTH);
+ reg[8] = cpu_to_fdt64(SBSA_GIC_VBASE_ADDR);
+ reg[9] = cpu_to_fdt64((u64)SBSA_GIC_VBASE_LENGTH);
+
+ ret = fdt_setprop_inplace(fdt, offs, "reg", reg, sizeof(reg));
+ }
+
+ smc_get_gic_its_base(&gic_its_base);
+
+ if (gic_its_base != 0) {
+ offs = fdt_path_offset(fdt, "/its");
+ if (offs < 0)
+ return offs;
+
+ ret = fdt_setprop_string(fdt, offs, "status", "okay");
+ if (ret < 0)
+ return ret;
+
+ reg[0] = cpu_to_fdt64(gic_its_base);
+ reg[1] = 0;
+
+ ret = fdt_setprop(fdt, offs, "reg", reg, sizeof(u64) * 2);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ void *qemu_fdt;
+ int ret;
+
+ /*
+ * Locate the QEMU provided DTB that contains the CPUs and amount of DRAM.
+ */
+ qemu_fdt = dtb_dt_qemu();
+ if (!qemu_fdt) {
+ log_err("QEMU FDT not found\n");
+ return -ENODEV;
+ }
+
+ ret = fdt_increase_size((void *)fdt_blob, 1024 + fdt_totalsize(qemu_fdt));
+ if (ret)
+ return -ENOMEM;
+
+ /*
+ * Merge the QEMU DTB as overlay into the U-Boot provided DTB.
+ */
+ ret = fdt_overlay_apply_node((void *)fdt_blob, 0, qemu_fdt, 0);
+ if (ret < 0)
+ log_err("Failed to apply overlay: %d\n", ret);
+
+ /* Fix QEMU nodes to make sure U-Boot drivers are properly working */
+ ret = fdtdec_fix_cpus((void *)fdt_blob);
+ if (ret < 0)
+ log_err("Failed to fix CPUs in FDT: %d\n", ret);
+
+ ret = fdtdec_fix_gic((void *)fdt_blob);
+ if (ret < 0)
+ log_err("Failed to fix INTC in FDT: %d\n", ret);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return env_set_hex("fdt_addr", (uintptr_t)gd->fdt_blob);
+}
+
+void reset_cpu(void)
+{
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
\ No newline at end of file
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.env b/board/emulation/qemu-sbsa/qemu-sbsa.env
new file mode 100644
index 0000000..88fdb0e
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.env
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for qemu-arm and qemu-arm64 */
+
+stdin=serial,usbkbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+fdt_high=0xffffffffffffffff
+initrd_high=0xffffffffffffffff
+scriptaddr=0x100000300000
+pxefile_addr_r=0x10000400000
+kernel_addr_r=0x10000200000
+ramdisk_addr_r=0x10001000000
+boot_targets=qfw usb scsi virtio nvme dhcp
diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.h b/board/emulation/qemu-sbsa/qemu-sbsa.h
new file mode 100644
index 0000000..391a70b
--- /dev/null
+++ b/board/emulation/qemu-sbsa/qemu-sbsa.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+/**
+ * smc_get_mpidr() - Call into SMC and get the MPIDR for given CPU
+ *
+ * @id: CPU index
+ * @mpidr: Pointer where to place the MPIDR
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_mpidr(unsigned long id, u64 *mpidr);
+
+/**
+ * smc_get_gic_dist_base() - Call into SMC and get GIC dist base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_dist_base(u64 *base);
+
+/**
+ * smc_get_gic_redist_base() - Call into SMC and get the GIC redistributor
+ * base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_redist_base(u64 *base);
+
+/**
+ * smc_get_gic_its_base() - Call into SMC and get the ITS base address
+ *
+ * @mpidr: Pointer where to place the base address
+ * @return 0 if OK, other -ve on error
+ */
+int smc_get_gic_its_base(u64 *base);
diff --git a/board/emulation/qemu-sbsa/smc.c b/board/emulation/qemu-sbsa/smc.c
new file mode 100644
index 0000000..9a2d091
--- /dev/null
+++ b/board/emulation/qemu-sbsa/smc.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <init.h>
+#include <log.h>
+#include <linux/arm-smccc.h>
+
+#define SMC_SIP_FUNCTION_ID(n) (0xC2000000 | (n))
+
+#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1)
+#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100)
+#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
+#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
+#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
+#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
+
+int smc_get_mpidr(unsigned long id, u64 *mpidr)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_CPU_NODE, id, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *mpidr = res.a2;
+
+ return res.a0;
+}
+
+int smc_get_gic_dist_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a1;
+
+ return res.a0;
+}
+
+int smc_get_gic_redist_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a2;
+
+ return res.a0;
+}
+
+int smc_get_gic_its_base(u64 *base)
+{
+ struct arm_smccc_res res;
+
+ res.a0 = ~0;
+ arm_smccc_smc(SIP_SVC_GET_GIC_ITS, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (!res.a0)
+ *base = res.a1;
+
+ return res.a0;
+}
diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c
index e2ed70ca..bfdc447 100644
--- a/board/engicam/imx8mp/icore_mx8mp.c
+++ b/board/engicam/imx8mp/icore_mx8mp.c
@@ -33,7 +33,7 @@
setbits_le32(&gpr->gpr[1], BIT(22));
}
-#if CONFIG_IS_ENABLED(NET)
+#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
diff --git a/board/freescale/imx93_qsb/Kconfig b/board/freescale/imx93_qsb/Kconfig
new file mode 100644
index 0000000..fea69c8
--- /dev/null
+++ b/board/freescale/imx93_qsb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX93_9X9_QSB
+
+config SYS_BOARD
+ default "imx93_qsb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx93_qsb"
+
+endif
diff --git a/board/freescale/imx93_qsb/MAINTAINERS b/board/freescale/imx93_qsb/MAINTAINERS
new file mode 100644
index 0000000..a3247d1
--- /dev/null
+++ b/board/freescale/imx93_qsb/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX93 QSB BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx93_qsb/
+F: include/configs/imx93_qsb.h
+F: configs/imx93_9x9_qsb_defconfig
+F: configs/imx93_9x9_qsb_inline_ecc_defconfig
diff --git a/board/freescale/imx93_qsb/Makefile b/board/freescale/imx93_qsb/Makefile
new file mode 100644
index 0000000..c94a6b2
--- /dev/null
+++ b/board/freescale/imx93_qsb/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx93_qsb.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX9_DRAM_INLINE_ECC
+obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing_ecc.o
+else
+obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing.o
+endif
+endif
diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c
new file mode 100644
index 0000000..388d991
--- /dev/null
+++ b/board/freescale/imx93_qsb/imx93_qsb.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+ env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "9X9_QSB");
+ env_set("board_rev", "iMX93");
+#endif
+ return 0;
+}
diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env
new file mode 100644
index 0000000..92486c6
--- /dev/null
+++ b/board/freescale/imx93_qsb/imx93_qsb.env
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+boot_targets=mmc0 mmc1
+boot_fit=no
+bootm_size=0x10000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
+prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+mmcboot=
+ echo Booting from mmc ...;
+ run mmcargs;
+ if test ${sec_boot} = yes; then
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ if run loadfdt; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+ echo Booting from net ...;
+ run netargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ if test ${sec_boot} = yes; then
+ ${get_cmd} ${cntr_addr} ${cntr_file};
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ ${get_cmd} ${loadaddr} ${image};
+ if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
diff --git a/board/freescale/imx93_qsb/lpddr4_timing.c b/board/freescale/imx93_qsb/lpddr4_timing.c
new file mode 100644
index 0000000..c589c16
--- /dev/null
+++ b/board/freescale/imx93_qsb/lpddr4_timing.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ff},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x1465311B},
+ {0x4e300104, 0xF8CC0017},
+ {0x4e300108, 0xD4D68E00},
+ {0x4e30010C, 0x0071E100},
+ {0x4e300124, 0x18660000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x33F00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x00000022},
+ {0x4e300254, 0x01280128},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x1D441D0D},
+ {0x4e300304, 0x01281E10},
+ {0x4e300308, 0x0C3C0C34},
+ },
+ {
+ {0x01, 0xD4},
+ {0x02, 0x2D},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x02121100},
+ {0x4e300104, 0xF866000C},
+ {0x4e300108, 0xF2FA8088},
+ {0x4e30010C, 0x006101A0},
+ {0x4e300124, 0x0C340000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30700000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000011},
+ {0x4e300254, 0x00900090},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ }
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x320},
+ {0x120008, 0x190},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xc80},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x48},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x48},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xc80},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x384},
+ {0x2000c, 0xc8},
+ {0x2000d, 0x7d0},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x1c2},
+ {0x12000c, 0x64},
+ {0x12000d, 0x3e8},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 1600, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx93_qsb/lpddr4_timing_ecc.c b/board/freescale/imx93_qsb/lpddr4_timing_ecc.c
new file mode 100644
index 0000000..60cd490
--- /dev/null
+++ b/board/freescale/imx93_qsb/lpddr4_timing_ecc.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /* Initialize DDRC registers */
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ef},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1012},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30d00},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0xc0000000},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x1465311B},
+ {0x4e300104, 0xF8CC0017},
+ {0x4e300108, 0xD4D68E00},
+ {0x4e30010C, 0x0071E100},
+ {0x4e300124, 0x18660000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x33F00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x00000022},
+ {0x4e300254, 0x01280128},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x1D441D0D},
+ {0x4e300304, 0x01281E10},
+ {0x4e300308, 0x0C3C0C34},
+ },
+ {
+ {0x01, 0xD4},
+ {0x02, 0x2D},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x02121100},
+ {0x4e300104, 0xF866000C},
+ {0x4e300108, 0xF2FA8088},
+ {0x4e30010C, 0x006101A0},
+ {0x4e300124, 0x0C340000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30700000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000011},
+ {0x4e300254, 0x00900090},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ }
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x320},
+ {0x120008, 0x190},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
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+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xc80},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x48},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x48},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xc80},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x33},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
+ {0x54034, 0x4600},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x384},
+ {0x2000c, 0xc8},
+ {0x2000d, 0x7d0},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x1c2},
+ {0x12000c, 0x64},
+ {0x12000d, 0x3e8},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 1600, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c
new file mode 100644
index 0000000..6d1ab60
--- /dev/null
+++ b/board/freescale/imx93_qsb/spl.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx93_pins.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
+ puts("Normal Boot\n");
+}
+
+void spl_dram_init(void)
+{
+ struct dram_timing_info *ptiming = &dram_timing;
+
+ printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+ ddr_init(ptiming);
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int val = 0, buck_val;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pca9450@25\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* enable DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8V for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85V for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9V for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+ } else {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ /* set standby voltage to 0.65v */
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+ /* 1.1v for LPDDR4 */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
+
+ /* I2C_LT_EN*/
+ pmic_reg_write(dev, 0xa, 0x3);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ timer_init();
+
+ arch_cpu_init();
+
+ spl_early_init();
+
+ preloader_console_init();
+
+ ret = imx9_probe_mu();
+ if (ret) {
+ printf("Fail to init ELE API\n");
+ } else {
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
+ }
+
+ clock_init_late();
+
+ power_init_board();
+
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
+ set_arm_clk(get_cpu_speed_grade_hz());
+
+ /* Init power of mix */
+ soc_power_init();
+
+ /* Setup TRDC for DDR access */
+ trdc_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Put M33 into CPUWAIT for following kick */
+ ret = m33_prepare();
+ if (!ret)
+ printf("M33 prepare ok\n");
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env b/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env
new file mode 100644
index 0000000..c61e9e3
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for imxrt1050-evk */
+
+#ifdef CONFIG_VIDEO
+stdin=serial
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+#endif
+
+fdt_addr_r=0x80800000
+kernel_addr_r=0x80000000
+boot_targets=nor
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.env b/board/freescale/imxrt1050-evk/imxrt1050-evk.env
new file mode 100644
index 0000000..1c5cbc2
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.env
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for imxrt1050-evk */
+
+#ifdef CONFIG_VIDEO
+stdin=serial
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+#endif
+
+fdt_addr_r=0x80800000
+kernel_addr_r=0x80000000
+boot_targets=mmc
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c4ab59d..fbb5a12 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -31,8 +31,6 @@
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -155,49 +153,6 @@
}
#endif
-#ifdef CONFIG_USB_EHCI_MX6
-#ifndef CONFIG_DM_USB
-
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
-};
-
-/* At default the 3v3 enables the MIC2026 for VBUS power */
-static void setup_usb(void)
-{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-#endif
-#endif
-
#ifdef CONFIG_FEC_MXC
static int setup_fec(int fec_id)
{
@@ -284,12 +239,6 @@
setup_fec(CFG_FEC_ENET_DEV);
#endif
-#ifdef CONFIG_USB_EHCI_MX6
-#ifndef CONFIG_DM_USB
- setup_usb();
-#endif
-#endif
-
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile
new file mode 100644
index 0000000..2858e0d
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
new file mode 100644
index 0000000..05cf55e
--- /dev/null
+++ b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <adc.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+
+#define HW_ID_CHANNEL 5
+
+struct board_model {
+ unsigned int low;
+ unsigned int high;
+ const char *fdtfile;
+};
+
+static const struct board_model board_models[] = {
+ { 348, 528, "rockchip/rk3588-nanopc-t6.dtb" },
+ { 1957, 2137, "rockchip/rk3588-nanopc-t6-lts.dtb" },
+};
+
+static const struct board_model *get_board_model(void)
+{
+ unsigned int val;
+ int i, ret;
+
+ ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
+ if (ret)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(board_models); i++) {
+ unsigned int min = board_models[i].low;
+ unsigned int max = board_models[i].high;
+
+ if (min <= val && val <= max)
+ return &board_models[i];
+ }
+
+ return NULL;
+}
+
+int rk_board_late_init(void)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model)
+ env_set("fdtfile", model->fdtfile);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model && !strcmp(name, model->fdtfile))
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/board/hardkernel/odroid_m1s/Kconfig b/board/hardkernel/odroid_m1s/Kconfig
new file mode 100644
index 0000000..5e0d2ca
--- /dev/null
+++ b/board/hardkernel/odroid_m1s/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_M1S_RK3566
+
+config SYS_BOARD
+ default "odroid_m1s"
+
+config SYS_VENDOR
+ default "hardkernel"
+
+config SYS_CONFIG_NAME
+ default "odroid_m1"
+
+endif
diff --git a/board/hardkernel/odroid_m1s/MAINTAINERS b/board/hardkernel/odroid_m1s/MAINTAINERS
new file mode 100644
index 0000000..0c8d112
--- /dev/null
+++ b/board/hardkernel/odroid_m1s/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID-M1S
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/hardkernel/odroid_m1s/
+F: configs/odroid-m1s-rk3566_defconfig
+F: arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi
diff --git a/board/hardkernel/odroid_m2/Kconfig b/board/hardkernel/odroid_m2/Kconfig
new file mode 100644
index 0000000..b537459
--- /dev/null
+++ b/board/hardkernel/odroid_m2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_M2_RK3588S
+
+config SYS_BOARD
+ default "odroid_m2"
+
+config SYS_VENDOR
+ default "hardkernel"
+
+config SYS_CONFIG_NAME
+ default "odroid_m2"
+
+endif
diff --git a/board/hardkernel/odroid_m2/MAINTAINERS b/board/hardkernel/odroid_m2/MAINTAINERS
new file mode 100644
index 0000000..13c0a8b
--- /dev/null
+++ b/board/hardkernel/odroid_m2/MAINTAINERS
@@ -0,0 +1,7 @@
+ODROID-M2
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/hardkernel/odroid_m2/
+F: include/configs/odroid_m2.h
+F: configs/odroid-m2-rk3588s_defconfig
+F: arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi
diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig
index 4309f75..6e8c479 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -24,6 +24,8 @@
imply SMP
imply CLK_CCF
imply CLK_MPFS
+ imply REGMAP
+ imply SYSCON
imply SYS_NS16550
imply CMD_DHCP
imply CMD_EXT2
diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c
index 112770b..c709d01 100644
--- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c
+++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c
@@ -29,7 +29,7 @@
setbits_le32(&gpr->gpr[1], BIT(22));
}
-#if CONFIG_IS_ENABLED(NET)
+#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
diff --git a/board/radxa/rock5b-rk3588/Makefile b/board/radxa/rock5b-rk3588/Makefile
new file mode 100644
index 0000000..95d8135
--- /dev/null
+++ b/board/radxa/rock5b-rk3588/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Collabora Ltd.
+#
+
+obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
new file mode 100644
index 0000000..fc2f69d
--- /dev/null
+++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023-2024 Collabora Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ if (IS_ENABLED(CONFIG_TYPEC_FUSB302))
+ fdt_status_okay_by_compatible(blob, "fcs,fusb302");
+ return 0;
+}
+#endif
diff --git a/board/raspberrypi/rpi/.gitignore b/board/raspberrypi/rpi/.gitignore
new file mode 100644
index 0000000..39e46ba
--- /dev/null
+++ b/board/raspberrypi/rpi/.gitignore
@@ -0,0 +1,3 @@
+dsdt_generated.aml
+dsdt_generated.asl.tmp
+dsdt_generated.c
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
index b1186cd..bb1b7cc 100644
--- a/board/raspberrypi/rpi/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -4,3 +4,5 @@
obj-y := rpi.o
obj-y += lowlevel_init.o
+
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o
diff --git a/board/raspberrypi/rpi/acpitables.h b/board/raspberrypi/rpi/acpitables.h
new file mode 100644
index 0000000..3ba8f19
--- /dev/null
+++ b/board/raspberrypi/rpi/acpitables.h
@@ -0,0 +1,90 @@
+/** @file
+ *
+ * RPi defines for constructing ACPI tables
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2019, ARM Ltd. All rights reserved.
+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef __RPI_ACPITABLES_H__
+#define __RPI_ACPITABLES_H__
+
+#include <acpi/acpi_table.h>
+
+// The ASL compiler can't perform arithmetic on MEMORY32FIXED ()
+// parameters so you can't pass a constant like BASE + OFFSET.
+// We therefore define a macro that can perform arithmetic base
+// address update with an offset.
+#define MEMORY32SETBASE(BufName, MemName, VarName, Offset) \
+ CreateDwordField (^BufName, ^MemName._BAS, VarName) \
+ Add (BCM2836_SOC_REGISTERS, Offset, VarName)
+
+//------------------------------------------------------------------------
+// Interrupts. These are specific to each platform
+//------------------------------------------------------------------------
+#if defined(CONFIG_TARGET_RPI_3)
+#define BCM2836_V3D_BUS_INTERRUPT 0x2A
+#define BCM2836_DMA_INTERRUPT 0x3B
+#define BCM2836_SPI1_INTERRUPT 0x3D
+#define BCM2836_SPI2_INTERRUPT 0x3D
+#define BCM2836_HVS_INTERRUPT 0x41
+#define BCM2836_HDMI0_INTERRUPT 0x48
+#define BCM2836_HDMI1_INTERRUPT 0x49
+#define BCM2836_PV2_INTERRUPT 0x4A
+#define BCM2836_PV0_INTERRUPT 0x4D
+#define BCM2836_PV1_INTERRUPT 0x4E
+#define BCM2836_MBOX_INTERRUPT 0x61
+#define BCM2836_VCHIQ_INTERRUPT 0x62
+#define BCM2386_GPIO_INTERRUPT0 0x51
+#define BCM2386_GPIO_INTERRUPT1 0x52
+#define BCM2386_GPIO_INTERRUPT2 0x53
+#define BCM2386_GPIO_INTERRUPT3 0x54
+#define BCM2836_I2C1_INTERRUPT 0x55
+#define BCM2836_I2C2_INTERRUPT 0x55
+#define BCM2836_SPI0_INTERRUPT 0x56
+#define BCM2836_USB_INTERRUPT 0x29
+#define BCM2836_SDHOST_INTERRUPT 0x58
+#define BCM2836_MMCHS1_INTERRUPT 0x5E
+#define BCM2836_MINI_UART_INTERRUPT 0x3D
+#define BCM2836_PL011_UART_INTERRUPT 0x59
+#elif defined(CONFIG_TARGET_RPI_4)
+#define BCM2836_V3D_BUS_INTERRUPT 0x2A
+#define BCM2836_DMA_INTERRUPT 0x3B
+#define BCM2836_SPI1_INTERRUPT 0x7D
+#define BCM2836_SPI2_INTERRUPT 0x7D
+#define BCM2836_HVS_INTERRUPT 0x41
+#define BCM2836_HDMI0_INTERRUPT 0x48
+#define BCM2836_HDMI1_INTERRUPT 0x49
+#define BCM2836_PV2_INTERRUPT 0x4A
+#define BCM2836_PV0_INTERRUPT 0x4D
+#define BCM2836_PV1_INTERRUPT 0x4E
+#define BCM2836_MBOX_INTERRUPT 0x41
+#define BCM2836_VCHIQ_INTERRUPT 0x42
+#define BCM2386_GPIO_INTERRUPT0 0x91
+#define BCM2386_GPIO_INTERRUPT1 0x92
+#define BCM2386_GPIO_INTERRUPT2 0x93
+#define BCM2386_GPIO_INTERRUPT3 0x94
+#define BCM2836_I2C1_INTERRUPT 0x95
+#define BCM2836_I2C2_INTERRUPT 0x95
+#define BCM2836_SPI0_INTERRUPT 0x96
+#define BCM2836_USB_INTERRUPT 0x69
+#define BCM2836_SDHOST_INTERRUPT 0x98
+#define BCM2836_MMCHS1_INTERRUPT 0x9E
+#define BCM2836_MINI_UART_INTERRUPT 0x7D
+#define BCM2836_PL011_UART_INTERRUPT 0x99
+#define GENET_INTERRUPT0 0xBD
+#define GENET_INTERRUPT1 0xBE
+#define GENET_BASE_ADDRESS 0xFD580000
+#define GENET_LENGTH 0x10000
+#define THERM_SENSOR_BASE_ADDRESS 0xFD5d2200
+#define THERM_SENSOR_LENGTH 0x8
+#else
+#error "Unsupported rpi module for ACPI tables"
+#endif
+
+#endif // __ACPITABLES_H__
diff --git a/board/raspberrypi/rpi/dsdt.asl b/board/raspberrypi/rpi/dsdt.asl
new file mode 100644
index 0000000..c89b08d
--- /dev/null
+++ b/board/raspberrypi/rpi/dsdt.asl
@@ -0,0 +1,254 @@
+/** @file
+ *
+ * Differentiated System Definition Table (DSDT)
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2711.h>
+#include <asm/arch/acpi/bcm2836.h>
+#include <asm/arch/acpi/bcm2836_gpio.h>
+#include <asm/arch/acpi/bcm2836_gpu.h>
+#include <asm/arch/acpi/bcm2836_pwm.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+
+#include "acpitables.h"
+
+#define BCM_ALT0 0x4
+#define BCM_ALT1 0x5
+#define BCM_ALT2 0x6
+#define BCM_ALT3 0x7
+#define BCM_ALT4 0x3
+#define BCM_ALT5 0x2
+
+//
+// The ASL compiler does not support argument arithmetic in functions
+// like QWordMemory (). So we need to instantiate dummy qword regions
+// that we can then update the Min, Max and Length attributes of.
+// The three macros below help accomplish this.
+//
+// QWORDMEMORYSET specifies a CPU memory range (whose base address is
+// BCM2836_SOC_REGISTERS + Offset), and QWORDBUSMEMORYSET specifies
+// a VPU memory range (whose base address is provided directly).
+//
+#define QWORDMEMORYBUF(Index) \
+ QWordMemory (ResourceProducer,, \
+ MinFixed, MaxFixed, NonCacheable, ReadWrite, \
+ 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index)
+
+#define QWORDMEMORYSET(Index, Offset, Length) \
+ CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
+ CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
+ CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
+ Store (Length, LE ## Index) \
+ Add (BCM2836_SOC_REGISTERS, Offset, MI ## Index) \
+ Add (MI ## Index, LE ## Index - 1, MA ## Index)
+
+#define QWORDBUSMEMORYSET(Index, Base, Length) \
+ CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
+ CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
+ CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
+ Store (Base, MI ## Index) \
+ Store (Length, LE ## Index) \
+ Add (MI ## Index, LE ## Index - 1, MA ## Index)
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+ External (\_PR.CP00, DeviceObj)
+ External (\_PR.CP01, DeviceObj)
+ External (\_PR.CP02, DeviceObj)
+ External (\_PR.CP03, DeviceObj)
+ Scope (\_SB_)
+ {
+ include ("pep.asl")
+
+ //
+ // GPU device container describes the DMA translation required
+ // when a device behind the GPU wants to access Arm memory.
+ // Only the first GB can be addressed.
+ //
+ Device (GDV0)
+ {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ //
+ // Container devices with _DMA must have _CRS, meaning GDV0
+ // to provide all resources that GpuDevs.asl consume (except
+ // interrupts).
+ //
+ Name (RBUF, ResourceTemplate () {
+ QWORDMEMORYBUF(01)
+ QWORDMEMORYBUF(02)
+ QWORDMEMORYBUF(03)
+ // QWORDMEMORYBUF(04)
+ // QWORDMEMORYBUF(05)
+ QWORDMEMORYBUF(06)
+ QWORDMEMORYBUF(07)
+ QWORDMEMORYBUF(08)
+ QWORDMEMORYBUF(09)
+ QWORDMEMORYBUF(10)
+ QWORDMEMORYBUF(11)
+ QWORDMEMORYBUF(12)
+ QWORDMEMORYBUF(13)
+ QWORDMEMORYBUF(14)
+ QWORDMEMORYBUF(15)
+ // QWORDMEMORYBUF(16)
+ QWORDMEMORYBUF(17)
+ QWORDMEMORYBUF(18)
+ QWORDMEMORYBUF(19)
+ QWORDMEMORYBUF(20)
+ QWORDMEMORYBUF(21)
+ QWORDMEMORYBUF(22)
+ QWORDMEMORYBUF(23)
+ QWORDMEMORYBUF(24)
+ QWORDMEMORYBUF(25)
+ })
+
+ // USB
+ QWORDMEMORYSET(01, BCM2836_USB_OFFSET, BCM2836_USB_LENGTH)
+
+ // GPU
+ QWORDMEMORYSET(02, BCM2836_V3D_BUS_OFFSET, BCM2836_V3D_BUS_LENGTH)
+ QWORDMEMORYSET(03, BCM2836_HVS_OFFSET, BCM2836_HVS_LENGTH)
+ // QWORDMEMORYSET(04, BCM2836_PV0_OFFSET, BCM2836_PV0_LENGTH)
+ // QWORDMEMORYSET(05, BCM2836_PV1_OFFSET, BCM2836_PV1_LENGTH)
+ QWORDMEMORYSET(06, BCM2836_PV2_OFFSET, BCM2836_PV2_LENGTH)
+ QWORDMEMORYSET(07, BCM2836_HDMI0_OFFSET, BCM2836_HDMI0_LENGTH)
+ QWORDMEMORYSET(08, BCM2836_HDMI1_OFFSET, BCM2836_HDMI1_LENGTH)
+
+ // Mailbox
+ QWORDMEMORYSET(09, BCM2836_MBOX_OFFSET, BCM2836_MBOX_LENGTH)
+
+ // VCHIQ
+ QWORDMEMORYSET(10, BCM2836_VCHIQ_OFFSET, BCM2836_VCHIQ_LENGTH)
+
+ // GPIO
+ QWORDMEMORYSET(11, GPIO_OFFSET, GPIO_LENGTH)
+
+ // I2C
+ QWORDMEMORYSET(12, BCM2836_I2C1_OFFSET, BCM2836_I2C1_LENGTH)
+ QWORDMEMORYSET(13, BCM2836_I2C2_OFFSET, BCM2836_I2C2_LENGTH)
+
+ // SPI
+ QWORDMEMORYSET(14, BCM2836_SPI0_OFFSET, BCM2836_SPI0_LENGTH)
+ QWORDMEMORYSET(15, BCM2836_SPI1_OFFSET, BCM2836_SPI1_LENGTH)
+ // QWORDMEMORYSET(16, BCM2836_SPI2_OFFSET, BCM2836_SPI2_LENGTH)
+
+ // PWM
+ QWORDMEMORYSET(17, BCM2836_PWM_DMA_OFFSET, BCM2836_PWM_DMA_LENGTH)
+ QWORDMEMORYSET(18, BCM2836_PWM_CTRL_OFFSET, BCM2836_PWM_CTRL_LENGTH)
+ QWORDBUSMEMORYSET(19, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH)
+ QWORDBUSMEMORYSET(20, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH)
+ QWORDMEMORYSET(21, BCM2836_PWM_CLK_OFFSET, BCM2836_PWM_CLK_LENGTH)
+
+ // UART
+ QWORDMEMORYSET(22, BCM2836_PL011_UART_OFFSET, BCM2836_PL011_UART_LENGTH)
+ QWORDMEMORYSET(23, BCM2836_MINI_UART_OFFSET, BCM2836_MINI_UART_LENGTH)
+
+ // SDC
+ QWORDMEMORYSET(24, MMCHS1_OFFSET, MMCHS1_LENGTH)
+ QWORDMEMORYSET(25, SDHOST_OFFSET, SDHOST_LENGTH)
+
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ //
+ // Only the first GB is available.
+ // Bus 0xC0000000 -> CPU 0x00000000.
+ //
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x00000000C0000000, // MIN
+ 0x00000000FFFFFFFF, // MAX
+ 0xFFFFFFFF40000000, // TRA
+ 0x0000000040000000, // LEN
+ ,
+ ,
+ )
+ })
+#include "gpudevs.asl"
+ }
+
+#if defined(CONFIG_TARGET_RPI_4)
+ Device (ETH0)
+ {
+ Name (_HID, "BCM6E4E")
+ Name (_CID, "BCM6E4E")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Return (ResourceTemplate ()
+ {
+ // No need for MEMORY32SETBASE on Genet as we have a straight base address constant
+ MEMORY32FIXED (ReadWrite, GENET_BASE_ADDRESS, GENET_LENGTH, )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { GENET_INTERRUPT0, GENET_INTERRUPT1 }
+ })
+ }
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "brcm,max-dma-burst-size", 0x08 },
+ Package () { "phy-mode", "rgmii-rxid" },
+ }
+ })
+ }
+
+ // Define a simple thermal zone. The idea here is we compute the SOC temp
+ // via a register we can read, and give it to the OS. This enables basic
+ // reports from the "sensors" utility, and the OS can then poll and take
+ // actions if that temp exceeds any of the given thresholds.
+ Device (EC00)
+ {
+ Name (_HID, EISAID ("PNP0C06"))
+ Name (_CCA, 0x0)
+
+ // all temps in are tenths of K (aka 2732 is the min temps in Linux (aka 0C))
+ ThermalZone (TZ00) {
+ OperationRegion (TEMS, SystemMemory, THERM_SENSOR_BASE_ADDRESS, THERM_SENSOR_LENGTH)
+ Field (TEMS, DWordAcc, NoLock, Preserve) {
+ TMPS, 32
+ }
+ Method (_TMP, 0, Serialized) {
+ return (((410040 - ((TMPS & 0x3ff) * 487)) / 100) + 2732);
+ }
+
+ Method (_SCP, 3) { } // receive cooling policy from OS
+
+ Method (_CRT) { Return (3632) } // (90C) Critical temp point (immediate power-off)
+ Method (_HOT) { Return (3582) } // (85C) HOT state where OS should hibernate
+ Method (_PSV) { Return (3532) } // (80C) Passive cooling (CPU throttling) trip point
+
+ // SSDT inserts _AC0/_AL0 @60C here, if a FAN is configured
+
+ Name (_TZP, 10) //The OSPM must poll this device every 1 seconds
+ Name (_PSL, Package () { \_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03 })
+ }
+ }
+#endif
+
+
+#include "uart.asl"
+#include "rhpx.asl"
+#include "sdhc.asl"
+#include "emmc.asl"
+#include "pci.asl"
+ }
+}
diff --git a/board/raspberrypi/rpi/emmc.asl b/board/raspberrypi/rpi/emmc.asl
new file mode 100644
index 0000000..63f0136
--- /dev/null
+++ b/board/raspberrypi/rpi/emmc.asl
@@ -0,0 +1,136 @@
+/** @file
+ *
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+#include <asm/arch/acpi/bcm2711.h>
+
+Device (GDV1) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x2)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM)
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET)
+ Return (^RBUF)
+ }
+
+ // Translated DMA region for BCM2711 silicon revisions older than C0
+ Name (DMTR, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x00000000C0000000, // MIN
+ 0x00000000FFFFFFFF, // MAX
+ 0xFFFFFFFF40000000, // TRA
+ 0x0000000040000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // Non translated DMA region for BCM2711 revisions C0 and newer
+ Name (DMNT, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0000000000000000, // MIN
+ 0x000000FFFFFFFFFF, // MAX
+ 0x0000000000000000, // TRA
+ 0x0000010000000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // emmc2 Host Controller. (brcm,bcm2711-emmc2)
+ Device (SDC3)
+ {
+ Name (_HID, "BRCME88C")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+ Name (SDMA, 0x2)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET)
+ Return (^RBUF)
+ }
+
+ // Unfortunately this controller doesn't honor the
+ // standard SDHCI voltage control registers
+ // (or at least Linux's standard code can't
+ // lower the voltage) So, UHS mode is disabled with caps
+ Name (DSD1, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps-mask", 0x0000000500080000 },
+ }
+ })
+ // Along with disabling UHS, here both SDMA and ADMA2
+ // are also disabled until the linux _DMA() mask/translate
+ // works properly.
+ Name (DSD2, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps-mask", 0x0000000504480000 },
+ }
+ })
+ Method (_DSD, 0x0, Serialized)
+ {
+ // Select one of the sdhci-caps-mask definitions
+ // depending on whether we also want to disable DMA
+ if (SDMA == 0)
+ {
+ return (^DSD2)
+ }
+ else
+ {
+ return (^DSD1)
+ }
+ }
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+ } //SDC3
+} //GDV1
diff --git a/board/raspberrypi/rpi/gpudevs.asl b/board/raspberrypi/rpi/gpudevs.asl
new file mode 100644
index 0000000..a3077a9
--- /dev/null
+++ b/board/raspberrypi/rpi/gpudevs.asl
@@ -0,0 +1,372 @@
+/** @file
+ *
+ * [DSDT] Devices behind the GPU.
+ *
+ * Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+// DWC OTG Controller
+Device (USB0)
+{
+ Name (_HID, "BCM2848")
+#if defined(CONFIG_TARGET_RPI_3)
+ Name (_CID, "DWC_OTG")
+#elif defined(CONFIG_TARGET_RPI_4)
+ Name (_CID, "BCM2848")
+#endif
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_USB_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_USB_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_USB_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// Video Core 4 GPU
+Device (GPU0)
+{
+ Name (_HID, "BCM2850")
+ Name (_CID, "BCM2850")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ // Memory and interrupt for the GPU
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_V3D_BUS_LENGTH, RM01)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_V3D_BUS_INTERRUPT }
+
+ // HVS - Hardware Video Scalar
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HVS_LENGTH, RM02)
+ // The HVS interrupt is reserved by the VPU
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HVS_INTERRUPT }
+
+ // PixelValve0 - DSI0 or DPI
+ // MEMORY32FIXED (ReadWrite, BCM2836_PV0_BASE_ADDRESS, BCM2836_PV0_LENGTH, RM03)
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV0_INTERRUPT }
+
+ // PixelValve1 - DS1 or SMI
+ // MEMORY32FIXED (ReadWrite, BCM2836_PV1_BASE_ADDRESS, BCM2836_PV1_LENGTH, RM04)
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV1_INTERRUPT }
+
+ // PixelValve2 - HDMI output - connected to HVS display FIFO 1
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PV2_LENGTH, RM05)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV2_INTERRUPT }
+
+ // HDMI registers
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI0_LENGTH, RM06)
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI1_LENGTH, RM07)
+ // hdmi_int[0]
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI0_INTERRUPT }
+ // hdmi_int[1]
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI1_INTERRUPT }
+
+ // HDMI DDC connection
+ I2CSerialBus (0x50,, 100000,, "\\_SB.GDV0.I2C2",,,,) // EDID
+ I2CSerialBus (0x30,, 100000,, "\\_SB.GDV0.I2C2",,,,) // E-DDC Segment Pointer
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_V3D_BUS_OFFSET)
+ MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_HVS_OFFSET)
+ MEMORY32SETBASE (RBUF, RM05, RB05, BCM2836_PV2_OFFSET)
+ MEMORY32SETBASE (RBUF, RM06, RB06, BCM2836_HDMI0_OFFSET)
+ MEMORY32SETBASE (RBUF, RM07, RB07, BCM2836_HDMI1_OFFSET)
+ Return (^RBUF)
+ }
+
+ // GPU Power Management Component Data
+ // Reference : https://github.com/Microsoft/graphics-driver-samples/wiki/Install-Driver-in-a-Windows-VM
+ Method (PMCD, 0, Serialized)
+ {
+ Name (RBUF, Package ()
+ {
+ 1, // Version
+ 1, // Number of graphics power components
+ Package () // Power components package
+ {
+ Package () // GPU component package
+ {
+ 0, // Component Index
+ 0, // DXGK_POWER_COMPONENT_MAPPING.ComponentType (0 = DXGK_POWER_COMPONENT_ENGINE)
+ 0, // DXGK_POWER_COMPONENT_MAPPING.NodeIndex
+
+ Buffer () // DXGK_POWER_RUNTIME_COMPONENT.ComponentGuid
+ { // 9B2D1E26-1575-4747-8FC0-B9EB4BAA2D2B
+ 0x26, 0x1E, 0x2D, 0x9B, 0x75, 0x15, 0x47, 0x47,
+ 0x8f, 0xc0, 0xb9, 0xeb, 0x4b, 0xaa, 0x2d, 0x2b
+ },
+
+ "VC4_Engine_00",// DXGK_POWER_RUNTIME_COMPONENT.ComponentName
+ 2, // DXGK_POWER_RUNTIME_COMPONENT.StateCount
+
+ Package () // DXGK_POWER_RUNTIME_COMPONENT.States[] package
+ {
+ Package () // F0
+ {
+ 0, // DXGK_POWER_RUNTIME_STATE.TransitionLatency
+ 0, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement
+ 1210000, // DXGK_POWER_RUNTIME_STATE.NominalPower (microwatt)
+ },
+
+ Package () // F1 - Placeholder
+ {
+ 10000, // DXGK_POWER_RUNTIME_STATE.TransitionLatency
+ 10000, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement
+ 4, // DXGK_POWER_RUNTIME_STATE.NominalPower
+ },
+ }
+ }
+ }
+ })
+ Return (RBUF)
+ }
+}
+
+// PiQ Mailbox Driver
+Device (RPIQ)
+{
+ Name (_HID, "BCM2849")
+ Name (_CID, "BCM2849")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_MBOX_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_MBOX_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MBOX_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// VCHIQ Driver
+Device (VCIQ)
+{
+ Name (_HID, "BCM2835")
+ Name (_CID, "BCM2835")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_VCHIQ_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_VCHIQ_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_VCHIQ_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// VC Shared Memory Driver
+Device (VCSM)
+{
+ Name (_HID, "BCM2856")
+ Name (_CID, "BCM2856")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.VCIQ })
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+}
+
+// Description: GPIO
+Device (GPI0)
+{
+ Name (_HID, "BCM2845")
+ Name (_CID, "BCM2845")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, GPIO_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ BCM2386_GPIO_INTERRUPT0, BCM2386_GPIO_INTERRUPT1,
+ BCM2386_GPIO_INTERRUPT2, BCM2386_GPIO_INTERRUPT3
+ }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, GPIO_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// Description: I2C
+Device (I2C1)
+{
+ Name (_HID, "BCM2841")
+ Name (_CID, "BCM2841")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C1_INTERRUPT }
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 2, 3 }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C1_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// I2C2 is the HDMI DDC connection
+Device (I2C2)
+{
+ Name (_HID, "BCM2841")
+ Name (_CID, "BCM2841")
+ Name (_UID, 0x2)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C2_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C2_INTERRUPT }
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C2_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// SPI
+Device (SPI0)
+{
+ Name (_HID, "BCM2838")
+ Name (_CID, "BCM2838")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI0_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_SPI0_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 9, 10, 11 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 8 } // CE0
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 7 } // CE1
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI0_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+Device (SPI1)
+{
+ Name (_HID, "BCM2839")
+ Name (_CID, "BCM2839")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI1_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 19, 20, 21 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 16 } // CE2
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI1_OFFSET)
+ Return (^RBUF)
+ }
+}
+
+// SPI2 has no pins on GPIO header
+// Device (SPI2)
+// {
+// Name (_HID, "BCM2839")
+// Name (_CID, "BCM2839")
+// Name (_UID, 0x2)
+// Name (_CCA, 0x0)
+// Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+// Method (_STA)
+// {
+// Return (0xf) // Disabled
+// }
+// Method (_CRS, 0x0, Serialized)
+// {
+// Name (RBUF, ResourceTemplate ()
+// {
+// MEMORY32FIXED (ReadWrite, BCM2836_SPI2_BASE_ADDRESS, BCM2836_SPI2_LENGTH, RMEM)
+// Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI2_INTERRUPT }
+// })
+// Return (RBUF)
+// }
+// }
+
+// PWM Driver
+Device (PWM0)
+{
+ Name (_HID, "BCM2844")
+ Name (_CID, "BCM2844")
+ Name (_UID, 0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ // DMA channel 11 control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_DMA_LENGTH, RM01)
+ // PWM control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CTRL_LENGTH, RM02)
+ // PWM control bus
+ MEMORY32FIXED (ReadWrite, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH, )
+ // PWM control uncached
+ MEMORY32FIXED (ReadWrite, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH, )
+ // PWM clock control
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CLK_LENGTH, RM03)
+ // Interrupt DMA channel 11
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_DMA_INTERRUPT }
+ // DMA channel 11, DREQ 5 for PWM
+ FixedDMA (5, 11, Width32Bit, )
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_PWM_DMA_OFFSET)
+ MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_PWM_CTRL_OFFSET)
+ MEMORY32SETBASE (RBUF, RM03, RB03, BCM2836_PWM_CLK_OFFSET)
+ Return (^RBUF)
+ }
+}
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/pci.asl b/board/raspberrypi/rpi/pci.asl
new file mode 100644
index 0000000..a7a09df
--- /dev/null
+++ b/board/raspberrypi/rpi/pci.asl
@@ -0,0 +1,177 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device(PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package (4) { 0x0000FFFF, 0, zero, 175 },
+ Package (4) { 0x0000FFFF, 1, zero, 176 },
+ Package (4) { 0x0000FFFF, 2, zero, 177 },
+ Package (4) { 0x0000FFFF, 3, zero, 178 }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux-ecam-quirk-id", "bcm2711" },
+ }
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+
+ // bus numbers assigned to this root
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // 32-bit mmio window in 64-bit addr
+ QWordMemory (
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0, // PCIE_PCI_MMIO_BEGIN
+ 1, // PCIE_MMIO_LEN + PCIE_PCI_MMIO_BEGIN
+ PCIE_CPU_MMIO_WINDOW, // PCIE_PCI_MMIO_BEGIN - PCIE_CPU_MMIO_WINDOW
+ 2 // PCIE_MMIO_LEN + 1
+ ,,,MMI1
+ )
+
+ // root port registers, not to be used if SMCCC is utilized
+ QWordMemory (
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, PCIE_TOP_OF_MEM_WIN, MMIB)
+ Add (PCIE_BRIDGE_MMIO_LEN, PCIE_TOP_OF_MEM_WIN, MMIE)
+ Subtract (MMIT, PCIE_TOP_OF_MEM_WIN, MMIT)
+ Add (PCIE_BRIDGE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+
+ // OS Control Handoff
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Device (XHC0)
+ {
+ Name (_ADR, 0x00010000)
+ Name (_CID, "PNP0D10")
+ Name (_UID, 0x0) // _UID: Unique ID
+ Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
+
+ /*
+ * Microsoft's USB Device-Specific Methods. See:
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
+ */
+ Name (DSMU, ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899"))
+
+ Method (_DSM, 4, Serialized) {
+ If (LEqual (Arg0, DSMU)) { // USB capabilities UUID
+ Switch (ToInteger (Arg2)) {
+ Case (0) { // Function 0: List of supported functions
+ Return (Buffer () { 0x41 }) // 0x41 - Functions 0 and 6 supported
+ }
+ Case (6) { // Function 6: RegisterAccessType
+ Return (Buffer () { 0x01 }) // 0x01 - Must use 32bit register access
+ }
+ Default { } // Unsupported
+ }
+ }
+ return (Buffer () { 0x00 }) // Return 0x00 for anything unsupported
+ }
+ } // end XHC0
+
+} // PCI0
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/pep.asl b/board/raspberrypi/rpi/pep.asl
new file mode 100644
index 0000000..87469e2
--- /dev/null
+++ b/board/raspberrypi/rpi/pep.asl
@@ -0,0 +1,90 @@
+/** @file
+ *
+ * Platform Extension Plugin (PEP).
+ *
+ * Copyright (c) 2019, ARM Ltd. All rights reserved.
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device(PEPD)
+{
+ //
+ // PEP virtual device.
+ //
+ Name (_HID, "BCM2854") // Note: Since PEP on RPi is a virtual device,
+ Name (_CID, "BCM2854") // its device id needs to be generated by Microsoft
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ // No hardware resources for PEP driver are needed.
+ })
+
+ //
+ // Processor info. PEP proprietary method to return
+ // PEP_PROCESSOR_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GPI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53,
+ 0x00, 0x42, 0x00, 0x2E, 0x00, 0x43, 0x00, 0x50, 0x00, 0x55, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+
+ //
+ // Coordinated state info. PEP proprietary method to return
+ // PEP_COORDINATED_STATE_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GCI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00
+ })
+
+ //
+ // Device info. PEP proprietary method to return
+ // PEP_DEVICE_TABLE_PLAT structure.
+ //
+ // See Pep.h and Pep.c.
+ //
+ Name (_GDI, Buffer()
+ {
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53,
+ 0x00, 0x42, 0x00, 0x2E, 0x00, 0x49, 0x00, 0x32, 0x00, 0x43, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+}
diff --git a/board/raspberrypi/rpi/rhpx.asl b/board/raspberrypi/rpi/rhpx.asl
new file mode 100644
index 0000000..214b55c
--- /dev/null
+++ b/board/raspberrypi/rpi/rhpx.asl
@@ -0,0 +1,195 @@
+/** @file
+ *
+ * [DSDT] RHProxy device to enable WinRT API (RHPX)
+ *
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+Device (RHPX)
+{
+ Name (_HID, "MSFT8000")
+ Name (_CID, "MSFT8000")
+ Name (_UID, 1)
+
+ Name(_CRS, ResourceTemplate ()
+ {
+ // Index 0
+ SPISerialBus ( // SCKL - GPIO 11 - Pin 23
+ // MOSI - GPIO 10 - Pin 19
+ // MISO - GPIO 9 - Pin 21
+ // CE0 - GPIO 8 - Pin 24
+ 0, // Device selection (CE0)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 1
+ SPISerialBus ( // SCKL - GPIO 11 - Pin 23
+ // MOSI - GPIO 10 - Pin 19
+ // MISO - GPIO 9 - Pin 21
+ // CE1 - GPIO 7 - Pin 26
+ 1, // Device selection (CE1)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 2
+ I2CSerialBus ( // Pin 3 (GPIO2, SDA1), 5 (GPIO3, SCL1)
+ 0xFFFF, // SlaveAddress: placeholder
+ , // SlaveMode: default to ControllerInitiated
+ 0, // ConnectionSpeed: placeholder
+ , // Addressing Mode: default to 7 bit
+ "\\_SB.GDV0.I2C1", // ResourceSource: I2C bus controller name
+ ,
+ ,
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // Index 3
+ SPISerialBus ( // SPI1_SCLK - GPIO21
+ // SPI1_MOSI - GPIO20
+ // SPI1_MISO - GPIO19
+ // SPI1_CE2_N - GPIO16
+ 2, // Device selection (CE2)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // WireMode
+ 8, // DataBit len
+ ControllerInitiated, // Slave mode
+ 4000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseFirst, // Clock phase
+ "\\_SB.GDV0.SPI1", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // GPIO 2
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 2 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 2 }
+ // GPIO 3
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 3 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 3 }
+ // GPIO 4
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 4 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 4 }
+ // GPIO 5
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 5 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 5 }
+ // GPIO 6
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 6 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 6 }
+ // GPIO 7
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 7 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 7 }
+ // GPIO 8
+ GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 8 }
+ GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 8 }
+ // GPIO 9
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 9 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 9 }
+ // GPIO 10
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 10 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 10 }
+ // GPIO 11
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 11 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 11 }
+ // GPIO 12
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 12 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 12 }
+ // GPIO 13
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 13 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 13 }
+ // NTRAID#MSFT-7141401-2016/04/7-jordanrh - disable UART muxing
+ // until a proper solution can be created for the dmap conflict
+ // GPIO 14 - UART TX
+ // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 14 }
+ // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 14 }
+ // GPIO 15 - UART RX
+ // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 15 }
+ // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 15 }
+ // GPIO 16
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 16 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 16 }
+ // GPIO 17
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 17 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 17 }
+ // GPIO 18
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 18 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 18 }
+ // GPIO 19
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 19 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 19 }
+ // GPIO 20
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 20 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 20 }
+ // GPIO 21
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 21 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 21 }
+ // GPIO 22
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 22 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 22 }
+ // GPIO 23
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 23 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 23 }
+ // GPIO 24
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 24 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 24 }
+ // GPIO 25
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 25 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 25 }
+ // GPIO 26
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 26 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 26 }
+ // GPIO 27
+ GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 27 }
+ GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 27 }
+ })
+
+ Name (_DSD, Package()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ // Reference http://www.raspberrypi.org/documentation/hardware/raspberrypi/spi/README.md
+ // SPI 0
+ Package (2) { "bus-SPI-SPI0", Package() { 0, 1 } }, // Index 0 & 1
+ Package (2) { "SPI0-MinClockInHz", 7629 }, // 7629 Hz
+ Package (2) { "SPI0-MaxClockInHz", 125000000 }, // 125 MHz
+ Package (2) { "SPI0-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length
+ // I2C1
+ Package (2) { "bus-I2C-I2C1", Package() { 2 } },
+ // GPIO Pin Count and supported drive modes
+ Package (2) { "GPIO-PinCount", 54 },
+ Package (2) { "GPIO-UseDescriptorPinNumbers", 1 },
+ Package (2) { "GPIO-SupportedDriveModes", 0xf }, // InputHighImpedance, InputPullUp, InputPullDown, OutputCmos
+ // SPI 1
+ Package (2) { "bus-SPI-SPI1", Package() { 3 }}, // Index 3
+ Package (2) { "SPI1-MinClockInHz", 30511 }, // 30.5 kHz
+ Package (2) { "SPI1-MaxClockInHz", 20000000 }, // 20 MHz
+ Package (2) { "SPI1-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length
+ }
+ })
+}
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index ab5ea85..9122f33 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -23,6 +23,11 @@
#endif
#include <watchdog.h>
#include <dm/pinctrl.h>
+#include <dm/ofnode.h>
+#include <acpi/acpi_table.h>
+#include <acpi/acpigen.h>
+#include <dm/lists.h>
+#include <tables_csum.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -583,3 +588,181 @@
return 0;
}
+
+#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
+static bool is_rpi4(void)
+{
+ return of_machine_is_compatible("brcm,bcm2711") ||
+ of_machine_is_compatible("brcm,bcm2712");
+}
+
+static bool is_rpi3(void)
+{
+ return of_machine_is_compatible("brcm,bcm2837");
+}
+
+static int acpi_rpi_board_fill_ssdt(struct acpi_ctx *ctx)
+{
+ int node, ret, uart_in_use, mini_clock_rate;
+ bool enabled;
+ struct udevice *dev;
+ struct {
+ const char *fdt_compatible;
+ const char *acpi_scope;
+ bool on_rpi4;
+ bool on_rpi3;
+ u32 mmio_address;
+ } map[] = {
+ {"brcm,bcm2711-pcie", "\\_SB.PCI0", true, false},
+ {"brcm,bcm2711-emmc2", "\\_SB.GDV1.SDC3", true, false},
+ {"brcm,bcm2835-pwm", "\\_SB.GDV0.PWM0", true, true},
+ {"brcm,bcm2711-genet-v5", "\\_SB.ETH0", true, false},
+ {"brcm,bcm2711-thermal", "\\_SB.EC00", true, true},
+ {"brcm,bcm2835-sdhci", "\\_SB.SDC1", true, true},
+ {"brcm,bcm2835-sdhost", "\\_SB.SDC2", false, true},
+ {"brcm,bcm2835-mbox", "\\_SB.GDV0.RPIQ", true, true},
+ {"brcm,bcm2835-i2c", "\\_SB.GDV0.I2C1", true, true, 0xfe205000},
+ {"brcm,bcm2835-i2c", "\\_SB.GDV0.I2C2", true, true, 0xfe804000},
+ {"brcm,bcm2835-spi", "\\_SB.GDV0.SPI0", true, true},
+ {"brcm,bcm2835-aux-spi", "\\_SB.GDV0.SPI1", true, true, 0xfe215080},
+ {"arm,pl011", "\\_SB.URT0", true, true},
+ {"brcm,bcm2835-aux-uart", "\\_SB.URTM", true, true},
+ { /* Sentinel */ }
+ };
+
+ /* Device enable */
+ for (int i = 0; map[i].fdt_compatible; i++) {
+ if ((is_rpi4() && !map[i].on_rpi4) ||
+ (is_rpi3() && !map[i].on_rpi3)) {
+ enabled = false;
+ } else {
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ map[i].fdt_compatible);
+ while (node != -FDT_ERR_NOTFOUND && map[i].mmio_address) {
+ struct fdt_resource r;
+
+ ret = fdt_get_resource(gd->fdt_blob, node, "reg", 0, &r);
+ if (ret) {
+ node = -FDT_ERR_NOTFOUND;
+ break;
+ }
+
+ if (r.start == map[i].mmio_address)
+ break;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ map[i].fdt_compatible);
+ }
+
+ enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0;
+ }
+ acpigen_write_scope(ctx, map[i].acpi_scope);
+ acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0);
+ acpigen_pop_len(ctx);
+ }
+
+ /* GPIO quirks */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2835-gpio");
+ if (node <= 0)
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2711-gpio");
+
+ acpigen_write_scope(ctx, "\\_SB.GDV0.GPI0");
+ enabled = (node > 0) ? fdtdec_get_is_enabled(gd->fdt_blob, node) : 0;
+ acpigen_write_name_integer(ctx, "_STA", enabled ? 0xf : 0);
+ acpigen_pop_len(ctx);
+
+ if (is_rpi4()) {
+ /* eMMC quirks */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "brcm,bcm2711-emmc2");
+ if (node) {
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 size;
+
+ ret = fdt_get_dma_range(gd->fdt_blob, node, &cpu, &bus, &size);
+
+ acpigen_write_scope(ctx, "\\_SB.GDV1");
+ acpigen_write_method_serialized(ctx, "_DMA", 0);
+ acpigen_emit_byte(ctx, RETURN_OP);
+
+ if (!ret && bus != cpu) /* Translated DMA range */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMTR");
+ else if (!ret && bus == cpu) /* Non translated DMA */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMNT");
+ else /* Silicon revisions older than C0: Translated DMA range */
+ acpigen_emit_namestring(ctx, "\\_SB.GDV1.DMTR");
+ acpigen_pop_len(ctx);
+ }
+ }
+
+ /* Serial */
+ uart_in_use = ~0;
+ mini_clock_rate = 0x1000000;
+
+ ret = uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_DRIVER_GET(bcm283x_pl011_uart),
+ &dev);
+ if (!ret)
+ uart_in_use = 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_DRIVER_GET(serial_bcm283x_mu),
+ &dev);
+ if (!ret) {
+ if (uart_in_use == 0)
+ log_err("Invalid config: PL011 and MiniUART are both enabled.");
+ else
+ uart_in_use = 1;
+
+ mini_clock_rate = dev_read_u32_default(dev, "clock", 0x1000000);
+ }
+ if (uart_in_use > 1)
+ log_err("No working serial: PL011 and MiniUART are both disabled.");
+
+ acpigen_write_scope(ctx, "\\_SB.BTH0");
+ acpigen_write_name_integer(ctx, "URIU", uart_in_use);
+ acpigen_pop_len(ctx);
+
+ acpigen_write_scope(ctx, "\\_SB.URTM");
+ acpigen_write_name_integer(ctx, "MUCR", mini_clock_rate);
+ acpigen_pop_len(ctx);
+
+ return 0;
+}
+
+static int rpi_acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *ssdt;
+ int ret;
+
+ ssdt = ctx->current;
+ memset(ssdt, '\0', sizeof(struct acpi_table_header));
+
+ acpi_fill_header(ssdt, "SSDT");
+ ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT);
+ ssdt->creator_revision = 1;
+ ssdt->length = sizeof(struct acpi_table_header);
+
+ acpi_inc(ctx, sizeof(struct acpi_table_header));
+
+ ret = acpi_rpi_board_fill_ssdt(ctx);
+ if (ret) {
+ ctx->current = ssdt;
+ return log_msg_ret("fill", ret);
+ }
+
+ /* (Re)calculate length and checksum */
+ ssdt->length = ctx->current - (void *)ssdt;
+ ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+ log_debug("SSDT at %p, length %x\n", ssdt, ssdt->length);
+
+ /* Drop the table if it is empty */
+ if (ssdt->length == sizeof(struct acpi_table_header))
+ return log_msg_ret("fill", -ENOENT);
+ acpi_add_table(ctx, ssdt);
+
+ return 0;
+}
+
+ACPI_WRITER(5ssdt, "SSDT", rpi_acpi_write_ssdt, 0);
+#endif
diff --git a/board/raspberrypi/rpi/sdhc.asl b/board/raspberrypi/rpi/sdhc.asl
new file mode 100644
index 0000000..3feac14
--- /dev/null
+++ b/board/raspberrypi/rpi/sdhc.asl
@@ -0,0 +1,111 @@
+/** @file
+ *
+ * [DSDT] SD controller/card definition (SDHC)
+ *
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836_sdhost.h>
+#include <asm/arch/acpi/bcm2836_sdio.h>
+
+#include "acpitables.h"
+
+//
+// Note: UEFI can use either SDHost or Arasan. We expose both to the OS.
+//
+
+// ArasanSD 3.0 SD Host Controller. (brcm,bcm2835-sdhci)
+Device (SDC1)
+{
+ Name (_HID, "BCM2847")
+ Name (_CID, "BCM2847")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, MMCHS1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS1_OFFSET)
+ Return (^RBUF)
+ }
+
+ // The standard CAPs registers on this controller
+ // appear to be 0, lets set some minimal defaults
+ // Since this cap doesn't indicate DMA capability
+ // we don't need a _DMA()
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "sdhci-caps", 0x0120fa81 },
+ }
+ })
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+}
+
+// Broadcom SDHost 2.0 SD Host Controller
+Device (SDC2)
+{
+ Name (_HID, "BCM2855")
+ Name (_CID, "BCM2855")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, SDHOST_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_SDHOST_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, SDHOST_OFFSET)
+ Return (^RBUF)
+ }
+
+ //
+ // A child device that represents the
+ // sd card, which is marked as non-removable.
+ //
+ Device (SDMM)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+ Method (_RMV) // Is removable
+ {
+ Return (0) // 0 - fixed
+ }
+ }
+}
\ No newline at end of file
diff --git a/board/raspberrypi/rpi/uart.asl b/board/raspberrypi/rpi/uart.asl
new file mode 100644
index 0000000..78dc9a7
--- /dev/null
+++ b/board/raspberrypi/rpi/uart.asl
@@ -0,0 +1,208 @@
+/** @file
+ *
+ * [DSDT] Serial devices (UART).
+ *
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ * Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#include "acpitables.h"
+
+// PL011 based UART.
+Device (URT0)
+{
+ Name (_HID, "BCM2837")
+ Name (_CID, "ARMH0011")
+ Name (_UID, 0x4)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_PL011_UART_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PL011_UART_INTERRUPT }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_PL011_UART_OFFSET)
+ Return (^RBUF)
+ }
+
+ Name (CLCK, 48000000)
+
+ Name (_DSD, Package ()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
+ {
+ Package (2) { "clock-frequency", CLCK },
+ }
+ })
+}
+
+//
+// UART Mini.
+//
+// This device is referenced in the DBG2 table, which will cause the system to
+// not start the driver when the debugger is enabled and to mark the device
+// with problem code 53 (CM_PROB_USED_BY_DEBUGGER).
+//
+
+Device (URTM)
+{
+ Name (_HID, "BCM2836")
+ Name (_CID, "BCM2836")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_MINI_UART_LENGTH, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MINI_UART_INTERRUPT }
+
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MINI_UART_OFFSET)
+ Return (^RBUF)
+ }
+
+ //
+ // Mini Uart Clock Rate will be dynamically updated during boot
+ //
+ External (\_SB.URTM.MUCR, IntObj)
+
+ Name (_DSD, Package ()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
+ {
+ Package (2) { "clock-frequency", MUCR },
+ }
+ })
+}
+
+//
+// Multifunction serial bus device to support Bluetooth function.
+//
+Device(BTH0)
+{
+ Name (_HID, "BCM2EA6")
+ Name (_CID, "BCM2EA6")
+
+ //
+ // UART In Use will be dynamically updated during boot
+ //
+ External (\_SB.BTH0.URIU, IntObj)
+
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+
+ //
+ // Resource for URT0 (PL011)
+ //
+ Name (BTPL, ResourceTemplate ()
+ {
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in BPS
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0x00, // LinesInUse: 8 1-bit flags to
+ // declare enabled control lines.
+ // Raspberry Pi does not exposed
+ // HW control signals -> not supported.
+ // Optional bits:
+ // - Bit 7 (0x80) Request To Send (RTS)
+ // - Bit 6 (0x40) Clear To Send (CTS)
+ // - Bit 5 (0x20) Data Terminal Ready (DTR)
+ // - Bit 4 (0x10) Data Set Ready (DSR)
+ // - Bit 3 (0x08) Ring Indicator (RI)
+ // - Bit 2 (0x04) Data Carrier Detect (DTD)
+ // - Bit 1 (0x02) Reserved. Must be 0.
+ // - Bit 0 (0x01) Reserved. Must be 0.
+ , // IsBigEndian:
+ // default to LittleEndian.
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to
+ // no flow control.
+ 16, // ReceiveBufferSize
+ 16, // TransmitBufferSize
+ "\\_SB.GDV0.URT0", // ResourceSource:
+ // UART bus controller name
+ , // ResourceSourceIndex: assumed to be 0
+ , // ResourceUsage: assumed to be
+ // ResourceConsumer
+ UAR0, // DescriptorName: creates name
+ // for offset of resource descriptor
+ ) // Vendor data
+ })
+
+ //
+ // Resource for URTM (miniUART)
+ //
+ Name (BTMN, ResourceTemplate ()
+ {
+ //
+ // BT UART: ResourceSource will be dynamically updated to
+ // either URT0 (PL011) or URTM (miniUART) during boot
+ //
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in BPS
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0x00, // LinesInUse: 8 1-bit flags to
+ // declare enabled control lines.
+ // Raspberry Pi does not exposed
+ // HW control signals -> not supported.
+ // Optional bits:
+ // - Bit 7 (0x80) Request To Send (RTS)
+ // - Bit 6 (0x40) Clear To Send (CTS)
+ // - Bit 5 (0x20) Data Terminal Ready (DTR)
+ // - Bit 4 (0x10) Data Set Ready (DSR)
+ // - Bit 3 (0x08) Ring Indicator (RI)
+ // - Bit 2 (0x04) Data Carrier Detect (DTD)
+ // - Bit 1 (0x02) Reserved. Must be 0.
+ // - Bit 0 (0x01) Reserved. Must be 0.
+ , // IsBigEndian:
+ // default to LittleEndian.
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to
+ // no flow control.
+ 16, // ReceiveBufferSize
+ 16, // TransmitBufferSize
+ "\\_SB.GDV0.URTM", // ResourceSource:
+ // UART bus controller name
+ , // ResourceSourceIndex: assumed to be 0
+ , // ResourceUsage: assumed to be
+ // ResourceConsumer
+ UARM, // DescriptorName: creates name
+ // for offset of resource descriptor
+ ) // Vendor data
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ if (URIU == 0)
+ {
+ //
+ // PL011 UART is configured for console output
+ // Return Mini UART for Bluetooth
+ //
+ return (^BTMN)
+ }
+ else
+ {
+ //
+ // Mini UART is configured for console output
+ // Return PL011 UART for Bluetooth
+ //
+ return (^BTPL)
+ }
+ }
+}
diff --git a/board/renesas/MAINTAINERS b/board/renesas/MAINTAINERS
new file mode 100644
index 0000000..13551cd
--- /dev/null
+++ b/board/renesas/MAINTAINERS
@@ -0,0 +1,17 @@
+RENESAS BOARDS
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+N: grpeach
+N: r2dplus
+N: r7s72100
+N: r8a66597
+N: r8a77
+N: r9a0[0-9]g
+N: rcar
+N: renesas
+N: rza1
+N: rzg2l
+N: serial_sh
+N: sh77
+N: sh_eth
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index ed292c3..e6bedc3 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -38,6 +38,8 @@
u8 mac_addr_cnt;
u8 mac_addr[8][ARP_HLEN];
char seboot_version[40 + 1];
+ u8 padding[3];
+ u32 ddr_size_mb;
} __packed;
/*
@@ -172,6 +174,14 @@
strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
}
+static bool board_is_sm(void)
+{
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+
+ return info->magic == IOT2050_INFO_MAGIC &&
+ strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0;
+}
+
static void remove_mmc1_target(void)
{
char *boot_targets = strdup(env_get("boot_targets"));
@@ -185,6 +195,15 @@
free(boot_targets);
}
+static void enable_pcie_connector_power(void)
+{
+ if (board_is_sm())
+ set_pinvalue("gpio@601000_22", "P3V3_PCIE_CON_EN", 1);
+ else
+ set_pinvalue("gpio@601000_17", "P3V3_PCIE_CON_EN", 1);
+ udelay(4 * 100);
+}
+
void set_board_info_env(void)
{
struct iot2050_info *info = IOT2050_INFO_DATA;
@@ -220,8 +239,10 @@
if (board_is_advanced()) {
if (board_is_pg1())
fdtfile = "ti/k3-am6548-iot2050-advanced.dtb";
- else if(board_is_m2())
+ else if (board_is_m2())
fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb";
+ else if (board_is_sm())
+ fdtfile = "ti/k3-am6548-iot2050-advanced-sm.dtb";
else
fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb";
} else {
@@ -237,23 +258,14 @@
env_save();
}
-static void m2_overlay_prepare(void)
+static void do_overlay_prepare(const char *overlay_path)
{
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
- const char *overlay_path;
void *overlay;
u64 loadaddr;
ofnode node;
int ret;
- if (connector_mode == BKEY_PCIEX2)
- return;
-
- if (connector_mode == BKEY_PCIE_EKEY_PCIE)
- overlay_path = "/fit-images/bkey-ekey-pcie-overlay";
- else
- overlay_path = "/fit-images/bkey-usb3-overlay";
-
node = ofnode_path(overlay_path);
if (!ofnode_valid(node))
goto fit_error;
@@ -280,6 +292,21 @@
#endif
}
+static void m2_overlay_prepare(void)
+{
+ const char *overlay_path;
+
+ if (connector_mode == BKEY_PCIEX2)
+ return;
+
+ if (connector_mode == BKEY_PCIE_EKEY_PCIE)
+ overlay_path = "/fit-images/bkey-ekey-pcie-overlay";
+ else
+ overlay_path = "/fit-images/bkey-usb3-overlay";
+
+ do_overlay_prepare(overlay_path);
+}
+
static void m2_connector_setup(void)
{
ulong m2_manual_config = env_get_ulong("m2_manual_config", 10,
@@ -288,10 +315,6 @@
struct m2_config_pins config_pins;
unsigned int n;
- /* enable M.2 connector power */
- set_pinvalue("gpio@601000_17", "P3V3_M2_EN", 1);
- udelay(4 * 100);
-
if (m2_manual_config < CONNECTOR_MODE_INVALID) {
mode_info = " [manual mode]";
connector_mode = m2_manual_config;
@@ -339,25 +362,42 @@
int dram_init(void)
{
- if (board_is_advanced())
- gd->ram_size = SZ_2G;
- else
- gd->ram_size = SZ_1G;
+ struct iot2050_info *info = IOT2050_INFO_DATA;
+ gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+
+ return gd->ram_top;
+}
+
int dram_init_banksize(void)
{
dram_init();
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ if (gd->ram_size > SZ_2G) {
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = SZ_2G;
- /* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ } else {
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = 0;
+ gd->bd->bi_dram[1].size = 0;
+ }
return 0;
}
@@ -368,8 +408,8 @@
struct iot2050_info *info = IOT2050_INFO_DATA;
char upper_name[32];
- /* skip the prefix "k3-am65x8-" */
- name += 10;
+ /* skip the prefix "ti/k3-am65x8-" */
+ name += 13;
if (info->magic != IOT2050_INFO_MAGIC ||
strlen(name) >= sizeof(upper_name))
@@ -429,6 +469,8 @@
/* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */
writel(0x3, SERDES0_LANE_SELECT);
+ enable_pcie_connector_power();
+
if (board_is_m2())
m2_connector_setup();
@@ -443,7 +485,7 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-static void m2_fdt_fixup(void *blob)
+static void variants_fdt_fixup(void *blob)
{
void *overlay_copy = NULL;
void *fdt_copy = NULL;
@@ -483,14 +525,14 @@
return;
fixup_error:
- pr_err("Could not apply M.2 device tree overlay\n");
+ pr_err("Could not apply device tree overlay\n");
goto cleanup;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
if (board_is_m2())
- m2_fdt_fixup(blob);
+ variants_fdt_fixup(blob);
return 0;
}
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index f55c6b5..3fd535e 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -41,7 +41,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"tx-internal-delay-ps", "1500"},
};
@@ -68,9 +68,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
- {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "tx-internal-delay-ps", "1500"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-adj-enabled", NULL},
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index cb60d3b..fc97c58 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -89,11 +89,11 @@
static struct mx7_calibration calib_param = {
.num_val = 5,
.values = {
- 0x0E407304,
- 0x0E447304,
- 0x0E447306,
- 0x0E447304,
- 0x0E447304,
+ 0x0E207304,
+ 0x0E247304,
+ 0x0E247306,
+ 0x0E247304,
+ 0x0E207304,
},
};
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 720bf2c..774ef7a 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -900,7 +900,8 @@
#endif
/* CPSW plat */
-#if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#if (CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)) && \
+ !CONFIG_IS_ENABLED(OF_CONTROL)
struct cpsw_slave_data slave_data[] = {
{
.slave_reg_ofs = CPSW_SLAVE0_OFFSET,
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 1166c9b..9075df0 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -16,6 +16,7 @@
#include <cpu_func.h>
#include <k3-ddrss.h>
#include <fdt_support.h>
+#include <fdt_simplefb.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <dm/uclass.h>
@@ -162,3 +163,23 @@
#endif
}
#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret = -1;
+
+ if (IS_ENABLED(CONFIG_FDT_SIMPLEFB))
+ ret = fdt_simplefb_enable_and_mem_rsv(blob);
+
+ /* If simplefb is not enabled and video is active, then at least reserve
+ * the framebuffer region to preserve the splash screen while OS is booting
+ */
+ if (IS_ENABLED(CONFIG_VIDEO) && IS_ENABLED(CONFIG_OF_LIBFDT)) {
+ if (ret && video_is_active())
+ return fdt_add_fb_mem_rsv(blob);
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
index b7605ff3..e92e8d0 100644
--- a/board/ti/j784s4/MAINTAINERS
+++ b/board/ti/j784s4/MAINTAINERS
@@ -8,6 +8,7 @@
F: configs/j784s4_evm_a72_defconfig
F: arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
F: arch/arm/dts/k3-j784s4-r5-evm.dts
+F: arch/arm/dts/k3-j784s4-r5.dtsi
F: arch/arm/dts/k3-j784s4-ddr.dtsi
F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
F: doc/board/ti/j784s4_evm.rst
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4854771..a92aa5c 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -49,8 +49,10 @@
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CFG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
- if (!(board_is_k2g_ice() || board_is_k2g_i1()))
+ if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
+ aemif_configs->base = (void *)KS2_AEMIF_CNTRL_BASE;
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ }
#endif
if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 68f401e..38dd805 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -491,7 +491,8 @@
ret |= env_set_by_index("uuid", id, uuid);
}
- if (!CONFIG_IS_ENABLED(NET))
+ if (!(CONFIG_IS_ENABLED(NET) ||
+ CONFIG_IS_ENABLED(NET_LWIP)))
continue;
for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) {
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index a3a6f21..c52ba18 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -10,14 +10,14 @@
default "generic"
config TEXT_BASE
- default 0x21200000
+ default 0x81200000
config SPL_TEXT_BASE
- default 0x20000000
+ default 0x80000000
config SPL_OPENSBI_LOAD_ADDR
hex
- default 0x20200000
+ default 0x80200000
config BOARD_SPECIFIC_OPTIONS
def_bool y
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index dc45238..6fc0512 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -57,7 +57,7 @@
max_size = gd->start_addr_sp - CONFIG_STACK_SIZE;
max_size = round_down(max_size, SZ_16M);
- status |= env_set_hex("scriptaddr", max_size + SZ_2M);
+ status |= env_set_hex("scriptaddr", (max_size - gd->ram_base) + SZ_2M);
status |= env_set_hex("pxefile_addr_r", max_size + SZ_1M);
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index d0e431e..927f398 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -51,8 +51,7 @@
# To disable bootmenu set enable_bootmenu=0
enable_bootmenu=1
-check_cc_for_default_boot=if test ${card1_name} = SCK-KV-G || test ${card1_name} = SCK-KR-G || test ${card1_name} = SCK-KD-G; then setenv bootmenu_default 1; else setenv bootmenu_default 0; fi
-som_bootmenu=if test ${enable_bootmenu} = 1; then run check_cc_for_default_boot; bootmenu; else run som_mmc_boot; fi
+som_bootmenu=if test ${enable_bootmenu} = 1; then bootmenu; else run som_mmc_boot; fi
k26_starter=SMK-K26-XCL2G
k24_starter=SMK-K24-XCL2G
diff --git a/boot/Kconfig b/boot/Kconfig
index 925afe0..7dd30a0 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -233,6 +233,7 @@
config SPL_LOAD_FIT_ADDRESS
hex "load address of fit image"
depends on SPL_LOAD_FIT
+ default 0x44000000 if ARCH_IMX8M
default 0x0
help
Specify the load address of the fit image that will be loaded
@@ -282,14 +283,6 @@
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
-config SPL_FIT_SOURCE
- string ".its source file for U-Boot FIT image"
- depends on SPL_FIT
- help
- Specifies a (platform specific) FIT source file to generate the
- U-Boot FIT image. This could specify further image to load and/or
- execute.
-
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
depends on SPL_FIT
@@ -477,6 +470,13 @@
standard boot does not support all of the features of distro boot
yet.
+config BOOTSTD_MENU
+ bool "Provide a menu of available bootflows for standard boot"
+ depends on BOOTSTD_FULL && EXPO
+ default y
+ help
+ Provide a menu of available bootflows and related options.
+
config BOOTSTD_PROG
bool "Use programmatic boot"
depends on !CMDLINE
@@ -503,7 +503,8 @@
select ANDROID_AB
select ANDROID_BOOT_IMAGE
select CMD_BCB
- select CMD_FASTBOOT
+ imply CMD_FASTBOOT
+ imply FASTBOOT if !NET_LWIP
select PARTITION_TYPE_GUID
select PARTITION_UUIDS
help
@@ -559,6 +560,7 @@
config BOOTMETH_EFILOADER
bool "Bootdev support for EFI boot"
depends on EFI_BINARY_EXEC
+ imply CMD_TFTPBOOT if CMD_NET
default y
help
Enables support for EFI boot using bootdevs. This makes the
@@ -1689,6 +1691,7 @@
config FDT_SIMPLEFB
bool "FDT tools for simplefb support"
+ depends on VIDEO
help
Enable the fdt tools to manage the simple fb nodes in device tree.
These functions can be used by board to indicate to the OS
@@ -1696,7 +1699,7 @@
memory
config ARCH_FIXUP_FDT_MEMORY
- bool "Enable arch_fixup_memory_banks() call"
+ bool "Enable fdt_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
diff --git a/boot/Makefile b/boot/Makefile
index b24f806..43def7c 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -24,6 +24,7 @@
obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootmeth-uclass.o
obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootstd-uclass.o
+obj-$(CONFIG_$(PHASE_)BOOTSTD_MENU) += bootflow_menu.o
obj-$(CONFIG_$(PHASE_)BOOTSTD_PROG) += prog_boot.o
obj-$(CONFIG_$(PHASE_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o
@@ -35,10 +36,6 @@
obj-$(CONFIG_$(PHASE_)BOOTMETH_SCRIPT) += bootmeth_script.o
obj-$(CONFIG_$(PHASE_)CEDIT) += cedit.o
obj-$(CONFIG_$(PHASE_)BOOTMETH_EFI_BOOTMGR) += bootmeth_efi_mgr.o
-ifdef CONFIG_$(PHASE_)BOOTSTD_FULL
-obj-$(CONFIG_$(PHASE_)EXPO) += bootflow_menu.o
-obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootflow_menu.o
-endif
obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_$(PHASE_)FDT_SIMPLEFB) += fdt_simplefb.o
@@ -62,6 +59,9 @@
obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o
obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o
+ifdef CONFIG_COREBOOT_SYSINFO
+obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo_build_cb.o
+endif
obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o
obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_REQUEST) += vbe_request.o
diff --git a/boot/android_ab.c b/boot/android_ab.c
index 1196a18..a287eac 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -13,13 +13,13 @@
#include <u-boot/crc.h>
/**
- * Compute the CRC-32 of the bootloader control struct.
+ * ab_control_compute_crc() - Compute the CRC32 of the bootloader control.
+ *
+ * @abc: Bootloader control block
*
* Only the bytes up to the crc32_le field are considered for the CRC-32
* calculation.
*
- * @param[in] abc bootloader control block
- *
* Return: crc32 sum
*/
static uint32_t ab_control_compute_crc(struct bootloader_control *abc)
@@ -28,14 +28,14 @@
}
/**
- * Initialize bootloader_control to the default value.
+ * ab_control_default() - Initialize bootloader_control to the default value.
+ *
+ * @abc: Bootloader control block
*
* It allows us to boot all slots in order from the first one. This value
* should be used when the bootloader message is corrupted, but not when
* a valid message indicates that all slots are unbootable.
*
- * @param[in] abc bootloader control block
- *
* Return: 0 on success and a negative on error
*/
static int ab_control_default(struct bootloader_control *abc)
@@ -52,7 +52,7 @@
if (!abc)
return -EFAULT;
- memcpy(abc->slot_suffix, "a\0\0\0", 4);
+ memcpy(abc->slot_suffix, "_a\0\0", 4);
abc->magic = BOOT_CTRL_MAGIC;
abc->version = BOOT_CTRL_VERSION;
abc->nb_slot = NUM_SLOTS;
@@ -67,7 +67,13 @@
}
/**
- * Load the boot_control struct from disk into newly allocated memory.
+ * ab_control_create_from_disk() - Load the boot_control from disk into memory.
+ *
+ * @dev_desc: Device where to read the boot_control struct from
+ * @part_info: Partition in 'dev_desc' where to read from, normally
+ * the "misc" partition should be used
+ * @abc: pointer to pointer to bootloader_control data
+ * @offset: boot_control struct offset
*
* This function allocates and returns an integer number of disk blocks,
* based on the block size of the passed device to help performing a
@@ -75,10 +81,6 @@
* The boot_control struct offset (2 KiB) must be a multiple of the device
* block size, for simplicity.
*
- * @param[in] dev_desc Device where to read the boot_control struct from
- * @param[in] part_info Partition in 'dev_desc' where to read from, normally
- * the "misc" partition should be used
- * @param[out] pointer to pointer to bootloader_control data
* Return: 0 on success and a negative on error
*/
static int ab_control_create_from_disk(struct blk_desc *dev_desc,
@@ -122,15 +124,17 @@
}
/**
- * Store the loaded boot_control block.
+ * ab_control_store() - Store the loaded boot_control block.
+ *
+ * @dev_desc: Device where we should write the boot_control struct
+ * @part_info: Partition on the 'dev_desc' where to write
+ * @abc Pointer to the boot control struct and the extra bytes after
+ * it up to the nearest block boundary
+ * @offset: boot_control struct offset
*
* Store back to the same location it was read from with
* ab_control_create_from_misc().
*
- * @param[in] dev_desc Device where we should write the boot_control struct
- * @param[in] part_info Partition on the 'dev_desc' where to write
- * @param[in] abc Pointer to the boot control struct and the extra bytes after
- * it up to the nearest block boundary
* Return: 0 on success and a negative on error
*/
static int ab_control_store(struct blk_desc *dev_desc,
@@ -160,12 +164,13 @@
}
/**
- * Compare two slots.
+ * ab_compare_slots() - Compare two slots.
+ *
+ * @a: The first bootable slot metadata
+ * @b: The second bootable slot metadata
*
* The function determines slot which is should we boot from among the two.
*
- * @param[in] a The first bootable slot metadata
- * @param[in] b The second bootable slot metadata
* Return: Negative if the slot "a" is better, positive of the slot "b" is
* better or 0 if they are equally good.
*/
@@ -323,7 +328,8 @@
* or the device tree.
*/
memset(slot_suffix, 0, sizeof(slot_suffix));
- slot_suffix[0] = BOOT_SLOT_NAME(slot);
+ slot_suffix[0] = '_';
+ slot_suffix[1] = BOOT_SLOT_NAME(slot);
if (memcmp(abc->slot_suffix, slot_suffix,
sizeof(slot_suffix))) {
memcpy(abc->slot_suffix, slot_suffix,
@@ -367,3 +373,71 @@
return slot;
}
+
+int ab_dump_abc(struct blk_desc *dev_desc, struct disk_partition *part_info)
+{
+ struct bootloader_control *abc;
+ u32 crc32_le;
+ int i, ret;
+ struct slot_metadata *slot;
+
+ if (!dev_desc || !part_info) {
+ log_err("ANDROID: Empty device descriptor or partition info\n");
+ return -EINVAL;
+ }
+
+ ret = ab_control_create_from_disk(dev_desc, part_info, &abc, 0);
+ if (ret < 0) {
+ log_err("ANDROID: Cannot create bcb from disk %d\n", ret);
+ return ret;
+ }
+
+ if (abc->magic != BOOT_CTRL_MAGIC) {
+ log_err("ANDROID: Unknown A/B metadata: %.8x\n", abc->magic);
+ ret = -ENODATA;
+ goto error;
+ }
+
+ if (abc->version > BOOT_CTRL_VERSION) {
+ log_err("ANDROID: Unsupported A/B metadata version: %.8x\n",
+ abc->version);
+ ret = -ENODATA;
+ goto error;
+ }
+
+ if (abc->nb_slot > ARRAY_SIZE(abc->slot_info)) {
+ log_err("ANDROID: Wrong number of slots %u, expected %zu\n",
+ abc->nb_slot, ARRAY_SIZE(abc->slot_info));
+ ret = -ENODATA;
+ goto error;
+ }
+
+ printf("Bootloader Control: [%s]\n", part_info->name);
+ printf("Active Slot: %s\n", abc->slot_suffix);
+ printf("Magic Number: 0x%x\n", abc->magic);
+ printf("Version: %u\n", abc->version);
+ printf("Number of Slots: %u\n", abc->nb_slot);
+ printf("Recovery Tries Remaining: %u\n", abc->recovery_tries_remaining);
+
+ printf("CRC: 0x%.8x", abc->crc32_le);
+
+ crc32_le = ab_control_compute_crc(abc);
+ if (abc->crc32_le != crc32_le)
+ printf(" (Invalid, Expected: 0x%.8x)\n", crc32_le);
+ else
+ printf(" (Valid)\n");
+
+ for (i = 0; i < abc->nb_slot; ++i) {
+ slot = &abc->slot_info[i];
+ printf("\nSlot[%d] Metadata:\n", i);
+ printf("\t- Priority: %u\n", slot->priority);
+ printf("\t- Tries Remaining: %u\n", slot->tries_remaining);
+ printf("\t- Successful Boot: %u\n", slot->successful_boot);
+ printf("\t- Verity Corrupted: %u\n", slot->verity_corrupted);
+ }
+
+error:
+ free(abc);
+
+ return ret;
+}
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index 807f8df..64ec4fd 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -434,6 +434,9 @@
struct uclass *uc;
enum uclass_id id;
+ if (!CONFIG_IS_ENABLED(BLK))
+ return -ENOSYS;
+
ret = label_to_uclass(label, &seq, &method_flags);
if (ret < 0)
return log_msg_ret("uc", ret);
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 59d77d2..d8807eb 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -936,11 +936,15 @@
return ret;
*buf = '\0';
- if (!strcmp("earlycon", arg)) {
+ if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
snprintf(buf, sizeof(buf),
"uart8250,mmio32,%#lx,%dn8", info.addr,
info.baudrate);
- } else if (!strcmp("console", arg)) {
+ } else if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_PL01X) {
+ snprintf(buf, sizeof(buf),
+ "pl011,mmio32,%#lx,%dn8", info.addr,
+ info.baudrate);
+ } else if (!strcmp("console", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
snprintf(buf, sizeof(buf),
"ttyS0,%dn8", info.baudrate);
}
diff --git a/boot/cedit.c b/boot/cedit.c
index c29a2be..d69290c 100644
--- a/boot/cedit.c
+++ b/boot/cedit.c
@@ -20,6 +20,7 @@
#include <video.h>
#include <linux/delay.h>
#include "scene_internal.h"
+#include <u-boot/schedule.h>
enum {
CMOS_MAX_BITS = 2048,
@@ -51,10 +52,11 @@
int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id)
{
+ struct expo_arrange_info arr;
struct scene_obj_txt *txt;
struct scene_obj *obj;
struct scene *scn;
- int y;
+ int y, ret;
scn = expo_lookup_scene_id(exp, scene_id);
if (!scn)
@@ -68,6 +70,11 @@
if (txt)
scene_obj_set_pos(scn, txt->obj.id, 200, 10);
+ memset(&arr, '\0', sizeof(arr));
+ ret = scene_calc_arrange(scn, &arr);
+ if (ret < 0)
+ return log_msg_ret("arr", ret);
+
y = 100;
list_for_each_entry(obj, &scn->obj_head, sibling) {
switch (obj->type) {
@@ -77,12 +84,13 @@
break;
case SCENEOBJT_MENU:
scene_obj_set_pos(scn, obj->id, 50, y);
- scene_menu_arrange(scn, (struct scene_obj_menu *)obj);
+ scene_menu_arrange(scn, &arr,
+ (struct scene_obj_menu *)obj);
y += 50;
break;
case SCENEOBJT_TEXTLINE:
scene_obj_set_pos(scn, obj->id, 50, y);
- scene_textline_arrange(scn,
+ scene_textline_arrange(scn, &arr,
(struct scene_obj_textline *)obj);
y += 50;
break;
@@ -147,7 +155,7 @@
struct video_priv *vid_priv;
uint scene_id;
struct scene *scn;
- bool done;
+ bool done, save;
int ret;
cli_ch_init(cch);
@@ -157,6 +165,7 @@
scene_id = ret;
done = false;
+ save = false;
do {
struct expo_action act;
int ichar, key;
@@ -201,6 +210,15 @@
case EXPOACT_OPEN:
scene_set_open(scn, act.select.id, true);
cedit_arange(exp, vid_priv, scene_id);
+ switch (scn->highlight_id) {
+ case EXPOID_SAVE:
+ done = true;
+ save = true;
+ break;
+ case EXPOID_DISCARD:
+ done = true;
+ break;
+ }
break;
case EXPOACT_CLOSE:
scene_set_open(scn, act.select.id, false);
@@ -222,6 +240,8 @@
if (ret)
return log_msg_ret("end", ret);
+ if (!save)
+ return -EACCES;
return 0;
}
@@ -274,11 +294,49 @@
return 0;
}
+/**
+ * get_cur_menuitem_val() - Get the value of a menu's current item
+ *
+ * Obtains the value of the current item in the menu. If no value, then
+ * enumerates the items of a menu (0, 1, 2) and returns the sequence number of
+ * the currently selected item. If the first item is selected, this returns 0;
+ * if the second, 1; etc.
+ *
+ * @menu: Menu to check
+ * @valp: Returns current-item value / sequence number
+ * Return: 0 on success, else -ve error value
+ */
+static int get_cur_menuitem_val(const struct scene_obj_menu *menu, int *valp)
+{
+ const struct scene_menitem *mi;
+ int seq;
+
+ seq = 0;
+ list_for_each_entry(mi, &menu->item_head, sibling) {
+ if (mi->id == menu->cur_item_id) {
+ *valp = mi->value == INT_MAX ? seq : mi->value;
+ return 0;
+ }
+ seq++;
+ }
+
+ return log_msg_ret("nf", -ENOENT);
+}
+
+/**
+ * write_dt_string() - Write a string to the devicetree, expanding if needed
+ *
+ * If this fails, it tries again after expanding the devicetree a little
+ *
+ * @buf: Buffer containing the devicetree
+ * @name: Property name to use
+ * @str: String value
+ * Return: 0 if OK, -EFAULT if something went horribly wrong
+ */
static int write_dt_string(struct abuf *buf, const char *name, const char *str)
{
int ret, i;
- /* write the text of the current item */
ret = -EAGAIN;
for (i = 0; ret && i < 2; i++) {
ret = fdt_property_string(abuf_data(buf), name, str);
@@ -296,6 +354,38 @@
return 0;
}
+/**
+ * write_dt_u32() - Write an int to the devicetree, expanding if needed
+ *
+ * If this fails, it tries again after expanding the devicetree a little
+ *
+ * @buf: Buffer containing the devicetree
+ * @name: Property name to use
+ * @lva: Integer value
+ * Return: 0 if OK, -EFAULT if something went horribly wrong
+ */
+static int write_dt_u32(struct abuf *buf, const char *name, uint val)
+{
+ int ret, i;
+
+ /* write the text of the current item */
+ ret = -EAGAIN;
+ for (i = 0; ret && i < 2; i++) {
+ ret = fdt_property_u32(abuf_data(buf), name, val);
+ if (!i) {
+ ret = check_space(ret, buf);
+ if (ret)
+ return log_msg_ret("rs2", -ENOMEM);
+ }
+ }
+
+ /* this should not happen */
+ if (ret)
+ return log_msg_ret("str", -EFAULT);
+
+ return 0;
+}
+
static int h_write_settings(struct scene_obj *obj, void *vpriv)
{
struct cedit_iter_priv *priv = vpriv;
@@ -320,23 +410,21 @@
const struct scene_obj_menu *menu;
const char *str;
char name[80];
- int i;
+ int val;
/* write the ID of the current item */
menu = (struct scene_obj_menu *)obj;
- ret = -EAGAIN;
- for (i = 0; ret && i < 2; i++) {
- ret = fdt_property_u32(abuf_data(buf), obj->name,
- menu->cur_item_id);
- if (!i) {
- ret = check_space(ret, buf);
- if (ret)
- return log_msg_ret("res", -ENOMEM);
- }
- }
- /* this should not happen */
+ ret = write_dt_u32(buf, obj->name, menu->cur_item_id);
if (ret)
- return log_msg_ret("wrt", -EFAULT);
+ return log_msg_ret("wrt", ret);
+
+ snprintf(name, sizeof(name), "%s-value", obj->name);
+ ret = get_cur_menuitem_val(menu, &val);
+ if (ret < 0)
+ return log_msg_ret("cur", ret);
+ ret = write_dt_u32(buf, name, val);
+ if (ret)
+ return log_msg_ret("wr2", ret);
ret = get_cur_menuitem_text(menu, &str);
if (ret)
@@ -470,6 +558,9 @@
const char *str;
int val, ret;
+ if (obj->id < EXPOID_BASE_ID)
+ return 0;
+
snprintf(var, sizeof(var), "c.%s", obj->name);
switch (obj->type) {
@@ -499,6 +590,14 @@
ret = env_set(name, str);
if (ret)
return log_msg_ret("st2", ret);
+
+ ret = get_cur_menuitem_val(menu, &val);
+ if (ret < 0)
+ return log_msg_ret("cur", ret);
+ snprintf(name, sizeof(name), "c.%s-value", obj->name);
+ if (priv->verbose)
+ printf("%s=%d\n", name, val);
+
break;
case SCENEOBJT_TEXTLINE: {
const struct scene_obj_textline *tline;
@@ -542,6 +641,9 @@
char var[60];
int val;
+ if (obj->id < EXPOID_BASE_ID)
+ return 0;
+
snprintf(var, sizeof(var), "c.%s", obj->name);
switch (obj->type) {
@@ -559,7 +661,7 @@
/*
* note that no validation is done here, to make sure the ID is
- * valid * and actually points to a menu item
+ * valid and actually points to a menu item
*/
menu->cur_item_id = val;
break;
@@ -599,55 +701,23 @@
return 0;
}
-/**
- * get_cur_menuitem_seq() - Get the sequence number of a menu's current item
- *
- * Enumerates the items of a menu (0, 1, 2) and returns the sequence number of
- * the currently selected item. If the first item is selected, this returns 0;
- * if the second, 1; etc.
- *
- * @menu: Menu to check
- * Return: Sequence number on success, else -ve error value
- */
-static int get_cur_menuitem_seq(const struct scene_obj_menu *menu)
-{
- const struct scene_menitem *mi;
- int seq, found;
-
- seq = 0;
- found = -1;
- list_for_each_entry(mi, &menu->item_head, sibling) {
- if (mi->id == menu->cur_item_id) {
- found = seq;
- break;
- }
- seq++;
- }
-
- if (found == -1)
- return log_msg_ret("nf", -ENOENT);
-
- return found;
-}
-
static int h_write_settings_cmos(struct scene_obj *obj, void *vpriv)
{
const struct scene_obj_menu *menu;
struct cedit_iter_priv *priv = vpriv;
int val, ret;
- uint i, seq;
+ uint i;
- if (obj->type != SCENEOBJT_MENU)
+ if (obj->type != SCENEOBJT_MENU || obj->id < EXPOID_BASE_ID)
return 0;
menu = (struct scene_obj_menu *)obj;
val = menu->cur_item_id;
- ret = get_cur_menuitem_seq(menu);
+ ret = get_cur_menuitem_val(menu, &val);
if (ret < 0)
return log_msg_ret("cur", ret);
- seq = ret;
- log_debug("%s: seq=%d\n", menu->obj.name, seq);
+ log_debug("%s: val=%d\n", menu->obj.name, val);
/* figure out where to place this item */
if (!obj->bit_length)
@@ -655,11 +725,11 @@
if (obj->start_bit + obj->bit_length > CMOS_MAX_BITS)
return log_msg_ret("bit", -E2BIG);
- for (i = 0; i < obj->bit_length; i++, seq >>= 1) {
+ for (i = 0; i < obj->bit_length; i++, val >>= 1) {
uint bitnum = obj->start_bit + i;
priv->mask[CMOS_BYTE(bitnum)] |= 1 << CMOS_BIT(bitnum);
- if (seq & 1)
+ if (val & 1)
priv->value[CMOS_BYTE(bitnum)] |= BIT(CMOS_BIT(bitnum));
log_debug("bit %x %x %x\n", bitnum,
priv->mask[CMOS_BYTE(bitnum)],
@@ -693,6 +763,7 @@
}
/* write the data to the RTC */
+ log_debug("Writing CMOS\n");
first = CMOS_MAX_BYTES;
last = -1;
for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
@@ -727,7 +798,7 @@
int val, ret;
uint i;
- if (obj->type != SCENEOBJT_MENU)
+ if (obj->type != SCENEOBJT_MENU || obj->id < EXPOID_BASE_ID)
return 0;
menu = (struct scene_obj_menu *)obj;
@@ -760,7 +831,8 @@
}
/* update the current item */
- mi = scene_menuitem_find_seq(menu, val);
+ log_debug("look for menuitem value %d in menu %d\n", val, menu->obj.id);
+ mi = scene_menuitem_find_val(menu, val);
if (!mi)
return log_msg_ret("seq", -ENOENT);
@@ -794,7 +866,7 @@
goto done;
}
- /* read the data to the RTC */
+ /* indicate what bytes were read from the RTC */
first = CMOS_MAX_BYTES;
last = -1;
for (i = 0, count = 0; i < CMOS_MAX_BYTES; i++) {
diff --git a/boot/expo.c b/boot/expo.c
index ed01483..786f665 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -29,6 +29,7 @@
exp->priv = priv;
INIT_LIST_HEAD(&exp->scene_head);
INIT_LIST_HEAD(&exp->str_head);
+ exp->next_id = EXPOID_BASE_ID;
*expp = exp;
@@ -258,6 +259,8 @@
ofnode_read_u32(node, "font-size", &theme->font_size);
ofnode_read_u32(node, "menu-inset", &theme->menu_inset);
ofnode_read_u32(node, "menuitem-gap-y", &theme->menuitem_gap_y);
+ ofnode_read_u32(node, "menu-title-margin-x",
+ &theme->menu_title_margin_x);
list_for_each_entry(scn, &exp->scene_head, sibling) {
ret = scene_apply_theme(scn, theme);
diff --git a/boot/expo_build.c b/boot/expo_build.c
index a4df798..d97347e 100644
--- a/boot/expo_build.c
+++ b/boot/expo_build.c
@@ -46,7 +46,6 @@
const char *find_name, uint obj_id)
{
const char *text;
- uint str_id;
int ret;
info->err_prop = find_name;
@@ -67,14 +66,9 @@
return log_msg_ret("id", -EINVAL);
}
- ret = expo_str(scn->expo, find_name, 0, text);
+ ret = scene_txt_str(scn, find_name, obj_id, 0, text, NULL);
if (ret < 0)
return log_msg_ret("add", ret);
- str_id = ret;
-
- ret = scene_txt_str(scn, find_name, obj_id, str_id, text, NULL);
- if (ret < 0)
- return log_msg_ret("add", ret);
return ret;
}
@@ -94,7 +88,6 @@
const char *find_name, int index, uint obj_id)
{
const char *text;
- uint str_id;
int ret;
ret = ofnode_read_string_index(node, find_name, index, &text);
@@ -114,12 +107,7 @@
return log_msg_ret("id", -EINVAL);
}
- ret = expo_str(scn->expo, find_name, 0, text);
- if (ret < 0)
- return log_msg_ret("add", ret);
- str_id = ret;
-
- ret = scene_txt_str(scn, find_name, obj_id, str_id, text, NULL);
+ ret = scene_txt_str(scn, find_name, obj_id, 0, text, NULL);
if (ret < 0)
return log_msg_ret("add", ret);
@@ -227,10 +215,10 @@
static int menu_build(struct build_info *info, ofnode node, struct scene *scn,
uint id, struct scene_obj **objp)
{
+ const u32 *item_ids, *item_values;
struct scene_obj_menu *menu;
+ int ret, size, i, num_items;
uint title_id, menu_id;
- const u32 *item_ids;
- int ret, size, i;
const char *name;
name = ofnode_get_name(node);
@@ -254,9 +242,15 @@
return log_msg_ret("itm", -EINVAL);
if (!size || size % sizeof(u32))
return log_msg_ret("isz", -EINVAL);
- size /= sizeof(u32);
+ num_items = size / sizeof(u32);
- for (i = 0; i < size; i++) {
+ item_values = ofnode_read_prop(node, "item-value", &size);
+ if (item_values) {
+ if (size != num_items * sizeof(u32))
+ return log_msg_ret("vsz", -EINVAL);
+ }
+
+ for (i = 0; i < num_items; i++) {
struct scene_menitem *item;
uint label, key, desc;
@@ -280,6 +274,8 @@
desc, 0, 0, &item);
if (ret < 0)
return log_msg_ret("mi", ret);
+ if (item_values)
+ item->value = fdt32_to_cpu(item_values[i]);
}
*objp = &menu->obj;
@@ -408,7 +404,7 @@
if (ret < 0)
return log_msg_ret("tit", ret);
title_id = ret;
- scene_title_set(scn, title_id);
+ scn->title_id = title_id;
ret = add_txt_str(info, scn_node, scn, "prompt", 0);
if (ret < 0)
@@ -424,7 +420,7 @@
return 0;
}
-int build_it(struct build_info *info, ofnode root, struct expo **expp)
+static int build_it(struct build_info *info, ofnode root, struct expo **expp)
{
ofnode scenes, node;
struct expo *exp;
diff --git a/boot/expo_build_cb.c b/boot/expo_build_cb.c
new file mode 100644
index 0000000..442ad76
--- /dev/null
+++ b/boot/expo_build_cb.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Building an expo from an FDT description
+ *
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY LOGC_EXPO
+
+#include <cedit.h>
+#include <ctype.h>
+#include <errno.h>
+#include <expo.h>
+#include <log.h>
+#include <malloc.h>
+#include <vsprintf.h>
+#include <asm/cb_sysinfo.h>
+
+/**
+ * struct build_info - Information to use when building
+ */
+struct build_info {
+ const struct cb_cmos_option_table *tab;
+ struct cedit_priv *priv;
+};
+
+/**
+ * convert_to_title() - Convert text to 'title' format and allocate a string
+ *
+ * Converts "this_is_a_test" to "This is a test" so it looks better
+ *
+ * @text: Text to convert
+ * Return: Allocated string, or NULL if out of memory
+ */
+static char *convert_to_title(const char *text)
+{
+ int len = strlen(text);
+ char *buf, *s;
+
+ buf = malloc(len + 1);
+ if (!buf)
+ return NULL;
+
+ for (s = buf; *text; s++, text++) {
+ if (s == buf)
+ *s = toupper(*text);
+ else if (*text == '_')
+ *s = ' ';
+ else
+ *s = *text;
+ }
+ *s = '\0';
+
+ return buf;
+}
+
+/**
+ * menu_build() - Build a menu and add it to a scene
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @info: Build information
+ * @entry: CMOS entry to build a menu for
+ * @scn: Scene to add the menu to
+ * @objp: Returns the object pointer
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+static int menu_build(struct build_info *info,
+ const struct cb_cmos_entries *entry, struct scene *scn,
+ struct scene_obj **objp)
+{
+ struct scene_obj_menu *menu;
+ const void *ptr, *end;
+ uint menu_id;
+ char *title;
+ int ret, i;
+
+ ret = scene_menu(scn, entry->name, 0, &menu);
+ if (ret < 0)
+ return log_msg_ret("men", ret);
+ menu_id = ret;
+
+ title = convert_to_title(entry->name);
+ if (!title)
+ return log_msg_ret("con", -ENOMEM);
+
+ /* Set the title */
+ ret = scene_txt_str(scn, "title", 0, 0, title, NULL);
+ if (ret < 0)
+ return log_msg_ret("tit", ret);
+ menu->title_id = ret;
+
+ end = (void *)info->tab + info->tab->size;
+ for (ptr = (void *)info->tab + info->tab->header_length, i = 0;
+ ptr < end; i++) {
+ const struct cb_cmos_enums *enums = ptr;
+ struct scene_menitem *item;
+ uint label;
+
+ ptr += enums->size;
+ if (enums->tag != CB_TAG_OPTION_ENUM ||
+ enums->config_id != entry->config_id)
+ continue;
+
+ ret = scene_txt_str(scn, enums->text, 0, 0, enums->text, NULL);
+ if (ret < 0)
+ return log_msg_ret("tit", ret);
+ label = ret;
+
+ ret = scene_menuitem(scn, menu_id, simple_xtoa(i), 0, 0, label,
+ 0, 0, 0, &item);
+ if (ret < 0)
+ return log_msg_ret("mi", ret);
+ item->value = enums->value;
+ }
+ *objp = &menu->obj;
+
+ return 0;
+}
+
+/**
+ * scene_build() - Build a scene and all its objects
+ *
+ * See doc/developer/expo.rst for a description of the format
+ *
+ * @info: Build information
+ * @scn: Scene to add the object to
+ * Returns: 0 if OK, -ENOMEM if out of memory, -EINVAL if there is a format
+ * error, -ENOENT if there is a references to a non-existent string
+ */
+static int scene_build(struct build_info *info, struct expo *exp)
+{
+ struct scene_obj_menu *menu;
+ const void *ptr, *end;
+ struct scene_obj *obj;
+ struct scene *scn;
+ uint label, menu_id;
+ int ret;
+
+ ret = scene_new(exp, "cmos", 0, &scn);
+ if (ret < 0)
+ return log_msg_ret("scn", ret);
+
+ ret = scene_txt_str(scn, "title", 0, 0, "CMOS RAM settings", NULL);
+ if (ret < 0)
+ return log_msg_ret("add", ret);
+ scn->title_id = ret;
+
+ ret = scene_txt_str(scn, "prompt", 0, 0,
+ "UP and DOWN to choose, ENTER to select", NULL);
+ if (ret < 0)
+ return log_msg_ret("add", ret);
+
+ end = (void *)info->tab + info->tab->size;
+ for (ptr = (void *)info->tab + info->tab->header_length; ptr < end;) {
+ const struct cb_cmos_entries *entry;
+ const struct cb_record *rec = ptr;
+
+ entry = ptr;
+ ptr += rec->size;
+ if (rec->tag != CB_TAG_OPTION)
+ continue;
+ switch (entry->config) {
+ case 'e':
+ ret = menu_build(info, entry, scn, &obj);
+ break;
+ default:
+ continue;
+ }
+ if (ret < 0)
+ return log_msg_ret("add", ret);
+
+ obj->start_bit = entry->bit;
+ obj->bit_length = entry->length;
+ }
+
+ ret = scene_menu(scn, "save", EXPOID_SAVE, &menu);
+ if (ret < 0)
+ return log_msg_ret("men", ret);
+ menu_id = ret;
+
+ ret = scene_txt_str(scn, "save", 0, 0, "Save and exit", NULL);
+ if (ret < 0)
+ return log_msg_ret("sav", ret);
+ label = ret;
+ ret = scene_menuitem(scn, menu_id, "save", 0, 0, label,
+ 0, 0, 0, NULL);
+ if (ret < 0)
+ return log_msg_ret("mi", ret);
+
+ ret = scene_menu(scn, "nosave", EXPOID_DISCARD, &menu);
+ if (ret < 0)
+ return log_msg_ret("men", ret);
+ menu_id = ret;
+
+ ret = scene_txt_str(scn, "nosave", 0, 0, "Exit without saving", NULL);
+ if (ret < 0)
+ return log_msg_ret("nos", ret);
+ label = ret;
+ ret = scene_menuitem(scn, menu_id, "exit", 0, 0, label,
+ 0, 0, 0, NULL);
+ if (ret < 0)
+ return log_msg_ret("mi", ret);
+
+ return 0;
+}
+
+static int build_it(struct build_info *info, struct expo **expp)
+{
+ struct expo *exp;
+ int ret;
+
+ ret = expo_new("coreboot", NULL, &exp);
+ if (ret)
+ return log_msg_ret("exp", ret);
+ expo_set_dynamic_start(exp, EXPOID_BASE_ID);
+
+ ret = scene_build(info, exp);
+ if (ret < 0)
+ return log_msg_ret("scn", ret);
+
+ *expp = exp;
+
+ return 0;
+}
+
+int cb_expo_build(struct expo **expp)
+{
+ struct build_info info;
+ struct expo *exp;
+ int ret;
+
+ info.tab = lib_sysinfo.option_table;
+ if (!info.tab)
+ return log_msg_ret("tab", -ENOENT);
+
+ ret = build_it(&info, &exp);
+ if (ret)
+ return log_msg_ret("bui", ret);
+ *expp = exp;
+
+ return 0;
+}
diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c
index 71b833e..5822131 100644
--- a/boot/fdt_simplefb.c
+++ b/boot/fdt_simplefb.c
@@ -103,7 +103,6 @@
return fdt_simplefb_configure_node(blob, off);
}
-#if IS_ENABLED(CONFIG_VIDEO)
int fdt_simplefb_enable_and_mem_rsv(void *blob)
{
int ret;
@@ -118,4 +117,3 @@
return fdt_add_fb_mem_rsv(blob);
}
-#endif
diff --git a/boot/image-android.c b/boot/image-android.c
index e74dd49..cd01278 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -14,6 +14,7 @@
#include <linux/libfdt.h>
#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
+#define ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR 0x11000000
static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
@@ -208,7 +209,8 @@
return true;
}
-static ulong android_image_get_kernel_addr(struct andr_image_data *img_data)
+static ulong android_image_get_kernel_addr(struct andr_image_data *img_data,
+ ulong comp)
{
/*
* All the Android tools that generate a boot.img use this
@@ -221,8 +223,11 @@
*
* Otherwise, we will return the actual value set by the user.
*/
- if (img_data->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR)
- return img_data->kernel_ptr;
+ if (img_data->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR) {
+ if (comp == IH_COMP_NONE)
+ return img_data->kernel_ptr;
+ return env_get_ulong("kernel_addr_r", 16, 0);
+ }
/*
* abootimg creates images where all load addresses are 0
@@ -256,13 +261,16 @@
ulong *os_data, ulong *os_len)
{
struct andr_image_data img_data = {0};
- u32 kernel_addr;
+ ulong kernel_addr;
const struct legacy_img_hdr *ihdr;
+ ulong comp;
if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
return -EINVAL;
- kernel_addr = android_image_get_kernel_addr(&img_data);
+ comp = android_image_get_kcomp(hdr, vendor_boot_img);
+
+ kernel_addr = android_image_get_kernel_addr(&img_data, comp);
ihdr = (const struct legacy_img_hdr *)img_data.kernel_ptr;
/*
@@ -275,7 +283,7 @@
if (strlen(andr_tmp_str))
printf("Android's image name: %s\n", andr_tmp_str);
- printf("Kernel load addr 0x%08x size %u KiB\n",
+ printf("Kernel load addr 0x%08lx size %u KiB\n",
kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024));
int len = 0;
@@ -359,11 +367,14 @@
const void *vendor_boot_img)
{
struct andr_image_data img_data;
+ ulong comp;
if (!android_image_get_data(hdr, vendor_boot_img, &img_data))
return -EINVAL;
- return android_image_get_kernel_addr(&img_data);
+ comp = android_image_get_kcomp(hdr, vendor_boot_img);
+
+ return android_image_get_kernel_addr(&img_data, comp);
}
ulong android_image_get_kcomp(const void *hdr,
@@ -395,9 +406,25 @@
if (!img_data.ramdisk_size)
return -ENOENT;
-
+ /*
+ * Android tools can generate a boot.img with default load address
+ * or 0, even though it doesn't really make a lot of sense, and it
+ * might be valid on some platforms, we treat that address as
+ * the default value for this field, and try to pass ramdisk
+ * in place if possible.
+ */
if (img_data.header_version > 2) {
- ramdisk_ptr = img_data.ramdisk_addr;
+ /* Ramdisk can't be used in-place, copy it to ramdisk_addr_r */
+ if (img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR) {
+ ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0);
+ if (!ramdisk_ptr) {
+ printf("Invalid ramdisk_addr_r to copy ramdisk into\n");
+ return -EINVAL;
+ }
+ } else {
+ ramdisk_ptr = img_data.ramdisk_addr;
+ }
+ *rd_data = ramdisk_ptr;
memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr,
img_data.vendor_ramdisk_size);
ramdisk_ptr += img_data.vendor_ramdisk_size;
@@ -410,15 +437,20 @@
img_data.bootconfig_size);
}
} else {
- ramdisk_ptr = img_data.ramdisk_addr;
- memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr,
- img_data.ramdisk_size);
+ /* Ramdisk can be used in-place, use current ptr */
+ if (img_data.ramdisk_addr == 0 ||
+ img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR) {
+ *rd_data = img_data.ramdisk_ptr;
+ } else {
+ ramdisk_ptr = img_data.ramdisk_addr;
+ *rd_data = ramdisk_ptr;
+ memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr,
+ img_data.ramdisk_size);
+ }
}
printf("RAM disk load addr 0x%08lx size %u KiB\n",
- img_data.ramdisk_addr, DIV_ROUND_UP(img_data.ramdisk_size, 1024));
-
- *rd_data = img_data.ramdisk_addr;
+ *rd_data, DIV_ROUND_UP(img_data.ramdisk_size, 1024));
*rd_len = img_data.ramdisk_size;
return 0;
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 8eda521..3d5b6f9 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -73,7 +73,7 @@
long ret;
ret = lmb_reserve_flags(addr, size, flags);
- if (ret >= 0) {
+ if (!ret) {
debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
(unsigned long long)addr,
(unsigned long long)size, flags);
@@ -110,7 +110,7 @@
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- boot_fdt_reserve_region(addr, size, LMB_NONE);
+ boot_fdt_reserve_region(addr, size, LMB_NOOVERWRITE);
}
/* process reserved-memory */
@@ -122,7 +122,7 @@
ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
&res);
if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
- flags = LMB_NONE;
+ flags = LMB_NOOVERWRITE;
if (fdtdec_get_bool(fdt_blob, subnode,
"no-map"))
flags = LMB_NOMAP;
diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c
index 35873b1..a121de6 100644
--- a/boot/image-fit-sig.c
+++ b/boot/image-fit-sig.c
@@ -95,7 +95,7 @@
info->required_keynode = required_keynode;
printf("%s:%s", algo_name, info->keyname);
- if (!info->checksum || !info->crypto || !info->padding) {
+ if (!info->checksum || !info->crypto) {
*err_msgp = "Unknown signature algorithm";
return -1;
}
diff --git a/boot/scene.c b/boot/scene.c
index 270c9c6..3290a40 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -70,13 +70,6 @@
free(scn);
}
-int scene_title_set(struct scene *scn, uint id)
-{
- scn->title_id = id;
-
- return 0;
-}
-
int scene_obj_count(struct scene *scn)
{
return list_count_nodes(&scn->obj_head);
@@ -339,7 +332,7 @@
/* draw a background for the object */
if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
- fore = VID_BLACK;
+ fore = VID_DARK_GREY;
back = VID_WHITE;
} else {
fore = VID_LIGHT_GRAY;
@@ -471,11 +464,59 @@
return 0;
}
+int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr)
+{
+ struct scene_obj *obj;
+
+ arr->label_width = 0;
+ list_for_each_entry(obj, &scn->obj_head, sibling) {
+ uint label_id = 0;
+ int width;
+
+ switch (obj->type) {
+ case SCENEOBJT_NONE:
+ case SCENEOBJT_IMAGE:
+ case SCENEOBJT_TEXT:
+ break;
+ case SCENEOBJT_MENU: {
+ struct scene_obj_menu *menu;
+
+ menu = (struct scene_obj_menu *)obj,
+ label_id = menu->title_id;
+ break;
+ }
+ case SCENEOBJT_TEXTLINE: {
+ struct scene_obj_textline *tline;
+
+ tline = (struct scene_obj_textline *)obj,
+ label_id = tline->label_id;
+ break;
+ }
+ }
+
+ if (label_id) {
+ int ret;
+
+ ret = scene_obj_get_hw(scn, label_id, &width);
+ if (ret < 0)
+ return log_msg_ret("hei", ret);
+ arr->label_width = max(arr->label_width, width);
+ }
+ }
+
+ return 0;
+}
+
int scene_arrange(struct scene *scn)
{
+ struct expo_arrange_info arr;
struct scene_obj *obj;
int ret;
+ ret = scene_calc_arrange(scn, &arr);
+ if (ret < 0)
+ return log_msg_ret("arr", ret);
+
list_for_each_entry(obj, &scn->obj_head, sibling) {
switch (obj->type) {
case SCENEOBJT_NONE:
@@ -486,7 +527,7 @@
struct scene_obj_menu *menu;
menu = (struct scene_obj_menu *)obj,
- ret = scene_menu_arrange(scn, menu);
+ ret = scene_menu_arrange(scn, &arr, menu);
if (ret)
return log_msg_ret("arr", ret);
break;
@@ -495,7 +536,7 @@
struct scene_obj_textline *tline;
tline = (struct scene_obj_textline *)obj,
- ret = scene_textline_arrange(scn, tline);
+ ret = scene_textline_arrange(scn, &arr, tline);
if (ret)
return log_msg_ret("arr", ret);
break;
diff --git a/boot/scene_internal.h b/boot/scene_internal.h
index e72202c..ec9008e 100644
--- a/boot/scene_internal.h
+++ b/boot/scene_internal.h
@@ -96,10 +96,12 @@
* if not already done
*
* @scn: Scene to update
+ * @arr: Arrangement information
* @menu: Menu to process
* Returns: 0 if OK, -ve on error
*/
-int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu);
+int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr,
+ struct scene_obj_menu *menu);
/**
* scene_textline_arrange() - Set the position of things in a textline
@@ -108,10 +110,12 @@
* positioned correctly relative to the textline.
*
* @scn: Scene to update
+ * @arr: Arrangement information
* @tline: textline to process
* Returns: 0 if OK, -ve on error
*/
-int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline);
+int scene_textline_arrange(struct scene *scn, struct expo_arrange_info *arr,
+ struct scene_obj_textline *tline);
/**
* scene_apply_theme() - Apply a theme to a scene
@@ -278,6 +282,16 @@
uint seq);
/**
+ * scene_menuitem_find_val() - Find the menu item with a given value
+ *
+ * @menu: Menu to check
+ * @find_val: Value to look for
+ * Return: menu item if found, else NULL
+ */
+struct scene_menitem *scene_menuitem_find_val(const struct scene_obj_menu *menu,
+ int val);
+
+/**
* scene_bbox_union() - update bouding box with the demensions of an object
*
* Updates @bbox so that it encompasses the bounding box of object @id
@@ -358,4 +372,16 @@
*/
int scene_textline_close(struct scene *scn, struct scene_obj_textline *tline);
+/**
+ * scene_calc_arrange() - Calculate sizes needed to arrange a scene
+ *
+ * Checks the size of some objects and stores this info to help with a later
+ * scene arrangement
+ *
+ * @scn: Scene to check
+ * @arr: Place to put scene-arrangement info
+ * Returns: 0 if OK, -ve on error
+ */
+int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr);
+
#endif /* __SCENE_INTERNAL_H */
diff --git a/boot/scene_menu.c b/boot/scene_menu.c
index 80bd745..17150af 100644
--- a/boot/scene_menu.c
+++ b/boot/scene_menu.c
@@ -61,6 +61,22 @@
return NULL;
}
+struct scene_menitem *scene_menuitem_find_val(const struct scene_obj_menu *menu,
+ int val)
+{
+ struct scene_menitem *item;
+ uint i;
+
+ i = 0;
+ list_for_each_entry(item, &menu->item_head, sibling) {
+ if (item->value == INT_MAX ? val == i : item->value == val)
+ return item;
+ i++;
+ }
+
+ return NULL;
+}
+
/**
* update_pointers() - Update the pointer object and handle highlights
*
@@ -168,7 +184,8 @@
return 0;
}
-int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu)
+int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr,
+ struct scene_obj_menu *menu)
{
const bool open = menu->obj.flags & SCENEOF_OPEN;
struct expo *exp = scn->expo;
@@ -182,16 +199,18 @@
x = menu->obj.dim.x;
y = menu->obj.dim.y;
if (menu->title_id) {
+ int width;
+
ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.dim.x, y);
if (ret < 0)
return log_msg_ret("tit", ret);
- ret = scene_obj_get_hw(scn, menu->title_id, NULL);
+ ret = scene_obj_get_hw(scn, menu->title_id, &width);
if (ret < 0)
return log_msg_ret("hei", ret);
if (stack)
- x += 200;
+ x += arr->label_width + theme->menu_title_margin_x;
else
y += ret * 2;
}
@@ -413,6 +432,7 @@
item->desc_id = desc_id;
item->preview_id = preview_id;
item->flags = flags;
+ item->value = INT_MAX;
list_add_tail(&item->sibling, &menu->item_head);
if (itemp)
diff --git a/boot/scene_textline.c b/boot/scene_textline.c
index bba8663..6adef7c 100644
--- a/boot/scene_textline.c
+++ b/boot/scene_textline.c
@@ -87,7 +87,8 @@
return 0;
}
-int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline)
+int scene_textline_arrange(struct scene *scn, struct expo_arrange_info *arr,
+ struct scene_obj_textline *tline)
{
const bool open = tline->obj.flags & SCENEOF_OPEN;
bool point;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 37894eb..6368336 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -221,6 +221,13 @@
help
Register dump
+config CMD_TCPM
+ bool "tcpm"
+ depends on TYPEC_TCPM
+ help
+ Show voltage and current negotiated via USB PD as well as the
+ current state of the Type C Port Manager (TCPM) state machine.
+
config CMD_TLV_EEPROM
bool "tlv_eeprom"
depends on I2C_EEPROM
@@ -878,9 +885,21 @@
config CMD_MEMINFO
bool "meminfo"
+ default y if SANDBOX
help
Display memory information.
+config CMD_MEMINFO_MAP
+ bool "- with memory map"
+ depends on CMD_MEMINFO
+ default y if SANDBOX
+ help
+ Shows a memory map, in addition to just the DRAM size. This allows
+ seeing where U-Boot's memory area is, at the top of DRAM, as well as
+ detail about each piece of it.
+
+ See doc/usage/cmd/meminfo.rst for more information.
+
config CMD_MEMORY
bool "md, mm, nm, mw, cp, cmp, base, loop"
default y
@@ -1653,6 +1672,7 @@
config CMD_USB_SDP
bool "sdp"
+ depends on USB_GADGET_DOWNLOAD
select USB_FUNCTION_SDP
help
Enables the command "sdp" which is used to have U-Boot emulating the
@@ -1774,26 +1794,16 @@
endmenu
-menu "Android support commands"
-
-config CMD_AB_SELECT
- bool "ab_select"
- depends on ANDROID_AB
- help
- On Android devices with more than one boot slot (multiple copies of
- the kernel and system images) this provides a command to select which
- slot should be used to boot from and register the boot attempt. This
- is used by the new A/B update model where one slot is updated in the
- background while running from the other slot.
-
-endmenu
-
-if NET
+if NET || NET_LWIP
menuconfig CMD_NET
bool "Network commands"
default y
+endif
+
+if NET
+
if CMD_NET
config CMD_BOOTP
@@ -1802,12 +1812,6 @@
help
bootp - boot image via network using BOOTP/TFTP protocol
-config CMD_DHCP
- bool "dhcp"
- depends on CMD_BOOTP
- help
- Boot image via network using DHCP/TFTP protocol
-
config CMD_DHCP6
bool "dhcp6"
depends on IPV6
@@ -1951,12 +1955,6 @@
default "U-Boot.arm" if ARM
default "U-Boot"
-config CMD_TFTPBOOT
- bool "tftpboot"
- default y
- help
- tftpboot - load file via network using TFTP protocol
-
config CMD_TFTPPUT
bool "tftp put"
depends on CMD_TFTPBOOT
@@ -2008,42 +2006,6 @@
is complete. Enable this option to disable this behavior and instead
require files to be loaded over the network by subsequent commands.
-config CMD_WGET
- bool "wget"
- select PROT_TCP
- default y if SANDBOX
- help
- wget is a simple command to download kernel, or other files,
- from a http server over TCP.
-
-config CMD_MII
- bool "mii"
- imply CMD_MDIO
- help
- If set, allows 802.3(clause 22) MII Management functions interface access
- The management interface specified in Clause 22 provides
- a simple, two signal, serial interface to connect a
- Station Management entity and a managed PHY for providing access
- to management parameters and services.
- The interface is referred to as the MII management interface.
-
-config MII_INIT
- bool "Call mii_init() in the mii command"
- depends on CMD_MII && (MPC8XX_FEC || FSLDMAFE || MCFFEC)
-
-config CMD_MDIO
- bool "mdio"
- depends on PHYLIB
- help
- If set, allows Enable 802.3(clause 45) MDIO interface registers access
- The MDIO interface is orthogonal to the MII interface and extends
- it by adding access to more registers through indirect addressing.
-
-config CMD_PING
- bool "ping"
- help
- Send ICMP ECHO_REQUEST to network host
-
config CMD_PING6
bool "ping6"
depends on IPV6
@@ -2062,11 +2024,6 @@
help
Synchronize RTC via network
-config CMD_DNS
- bool "dns"
- help
- Lookup the IP of a hostname
-
config CMD_LINK_LOCAL
bool "linklocal"
select LIB_RAND
@@ -2087,7 +2044,7 @@
help
Will automatically perform router solicitation on first IPv6
network operation
-endif
+endif # if CMD_NET
config CMD_ETHSW
bool "ethsw"
@@ -2097,6 +2054,78 @@
operations such as enabling / disabling a port and
viewing/maintaining the filtering database (FDB)
+config CMD_WOL
+ bool "wol"
+ help
+ Wait for wake-on-lan Magic Packet
+
+endif # if NET
+
+if NET || NET_LWIP
+
+if CMD_NET
+
+config CMD_DHCP
+ bool "dhcp"
+ select PROT_DHCP_LWIP if NET_LWIP
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config CMD_DNS
+ bool "dns"
+ select PROT_DNS_LWIP if NET_LWIP
+ help
+ Lookup the IP of a hostname
+
+config CMD_MII
+ bool "mii"
+ imply CMD_MDIO
+ help
+ If set, allows 802.3(clause 22) MII Management functions interface access
+ The management interface specified in Clause 22 provides
+ a simple, two signal, serial interface to connect a
+ Station Management entity and a managed PHY for providing access
+ to management parameters and services.
+ The interface is referred to as the MII management interface.
+
+config MII_INIT
+ bool "Call mii_init() in the mii command"
+ depends on CMD_MII && (MPC8XX_FEC || FSLDMAFE || MCFFEC)
+
+config CMD_MDIO
+ bool "mdio"
+ depends on PHYLIB
+ help
+ If set, allows Enable 802.3(clause 45) MDIO interface registers access
+ The MDIO interface is orthogonal to the MII interface and extends
+ it by adding access to more registers through indirect addressing.
+
+config CMD_PING
+ bool "ping"
+ select PROT_RAW_LWIP if NET_LWIP
+ help
+ Send ICMP ECHO_REQUEST to network host
+
+config CMD_TFTPBOOT
+ bool "tftp"
+ select PROT_UDP_LWIP if NET_LWIP
+ default y
+ help
+ tftpboot - load file via network using TFTP protocol
+
+config CMD_WGET
+ bool "wget"
+ depends on CMD_NET
+ default y if SANDBOX
+ select PROT_TCP if NET
+ select PROT_TCP_LWIP if NET_LWIP
+ select PROT_DNS_LWIP if NET_LWIP
+ help
+ wget is a simple command to download kernel, or other files,
+ from a http server over TCP.
+
+endif # if CMD_NET
+
config CMD_PXE
bool "pxe"
select PXE_UTILS
@@ -2104,12 +2133,7 @@
help
Boot image via network using PXE protocol
-config CMD_WOL
- bool "wol"
- help
- Wait for wake-on-lan Magic Packet
-
-endif
+endif # if NET || NET_LWIP
menu "Misc commands"
@@ -2266,6 +2290,7 @@
config CMD_RTC
bool "rtc"
depends on DM_RTC
+ default y if X86
help
Enable the 'rtc' command for low-level access to RTC devices.
@@ -2846,6 +2871,17 @@
memory by coreboot before jumping to U-Boot. It can be useful for
debugging the beaaviour of coreboot or U-Boot.
+config CMD_CBCMOS
+ bool "cbcmos"
+ depends on X86
+ default y if SYS_COREBOOT
+ help
+ This provides information options to check the CMOS RAM checksum,
+ if present, as well as to update it.
+
+ It is useful when coreboot CMOS-RAM settings must be examined or
+ updated.
+
config CMD_CYCLIC
bool "cyclic - Show information about cyclic functions"
depends on CYCLIC
diff --git a/cmd/Makefile b/cmd/Makefile
index 21d3763..d1f369d 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -17,7 +17,6 @@
obj-$(CONFIG_CMD_ACPI) += acpi.o
obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
obj-$(CONFIG_CMD_AES) += aes.o
-obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o
obj-$(CONFIG_CMD_ADC) += adc.o
obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
obj-$(CONFIG_BLK) += blk_common.o
@@ -110,6 +109,7 @@
obj-$(CONFIG_CMD_LSBLK) += lsblk.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
+obj-$(CONFIG_CMD_MEMINFO) += meminfo.o
obj-$(CONFIG_CMD_IO) += io.o
obj-$(CONFIG_CMD_MII) += mii.o
obj-$(CONFIG_CMD_MISC) += misc.o
@@ -127,7 +127,11 @@
endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
-obj-$(CONFIG_CMD_NET) += net.o
+ifdef CONFIG_NET
+obj-$(CONFIG_CMD_NET) += net.o net-common.o
+else ifdef CONFIG_NET_LWIP
+obj-$(CONFIG_CMD_NET) += net-lwip.o net-common.o
+endif
obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
@@ -172,6 +176,7 @@
obj-$(CONFIG_CMD_SMC) += smccc.o
obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o
obj-$(CONFIG_CMD_STACKPROTECTOR_TEST) += stackprot_test.o
+obj-$(CONFIG_CMD_TCPM) += tcpm.o
obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
obj-$(CONFIG_CMD_TERMINAL) += terminal.o
obj-$(CONFIG_CMD_TIME) += time.o
diff --git a/cmd/ab_select.c b/cmd/ab_select.c
deleted file mode 100644
index 7c178c7..0000000
--- a/cmd/ab_select.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * Copyright (C) 2017 The Android Open Source Project
- */
-
-#include <android_ab.h>
-#include <command.h>
-#include <env.h>
-#include <part.h>
-
-static int do_ab_select(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- int ret;
- struct blk_desc *dev_desc;
- struct disk_partition part_info;
- char slot[2];
- bool dec_tries = true;
-
- if (argc < 4)
- return CMD_RET_USAGE;
-
- for (int i = 4; i < argc; i++) {
- if (strcmp(argv[i], "--no-dec") == 0) {
- dec_tries = false;
- } else {
- return CMD_RET_USAGE;
- }
- }
-
- /* Lookup the "misc" partition from argv[2] and argv[3] */
- if (part_get_info_by_dev_and_name_or_num(argv[2], argv[3],
- &dev_desc, &part_info,
- false) < 0) {
- return CMD_RET_FAILURE;
- }
-
- ret = ab_select_slot(dev_desc, &part_info, dec_tries);
- if (ret < 0) {
- printf("Android boot failed, error %d.\n", ret);
- return CMD_RET_FAILURE;
- }
-
- /* Android standard slot names are 'a', 'b', ... */
- slot[0] = BOOT_SLOT_NAME(ret);
- slot[1] = '\0';
- env_set(argv[1], slot);
- printf("ANDROID: Booting slot: %s\n", slot);
- return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(ab_select, 5, 0, do_ab_select,
- "Select the slot used to boot from and register the boot attempt.",
- "<slot_var_name> <interface> <dev[:part|#part_name]> [--no-dec]\n"
- " - Load the slot metadata from the partition 'part' on\n"
- " device type 'interface' instance 'dev' and store the active\n"
- " slot in the 'slot_var_name' variable. This also updates the\n"
- " Android slot metadata with a boot attempt, which can cause\n"
- " successive calls to this function to return a different result\n"
- " if the returned slot runs out of boot attempts.\n"
- " - If 'part_name' is passed, preceded with a # instead of :, the\n"
- " partition name whose label is 'part_name' will be looked up in\n"
- " the partition table. This is commonly the \"misc\" partition.\n"
- " - If '--no-dec' is set, the number of tries remaining will not\n"
- " decremented for the selected boot slot\n"
-);
diff --git a/cmd/bcb.c b/cmd/bcb.c
index 97a96c0..16eabfe 100644
--- a/cmd/bcb.c
+++ b/cmd/bcb.c
@@ -8,6 +8,7 @@
#include <android_bootloader_message.h>
#include <bcb.h>
#include <command.h>
+#include <android_ab.h>
#include <display_options.h>
#include <log.h>
#include <part.h>
@@ -16,15 +17,6 @@
#include <vsprintf.h>
#include <linux/err.h>
-enum bcb_cmd {
- BCB_CMD_LOAD,
- BCB_CMD_FIELD_SET,
- BCB_CMD_FIELD_CLEAR,
- BCB_CMD_FIELD_TEST,
- BCB_CMD_FIELD_DUMP,
- BCB_CMD_STORE,
-};
-
static const char * const fields[] = {
"command",
"status",
@@ -38,67 +30,9 @@
static struct blk_desc *block;
static struct disk_partition *partition = &partition_data;
-static int bcb_cmd_get(char *cmd)
-{
- if (!strcmp(cmd, "load"))
- return BCB_CMD_LOAD;
- if (!strcmp(cmd, "set"))
- return BCB_CMD_FIELD_SET;
- if (!strcmp(cmd, "clear"))
- return BCB_CMD_FIELD_CLEAR;
- if (!strcmp(cmd, "test"))
- return BCB_CMD_FIELD_TEST;
- if (!strcmp(cmd, "store"))
- return BCB_CMD_STORE;
- if (!strcmp(cmd, "dump"))
- return BCB_CMD_FIELD_DUMP;
- else
- return -1;
-}
-
-static int bcb_is_misused(int argc, char *const argv[])
+static int bcb_not_loaded(void)
{
- int cmd = bcb_cmd_get(argv[0]);
-
- switch (cmd) {
- case BCB_CMD_LOAD:
- if (argc != 3 && argc != 4)
- goto err;
- break;
- case BCB_CMD_FIELD_SET:
- if (argc != 3)
- goto err;
- break;
- case BCB_CMD_FIELD_TEST:
- if (argc != 4)
- goto err;
- break;
- case BCB_CMD_FIELD_CLEAR:
- if (argc != 1 && argc != 2)
- goto err;
- break;
- case BCB_CMD_STORE:
- if (argc != 1)
- goto err;
- break;
- case BCB_CMD_FIELD_DUMP:
- if (argc != 2)
- goto err;
- break;
- default:
- printf("Error: 'bcb %s' not supported\n", argv[0]);
- return -1;
- }
-
- if (cmd != BCB_CMD_LOAD && !block) {
- printf("Error: Please, load BCB first!\n");
- return -1;
- }
-
- return 0;
-err:
- printf("Error: Bad usage of 'bcb %s'\n", argv[0]);
-
+ printf("Error: Please, load BCB first!\n");
return -1;
}
@@ -216,6 +150,9 @@
char *endp;
char *iface = "mmc";
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
if (argc == 4) {
iface = argv[1];
argc--;
@@ -270,6 +207,12 @@
static int do_bcb_set(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ if (!block)
+ return bcb_not_loaded();
+
return __bcb_set(argv[1], argv[2]);
}
@@ -279,6 +222,9 @@
int size;
char *field;
+ if (!block)
+ return bcb_not_loaded();
+
if (argc == 1) {
memset(&bcb, 0, sizeof(bcb));
return CMD_RET_SUCCESS;
@@ -297,7 +243,15 @@
{
int size;
char *field;
- char *op = argv[2];
+ char *op;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ if (!block)
+ return bcb_not_loaded();
+
+ op = argv[2];
if (bcb_field_get(argv[1], &field, &size))
return CMD_RET_FAILURE;
@@ -325,6 +279,12 @@
int size;
char *field;
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!block)
+ return bcb_not_loaded();
+
if (bcb_field_get(argv[1], &field, &size))
return CMD_RET_FAILURE;
@@ -356,6 +316,9 @@
static int do_bcb_store(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
+ if (!block)
+ return bcb_not_loaded();
+
return __bcb_store();
}
@@ -414,44 +377,75 @@
__bcb_reset();
}
-static struct cmd_tbl cmd_bcb_sub[] = {
- U_BOOT_CMD_MKENT(load, CONFIG_SYS_MAXARGS, 1, do_bcb_load, "", ""),
- U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 1, do_bcb_set, "", ""),
- U_BOOT_CMD_MKENT(clear, CONFIG_SYS_MAXARGS, 1, do_bcb_clear, "", ""),
- U_BOOT_CMD_MKENT(test, CONFIG_SYS_MAXARGS, 1, do_bcb_test, "", ""),
- U_BOOT_CMD_MKENT(dump, CONFIG_SYS_MAXARGS, 1, do_bcb_dump, "", ""),
- U_BOOT_CMD_MKENT(store, CONFIG_SYS_MAXARGS, 1, do_bcb_store, "", ""),
-};
-
-static int do_bcb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+__maybe_unused static int do_bcb_ab_select(struct cmd_tbl *cmdtp,
+ int flag, int argc,
+ char * const argv[])
{
- struct cmd_tbl *c;
+ int ret;
+ struct blk_desc *dev_desc;
+ struct disk_partition part_info;
+ char slot[2];
+ bool dec_tries = true;
- if (argc < 2)
+ if (argc < 4)
return CMD_RET_USAGE;
+ for (int i = 4; i < argc; i++) {
+ if (!strcmp(argv[i], "--no-dec"))
+ dec_tries = false;
+ else
+ return CMD_RET_USAGE;
+ }
+
+ /* Lookup the "misc" partition from argv[2] and argv[3] */
+ if (part_get_info_by_dev_and_name_or_num(argv[2], argv[3],
+ &dev_desc, &part_info,
+ false) < 0) {
+ return CMD_RET_FAILURE;
+ }
+
+ ret = ab_select_slot(dev_desc, &part_info, dec_tries);
+ if (ret < 0) {
+ printf("Android boot failed, error %d.\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ /* Android standard slot names are 'a', 'b', ... */
+ slot[0] = BOOT_SLOT_NAME(ret);
+ slot[1] = '\0';
+ env_set(argv[1], slot);
+ printf("ANDROID: Booting slot: %s\n", slot);
+
- argc--;
- argv++;
+ return CMD_RET_SUCCESS;
+}
+
+__maybe_unused static int do_bcb_ab_dump(struct cmd_tbl *cmdtp,
+ int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+ struct blk_desc *dev_desc;
+ struct disk_partition part_info;
- c = find_cmd_tbl(argv[0], cmd_bcb_sub, ARRAY_SIZE(cmd_bcb_sub));
- if (!c)
+ if (argc < 3)
return CMD_RET_USAGE;
- if (bcb_is_misused(argc, argv)) {
- /*
- * We try to improve the user experience by reporting the
- * root-cause of misusage, so don't return CMD_RET_USAGE,
- * since the latter prints out the full-blown help text
- */
+ if (part_get_info_by_dev_and_name_or_num(argv[1], argv[2],
+ &dev_desc, &part_info,
+ false) < 0) {
return CMD_RET_FAILURE;
}
- return c->cmd(cmdtp, flag, argc, argv);
+ ret = ab_dump_abc(dev_desc, &part_info);
+ if (ret < 0) {
+ printf("Cannot dump ABC data, error %d.\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
}
-U_BOOT_CMD(
- bcb, CONFIG_SYS_MAXARGS, 1, do_bcb,
- "Load/set/clear/test/dump/store Android BCB fields",
+U_BOOT_LONGHELP(bcb,
"load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>\n"
"load <dev> <part> - load BCB from mmc <dev>:<part>\n"
"bcb set <field> <val> - set BCB <field> to <val>\n"
@@ -460,6 +454,27 @@
"bcb dump <field> - dump BCB <field>\n"
"bcb store - store BCB back to <interface>\n"
"\n"
+#if IS_ENABLED(CONFIG_ANDROID_AB)
+ "bcb ab_select -\n"
+ " Select the slot used to boot from and register the boot attempt.\n"
+ " <slot_var_name> <interface> <dev[:part|#part_name]> [--no-dec]\n"
+ " - Load the slot metadata from the partition 'part' on\n"
+ " device type 'interface' instance 'dev' and store the active\n"
+ " slot in the 'slot_var_name' variable. This also updates the\n"
+ " Android slot metadata with a boot attempt, which can cause\n"
+ " successive calls to this function to return a different result\n"
+ " if the returned slot runs out of boot attempts.\n"
+ " - If 'part_name' is passed, preceded with a # instead of :, the\n"
+ " partition name whose label is 'part_name' will be looked up in\n"
+ " the partition table. This is commonly the \"misc\" partition.\n"
+ " - If '--no-dec' is set, the number of tries remaining will not\n"
+ " decremented for the selected boot slot\n"
+ "\n"
+ "bcb ab_dump -\n"
+ " Dump boot_control information from specific partition.\n"
+ " <interface> <dev[:part|#part_name]>\n"
+ "\n"
+#endif
"Legend:\n"
"<interface> - storage device interface (virtio, mmc, etc)\n"
"<dev> - storage device index containing the BCB partition\n"
@@ -472,3 +487,17 @@
" NOTE: any ':' character in <val> will be replaced by line feed\n"
" during 'bcb set' and used as separator by upper layers\n"
);
+
+U_BOOT_CMD_WITH_SUBCMDS(bcb,
+ "Load/set/clear/test/dump/store Android BCB fields", bcb_help_text,
+ U_BOOT_SUBCMD_MKENT(load, 4, 1, do_bcb_load),
+ U_BOOT_SUBCMD_MKENT(set, 3, 1, do_bcb_set),
+ U_BOOT_SUBCMD_MKENT(clear, 2, 1, do_bcb_clear),
+ U_BOOT_SUBCMD_MKENT(test, 4, 1, do_bcb_test),
+ U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_bcb_dump),
+ U_BOOT_SUBCMD_MKENT(store, 1, 1, do_bcb_store),
+#if IS_ENABLED(CONFIG_ANDROID_AB)
+ U_BOOT_SUBCMD_MKENT(ab_select, 5, 1, do_bcb_ab_select),
+ U_BOOT_SUBCMD_MKENT(ab_dump, 3, 1, do_bcb_ab_dump),
+#endif
+);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f6e534d..4c0e2ad 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -151,7 +151,7 @@
bdinfo_print_num_l("relocaddr", gd->relocaddr);
bdinfo_print_num_l("reloc off", gd->reloc_off);
printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8);
- if (IS_ENABLED(CONFIG_CMD_NET))
+ if (IS_ENABLED(CONFIG_CMD_NET) || IS_ENABLED(CONFIG_CMD_NET_LWIP))
print_eth();
bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
if (IS_ENABLED(CONFIG_VIDEO))
@@ -192,7 +192,8 @@
case 'a':
return bdinfo_print_all(bd);
case 'e':
- if (!IS_ENABLED(CONFIG_CMD_NET))
+ if (!IS_ENABLED(CONFIG_CMD_NET) &&
+ !IS_ENABLED(CONFIG_CMD_NET_LWIP))
return CMD_RET_USAGE;
print_eth();
return CMD_RET_SUCCESS;
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index 1588f27..f67948d 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -393,7 +393,11 @@
printf("Partition: %d\n", bflow->part);
printf("Subdir: %s\n", bflow->subdir ? bflow->subdir : "(none)");
printf("Filename: %s\n", bflow->fname);
- printf("Buffer: %lx\n", (ulong)map_to_sysmem(bflow->buf));
+ printf("Buffer: ");
+ if (bflow->buf)
+ printf("%lx\n", (ulong)map_to_sysmem(bflow->buf));
+ else
+ printf("(not loaded)\n");
printf("Size: %x (%d bytes)\n", bflow->size, bflow->size);
printf("OS: %s\n", bflow->os_name ? bflow->os_name : "(none)");
printf("Cmdline: ");
@@ -403,7 +407,8 @@
puts("(none)");
putc('\n');
if (bflow->x86_setup)
- printf("X86 setup: %p\n", bflow->x86_setup);
+ printf("X86 setup: %lx\n",
+ (ulong)map_to_sysmem(bflow->x86_setup));
printf("Logo: %s\n", bflow->logo ?
simple_xtoa((ulong)map_to_sysmem(bflow->logo)) : "(none)");
if (bflow->logo) {
diff --git a/cmd/cedit.c b/cmd/cedit.c
index fec67a8..f696356 100644
--- a/cmd/cedit.c
+++ b/cmd/cedit.c
@@ -67,6 +67,28 @@
return 0;
}
+#ifdef CONFIG_COREBOOT_SYSINFO
+static int do_cedit_cb_load(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct expo *exp;
+ int ret;
+
+ if (argc > 1)
+ return CMD_RET_USAGE;
+
+ ret = cb_expo_build(&exp);
+ if (ret) {
+ printf("Failed to build expo: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ cur_exp = exp;
+
+ return 0;
+}
+#endif /* CONFIG_COREBOOT_SYSINFO */
+
static int do_cedit_write_fdt(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -271,6 +293,9 @@
U_BOOT_LONGHELP(cedit,
"load <interface> <dev[:part]> <filename> - load config editor\n"
+#ifdef CONFIG_COREBOOT_SYSINFO
+ "cb_load - load coreboot CMOS editor\n"
+#endif
"cedit read_fdt <i/f> <dev[:part]> <filename> - read settings\n"
"cedit write_fdt <i/f> <dev[:part]> <filename> - write settings\n"
"cedit read_env [-v] - read settings from env vars\n"
@@ -281,6 +306,9 @@
U_BOOT_CMD_WITH_SUBCMDS(cedit, "Configuration editor", cedit_help_text,
U_BOOT_SUBCMD_MKENT(load, 5, 1, do_cedit_load),
+#ifdef CONFIG_COREBOOT_SYSINFO
+ U_BOOT_SUBCMD_MKENT(cb_load, 5, 1, do_cedit_cb_load),
+#endif
U_BOOT_SUBCMD_MKENT(read_fdt, 5, 1, do_cedit_read_fdt),
U_BOOT_SUBCMD_MKENT(write_fdt, 5, 1, do_cedit_write_fdt),
U_BOOT_SUBCMD_MKENT(read_env, 2, 1, do_cedit_read_env),
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index bea09e4..0291802 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -963,7 +963,7 @@
return handle_user_input(bo->description, EFICONFIG_DESCRIPTION_MAX, 22,
"\n ** Edit Description **\n"
"\n"
- " enter description: ");
+ " Enter description: ");
}
/**
diff --git a/cmd/elf.c b/cmd/elf.c
index 114f2ca..6b49c61 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -133,7 +133,7 @@
else
addr = hextoul(argv[1], NULL);
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_LWIP)
/*
* Check to see if we need to tftp the image ourselves
* before starting
diff --git a/cmd/fat.c b/cmd/fat.c
index 1655e80..5b7484d 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -14,7 +14,7 @@
#include <part.h>
#include <asm/cache.h>
-int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
return do_size(cmdtp, flag, argc, argv, FS_TYPE_FAT);
}
diff --git a/cmd/font.c b/cmd/font.c
index eb13fb1..36e4120 100644
--- a/cmd/font.c
+++ b/cmd/font.c
@@ -55,9 +55,6 @@
uint size;
int ret;
- if (argc != 2)
- return CMD_RET_USAGE;
-
if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev))
return CMD_RET_FAILURE;
ret = vidconsole_get_font_size(dev, &font_name, &size);
@@ -66,12 +63,16 @@
return CMD_RET_FAILURE;
}
- size = dectoul(argv[1], NULL);
+ if (argc < 2) {
+ printf("%d\n", size);
+ } else {
+ size = dectoul(argv[1], NULL);
- ret = vidconsole_select_font(dev, font_name, size);
- if (ret) {
- printf("Failed (error %d)\n", ret);
- return CMD_RET_FAILURE;
+ ret = vidconsole_select_font(dev, font_name, size);
+ if (ret) {
+ printf("Failed (error %d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
}
return 0;
diff --git a/cmd/irq.c b/cmd/irq.c
index 655aba5..da223b4 100644
--- a/cmd/irq.c
+++ b/cmd/irq.c
@@ -29,9 +29,6 @@
"[on, off]"
);
-/* Implemented in $(CPU)/interrupts.c */
-int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-
U_BOOT_CMD(
irqinfo, 1, 1, do_irqinfo,
"print information about IRQs",
diff --git a/cmd/mem.c b/cmd/mem.c
index 4d6fde2..9e71677 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1379,17 +1379,6 @@
#endif
-#ifdef CONFIG_CMD_MEMINFO
-static int do_mem_info(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- puts("DRAM: ");
- print_size(gd->ram_size, "\n");
-
- return 0;
-}
-#endif
-
U_BOOT_CMD(
base, 2, 1, do_mem_base,
"print or set address offset",
@@ -1433,14 +1422,6 @@
);
#endif /* CONFIG_CMD_MX_CYCLIC */
-#ifdef CONFIG_CMD_MEMINFO
-U_BOOT_CMD(
- meminfo, 3, 1, do_mem_info,
- "display memory information",
- ""
-);
-#endif
-
#ifdef CONFIG_CMD_RANDOM
U_BOOT_CMD(
random, 4, 0, do_random,
diff --git a/cmd/meminfo.c b/cmd/meminfo.c
new file mode 100644
index 0000000..5e83d61
--- /dev/null
+++ b/cmd/meminfo.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <bloblist.h>
+#include <bootstage.h>
+#include <command.h>
+#include <display_options.h>
+#include <lmb.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void print_region(const char *name, ulong base, ulong size, ulong *uptop)
+{
+ ulong end = base + size;
+
+ printf("%-12s %8lx %8lx %8lx", name, base, size, end);
+ if (*uptop)
+ printf(" %8lx", *uptop - end);
+ putc('\n');
+ *uptop = base;
+}
+
+static void show_lmb(const struct lmb *lmb, ulong *uptop)
+{
+ int i;
+
+ for (i = lmb->used_mem.count - 1; i >= 0; i--) {
+ const struct lmb_region *rgn = alist_get(&lmb->used_mem, i,
+ struct lmb_region);
+
+ /*
+ * Assume that the top lmb region is the U-Boot region, so just
+ * take account of the memory not already reported
+ */
+ if (lmb->used_mem.count - 1)
+ print_region("lmb", rgn->base, *uptop - rgn->base,
+ uptop);
+ else
+ print_region("lmb", rgn->base, rgn->size, uptop);
+ *uptop = rgn->base;
+ }
+}
+
+static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong upto, stk_bot;
+
+ puts("DRAM: ");
+ print_size(gd->ram_size, "\n");
+
+ if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP))
+ return 0;
+
+ printf("\n%-12s %8s %8s %8s %8s\n", "Region", "Base", "Size", "End",
+ "Gap");
+ printf("------------------------------------------------\n");
+ upto = 0;
+ if (IS_ENABLED(CONFIG_VIDEO))
+ print_region("video", gd_video_bottom(),
+ gd_video_size(), &upto);
+ if (IS_ENABLED(CONFIG_TRACE))
+ print_region("trace", map_to_sysmem(gd_trace_buff()),
+ gd_trace_size(), &upto);
+ print_region("code", gd->relocaddr, gd->mon_len, &upto);
+ print_region("malloc", map_to_sysmem((void *)mem_malloc_start),
+ mem_malloc_end - mem_malloc_start, &upto);
+ print_region("board_info", map_to_sysmem(gd->bd),
+ sizeof(struct bd_info), &upto);
+ print_region("global_data", map_to_sysmem((void *)gd),
+ sizeof(struct global_data), &upto);
+ print_region("devicetree", map_to_sysmem(gd->fdt_blob),
+ fdt_totalsize(gd->fdt_blob), &upto);
+ if (IS_ENABLED(CONFIG_BOOTSTAGE))
+ print_region("bootstage", map_to_sysmem(gd_bootstage()),
+ bootstage_get_size(false), &upto);
+ if (IS_ENABLED(CONFIG_BLOBLIST))
+ print_region("bloblist", map_to_sysmem(gd_bloblist()),
+ bloblist_get_total_size(), &upto);
+ stk_bot = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ print_region("stack", stk_bot, CONFIG_STACK_SIZE, &upto);
+ if (IS_ENABLED(CONFIG_LMB))
+ show_lmb(lmb_get(), &upto);
+ print_region("free", gd->ram_base, upto, &upto);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ meminfo, 1, 1, do_meminfo,
+ "display memory information",
+ ""
+);
diff --git a/cmd/net-common.c b/cmd/net-common.c
new file mode 100644
index 0000000..1c9fb83
--- /dev/null
+++ b/cmd/net-common.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <command.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <net.h>
+#include <linux/compat.h>
+#include <linux/ethtool.h>
+
+static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct udevice *current = eth_get_dev();
+ unsigned char env_enetaddr[ARP_HLEN];
+ const struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_ETH, dev, uc) {
+ eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr);
+ printf("eth%d : %s %pM %s\n", dev_seq(dev), dev->name, env_enetaddr,
+ current == dev ? "active" : "");
+ }
+ return CMD_RET_SUCCESS;
+}
+
+static int do_net_stats(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ int nstats, err, i, off;
+ struct udevice *dev;
+ u64 *values;
+ u8 *strings;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ err = uclass_get_device_by_name(UCLASS_ETH, argv[1], &dev);
+ if (err) {
+ printf("Could not find device %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ if (!eth_get_ops(dev)->get_sset_count ||
+ !eth_get_ops(dev)->get_strings ||
+ !eth_get_ops(dev)->get_stats) {
+ printf("Driver does not implement stats dump!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ nstats = eth_get_ops(dev)->get_sset_count(dev);
+ strings = kcalloc(nstats, ETH_GSTRING_LEN, GFP_KERNEL);
+ if (!strings)
+ return CMD_RET_FAILURE;
+
+ values = kcalloc(nstats, sizeof(u64), GFP_KERNEL);
+ if (!values)
+ goto err_free_strings;
+
+ eth_get_ops(dev)->get_strings(dev, strings);
+ eth_get_ops(dev)->get_stats(dev, values);
+
+ off = 0;
+ for (i = 0; i < nstats; i++) {
+ printf(" %s: %llu\n", &strings[off], values[i]);
+ off += ETH_GSTRING_LEN;
+ };
+
+ kfree(strings);
+ kfree(values);
+
+ return CMD_RET_SUCCESS;
+
+err_free_strings:
+ kfree(strings);
+
+ return CMD_RET_FAILURE;
+}
+
+static struct cmd_tbl cmd_net[] = {
+ U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""),
+ U_BOOT_CMD_MKENT(stats, 2, 0, do_net_stats, "", ""),
+};
+
+static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ cp = find_cmd_tbl(argv[1], cmd_net, ARRAY_SIZE(cmd_net));
+
+ /* Drop the net command */
+ argc--;
+ argv++;
+
+ if (!cp || argc > cp->maxargs)
+ return CMD_RET_USAGE;
+ if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
+ return CMD_RET_SUCCESS;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ net, 3, 1, do_net,
+ "NET sub-system",
+ "list - list available devices\n"
+ "stats <device> - dump statistics for specified device\n"
+);
diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c
new file mode 100644
index 0000000..42f8bd6
--- /dev/null
+++ b/cmd/net-lwip.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <net.h>
+
+#if defined(CONFIG_CMD_DHCP)
+U_BOOT_CMD(
+ dhcp, 3, 1, do_dhcp,
+ "boot image via network using DHCP/TFTP protocol",
+ "[loadAddress] [[hostIPaddr:]bootfilename]"
+);
+#endif
+
+#if defined(CONFIG_CMD_PING)
+U_BOOT_CMD(
+ ping, 2, 1, do_ping,
+ "send ICMP ECHO_REQUEST to network host",
+ "pingAddress"
+);
+#endif
+
+#if defined(CONFIG_CMD_TFTPBOOT)
+U_BOOT_CMD(
+ tftpboot, 3, 0, do_tftpb,
+ "boot image via network using TFTP protocol\n",
+ "[loadAddress] [[hostIPaddr:]bootfilename]"
+);
+#endif
+
+#if defined(CONFIG_CMD_DNS)
+U_BOOT_CMD(
+ dns, 3, 1, do_dns,
+ "lookup the IP of a hostname",
+ "hostname [envvar]"
+);
+#endif
+
+#if defined(CONFIG_CMD_WGET)
+U_BOOT_CMD(
+ wget, 3, 1, do_wget,
+ "boot image via network using HTTP protocol",
+ "[loadAddress] URL"
+);
+#endif
diff --git a/cmd/net.c b/cmd/net.c
index 53ce2bc..c90578e 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -674,118 +674,3 @@
);
#endif /* CONFIG_CMD_LINK_LOCAL */
-
-static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- const struct udevice *current = eth_get_dev();
- unsigned char env_enetaddr[ARP_HLEN];
- const struct udevice *dev;
- struct uclass *uc;
-
- uclass_id_foreach_dev(UCLASS_ETH, dev, uc) {
- eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr);
- printf("eth%d : %s %pM %s\n", dev_seq(dev), dev->name, env_enetaddr,
- current == dev ? "active" : "");
- }
- return CMD_RET_SUCCESS;
-}
-
-static int do_net_stats(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int nstats, err, i, off;
- struct udevice *dev;
- u64 *values;
- u8 *strings;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- err = uclass_get_device_by_name(UCLASS_ETH, argv[1], &dev);
- if (err) {
- printf("Could not find device %s\n", argv[1]);
- return CMD_RET_FAILURE;
- }
-
- if (!eth_get_ops(dev)->get_sset_count ||
- !eth_get_ops(dev)->get_strings ||
- !eth_get_ops(dev)->get_stats) {
- printf("Driver does not implement stats dump!\n");
- return CMD_RET_FAILURE;
- }
-
- nstats = eth_get_ops(dev)->get_sset_count(dev);
- strings = kcalloc(nstats, ETH_GSTRING_LEN, GFP_KERNEL);
- if (!strings)
- return CMD_RET_FAILURE;
-
- values = kcalloc(nstats, sizeof(u64), GFP_KERNEL);
- if (!values)
- goto err_free_strings;
-
- eth_get_ops(dev)->get_strings(dev, strings);
- eth_get_ops(dev)->get_stats(dev, values);
-
- off = 0;
- for (i = 0; i < nstats; i++) {
- printf(" %s: %llu\n", &strings[off], values[i]);
- off += ETH_GSTRING_LEN;
- };
-
- return CMD_RET_SUCCESS;
-
-err_free_strings:
- kfree(strings);
-
- return CMD_RET_FAILURE;
-}
-
-static struct cmd_tbl cmd_net[] = {
- U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""),
- U_BOOT_CMD_MKENT(stats, 2, 0, do_net_stats, "", ""),
-};
-
-static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmd_tbl *cp;
-
- cp = find_cmd_tbl(argv[1], cmd_net, ARRAY_SIZE(cmd_net));
-
- /* Drop the net command */
- argc--;
- argv++;
-
- if (!cp || argc > cp->maxargs)
- return CMD_RET_USAGE;
- if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
- return CMD_RET_SUCCESS;
-
- return cp->cmd(cmdtp, flag, argc, argv);
-}
-
-U_BOOT_CMD(
- net, 3, 1, do_net,
- "NET sub-system",
- "list - list available devices\n"
- "stats <device> - dump statistics for specified device\n"
-);
-
-#if defined(CONFIG_CMD_NCSI)
-static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
-{
- if (!phy_interface_is_ncsi() || !ncsi_active()) {
- printf("Device not configured for NC-SI\n");
- return CMD_RET_FAILURE;
- }
-
- if (net_loop(NCSI) < 0)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
- ncsi, 1, 1, do_ncsi,
- "Configure attached NIC via NC-SI",
- ""
-);
-#endif /* CONFIG_CMD_NCSI */
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 74ff5c6..392f90f 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -198,7 +198,7 @@
* Prompt for environment variable
*/
#if defined(CONFIG_CMD_ASKENV)
-int do_env_ask(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int do_env_ask(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char message[CONFIG_SYS_CBSIZE];
int i, len, pos, size;
@@ -312,8 +312,8 @@
/*
* Print the callbacks available and what they are bound to
*/
-int do_env_callback(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int do_env_callback(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
{
struct env_clbk_tbl *clbkp;
int i;
@@ -381,7 +381,7 @@
/*
* Print the flags available and what variables have flags
*/
-int do_env_flags(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int do_env_flags(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Print the available variable types */
printf("Available variable type flags (position %d):\n",
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index a231604..5ecf567 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -54,8 +54,10 @@
{ SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" },
{ SBI_EXT_NACL, "Nested Acceleration Extension" },
{ SBI_EXT_STA, "Steal-time Accounting Extension" },
- { SBI_EXT_DBTR, "Debug Trigger Extension" },
{ SBI_EXT_SSE, "Supervisor Software Events" },
+ { SBI_EXT_FWFT, "Firmware Features Extension" },
+ { SBI_EXT_DBTR, "Debug Triggers Extension" },
+ { SBI_EXT_MPXY, "Message Proxy Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/sb.c b/cmd/sb.c
index db485fd..9245052 100644
--- a/cmd/sb.c
+++ b/cmd/sb.c
@@ -7,6 +7,7 @@
#include <command.h>
#include <dm.h>
#include <spl.h>
+#include <asm/cpu.h>
#include <asm/global_data.h>
#include <asm/state.h>
@@ -29,6 +30,14 @@
#endif
}
+static int do_sb_map(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ sandbox_map_list();
+
+ return 0;
+}
+
static int do_sb_state(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -40,29 +49,12 @@
return 0;
}
-static struct cmd_tbl cmd_sb_sub[] = {
- U_BOOT_CMD_MKENT(handoff, 1, 0, do_sb_handoff, "", ""),
- U_BOOT_CMD_MKENT(state, 1, 0, do_sb_state, "", ""),
-};
-
-static int do_sb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmd_tbl *c;
-
- /* Skip past 'sb' */
- argc--;
- argv++;
-
- c = find_cmd_tbl(argv[0], cmd_sb_sub, ARRAY_SIZE(cmd_sb_sub));
- if (c)
- return c->cmd(cmdtp, flag, argc, argv);
- else
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- sb, 8, 1, do_sb,
- "Sandbox status commands",
+U_BOOT_LONGHELP(sb,
"handoff - Show handoff data received from SPL\n"
- "sb state - Show sandbox state"
-);
+ "sb map - Show mapped memory\n"
+ "sb state - Show sandbox state");
+
+U_BOOT_CMD_WITH_SUBCMDS(sb, "Sandbox status commands", sb_help_text,
+ U_BOOT_SUBCMD_MKENT(handoff, 1, 1, do_sb_handoff),
+ U_BOOT_SUBCMD_MKENT(map, 1, 1, do_sb_map),
+ U_BOOT_SUBCMD_MKENT(state, 1, 1, do_sb_state));
diff --git a/cmd/tcpm.c b/cmd/tcpm.c
new file mode 100644
index 0000000..39578f6
--- /dev/null
+++ b/cmd/tcpm.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Collabora
+ */
+
+#include <command.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <usb/tcpm.h>
+
+#define LIMIT_DEV 32
+#define LIMIT_PARENT 20
+
+static struct udevice *currdev;
+
+static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ int devnum, ret;
+
+ switch (argc) {
+ case 2:
+ devnum = (int)dectoul(argv[1], NULL);
+ ret = tcpm_get(devnum, &currdev);
+ if (ret) {
+ log_err("Can't get TCPM %d: %d (%s)!\n", devnum, ret, errno_str(ret));
+ return CMD_RET_FAILURE;
+ }
+ case 1:
+ if (!currdev) {
+ log_err("TCPM device is not set!\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ printf("dev: %d @ %s\n", dev_seq(currdev), currdev->name);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_list(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ int ret, err = 0;
+
+ printf("| ID | %-*.*s| %-*.*s| %s @ %s\n",
+ LIMIT_DEV, LIMIT_DEV, "Name",
+ LIMIT_PARENT, LIMIT_PARENT, "Parent name",
+ "Parent uclass", "seq");
+
+ for (ret = uclass_first_device_check(UCLASS_TCPM, &dev); dev;
+ ret = uclass_next_device_check(&dev)) {
+ if (ret)
+ err = ret;
+
+ printf("| %2d | %-*.*s| %-*.*s| %s @ %d | status: %i\n",
+ dev_seq(dev),
+ LIMIT_DEV, LIMIT_DEV, dev->name,
+ LIMIT_PARENT, LIMIT_PARENT, dev->parent->name,
+ dev_get_uclass_name(dev->parent), dev_seq(dev->parent),
+ ret);
+ }
+
+ if (err)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+int do_print_info(struct udevice *dev)
+{
+ enum typec_orientation orientation = tcpm_get_orientation(dev);
+ const char *state = tcpm_get_state(dev);
+ int pd_rev = tcpm_get_pd_rev(dev);
+ int mv = tcpm_get_voltage(dev);
+ int ma = tcpm_get_current(dev);
+ enum typec_role pwr_role = tcpm_get_pwr_role(dev);
+ enum typec_data_role data_role = tcpm_get_data_role(dev);
+ bool connected = tcpm_is_connected(dev);
+
+ if (!connected) {
+ printf("TCPM State: %s\n", state);
+ return 0;
+ }
+
+ printf("Orientation: %s\n", typec_orientation_name[orientation]);
+ printf("PD Revision: %s\n", typec_pd_rev_name[pd_rev]);
+ printf("Power Role: %s\n", typec_role_name[pwr_role]);
+ printf("Data Role: %s\n", typec_data_role_name[data_role]);
+ printf("Voltage: %2d.%03d V\n", mv / 1000, mv % 1000);
+ printf("Current: %2d.%03d A\n", ma / 1000, ma % 1000);
+
+ return 0;
+}
+
+static int do_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (!currdev) {
+ printf("First, set the TCPM device!\n");
+ return CMD_RET_USAGE;
+ }
+
+ return do_print_info(currdev);
+}
+
+static struct cmd_tbl subcmd[] = {
+ U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""),
+ U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""),
+ U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
+};
+
+static int do_tcpm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cmd_tbl *cmd;
+
+ argc--;
+ argv++;
+
+ cmd = find_cmd_tbl(argv[0], subcmd, ARRAY_SIZE(subcmd));
+ if (!cmd || argc > cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ return cmd->cmd(cmdtp, flag, argc, argv);
+}
+
+ /**************************************************/
+
+U_BOOT_CMD(tcpm, CONFIG_SYS_MAXARGS, 1, do_tcpm,
+ "TCPM sub-system",
+ "list - list TCPM devices\n"
+ "tcpm dev [ID] - show or [set] operating TCPM device\n"
+ "tcpm info - dump information\n"
+);
diff --git a/cmd/upl.c b/cmd/upl.c
index c974588..4996f36 100644
--- a/cmd/upl.c
+++ b/cmd/upl.c
@@ -72,7 +72,7 @@
return CMD_RET_FAILURE;
}
addr = map_to_sysmem(abuf_data(&buf));
- printf("UPL handoff written to %lx size %lx\n", addr, abuf_size(&buf));
+ printf("UPL handoff written to %lx size %zx\n", addr, abuf_size(&buf));
if (env_set_hex("upladdr", addr) ||
env_set_hex("uplsize", abuf_size(&buf))) {
printf("Cannot set env var\n");
diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile
index b1f39d3..5f3f5be 100644
--- a/cmd/x86/Makefile
+++ b/cmd/x86/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_CMD_CBSYSINFO) += cbsysinfo.o
-obj-y += mtrr.o
+obj-y += cpuid.o msr.o mtrr.o
+obj-$(CONFIG_CMD_CBCMOS) += cbcmos.o
obj-$(CONFIG_CMD_EXCEPTION) += exception.o
obj-$(CONFIG_USE_HOB) += hob.o
obj-$(CONFIG_HAVE_FSP) += fsp.o
diff --git a/cmd/x86/cbcmos.c b/cmd/x86/cbcmos.c
new file mode 100644
index 0000000..fe5582f
--- /dev/null
+++ b/cmd/x86/cbcmos.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for booting from coreboot
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_RTC
+
+#include <command.h>
+#include <dm.h>
+#include <rtc.h>
+#include <asm/cb_sysinfo.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct sysinfo_t *get_table(void)
+{
+ if (!gd->arch.coreboot_table) {
+ printf("No coreboot sysinfo table found\n");
+ return NULL;
+ }
+
+ return &lib_sysinfo;
+}
+
+static int calc_sum(struct udevice *dev, uint start_bit, uint bit_count)
+{
+ uint start_byte = start_bit / 8;
+ uint byte_count = bit_count / 8;
+ int ret, i;
+ uint sum;
+
+ log_debug("Calc sum from %x: %x bytes\n", start_byte, byte_count);
+ sum = 0;
+ for (i = 0; i < bit_count / 8; i++) {
+ ret = rtc_read8(dev, start_bit / 8 + i);
+ if (ret < 0)
+ return ret;
+ sum += ret;
+ }
+
+ return (sum & 0xff) << 8 | (sum & 0xff00) >> 8;
+}
+
+/**
+ * prep_cbcmos() - Prepare for a CMOS-RAM command
+ *
+ * @tab: coreboot table
+ * @devnum: RTC device name to use, or NULL for the first one
+ * @dep: Returns RTC device on success
+ * Return: calculated checksum for CMOS RAM or -ve on error
+ */
+static int prep_cbcmos(const struct sysinfo_t *tab, const char *devname,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (!tab)
+ return CMD_RET_FAILURE;
+ if (devname)
+ ret = uclass_get_device_by_name(UCLASS_RTC, devname, &dev);
+ else
+ ret = uclass_first_device_err(UCLASS_RTC, &dev);
+ if (ret) {
+ printf("Failed to get RTC device: %dE\n", ret);
+ return ret;
+ }
+
+ ret = calc_sum(dev, tab->cmos_range_start,
+ tab->cmos_range_end + 1 - tab->cmos_range_start);
+ if (ret < 0) {
+ printf("Failed to read RTC device: %dE\n", ret);
+ return ret;
+ }
+ *devp = dev;
+
+ return ret;
+}
+
+static int do_cbcmos_check(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct sysinfo_t *tab = get_table();
+ struct udevice *dev;
+ u16 cur, sum;
+ int ret;
+
+ ret = prep_cbcmos(tab, argv[1], &dev);
+ if (ret < 0)
+ return CMD_RET_FAILURE;
+ sum = ret;
+
+ ret = rtc_read16(dev, tab->cmos_checksum_location / 8, &cur);
+ if (ret < 0) {
+ printf("Failed to read RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ if (sum != cur) {
+ printf("Checksum %04x error: calculated %04x\n", cur, sum);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_cbcmos_update(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct sysinfo_t *tab = get_table();
+ struct udevice *dev;
+ u16 sum;
+ int ret;
+
+ ret = prep_cbcmos(tab, argv[1], &dev);
+ if (ret < 0)
+ return CMD_RET_FAILURE;
+ sum = ret;
+
+ ret = rtc_write16(dev, tab->cmos_checksum_location / 8, sum);
+ if (ret < 0) {
+ printf("Failed to read RTC device: %dE\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ printf("Checksum %04x written\n", sum);
+
+ return 0;
+}
+
+U_BOOT_LONGHELP(cbcmos,
+ "check - check CMOS RAM\n"
+ "cbcmos update - Update CMOS-RAM checksum";
+);
+
+U_BOOT_CMD_WITH_SUBCMDS(cbcmos, "coreboot CMOS RAM", cbcmos_help_text,
+ U_BOOT_SUBCMD_MKENT(check, 2, 1, do_cbcmos_check),
+ U_BOOT_SUBCMD_MKENT(update, 2, 1, do_cbcmos_update));
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index 7ca2e13..ea4d896 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -184,6 +184,77 @@
return "<unknown>";
}
+static void show_option_vals(const struct cb_cmos_option_table *tab,
+ uint id)
+{
+ const void *ptr, *end;
+ bool found = false;
+
+ end = (void *)tab + tab->size;
+ for (ptr = (void *)tab + tab->header_length; ptr < end;) {
+ const struct cb_record *rec = ptr;
+
+ switch (rec->tag) {
+ case CB_TAG_OPTION_ENUM: {
+ const struct cb_cmos_enums *enums = ptr;
+
+ if (enums->config_id == id) {
+ if (!found)
+ printf(" ");
+ printf(" %d:%s", enums->value, enums->text);
+ found = true;
+ }
+ break;
+ }
+ break;
+ case CB_TAG_OPTION_DEFAULTS:
+ case CB_TAG_OPTION_CHECKSUM:
+ case CB_TAG_OPTION:
+ break;
+ default:
+ printf("tag %x\n", rec->tag);
+ break;
+ }
+ ptr += rec->size;
+ }
+}
+
+static void show_option_table(const struct cb_cmos_option_table *tab)
+{
+ const void *ptr, *end;
+
+ print_ptr("option_table", tab);
+ if (!tab->size)
+ return;
+
+ printf(" Bit Len Cfg ID Name\n");
+ end = (void *)tab + tab->size;
+ for (ptr = (void *)tab + tab->header_length; ptr < end;) {
+ const struct cb_record *rec = ptr;
+
+ switch (rec->tag) {
+ case CB_TAG_OPTION: {
+ const struct cb_cmos_entries *entry = ptr;
+
+ printf("%4x %4x %3c %3x %-20s", entry->bit,
+ entry->length, entry->config, entry->config_id,
+ entry->name);
+ show_option_vals(tab, entry->config_id);
+ printf("\n");
+ break;
+ }
+ case CB_TAG_OPTION_ENUM:
+ case CB_TAG_OPTION_DEFAULTS:
+ case CB_TAG_OPTION_CHECKSUM:
+ break;
+ default:
+ printf("tag %x\n", rec->tag);
+ break;
+ }
+ ptr += rec->size;
+ }
+}
+
static void show_table(struct sysinfo_t *info, bool verbose)
{
struct cb_serial *ser = info->serial;
@@ -218,7 +289,7 @@
printf("%12d: %02x:%-8s %016llx %016llx\n", i, mr->type,
get_mem_name(mr->type), mr->base, mr->size);
}
- print_ptr("option_table", info->option_table);
+ show_option_table(info->option_table);
print_hex("CMOS start", info->cmos_range_start);
if (info->cmos_range_start) {
diff --git a/cmd/x86/cpuid.c b/cmd/x86/cpuid.c
new file mode 100644
index 0000000..222754b
--- /dev/null
+++ b/cmd/x86/cpuid.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'cpuid' command provides access to the CPU's cpuid information
+ *
+ * Copyright 2024 Google, LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <command.h>
+#include <vsprintf.h>
+#include <asm/cpu.h>
+
+static int do_cpuid(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cpuid_result res;
+ ulong op;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ op = hextoul(argv[1], NULL);
+ res = cpuid(op);
+ printf("eax %08x\n", res.eax);
+ printf("ebx %08x\n", res.ebx);
+ printf("ecx %08x\n", res.ecx);
+ printf("edx %08x\n", res.edx);
+
+ return 0;
+}
+
+U_BOOT_LONGHELP(cpuid, "Show CPU Identification information");
+
+U_BOOT_CMD(
+ cpuid, 2, 1, do_cpuid,
+ "cpuid <op>", cpuid_help_text
+);
diff --git a/cmd/x86/msr.c b/cmd/x86/msr.c
new file mode 100644
index 0000000..3cb70d1
--- /dev/null
+++ b/cmd/x86/msr.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'cpuid' command provides access to the CPU's cpuid information
+ *
+ * Copyright 2024 Google, LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <command.h>
+#include <vsprintf.h>
+#include <asm/msr.h>
+
+static int do_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct msr_t msr;
+ ulong op;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ op = hextoul(argv[1], NULL);
+ msr = msr_read(op);
+ printf("%08x %08x\n", msr.hi, msr.lo);
+
+ return 0;
+}
+
+static int do_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct msr_t msr;
+ ulong op;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ op = hextoul(argv[1], NULL);
+ msr.hi = hextoul(argv[2], NULL);
+ msr.lo = hextoul(argv[3], NULL);
+ msr_write(op, msr);
+
+ return 0;
+}
+
+U_BOOT_LONGHELP(msr,
+ "read <op> - read a machine-status register (MSR) as <hi 32-bits> <lo 32-bits>\n"
+ "write <op< <hi> <lo> - write an MSR");
+
+U_BOOT_CMD_WITH_SUBCMDS(msr, "Machine Status Registers", msr_help_text,
+ U_BOOT_CMD_MKENT(read, CONFIG_SYS_MAXARGS, 1, do_read, "", ""),
+ U_BOOT_CMD_MKENT(write, CONFIG_SYS_MAXARGS, 1, do_write, "", ""));
diff --git a/common/Kconfig b/common/Kconfig
index 957de0c..e8d89bf 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -424,7 +424,7 @@
config LOG_SYSLOG
bool "Log output to syslog server"
- depends on NET
+ depends on NET || NET_LWIP
help
Enables a log driver which broadcasts log records via UDP port 514
to syslog servers.
@@ -850,6 +850,7 @@
depends on LIBAVB
depends on MMC
depends on PARTITION_UUIDS
+ depends on FASTBOOT
help
This option enables compilation of bootloader-dependent operations,
used by Android Verified Boot 2.0 library (libavb). Includes:
@@ -927,6 +928,9 @@
new seed for use on subsequent boots, and whether or not the
kernel should account any entropy from the given seed.
+ Default seed size (64 bytes) can be overridden by a decimal
+ environment variable rng_seed_size.
+
endmenu
menu "Update support"
@@ -1077,6 +1081,7 @@
hex "Size of bloblist after relocation"
default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
default 0x0 if BLOBLIST_PASSAGE
+ default 0x20000 if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE)
help
Sets the size of the bloblist in bytes after relocation. Since U-Boot
has a lot more memory available then, it is possible to use a larger
diff --git a/common/bloblist.c b/common/bloblist.c
index 6640ad1..ec6ff7a 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -499,7 +499,7 @@
{
bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
int ret = -ENOENT;
- ulong addr, size;
+ ulong addr = 0, size;
/*
* If U-Boot is not in the first phase, an existing bloblist must be
* at a fixed address.
diff --git a/common/board_f.c b/common/board_f.c
index f1bd70f..98dc259 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -501,9 +501,9 @@
static int reserve_noncached(void)
{
/*
- * The value of gd->start_addr_sp must match the value of malloc_start
- * calculated in board_r.c:initr_malloc(), which is passed to
- * dlmalloc.c:mem_malloc_init() and then used by
+ * The value of gd->start_addr_sp must match the value of
+ * mem_malloc_start calculated in board_r.c:initr_malloc(), which is
+ * passed to dlmalloc.c:mem_malloc_init() and then used by
* cache.c:noncached_init()
*
* These calculations must match the code in cache.c:noncached_init()
@@ -582,7 +582,7 @@
static int reserve_bootstage(void)
{
#ifdef CONFIG_BOOTSTAGE
- int size = bootstage_get_size();
+ int size = bootstage_get_size(true);
gd->start_addr_sp = reserve_stack_aligned(size);
gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size);
diff --git a/common/board_r.c b/common/board_r.c
index 1acad06..62228a7 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -32,6 +32,7 @@
#include <command.h>
#include <console.h>
#include <dm.h>
+#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
#include <fdtdec.h>
@@ -63,10 +64,8 @@
#include <dm/ofnode.h>
#include <linux/compiler.h>
#include <linux/err.h>
-#include <efi_loader.h>
#include <wdt.h>
#include <asm-generic/gpio.h>
-#include <efi_loader.h>
#include <relocate.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -204,8 +203,7 @@
*/
start = gd->relocaddr - TOTAL_MALLOC_LEN;
gd_set_malloc_start(start);
- mem_malloc_init((ulong)map_sysmem(start, TOTAL_MALLOC_LEN),
- TOTAL_MALLOC_LEN);
+ mem_malloc_init(start, TOTAL_MALLOC_LEN);
return 0;
}
@@ -484,7 +482,7 @@
return 0;
}
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET)
static int initr_net(void)
{
puts("Net: ");
@@ -749,7 +747,7 @@
#ifdef CONFIG_PCI_ENDPOINT
pci_ep_init,
#endif
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET)
INIT_FUNC_WATCHDOG_RESET
initr_net,
#endif
diff --git a/common/bootstage.c b/common/bootstage.c
index dd6aed7..4532100 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -249,6 +249,8 @@
printf("%11s", "");
print_grouped_ull(rec->time_us, BOOTSTAGE_DIGITS);
} else {
+ if (prev > rec->time_us)
+ prev = 0;
print_grouped_ull(rec->time_us, BOOTSTAGE_DIGITS);
print_grouped_ull(rec->time_us - prev, BOOTSTAGE_DIGITS);
}
@@ -257,13 +259,6 @@
return rec->time_us;
}
-static int h_compare_record(const void *r1, const void *r2)
-{
- const struct bootstage_record *rec1 = r1, *rec2 = r2;
-
- return rec1->time_us > rec2->time_us ? 1 : -1;
-}
-
#ifdef CONFIG_OF_LIBFDT
/**
* Add all bootstage timings to a device tree.
@@ -342,9 +337,6 @@
prev = print_time_record(rec, 0);
- /* Sort records by increasing time */
- qsort(data->record, data->rec_count, sizeof(*rec), h_compare_record);
-
for (i = 1, rec++; i < data->rec_count; i++, rec++) {
if (rec->id && !rec->start_us)
prev = print_time_record(rec, prev);
@@ -520,17 +512,19 @@
}
#endif
-int bootstage_get_size(void)
+int bootstage_get_size(bool add_strings)
{
- struct bootstage_data *data = gd->bootstage;
- struct bootstage_record *rec;
int size;
- int i;
size = sizeof(struct bootstage_data);
- for (rec = data->record, i = 0; i < data->rec_count;
- i++, rec++)
- size += strlen(rec->name) + 1;
+ if (add_strings) {
+ struct bootstage_data *data = gd->bootstage;
+ struct bootstage_record *rec;
+ int i;
+
+ for (rec = data->record, i = 0; i < data->rec_count; i++, rec++)
+ size += strlen(rec->name) + 1;
+ }
return size;
}
diff --git a/common/cyclic.c b/common/cyclic.c
index ec38fad..196797f 100644
--- a/common/cyclic.c
+++ b/common/cyclic.c
@@ -15,6 +15,7 @@
#include <linux/errno.h>
#include <linux/list.h>
#include <asm/global_data.h>
+#include <u-boot/schedule.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +45,7 @@
hlist_del(&cyclic->list);
}
-void cyclic_run(void)
+static void cyclic_run(void)
{
struct cyclic_info *cyclic;
struct hlist_node *tmp;
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 1ac7ce3..cc4d3a0 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -16,6 +16,8 @@
#include <asm/global_data.h>
#include <malloc.h>
+#include <mapmem.h>
+#include <string.h>
#include <asm/io.h>
#include <valgrind/memcheck.h>
@@ -598,9 +600,9 @@
void mem_malloc_init(ulong start, ulong size)
{
- mem_malloc_start = start;
- mem_malloc_end = start + size;
- mem_malloc_brk = start;
+ mem_malloc_start = (ulong)map_sysmem(start, size);
+ mem_malloc_end = mem_malloc_start + size;
+ mem_malloc_brk = mem_malloc_start;
#ifdef CONFIG_SYS_MALLOC_DEFAULT_TO_INIT
malloc_init();
diff --git a/common/log.c b/common/log.c
index b83a661..c9fe352 100644
--- a/common/log.c
+++ b/common/log.c
@@ -32,6 +32,7 @@
"fs",
"expo",
"console",
+ "test",
};
_Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE,
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2baf2ba..045fcac 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -271,6 +271,8 @@
default 0x40200000 if OMAP34XX
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
+ default 0x00908000 if ARCH_MX6
+ default 0x00912000 if ARCH_MX7
default 0x40301350 if OMAP54XX
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
@@ -1083,6 +1085,7 @@
config SPL_NET
bool "Support networking"
+ depends on !NET_LWIP
help
Enable support for network devices (such as Ethernet) in SPL.
This permits SPL to load U-Boot over a network link rather than
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 94657d0..1ceb63d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -678,9 +678,7 @@
spl_set_bd();
if (IS_ENABLED(CONFIG_SPL_SYS_MALLOC)) {
- mem_malloc_init((ulong)map_sysmem(SPL_SYS_MALLOC_START,
- SPL_SYS_MALLOC_SIZE),
- SPL_SYS_MALLOC_SIZE);
+ mem_malloc_init(SPL_SYS_MALLOC_START, SPL_SYS_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
}
if (!(gd->flags & GD_FLG_SPL_INIT)) {
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index bbfee23..36107a3 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -423,7 +423,7 @@
*/
unsigned long poll_delay = CONFIG_SYS_HZ / 50;
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_LWIP)
/*
* If net_busy_flag is 1, NET transfer is running,
* then we check key-pressed every second (first check may be
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index 009384e..c37c49c 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -5,4 +5,4 @@
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index eac85b9..ed1446d 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -22,7 +22,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index c480762..488115d 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7794-alt"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Alt"
CONFIG_R8A7794=y
CONFIG_TARGET_ALT=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,65 +29,16 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_SH_MMCIF=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index 54da31f..09753fd 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -42,7 +42,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index efc154e..b793f00 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -48,7 +48,6 @@
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 0f8533e..5cacd7f 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -44,7 +44,6 @@
CONFIG_CMD_ABOOTIMG=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
-CONFIG_CMD_AB_SELECT=y
CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 81a9383..2d8068e 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -46,7 +46,6 @@
CONFIG_CMD_ABOOTIMG=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_BCB=y
-CONFIG_CMD_AB_SELECT=y
CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_PMIC is not set
CONFIG_CMD_AVB=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 24be88b..c396171 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 2fe6c49..2e758b4 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -66,8 +66,9 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index 0cdbd30..5fed277 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -70,7 +70,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index 0038747..9daee2a 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -67,7 +67,7 @@
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 0b7ee94..003fa4f 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -63,6 +63,7 @@
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 3019525..6ff0782 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -75,6 +75,7 @@
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index e9b6882..f4800ef 100644
--- a/configs/am68_sk_r5_defconfig
+++ b/configs/am68_sk_r5_defconfig
@@ -5,6 +5,10 @@
CONFIG_SOC_K3_J721S2=y
CONFIG_TARGET_J721S2_R5_EVM=y
+CONFIG_K3_AVS0=n
+CONFIG_DM_REGULATOR_TPS65941=n
+CONFIG_PMIC_TPS65941=n
+
CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board"
CONFIG_OF_LIST="k3-am68-sk-r5-base-board"
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index f1f5201..94c5379 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -33,7 +33,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="AMCORE"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig
index d4760e4..ea22541 100644
--- a/configs/amd_versal2_mini_defconfig
+++ b/configs/amd_versal2_mini_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -35,6 +36,7 @@
CONFIG_SYS_PROMPT="versal2> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
@@ -62,7 +64,7 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -75,3 +77,4 @@
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
# CONFIG_GZIP is not set
+# CONFIG_LMB is not set
diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig
index d2de379..6d4b261 100644
--- a/configs/amd_versal2_mini_emmc_defconfig
+++ b/configs/amd_versal2_mini_emmc_defconfig
@@ -54,7 +54,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig
index 22a8bfa..71bd667 100644
--- a/configs/amd_versal2_mini_ospi_defconfig
+++ b/configs/amd_versal2_mini_ospi_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -33,6 +34,7 @@
CONFIG_SYS_PROMPT="versal2> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
@@ -56,7 +58,7 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -82,3 +84,4 @@
CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
# CONFIG_GZIP is not set
+# CONFIG_LMB is not set
diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig
index de404b0..ee87d45 100644
--- a/configs/amd_versal2_mini_qspi_defconfig
+++ b/configs/amd_versal2_mini_qspi_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEBUG_UART=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -33,6 +34,7 @@
CONFIG_SYS_PROMPT="versal2> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
@@ -56,13 +58,12 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
# CONFIG_MMC is not set
-CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_STMICRO=y
@@ -77,3 +78,4 @@
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
# CONFIG_GZIP is not set
+# CONFIG_LMB is not set
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index 83337d6..d3216ec 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -3,7 +3,7 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-anbernic-rg353p"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_SERIAL=y
@@ -20,8 +20,10 @@
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rg353p.dtb"
+CONFIG_DISABLE_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
+CONFIG_BOARD_TYPES=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_RNG_SEED=y
@@ -39,16 +41,15 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_LIST="rockchip/rk3566-anbernic-rg353p rockchip/rk3566-anbernic-rg353v rockchip/rk3566-anbernic-rg503 rockchip/rk3566-anbernic-rg-arc-d rockchip/rk3566-anbernic-rg353ps rockchip/rk3566-anbernic-rg353vs rockchip/rk3566-anbernic-rg-arc-s rockchip/rk3566-powkiddy-rgb30 rockchip/rk3566-powkiddy-rk2023 rockchip/rk3566-powkiddy-rgb10max3"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+CONFIG_SPL_ADC=y
CONFIG_SPL_CLK=y
-CONFIG_ARM_SMCCC_FEATURES=y
-CONFIG_SCMI_FIRMWARE=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -71,6 +72,7 @@
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
# CONFIG_RNG_SMCCC_TRNG is not set
CONFIG_BAUDRATE=1500000
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 9d503bd..9083bf2 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -46,7 +46,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=25000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig
index d830a85..0864bf4 100644
--- a/configs/ap152_defconfig
+++ b/configs/ap152_defconfig
@@ -46,7 +46,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=25000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 92d304a..b44861d 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -16,7 +15,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-apalis-eval"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig
index 6a5affc..2d685da 100644
--- a/configs/apple_m1_defconfig
+++ b/configs/apple_m1_defconfig
@@ -11,7 +11,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_CMD_SELECT_FONT=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_APPLE_SPI_KEYB=y
# CONFIG_MMC is not set
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index 95d6f3f..b6e259b 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x13000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index 7de3783..0ea13d4 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x13000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index d1942c2..8dd369d 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -27,7 +27,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_JFFS2=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 141e83f..9ebe2de 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -41,7 +41,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index d497d59..0fef493 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -39,7 +39,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 1bcdab8..c40e998 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -40,7 +40,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index aeb1f90..ed026e5 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -36,7 +36,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index 0301205..0729445 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -38,7 +38,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig
index 6c119eb..053c459 100644
--- a/configs/bcm968380gerg_ram_defconfig
+++ b/configs/bcm968380gerg_ram_defconfig
@@ -41,7 +41,7 @@
CONFIG_CMD_NAND=y
# CONFIG_CMD_SLEEP is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig
index 989017b..c53c6ff 100644
--- a/configs/bcmns_defconfig
+++ b/configs/bcmns_defconfig
@@ -29,7 +29,7 @@
CONFIG_OF_EMBED=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="NS"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index aa30585..09fef29 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -1,86 +1,21 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7792-blanche"
CONFIG_ARCH_RENESAS_BOARD_STRING="Blanche"
CONFIG_R8A7792=y
CONFIG_TARGET_BLANCHE=y
-CONFIG_SYS_MONITOR_LEN=262144
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_ENV_ADDR=0x40000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
# CONFIG_CMD_SF is not set
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_SH_MMCIF=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SMC911X=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 299e263..0bbb682 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -2,7 +2,6 @@
# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 1be5756..075e3f1 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -74,7 +74,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index f251d69..bba25e0 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index cabd222..eaa8a33 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -46,7 +46,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index 8d4b54c..b82d604 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index 2f58e94..cef80d6 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index cfe7c2a..0e91677 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,7 +12,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_CM_FX6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index fc9404a..facf0b2 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -16,7 +15,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-colibri-eval-v3"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index da42ad0..706c0cd 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -17,6 +17,7 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi"
+CONFIG_CEDIT=y
CONFIG_SYS_PBSIZE=532
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -46,6 +47,7 @@
CONFIG_USE_ROOTPATH=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_OFNODE_MULTI_TREE=y
# CONFIG_ACPIGEN is not set
CONFIG_SYS_IDE_MAXDEVICE=4
CONFIG_SYS_ATA_DATA_OFFSET=0
@@ -61,6 +63,9 @@
CONFIG_SOUND_I8254=y
CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_SIZE=20
+# CONFIG_CONSOLE_TRUETYPE_NIMBUS is not set
+CONFIG_CONSOLE_TRUETYPE_ANKACODER=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_SPL_ACPI=y
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 0b103ef..bd190e4 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -11,10 +11,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTAGE=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi"
+CONFIG_CEDIT=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LOG=y
@@ -30,6 +32,7 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
@@ -40,6 +43,7 @@
CONFIG_USE_ROOTPATH=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_OFNODE_MULTI_TREE=y
# CONFIG_ACPIGEN is not set
CONFIG_SYS_IDE_MAXDEVICE=4
CONFIG_SYS_ATA_DATA_OFFSET=0
@@ -55,6 +59,9 @@
CONFIG_SOUND_I8254=y
CONFIG_VIDEO_COPY=y
CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_SIZE=20
+# CONFIG_CONSOLE_TRUETYPE_NIMBUS is not set
+CONFIG_CONSOLE_TRUETYPE_ANKACODER=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig
index 0cb3399..d779e7d 100644
--- a/configs/cortina_presidio-asic-base_defconfig
+++ b/configs/cortina_presidio-asic-base_defconfig
@@ -32,7 +32,7 @@
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CORTINA_GPIO=y
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig
index 093874d..cdb9681 100644
--- a/configs/cortina_presidio-asic-pnand_defconfig
+++ b/configs/cortina_presidio-asic-pnand_defconfig
@@ -33,7 +33,7 @@
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CORTINA_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index b327149..5b69a20 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -58,7 +58,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 27dab9e..468ec38 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -1,132 +1,77 @@
+#include <configs/imx_dhsom.config>
+
CONFIG_ARM=y
-CONFIG_SPL_SYS_L2_PL310=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6QDL=y
-CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DHCOMIMX6=y
-CONFIG_DM_GPIO=y
+CONFIG_SPL_SYS_L2_PL310=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
-CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_MX6_DDRCAL=y
+CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
-CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_ENV_OFFSET_REDUND=0x110000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_AHCI=y
-CONFIG_SYS_MEMTEST_START=0x10000000
-CONFIG_SYS_MEMTEST_END=0x20000000
-CONFIG_LTO=y
-CONFIG_FIT=y
+CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_PBSIZE=532
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_LTO=y
+
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SYS_MAXARGS=32
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+CONFIG_SYS_MEMTEST_END=0x20000000
+CONFIG_SYS_MEMTEST_START=0x10000000
+CONFIG_SYS_MONITOR_LEN=409600
+CONFIG_SYS_PBSIZE=532
+
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SYS_BOOTCOUNT_BE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTDELAY=3
+
+CONFIG_BZIP2=y
CONFIG_CMD_SATA=y
-# CONFIG_CMD_SCSI is not set
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_WDT=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FEC"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARP_TIMEOUT=200
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
+CONFIG_DISTRO_DEFAULTS=y
+
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_OFFSET_REDUND=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SIZE=0x4000
+
+# CONFIG_CMD_SCSI is not set
+CONFIG_AHCI=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_LBA48=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SCSI=y
+
+CONFIG_ARP_TIMEOUT=200
+CONFIG_ETHPRIME="FEC"
+CONFIG_USE_ETHPRIME=y
+CONFIG_PHYLIB=y
+
+CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
+CONFIG_SPI_FLASH_UNLOCK_ALL=y
+
+CONFIG_MISC=y
+
CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
+
+CONFIG_SDP_LOADADDR=0x17ffffc0
+CONFIG_SPL_FIT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="dh"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_CI_UDC=y
-CONFIG_SDP_LOADADDR=0x17ffffc0
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_BZIP2=y
+
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/dhsom.config b/configs/dhsom.config
new file mode 100644
index 0000000..fc76632
--- /dev/null
+++ b/configs/dhsom.config
@@ -0,0 +1,56 @@
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_XXD=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_HASH_VERIFY=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_SHA1SUM_VERIFY=y
+
+CONFIG_VERSION_VARIABLE=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index c91cb64..765920b 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
@@ -18,7 +17,6 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index c5a4f82..4007c89 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_GPIO=y
@@ -18,7 +17,6 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index 0bb7e30..c321e6f 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -65,7 +65,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/durian_defconfig b/configs/durian_defconfig
index 7765fe3..ea1d37e 100644
--- a/configs/durian_defconfig
+++ b/configs/durian_defconfig
@@ -28,7 +28,7 @@
CONFIG_CMD_PCI=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
# CONFIG_MMC is not set
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index e5d9099..5797c6c 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -20,7 +20,7 @@
CONFIG_CMD_PART=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK_EXYNOS850=y
CONFIG_MMC_DW=y
CONFIG_SOC_SAMSUNG=y
diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig
index af9fc5f..c3af7af 100644
--- a/configs/ea-lpc3250devkitv2_defconfig
+++ b/configs/ea-lpc3250devkitv2_defconfig
@@ -25,7 +25,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_LPC32XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_LPC32XX=y
diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig
index 0025e56..c730945 100644
--- a/configs/efi-x86_app32_defconfig
+++ b/configs/efi-x86_app32_defconfig
@@ -36,7 +36,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_GZIP is not set
diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig
index 1cc50b6..1831fb2 100644
--- a/configs/efi-x86_app64_defconfig
+++ b/configs/efi-x86_app64_defconfig
@@ -40,7 +40,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig
index efa5eec..376862a 100644
--- a/configs/emsdp_defconfig
+++ b/configs/emsdp_defconfig
@@ -30,7 +30,7 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="app.bin"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 48f5b90..b087144 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -57,7 +57,7 @@
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 0f3d260..6091319 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -88,13 +88,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 403a5a5..cfa51b2 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
@@ -16,7 +15,6 @@
CONFIG_TARGET_GE_B1X5V2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 9cd88af..c24513f 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 9b9eab6..1d06f34 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -41,7 +41,7 @@
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index f22277f..ebe883e 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -35,7 +35,7 @@
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index be78678..d212f91 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7793-gose"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Gose"
CONFIG_R8A7793=y
CONFIG_TARGET_GOSE=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,63 +29,14 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 44f37c5..95d5b11 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -15,7 +14,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_CMD_EECONFIG=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 82b359d..1d8af5c 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -15,7 +14,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_CMD_EECONFIG=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig
index d06f922..d7cc7d1 100644
--- a/configs/hc2910_2aghd05_defconfig
+++ b/configs/hc2910_2aghd05_defconfig
@@ -37,7 +37,7 @@
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 61d110e..e45446c 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index bc64a80..6266f3c 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -1,83 +1,42 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m"
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
# CONFIG_SPL is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m renesas/r8a774b1-hihope-rzg2n renesas/r8a774e1-hihope-rzg2h"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_GPIO_HOG=y
-CONFIG_RCAR_GPIO=y
CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index f1d9bb3..51c825d 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -60,7 +60,7 @@
CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 3a20b7a..4352e38 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index 0e4ac2f..95797ff 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
@@ -8,7 +7,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6DL_MAMOJ=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig
index c4e02a8..a364e2c 100644
--- a/configs/imx6dl_sielaff_defconfig
+++ b/configs/imx6dl_sielaff_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
@@ -16,7 +15,6 @@
CONFIG_TARGET_MX6S_SIELAFF=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index 354b737..54758df 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -13,7 +13,6 @@
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_MX6Q_ACC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -82,7 +81,7 @@
CONFIG_ENV_WRITEABLE_LIST=y
CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index 48d08d3..2c7b8cc 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 2f68e2c..fd251e7 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -12,7 +11,6 @@
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_MX6LOGICPD=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index 77a1212..cf4c2d9 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 1e79c4f..fb0787d 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index 48d08d3..2c7b8cc 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index 69ba60f..49feb1a 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,7 +10,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index 6a84c0a..a5c3b48 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -11,7 +11,6 @@
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index 32e18bd..187fae8 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -11,7 +11,6 @@
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index a65659e..f285b82 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -11,7 +11,6 @@
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index acd49fb..fe70c19 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -11,7 +11,6 @@
CONFIG_MX6UL=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index 93ead4c..15a3ec5 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -12,7 +12,6 @@
CONFIG_MX6ULL=y
CONFIG_TARGET_MX6ULZ_SMM_M2=y
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ulz-bsh-smm-m2"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_BSS_START_ADDR=0x84100000
CONFIG_SPL=y
@@ -42,7 +41,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
diff --git a/configs/imx8mp_dhcom_drc02_defconfig b/configs/imx8mp_dhcom_drc02_defconfig
index d0877ad..c43839c 100644
--- a/configs/imx8mp_dhcom_drc02_defconfig
+++ b/configs/imx8mp_dhcom_drc02_defconfig
@@ -1,275 +1,7 @@
+#include <configs/imx8mp_dhsom.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0xFE0000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-drc02"
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x400
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30860000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFF0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-drc02.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x26000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_FIT_IMAGE_TINY is not set
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE_AUTO=y
-CONFIG_ENV_SPI_MAX_HZ=80000000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_SPL_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
-CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-# CONFIG_INPUT is not set
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_SMSC=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_NVME_PCI=y
-CONFIG_PCIE_DW_IMX=y
-CONFIG_PHY_IMX8MQ_USB=y
-CONFIG_PHY_IMX8M_PCIE=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
-CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=2
-CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_NXP_FSPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_PREBOOT=""
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 9aa2faf..aae2e21 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -1,271 +1,9 @@
+#include <configs/imx8mp_dhsom.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0xFE0000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk2"
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x400
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30860000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFF0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
-CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk2.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x26000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_FIT_IMAGE_TINY is not set
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE_AUTO=y
-CONFIG_ENV_SPI_MAX_HZ=80000000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
-CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-# CONFIG_INPUT is not set
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_SMSC=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PHY_IMX8MQ_USB=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
-CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=2
-CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_NXP_FSPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-dhcom-pdk2"
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mp-dhcom-pdk2.dtb"
+CONFIG_PREBOOT=""
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 03a0485..f40bf26 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -1,276 +1,16 @@
+#include <configs/imx8mp_dhsom.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0xFE0000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk3"
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x400
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30860000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFF0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_PCI=y
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
-CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-dhcom-pdk3"
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mp-dhcom-pdk3.dtb"
CONFIG_PREBOOT="gpio clear GPIO1_11 ; sleep 0.1 ; gpio set GPIO1_11 ; sleep 0.1 ; i2c dev 4 && i2c mw 0x70 0 4 && i2c probe 0x2d && i2c mw 0x2d 0xaa55.2 0"
-CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk3.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x26000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_FIT_IMAGE_TINY is not set
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE_AUTO=y
-CONFIG_ENV_SPI_MAX_HZ=80000000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_SPL_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
-CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-# CONFIG_INPUT is not set
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_SMSC=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
CONFIG_NVME_PCI=y
+CONFIG_PCI=y
CONFIG_PCIE_DW_IMX=y
-CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PHY_IMX8M_PCIE=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
-CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=2
-CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_NXP_FSPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
diff --git a/configs/imx8mp_dhcom_picoitx_defconfig b/configs/imx8mp_dhcom_picoitx_defconfig
index 7cefe9a..99cd5f2 100644
--- a/configs/imx8mp_dhcom_picoitx_defconfig
+++ b/configs/imx8mp_dhcom_picoitx_defconfig
@@ -1,273 +1,7 @@
+#include <configs/imx8mp_dhsom.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0xFE0000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-picoitx"
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x400
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30860000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFF0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
-CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-picoitx.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x26000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_FIT_IMAGE_TINY is not set
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE_AUTO=y
-CONFIG_ENV_SPI_MAX_HZ=80000000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
-CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-# CONFIG_INPUT is not set
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_SMSC=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PHY_IMX8MQ_USB=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
-CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=2
-CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_NXP_FSPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_PREBOOT=""
diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config
new file mode 100644
index 0000000..4161431
--- /dev/null
+++ b/configs/imx8mp_dhsom.config
@@ -0,0 +1,158 @@
+#include <configs/imx_dhsom.config>
+
+CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
+# CONFIG_INPUT is not set
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SYS_PBSIZE=2081
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_USE_PREBOOT=y
+
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_DM=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_TEXT_BASE=0x920000
+
+CONFIG_CONSOLE_MUX=y
+CONFIG_CONS_INDEX=2
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=24000000
+
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_SMC=y
+CONFIG_SPL_I2C=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+
+CONFIG_ENV_OFFSET=0xFE0000
+CONFIG_ENV_OFFSET_REDUND=0xFF0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NXP_FSPI=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+
+CONFIG_FSL_CAAM=y
+
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_GPIO_HOG=y
+
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_PHY_SMSC=y
+CONFIG_RGMII=y
+
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_POWER=y
+
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_PINCTRL=y
+
+CONFIG_CMD_SPI=y
+CONFIG_DM_MTD=y
+
+CONFIG_DM_RESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+
+CONFIG_DM_RNG=y
+
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+
+CONFIG_CMD_USB_SDP=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_XHCI_HCD=y
+
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig
new file mode 100644
index 0000000..d4c10fe
--- /dev/null
+++ b/configs/imx8mp_navqp_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-navqp"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_NAVQP=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x960000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-navqp.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig
new file mode 100644
index 0000000..74460a7
--- /dev/null
+++ b/configs/imx93_9x9_qsb_defconfig
@@ -0,0 +1,139 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="imx93_qsb"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-9x9-qsb"
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_TARGET_IMX93_9X9_QSB=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_CLK_IMX93=y
+CONFIG_CPU=y
+CONFIG_CPU_IMX=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig
new file mode 100644
index 0000000..4b39db4
--- /dev/null
+++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig
@@ -0,0 +1,140 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="imx93_qsb"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-9x9-qsb"
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_TARGET_IMX93_9X9_QSB=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_CLK_IMX93=y
+CONFIG_CPU=y
+CONFIG_CPU_IMX=y
+CONFIG_IMX9_DRAM_INLINE_ECC=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
diff --git a/configs/imx_dhsom.config b/configs/imx_dhsom.config
new file mode 100644
index 0000000..d166b2c
--- /dev/null
+++ b/configs/imx_dhsom.config
@@ -0,0 +1,96 @@
+#include <configs/dhsom.config>
+
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_FIT=y
+CONFIG_OF_CONTROL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+
+CONFIG_SPL=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_WATCHDOG=y
+# CONFIG_SPL_DM_SERIAL is not set
+# CONFIG_SPL_DM_USB is not set
+
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_SYSBOOT=y
+
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+
+CONFIG_DM_I2C=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+
+CONFIG_FSL_USDHC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+
+CONFIG_IPV6=y
+CONFIG_FEC_MXC=y
+CONFIG_IP_DEFRAG=y
+CONFIG_MII=y
+CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_TFTP_TSIZE=y
+
+CONFIG_MTD=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MXC_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+
+CONFIG_PINCTRL=y
+
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 5865d41..58a3e92 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -67,6 +67,7 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f8b8539..141303c 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -23,10 +23,10 @@
CONFIG_SPL=y
CONFIG_HAVE_SYS_UBOOT_START=y
CONFIG_SYS_UBOOT_START=0x800023FD
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SD_BOOT=y
CONFIG_SPI_BOOT=y
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
@@ -84,5 +84,6 @@
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index 73001ff..b77dbab 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="imxrt1050-evk-nor"
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
CONFIG_ENV_OFFSET=0x80000
@@ -24,10 +25,10 @@
CONFIG_SPL=y
CONFIG_HAVE_SYS_UBOOT_START=y
CONFIG_SYS_UBOOT_START=0x800023FD
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SD_BOOT=y
CONFIG_SPI_BOOT=y
-# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
@@ -85,6 +86,7 @@
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
CONFIG_FSPI_CONF_HEADER=y
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 5f28c22..487da27 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -68,3 +68,4 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 401e57a..2624f0c 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -17,7 +17,7 @@
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am6528-iot2050-basic"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -79,8 +79,11 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="ti/k3-am6528-iot2050-basic ti/k3-am6528-iot2050-basic-pg2 ti/k3-am6548-iot2050-advanced ti/k3-am6548-iot2050-advanced-pg2 ti/k3-am6548-iot2050-advanced-m2 ti/k3-am6548-iot2050-advanced-sm"
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6548-iot2050-advanced-m2-bkey-usb3 ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie"
CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl"
+CONFIG_SPL_OF_LIST="ti/k3-am6528-iot2050-basic"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig
index ba275d0..5b7e131 100644
--- a/configs/iot_devkit_defconfig
+++ b/configs/iot_devkit_defconfig
@@ -34,7 +34,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="app.bin"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 2fbfda5..03849b9 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -32,6 +32,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
+CONFIG_PCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
@@ -71,6 +72,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
@@ -91,6 +93,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
@@ -153,6 +156,9 @@
CONFIG_PHY_TI_DP83869=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_CONFIG_HOST_BRIDGE=y
+CONFIG_PCIE_CDNS_TI=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index dcb7087..1db9251 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -76,6 +76,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 640c1be..bd55634 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -97,6 +97,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 4c2d53b..ad6dbbc 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -85,6 +85,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 769c609..d619ac8 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -90,6 +90,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index eeb38af..d647f7c 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -86,6 +86,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
@@ -110,6 +111,7 @@
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
+CONFIG_K3_AVS0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
@@ -139,6 +141,11 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65941=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index 74fbe52..e6a573d 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -70,7 +70,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index f022017..c7fc6be 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -42,6 +42,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 2281517..0b5441f 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -73,6 +73,7 @@
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index 510fe4f..de5357c 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -47,7 +47,6 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index d2da8ff..4d7b90f 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -47,7 +47,6 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AVB=y
CONFIG_OF_CONTROL=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index f5deacf..9bce9e3 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7791-koelsch"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Koelsch"
CONFIG_R8A7791=y
CONFIG_TARGET_KOELSCH=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,63 +29,14 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig
index 0ca7d33..9ee0225 100644
--- a/configs/kontron-sl-mx6ul_defconfig
+++ b/configs/kontron-sl-mx6ul_defconfig
@@ -14,7 +14,6 @@
CONFIG_TARGET_KONTRON_MX6UL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-bl"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index fceda3f..7fd2bfb 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x2200
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -12,7 +11,6 @@
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KP_IMX6Q_TPC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 920d026..0d4eed0 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7790-lager"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Lager"
CONFIG_R8A7790=y
CONFIG_TARGET_LAGER=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,65 +29,16 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_SH_MMCIF=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 34ef3493..60b7a84 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -44,7 +44,7 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 941a1cf..9a81e97 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -12,7 +12,6 @@
CONFIG_TARGET_LITEBOARD=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig
index d202cad..7ab8179 100644
--- a/configs/lxr2_defconfig
+++ b/configs/lxr2_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
@@ -15,7 +14,6 @@
CONFIG_TARGET_LXR2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-lxr"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 198fec2..b90d294 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 8edc461..9b60ce3 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,7 +12,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 6088d08..ecd3e31 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,7 +12,6 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_MCCMON6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index 94952a9..a35721a 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -4,8 +4,8 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
-CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit"
+CONFIG_OF_UPSTREAM=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_MEM_TOP_HIDE=0x400000
CONFIG_TARGET_MICROCHIP_ICICLE=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index 0610b51..dc9b12e 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -68,7 +68,7 @@
CONFIG_SPL_OF_PLATDATA=y
CONFIG_TPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
index 505f063..e8984b6 100644
--- a/configs/mvebu_crb_cn9130_defconfig
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -46,7 +46,7 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 962edb7..e5de34c 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -43,7 +43,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 7c6b53e..f9b03a7 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -42,7 +42,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig
index f80812c..6dd6be7 100644
--- a/configs/mvebu_db_cn9130_defconfig
+++ b/configs/mvebu_db_cn9130_defconfig
@@ -47,7 +47,7 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 375705c..e9ee885 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -54,7 +54,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig
index fe3def1..aa9026a 100644
--- a/configs/mvebu_espressobin_ultra-88f3720_defconfig
+++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig
@@ -53,7 +53,7 @@
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index c1b470c..90d341e 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -46,7 +46,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig
index 1d86e26..21ab217 100644
--- a/configs/mvebu_puzzle-m801-88f8040_defconfig
+++ b/configs/mvebu_puzzle-m801-88f8040_defconfig
@@ -50,7 +50,7 @@
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_PCA953X=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 793ba6a..6152d93 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -41,7 +41,7 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_PINCTRL=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index a94d34d..951d506 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -47,7 +47,7 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index e3aba71..14c1386 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -12,7 +11,6 @@
CONFIG_TARGET_MX6CUBOXI=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 0c98c68..b5cc341 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -9,7 +8,6 @@
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_MX6MEMCAL=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_MEMTEST_START=0x10000000
@@ -39,7 +37,7 @@
CONFIG_CMD_CACHE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
# CONFIG_MMC is not set
CONFIG_FSL_USDHC=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index bb830c4..9169923 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 76f6eec..94b251c 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
@@ -14,7 +13,6 @@
CONFIG_TARGET_MX6SABREAUTO=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 2a83b8c..f041f1f 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_GPIO=y
@@ -14,7 +13,6 @@
CONFIG_TARGET_MX6SABRESD=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index bbeb364..f841b21 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -15,7 +15,6 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -89,10 +88,12 @@
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_SOFT_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SYSRESET_WATCHDOG_AUTO=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
@@ -108,3 +109,4 @@
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 101653a..11a18d1 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -15,7 +15,6 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index d57b47e..2c13dd4 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -36,7 +36,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index eba57dd..a49cb2a 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -33,7 +33,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index 262ee67..12f1311 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -33,7 +33,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index dc9fc50..8e05d39 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -31,7 +31,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 8d54882..7851bc4 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -65,7 +65,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index d62c816..772b7df 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -32,6 +32,7 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
+CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -43,13 +44,20 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rockchip/rk3588-nanopc-t6 rockchip/rk3588-nanopc-t6-lts"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+CONFIG_SPL_ADC=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
@@ -69,12 +77,16 @@
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
index 702fb5b..f83df37 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -94,13 +94,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 02edd49..1e65091 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -94,13 +94,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 883471d..90073a1 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -94,13 +94,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig
index 352b98f..377cc26 100644
--- a/configs/netgear_cg3100d_ram_defconfig
+++ b/configs/netgear_cg3100d_ram_defconfig
@@ -39,7 +39,7 @@
CONFIG_CMD_SPI=y
# CONFIG_CMD_SLEEP is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_BCM6345_GPIO=y
CONFIG_LED=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 7060d3c..a0d7772 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index c2566c9..436ce28 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 07800ef..827e883 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index c5e6ce5..62fc8d8 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index e91c19d..d16cf2a 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index b8b410c..bd3ae13 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index dd3541b..bcd40b3 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -15,7 +14,6 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/nsim_700_defconfig b/configs/nsim_700_defconfig
index a46d2ee..d50e85a 100644
--- a/configs/nsim_700_defconfig
+++ b/configs/nsim_700_defconfig
@@ -25,7 +25,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
diff --git a/configs/nsim_700be_defconfig b/configs/nsim_700be_defconfig
index 8dc3181..4832195 100644
--- a/configs/nsim_700be_defconfig
+++ b/configs/nsim_700be_defconfig
@@ -26,7 +26,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
diff --git a/configs/nsim_hs38be_defconfig b/configs/nsim_hs38be_defconfig
index 5f21b31..67de123 100644
--- a/configs/nsim_hs38be_defconfig
+++ b/configs/nsim_hs38be_defconfig
@@ -27,7 +27,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index 0febe80..76adbf2 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -46,7 +46,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_TFTP_TSIZE=y
CONFIG_SATA=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_CLK=y
diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig
new file mode 100644
index 0000000..21f4fcb
--- /dev/null
+++ b/configs/odroid-m1s-rk3566_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-odroid-m1s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ODROID_M1S_RK3566=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-odroid-m1s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_INI=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_CRAMFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_FS_CRAMFS=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig
new file mode 100644
index 0000000..d612ef3
--- /dev/null
+++ b/configs/odroid-m2-rk3588s_defconfig
@@ -0,0 +1,96 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-odroid-m2"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ODROID_M2_RK3588S=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-odroid-m2.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_INI=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_CRAMFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_FS_CRAMFS=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig
index a47214b..1e693c6 100644
--- a/configs/openpiton_riscv64_defconfig
+++ b/configs/openpiton_riscv64_defconfig
@@ -62,7 +62,7 @@
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_EMBED=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig
index d2eb891..09054d9 100644
--- a/configs/openpiton_riscv64_spl_defconfig
+++ b/configs/openpiton_riscv64_spl_defconfig
@@ -78,7 +78,7 @@
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 2b06de5..ef26332 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -11,7 +11,6 @@
CONFIG_MX6UL=y
CONFIG_TARGET_OPOS6ULDEV=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 8b05aa2..23d3baa 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -104,13 +104,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index 05f1924..faadfa8 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -104,13 +104,12 @@
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 9fd7bc1..c6cc17a 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -41,7 +41,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_MMC_DW=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 48f63c9..8ab2c1c 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -16,7 +15,6 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig
index c28ceac..72f6274 100644
--- a/configs/pe2201_defconfig
+++ b/configs/pe2201_defconfig
@@ -27,7 +27,7 @@
CONFIG_CMD_PCI=y
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
# CONFIG_MMC is not set
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index e3aca6e..b945adf 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -12,7 +12,6 @@
CONFIG_TARGET_PICO_IMX6UL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 9b2496e..4a9c5ac 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -12,7 +11,6 @@
CONFIG_TARGET_PICO_IMX6=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index ce29718..c9a0ccd 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -12,7 +12,6 @@
CONFIG_TARGET_PICO_IMX6UL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index 81f3e9b..daff2e3 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -12,7 +12,6 @@
CONFIG_TARGET_PICO_IMX6UL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 7cc0a86..7567a6a 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -9,7 +9,7 @@
CONFIG_I2C0_ENABLE=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SPL_I2C=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index 9f4d434..026c6de 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -37,7 +37,7 @@
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 77844af..98a67be 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7791-porter"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Porter"
CONFIG_R8A7791=y
CONFIG_TARGET_PORTER=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,63 +29,14 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig
new file mode 100644
index 0000000..69195af
--- /dev/null
+++ b/configs/qemu-arm-sbsa_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_QEMU=y
+CONFIG_TARGET_QEMU_ARM_SBSA=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootflow scan"
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_EFI_MEDIA=y
+CONFIG_FS_FAT=y
+CONFIG_EFI_VARIABLE_NO_STORE=y
+CONFIG_BLOBLIST_ALLOC=y
+CONFIG_BLOBLIST_SIZE_RELOC=0x20000
diff --git a/configs/qemu_arm64_lwip_defconfig b/configs/qemu_arm64_lwip_defconfig
new file mode 100644
index 0000000..d3d8ef1
--- /dev/null
+++ b/configs/qemu_arm64_lwip_defconfig
@@ -0,0 +1,9 @@
+#include <configs/qemu_arm64_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_QEMU=y
+
+CONFIG_NET_LWIP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_WGET=y
+CONFIG_EFI_HTTP_BOOT=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 33484df..4534b17 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -1,84 +1,43 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77970-eagle"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EAGLE=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77970-eagle.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
-CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig
index ab49d54..4a146e1 100644
--- a/configs/r8a77970_v3msk_defconfig
+++ b/configs/r8a77970_v3msk_defconfig
@@ -1,87 +1,46 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77970-v3msk"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
CONFIG_TARGET_V3MSK=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
-CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index 1e7e430..9cf93d7 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -1,66 +1,37 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77980-condor"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_CONDOR=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77980-condor.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
@@ -69,24 +40,12 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SH_ETHER=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
index e942acd..d177207 100644
--- a/configs/r8a77980_v3hsk_defconfig
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -1,83 +1,42 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77980-v3hsk"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_R8A77980=y
CONFIG_TARGET_V3HSK=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_SH_ETHER=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 7418d39..da93d44 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -1,69 +1,40 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77990-ebisu"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_BASE=0x00000000
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77990-ebisu.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
@@ -72,7 +43,6 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -85,22 +55,11 @@
CONFIG_RENESAS_RPC_HF=y
CONFIG_SYS_MAX_FLASH_SECT=256
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 29d921d..0fe5be6 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -1,68 +1,39 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77995-draak"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_DRAAK=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_BASE=0x00000000
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77995-draak.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
-CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
@@ -71,7 +42,6 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -82,22 +52,11 @@
CONFIG_RENESAS_RPC_HF=y
CONFIG_SYS_MAX_FLASH_SECT=256
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig
index ad53d88..aae4406 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -1,75 +1,23 @@
+#include <configs/renesas_rcar4.config>
+
CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=16666666
-CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN4=y
+CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779a0-falcon"
-CONFIG_RCAR_GEN4=y
CONFIG_TARGET_FALCON=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_CLK_FREQ=16666666
-# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a779a0-falcon.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb"
CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig
index 1959abc..7274038 100644
--- a/configs/r8a779f0_spider_defconfig
+++ b/configs/r8a779f0_spider_defconfig
@@ -1,84 +1,32 @@
+#include <configs/renesas_rcar4.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_RCAR_GEN4=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xD00000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f0-spider"
-CONFIG_RCAR_GEN4=y
CONFIG_TARGET_SPIDER=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_CLK_FREQ=20000000
-# CONFIG_PSCI_RESET is not set
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb"
CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_UFS=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
-CONFIG_CLK=y
CONFIG_CLK_GPIO=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL_10G=y
-CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_ETHER_SWITCH=y
CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1843200
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_UFS=y
CONFIG_UFS_RENESAS=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=131072
diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
index ba7abb9..758b0ff 100644
--- a/configs/r8a779g0_whitehawk_defconfig
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -1,75 +1,23 @@
+#include <configs/renesas_rcar4.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_RCAR_GEN4=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779g0-white-hawk"
-CONFIG_RCAR_GEN4=y
CONFIG_TARGET_WHITEHAWK=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_CLK_FREQ=16666666
-# CONFIG_PSCI_RESET is not set
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779g0-white-hawk.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779g0-white-hawk.dtb"
CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_BAUDRATE=921600
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig
index 73dd62e..ef70921 100644
--- a/configs/r8a779h0_grayhawk_defconfig
+++ b/configs/r8a779h0_grayhawk_defconfig
@@ -1,75 +1,23 @@
+#include <configs/renesas_rcar4.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_RCAR_GEN4=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779h0-gray-hawk-single"
-CONFIG_RCAR_GEN4=y
CONFIG_TARGET_GRAYHAWK=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_SYS_CLK_FREQ=16666666
-# CONFIG_PSCI_RESET is not set
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray-hawk.dtb && booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb"
CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_BAUDRATE=921600
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index f60beba..2655fdc 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -39,6 +39,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index 99f9e1c..4df594d 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -44,6 +44,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index b33b8fe..6b095f6 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -1,73 +1,44 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77951-salvator-x"
CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe633f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_PCI=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_BASE=0x00000000
# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
-CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77951-salvator-x.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77951-salvator-x.dtb"
-CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="renesas/r8a77951-salvator-x renesas/r8a77960-salvator-x renesas/r8a77965-salvator-x"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
@@ -76,7 +47,6 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -89,11 +59,7 @@
CONFIG_RENESAS_RPC_HF=y
CONFIG_SYS_MAX_FLASH_SECT=256
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
@@ -101,13 +67,6 @@
CONFIG_NVME_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_RCAR_GEN3=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_TEE=y
CONFIG_OPTEE=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index f8e8c92..7ffa115 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -1,70 +1,41 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77951-ulcb"
CONFIG_SPL_TEXT_BASE=0xe6338000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe633f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_BASE=0x00000000
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a77951-ulcb.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a77951-ulcb.dtb"
-CONFIG_SYS_PBSIZE=2068
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="renesas/r8a77951-ulcb renesas/r8a77960-ulcb renesas/r8a77965-ulcb"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
@@ -73,7 +44,6 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
@@ -86,22 +56,11 @@
CONFIG_RENESAS_RPC_HF=y
CONFIG_SYS_MAX_FLASH_SECT=256
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_TEE=y
diff --git a/configs/renesas_rcar.config b/configs/renesas_rcar.config
new file mode 100644
index 0000000..351803b
--- /dev/null
+++ b/configs/renesas_rcar.config
@@ -0,0 +1,27 @@
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_MTD=y
+CONFIG_OF_CONTROL=y
+CONFIG_RCAR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_VERSION_VARIABLE=y
diff --git a/configs/renesas_rcar2.config b/configs/renesas_rcar2.config
new file mode 100644
index 0000000..74dfd41
--- /dev/null
+++ b/configs/renesas_rcar2.config
@@ -0,0 +1,42 @@
+#include <configs/renesas_rcar.config>
+
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_USB=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_PARTITION_UUIDS=y
+CONFIG_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_SH_QSPI=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SYS_PBSIZE=256
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/renesas_rcar3.config b/configs/renesas_rcar3.config
new file mode 100644
index 0000000..228e1b4
--- /dev/null
+++ b/configs/renesas_rcar3.config
@@ -0,0 +1,6 @@
+#include <configs/renesas_rcar64.config>
+
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_PBSIZE=2068
diff --git a/configs/renesas_rcar4.config b/configs/renesas_rcar4.config
new file mode 100644
index 0000000..87d6a60
--- /dev/null
+++ b/configs/renesas_rcar4.config
@@ -0,0 +1,17 @@
+#include <configs/renesas_rcar64.config>
+
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_CMD_MMC=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/renesas_rcar64.config b/configs/renesas_rcar64.config
new file mode 100644
index 0000000..12211ae
--- /dev/null
+++ b/configs/renesas_rcar64.config
@@ -0,0 +1,14 @@
+#include <configs/renesas_rcar.config>
+
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SPI=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_REGMAP=y
+CONFIG_REMAKE_ELF=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYSCON=y
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MONITOR_LEN=1048576
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index a1e806b..24c6c59 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -14,7 +13,6 @@
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index d2f9cb7..733ce63 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -53,6 +53,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig
index 3f5d2cd..0c73a21 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -47,6 +47,8 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig
index 76408fa..3ae1969 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -51,6 +51,8 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 3a9b641..f3a5c2c 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -52,6 +52,8 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index bb0fed7..9bda50c 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -52,6 +52,8 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 0a97c89..52dad76 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -53,6 +53,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig b/configs/rock-pi-e-v3-rk3328_defconfig
index df5c7e2..518ea4e 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -54,6 +54,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index 9ffe917..9618d59 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -39,6 +39,8 @@
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index dd360d5..c54e13e 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -24,6 +24,7 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -56,6 +57,8 @@
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
@@ -103,3 +106,6 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_FUSB302=y
+CONFIG_CMD_TCPM=y
diff --git a/configs/rpi_4_acpi_defconfig b/configs/rpi_4_acpi_defconfig
new file mode 100644
index 0000000..b32dfc1
--- /dev/null
+++ b/configs/rpi_4_acpi_defconfig
@@ -0,0 +1,10 @@
+#include <configs/rpi_4_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_4=y
+CONFIG_BLOBLIST_ALLOC=y
+CONFIG_OF_BOARD=y
+CONFIG_ACPI=y
+CONFIG_GENERATE_ACPI_TABLE=y
+
diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig
index 95e82df..5e19d36 100644
--- a/configs/rzg2_beacon_defconfig
+++ b/configs/rzg2_beacon_defconfig
@@ -1,84 +1,43 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-beacon-rzg2m-kit"
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_BEACON_RZG2M=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SYS_LOAD_ADDR=0x58000000
# CONFIG_SPL is not set
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="renesas/r8a774a1-beacon-rzg2m-kit renesas/r8a774b1-beacon-rzg2n-kit renesas/r8a774e1-beacon-rzg2h-kit"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig
index 2386209..548963c 100644
--- a/configs/s5p4418_nanopi2_defconfig
+++ b/configs/s5p4418_nanopi2_defconfig
@@ -49,7 +49,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_DEV=2
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_NEXELL=y
CONFIG_MMC_DW=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 4316510..084e19e 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -44,7 +44,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 1607a31..190ec96 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -41,7 +41,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SYS_I2C_S3C24X0=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index 4b29891..7cde865 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -64,7 +64,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_FAT=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
diff --git a/configs/sama5d29_curiosity_mmc1_defconfig b/configs/sama5d29_curiosity_mmc1_defconfig
index 25ff38c..c8976ee 100644
--- a/configs/sama5d29_curiosity_mmc1_defconfig
+++ b/configs/sama5d29_curiosity_mmc1_defconfig
@@ -72,7 +72,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA5D29"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
diff --git a/configs/sama5d29_curiosity_mmc_defconfig b/configs/sama5d29_curiosity_mmc_defconfig
index e691839..7fe1a5b 100644
--- a/configs/sama5d29_curiosity_mmc_defconfig
+++ b/configs/sama5d29_curiosity_mmc_defconfig
@@ -71,7 +71,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA5D29"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
diff --git a/configs/sama5d29_curiosity_qspiflash_defconfig b/configs/sama5d29_curiosity_qspiflash_defconfig
index f340423..fd35511 100644
--- a/configs/sama5d29_curiosity_qspiflash_defconfig
+++ b/configs/sama5d29_curiosity_qspiflash_defconfig
@@ -71,7 +71,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA5D29"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
diff --git a/configs/sama7g54_curiosity_mmc_defconfig b/configs/sama7g54_curiosity_mmc_defconfig
index 41c1845..fec883e 100644
--- a/configs/sama7g54_curiosity_mmc_defconfig
+++ b/configs/sama7g54_curiosity_mmc_defconfig
@@ -75,7 +75,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA7G54"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_AT91=y
diff --git a/configs/sama7g54_curiosity_nandflash_defconfig b/configs/sama7g54_curiosity_nandflash_defconfig
index 59e8189..7a4cdb0 100644
--- a/configs/sama7g54_curiosity_nandflash_defconfig
+++ b/configs/sama7g54_curiosity_nandflash_defconfig
@@ -73,7 +73,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA7G54"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_AT91=y
diff --git a/configs/sama7g54_curiosity_qspiflash_defconfig b/configs/sama7g54_curiosity_qspiflash_defconfig
index 20cd714..adf5f55 100644
--- a/configs/sama7g54_curiosity_qspiflash_defconfig
+++ b/configs/sama7g54_curiosity_qspiflash_defconfig
@@ -74,7 +74,7 @@
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="SAMA7G54"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_AT91=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 1b3b8c6..b5f80b8 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -27,6 +27,7 @@
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ANDROID_AB=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
@@ -46,6 +47,7 @@
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_BCB=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index f596f1c..d111858 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -103,7 +103,6 @@
CONFIG_CMD_CAT=y
CONFIG_CMD_SETEXPR_FMT=y
CONFIG_CMD_XXD=y
-CONFIG_CMD_AB_SELECT=y
CONFIG_CMD_DHCP6=y
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_PCAP=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index d1b1c03..031fdc0 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -1,84 +1,43 @@
+#include <configs/renesas_rcar3.config>
+
CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN3=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3F0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774c0-ek874"
CONFIG_SPL_TEXT_BASE=0xe6318000
-CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SILINUX_EK874=y
-CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_STACK=0xe6304000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_LOAD_ADDR=0x58000000
-CONFIG_REMAKE_ELF=y
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774c0-ek874.dtb; booti 0x48080000 - 0x48000000"
CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb"
-CONFIG_SYS_PBSIZE=2068
# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
CONFIG_SOC_DEVICE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index feca2ce..53597e9 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7794-silk"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Silk"
CONFIG_R8A7794=y
CONFIG_TARGET_SILK=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,65 +29,16 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_SH_MMCIF=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
index 0d74d63..b2e21c7 100644
--- a/configs/sipeed_maix_bitm_defconfig
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -19,7 +19,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK_K210_SET_RATE=y
# CONFIG_INPUT is not set
CONFIG_FS_EXT4=y
diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig
index 4af6e34..d838b25 100644
--- a/configs/sipeed_maix_smode_defconfig
+++ b/configs/sipeed_maix_smode_defconfig
@@ -20,7 +20,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_INPUT is not set
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 511645c..c350892 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="StarFive # "
+CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig
index 88e7608..631ccab 100644
--- a/configs/stemmy_defconfig
+++ b/configs/stemmy_defconfig
@@ -29,7 +29,7 @@
CONFIG_CMD_PART=y
CONFIG_CMD_GETTIME=y
CONFIG_EFI_PARTITION=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x18100000
CONFIG_FASTBOOT_FLASH=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 5199e54..7788933 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -27,7 +27,7 @@
CONFIG_CMD_TIMER=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index 412533e..2fa8dc9 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -25,7 +25,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index 93420cb..9839941 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -26,7 +26,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 376edc2..40fc938 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -30,6 +30,6 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index c249c4d..953e67e 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -30,6 +30,6 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
index d66f440..4ca2d30 100644
--- a/configs/stm32h750-art-pi_defconfig
+++ b/configs/stm32h750-art-pi_defconfig
@@ -36,7 +36,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_DMA=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
index ff9707d..1ca057c 100644
--- a/configs/stm32mp13_dhcor_defconfig
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -6,7 +6,7 @@
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x3E0000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dhcor-dhsbc"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dhcor-dhsbc"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_STM32MP13X=y
@@ -65,6 +65,7 @@
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_MAX_HZ=50000000
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 7426a78..a92c615d 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -7,7 +7,7 @@
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-pdk2"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -32,7 +32,6 @@
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
@@ -56,7 +55,6 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
@@ -92,7 +90,8 @@
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_LIVE=y
-CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index b6d7f1e..4162eda 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -7,7 +7,7 @@
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
@@ -30,7 +30,6 @@
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
-CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
@@ -54,7 +53,6 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
-CONFIG_SPL_TARGET="u-boot.itb"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
@@ -90,7 +88,8 @@
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_LIVE=y
-CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact"
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 85e6830..d3f0c08 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -32,7 +32,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_OF_LIVE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index f43a24c..79b21ac 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -39,7 +39,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="stmark2"
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_MTD=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index e2ca0ae..a25a562 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,41 +1,25 @@
+#include <configs/renesas_rcar2.config>
+
CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_RENESAS=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_RENESAS=y
CONFIG_TEXT_BASE=0x50000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
-CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a7790-stout"
CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_ARCH_RENESAS_BOARD_STRING="Stout"
CONFIG_R8A7790=y
CONFIG_TARGET_STOUT=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xe6340000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ENV_ADDR=0xC0000
-CONFIG_PCI=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=256
CONFIG_SPL_MAX_SIZE=0x4000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
@@ -45,64 +29,15 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
-CONFIG_PARTITION_UUIDS=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_CLK=y
-CONFIG_CLK_RENESAS=y
-CONFIG_RCAR_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_RENESAS_SDHI=y
-CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SCIF_CONSOLE=y
CONFIG_SH_SCIF_CLK_FREQ=52000000
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SH_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_SYS_TIMER_COUNTS_DOWN=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 3ab6799..99fe65d 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index 98bcb22..3b6ff62 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -4,6 +4,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
@@ -50,6 +51,7 @@
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
@@ -59,9 +61,9 @@
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_BLOCK_CACHE is not set
-# CONFIG_GPIO is not set
+CONFIG_DWAPB_GPIO=y
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
# CONFIG_DM_MMC is not set
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 3cc04af..24ad84b 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -33,7 +33,7 @@
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index ad234a3..cecd261 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -23,7 +23,7 @@
CONFIG_CMD_DATE=n
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET=n
+CONFIG_NO_NET=y
CONFIG_ACPIGEN=n
CONFIG_AXI=y
CONFIG_AXI_SANDBOX=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index accdfe9..039ac71 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -52,7 +52,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 1c65f6e..b53f3a7 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -52,7 +52,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 53bf0af..ba7f248 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -52,7 +52,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
index 291083d..e0d6199 100644
--- a/configs/total_compute_defconfig
+++ b/configs/total_compute_defconfig
@@ -42,7 +42,7 @@
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_CLK=y
# CONFIG_MMC_WRITE is not set
CONFIG_ARM_PL180_MMCI=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 3796aed..f4afd37 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -43,7 +43,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 91ad6b5..14849d0 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -42,7 +42,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 3bb8559..dd1a45b 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -90,7 +90,7 @@
CONFIG_NETCONSOLE=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
-CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_GENERIC=y
CONFIG_DM_PCA953X=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 00b732b..5730dac 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0x0200000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -12,7 +11,6 @@
CONFIG_TARGET_UDOO=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index 0c76b00..8183edd 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -12,7 +12,6 @@
CONFIG_TARGET_UDOO_NEO=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6sx-udoo-neo-basic"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 0b96484..9c69d9a 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -10,7 +10,6 @@
CONFIG_MX6ULL=y
CONFIG_TARGET_DART_6UL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index aa4a400..abb458d 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -100,8 +100,7 @@
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_BUF_ADDR=0x44200000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index bf1a0b8..661761f 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -112,8 +112,7 @@
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_BUF_ADDR=0x44200000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index e5c9c28..5842916 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -16,7 +16,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index e9deab3..e0dc56b 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -15,7 +14,6 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1"
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig
index 64e8eb2..e9a5219 100644
--- a/configs/xenguest_arm64_defconfig
+++ b/configs/xenguest_arm64_defconfig
@@ -37,7 +37,7 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_MMC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DM_SERIAL=y
diff --git a/configs/xenguest_arm64_virtio_defconfig b/configs/xenguest_arm64_virtio_defconfig
index b5e9b39..acf131f 100644
--- a/configs/xenguest_arm64_virtio_defconfig
+++ b/configs/xenguest_arm64_virtio_defconfig
@@ -42,7 +42,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_PARTITION_TYPE_GUID=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_MMC is not set
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 3983b20..7333413 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -2,17 +2,17 @@
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
-CONFIG_SPL_STACK=0x20200000
-CONFIG_SPL_BSS_START_ADDR=0x24000000
+CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SYS_LOAD_ADDR=0x20200000
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
-CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y
@@ -20,7 +20,7 @@
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 229a38d..7388a78 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -58,7 +58,7 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 8cd24f4..a36e40d 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -56,7 +56,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index e868d47..3ae2115 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -56,7 +56,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index eecbc12..d0ea2b6 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -52,7 +52,7 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 3c0adcd..ef6eec0 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -54,7 +54,7 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index ba656c9..1640dfa 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -62,7 +62,7 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index 61b0b2a..4c6159a 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -51,7 +51,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 6dc82bc..071eeb8 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -51,7 +51,7 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index 8d05d99..227c45d 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -53,7 +53,7 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 1e76692..7aab69c 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -54,7 +54,7 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 391b6f4..c56b1e83 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -65,7 +65,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 132210b..a8dbf00 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -65,7 +65,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 1de6b00..ba8f02c 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -49,7 +49,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 8c67786..a8a0055 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -49,7 +49,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 1a2dafe..c08b10c 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -68,7 +68,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_FIRMWARE is not set
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index d95e697..80852f3 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -70,7 +70,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index fbec4a6..326e4e3 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -70,7 +70,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 53c7edf..cd84df1 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -79,7 +79,7 @@
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
+CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 7f04c6e..bdcfcba 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -216,7 +216,7 @@
return 0;
}
-void part_print_efi(struct blk_desc *desc)
+static void __maybe_unused part_print_efi(struct blk_desc *desc)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
@@ -258,8 +258,8 @@
return;
}
-int part_get_info_efi(struct blk_desc *desc, int part,
- struct disk_partition *info)
+static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part,
+ struct disk_partition *info)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz);
gpt_entry *gpt_pte = NULL;
diff --git a/doc/android/ab.rst b/doc/android/ab.rst
index 2adf887..7fd4aeb 100644
--- a/doc/android/ab.rst
+++ b/doc/android/ab.rst
@@ -18,7 +18,7 @@
your board configuration file::
CONFIG_ANDROID_AB=y
- CONFIG_CMD_AB_SELECT=y
+ CONFIG_CMD_BCB=y
The disk space on target device must be partitioned in a way so that each
partition which needs to be updated has two or more instances. The name of
@@ -26,8 +26,8 @@
For example: ``boot_a``, ``boot_b``, ``system_a``, ``system_b``, ``vendor_a``,
``vendor_b``.
-As a result you can use ``ab_select`` command to ensure A/B boot process in your
-boot script. This command analyzes and processes A/B metadata stored on a
+As a result you can use ``bcb ab_select`` command to ensure A/B boot process in
+your boot script. This command analyzes and processes A/B metadata stored on a
special partition (e.g. ``misc``) and determines which slot should be used for
booting up.
@@ -42,15 +42,15 @@
.. code-block:: none
- ab_select <slot_var_name> <interface> <dev[:part_number|#part_name]>
+ bcb ab_select <slot_var_name> <interface> <dev[:part_number|#part_name]>
for example::
- => ab_select slot_name mmc 1:4
+ => bcb ab_select slot_name mmc 1:4
or::
- => ab_select slot_name mmc 1#misc
+ => bcb ab_select slot_name mmc 1#misc
Result::
diff --git a/doc/api/fs.rst b/doc/api/fs.rst
new file mode 100644
index 0000000..38c8b0d
--- /dev/null
+++ b/doc/api/fs.rst
@@ -0,0 +1,7 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+File system API
+===============
+
+.. kernel-doc:: include/fs.h
+ :internal:
diff --git a/doc/api/index.rst b/doc/api/index.rst
index 9f7f23f..a108718 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -12,6 +12,7 @@
dm
efi
event
+ fs
getopt
interrupt
led
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 7154f59..f52b24f 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -181,16 +181,10 @@
CI runs tests using a pre-built coreboot image. This ensures that U-Boot can
boot as a coreboot payload, based on a known-good build of coreboot.
-To update the `coreboot.rom` file which is used:
+To update the `coreboot.rom` file which is used, see ``tools/Dockerfile``
-#. Build coreboot with `CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y`. If using
- `make menuconfig`, this is under
- `Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer`.
-
-#. Compress the resulting `coreboot.rom`::
-
- xz -c /path/to/coreboot/build/coreboot.rom > coreboot.rom.xz
-
-#. Upload the file to Google drive
+Editing CMOS RAM settings
+-------------------------
-#. Send a patch to change the file ID used by wget in the CI yaml files.
+U-Boot supports creating a configuration editor to edit coreboot CMOS-RAM
+settings. See :ref:`cedit_cb_load`.
diff --git a/doc/board/emcraft/imx8mp-navqp.rst b/doc/board/emcraft/imx8mp-navqp.rst
new file mode 100644
index 0000000..89d8f95
--- /dev/null
+++ b/doc/board/emcraft/imx8mp-navqp.rst
@@ -0,0 +1,65 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. sectionauthor:: Gilles Talis <gilles.talis@gmail.com>
+
+i.MX8M Plus NavQ+ Board
+=======================
+
+U-Boot for the EmCraft Systems i.MX8M Plus NavQ+ board
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone -b lts-v2.10 https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make PLAT=imx8mp bl31
+ $ cp build/imx8mp/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+ $ cd ..
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
+ $ chmod +x firmware-imx-8.23.bin
+ $ ./firmware-imx-8.23.bin
+ $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*_202006.bin ./
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make imx8mp_navqp_defconfig
+ $ make
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB0 for U-Boot console
diff --git a/doc/board/emcraft/index.rst b/doc/board/emcraft/index.rst
new file mode 100644
index 0000000..564552c
--- /dev/null
+++ b/doc/board/emcraft/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emcraft
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ imx8mp-navqp
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
index 98a0b26..f890816 100644
--- a/doc/board/emulation/index.rst
+++ b/doc/board/emulation/index.rst
@@ -8,10 +8,14 @@
acpi
blkdev
- ../../usage/semihosting
qemu-arm
qemu-mips
qemu-ppce500
qemu-riscv
+ qemu-sbsa
qemu-x86
qemu-xtensa
+
+Also see
+
+* :doc:`../../usage/semihosting`
diff --git a/doc/board/emulation/qemu-sbsa.rst b/doc/board/emulation/qemu-sbsa.rst
new file mode 100644
index 0000000..fe1dc32
--- /dev/null
+++ b/doc/board/emulation/qemu-sbsa.rst
@@ -0,0 +1,98 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2024, Patrick Rudolph <patrick.rudolph@9elements.com>
+
+QEMU ARM SBSA
+=============
+
+QEMU for ARM supports Arm Server Base System Architecture Reference board,
+short 'sbsa-ref' that utilizes ACPI over FDT. This document describes how to run
+U-Boot under it. Only AArch64 is supported.
+
+The 'sbsa' platform provides the following as the basic functionality:
+
+ - A freely configurable amount of CPU cores
+ - U-Boot loaded and executing in the emulated flash at address 0x10000000
+ - No device tree blob
+ - A freely configurable amount of RAM
+ - A PL011 serial port
+ - An ARMv7/ARMv8 architected timer
+ - PSCI for rebooting the system
+ - A generic ECAM-based PCI host controller
+
+Additionally, a number of optional peripherals can be added to the PCI bus.
+
+Compile ARM Trusted Firmware (ATF)
+----------------------------------
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/ARM-software/arm-trusted-firmware
+
+.. code-block:: bash
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
+ cd tfa
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ ARM_LINUX_KERNEL_AS_BL33=1 DEBUG=1 PLAT=qemu_sbsa
+
+Copy the resulting FIP and BL1 binary
+
+.. code-block:: bash
+
+ cp build/qemu_sbsa/debug/fip.bin ../
+ cp build/qemu_sbsa/debug/bl1.bin ../
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+.. code-block:: bash
+
+ make qemu-arm-sbsa_defconfig
+ make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+.. code-block:: bash
+
+ qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
+ -pflash secure-world.rom \
+ -pflash unsecure-world.rom
+
+Note that for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
+ensures that output appears on the terminal. Use Ctrl-A X to quit.
+
+Booting distros
+---------------
+
+It is possible to install and boot a standard Linux distribution using
+sbsa by setting up a root disk::
+
+.. code-block:: bash
+
+ qemu-img create root.img 20G
+
+then using the installer to install. For example, with Debian 12::
+
+.. code-block:: bash
+
+ qemu-system-aarch64 \
+ -machine sbsa-ref -cpu cortex-a57 -m 4G -smp 4 \
+ -pflash secure-world.rom \
+ -pflash unsecure-world.rom \
+ -device virtio-rng-pci \
+ -device usb-kbd -device usb-tablet \
+ -cdrom debian-12.0.0-arm64-netinst.iso \
+ -hda root.img
+
+Debug UART
+----------
+
+The debug UART on the ARM sbsa board uses these settings::
+
+ CONFIG_DEBUG_UART=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 3fb7c84..ca5246e 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -24,6 +24,7 @@
cloos/index
congatec/index
coreboot/index
+ emcraft/index
emulation/index
gateworks/index
google/index
diff --git a/doc/board/nxp/imx93_9x9_qsb.rst b/doc/board/nxp/imx93_9x9_qsb.rst
new file mode 100644
index 0000000..e4dfe47
--- /dev/null
+++ b/doc/board/nxp/imx93_9x9_qsb.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx93_9x9_qsb
+=======================
+
+U-Boot for the NXP i.MX93 Quick Start Board
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.10
+
+.. code-block:: bash
+
+ $ unset LDFLAGS
+ $ make PLAT=imx93 bl31
+ $ cp build/imx93/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+ $ chmod +x firmware-imx-8.21.bin
+ $ ./firmware-imx-8.21.bin
+ $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin
+ $ chmod +x firmware-sentinel-0.11.bin
+ $ ./firmware-sentinel-0.11.bin
+ $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx93_9x9_qsb_defconfig or imx93_9x9_qsb_inline_ecc_defconfig
+ $ make
+
+- Inline ECC is to enable DDR ECC feature with imx93_9x9_qsb_inline_ecc_defconfig
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index 5f1e878..734bab6 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -12,6 +12,7 @@
imx8mq_evk
imx8qxp_mek
imx8ulp_evk
+ imx93_9x9_qsb
imx93_11x11_evk
imxrt1020-evk
imxrt1050-evk
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 86d83be..7b11a2e 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -98,6 +98,7 @@
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
+ - Hardkernel ODROID-M1S (odroid-m1s-rk3566)
- Pine64 PineTab2 (pinetab2-rk3566)
- Pine64 Quartz64-A Board (quartz64-a-rk3566)
- Pine64 Quartz64-B Board (quartz64-b-rk3566)
@@ -132,6 +133,7 @@
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
- Generic RK3588S/RK3588 (generic-rk3588)
+ - Hardkernel ODROID-M2 (odroid-m2-rk3588s)
- Indiedroid Nova (nova-rk3588s)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index ee3c5c9..37b23f6 100644
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -8,7 +8,9 @@
AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced
variant is prepared for secure boot. M.2 Variant also uses the AM6548 HS.
Instead of a MiniPCI connector, it comes with two M.2 connectors and can
-support 5G/WIFI/BT applications or connect an SSD.
+support 5G/WIFI/BT applications or connect an SSD. Compared with the AM6548
+Advanced variant, SM variant removes the Arduino interface, and adds a new
+ASIC for communicating with the PLC 1200 signal modules.
The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader
called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and
@@ -29,6 +31,9 @@
- seboot_pg1.bin
- seboot_pg2.bin
+Note that SE-Boot D/V01.04.01.02 or greater is required, otherwise the DDR size
+will not be picked up correctly by U-Boot.
+
When using the watchdog, a related firmware for the R5 core(s) is needed, e.g.
https://github.com/siemens/k3-rti-wdt. The name and location of the image is
configured via CONFIG_WDT_K3_RTI_FW_FILE.
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index 63b4477..8cf7129 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -180,35 +180,54 @@
STM32MP15x device Tree Selection
````````````````````````````````
-The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig) are:
+The supported device trees for STM32MP15x (**stm32mp15_defconfig** for TF-A_
+with FIP support) are:
+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
+ + **stm32mp157c-ev1-scmi**
+ stm32mp157c-ev1
+ ed1: daughter board with pmic stpmic1
+ + **stm32mp157c-ed1-scmi**
+ stm32mp157c-ed1
+ dk1: Discovery board
+ + **stm32mp157a-dk1-scmi**
+ stm32mp157a-dk1
+ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
+ + **stm32mp157c-dk2-scmi**
+ stm32mp157c-dk2
+The scmi variant of each device tree is only supported with OP-TEE as secure
+monitor and it is the configuration **recommended** by STMicroelectronics for
+product, with secured system resources (RCC_TZCR.TZEN=1).
+
+The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig
+TF-A without FIP support and stm32mp15_basic_defconfig with SPL) are:
+
++ the same STMicroelectronics boards with the no scmi device tree files:
+
+ + stm32mp157c-ev1
+ + stm32mp157c-ed1
+ + stm32mp157a-dk1
+ + stm32mp157c-dk2
+
+ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM
+ stm32mp15xx-dhcor-avenger96
STM32MP13x device Tree Selection
````````````````````````````````
-The supported device trees for STM32MP13x (stm32mp13_defconfig) are:
+The supported device trees for STM32MP13x (**stm32mp13_defconfig**) are:
+ dk: Discovery board
- + stm32mp135f-dk
+ + **stm32mp135f-dk**
Build Procedure
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 51dab83..dab2970 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -305,6 +305,10 @@
- 00000000
- 11001010
+ * - Ethernet
+ - 00110000
+ - 11000100
+
For SW2 and SW1, the switch state in the "ON" position = 1.
DFU based boot
@@ -330,6 +334,198 @@
.. am62x_evm_rst_include_end_dfu_boot
+Ethernet based boot
+-------------------
+
+To boot the board via Ethernet, configure the BOOT MODE pins for Ethernet boot.
+
+On powering on the device, ROM uses the Ethernet Port corresponding to CPSW3G's MAC
+Port 1 to transmit "TI K3 Bootp Boot".
+
+The TFTP server and DHCP server on the receiver device need to be configured such
+that VCI string "TI K3 Bootp Boot" maps to the file `tiboot3.bin` and the TFTP
+server should be capable of transferring it to the device.
+
+**Configuring DHCP server includes following steps:**
+
+* Install DHCP server:
+
+.. prompt:: bash $
+
+ sudo apt install isc-dhcp-server
+
+* Disable services before configuring:
+
+.. prompt:: bash $
+
+ sudo systemctl disable --now isc-dhcp-server.service isc-dhcp-server6.service
+
+* DHCP server setup
+
+Run the ip link or ifconfig command to find the name of your network interface:
+
+Example
+
+.. code-block::
+
+ eno1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
+ inet 172.24.145.229 netmask 255.255.254.0 broadcast 172.24.145.255
+ inet6 fe80::bbd5:34c8:3d4c:5de4 prefixlen 64 scopeid 0x20<link>
+ ether c0:18:03:bd:b1:a6 txqueuelen 1000 (Ethernet)
+ RX packets 2733979 bytes 1904440459 (1.9 GB)
+ RX errors 0 dropped 3850 overruns 0 frame 0
+ TX packets 796807 bytes 84534764 (84.5 MB)
+ TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
+ device interrupt 16 memory 0xe2200000-e2220000
+
+ enxf8e43b8cffe8: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
+ ether f8:e4:3b:8c:ff:e8 txqueuelen 1000 (Ethernet)
+ RX packets 95 bytes 31160 (31.1 KB)
+ RX errors 0 dropped 0 overruns 0 frame 0
+ TX packets 89 bytes 17445 (17.4 KB)
+ TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
+
+ lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
+ inet 127.0.0.1 netmask 255.0.0.0
+ inet6 ::1 prefixlen 128 scopeid 0x10<host>
+ loop txqueuelen 1000 (Local Loopback)
+ RX packets 85238 bytes 7244462 (7.2 MB)
+ RX errors 0 dropped 0 overruns 0 frame 0
+ TX packets 85238 bytes 7244462 (7.2 MB)
+ TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
+
+Suppose we are using enxf8e43b8cffe8 interface, one end of it is connected to host PC
+and other to board.
+
+* Do the following changes in /etc/dhcp/dhcpd.conf in host PC.
+
+.. code-block::
+
+ subnet 192.168.0.0 netmask 255.255.254.0
+ {
+ range dynamic-bootp 192.168.0.2 192.168.0.5;
+ if substring (option vendor-class-identifier, 0, 16) = "TI K3 Bootp Boot"
+ {
+ filename "tiboot3.bin";
+ } elsif substring (option vendor-class-identifier, 0, 20) = "AM62X U-Boot R5 SPL"
+ {
+ filename "tispl.bin";
+ } elsif substring (option vendor-class-identifier, 0, 21) = "AM62X U-Boot A53 SPL"
+ {
+ filename "u-boot.img";
+ }
+ default-lease-time 60000;
+ max-lease-time 720000;
+ next-server 192.168.0.1;
+ }
+
+* Do following changes in /etc/default/isc-dhcp-server
+
+.. code-block::
+
+ DHCPDv4_CONF=/etc/dhcp/dhcpd.conf
+ INTERFACESv4="enxf8e43b8cffe8"
+ INTERFACESv6=""
+
+* For your interface change ip address and netmask to next-server and your netmask
+
+.. prompt:: bash $
+
+ sudo ifconfig enxf8e43b8cffe8 192.168.0.1 netmask 255.255.254.0
+
+* Enable DHCP
+
+.. prompt:: bash $
+
+ sudo systemctl enable --now isc-dhcp-server
+
+* To see if there is any configuration error or if dhcp is running run
+
+.. prompt:: bash $
+
+ sudo service isc-dhcp-server status
+ # If it shows error then something is wrong with configuration
+
+**For TFTP setup follow below steps:**
+
+* Install TFTP server:
+
+.. prompt:: bash $
+
+ sudo apt install tftpd-hpa
+
+tftpd-hpa package should be installed.
+
+Now, check whether the tftpd-hpa service is running with the following command:
+
+.. prompt:: bash $
+
+ sudo systemctl status tftpd-hpa
+
+* Configuring TFTP server:
+
+The default configuration file of tftpd-hpa server is /etc/default/tftpd-hpa.
+If you want to configure the TFTP server, then you have to modify this configuration
+file and restart the tftpd-hpa service afterword.
+
+To modify the /etc/default/tftpd-hpa configuration file, run the following command
+
+.. prompt:: bash $
+
+ sudo vim /etc/default/tftpd-hpa
+
+Configuration file may contain following configuration options by default:
+
+.. code-block::
+
+ # /etc/default/tftpd-hpa
+
+ TFTP_USERNAME="tftp"
+ TFTP_DIRECTORY="/var/lib/tftpboot"
+ TFTP_ADDRESS=":69"
+ TFTP_OPTIONS="--secure"
+
+Now change the **TFTP_DIRECTORY** to **/tftp** and add the **--create** option to the
+**TFTP_OPTIONS**. Without the **--create** option, you won't be able to create or upload
+new files to the TFTP server. You will only be able to update existing files.
+
+After above changes /etc/default/tftpd-hpa file would look like this:
+
+.. code-block::
+
+ # /etc/default/tftpd-hpa
+
+ TFTP_USERNAME="tftp"
+ TFTP_DIRECTORY="/tftp"
+ TFTP_ADDRESS=":69"
+ TFTP_OPTIONS="--secure --create"
+
+Since we have configured tftp directory as /tftp, put tiboot3.bin, tispl.bin
+and u-boot.img after building it using sdk or manually cloning all the repos.
+
+To build binaries use following defconfig files:
+
+.. code-block::
+
+ am62x_evm_r5_ethboot_defconfig
+ am62x_evm_a53_ethboot_defconfig
+
+`tiboot3.bin` is expected to be built from `am62x_evm_r5_ethboot_defconfig` and
+`tispl.bin` and `u-boot.img` are expected to be built from
+`am62x_evm_a53_ethboot_defconfig`.
+
+Images should get fetched in following sequence as a part of boot procedure:
+
+.. code-block::
+
+ tiboot3.bin => tispl.bin => u-boot.img
+
+ROM loads and executes `tiboot3.bin` provided by the TFTP server.
+
+Next, based on NET_VCI_STRING string mentioned in respective defconfig file `tiboot3.bin`
+fetches `tispl.bin` and then `tispl.bin` fetches `u-boot.img` from TFTP server which
+completes Ethernet boot on the device.
+
Debugging U-Boot
----------------
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index c3513f0..5d01f48 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -32,19 +32,22 @@
am62ax_sk
am62x_sk
- ../beagle/am62x_beagleplay
- ../phytec/phycore-am62x
- ../toradex/verdin-am62
am62px_sk
am64x_evm
am65x_evm
j7200_evm
- ../beagle/j721e_beagleboneai64
j721e_evm
j721s2_evm
j722s_evm
j784s4_evm
+K3 SoC based boards in other sections
+
+* :doc:`../beagle/am62x_beagleplay`
+* :doc:`../beagle/j721e_beagleboneai64`
+* :doc:`../phytec/phycore-am62x`
+* :doc:`../toradex/verdin-am62`
+
Boot Flow Overview
------------------
diff --git a/doc/develop/binman_tests.rst b/doc/develop/binman_tests.rst
new file mode 100644
index 0000000..a632694
--- /dev/null
+++ b/doc/develop/binman_tests.rst
@@ -0,0 +1,734 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. toctree::
+ :maxdepth: 1
+
+Binman Tests
+============
+
+.. contents::
+ :depth: 2
+ :local:
+
+There is some material on writing tests in the main Binman documentation
+(see :doc:`package/index`). This short guide is separate so people don't
+feel they have to read as much.
+
+Code and output is mostly included verbatim, which makes the doc longer, but
+avoids its becoming confusing when the output or referenced code changes in the
+future.
+
+Purpose
+-------
+
+The main purpose of tests in Binman is to make sure that Binman actually does
+what it is supposed to. Various people contribute code, refactoring is done
+over time, but U-Boot users (developers, SoC vendors, board vendors) rely on
+Binman producing images which function correctly. Without tests, a one-line
+change could unintentionally break a corner-case and the problem might not be
+noticed for months. Debugging an image-generation problem with a board you
+don't have can be very hard.
+
+A secondary purpose is productivity. U-Boot contributors are busy and often
+have too much on their plate. Trying to figure out why their patch broke
+some other vendor's workflow can be very time-consuming and frustrating. By
+building in tests from the start, this is largely avoided. If your change has
+full test coverage and doesn't break any test, all is well and no one can
+complain.
+
+A lessor purpose is to document what Binman actually does. If a test covers a
+feature, it works. If there is no test coverage, no one can say for sure
+whether it works in all expected situations, certainly not wihout manual
+effort.
+
+In fact, strictly speaking it isn't completely clear what 'works' even means in
+the case where these is no test to cover the code. We are often left guessing
+as to what the documentation means, what was actually intended, etc.
+
+Finally, code-coverage helps to remove 'zombie code', copied from elsewhere
+because it looks reasonable, but not actually needed. The same situation arises
+in silicon-chip design, where a part of the chip is not validated. If it isn't
+validated, it can be assumed not to work, either now or later, so it is best to
+remove that logic to avoid it causing problems.
+
+Setting up
+----------
+
+Binman tests use various utility programs. Most of these are documented in
+:doc:`../build/gcc`. But some are SoC-specific. To fetch these, tell Binman to
+fetch or build any missing tools:
+
+.. code-block:: bash
+
+ $ binman tool -f missing
+
+When this completes successfully, you can list the tools. You should see
+something like this:
+
+.. code-block:: bash
+
+ $ binman tool -l
+ Name Version Description Path
+ --------------- ----------- ------------------------- ------------------------------
+ bootgen ****** Bootg Xilinx Bootgen /home/sglass/.binman-tools/bootgen
+ bzip2 1.0.8 bzip2 compression /usr/bin/bzip2
+ cbfstool unknown Manipulate CBFS files /home/sglass/bin/cbfstool
+ fdt_add_pubkey unknown Generate image for U-Boot /home/sglass/bin/fdt_add_pubkey
+ fdtgrep unknown Grep devicetree files /home/sglass/bin/fdtgrep
+ fiptool v2.11.0(rele Manipulate ATF FIP files /home/sglass/.binman-tools/fiptool
+ futility v0.0.1-9f2e9 Chromium OS firmware utili /home/sglass/.binman-tools/futility
+ gzip 1.12 gzip compression /usr/bin/gzip
+ ifwitool unknown Manipulate Intel IFWI file /home/sglass/.binman-tools/ifwitool
+ lz4 v1.9.4 lz4 compression /usr/bin/lz4
+ lzma_alone 9.22 beta lzma_alone compression /usr/bin/lzma_alone
+ lzop v1.04 lzo compression /usr/bin/lzop
+ mkeficapsule 2024.10-rc5- mkeficapsule tool for gene /home/sglass/bin/mkeficapsule
+ mkimage 2024.10-rc5- Generate image for U-Boot /home/sglass/bin/mkimage
+ openssl 3.0.13 30 Ja openssl cryptography toolk /usr/bin/openssl
+ xz 5.4.5 xz compression /usr/bin/xz
+ zstd v1.5.5 zstd compression /usr/bin/zstd
+
+The tools are written to ``~/.binman-tools`` so add that to your ``PATH``.
+It's fine to have some of the tools elsewhere (e.g. ``~/bin``) so long as they
+are up-to-date. This allows you use the version of the tools intended for
+running tests.
+
+Now you should be able to actually run the tests:
+
+.. code-block:: bash
+
+ $ binman test
+ ======================== Running binman tests ========================
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ........
+ ----------------------------------------------------------------------
+ Ran 568 tests in 2.578s
+
+ OK
+
+If this doesn't work, see if you can have some missing tools. Check that the
+dependencies are all there as above. If it is very slow, try installing
+concurrencytest so that the tests run in parallel.
+
+The next thing to set up is code coverage, using the -T flag:
+
+.. code-block:: bash
+
+ $ binman test -T
+ ======================== Running binman tests ========================
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ......................................................................
+ ........
+ ----------------------------------------------------------------------
+ Ran 568 tests in 17.367s
+
+ OK
+
+ 99%
+ Name Stmts Miss Cover
+ ---------------------------------------------------------------------------
+ tools/binman/__init__.py 0 0 100%
+ tools/binman/bintool.py 263 0 100%
+ tools/binman/btool/bootgen.py 21 0 100%
+ tools/binman/btool/btool_gzip.py 5 0 100%
+ tools/binman/btool/bzip2.py 5 0 100%
+ tools/binman/btool/cbfstool.py 24 0 100%
+ tools/binman/btool/cst.py 15 4 73%
+ tools/binman/btool/fdt_add_pubkey.py 21 0 100%
+ tools/binman/btool/fdtgrep.py 26 0 100%
+ tools/binman/btool/fiptool.py 19 0 100%
+ tools/binman/btool/futility.py 19 0 100%
+ tools/binman/btool/ifwitool.py 22 0 100%
+ tools/binman/btool/lz4.py 22 0 100%
+ tools/binman/btool/lzma_alone.py 34 0 100%
+ tools/binman/btool/lzop.py 5 0 100%
+ tools/binman/btool/mkeficapsule.py 27 0 100%
+ tools/binman/btool/mkimage.py 23 0 100%
+ tools/binman/btool/openssl.py 42 0 100%
+ tools/binman/btool/xz.py 5 0 100%
+ tools/binman/btool/zstd.py 5 0 100%
+ tools/binman/cbfs_util.py 376 0 100%
+ tools/binman/cmdline.py 90 0 100%
+ tools/binman/control.py 409 0 100%
+ tools/binman/elf.py 241 0 100%
+ tools/binman/entry.py 548 0 100%
+ tools/binman/etype/alternates_fdt.py 58 0 100%
+ tools/binman/etype/atf_bl31.py 5 0 100%
+ tools/binman/etype/atf_fip.py 67 0 100%
+ tools/binman/etype/blob.py 49 0 100%
+ tools/binman/etype/blob_dtb.py 46 0 100%
+ tools/binman/etype/blob_ext.py 9 0 100%
+ tools/binman/etype/blob_ext_list.py 32 0 100%
+ tools/binman/etype/blob_named_by_arg.py 9 0 100%
+ tools/binman/etype/blob_phase.py 22 0 100%
+ tools/binman/etype/cbfs.py 101 0 100%
+ tools/binman/etype/collection.py 30 0 100%
+ tools/binman/etype/cros_ec_rw.py 5 0 100%
+ tools/binman/etype/efi_capsule.py 59 0 100%
+ tools/binman/etype/efi_empty_capsule.py 33 0 100%
+ tools/binman/etype/encrypted.py 34 0 100%
+ tools/binman/etype/fdtmap.py 62 0 100%
+ tools/binman/etype/files.py 35 0 100%
+ tools/binman/etype/fill.py 13 0 100%
+ tools/binman/etype/fit.py 311 0 100%
+ tools/binman/etype/fmap.py 37 0 100%
+ tools/binman/etype/gbb.py 37 0 100%
+ tools/binman/etype/image_header.py 53 0 100%
+ tools/binman/etype/intel_cmc.py 4 0 100%
+ tools/binman/etype/intel_descriptor.py 39 0 100%
+ tools/binman/etype/intel_fit.py 12 0 100%
+ tools/binman/etype/intel_fit_ptr.py 17 0 100%
+ tools/binman/etype/intel_fsp.py 4 0 100%
+ tools/binman/etype/intel_fsp_m.py 4 0 100%
+ tools/binman/etype/intel_fsp_s.py 4 0 100%
+ tools/binman/etype/intel_fsp_t.py 4 0 100%
+ tools/binman/etype/intel_ifwi.py 67 0 100%
+ tools/binman/etype/intel_me.py 4 0 100%
+ tools/binman/etype/intel_mrc.py 6 0 100%
+ tools/binman/etype/intel_refcode.py 6 0 100%
+ tools/binman/etype/intel_vbt.py 4 0 100%
+ tools/binman/etype/intel_vga.py 4 0 100%
+ tools/binman/etype/mkimage.py 84 0 100%
+ tools/binman/etype/null.py 9 0 100%
+ tools/binman/etype/nxp_imx8mcst.py 78 59 24%
+ tools/binman/etype/nxp_imx8mimage.py 38 6 84%
+ tools/binman/etype/opensbi.py 5 0 100%
+ tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py 6 0 100%
+ tools/binman/etype/pre_load.py 76 0 100%
+ tools/binman/etype/rockchip_tpl.py 5 0 100%
+ tools/binman/etype/scp.py 5 0 100%
+ tools/binman/etype/section.py 418 0 100%
+ tools/binman/etype/tee_os.py 31 0 100%
+ tools/binman/etype/text.py 21 0 100%
+ tools/binman/etype/ti_board_config.py 139 0 100%
+ tools/binman/etype/ti_dm.py 5 0 100%
+ tools/binman/etype/ti_secure.py 65 0 100%
+ tools/binman/etype/ti_secure_rom.py 117 0 100%
+ tools/binman/etype/u_boot.py 7 0 100%
+ tools/binman/etype/u_boot_dtb.py 9 0 100%
+ tools/binman/etype/u_boot_dtb_with_ucode.py 51 0 100%
+ tools/binman/etype/u_boot_elf.py 19 0 100%
+ tools/binman/etype/u_boot_env.py 27 0 100%
+ tools/binman/etype/u_boot_expanded.py 4 0 100%
+ tools/binman/etype/u_boot_img.py 7 0 100%
+ tools/binman/etype/u_boot_nodtb.py 7 0 100%
+ tools/binman/etype/u_boot_spl.py 8 0 100%
+ tools/binman/etype/u_boot_spl_bss_pad.py 14 0 100%
+ tools/binman/etype/u_boot_spl_dtb.py 9 0 100%
+ tools/binman/etype/u_boot_spl_elf.py 8 0 100%
+ tools/binman/etype/u_boot_spl_expanded.py 12 0 100%
+ tools/binman/etype/u_boot_spl_nodtb.py 8 0 100%
+ tools/binman/etype/u_boot_spl_pubkey_dtb.py 32 0 100%
+ tools/binman/etype/u_boot_spl_with_ucode_ptr.py 8 0 100%
+ tools/binman/etype/u_boot_tpl.py 8 0 100%
+ tools/binman/etype/u_boot_tpl_bss_pad.py 14 0 100%
+ tools/binman/etype/u_boot_tpl_dtb.py 9 0 100%
+ tools/binman/etype/u_boot_tpl_dtb_with_ucode.py 8 0 100%
+ tools/binman/etype/u_boot_tpl_elf.py 8 0 100%
+ tools/binman/etype/u_boot_tpl_expanded.py 12 0 100%
+ tools/binman/etype/u_boot_tpl_nodtb.py 8 0 100%
+ tools/binman/etype/u_boot_tpl_with_ucode_ptr.py 12 0 100%
+ tools/binman/etype/u_boot_ucode.py 33 0 100%
+ tools/binman/etype/u_boot_vpl.py 8 0 100%
+ tools/binman/etype/u_boot_vpl_bss_pad.py 14 0 100%
+ tools/binman/etype/u_boot_vpl_dtb.py 9 0 100%
+ tools/binman/etype/u_boot_vpl_elf.py 8 0 100%
+ tools/binman/etype/u_boot_vpl_expanded.py 12 0 100%
+ tools/binman/etype/u_boot_vpl_nodtb.py 8 0 100%
+ tools/binman/etype/u_boot_with_ucode_ptr.py 42 0 100%
+ tools/binman/etype/vblock.py 38 0 100%
+ tools/binman/etype/x86_reset16.py 7 0 100%
+ tools/binman/etype/x86_reset16_spl.py 7 0 100%
+ tools/binman/etype/x86_reset16_tpl.py 7 0 100%
+ tools/binman/etype/x86_start16.py 7 0 100%
+ tools/binman/etype/x86_start16_spl.py 7 0 100%
+ tools/binman/etype/x86_start16_tpl.py 7 0 100%
+ tools/binman/etype/x509_cert.py 71 0 100%
+ tools/binman/etype/xilinx_bootgen.py 72 0 100%
+ tools/binman/fip_util.py 202 0 100%
+ tools/binman/fmap_util.py 49 0 100%
+ tools/binman/image.py 181 0 100%
+ tools/binman/state.py 201 0 100%
+ ---------------------------------------------------------------------------
+ TOTAL 5954 69 99%
+
+ To get a report in 'htmlcov/index.html', type: python3-coverage html
+ Coverage error: 99%, but should be 100%
+ ValueError: Test coverage failure
+
+Unfortunately the run failed. As it suggests, create a report:
+
+.. code-block:: bash
+
+ $ python3-coverage html
+ Wrote HTML report to htmlcov/index.html
+
+If you open that file in the browser, you can see which files are not reaching
+100% and click on them. Here is ``nxp_imx8mimage.py``, for example:
+
+.. code-block:: python
+
+ 43 # Generate mkimage configuration file similar to imx8mimage.cfg
+ 44 # and pass it to mkimage to generate SPL image for us here.
+ 45 cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq)
+ 46 with open(cfg_fname, 'w') as outf:
+ 47 print('ROM_VERSION v%d' % self.rom_version, file=outf)
+ 48 print('BOOT_FROM %s' % self.boot_from, file=outf)
+ 49 print('LOADER %s %#x' % (input_fname, self.loader_address), file=outf)
+ 50
+ 51 output_fname = tools.get_output_filename(f'cfg-out.{uniq}')
+ 52 args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage',
+ 53 output_fname]
+ 54 if self.mkimage.run_cmd(*args) is not None:
+ 55 return tools.read_file(output_fname)
+ 56 else:
+ 57 # Bintool is missing; just use the input data as the output
+ 58 x self.record_missing_bintool(self.mkimage)
+ 59 x return data
+ 60
+ 61 def SetImagePos(self, image_pos):
+ 62 # Customized SoC specific SetImagePos which skips the mkimage etype
+ 63 # implementation and removes the 0x48 offset introduced there. That
+ 64 # offset is only used for uImage/fitImage, which is not the case in
+ 65 # here.
+ 66 upto = 0x00
+ 67 for entry in super().GetEntries().values():
+ 68 x entry.SetOffsetSize(upto, None)
+ 69
+ 70 # Give up if any entries lack a size
+ 71 x if entry.size is None:
+ 72 x return
+ 73 x upto += entry.size
+ 74
+ 75 Entry_section.SetImagePos(self, image_pos)
+
+Most of the file is covered, but the lines marked with ``x`` indicate missing
+coverage. The will show up red in your browser.
+
+What is a test?
+---------------
+
+A test is a function in ``ftest.py`` which uses an image description in
+``tools/binman/test`` to perform some operations and exercise the code. Some
+tests are just a few lines; some are more complicated.
+
+Here is a simple test:
+
+.. code-block:: python
+
+ def testSimple(self):
+ """Test a simple binman with a single file"""
+ data = self._DoReadFile('005_simple.dts')
+ self.assertEqual(U_BOOT_DATA, data)
+
+This test tells Binman to build an image using the description. Then it checks
+that the resulting image looks correct. The image description is:
+
+.. code-block:: devicetree
+
+ /dts-v1/;
+
+ / {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ };
+ };
+
+As you will know from the Binman documentation, this says that there is
+one image and it contains the U-Boot binary. So this test builds an image
+consisting of a U-Boot binary, then checks that it does indeed have just a
+U-Boot binary in it.
+
+Test data
+---------
+
+Using real binaries (like ``u-boot.bin``) to test Binman would be quite tedious.
+Every output file would be large and it would be hard to tell by looking at the
+output (e.g. with a hex dump) if a particular entry contains ``u-boot.bin`` or
+``u-boot-spl.bin`` or something else.
+
+Binman gets around this by using simple placeholders. Here is the placeholder
+for u-boot.bin:
+
+.. code-block:: python
+
+ U_BOOT_DATA = b'1234'
+
+This is just bytes. So the test above checks that the output image contains
+these four bytes. This makes verification fast for Binman and very easy for
+humans.
+
+Even the devicetree is a placeholder:
+
+.. code-block:: python
+
+ U_BOOT_DTB_DATA = b'udtb'
+
+But for some tests you need to use the real devicetree. In that case you can
+use ``_DoReadFileRealDtb()``. See ``testUpdateFdtAll()`` for an example of how
+to check the devicetree updated by Binman.
+
+Test structure
+--------------
+
+Each test is designed to test just one thing. Binman tests are named according
+to what they are testing. Individually they don't do very much, but as a whole
+they test every line of code in Binman.
+
+So ``testSimple()`` is designed to check that Binman can build the
+simplest-possible image that isn't completely empty.
+
+Another type of test is one which checks error-handling, for example:
+
+.. code-block:: python
+
+ def testFillNoSize(self):
+ """Test for an fill entry type with no size"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('070_fill_no_size.dts')
+ self.assertIn("'fill' entry is missing properties: size",
+ str(e.exception))
+
+This test deliberately tries to provoke an error. The image description is:
+
+.. code-block:: devicetree
+
+ // SPDX-License-Identifier: GPL-2.0+
+ /dts-v1/;
+
+ / {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+ fill {
+ fill-byte = [ff];
+ };
+ };
+ };
+
+You can see that there is no size for the 'fill' entry, so we would expect
+Binman to complain. The test checks that it actually does. It also checks the
+error message produced by Binman. Sometimes you need to add several tests, each
+with their own broken image description, in order to check all the error cases.
+
+Sometimes you need to capture the console output of Binman, to check it is
+correct. You can to this with ``test_util.capture_sys_output()``, for example:
+
+.. code-block:: python
+
+ with test_util.capture_sys_output() as (_, stderr):
+ self._DoTestFile('071_gbb.dts', force_missing_bintools='futility',
+ entry_args=entry_args)
+ err = stderr.getvalue()
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
+
+The test collects the output and checks it with a regular expression. If you
+need to see the test output (e.g. to debug it), you will have to remove that
+capture line.
+
+How to add a new test
+---------------------
+
+This section explains the process of writing a new test. It uses an example to
+help with this, but your code will be different.
+
+Generally you are adding a test because you are adding a new entry type
+('etype'). So start by creating the shortest and simplest image-description you
+can, which contains the new etype. Put it in a numbered file in
+``tool/binman/test`` so that it comes last. All the numbers are unique and there
+are no gaps.
+
+Example from ``tools/binman/test/339_nxp_imx8.dts``:
+
+.. code-block:: devicetree
+
+ // SPDX-License-Identifier: GPL-2.0+
+
+ /dts-v1/;
+
+ / {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ nxp-imx8mimage {
+ args; /* TODO: Needed by mkimage etype superclass */
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <0x10>;
+ };
+ };
+ };
+
+Note that you should use tabs in the file, not spaces. You can see that this has
+been cut down to the bare minimum, just enough to include the etype and the
+arguments it needs. This is of course not a real image. It will not boot on
+anything. But that's fine; we are just trying to test this one etype. Try not
+to add any other sections and etypes unless they are absolutely essential for
+your test to work. This helps others too: they don't need to understand the full
+complexity of your etype just to read your test.
+
+Then create your test by adding a new function at the end of ``ftest.py``:
+
+.. code-block:: python
+
+ def testNxpImx8Image(self):
+ """Test that binman can produce an iMX8 image"""
+ self._DoTestFile('339_nxp_imx8.dts')
+
+This uses the test file that you created. It doesn't check anything, it just
+runs the image description through binman.
+
+Let's run it:
+
+.. code-block:: bash
+
+ $ binman test testNxpImx8Image
+ ======================== Running binman tests ========================
+ .
+ ----------------------------------------------------------------------
+ Ran 1 test in 0.242s
+
+ OK
+
+So the test passes. It doesn't really do a lot, but it does exercise the etype.
+The next step is to update it to actually check the output:
+
+.. code-block:: python
+
+ def testNxpImx8Image(self):
+ """Test that binman can produce an iMX8 image"""
+ data = self._DoReadFile('339_nxp_imx8.dts')
+ print('data', len(data))
+
+The ``_DoReadFile()`` function is documented in the code. It returns the image
+contents as the first part of a tuple.
+
+Running this we see:
+
+.. code-block:: bash
+
+ data 2200
+
+So it is producing a little over 8K of data. Your etype will be different, but
+in any case you can add Python code to check that this data is actually correct,
+based on your knowledge of your etype. Note that you should not be checking
+whether the external tools (called 'bintools' in Binman) are actually working,
+since presumably they have their own tests. You just need to check that the
+image seems reasonable, e.g. is not empty, contains the expected sections, etc.
+
+When your etype does use a bintool, it also needs tests, but generally it will
+be tested by virtue of the etype test. This is because your etype must call the
+bintool to create the image. Sometimes you might need to add a test for a
+bintool error-condition, though.
+
+Finishing code coverage
+-----------------------
+
+The objective is to have test-coverage for every line of code that you add to
+Binman. So how can you tell? First, get a coverage report as described above.
+Look through the output for any files which are not at 100%. Add more test cases
+(image descriptions and new functions in ``ftest.py``) until you have covered
+each line.
+
+In the above example, here are some possible steps:
+
+#. The first red bit is where the ``mkimage`` call returns None. This can be
+ traced to ``Bintoolmkimage.mkimage()`` which calls
+ ``Bintool.run_cmd_result()`` and ``None`` means that ``mkimage`` is missing.
+ So the etype has code to handle that case, but it is never used. You can
+ look for other examples of ``self.mkimage`` returning ``None`` - e.g.
+ ``Entry_mkimage.BuildSectionData()`` does this. The clue for finding this is
+ that the ``nxp-imx8mimage`` etype is based on ``Entry_mkimage``:
+
+ .. code-block:: python
+
+ class Entry_nxp_imx8mimage(Entry_mkimage):
+
+ It must be tested somewhere...in this case ``testMkimage()`` doesn't do it,
+ but ``testMkimageMissing()`` immediately below that does. So you can create a
+ similar test, e.g.:
+
+ .. code-block:: python
+
+ def testNxpImx8ImageMkimageMissing(self):
+ """Test that binman can produce an iMX8 image"""
+ with test_util.capture_sys_output() as (_, stderr):
+ self._DoTestFile('339_nxp_imx8.dts',
+ force_missing_bintools='mkimage')
+ err = stderr.getvalue()
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage")
+
+ Note that this uses exactly the same image description as the first test.
+ It just checks what happens when the tool is missing. Checking the coverage
+ again, you will see that the first red bit has gone:
+
+ .. code-block:: bash
+
+ $ binman test -T
+ $ python3-coverage html
+
+#. The second red bit is for ``SetImagePos()``. You can see that it is iterating
+ through the sub-entries inside the ``nxp-imx8mimage`` entry. In the case of
+ the 339 file, there are no such entries, so this code inside the for() loop
+ isn't used:
+
+ .. code-block:: python
+
+ def SetImagePos(self, image_pos):
+ # Customized SoC specific SetImagePos which skips the mkimage etype
+ # implementation and removes the 0x48 offset introduced there. That
+ # offset is only used for uImage/fitImage, which is not the case in
+ # here.
+ upto = 0x00
+ for entry in super().GetEntries().values():
+ entry.SetOffsetSize(upto, None)
+
+ # Give up if any entries lack a size
+ if entry.size is None:
+ return
+ upto += entry.size
+
+ Entry_section.SetImagePos(self, image_pos)
+
+ The solution is to add an entry, e.g. in ``340_nxp_imx8_non_empty.dts``:
+
+ .. code-block:: devicetree
+
+ // SPDX-License-Identifier: GPL-2.0+
+
+ /dts-v1/;
+
+ / {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ nxp-imx8mimage {
+ args; /* TODO: Needed by mkimage etype superclass */
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <0x10>;
+
+ u-boot {
+ };
+ };
+ };
+ };
+
+ Now write a little test to use it:
+
+ .. code-block:: python
+
+ def testNxpImx8ImageNonEmpty(self):
+ """Test that binman can produce an iMX8 image with something in it"""
+ data = self._DoReadFile('340_nxp_imx8_non_empty.dts')
+ # check data here
+
+ With that, the second red bit goes away, because the for() loop is now used.
+
+#. There is one more red bit left, the ``return`` in ``SetImagePos()``. The
+ above effort got the for() loop to be executed, but it doesn't cover the
+ ``return``. It might have been copied from some other etype, e.g. the mkimage
+ one. See ``Entry_mkimage.SetImagePos()`` which contains the code:
+
+ .. code-block:: python
+
+ for entry in self.GetEntries().values():
+ entry.SetOffsetSize(upto, None)
+
+ # Give up if any entries lack a size
+ if entry.size is None:
+ return
+ upto += entry.size
+
+ But which test covers that code for mkimage? By figuring that out, you could
+ use a similar technique. One way to find out is to delete the two lines in
+ ``Entry_mkimage`` which check for entry.size being None and returning, then
+ see what breaks with ``binman test``:
+
+ .. code-block:: bash
+
+ ERROR: binman.ftest.TestFunctional.testMkimageCollection (subunit.RemotedTestCase)
+ binman.ftest.TestFunctional.testMkimageCollection
+ ----------------------------------------------------------------------
+ testtools.testresult.real._StringException: Traceback (most recent call last):
+ TypeError: unsupported operand type(s) for +=: 'int' and 'NoneType'
+
+ ======================================================================
+ ERROR: binman.ftest.TestFunctional.testMkimageImage (subunit.RemotedTestCase)
+ binman.ftest.TestFunctional.testMkimageImage
+ ----------------------------------------------------------------------
+ testtools.testresult.real._StringException: Traceback (most recent call last):
+ TypeError: unsupported operand type(s) for +=: 'int' and 'NoneType'
+
+ ======================================================================
+ ERROR: binman.ftest.TestFunctional.testMkimageSpecial (subunit.RemotedTestCase)
+ binman.ftest.TestFunctional.testMkimageSpecial
+ ----------------------------------------------------------------------
+ testtools.testresult.real._StringException: Traceback (most recent call last):
+ TypeError: unsupported operand type(s) for +=: 'int' and 'NoneType'
+
+ We can verify that you got the right test, by putting the lines back in and
+ getting coverage for just that test:
+
+ .. code-block:: bash
+
+ binman test -T testMkimageCollection
+ python3-coverage html
+
+ You will see a lot of red since we are seeing test coverage just for one
+ test, but if you look in ``mkimage.py`` at ``SetImagePos()`` you will see
+ that the ``return`` is covered (i.e. it is marked green).
+
+ Looking at the ``.dts`` files for each of these tests, none jumps out as
+ being relevant to our case. It seems that this code just isn't needed, so the
+ best solution is to delete those two lines from the function:
+
+ .. code-block:: python
+
+ def SetImagePos(self, image_pos):
+ # Customized SoC specific SetImagePos which skips the mkimage etype
+ # implementation and removes the 0x48 offset introduced there. That
+ # offset is only used for uImage/fitImage, which is not the case in
+ # here.
+ upto = 0x00
+ for entry in super().GetEntries().values():
+ entry.SetOffsetSize(upto, None)
+ upto += entry.size
+
+ Entry_section.SetImagePos(self, image_pos)
+
+We should check the updated code on a real build, to make sure it really
+isn't needed, of course.
+
+Now, the test coverage is complete!
+
+If we later discover a case where those lines are needed, we can add the
+lines back, along with a test for this case.
+
+Getting help
+------------
+
+If you are stuck and cannot work out how to add test coverage for your entry
+type, ask on the U-Boot mailing list, cc ``Simon Glass <sjg@chromium.org>`` or
+on irc ``sjg1``
diff --git a/doc/develop/cedit.rst b/doc/develop/cedit.rst
index 82305b9..1ac55ab 100644
--- a/doc/develop/cedit.rst
+++ b/doc/develop/cedit.rst
@@ -94,7 +94,7 @@
enum::
enum {
- ZERO,
+ ID_PROMPT = EXPOID_BASE_ID,
ID_PROMPT,
@@ -130,6 +130,11 @@
in the `.dts` file that is not mentioned in your enum. Check both files and try
again.
+Note that the first ID in your file must be no less that `EXPOID_BASE_ID` since
+IDs before that are reserved. The `expo.py` tool automatically obtains this
+value from the `expo.h` header file, but you must set the first ID to this
+enum value.
+
Use the command interface
-------------------------
@@ -167,4 +172,4 @@
For now, reading and writing settings is not automatic. See the
:doc:`../usage/cmd/cedit` for how to do this on the command line or in a
-script.
+script. For x86 devices, see :ref:`cedit_cb_load`.
diff --git a/doc/develop/cyclic.rst b/doc/develop/cyclic.rst
index 893c269..6f1da6f 100644
--- a/doc/develop/cyclic.rst
+++ b/doc/develop/cyclic.rst
@@ -49,8 +49,8 @@
How is this cyclic functionality integrated / executed?
--------------------------------------------------------
-The cyclic infrastructure integrates the main function responsible for
-calling all registered cyclic functions cyclic_run() into the common
-WATCHDOG_RESET macro. This guarantees that cyclic_run() is executed
-very often, which is necessary for the cyclic functions to get scheduled
-and executed at their configured periods.
+The cyclic infrastructure integrates cyclic_run(), the main function
+responsible for calling all registered cyclic functions, into the
+common schedule() function. This guarantees that cyclic_run() is
+executed very often, which is necessary for the cyclic functions to
+get scheduled and executed at their configured periods.
diff --git a/doc/develop/driver-model/virtio.rst b/doc/develop/driver-model/virtio.rst
index 8ac9c94..31b94d0 100644
--- a/doc/develop/driver-model/virtio.rst
+++ b/doc/develop/driver-model/virtio.rst
@@ -34,6 +34,7 @@
- qemu_arm_defconfig
- qemu_arm64_defconfig
+ - qemu-arm-sbsa_defconfig
- qemu-riscv32_defconfig
- qemu-riscv64_defconfig
- qemu-x86_defconfig
diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst
index c87b6ec..cc7c361 100644
--- a/doc/develop/expo.rst
+++ b/doc/develop/expo.rst
@@ -88,8 +88,13 @@
handled by allocating space in the enum for a maximum number of items, then
adding the loop count to the enum values to obtain unique IDs.
-Where dynamic IDs are need, use expo_set_dynamic_start() to set the start value,
-so that they are allocated above the starting (enum) IDs.
+Some standard IDs are reserved for certain purposes. These are defined by
+`enum expo_id_t` and start at 1. `EXPOID_BASE_ID` defines the first ID which
+can be used for an expo.
+
+An ID of 0 is invalid. If this is specified in an expo call then a valid
+'dynamic IDs is allocated. Use expo_set_dynamic_start() to set the start
+value, so that they are allocated above the starting (enum) IDs.
All text strings are stored in a structure attached to the expo, referenced by
a text ID. This makes it easier at some point to implement multiple languages or
@@ -176,6 +181,10 @@
menuitem-gap-y
Number of pixels between menu items
+menu-title-margin-x
+ Number of pixels between right side of menu title to the left size of the
+ menu labels
+
Pop-up mode
-----------
@@ -352,6 +361,13 @@
Specifies the ID for each menu item. These are used for checking which item
has been selected.
+item-value
+ type: u32 list, optional
+
+ Specifies the value for each menu item. These are used for saving and
+ loading. If this is omitted the value is its position in the menu (0..n-1).
+ Valid values are positive and negative integers INT_MIN...(INT_MAX - 1).
+
item-label / item-label-id
type: string list / u32 list, required
@@ -413,8 +429,7 @@
/* this comment is parsed by the expo.py tool to insert the values below
enum {
- ZERO,
- ID_PROMPT,
+ ID_PROMPT = EXPOID_BASE_ID,
ID_SCENE1,
ID_SCENE1_TITLE,
@@ -466,6 +481,9 @@
/* IDs for the menu items */
item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
ID_CPU_SPEED_3>;
+
+ /* values for the menu items */
+ item-value = <(-1) 3 6>;
};
power-loss {
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index c23192c..30f7fdb 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -83,6 +83,7 @@
py_testing
tests_writing
tests_sandbox
+ binman_tests
Refactoring
-----------
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 9340e9c..faec644 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -51,10 +51,9 @@
Current Status
--------------
-* U-Boot v2024.10 was released on Mon 07 October 2024.
+* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
-* The Merge Window for the next release (v2025.01) is **open** until the -rc1
- release on Mon 28 October 2024.
+* The Merge Window for the next release (v2025.01) is **closed**.
* The next branch is now **closed**.
@@ -66,9 +65,9 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
+* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
.. * U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
diff --git a/doc/device-tree-bindings/i2c/i2c-gpio.txt b/doc/device-tree-bindings/i2c/i2c-gpio.txt
index b06b829..bb00854 100644
--- a/doc/device-tree-bindings/i2c/i2c-gpio.txt
+++ b/doc/device-tree-bindings/i2c/i2c-gpio.txt
@@ -20,6 +20,8 @@
Run deblocking sequence when the driver gets probed.
* i2c-gpio,scl-output-only;
Set if SCL is an output only
+* i2c-gpio,sda-output-only;
+ Set if SDA is an output only
Example:
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ca2f67a..1177e42 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -22,7 +22,7 @@
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias dinh Dinh Nguyen <dinguyen@kernel.org>
-alias ehristev Eugen Hristev <eugen.hristev@collabora.com>
+alias ehristev Eugen Hristev <eugen.hristev@linaro.org>
alias hs Heiko Schocher <hs@denx.de>
alias freenix Peng Fan <peng.fan@nxp.com>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt
index 40dde59..13e0327 100644
--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -1,25 +1,26 @@
-alabaster==0.7.16
-Babel==2.15.0
-certifi==2024.7.4
-charset-normalizer==3.3.2
-docutils==0.20.1
-idna==3.7
+alabaster==1.0.0
+babel==2.16.0
+certifi==2024.8.30
+charset-normalizer==3.4.0
+docutils==0.21.2
+idna==3.10
imagesize==1.4.1
Jinja2==3.1.4
-MarkupSafe==2.1.5
+MarkupSafe==3.0.2
packaging==24.1
+pip==24.2
Pygments==2.18.0
requests==2.32.3
six==1.16.0
snowballstemmer==2.2.0
-Sphinx==7.3.7
-sphinx-prompt==1.8.0
-sphinx-rtd-theme==2.0.0
-sphinxcontrib-applehelp==1.0.8
-sphinxcontrib-devhelp==1.0.6
-sphinxcontrib-htmlhelp==2.0.5
+Sphinx==8.1.3
+sphinx-prompt==1.9.0
+sphinx-rtd-theme==3.0.1
+sphinxcontrib-applehelp==2.0.0
+sphinxcontrib-devhelp==2.0.0
+sphinxcontrib-htmlhelp==2.1.0
sphinxcontrib-jquery==4.1
sphinxcontrib-jsmath==1.0.1
-sphinxcontrib-qthelp==1.0.7
-sphinxcontrib-serializinghtml==1.1.10
-urllib3==2.2.2
+sphinxcontrib-qthelp==2.0.0
+sphinxcontrib-serializinghtml==2.0.0
+urllib3==2.2.3
diff --git a/doc/usage/blkmap.rst b/doc/usage/blkmap.rst
index 7337ea5..75f736c 100644
--- a/doc/usage/blkmap.rst
+++ b/doc/usage/blkmap.rst
@@ -54,7 +54,7 @@
::
setexpr fileblks ${filesize} + 0x1ff
- setexpr fileblks ${filesize} / 0x200
+ setexpr fileblks ${fileblks} / 0x200
Then we can add a mapping to the start of our device, backed by the
memory at `${loadaddr}`:
diff --git a/doc/usage/cmd/cbcmos.rst b/doc/usage/cmd/cbcmos.rst
new file mode 100644
index 0000000..9395cf1
--- /dev/null
+++ b/doc/usage/cmd/cbcmos.rst
@@ -0,0 +1,45 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+cbcmos
+======
+
+Synopis
+-------
+
+::
+
+ cbcmos check [<dev>]
+ cbcmos update [<dev>]
+
+
+Description
+-----------
+
+This checks or updates the CMOS-RAM checksum value against the CMOS-RAM
+contents. It is used with coreboot, which provides information about where to
+find the checksum and what part of the CMOS RAM it covers.
+
+If `<dev>` is provided then the named real-time clock (RTC) device is used.
+Otherwise the default RTC is used.
+
+Example
+-------
+
+This shows checking and updating a checksum across bytes 38 and 39 of the
+CMOS RAM::
+
+ => rtc read 38 2
+ 00000038: 71 00 q.
+ => cbc check
+ => rtc write 38 66
+ => rtc read 38 2
+ 00000038: 66 00 f.
+ => cbc check
+ Checksum 7100 error: calculated 6600
+ => cbc update
+ Checksum 6600 written
+ => cbc check
+ =>
+
+See also :ref:`cedit_cb_load` which shows an example that includes the
+configuration editor.
diff --git a/doc/usage/cmd/cbsysinfo.rst b/doc/usage/cmd/cbsysinfo.rst
index 80d8ba1..28f61d9 100644
--- a/doc/usage/cmd/cbsysinfo.rst
+++ b/doc/usage/cmd/cbsysinfo.rst
@@ -23,3 +23,102 @@
::
=> cbsysinfo
+ Coreboot table at 500, size 5c4, records 1d (dec 29), decoded to 000000007dce4520, forwarded to 000000007ff9a000
+
+ CPU KHz : 0
+ Serial I/O port: 00000000
+ base : 00000000
+ pointer : 000000007ff9a370
+ type : 1
+ base : 000003f8
+ baud : 0d115200
+ regwidth : 1
+ input_hz : 0d1843200
+ PCI addr : 00000010
+ Mem ranges : 7
+ id: type || base || size
+ 0: 10:table 0000000000000000 0000000000001000
+ 1: 01:ram 0000000000001000 000000000009f000
+ 2: 02:reserved 00000000000a0000 0000000000060000
+ 3: 01:ram 0000000000100000 000000007fe6d000
+ 4: 10:table 000000007ff6d000 0000000000093000
+ 5: 02:reserved 00000000fec00000 0000000000001000
+ 6: 02:reserved 00000000ff800000 0000000000800000
+ option_table: 000000007ff9a018
+ Bit Len Cfg ID Name
+ 0 180 r 0 reserved_memory
+ 180 1 e 4 boot_option 0:Fallback 1:Normal
+ 184 4 h 0 reboot_counter
+ 190 8 r 0 reserved_century
+ 1b8 8 r 0 reserved_ibm_ps2_century
+ 1c0 1 e 1 power_on_after_fail 0:Disable 1:Enable
+ 1c4 4 e 6 debug_level 5:Notice 6:Info 7:Debug 8:Spew
+ 1d0 80 r 0 vbnv
+ 3f0 10 h 0 check_sum
+ CMOS start : 1c0
+ CMOS end : 1cf
+ CMOS csum loc: 3f0
+ VBNV start : ffffffff
+ VBNV size : ffffffff
+ CB version : 4.21-5-g7e6eae9679e3-dirty
+ Extra :
+ Build : Thu Sep 07 14:52:41 UTC 2023
+ Time : 14:52:41
+ Framebuffer : 000000007ff9a410
+ Phys addr : fd000000
+ X res : 0d800
+ X res : 0d600
+ Bytes / line: c80
+ Bpp : 0d32
+ pos/size red 16/8, green 8/8, blue 0/8, reserved 24/8
+ GPIOs : 0
+ id: port polarity val name
+ MACs : 0d10
+ 0: 12:00:00:00:28:00
+ 1: 00:00:00:fd:00:00
+ 2: 20:03:00:00:58:02
+ 3: 80:0c:00:00:20:10
+ 4: 08:00:08:18:08:00
+ 5: 16:00:00:00:10:00
+ 6: 00:d0:fd:7f:00:00
+ 7: 17:00:00:00:10:00
+ 8: 00:e0:fd:7f:00:00
+ 9: 37:00:00:00:10:00
+ Multiboot tab: 0000000000000000
+ CB header : 000000007ff9a000
+ CB mainboard: 000000007ff9a344
+ vendor : 0: Emulation
+ part_number : 10: QEMU x86 i440fx/piix4
+ vboot handoff: 0000000000000000
+ size : 0
+ vdat addr : 0000000000000000
+ size : 0
+ SMBIOS : 7ff6d000
+ size : 8000
+ ROM MTRR : 0
+ Tstamp table: 000000007ffdd000
+ CBmem cons : 000000007ffde000
+ Size : 1fff8
+ Cursor : 3332
+ MRC cache : 0000000000000000
+ ACPI GNVS : 0000000000000000
+ Board ID : ffffffff
+ RAM code : ffffffff
+ WiFi calib : 0000000000000000
+ Ramoops buff: 0
+ size : 0
+ SF size : 0
+ SF sector : 0
+ SF erase cmd: 0
+ FMAP offset : 0
+ CBFS offset : 200
+ CBFS size : 3ffe00
+ Boot media size: 400000
+ MTC start : 0
+ MTC size : 0
+ Chrome OS VPD: 0000000000000000
+ RSDP : 000000007ff75000
+ Unimpl. : 10 37 40
+ =>
+
+Note that "Unimpl." shows tags which U-Boot does not currently implement.
diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst
index 5670805..e54ea20 100644
--- a/doc/usage/cmd/cedit.rst
+++ b/doc/usage/cmd/cedit.rst
@@ -18,6 +18,7 @@
cedit write_env [-v]
cedit read_env [-v]
cedit write_cmos [-v] [dev]
+ cedit cb_load
Description
-----------
@@ -92,6 +93,13 @@
Normally the first RTC device is used to hold the data. You can specify a
different device by name using the `dev` parameter.
+.. _cedit_cb_load:
+
+cedit cb_load
+~~~~~~~~~~~~~
+
+This is supported only on x86 devices booted from coreboot. It creates a new
+configuration editor which can be used to edit CMOS settings.
Example
-------
@@ -107,8 +115,10 @@
/ {
cedit-values {
cpu-speed = <0x00000006>;
+ cpu-speed-value = <0x00000003>;
cpu-speed-str = "2 GHz";
power-loss = <0x0000000a>;
+ power-loss-value = <0x00000000>;
power-loss-str = "Always Off";
};
}
@@ -118,16 +128,23 @@
This shows settings being stored in the environment::
=> cedit write_env -v
- c.cpu-speed=7
+ c.cpu-speed=11
c.cpu-speed-str=2.5 GHz
- c.power-loss=12
- c.power-loss-str=Memory
+ c.cpu-speed-value=3
+ c.power-loss=14
+ c.power-loss-str=Always Off
+ c.power-loss-value=0
+ c.machine-name=my-machine
+ c.cpu-speed=11
+ c.power-loss=14
+ c.machine-name=my-machine
=> print
...
c.cpu-speed=6
c.cpu-speed-str=2 GHz
c.power-loss=10
c.power-loss-str=Always Off
+ c.machine-name=my-machine
...
=> cedit read_env -v
@@ -149,3 +166,71 @@
=> cedit write_cmos rtc@43
=>
+
+This example shows editing coreboot CMOS-RAM settings. A script could be used
+to automate this::
+
+ => cbsysinfo
+ Coreboot table at 500, size 5c4, records 1d (dec 29), decoded to 000000007dce3f40, forwarded to 000000007ff9a000
+
+ CPU KHz : 0
+ Serial I/O port: 00000000
+ base : 00000000
+ pointer : 000000007ff9a370
+ type : 1
+ base : 000003f8
+ baud : 0d115200
+ regwidth : 1
+ input_hz : 0d1843200
+ PCI addr : 00000010
+ Mem ranges : 7
+ id: type || base || size
+ 0: 10:table 0000000000000000 0000000000001000
+ 1: 01:ram 0000000000001000 000000000009f000
+ 2: 02:reserved 00000000000a0000 0000000000060000
+ 3: 01:ram 0000000000100000 000000007fe6d000
+ 4: 10:table 000000007ff6d000 0000000000093000
+ 5: 02:reserved 00000000fec00000 0000000000001000
+ 6: 02:reserved 00000000ff800000 0000000000800000
+ option_table: 000000007ff9a018
+ Bit Len Cfg ID Name
+ 0 180 r 0 reserved_memory
+ 180 1 e 4 boot_option 0:Fallback 1:Normal
+ 184 4 h 0 reboot_counter
+ 190 8 r 0 reserved_century
+ 1b8 8 r 0 reserved_ibm_ps2_century
+ 1c0 1 e 1 power_on_after_fail 0:Disable 1:Enable
+ 1c4 4 e 6 debug_level 5:Notice 6:Info 7:Debug 8:Spew
+ 1d0 80 r 0 vbnv
+ 3f0 10 h 0 check_sum
+ CMOS start : 1c0
+ CMOS end : 1cf
+ CMOS csum loc: 3f0
+ VBNV start : ffffffff
+ VBNV size : ffffffff
+ ...
+ Unimpl. : 10 37 40
+
+Check that the CMOS RAM checksum is correct, then create a configuration editor
+and load the settings from CMOS RAM::
+
+ => cbcmos check
+ => cedit cb
+ => cedit read_cmos
+
+Now run the cedit. In this case the user selected 'save' so `cedit run` returns
+success::
+
+ => if cedit run; then cedit write_cmos -v; fi
+ Write 2 bytes from offset 30 to 38
+ => echo $?
+ 0
+
+Update the checksum in CMOS RAM::
+
+ => cbcmos check
+ Checksum 6100 error: calculated 7100
+ => cbcmos update
+ Checksum 7100 written
+ => cbcmos check
+ =>
diff --git a/doc/usage/cmd/cpuid.rst b/doc/usage/cmd/cpuid.rst
new file mode 100644
index 0000000..cccf926
--- /dev/null
+++ b/doc/usage/cmd/cpuid.rst
@@ -0,0 +1,68 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+ single: cpuid (command)
+
+cpuid command
+=============
+
+Synopsis
+--------
+
+::
+
+ cpuid <op>
+
+Description
+-----------
+
+The cpuid command requests CPU-identification information on x86 CPUs. The
+operation <op> selects what information is returned. Up to four 32-bit registers
+can be update (eax-edx) depending on the operation.
+
+Configuration
+-------------
+
+The cpuid command is only available on x86.
+
+Return value
+------------
+
+The return value $? is 0 (true).
+
+Example
+-------
+
+::
+
+ => cpuid 1
+ eax 00060fb1
+ ebx 00040800
+ ecx 80002001
+ edx 178bfbfd
+
+This shows checking for 64-bit 'long' mode::
+
+ => cpuid 80000000
+ eax 8000000a
+ ebx 68747541
+ ecx 444d4163
+ edx 69746e65
+ => cpuid 80000001
+ eax 00060fb1
+ ebx 00000000
+ ecx 00000007
+ edx 2193fbfd # Bit 29 is set in edx, so long mode is available
+
+On a 32-bit-only CPU::
+
+ => cpuid 80000000
+ eax 80000004
+ ebx 756e6547
+ ecx 6c65746e
+ edx 49656e69
+ => cpuid 80000001
+ eax 00000663
+ ebx 00000000
+ ecx 00000000
+ edx 00000000 # Bit 29 is not set in edx, so long mode is not available
diff --git a/doc/usage/cmd/font.rst b/doc/usage/cmd/font.rst
index a8782546..44a04f5 100644
--- a/doc/usage/cmd/font.rst
+++ b/doc/usage/cmd/font.rst
@@ -13,7 +13,7 @@
font list
font select <name> [<size>]
- font size <size>
+ font size [<size>]
Description
-----------
@@ -34,7 +34,7 @@
font size
~~~~~~~~~
-This changes the font size only.
+This changes the font size only. With no argument it shows the current size.
Examples
--------
@@ -44,6 +44,8 @@
=> font list
nimbus_sans_l_regular
cantoraone_regular
+ => font size
+ 30
=> font size 40
=> font select cantoraone_regular 20
=>
diff --git a/doc/usage/cmd/meminfo.rst b/doc/usage/cmd/meminfo.rst
new file mode 100644
index 0000000..6c94493
--- /dev/null
+++ b/doc/usage/cmd/meminfo.rst
@@ -0,0 +1,128 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+.. index::
+ single: meminfo (command)
+
+meminfo command
+===============
+
+Synopsis
+--------
+
+::
+
+ meminfo
+
+Description
+-----------
+
+The meminfo command shows the amount of memory. If ``CONFIG_CMD_MEMINFO_MAP`` is
+enabled, then it also shows the layout of memory used by U-Boot and the region
+which is free for use by images.
+
+The layout of memory is set up before relocation, within the init sequence in
+``board_init_f()``, specifically the various ``reserve_...()`` functions. This
+'reservation' of memory starts from the top of RAM and proceeds downwards,
+ending with the stack. This results in the maximum possible amount of memory
+being left free for image-loading.
+
+The meminfo command writes the DRAM size, then the rest of its outputs in 5
+columns:
+
+Region
+ Name of the region
+
+Base
+ Base address of the region, i.e. where it starts in memory
+
+Size
+ Size of the region, which may be a little smaller than the actual size
+ reserved, e.g. due to alignment
+
+End
+ End of the region. The last byte of the region is one lower than the address
+ shown here
+
+Gap
+ Gap between the end of this region and the base of the one above
+
+Regions shown are:
+
+video
+ Memory reserved for video framebuffers. This reservation happens in the
+ bind() methods of all video drivers which are present before relocation,
+ so the size depends on that maximum amount of memory which all such drivers
+ want to reserve. This may be significantly greater than the amount actually
+ needed, if the display is ultimately set to a smaller resolution or colour
+ depth than the maximum supported.
+
+code
+ U-Boot's code and Block-Starting Symbol (BSS) region. Before relocation,
+ U-Boot copies its code to a high region and sets up a BSS immediately after
+ that. The size of this region is generally therefore ``__bss_end`` -
+ ``__image_copy_start``
+
+malloc
+ Contains the malloc() heap. The size of this is set by
+ ``CONFIG_SYS_MALLOC_LEN``.
+
+board_info
+ Contains the ``bd_info`` structure, with some information about the current
+ board.
+
+global_data
+ Contains the global-data structure, pointed to by ``gd``. This includes
+ various pointers, values and flags which control U-Boot.
+
+devicetree
+ Contains the flatted devicetree blob (FDT) being used by U-Boot to configure
+ itself and its devices.
+
+bootstage
+ Contains the bootstage records, which keep track of boot time as U-Boot
+ executes. The size of this is determined by
+ ``CONFIG_BOOTSTAGE_RECORD_COUNT``, with each record taking approximately
+ 32 bytes.
+
+bloblist
+ Contains the bloblist, which is a list of tables and other data created by
+ U-Boot while executed. The size of this is determined by
+ ``CONFIG_BLOBLIST_SIZE``.
+
+stack
+ Contains U-Boot's stack, growing downwards from the top. The nominal size of
+ this region is set by ``CONFIG_STACK_SIZE`` but there is no actual limit
+ enforced, so the stack can grow behind that. Images should be loaded lower
+ in memory to avoid any conflict.
+
+free
+ Free memory, which is available for loading images. The base address of
+ this is ``gd->ram_base`` which is generally set by ``CFG_SYS_SDRAM_BASE``.
+
+Example
+-------
+
+This example shows output with both ``CONFIG_CMD_MEMINFO`` and
+``CONFIG_CMD_MEMINFO_MAP`` enabled::
+
+ => meminfo
+ DRAM: 256 MiB
+
+ Region Base Size End Gap
+ ------------------------------------------------
+ video f000000 1000000 10000000
+ code ec3a000 3c5d28 efffd28 2d8
+ malloc 8c38000 6002000 ec3a000 0
+ board_info 8c37f90 68 8c37ff8 8
+ global_data 8c37d80 208 8c37f88 8
+ devicetree 8c33000 4d7d 8c37d7d 3
+ bootstage 8c32c20 3c8 8c32fe8 18
+ bloblist 8c32000 400 8c32400 820
+ stack 7c31ff0 1000000 8c31ff0 10
+ free 0 7c31ff0 7c31ff0 0
+
+
+Return value
+------------
+
+The return value $? is always 0 (true).
diff --git a/doc/usage/cmd/msr.rst b/doc/usage/cmd/msr.rst
new file mode 100644
index 0000000..04ee52c
--- /dev/null
+++ b/doc/usage/cmd/msr.rst
@@ -0,0 +1,61 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+ single: msr (command)
+
+msr command
+===========
+
+Synopsis
+--------
+
+::
+
+ msr read <op>
+ msr write <op> <hi> <lo>
+
+Description
+-----------
+
+The msr command reads and writes machine-status registers (MSRs) on x86 CPUs.
+The information is a 64-bit value split into two parts, <hi> for the top 32
+bits and <lo> for the bottom 32 bits.
+
+The operation <op> selects what information is read or written.
+
+msr read
+~~~~~~~~
+
+This reads an MSR and displays the value obtained.
+
+msr write
+~~~~~~~~~
+
+This writes a value to an MSR.
+
+Configuration
+-------------
+
+The msr command is only available on x86.
+
+Return value
+------------
+
+The return value $? is 0 (true).
+
+Example
+-------
+
+This shows reading msr 0x194 which is MSR_FLEX_RATIO on Intel CPUs::
+
+ => msr read 194
+ 00000000 00011200 # Bits 16 (flex ratio enable) and 20 (lock) are set
+
+This shows adjusting the energy-performance bias on an Intel CPU::
+
+ => msr read 1b0
+ 00000000 00000006 # 6 means 'normal'
+
+ => msr write 1b0 0 f # change to power-save
+ => msr read 1b0
+ 00000000 0000000f
diff --git a/doc/usage/cmd/sb.rst b/doc/usage/cmd/sb.rst
new file mode 100644
index 0000000..37431af
--- /dev/null
+++ b/doc/usage/cmd/sb.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+ single: sbi (command)
+
+sbi command
+===========
+
+Synopsis
+--------
+
+::
+
+ sb handoff
+ sb map
+ sb state
+
+Description
+-----------
+
+The *sb* command is used to display information about sandbox's internal
+operation. See :doc:`/arch/sandbox/index` for more information.
+
+sb handoff
+~~~~~~~~~~
+
+This shows information about any handoff information received from SPL. If
+U-Boot is started from an SPL build, it shows a valid magic number.
+
+sb map
+~~~~~~
+
+This shows any mappings between sandbox's emulated RAM and the underlying host
+address-space.
+
+Fields shown are:
+
+Addr
+ Address in emulated RAM
+
+Mapping
+ Equivalent address in the host address-space. While sandbox requests address
+ ``0x10000000`` from the OS, this is not always available.
+
+Refcnt
+ Shows the number of references to this mapping.
+
+sb state
+~~~~~~~~
+
+This shows basic information about the sandbox state, currently just the
+command-line with which sandbox was started.
+
+Example
+-------
+
+This shows checking for the presence of SPL-handoff information. For this to
+work, ``u-boot-spl`` must be run, with build that enables ``CONFIG_SPL``, such
+as ``sandbox_spl``::
+
+ => sb handoff
+ SPL handoff magic 14f93c7b
+
+This shows output from the *sb map* subcommand, with a single mapping::
+
+ Sandbox memory-mapping
+ Addr Mapping Refcnt
+ ff000000 000056185b46d6d0 2
+
+This shows output from the *sb state* subcommand::
+
+ => sb state
+ Arguments:
+ /tmp/b/sandbox/u-boot -D
+
+Configuration
+-------------
+
+The *sb handoff* command is only supported if CONFIG_HANDOFF is enabled.
diff --git a/doc/usage/cmd/tcpm.rst b/doc/usage/cmd/tcpm.rst
new file mode 100644
index 0000000..eb2c69d
--- /dev/null
+++ b/doc/usage/cmd/tcpm.rst
@@ -0,0 +1,66 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+.. index::
+ single: tcpm (command)
+
+tcpm command
+============
+
+Synopsis
+--------
+
+::
+
+ tcpm dev [devnum]
+ tcpm info
+ tcpm list
+
+Description
+-----------
+
+The tcpm command is used to control USB-PD controllers, also known as TypeC Port Manager (TCPM).
+
+The 'tcpm dev' command shows or set current TCPM device.
+
+ devnum
+ device number to change
+
+The 'tcpm info' command displays the current state of the device
+
+The 'tcpm list' command displays the list available devices.
+
+Examples
+--------
+
+The 'tcpm info' command displays device's status:
+::
+
+ => tcpm info
+ Orientation: normal
+ PD Revision: rev3
+ Power Role: sink
+ Data Role: device
+ Voltage: 20.000 V
+ Current: 2.250 A
+
+The current device can be shown or set via 'tcpm dev' command:
+::
+
+ => tcpm dev
+ TCPM device is not set!
+ => tcpm dev 0
+ dev: 0 @ usb-typec@22
+ => tcpm dev
+ dev: 0 @ usb-typec@22
+
+The list of available devices can be shown via 'tcpm list' command:
+::
+
+ => tcpm list
+ | ID | Name | Parent name | Parent uclass @ seq
+ | 0 | usb-typec@22 | i2c@feac0000 | i2c @ 4 | status: 0
+
+Configuration
+-------------
+
+The tcpm command is only available if CONFIG_CMD_TCPM=y.
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index cc33d3e..7bd9ffc 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -323,6 +323,11 @@
Useful on scripts which control the retry operation
themselves.
+rng_seed_size
+ Size of random value added to device-tree node /chosen/rng-seed.
+ This variable is given as a decimal number.
+ If unset, 64 bytes is used as the default.
+
silent_linux
If set then Linux will be told to boot silently, by
adding 'console=' to its command line. If "yes" it will be
diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst
index b5097d4..280eff7 100644
--- a/doc/usage/fit/howto.rst
+++ b/doc/usage/fit/howto.rst
@@ -57,14 +57,9 @@
multiple /configurations subnodes. The required images must be enumerated in
the "loadables" property as a list of strings.
-If a platform specific image source file (.its) is shipped with the U-Boot
-source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol.
-In this case it will be automatically used by U-Boot's Makefile to generate
-the image.
-If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR
-can point to a script which generates this image source file during
-the build process. It gets passed a list of device tree files (taken from the
-CONFIG_OF_LIST symbol).
+CONFIG_SPL_FIT_GENERATOR can point to a script which generates this image source
+file during the build process. It gets passed a list of device tree files (taken
+from the CONFIG_OF_LIST symbol).
The SPL also records to a DT all additional images (called loadables) which are
loaded. The information about loadables locations is passed via the DT node with
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 7056337..cb7a23f 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -43,6 +43,7 @@
cmd/bootz
cmd/button
cmd/cat
+ cmd/cbcmos
cmd/cbsysinfo
cmd/cedit
cmd/cli
@@ -52,6 +53,7 @@
cmd/conitrace
cmd/cp
cmd/cpu
+ cmd/cpuid
cmd/cyclic
cmd/dm
cmd/ebtupdate
@@ -83,9 +85,11 @@
cmd/loads
cmd/loadx
cmd/loady
+ cmd/meminfo
cmd/mbr
cmd/md
cmd/mmc
+ cmd/msr
cmd/mtest
cmd/mtrr
cmd/panic
@@ -100,6 +104,7 @@
cmd/reset
cmd/rng
cmd/saves
+ cmd/sb
cmd/sbi
cmd/scmi
cmd/scp03
@@ -112,6 +117,7 @@
cmd/smbios
cmd/sound
cmd/source
+ cmd/tcpm
cmd/temperature
cmd/tftpput
cmd/trace
diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c
index 16600be..b02430e 100644
--- a/drivers/adc/adc-uclass.c
+++ b/drivers/adc/adc-uclass.c
@@ -382,7 +382,7 @@
if (!ret)
return adc_vdd_plat_update(dev);
- if (ret != -ENOENT)
+ if (ret != -ENOSYS && ret != -ENOENT)
return ret;
/* No vdd-supply phandle. */
@@ -406,7 +406,7 @@
if (!ret)
return adc_vss_plat_update(dev);
- if (ret != -ENOENT)
+ if (ret != -ENOSYS && ret != -ENOENT)
return ret;
/* No vss-supply phandle. */
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index f6832ab..7cf9735 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -241,7 +241,7 @@
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
- struct udevice *vref;
+ struct udevice *vref = NULL;
struct clk clk;
int vref_uv;
int ret;
@@ -259,7 +259,7 @@
priv->active_channel = -1;
ret = device_get_supply_regulator(dev, "vref-supply", &vref);
- if (ret) {
+ if (ret && uc_pdata->vdd_microvolts <= 0) {
printf("can't get vref-supply: %d\n", ret);
return ret;
}
@@ -267,7 +267,10 @@
if (priv->reset)
rockchip_saradc_reset_controller(priv->reset);
- vref_uv = regulator_get_value(vref);
+ if (vref)
+ vref_uv = regulator_get_value(vref);
+ else
+ vref_uv = uc_pdata->vdd_microvolts;
if (vref_uv < 0) {
printf("can't get vref-supply value: %d\n", vref_uv);
return vref_uv;
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 6cca561..4fbb63a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -78,14 +78,16 @@
Enable this driver to support Sata devices through
Mediatek AHCI controller (e.g. MT7622).
-config AHCI_MVEBU
- bool "Marvell EBU AHCI SATA support"
- depends on ARCH_MVEBU || ARCH_OCTEON
+config AHCI_GENERIC
+ bool "Generic AHCI SATA support"
+ depends on OF_CONTROL
select SCSI_AHCI
select SCSI
help
- This option enables support for the Marvell EBU SoC's
- onboard AHCI SATA.
+ This option enables support for generic onboard AHCI SATA controller
+ that do not need platform specific quirks, like emulated devices,
+ Marvell EBU SoC's onboard AHCI SATA controllers or Cavium's Octeon
+ 7130 AHCI controllers.
If unsure, say N.
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index ee10c44..69fa9b7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -14,6 +14,6 @@
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
-obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
+obj-$(CONFIG_AHCI_GENERIC) += ahci_generic.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_generic.c
similarity index 71%
rename from drivers/ata/ahci_mvebu.c
rename to drivers/ata/ahci_generic.c
index f6e2d6b..6e5a6cb 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_generic.c
@@ -16,7 +16,7 @@
return 0;
}
-static int mvebu_ahci_bind(struct udevice *dev)
+static int generic_ahci_bind(struct udevice *dev)
{
struct udevice *scsi_dev;
int ret;
@@ -30,7 +30,7 @@
return 0;
}
-static int mvebu_ahci_probe(struct udevice *dev)
+static int generic_ahci_probe(struct udevice *dev)
{
/*
* Board specific SATA / AHCI enable code, e.g. enable the
@@ -43,18 +43,19 @@
return 0;
}
-static const struct udevice_id mvebu_ahci_ids[] = {
+static const struct udevice_id generic_ahci_ids[] = {
{ .compatible = "marvell,armada-380-ahci" },
{ .compatible = "marvell,armada-3700-ahci" },
{ .compatible = "marvell,armada-8k-ahci" },
{ .compatible = "cavium,octeon-7130-ahci" },
+ { .compatible = "generic-ahci" },
{ }
};
-U_BOOT_DRIVER(ahci_mvebu_drv) = {
- .name = "ahci_mvebu",
+U_BOOT_DRIVER(ahci_generic_drv) = {
+ .name = "ahci_generic",
.id = UCLASS_AHCI,
- .of_match = mvebu_ahci_ids,
- .bind = mvebu_ahci_bind,
- .probe = mvebu_ahci_probe,
+ .of_match = generic_ahci_ids,
+ .bind = generic_ahci_bind,
+ .probe = generic_ahci_probe,
};
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 312e038..f3ac8db 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -695,9 +695,22 @@
return -ENOENT;
}
-int blk_create_device(struct udevice *parent, const char *drv_name,
- const char *name, int uclass_id, int devnum, int blksz,
- lbaint_t lba, struct udevice **devp)
+/**
+ * blk_create_device() - Create a new block device
+ *
+ * @parent: Parent of the new device
+ * @drv_name: Driver name to use for the block device
+ * @name: Name for the device
+ * @uclass_id: Interface type (enum uclass_id_t)
+ * @devnum: Device number, specific to the interface type, or -1 to
+ * allocate the next available number
+ * @blksz: Block size of the device in bytes (typically 512)
+ * @lba: Total number of blocks of the device
+ * @devp: the new device (which has not been probed)
+ */
+static int blk_create_device(struct udevice *parent, const char *drv_name,
+ const char *name, int uclass_id, int devnum,
+ int blksz, lbaint_t lba, struct udevice **devp)
{
struct blk_desc *desc;
struct udevice *dev;
diff --git a/drivers/block/rkmtd.c b/drivers/block/rkmtd.c
index c55f052..f84cacd 100644
--- a/drivers/block/rkmtd.c
+++ b/drivers/block/rkmtd.c
@@ -794,36 +794,19 @@
return 0;
}
-static void rkmtd_blk_kmalloc_release(struct udevice *dev, void *res)
-{
- /* noop */
-}
-
static int rkmtd_bind(struct udevice *dev)
{
struct rkmtd_dev *plat = dev_get_plat(dev);
- char dev_name[30], *str;
struct blk_desc *desc;
struct udevice *bdev;
int ret;
- snprintf(dev_name, sizeof(dev_name), "%s.%s", dev->name, "blk");
-
- str = devres_alloc(rkmtd_blk_kmalloc_release, strlen(dev_name) + 1, GFP_KERNEL);
- if (unlikely(!str))
- return -ENOMEM;
-
- strcpy(str, dev_name);
-
- ret = blk_create_device(dev, "rkmtd_blk", str, UCLASS_RKMTD,
- -1, 512, LBA, &bdev);
+ ret = blk_create_devicef(dev, "rkmtd_blk", "blk", UCLASS_RKMTD,
+ -1, 512, LBA, &bdev);
if (ret) {
- free(str);
return log_msg_ret("blk", ret);
}
- devres_add(dev, str);
-
desc = dev_get_uclass_plat(bdev);
sprintf(desc->vendor, "0x%.4x", 0x2207);
memcpy(desc->product, "RKMTD", sizeof("RKMTD"));
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index 62fed7e..466d717 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -48,6 +48,8 @@
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
+ case IMX8QM_CLK_DUMMY:
+ return 0;
case IMX8QM_A53_DIV:
resource = SC_R_A53;
pm_clk = SC_PM_CLK_CPU;
@@ -264,6 +266,8 @@
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
+ case IMX8QM_CLK_DUMMY:
+ return 0;
case IMX8QM_I2C0_IPG_CLK:
case IMX8QM_I2C0_CLK:
case IMX8QM_I2C0_DIV:
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 18bdc08..7909862 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -51,6 +51,8 @@
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
+ case IMX8QXP_CLK_DUMMY:
+ return 0;
case IMX8QXP_A35_DIV:
resource = SC_R_A35;
pm_clk = SC_PM_CLK_CPU;
@@ -248,6 +250,8 @@
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
+ case IMX8QXP_CLK_DUMMY:
+ return 0;
case IMX8QXP_I2C0_CLK:
case IMX8QXP_I2C0_IPG_CLK:
resource = SC_R_I2C_0;
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 788e065..2c029ec 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -144,6 +144,9 @@
clk_dm(IMXRT1050_CLK_AHB_PODF,
imx_clk_divider("ahb_podf", "periph_sel",
base + 0x14, 10, 3));
+ clk_dm(IMXRT1050_CLK_IPG_PDOF,
+ imx_clk_divider("ipg_podf", "ahb_podf",
+ base + 0x14, 8, 2));
clk_dm(IMXRT1050_CLK_USDHC1_PODF,
imx_clk_divider("usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
index b702415..62072e10 100644
--- a/drivers/clk/microchip/Kconfig
+++ b/drivers/clk/microchip/Kconfig
@@ -1,5 +1,7 @@
config CLK_MPFS
bool "Clock support for Microchip PolarFire SoC"
depends on CLK && CLK_CCF
+ depends on SYSCON
+ depends on REGMAP
help
This enables support clock driver for Microchip PolarFire SoC platform.
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 0a82777..2c6694f 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -9,25 +9,39 @@
#include <log.h>
#include <dm/device.h>
#include <dm/devres.h>
+#include <dm/ofnode.h>
#include <dm/uclass.h>
+#include <regmap.h>
+#include <syscon.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
#include "mpfs_clk.h"
-static int mpfs_clk_probe(struct udevice *dev)
+static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base,
+ struct regmap **regmap)
{
- struct clk *parent_clk = dev_get_priv(dev);
- struct clk clk_msspll = { .id = CLK_MSSPLL };
- void __iomem *base;
- void __iomem *msspll_base;
- int ret;
+ ofnode node;
- base = dev_read_addr_index_ptr(dev, 0);
- if (!base)
- return -EINVAL;
+ node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg");
+ if (!ofnode_valid(node))
+ return -ENODEV;
- ret = clk_get_by_index(dev, 0, parent_clk);
+ *regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ *msspll_base = dev_read_addr_index_ptr(dev, 0);
+
+ return 0;
+}
+
+static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base,
+ struct regmap **regmap)
+{
+ int ret;
+
+ ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0);
if (ret)
return ret;
@@ -40,7 +54,30 @@
* Otherwise, skip registering it & pass the reference clock directly
* to the cfg clock registration function.
*/
- msspll_base = dev_read_addr_index_ptr(dev, 1);
+ *msspll_base = dev_read_addr_index_ptr(dev, 1);
+
+ return 0;
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ struct clk *parent_clk = dev_get_priv(dev);
+ struct clk clk_msspll = { .id = CLK_MSSPLL };
+ struct regmap *regmap;
+ void __iomem *msspll_base;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, parent_clk);
+ if (ret)
+ return ret;
+
+ ret = mpfs_clk_syscon_probe(dev, &msspll_base, ®map);
+ if (ret) {
+ ret = mpfs_clk_old_format_probe(dev, &msspll_base, ®map);
+ if (ret)
+ return ret;
+ }
+
if (msspll_base) {
ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
if (ret)
@@ -50,11 +87,11 @@
parent_clk = &clk_msspll;
}
- ret = mpfs_clk_register_cfgs(base, parent_clk);
+ ret = mpfs_clk_register_cfgs(parent_clk, regmap);
if (ret)
return ret;
- ret = mpfs_clk_register_periphs(base, dev);
+ ret = mpfs_clk_register_periphs(dev, regmap);
return ret;
}
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 72288cc..b8ad3ea 100644
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -7,6 +7,7 @@
#define __MICROCHIP_MPFS_CLK_H
#include <linux/clk-provider.h>
+#include <regmap.h>
/**
* mpfs_clk_register_cfgs() - register configuration clocks
*
@@ -14,7 +15,7 @@
* @parent: a pointer to parent clock.
* Return: zero on success, or a negative error code.
*/
-int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
+int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap);
/**
* mpfs_clk_register_msspll() - register the mss pll
*
@@ -30,7 +31,7 @@
* @dev: udevice representing the clock controller.
* Return: zero on success, or a negative error code.
*/
-int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
+int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap);
/**
* divider_get_val() - get the clock divider value
*
diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c
index 5e8fb99..7da1fc7 100644
--- a/drivers/clk/microchip/mpfs_clk_cfg.c
+++ b/drivers/clk/microchip/mpfs_clk_cfg.c
@@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
+#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@@ -57,7 +58,7 @@
*/
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
- void __iomem *sys_base;
+ struct regmap *regmap;
u32 prate;
struct clk hw;
};
@@ -68,11 +69,11 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
unsigned long rate;
u32 val;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
+ val >>= cfg->shift;
val &= clk_div_mask(cfg->width);
rate = cfg_hw->prate / (1u << val);
hw->rate = rate;
@@ -84,7 +85,6 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
u32 val;
int divider_setting;
@@ -93,10 +93,10 @@
if (divider_setting < 0)
return divider_setting;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
val |= divider_setting << cfg->shift;
- writel(val, base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_write(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, val);
return clk_get_rate(hw);
}
@@ -116,7 +116,7 @@
CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
};
-int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
+int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@@ -126,7 +126,7 @@
num_clks = ARRAY_SIZE(mpfs_cfg_clks);
for (i = 0; i < num_clks; i++) {
hw = &mpfs_cfg_clks[i].hw;
- mpfs_cfg_clks[i].sys_base = base;
+ mpfs_cfg_clks[i].regmap = regmap;
mpfs_cfg_clks[i].prate = clk_get_rate(parent);
name = mpfs_cfg_clks[i].cfg.name;
ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);
diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c
index 41c6df4..b734f49 100644
--- a/drivers/clk/microchip/mpfs_clk_periph.c
+++ b/drivers/clk/microchip/mpfs_clk_periph.c
@@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
+#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@@ -50,7 +51,7 @@
*/
struct mpfs_periph_hw_clock {
struct mpfs_periph_clock periph;
- void __iomem *sys_base;
+ struct regmap *regmap;
u32 prate;
struct clk hw;
};
@@ -61,17 +62,16 @@
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
- u32 reg, val;
+ u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
- reg = readl(base_addr + REG_SUBBLK_RESET_CR);
- val = reg & ~(1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_RESET_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
+ reg &= ~(1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
- reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
- val = reg | (1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
+ reg |= (1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@@ -81,17 +81,16 @@
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
- u32 reg, val;
+ u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
- reg = readl(base_addr + REG_SUBBLK_RESET_CR);
- val = reg | (1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_RESET_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
+ reg |= (1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
- reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
- val = reg & ~(1u << periph->shift);
- writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
+ regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
+ reg &= ~(1u << periph->shift);
+ regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@@ -159,7 +158,7 @@
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
};
-int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev)
+int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@@ -172,7 +171,7 @@
clk_request(dev, &parent);
hw = &mpfs_periph_clks[i].hw;
- mpfs_periph_clks[i].sys_base = base;
+ mpfs_periph_clks[i].regmap = regmap;
mpfs_periph_clks[i].prate = clk_get_rate(&parent);
name = mpfs_periph_clks[i].periph.name;
ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name);
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 4f1dfbc..aa38c0f 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -579,23 +579,24 @@
struct cpg_mssr_info *info =
(struct cpg_mssr_info *)dev_get_driver_data(parent);
struct udevice *cdev, *rdev;
- struct driver *drv;
+ struct driver *cdrv, *rdrv;
int ret;
- drv = lists_driver_lookup_name("clk_gen3");
- if (!drv)
+ cdrv = lists_driver_lookup_name("clk_gen3");
+ if (!cdrv)
return -ENOENT;
- ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info,
+
+ rdrv = lists_driver_lookup_name("rst_gen3");
+ if (!rdrv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(parent, cdrv, "clk_gen3", (ulong)info,
dev_ofnode(parent), &cdev);
if (ret)
return ret;
- drv = lists_driver_lookup_name("rst_gen3");
- if (!drv)
- return -ENOENT;
-
- ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev,
+ ret = device_bind_with_driver_data(parent, rdrv, "rst_gen3", (ulong)cdev,
dev_ofnode(parent), &rdev);
if (ret)
device_unbind(cdev);
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 22ede1c..ad7e1c0 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1588,6 +1588,105 @@
return priv->gpll_hz;
}
+static ulong px30_pmu_uart0_get_clk(struct px30_pmuclk_priv *priv)
+{
+ struct px30_pmucru *pmucru = priv->pmucru;
+ u32 clk_div_con;
+ u32 clk_pll_sel;
+ ulong pll_rate;
+ u32 clk_sel;
+ ulong clk;
+ u32 con;
+
+ con = readl(&pmucru->pmu_clksel_con[3]);
+ clk_div_con = bitfield_extract_by_mask(con, UART0_DIV_CON_MASK);
+ clk_pll_sel = bitfield_extract_by_mask(con, UART0_PLL_SEL_MASK);
+
+ switch (clk_pll_sel) {
+ case UART0_PLL_SEL_GPLL:
+ pll_rate = px30_pmuclk_get_gpll_rate(priv);
+ break;
+ case UART0_PLL_SEL_24M:
+ pll_rate = OSC_HZ;
+ break;
+ case UART0_PLL_SEL_480M:
+ case UART0_PLL_SEL_NPLL:
+ /* usbphy480M and NPLL clocks, generated by CRU, are not supported yet */
+ default:
+ return -ENOENT;
+ }
+
+ clk = DIV_TO_RATE(pll_rate, clk_div_con);
+ con = readl(&pmucru->pmu_clksel_con[4]);
+ clk_sel = bitfield_extract_by_mask(con, UART0_CLK_SEL_MASK);
+
+ switch (clk_sel) {
+ case UART0_CLK_SEL_UART0:
+ return clk;
+ case UART0_CLK_SEL_UART0_NP5:{
+ u32 clk_divnp5_div_con;
+
+ clk_divnp5_div_con =
+ bitfield_extract_by_mask(con, UART0_DIVNP5_MASK);
+ return 2 * (u64) clk / (2 * clk_divnp5_div_con + 3);
+ }
+ case UART0_CLK_SEL_UART0_FRAC:{
+ u32 fracdiv, n, m;
+
+ fracdiv = readl(&pmucru->pmu_clksel_con[5]);
+ n = bitfield_extract_by_mask(fracdiv,
+ CLK_UART_FRAC_NUMERATOR_MASK);
+ m = bitfield_extract_by_mask(fracdiv,
+ CLK_UART_FRAC_DENOMINATOR_MASK);
+ return (u64) clk * n / m;
+ }
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong px30_pmu_uart0_set_clk(struct px30_pmuclk_priv *priv, ulong rate)
+{
+ struct px30_pmucru *pmucru = priv->pmucru;
+ ulong m = 0, n = 0;
+ ulong gpll_rate;
+ u32 clk_div_con;
+ u32 clk_pll_sel;
+ u32 clk_sel;
+
+ gpll_rate = px30_pmuclk_get_gpll_rate(priv);
+ if (gpll_rate % rate == 0) {
+ clk_pll_sel = UART0_PLL_SEL_GPLL;
+ clk_sel = UART0_CLK_SEL_UART0;
+ clk_div_con = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (rate == OSC_HZ) {
+ clk_pll_sel = UART0_PLL_SEL_24M;
+ clk_sel = UART0_CLK_SEL_UART0;
+ clk_div_con = 1;
+ } else {
+ clk_pll_sel = UART0_PLL_SEL_GPLL;
+ clk_sel = UART0_CLK_SEL_UART0_FRAC;
+ clk_div_con = 1;
+ rational_best_approximation(rate, priv->gpll_hz,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0), &m, &n);
+ }
+
+ rk_clrsetreg(&pmucru->pmu_clksel_con[3],
+ UART0_PLL_SEL_MASK | UART0_DIV_CON_MASK,
+ clk_pll_sel << UART0_PLL_SEL_SHIFT | (clk_div_con - 1));
+ rk_clrsetreg(&pmucru->pmu_clksel_con[4], UART0_CLK_SEL_MASK,
+ clk_sel << UART0_CLK_SEL_SHIFT);
+ if (m && n) {
+ u32 fracdiv;
+
+ fracdiv = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(fracdiv, &pmucru->pmu_clksel_con[5]);
+ }
+
+ return px30_pmu_uart0_get_clk(priv);
+}
+
static ulong px30_pmuclk_get_rate(struct clk *clk)
{
struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev);
@@ -1601,6 +1700,9 @@
case PCLK_PMU_PRE:
rate = px30_pclk_pmu_get_pmuclk(priv);
break;
+ case SCLK_UART0_PMU:
+ rate = px30_pmu_uart0_get_clk(priv);
+ break;
default:
return -ENOENT;
}
@@ -1621,6 +1723,9 @@
case PCLK_PMU_PRE:
ret = px30_pclk_pmu_set_pmuclk(priv, rate);
break;
+ case SCLK_UART0_PMU:
+ ret = px30_pmu_uart0_set_clk(priv, rate);
+ break;
default:
return -ENOENT;
}
diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
index 9f78422..4763963 100644
--- a/drivers/core/acpi.c
+++ b/drivers/core/acpi.c
@@ -48,6 +48,7 @@
METHOD_FILL_SSDT,
METHOD_INJECT_DSDT,
METHOD_SETUP_NHLT,
+ METHOD_FILL_MADT,
};
/* Prototype for all methods */
@@ -282,6 +283,8 @@
switch (method) {
case METHOD_WRITE_TABLES:
return aops->write_tables;
+ case METHOD_FILL_MADT:
+ return aops->fill_madt;
case METHOD_FILL_SSDT:
return aops->fill_ssdt;
case METHOD_INJECT_DSDT:
@@ -328,6 +331,19 @@
return 0;
}
+int acpi_fill_madt_subtbl(struct acpi_ctx *ctx)
+{
+ int ret;
+
+ log_debug("Writing MADT table\n");
+ ret = acpi_recurse_method(ctx, dm_root(), METHOD_FILL_MADT, TYPE_NONE);
+ log_debug("Writing MADT finished, err=%d\n", ret);
+ if (ret)
+ return log_msg_ret("build", ret);
+
+ return ret;
+}
+
int acpi_fill_ssdt(struct acpi_ctx *ctx)
{
void *start = ctx->current;
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index d05be27..77acd76 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -490,17 +490,17 @@
{
const u8 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = *val;
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -509,17 +509,17 @@
{
const __be16 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname, sizeof(*outp));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be16_to_cpup(val);
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -534,14 +534,14 @@
{
const __be32 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
val = of_find_property_value_of_size(np, propname,
sz * sizeof(*out_values));
if (IS_ERR(val))
return PTR_ERR(val);
- dm_warn("size %zd\n", sz);
+ log_debug("size %zd\n", sz);
while (sz--)
*out_values++ = be32_to_cpup(val++);
@@ -553,19 +553,19 @@
{
const __be32 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be32_to_cpup(val + index);
- dm_warn("%#x (%d)\n", *outp, *outp);
+ log_debug("%#x (%d)\n", *outp, *outp);
return 0;
}
@@ -575,20 +575,20 @@
{
const __be64 *val;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (!np)
return -EINVAL;
val = of_find_property_value_of_size(np, propname,
sizeof(*outp) * (index + 1));
if (IS_ERR(val)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return PTR_ERR(val);
}
*outp = be64_to_cpup(val + index);
- dm_warn("%#llx (%lld)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ log_debug("%#llx (%lld)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -621,7 +621,7 @@
l = strnlen(p, end - p) + 1;
if (p + l > end)
return -EILSEQ;
- dm_warn("comparing %s with %s\n", string, p);
+ log_debug("comparing %s with %s\n", string, p);
if (strcmp(string, p) == 0)
return i; /* Found it; return index */
}
@@ -826,8 +826,8 @@
strncpy(ap->stem, stem, stem_len);
ap->stem[stem_len] = 0;
list_add_tail(&ap->link, &aliases_lookup);
- dm_warn("adding DT alias:%s: stem=%s id=%i node=%s\n",
- ap->alias, ap->stem, ap->id, of_node_full_name(np));
+ log_debug("adding DT alias:%s: stem=%s id=%i node=%s\n",
+ ap->alias, ap->stem, ap->id, of_node_full_name(np));
}
int of_alias_scan(void)
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index 6c7b4c9..250dd17 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -27,7 +27,7 @@
#ifdef DEBUG
static void of_dump_addr(const char *s, const __be32 *addr, int na)
{
- dm_warn("%s", s);
+ pr_debug("%s", s);
while (na--)
pr_cont(" %08x", be32_to_cpu(*(addr++)));
pr_cont("\n");
@@ -66,9 +66,9 @@
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr, na);
- dm_warn("default map, cp=%llx, s=%llx, da=%llx\n",
- (unsigned long long)cp, (unsigned long long)s,
- (unsigned long long)da);
+ log_debug("default map, cp=%llx, s=%llx, da=%llx\n",
+ (unsigned long long)cp, (unsigned long long)s,
+ (unsigned long long)da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
@@ -200,11 +200,11 @@
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
- dm_warn("empty ranges; 1:1 translation\n");
+ log_debug("empty ranges; 1:1 translation\n");
goto finish;
}
- dm_warn("walking ranges...\n");
+ log_debug("walking ranges...\n");
/* Now walk through the ranges */
rlen /= 4;
@@ -222,7 +222,7 @@
finish:
of_dump_addr("parent translation for:", addr, pna);
- dm_warn("with offset: %llx\n", (unsigned long long)offset);
+ log_debug("with offset: %llx\n", (unsigned long long)offset);
/* Translate it into parent bus space */
return pbus->translate(addr, offset, pna);
@@ -247,7 +247,7 @@
int na, ns, pna, pns;
u64 result = OF_BAD_ADDR;
- dm_warn("** translation for device %s **\n", of_node_full_name(dev));
+ log_debug("** translation for device %s **\n", of_node_full_name(dev));
/* Increase refcount at current level */
(void)of_node_get(dev);
@@ -266,8 +266,8 @@
}
memcpy(addr, in_addr, na * 4);
- dm_warn("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
- of_node_full_name(parent));
+ log_debug("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns,
+ of_node_full_name(parent));
of_dump_addr("translating address:", addr, na);
/* Translate */
@@ -279,7 +279,7 @@
/* If root, we have finished */
if (parent == NULL) {
- dm_warn("reached root node\n");
+ log_debug("reached root node\n");
result = of_read_number(addr, na);
break;
}
@@ -293,8 +293,8 @@
break;
}
- dm_warn("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
- pna, pns, of_node_full_name(parent));
+ log_debug("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name,
+ pna, pns, of_node_full_name(parent));
/* Apply bus translation */
if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop))
diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c
index bfc1e34..f49187d 100644
--- a/drivers/core/of_extra.c
+++ b/drivers/core/of_extra.c
@@ -58,7 +58,7 @@
const fdt_addr_t *cell;
int len;
- dm_warn("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
+ log_debug("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name);
cell = ofnode_get_property(node, prop_name, &len);
if (!cell || (len < sizeof(fdt_addr_t) * 2)) {
dm_warn("cell=%p, len=%d\n", cell, len);
@@ -67,8 +67,8 @@
*basep = fdt_addr_to_cpu(*cell);
*sizep = fdt_size_to_cpu(cell[1]);
- dm_warn("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
- (ulong)*sizep);
+ log_debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
+ (ulong)*sizep);
return 0;
}
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 48ae8ce..950895e 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -315,7 +315,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u8(ofnode_to_np(node), propname, outp);
@@ -323,11 +323,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = *cell;
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -346,7 +346,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u16(ofnode_to_np(node), propname, outp);
@@ -354,11 +354,11 @@
cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname,
&len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = be16_to_cpup(cell);
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -391,7 +391,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u32_index(ofnode_to_np(node), propname, index,
@@ -400,17 +400,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(int) * (index + 1))) {
- dm_warn("(not large enough)\n");
+ log_debug("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt32_to_cpu(cell[index]);
- dm_warn("%#x (%u)\n", *outp, *outp);
+ log_debug("%#x (%u)\n", *outp, *outp);
return 0;
}
@@ -430,17 +430,17 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
if (len < (sizeof(u64) * (index + 1))) {
- dm_warn("(not large enough)\n");
+ log_debug("(not large enough)\n");
return -EOVERFLOW;
}
*outp = fdt64_to_cpu(cell[index]);
- dm_warn("%#llx (%llu)\n", *outp, *outp);
+ log_debug("%#llx (%llu)\n", *outp, *outp);
return 0;
}
@@ -468,7 +468,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node))
return of_read_u64(ofnode_to_np(node), propname, outp);
@@ -476,12 +476,12 @@
cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
propname, &len);
if (!cell || len < sizeof(*cell)) {
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return -EINVAL;
}
*outp = fdt64_to_cpu(cell[0]);
- dm_warn("%#llx (%llu)\n", (unsigned long long)*outp,
- (unsigned long long)*outp);
+ log_debug("%#llx (%llu)\n", (unsigned long long)*outp,
+ (unsigned long long)*outp);
return 0;
}
@@ -499,11 +499,11 @@
bool prop;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
prop = ofnode_has_property(node, propname);
- dm_warn("%s\n", prop ? "true" : "false");
+ log_debug("%s\n", prop ? "true" : "false");
return prop ? true : false;
}
@@ -514,7 +514,7 @@
int len;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
struct property *prop = of_find_property(
@@ -529,7 +529,7 @@
propname, &len);
}
if (!val) {
- dm_warn("<not found>\n");
+ log_debug("<not found>\n");
if (sizep)
*sizep = -FDT_ERR_NOTFOUND;
return NULL;
@@ -553,7 +553,7 @@
dm_warn("<invalid>\n");
return NULL;
}
- dm_warn("%s\n", str);
+ log_debug("%s\n", str);
return str;
}
@@ -573,7 +573,7 @@
ofnode subnode;
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, subnode_name);
+ log_debug("%s: %s: ", __func__, subnode_name);
if (ofnode_is_np(node)) {
struct device_node *np = ofnode_to_np(node);
@@ -588,8 +588,8 @@
ofnode_to_offset(node), subnode_name);
subnode = noffset_to_ofnode(node, ooffset);
}
- dm_warn("%s\n", ofnode_valid(subnode) ?
- ofnode_get_name(subnode) : "<none>");
+ log_debug("%s\n", ofnode_valid(subnode) ?
+ ofnode_get_name(subnode) : "<none>");
return subnode;
}
@@ -598,7 +598,7 @@
u32 *out_values, size_t sz)
{
assert(ofnode_valid(node));
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
if (ofnode_is_np(node)) {
return of_read_u32_array(ofnode_to_np(node), propname,
@@ -1032,7 +1032,7 @@
if (!prop)
return ofnode_null();
- dm_warn("%s: node_path: %s\n", __func__, prop);
+ log_debug("%s: node_path: %s\n", __func__, prop);
return ofnode_path(prop);
}
@@ -1301,7 +1301,7 @@
int len;
int ret = -ENOENT;
- dm_warn("%s: %s: ", __func__, propname);
+ log_debug("%s: %s: ", __func__, propname);
/*
* If we follow the pci bus bindings strictly, we should check
@@ -1318,10 +1318,10 @@
int i;
for (i = 0; i < num; i++) {
- dm_warn("pci address #%d: %08lx %08lx %08lx\n", i,
- (ulong)fdt32_to_cpu(cell[0]),
- (ulong)fdt32_to_cpu(cell[1]),
- (ulong)fdt32_to_cpu(cell[2]));
+ log_debug("pci address #%d: %08lx %08lx %08lx\n", i,
+ (ulong)fdt32_to_cpu(cell[0]),
+ (ulong)fdt32_to_cpu(cell[1]),
+ (ulong)fdt32_to_cpu(cell[2]));
if ((fdt32_to_cpu(*cell) & type) == type) {
const unaligned_fdt64_t *ptr;
@@ -1348,7 +1348,7 @@
ret = -EINVAL;
fail:
- dm_warn("(not found)\n");
+ log_debug("(not found)\n");
return ret;
}
@@ -1632,7 +1632,7 @@
{
assert(ofnode_valid(node));
- dm_warn("%s: %s = %s", __func__, propname, value);
+ log_debug("%s: %s = %s", __func__, propname, value);
return ofnode_write_prop(node, propname, value, strlen(value) + 1,
false);
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 7ae0884..f846a35 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -304,6 +304,17 @@
return uclass_find_device_by_namelen(id, name, strlen(name), devp);
}
+struct udevice *uclass_try_first_device(enum uclass_id id)
+{
+ struct uclass *uc;
+
+ uc = uclass_find(id);
+ if (!uc || list_empty(&uc->dev_head))
+ return NULL;
+
+ return list_first_entry(&uc->dev_head, struct udevice, uclass_node);
+}
+
int uclass_find_next_free_seq(struct uclass *uc)
{
struct udevice *dev;
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 5c06cd9..4cc3679 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -26,6 +26,13 @@
help
Support CPU cores for RISC-V architecture.
+config CPU_ARMV8
+ bool "Enable generic ARMv8 CPU driver"
+ depends on CPU && ARM64
+ select IRQ
+ help
+ Support CPU cores for armv8 architecture.
+
config CPU_MICROBLAZE
bool "Enable Microblaze CPU driver"
depends on CPU && MICROBLAZE
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index bc75d9b..eaf4947 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -6,10 +6,12 @@
obj-$(CONFIG_CPU) += cpu-uclass.o
+obj-$(CONFIG_ARCH_BCM283X) += bcm283x_cpu.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
+obj-$(CONFIG_CPU_ARMV8) += armv8_cpu.o
obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c
new file mode 100644
index 0000000..4eedfe5
--- /dev/null
+++ b/drivers/cpu/armv8_cpu.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+#include <cpu.h>
+#include <dm.h>
+#include <irq.h>
+#include <acpi/acpigen.h>
+#include <asm/armv8/cpu.h>
+#include <asm/io.h>
+#include <dm/acpi.h>
+#include <linux/bitops.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+static int armv8_cpu_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ int cpuid;
+
+ cpuid = (read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT;
+
+ snprintf(buf, size, "CPU MIDR %04x", cpuid);
+
+ return 0;
+}
+
+static int armv8_cpu_get_info(const struct udevice *dev,
+ struct cpu_info *info)
+{
+ info->cpu_freq = 0;
+ info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int armv8_cpu_get_count(const struct udevice *dev)
+{
+ return uclass_id_count(UCLASS_CPU);
+}
+
+#ifdef CONFIG_ACPIGEN
+int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ uint core_id = dev_seq(dev);
+
+ acpigen_write_processor_device(ctx, core_id);
+
+ return 0;
+}
+
+int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ struct acpi_madt_gicc *gicc;
+ struct cpu_plat *cpu_plat;
+ struct udevice *gic;
+ u64 gicc_gicv = 0;
+ u64 gicc_gich = 0;
+ u64 gicc_gicr_base = 0;
+ u64 gicc_phys_base = 0;
+ u32 gicc_perf_gsiv = 0;
+ u64 gicc_mpidr;
+ u32 gicc_vgic_maint_irq = 0;
+ int addr_index;
+ fdt_addr_t addr;
+ int ret;
+ struct irq req_irq;
+
+ cpu_plat = dev_get_parent_plat(dev);
+ if (!cpu_plat)
+ return 0;
+
+ ret = irq_get_interrupt_parent(dev, &gic);
+ if (ret) {
+ log_err("%s: Failed to find interrupt parent for %s\n",
+ __func__, dev->name);
+ return -ENODEV;
+ }
+
+ addr_index = 1;
+
+ if (device_is_compatible(gic, "arm,gic-v3")) {
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gicr_base = addr;
+ }
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_phys_base = addr;
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gich = addr;
+
+ addr = dev_read_addr_index(gic, addr_index++);
+ if (addr != FDT_ADDR_T_NONE)
+ gicc_gicv = addr;
+
+ ret = irq_get_by_index(gic, 0, &req_irq);
+ if (!ret)
+ gicc_vgic_maint_irq = req_irq.id;
+
+ gicc_mpidr = dev_read_u64_default(dev, "reg", 0);
+ if (!gicc_mpidr)
+ gicc_mpidr = dev_read_u32_default(dev, "reg", 0);
+
+ /*
+ * gicc_vgic_maint_irq and gicc_gicv are the same for every CPU
+ */
+ gicc = ctx->current;
+ acpi_write_madt_gicc(gicc,
+ dev_seq(dev),
+ gicc_perf_gsiv, /* FIXME: needs a PMU driver */
+ gicc_phys_base,
+ gicc_gicv,
+ gicc_gich,
+ gicc_vgic_maint_irq,
+ gicc_gicr_base,
+ gicc_mpidr,
+ 0); /* FIXME: Not defined in DT */
+
+ acpi_inc(ctx, gicc->length);
+
+ return 0;
+}
+
+struct acpi_ops armv8_cpu_acpi_ops = {
+ .fill_ssdt = armv8_cpu_fill_ssdt,
+ .fill_madt = armv8_cpu_fill_madt,
+};
+#endif
+
+static const struct cpu_ops cpu_ops = {
+ .get_count = armv8_cpu_get_count,
+ .get_desc = armv8_cpu_get_desc,
+ .get_info = armv8_cpu_get_info,
+};
+
+static const struct udevice_id cpu_ids[] = {
+ { .compatible = "arm,armv8" },
+ {}
+};
+
+U_BOOT_DRIVER(arm_cpu) = {
+ .name = "arm-cpu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_ids,
+ .ops = &cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ ACPI_OPS_PTR(&armv8_cpu_acpi_ops)
+};
diff --git a/drivers/cpu/armv8_cpu.h b/drivers/cpu/armv8_cpu.h
new file mode 100644
index 0000000..48c705e
--- /dev/null
+++ b/drivers/cpu/armv8_cpu.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+#include <dm/acpi.h>
+#include <dm/device.h>
+
+#ifndef _ARMV8_CPU_H_
+#define _ARMV8_CPU_H_
+
+/**
+ * armv8_cpu_fill_ssdt() - Fill the SSDT
+ * Parses the FDT and writes the SSDT nodes.
+ *
+ * @dev: cpu device to generate ACPI tables for
+ * @ctx: ACPI context pointer
+ * @return: 0 if OK, or a negative error code.
+ */
+int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx);
+
+/**
+ * armv8_cpu_fill_madt() - Fill the MADT
+ * Parses the FDT and writes the MADT subtables.
+ *
+ * @dev: cpu device to generate ACPI tables for
+ * @ctx: ACPI context pointer
+ * @return: 0 if OK, or a negative error code.
+ */
+int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx);
+
+#endif
\ No newline at end of file
diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c
new file mode 100644
index 0000000..59a7b14
--- /dev/null
+++ b/drivers/cpu/bcm283x_cpu.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 9elements GmbH
+ */
+
+#include <cpu.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <acpi/acpigen.h>
+#include <asm/armv8/cpu.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <asm-generic/sections.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include "armv8_cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct bcm_plat {
+ u64 release_addr;
+};
+
+static int cpu_bcm_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+ const char *name;
+
+ if (size < 32)
+ return -ENOSPC;
+
+ if (device_is_compatible(dev, "arm,cortex-a53"))
+ name = "A53";
+ else if (device_is_compatible(dev, "arm,cortex-a72"))
+ name = "A72";
+ else
+ name = "?";
+
+ snprintf(buf, size, "Broadcom Cortex-%s at %u MHz\n",
+ name, plat->timebase_freq);
+
+ return 0;
+}
+
+static int cpu_bcm_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ info->cpu_freq = plat->timebase_freq * 1000;
+ info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int cpu_bcm_get_count(const struct udevice *dev)
+{
+ return uclass_id_count(UCLASS_CPU);
+}
+
+static int cpu_bcm_get_vendor(const struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "Broadcom");
+
+ return 0;
+}
+
+static int cpu_bcm_is_current(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ if (plat->cpu_id == (read_mpidr() & 0xffff))
+ return 1;
+
+ return 0;
+}
+
+/**
+ * bcm_cpu_on - Releases the secondary CPU from it's spintable
+ *
+ * Write the CPU's spintable mailbox and let the CPU enter U-Boot.
+ *
+ * @dev: Device to start
+ * @return: zero on success or error code on failure.
+ */
+static int bcm_cpu_on(struct udevice *dev)
+{
+ struct bcm_plat *plat = dev_get_plat(dev);
+ ulong *start_address;
+
+ if (plat->release_addr == ~0ULL)
+ return -ENODATA;
+
+ start_address = map_physmem(plat->release_addr, sizeof(uintptr_t), MAP_NOCACHE);
+
+ /* Point secondary CPU to U-Boot entry */
+ *start_address = (uintptr_t)_start;
+
+ /* Make sure the other CPUs see the written start address */
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ flush_dcache_all();
+
+ /* Send an event to wake up the secondary CPU. */
+ asm("dsb ishst\n"
+ "sev");
+
+ unmap_physmem(start_address, MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_bcm_ops = {
+ .get_desc = cpu_bcm_get_desc,
+ .get_info = cpu_bcm_get_info,
+ .get_count = cpu_bcm_get_count,
+ .get_vendor = cpu_bcm_get_vendor,
+ .is_current = cpu_bcm_is_current,
+};
+
+static const struct udevice_id cpu_bcm_ids[] = {
+ { .compatible = "arm,cortex-a53" }, /* RPi 3 */
+ { .compatible = "arm,cortex-a72" }, /* RPi 4 */
+ { }
+};
+
+static int bcm_cpu_bind(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+
+ plat->cpu_id = dev_read_addr(dev);
+
+ return 0;
+}
+
+/**
+ * bcm_cpu_of_to_plat - Gather spin-table release address
+ *
+ * Read the spin-table release address to allow all seconary CPUs to enter
+ * U-Boot when necessary.
+ *
+ * @dev: Device to start
+ */
+static int bcm_cpu_of_to_plat(struct udevice *dev)
+{
+ struct bcm_plat *plat = dev_get_plat(dev);
+ const char *prop;
+
+ if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
+ plat->release_addr = ~0ULL;
+
+ prop = dev_read_string(dev, "enable-method");
+ if (!prop || strcmp(prop, "spin-table"))
+ return -ENODEV;
+
+ plat->release_addr = dev_read_u64_default(dev, "cpu-release-addr", ~0ULL);
+
+ if (plat->release_addr == ~0ULL)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int bcm_cpu_probe(struct udevice *dev)
+{
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
+ struct clk clk;
+ int ret;
+
+ /* Get a clock if it exists */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ ret = clk_enable(&clk);
+ if (ret && (ret != -ENOSYS || ret != -EOPNOTSUPP))
+ return ret;
+ ret = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ plat->timebase_freq = ret;
+ }
+
+ /*
+ * The armstub holds the secondary CPUs in a spinloop. When
+ * ARMV8_MULTIENTRY is enabled release the secondary CPUs and
+ * let them enter U-Boot as well.
+ */
+ if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
+ ret = bcm_cpu_on(dev);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+struct acpi_ops bcm283x_cpu_acpi_ops = {
+ .fill_ssdt = armv8_cpu_fill_ssdt,
+ .fill_madt = armv8_cpu_fill_madt,
+};
+
+U_BOOT_DRIVER(cpu_bcm_drv) = {
+ .name = "bcm283x_cpu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_bcm_ids,
+ .ops = &cpu_bcm_ops,
+ .probe = bcm_cpu_probe,
+ .bind = bcm_cpu_bind,
+ .of_to_plat = bcm_cpu_of_to_plat,
+ .plat_auto = sizeof(struct bcm_plat),
+ ACPI_OPS_PTR(&bcm283x_cpu_acpi_ops)
+};
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 6c0a8c0..51262be 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -20,10 +20,11 @@
DECLARE_GLOBAL_DATA_PTR;
+#define IMX_REV_LEN 4
struct cpu_imx_plat {
const char *name;
- const char *rev;
const char *type;
+ char rev[IMX_REV_LEN];
u32 cpu_rsrc;
u32 cpurev;
u32 freq_mhz;
@@ -69,28 +70,29 @@
}
}
-static const char *get_imx_rev_str(u32 rev)
+static void get_imx_rev_str(struct cpu_imx_plat *plat, u32 rev)
{
- static char revision[4];
-
if (IS_ENABLED(CONFIG_IMX8)) {
switch (rev) {
case CHIP_REV_A:
- return "A";
+ plat->rev[0] = 'A';
+ break;
case CHIP_REV_B:
- return "B";
+ plat->rev[0] = 'B';
+ break;
case CHIP_REV_C:
- return "C";
+ plat->rev[0] = 'C';
+ break;
default:
- return "?";
+ plat->rev[0] = '?';
+ break;
}
+ plat->rev[1] = '\0';
} else {
- revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4);
- revision[1] = '.';
- revision[2] = '0' + (rev & 0xf);
- revision[3] = '\0';
-
- return revision;
+ plat->rev[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4);
+ plat->rev[1] = '.';
+ plat->rev[2] = '0' + (rev & 0xf);
+ plat->rev[3] = '\0';
}
}
@@ -318,7 +320,7 @@
set_core_data(dev);
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
- plat->rev = get_imx_rev_str(cpurev & 0xFFF);
+ get_imx_rev_str(plat, cpurev & 0xFFF);
plat->type = get_imx_type_str((cpurev & 0x1FF000) >> 12);
plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000;
plat->mpidr = dev_read_addr(dev);
diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig
index 473e3e5..6efcd7d 100644
--- a/drivers/crypto/aspeed/Kconfig
+++ b/drivers/crypto/aspeed/Kconfig
@@ -28,3 +28,13 @@
Enabling this allows the use of SHA operations in hardware. Note that only
SHA384 and SHA512 are supported by Caliptra 1.0.
+
+config ASPEED_CPTRA_ECDSA
+ bool "Caliptra ECDSA384 signature verifier for Aspeed SoCs"
+ depends on ECDSA_VERIFY || SPL_ECDSA_VERIFY
+ help
+ Select this option to enable a driver for using the ECDSA384_SIGNATURE_VERIFY
+ feature of Caliptra, which is integrated in AST27xx BMC SoCs.
+
+ Enabling this allows the use of ECDSA384 signature verification in hardware.
+ Note that only ECDSA384 is supported by Caliptra.
diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makefile
index 570587e..00def35 100644
--- a/drivers/crypto/aspeed/Makefile
+++ b/drivers/crypto/aspeed/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o
obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o
obj-$(CONFIG_ASPEED_CPTRA_SHA) += cptra_sha.o
+obj-$(CONFIG_ASPEED_CPTRA_ECDSA) += cptra_ecdsa.o
diff --git a/drivers/crypto/aspeed/cptra_ecdsa.c b/drivers/crypto/aspeed/cptra_ecdsa.c
new file mode 100644
index 0000000..4b70d89
--- /dev/null
+++ b/drivers/crypto/aspeed/cptra_ecdsa.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2024 ASPEED Technology Inc.
+ */
+#include <asm/io.h>
+#include <config.h>
+#include <crypto/ecdsa-uclass.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <malloc.h>
+#include <u-boot/ecdsa.h>
+
+/* SCU register offsets */
+#define SCU1_CPTRA 0x130
+#define SCU1_CPTRA_RDY_FOR_RT BIT(18)
+
+/* CPTRA MBOX register offsets */
+#define CPTRA_MBOX_LOCK 0x00
+#define CPTRA_MBOX_USER 0x04
+#define CPTRA_MBOX_CMD 0x08
+#define CPTRA_MBOX_DLEN 0x0c
+#define CPTRA_MBOX_DATAIN 0x10
+#define CPTRA_MBOX_DATAOUT 0x14
+#define CPTRA_MBOX_EXEC 0x18
+#define CPTRA_MBOX_STS 0x1c
+#define CPTRA_MBOX_STS_SOC_LOCK BIT(9)
+#define CPTRA_MBOX_STS_FSM_PS GENMASK(8, 6)
+#define CPTRA_MBOX_STS_PS GENMASK(3, 0)
+#define CPTRA_MBOX_UNLOCK 0x20
+
+#define CPTRA_ECDSA_SIG_LEN 96 /* ECDSA384 */
+#define CPTRA_ECDSA_SHA_LEN 48 /* SHA384 */
+
+#define CPTRA_MBCMD_ECDSA384_SIGNATURE_VERIFY 0x53494756
+
+enum cptra_mbox_sts {
+ CPTRA_MBSTS_CMD_BUSY,
+ CPTRA_MBSTS_DATA_READY,
+ CPTRA_MBSTS_CMD_COMPLETE,
+ CPTRA_MBSTS_CMD_FAILURE,
+};
+
+enum cptra_mbox_fsm {
+ CPTRA_MBFSM_IDLE,
+ CPTRA_MBFSM_RDY_FOR_CMD,
+ CPTRA_MBFSM_RDY_FOR_DLEN,
+ CPTRA_MBFSM_RDY_FOR_DATA,
+ CPTRA_MBFSM_EXEC_UC,
+ CPTRA_MBFSM_EXEC_SOC,
+ CPTRA_MBFSM_ERROR,
+};
+
+struct cptra_ecdsa {
+ void *regs;
+};
+
+static uint32_t mbox_csum(uint32_t csum, uint8_t *data, uint32_t dlen)
+{
+ uint32_t i;
+
+ for (i = 0; i < dlen; ++i)
+ csum -= data[i];
+
+ return csum;
+}
+
+static int cptra_ecdsa_verify(struct udevice *dev, const struct ecdsa_public_key *pubkey,
+ const void *hash, size_t hash_len,
+ const void *signature, size_t sig_len)
+{
+ struct cptra_ecdsa *ce;
+ uint8_t *x, *y, *r, *s;
+ uint32_t cmd, csum;
+ uint32_t reg, sts;
+ uint32_t *p32;
+ int i;
+
+ if (hash_len != CPTRA_ECDSA_SHA_LEN || sig_len != CPTRA_ECDSA_SIG_LEN)
+ return -EINVAL;
+
+ if ((strcmp(pubkey->curve_name, "secp384r1") && strcmp(pubkey->curve_name, "prime384v1")) ||
+ pubkey->size_bits != ((CPTRA_ECDSA_SIG_LEN / 2) << 3))
+ return -EINVAL;
+
+ ce = dev_get_priv(dev);
+
+ /* get CPTRA MBOX lock */
+ if (readl_poll_timeout(ce->regs + CPTRA_MBOX_LOCK, reg, reg == 0, 1000000))
+ return -EBUSY;
+
+ /* check MBOX is ready for command */
+ sts = readl(ce->regs + CPTRA_MBOX_STS);
+ if (FIELD_GET(CPTRA_MBOX_STS_FSM_PS, sts) != CPTRA_MBFSM_RDY_FOR_CMD)
+ return -EACCES;
+
+ /* init mbox parameters */
+ cmd = CPTRA_MBCMD_ECDSA384_SIGNATURE_VERIFY;
+ csum = 0;
+ x = (uint8_t *)pubkey->x;
+ y = (uint8_t *)pubkey->y;
+ r = (uint8_t *)signature;
+ s = (uint8_t *)signature + (CPTRA_ECDSA_SIG_LEN / 2);
+
+ /* calculate checksum */
+ csum = mbox_csum(csum, (uint8_t *)&cmd, sizeof(cmd));
+ csum = mbox_csum(csum, x, CPTRA_ECDSA_SIG_LEN / 2);
+ csum = mbox_csum(csum, y, CPTRA_ECDSA_SIG_LEN / 2);
+ csum = mbox_csum(csum, r, CPTRA_ECDSA_SIG_LEN / 2);
+ csum = mbox_csum(csum, s, CPTRA_ECDSA_SIG_LEN / 2);
+
+ /* write command, data length */
+ writel(cmd, ce->regs + CPTRA_MBOX_CMD);
+ writel(sizeof(csum) + (CPTRA_ECDSA_SIG_LEN << 1), ce->regs + CPTRA_MBOX_DLEN);
+
+ /* write ECDSA384_SIGNATURE_VERIFY command parameters */
+ writel(csum, ce->regs + CPTRA_MBOX_DATAIN);
+
+ for (i = 0, p32 = (uint32_t *)x; i < ((CPTRA_ECDSA_SIG_LEN / 2) / sizeof(*p32)); ++i)
+ writel(p32[i], ce->regs + CPTRA_MBOX_DATAIN);
+
+ for (i = 0, p32 = (uint32_t *)y; i < ((CPTRA_ECDSA_SIG_LEN / 2) / sizeof(*p32)); ++i)
+ writel(p32[i], ce->regs + CPTRA_MBOX_DATAIN);
+
+ for (i = 0, p32 = (uint32_t *)r; i < ((CPTRA_ECDSA_SIG_LEN / 2) / sizeof(*p32)); ++i)
+ writel(p32[i], ce->regs + CPTRA_MBOX_DATAIN);
+
+ for (i = 0, p32 = (uint32_t *)s; i < ((CPTRA_ECDSA_SIG_LEN / 2) / sizeof(*p32)); ++i)
+ writel(p32[i], ce->regs + CPTRA_MBOX_DATAIN);
+
+ /* trigger mbox command */
+ writel(0x1, ce->regs + CPTRA_MBOX_EXEC);
+
+ /* poll for result */
+ while (1) {
+ sts = FIELD_GET(CPTRA_MBOX_STS_PS, readl(ce->regs + CPTRA_MBOX_STS));
+ if (sts != CPTRA_MBSTS_CMD_BUSY)
+ break;
+ }
+
+ /* unlock mbox */
+ writel(0x0, ce->regs + CPTRA_MBOX_EXEC);
+
+ return (sts == CPTRA_MBSTS_CMD_FAILURE) ? sts : 0;
+}
+
+static int cptra_ecdsa_probe(struct udevice *dev)
+{
+ struct cptra_ecdsa *ce = dev_get_priv(dev);
+
+ ce->regs = (void *)devfdt_get_addr(dev);
+ if (ce->regs == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map Caliptra mailbox registers\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int cptra_ecdsa_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct ecdsa_ops cptra_ecdsa_ops = {
+ .verify = cptra_ecdsa_verify,
+};
+
+static const struct udevice_id cptra_ecdsa_ids[] = {
+ { .compatible = "aspeed,ast2700-cptra-ecdsa" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_cptra_ecdsa) = {
+ .name = "aspeed_cptra_ecdsa",
+ .id = UCLASS_ECDSA,
+ .of_match = cptra_ecdsa_ids,
+ .ops = &cptra_ecdsa_ops,
+ .probe = cptra_ecdsa_probe,
+ .remove = cptra_ecdsa_remove,
+ .priv_auto = sizeof(struct cptra_ecdsa),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index db09986..d1fc93b 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -22,6 +22,7 @@
#include <asm/io.h>
#include <linux/err.h>
#include <linux/sizes.h>
+#include <u-boot/schedule.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 9e57c2e..10a8e64 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -24,6 +24,7 @@
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/sizes.h>
+#include <u-boot/schedule.h>
#define PGTABLE_OFF 0x4000
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index b1795ee..0a45340 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -17,6 +17,11 @@
help
Enable DDR controller performance monitor counter for reference events.
+config IMX9_DRAM_INLINE_ECC
+ bool "Enable DDR INLINE ECC feature"
+ help
+ Select to enable DDR INLINE ECC feature
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index aadd7e8..604386b 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -20,6 +20,7 @@
config DFU_TFTP
bool "DFU via TFTP"
depends on NETDEVICES
+ depends on !NET_LWIP
select UPDATE_COMMON
select DFU_OVER_TFTP
help
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 7c1c0f9..8f7296a 100644
--- a/drivers/dfu/dfu_sf.c
+++ b/drivers/dfu/dfu_sf.c
@@ -123,6 +123,7 @@
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *s, *endp;
struct spi_flash *dev;
+ bool use_dt = true;
s = strsep(&devstr, ":");
if (!s || !*s || (bus = simple_strtoul(s, &endp, 0), *endp)) {
@@ -143,6 +144,8 @@
printf("Invalid SPI speed %s\n", s);
return NULL;
}
+ if (IS_ENABLED(CONFIG_DM_SPI_FLASH))
+ use_dt = false;
}
s = strsep(&devstr, ":");
@@ -152,9 +155,20 @@
printf("Invalid SPI mode %s\n", s);
return NULL;
}
+ if (IS_ENABLED(CONFIG_DM_SPI_FLASH))
+ use_dt = false;
}
- dev = spi_flash_probe(bus, cs, speed, mode);
+ if (IS_ENABLED(CONFIG_DM_SPI_FLASH) && use_dt) {
+ struct udevice *new;
+
+ if (!spi_flash_probe_bus_cs(bus, cs, &new))
+ dev = dev_get_uclass_priv(new);
+ else
+ dev = NULL;
+ } else {
+ dev = spi_flash_probe(bus, cs, speed, mode);
+ }
if (!dev) {
printf("Failed to create SPI flash at %u:%u:%u:%u\n",
bus, cs, speed, mode);
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index e23d09e..dac4023 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1700,141 +1700,6 @@
return ch_count;
}
-static int udma_probe(struct udevice *dev)
-{
- struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct udma_dev *ud = dev_get_priv(dev);
- int i, ret;
- struct udevice *tmp;
- struct udevice *tisci_dev = NULL;
- struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
- ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
-
- ud->match_data = (void *)dev_get_driver_data(dev);
- ret = udma_get_mmrs(dev);
- if (ret)
- return ret;
-
- ud->psil_base = ud->match_data->psil_base;
-
- ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
- "ti,sci", &tisci_dev);
- if (ret) {
- debug("Failed to get TISCI phandle (%d)\n", ret);
- tisci_rm->tisci = NULL;
- return -EINVAL;
- }
- tisci_rm->tisci = (struct ti_sci_handle *)
- (ti_sci_get_handle_from_sysfw(tisci_dev));
-
- tisci_rm->tisci_dev_id = -1;
- ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
- if (ret) {
- dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
- return ret;
- }
-
- tisci_rm->tisci_navss_dev_id = -1;
- ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
- &tisci_rm->tisci_navss_dev_id);
- if (ret) {
- dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
- return ret;
- }
-
- tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
- tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
-
- if (ud->match_data->type == DMA_TYPE_UDMA) {
- ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
- "ti,ringacc", &tmp);
- ud->ringacc = dev_get_priv(tmp);
- } else {
- struct k3_ringacc_init_data ring_init_data;
-
- ring_init_data.tisci = ud->tisci_rm.tisci;
- ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
- if (ud->match_data->type == DMA_TYPE_BCDMA) {
- ring_init_data.num_rings = ud->bchan_cnt +
- ud->tchan_cnt +
- ud->rchan_cnt;
- } else {
- ring_init_data.num_rings = ud->rflow_cnt +
- ud->tflow_cnt;
- }
-
- ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
- }
- if (IS_ERR(ud->ringacc))
- return PTR_ERR(ud->ringacc);
-
- ud->dev = dev;
- ret = setup_resources(ud);
- if (ret < 0)
- return ret;
-
- ud->ch_count = ret;
-
- for (i = 0; i < ud->bchan_cnt; i++) {
- struct udma_bchan *bchan = &ud->bchans[i];
-
- bchan->id = i;
- bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
- }
-
- for (i = 0; i < ud->tchan_cnt; i++) {
- struct udma_tchan *tchan = &ud->tchans[i];
-
- tchan->id = i;
- tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
- tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
- }
-
- for (i = 0; i < ud->rchan_cnt; i++) {
- struct udma_rchan *rchan = &ud->rchans[i];
-
- rchan->id = i;
- rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
- rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
- }
-
- for (i = 0; i < ud->rflow_cnt; i++) {
- struct udma_rflow *rflow = &ud->rflows[i];
-
- rflow->id = i;
- rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
- }
-
- for (i = 0; i < ud->ch_count; i++) {
- struct udma_chan *uc = &ud->channels[i];
-
- uc->ud = ud;
- uc->id = i;
- uc->config.remote_thread_id = -1;
- uc->bchan = NULL;
- uc->tchan = NULL;
- uc->rchan = NULL;
- uc->config.mapped_channel_id = -1;
- uc->config.default_flow_id = -1;
- uc->config.dir = DMA_MEM_TO_MEM;
- sprintf(uc->name, "UDMA chan%d\n", i);
- if (!i)
- uc->in_use = true;
- }
-
- pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
- dev->name,
- udma_read(ud->mmrs[MMR_GCFG], 0),
- udma_read(ud->mmrs[MMR_GCFG], 0x20),
- udma_read(ud->mmrs[MMR_GCFG], 0x24),
- udma_read(ud->mmrs[MMR_GCFG], 0x28),
- udma_read(ud->mmrs[MMR_GCFG], 0x2c));
-
- uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
-
- return 0;
-}
-
static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
{
u64 addr = 0;
@@ -2325,37 +2190,12 @@
/* Channel0 is reserved for memcpy */
struct udma_chan *uc = &ud->channels[0];
dma_addr_t paddr = 0;
- int ret;
-
- switch (ud->match_data->type) {
- case DMA_TYPE_UDMA:
- ret = udma_alloc_chan_resources(uc);
- break;
- case DMA_TYPE_BCDMA:
- ret = bcdma_alloc_chan_resources(uc);
- break;
- default:
- return -EINVAL;
- };
- if (ret)
- return ret;
udma_prep_dma_memcpy(uc, dst, src, len);
udma_start(uc);
udma_poll_completion(uc, &paddr);
udma_stop(uc);
- switch (ud->match_data->type) {
- case DMA_TYPE_UDMA:
- udma_free_chan_resources(uc);
- break;
- case DMA_TYPE_BCDMA:
- bcdma_free_bchan_resources(uc);
- break;
- default:
- return -EINVAL;
- };
-
return 0;
}
@@ -2717,6 +2557,177 @@
return -EINVAL;
}
+static int udma_probe(struct udevice *dev)
+{
+ struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct udma_dev *ud = dev_get_priv(dev);
+ int i, ret;
+ struct udevice *tmp;
+ struct udevice *tisci_dev = NULL;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ struct udma_chan *uc;
+ ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
+
+ ud->match_data = (void *)dev_get_driver_data(dev);
+ ret = udma_get_mmrs(dev);
+ if (ret)
+ return ret;
+
+ ud->psil_base = ud->match_data->psil_base;
+
+ ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+ "ti,sci", &tisci_dev);
+ if (ret) {
+ debug("Failed to get TISCI phandle (%d)\n", ret);
+ tisci_rm->tisci = NULL;
+ return -EINVAL;
+ }
+ tisci_rm->tisci = (struct ti_sci_handle *)
+ (ti_sci_get_handle_from_sysfw(tisci_dev));
+
+ tisci_rm->tisci_dev_id = -1;
+ ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
+ if (ret) {
+ dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
+ return ret;
+ }
+
+ tisci_rm->tisci_navss_dev_id = -1;
+ ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
+ &tisci_rm->tisci_navss_dev_id);
+ if (ret) {
+ dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
+ return ret;
+ }
+
+ tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
+ tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
+
+ if (ud->match_data->type == DMA_TYPE_UDMA) {
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+ "ti,ringacc", &tmp);
+ ud->ringacc = dev_get_priv(tmp);
+ } else {
+ struct k3_ringacc_init_data ring_init_data;
+
+ ring_init_data.tisci = ud->tisci_rm.tisci;
+ ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ ring_init_data.num_rings = ud->bchan_cnt +
+ ud->tchan_cnt +
+ ud->rchan_cnt;
+ } else {
+ ring_init_data.num_rings = ud->rflow_cnt +
+ ud->tflow_cnt;
+ }
+
+ ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+ }
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
+ ud->dev = dev;
+ ret = setup_resources(ud);
+ if (ret < 0)
+ return ret;
+
+ ud->ch_count = ret;
+
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->tchan_cnt; i++) {
+ struct udma_tchan *tchan = &ud->tchans[i];
+
+ tchan->id = i;
+ tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
+ tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
+ }
+
+ for (i = 0; i < ud->rchan_cnt; i++) {
+ struct udma_rchan *rchan = &ud->rchans[i];
+
+ rchan->id = i;
+ rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
+ rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
+ }
+
+ for (i = 0; i < ud->rflow_cnt; i++) {
+ struct udma_rflow *rflow = &ud->rflows[i];
+
+ rflow->id = i;
+ rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
+ }
+
+ for (i = 0; i < ud->ch_count; i++) {
+ struct udma_chan *uc = &ud->channels[i];
+
+ uc->ud = ud;
+ uc->id = i;
+ uc->config.remote_thread_id = -1;
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ uc->rchan = NULL;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+ uc->config.dir = DMA_MEM_TO_MEM;
+ sprintf(uc->name, "UDMA chan%d\n", i);
+ if (!i)
+ uc->in_use = true;
+ }
+
+ pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ dev->name,
+ udma_read(ud->mmrs[MMR_GCFG], 0),
+ udma_read(ud->mmrs[MMR_GCFG], 0x20),
+ udma_read(ud->mmrs[MMR_GCFG], 0x24),
+ udma_read(ud->mmrs[MMR_GCFG], 0x28),
+ udma_read(ud->mmrs[MMR_GCFG], 0x2c));
+
+ uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
+
+ uc = &ud->channels[0];
+ ret = 0;
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_alloc_chan_resources(uc);
+ break;
+ default:
+ break; /* Do nothing in any other case */
+ };
+
+ if (ret)
+ dev_err(dev, " Channel 0 allocation failure %d\n", ret);
+
+ return ret;
+}
+
+static int udma_remove(struct udevice *dev)
+{
+ struct udma_dev *ud = dev_get_priv(dev);
+ struct udma_chan *uc = &ud->channels[0];
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ udma_free_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ bcdma_free_bchan_resources(uc);
+ break;
+ default:
+ break;
+ };
+
+ return 0;
+}
+
static const struct dma_ops udma_ops = {
.transfer = udma_transfer,
.of_xlate = udma_of_xlate,
@@ -2855,5 +2866,7 @@
.of_match = udma_ids,
.ops = &udma_ops,
.probe = udma_probe,
+ .remove = udma_remove,
.priv_auto = sizeof(struct udma_dev),
+ .flags = DM_FLAG_OS_PREPARE,
};
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 7020757..1eb460f 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -1,5 +1,6 @@
menu "Fastboot support"
depends on CMDLINE
+ depends on !NET_LWIP
config FASTBOOT
bool
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 1e57116..92a8597 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -157,6 +157,13 @@
is found in the AST2400, AST2500 and AST2600 BMC SoCs and
provides access to over 200 GPIOs on each chip.
+config ASPEED_SGPIO
+ bool "Aspeed SGPIO Driver"
+ help
+ Say yes here to support the Aspeed serial GPIO driver. The controller
+ is found in the AST2400, AST2500 and AST2600 BMC SoCs and
+ provides access to generate serial GPIO signal.
+
config ASPEED_G7_GPIO
bool "Aspeed G7 GPIO Driver"
help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe81b6b..3f882c0 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o
obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o
+obj-$(CONFIG_ASPEED_SGPIO) += gpio-aspeed-sgpio.o
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 7a6eae9..04639a4 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -177,7 +177,9 @@
plat->base = (void *)base;
plat->bank = bank;
- plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
+
+ if (ofnode_read_u32(node, "ngpios", &plat->pins))
+ plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
new file mode 100644
index 0000000..4bbdec7
--- /dev/null
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ * Billy Tsai <billy_tsai@aspeedtech.com>
+ */
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/sizes.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+#define ASPEED_SGPIO_CTRL 0x54
+
+#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
+#define ASPEED_SGPIO_ENABLE BIT(0)
+#define ASPEED_SGPIO_PINS_SHIFT 6
+
+struct aspeed_sgpio_priv {
+ void *base;
+ struct clk pclk;
+ const struct aspeed_sgpio_pdata *pdata;
+};
+
+struct aspeed_sgpio_pdata {
+ const u32 pin_mask;
+ const struct aspeed_sgpio_llops *llops;
+};
+
+struct aspeed_sgpio_bank {
+ u16 val_regs;
+ u16 rdata_reg;
+ u16 tolerance_regs;
+ const char names[4][3];
+};
+
+/*
+ * Note: The "value" register returns the input value when the GPIO is
+ * configured as an input.
+ *
+ * The "rdata" register returns the output value when the GPIO is
+ * configured as an output.
+ */
+static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
+ {
+ .val_regs = 0x0000,
+ .rdata_reg = 0x0070,
+ .tolerance_regs = 0x0018,
+ .names = { "A", "B", "C", "D" },
+ },
+ {
+ .val_regs = 0x001C,
+ .rdata_reg = 0x0074,
+ .tolerance_regs = 0x0034,
+ .names = { "E", "F", "G", "H" },
+ },
+ {
+ .val_regs = 0x0038,
+ .rdata_reg = 0x0078,
+ .tolerance_regs = 0x0050,
+ .names = { "I", "J", "K", "L" },
+ },
+ {
+ .val_regs = 0x0090,
+ .rdata_reg = 0x007C,
+ .tolerance_regs = 0x00A8,
+ .names = { "M", "N", "O", "P" },
+ },
+};
+
+enum aspeed_sgpio_reg {
+ reg_val,
+ reg_rdata,
+ reg_tolerance,
+};
+
+struct aspeed_sgpio_llops {
+ void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg, bool val);
+ bool (*reg_bit_get)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg);
+};
+
+#define GPIO_VAL_VALUE 0x00
+
+static void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio,
+ const struct aspeed_sgpio_bank *bank,
+ const enum aspeed_sgpio_reg reg)
+{
+ switch (reg) {
+ case reg_val:
+ return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
+ case reg_rdata:
+ return gpio->base + bank->rdata_reg;
+ case reg_tolerance:
+ return gpio->base + bank->tolerance_regs;
+ default:
+ /* acturally if code runs to here, it's an error case */
+ BUG();
+ }
+}
+
+#define GPIO_BANK(x) ((x) >> 6)
+#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
+
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+{
+ unsigned int bank;
+
+ bank = GPIO_BANK(offset);
+
+ WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
+ return &aspeed_sgpio_banks[bank];
+}
+
+static bool aspeed_sgpio_is_input(unsigned int offset)
+{
+ return !(offset % 2);
+}
+
+static int aspeed_sgpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
+ enum aspeed_sgpio_reg reg;
+
+ reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
+
+ return gpio->pdata->llops->reg_bit_get(gpio, offset, reg);
+}
+
+static int aspeed_sgpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
+
+ if (aspeed_sgpio_is_input(offset))
+ return -EINVAL;
+
+ gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value);
+
+ return 0;
+}
+
+static int aspeed_sgpio_direction_input(struct udevice *dev,
+ unsigned int offset)
+{
+ return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+}
+
+static int aspeed_sgpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags)
+{
+ int ret = -EOPNOTSUPP;
+
+ if (flags & GPIOD_IS_OUT) {
+ bool value = flags & GPIOD_IS_OUT_ACTIVE;
+
+ ret = aspeed_sgpio_set_value(dev, offset, value);
+ } else if (flags & GPIOD_IS_IN) {
+ ret = aspeed_sgpio_direction_input(dev, offset);
+ }
+ return ret;
+}
+
+static int aspeed_sgpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ return aspeed_sgpio_is_input(offset) ? GPIOF_INPUT : GPIOF_OUTPUT;
+}
+
+static void aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg, bool val)
+{
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr = bank_reg(gpio, bank, reg);
+ u32 temp;
+
+ if (reg == reg_val)
+ /* Since this is an output, read the cached value from rdata, then update val. */
+ temp = readl(bank_reg(gpio, bank, reg_rdata));
+ else
+ temp = readl(addr);
+
+ if (val)
+ temp |= GPIO_BIT(offset);
+ else
+ temp &= ~GPIO_BIT(offset);
+
+ writel(temp, addr);
+}
+
+static bool aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv *gpio, unsigned int offset,
+ const enum aspeed_sgpio_reg reg)
+{
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr = bank_reg(gpio, bank, reg);
+
+ return !!(readl(addr) & GPIO_BIT(offset));
+}
+
+static const struct aspeed_sgpio_llops aspeed_g4_llops = {
+ .reg_bit_set = aspeed_g4_reg_bit_set,
+ .reg_bit_get = aspeed_g4_reg_bit_get,
+};
+
+static const struct dm_gpio_ops aspeed_sgpio_ops = {
+ .get_value = aspeed_sgpio_get_value,
+ .set_value = aspeed_sgpio_set_value,
+ .get_function = aspeed_sgpio_get_function,
+ .set_flags = aspeed_sgpio_set_flags,
+};
+
+static int aspeed_sgpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct aspeed_sgpio_priv *priv = dev_get_priv(dev);
+ u32 sgpio_freq, sgpio_clk_div, nr_gpios, gpio_cnt_regval, pin_mask;
+ ulong apb_freq;
+ int ret;
+
+ priv->base = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev);
+ if (!priv->pdata)
+ return -EINVAL;
+
+ pin_mask = priv->pdata->pin_mask;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios);
+ if (ret < 0) {
+ dev_err(dev, "Could not read ngpios property\n");
+ return -EINVAL;
+ } else if (nr_gpios % 8) {
+ dev_err(dev, "Number of GPIOs not multiple of 8: %d\n",
+ nr_gpios);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq);
+ if (ret < 0) {
+ dev_err(dev, "Could not read bus-frequency property\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_index(dev, 0, &priv->pclk);
+ if (ret < 0) {
+ dev_err(dev, "get clock failed\n");
+ return ret;
+ }
+
+ apb_freq = clk_get_rate(&priv->pclk);
+
+ /*
+ * From the datasheet,
+ * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
+ * period = 2 * (GPIO254[31:16] + 1) / PCLK
+ * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
+ * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
+ * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
+ * GPIO254[31:16] = PCLK / (frequency * 2) - 1
+ */
+ if (sgpio_freq == 0)
+ return -EINVAL;
+
+ sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
+
+ if (sgpio_clk_div > (1 << 16) - 1)
+ return -EINVAL;
+
+ gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
+ writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+ ASPEED_SGPIO_ENABLE, priv->base + ASPEED_SGPIO_CTRL);
+
+ uc_priv->bank_name = dev->name;
+ uc_priv->gpio_count = nr_gpios * 2;
+
+ return 0;
+}
+
+static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
+ .pin_mask = GENMASK(9, 6),
+ .llops = &aspeed_g4_llops,
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
+ .pin_mask = GENMASK(10, 6),
+ .llops = &aspeed_g4_llops,
+};
+
+static const struct udevice_id aspeed_sgpio_ids[] = {
+ { .compatible = "aspeed,ast2400-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2500-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2600-sgpiom", .data = (ulong)&ast2600_sgpiom_pdata, },
+};
+
+U_BOOT_DRIVER(sgpio_aspeed) = {
+ .name = "sgpio-aspeed",
+ .id = UCLASS_GPIO,
+ .of_match = aspeed_sgpio_ids,
+ .ops = &aspeed_sgpio_ops,
+ .probe = aspeed_sgpio_probe,
+ .priv_auto = sizeof(struct aspeed_sgpio_priv),
+};
diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c
index 42e7fe9..b6f533b 100644
--- a/drivers/gpio/mcp230xx_gpio.c
+++ b/drivers/gpio/mcp230xx_gpio.c
@@ -14,6 +14,7 @@
#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <dt-bindings/gpio/gpio.h>
+#include <linux/delay.h>
enum mcp230xx_type {
UNKNOWN = 0,
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c
index e0a575f..00aef40 100644
--- a/drivers/i2c/i2c-gpio.c
+++ b/drivers/i2c/i2c-gpio.c
@@ -101,7 +101,7 @@
bus->set_scl(bus, 1);
udelay(delay);
- value = bus->get_sda(bus);
+ value = bus->get_sda ? bus->get_sda(bus) : 0;
udelay(delay);
bus->set_scl(bus, 0);
udelay(2 * delay);
@@ -256,6 +256,9 @@
{
unsigned int delay = bus->udelay;
+ if (!bus->get_sda)
+ return -EOPNOTSUPP;
+
debug("%s: chip %x buffer: %p len %d\n", __func__, chip, buffer, len);
while (len-- > 0)
@@ -353,7 +356,10 @@
bus->udelay = dev_read_u32_default(dev, "i2c-gpio,delay-us",
DEFAULT_UDELAY);
- bus->get_sda = i2c_gpio_sda_get;
+ if (dev_read_bool(dev, "i2c-gpio,sda-output-only"))
+ bus->get_sda = NULL;
+ else
+ bus->get_sda = i2c_gpio_sda_get;
bus->set_sda = i2c_gpio_sda_set;
if (dev_read_bool(dev, "i2c-gpio,scl-output-only"))
bus->set_scl = i2c_gpio_scl_set_output_only;
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 323c4fb..cd5579a 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -36,6 +36,11 @@
device. Supported chips are PCA9543, PCA9544, PCA9546, PCA9547,
PCA9548 and PCA9646.
+ It's also compatible to Maxims MAX735x I2C switch chips, which are controlled
+ as the NXP PCA9548 and the MAX736x chips that act like the PCA9544.
+ This includes the:
+ MAX7356, MAX7357, MAX7358, MAX7367, MAX7368 and MAX7369
+
config I2C_MUX_GPIO
tristate "GPIO-based I2C multiplexer"
depends on I2C_MUX && DM_GPIO
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 795288f..9dd2697 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -14,6 +14,12 @@
#include <asm-generic/gpio.h>
enum pca_type {
+ MAX7356,
+ MAX7357,
+ MAX7358,
+ MAX7367,
+ MAX7368,
+ MAX7369,
PCA9543,
PCA9544,
PCA9546,
@@ -39,6 +45,31 @@
};
static const struct chip_desc chips[] = {
+ [MAX7356] = {
+ .muxtype = pca954x_isswi,
+ .width = 8,
+ },
+ [MAX7357] = {
+ .muxtype = pca954x_isswi,
+ .width = 8,
+ },
+ [MAX7358] = {
+ .muxtype = pca954x_isswi,
+ .width = 8,
+ },
+ [MAX7367] = {
+ .muxtype = pca954x_isswi,
+ .width = 4,
+ },
+ [MAX7368] = {
+ .muxtype = pca954x_isswi,
+ .width = 4,
+ },
+ [MAX7369] = {
+ .enable = 0x4,
+ .muxtype = pca954x_ismux,
+ .width = 4,
+ },
[PCA9543] = {
.muxtype = pca954x_isswi,
.width = 2,
@@ -102,6 +133,12 @@
};
static const struct udevice_id pca954x_ids[] = {
+ { .compatible = "maxim,max7356", .data = MAX7356 },
+ { .compatible = "maxim,max7357", .data = MAX7357 },
+ { .compatible = "maxim,max7358", .data = MAX7358 },
+ { .compatible = "maxim,max7367", .data = MAX7367 },
+ { .compatible = "maxim,max7368", .data = MAX7368 },
+ { .compatible = "maxim,max7369", .data = MAX7369 },
{ .compatible = "nxp,pca9543", .data = PCA9543 },
{ .compatible = "nxp,pca9544", .data = PCA9544 },
{ .compatible = "nxp,pca9546", .data = PCA9546 },
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 2f3cb59..2dfc1c4 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -29,7 +29,6 @@
#include <watchdog.h>
#include <dm.h>
#include <dm/pinctrl.h>
-#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -867,8 +866,7 @@
static int mxc_i2c_probe(struct udevice *bus)
{
struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(bus);
+ ofnode node = dev_ofnode(bus);
fdt_addr_t addr;
int ret, ret2;
@@ -912,17 +910,15 @@
* See Documentation/devicetree/bindings/i2c/i2c-imx.txt
* Use gpio to force bus idle when necessary.
*/
- ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
+ ret = ofnode_stringlist_search(node, "pinctrl-names", "gpio");
if (ret < 0) {
debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
dev_seq(bus), i2c_bus->base);
} else {
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
- "scl-gpios", 0, &i2c_bus->scl_gpio,
- GPIOD_IS_OUT);
- ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
- "sda-gpios", 0, &i2c_bus->sda_gpio,
- GPIOD_IS_OUT);
+ ret = gpio_request_by_name(bus, "scl-gpios", 0, &i2c_bus->scl_gpio,
+ GPIOD_IS_OUT);
+ ret2 = gpio_request_by_name(bus, "sda-gpios", 0, &i2c_bus->sda_gpio,
+ GPIOD_IS_OUT);
if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
!dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
ret || ret2) {
diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c
index 5f3f8d1..f292c82 100644
--- a/drivers/i2c/rz_riic.c
+++ b/drivers/i2c/rz_riic.c
@@ -14,6 +14,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <reset.h>
+#include <u-boot/schedule.h>
#include <wait_bit.h>
#define RIIC_ICCR1 0x00
diff --git a/drivers/led/led_sw_blink.c b/drivers/led/led_sw_blink.c
index 06a43db..ee1546d 100644
--- a/drivers/led/led_sw_blink.c
+++ b/drivers/led/led_sw_blink.c
@@ -5,6 +5,7 @@
* Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
*/
+#include <cyclic.h>
#include <dm.h>
#include <led.h>
#include <time.h>
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index d10edd2..7c40f17 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -39,7 +39,7 @@
config TI_AEMIF
tristate "Texas Instruments AEMIF driver"
- depends on ARCH_KEYSTONE
+ depends on ARCH_KEYSTONE || ARCH_DAVINCI
help
This driver is for the AEMIF module available in Texas Instruments
SoCs. AEMIF stands for Asynchronous External Memory Interface and
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 1cabf8a..fdc83e4 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -3,5 +3,5 @@
obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o
-obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
+obj-$(CONFIG_TI_AEMIF) += ti-aemif.o ti-aemif-cs.o
obj-$(CONFIG_TI_GPMC) += ti-gpmc.o
diff --git a/drivers/memory/ti-aemif-cs.c b/drivers/memory/ti-aemif-cs.c
new file mode 100644
index 0000000..0fcfee6
--- /dev/null
+++ b/drivers/memory/ti-aemif-cs.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DaVinci / Keystone2 : AEMIF's chip select configuration
+ *
+ */
+#include <asm/io.h>
+#include <clk.h>
+#include <div64.h>
+#include <dm.h>
+#include "ti-aemif-cs.h"
+
+#define AEMIF_CONFIG(cs) (0x10 + ((cs) * 4))
+
+#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
+#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
+#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
+#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
+#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
+#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
+#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
+#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
+#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
+#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
+
+#define SSTROBE_EN 0x1
+#define EW_EN 0x1
+
+#define WSETUP_MAX 0xf
+#define WSTROBE_MAX 0x3f
+#define WHOLD_MAX 0x7
+#define RSETUP_MAX 0xf
+#define RSTROBE_MAX 0x3f
+#define RHOLD_MAX 0x7
+#define TA_MAX 0x3
+
+#define WIDTH_8BITS 0x0
+#define WIDTH_16BITS 0x1
+
+#define set_config_field(reg, field, val) \
+ do { \
+ if ((val) != -1) { \
+ (reg) &= ~AEMIF_CFG_##field(0xffffffff); \
+ (reg) |= AEMIF_CFG_##field((val)); \
+ } \
+ } while (0)
+
+void aemif_cs_configure(int cs, struct aemif_config *cfg)
+{
+ unsigned long tmp;
+
+ tmp = __raw_readl(cfg->base + AEMIF_CONFIG(cs));
+
+ set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
+ set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
+ set_config_field(tmp, WR_SETUP, cfg->wr_setup);
+ set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
+ set_config_field(tmp, WR_HOLD, cfg->wr_hold);
+ set_config_field(tmp, RD_SETUP, cfg->rd_setup);
+ set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
+ set_config_field(tmp, RD_HOLD, cfg->rd_hold);
+ set_config_field(tmp, TURN_AROUND, cfg->turn_around);
+ set_config_field(tmp, WIDTH, cfg->width);
+
+ __raw_writel(tmp, cfg->base + AEMIF_CONFIG(cs));
+}
+
+struct ti_aemif_cs {
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static unsigned int aemif_calc_cfg(ulong rate, u64 timing_ns, u32 max_cfg)
+{
+ u64 result;
+
+ if (!timing_ns)
+ return 0;
+
+ result = DIV_ROUND_UP_ULL(timing_ns * rate, 1000000000ULL);
+
+ if (result - 1 > max_cfg)
+ return max_cfg;
+
+ return result - 1;
+}
+
+static int aemif_cs_set_timings(struct udevice *dev)
+{
+ struct ti_aemif_cs *priv = dev_get_priv(dev);
+ ulong rate = clk_get_rate(priv->clk);
+ struct aemif_config cfg = {};
+ u32 val;
+ u32 cs;
+
+ if (dev_read_u32(dev, "ti,cs-chipselect", &cs))
+ return -EINVAL;
+
+/*
+ * On DaVinci SoCs, chipselect is in range [2-5]
+ * On Keystone SoCs, chipselect is in range [0-3]
+ * The logic to access the configuration registers expects the CS to be in the
+ * Keystone range so a -2 offset is applied on DaVinci SoCs
+ */
+ if (IS_ENABLED(CONFIG_ARCH_DAVINCI)) {
+ if (cs < 2 || cs > 5)
+ return -EINVAL;
+ cs -= 2;
+ } else if (IS_ENABLED(CONFIG_ARCH_KEYSTONE)) {
+ if (cs > 3)
+ return -EINVAL;
+ }
+
+ if (dev_read_bool(dev, "ti,cs-select-strobe-mode"))
+ cfg.select_strobe = SSTROBE_EN;
+
+ if (dev_read_bool(dev, "ti,cs-extended-wait-mode"))
+ cfg.extend_wait = EW_EN;
+
+ val = dev_read_u32_default(dev, "ti,cs-write-setup-ns", U32_MAX);
+ cfg.wr_setup = aemif_calc_cfg(rate, val, WSETUP_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-write-strobe-ns", U32_MAX);
+ cfg.wr_strobe = aemif_calc_cfg(rate, val, WSTROBE_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-write-hold-ns", U32_MAX);
+ cfg.wr_hold = aemif_calc_cfg(rate, val, WHOLD_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-setup-ns", U32_MAX);
+ cfg.rd_setup = aemif_calc_cfg(rate, val, RSETUP_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-strobe-ns", U32_MAX);
+ cfg.rd_strobe = aemif_calc_cfg(rate, val, RSTROBE_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-read-hold-ns", U32_MAX);
+ cfg.rd_hold = aemif_calc_cfg(rate, val, RHOLD_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-min-turnaround-ns", U32_MAX);
+ cfg.turn_around = aemif_calc_cfg(rate, val, TA_MAX);
+
+ val = dev_read_u32_default(dev, "ti,cs-bus-width", 8);
+ if (val == 16)
+ cfg.width = WIDTH_16BITS;
+ else
+ cfg.width = WIDTH_8BITS;
+
+ cfg.base = priv->base;
+ aemif_cs_configure(cs, &cfg);
+
+ return 0;
+}
+
+static int aemif_cs_probe(struct udevice *dev)
+{
+ struct ti_aemif_cs *priv = dev_get_priv(dev);
+ struct udevice *aemif;
+
+ aemif = dev_get_parent(dev);
+ if (!aemif)
+ return -ENODEV;
+
+ priv->base = dev_read_addr_ptr(aemif);
+ if (!priv->base)
+ return -EINVAL;
+
+ priv->clk = devm_clk_get(aemif, "aemif");
+ if (IS_ERR(priv->clk))
+ return -EINVAL;
+
+ return aemif_cs_set_timings(dev);
+}
+
+static const struct udevice_id aemif_cs_ids[] = {
+ { .compatible = "ti,da850-aemif-cs", },
+ {},
+};
+
+U_BOOT_DRIVER(ti_aemif_cs) = {
+ .name = "ti_aemif_cs",
+ .id = UCLASS_MEMORY,
+ .of_match = aemif_cs_ids,
+ .probe = aemif_cs_probe,
+ .priv_auto = sizeof(struct ti_aemif_cs),
+};
diff --git a/drivers/memory/ti-aemif-cs.h b/drivers/memory/ti-aemif-cs.h
new file mode 100644
index 0000000..62e6c6e
--- /dev/null
+++ b/drivers/memory/ti-aemif-cs.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#include <asm/ti-common/ti-aemif.h>
+
+void aemif_cs_configure(int cs, struct aemif_config *cfg);
diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c
index 29131f5..b26423c 100644
--- a/drivers/memory/ti-aemif.c
+++ b/drivers/memory/ti-aemif.c
@@ -7,61 +7,31 @@
*/
#include <asm/arch/hardware.h>
+#include <asm/io.h>
#include <asm/ti-common/ti-aemif.h>
+#include <dm.h>
+#include "ti-aemif-cs.h"
-#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4)
-#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60)
-#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c)
-#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4))
-
-#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~AEMIF_CFG_##field(0xffffffff); \
- reg |= AEMIF_CFG_##field(val); \
- } \
- } while (0)
+#define AEMIF_WAITCYCLE_CONFIG (0x4)
+#define AEMIF_NAND_CONTROL (0x60)
+#define AEMIF_ONENAND_CONTROL (0x5c)
static void aemif_configure(int cs, struct aemif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == AEMIF_MODE_NAND) {
- tmp = __raw_readl(AEMIF_NAND_CONTROL);
+ tmp = __raw_readl(cfg->base + AEMIF_NAND_CONTROL);
tmp |= (1 << cs);
- __raw_writel(tmp, AEMIF_NAND_CONTROL);
+ __raw_writel(tmp, cfg->base + AEMIF_NAND_CONTROL);
} else if (cfg->mode == AEMIF_MODE_ONENAND) {
- tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
+ tmp = __raw_readl(cfg->base + AEMIF_ONENAND_CONTROL);
tmp |= (1 << cs);
- __raw_writel(tmp, AEMIF_ONENAND_CONTROL);
+ __raw_writel(tmp, cfg->base + AEMIF_ONENAND_CONTROL);
}
- tmp = __raw_readl(AEMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, AEMIF_CONFIG(cs));
+ aemif_cs_configure(cs, cfg);
}
void aemif_init(int num_cs, struct aemif_config *config)
@@ -76,3 +46,14 @@
for (cs = 0; cs < num_cs; cs++)
aemif_configure(cs, config + cs);
}
+
+static const struct udevice_id aemif_ids[] = {
+ { .compatible = "ti,da850-aemif", },
+ {},
+};
+
+U_BOOT_DRIVER(ti_aemif) = {
+ .name = "ti_aemif",
+ .id = UCLASS_MEMORY,
+ .of_match = aemif_ids,
+};
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index 79eb7c2..ac77859 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -62,6 +62,40 @@
return ops->read_and_clear(irq);
}
+int irq_get_interrupt_parent(const struct udevice *dev,
+ struct udevice **interrupt_parent)
+{
+ struct ofnode_phandle_args phandle_args;
+ struct udevice *irq = NULL;
+ ofnode node;
+ int ret;
+
+ if (!dev || !interrupt_parent)
+ return -EINVAL;
+
+ *interrupt_parent = NULL;
+
+ node = dev_ofnode(dev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ while (ofnode_valid(node)) {
+ ret = ofnode_parse_phandle_with_args(node, "interrupt-parent",
+ NULL, 0, 0, &phandle_args);
+ if (!ret && !device_get_global_by_ofnode(phandle_args.node, &irq))
+ break;
+ node = ofnode_get_parent(node);
+ }
+
+ if (!irq) {
+ log_err("Cannot find an interrupt parent for device %s\n", dev->name);
+ return -ENODEV;
+ }
+ *interrupt_parent = irq;
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(OF_PLATDATA)
int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells,
struct irq *irq)
@@ -142,10 +176,40 @@
int irq_get_by_index(struct udevice *dev, int index, struct irq *irq)
{
struct ofnode_phandle_args args;
- int ret;
+ struct udevice *interrupt_parent;
+ int ret, size, i;
+ const __be32 *list;
+ u32 count;
ret = dev_read_phandle_with_args(dev, "interrupts-extended",
"#interrupt-cells", 0, index, &args);
+ if (ret) {
+ list = dev_read_prop(dev, "interrupts", &size);
+ if (!list)
+ return -ENOENT;
+
+ ret = irq_get_interrupt_parent(dev, &interrupt_parent);
+ if (ret)
+ return -ENODEV;
+ args.node = dev_ofnode(interrupt_parent);
+
+ if (dev_read_u32(interrupt_parent, "#interrupt-cells", &count)) {
+ log_err("%s: could not get #interrupt-cells for %s\n",
+ __func__, dev->name);
+ return -ENOENT;
+ }
+
+ if (index * count >= size / sizeof(*list))
+ return -ENOENT;
+ if (count > OF_MAX_PHANDLE_ARGS)
+ count = OF_MAX_PHANDLE_ARGS;
+ args.args_count = count;
+ for (i = 0; i < count; i++)
+ args.args[i] = be32_to_cpup(&list[index * count + i]);
+
+ return irq_get_by_index_tail(ret, dev_ofnode(dev), &args,
+ "interrupts", index, irq);
+ }
return irq_get_by_index_tail(ret, dev_ofnode(dev), &args,
"interrupts-extended", index > 0, irq);
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 87471cc..99a18a1 100644
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
@@ -352,6 +352,9 @@
struct k3_avs_privdata *priv;
struct vd_data *vd;
int ret;
+ ofnode node;
+ struct ofnode_phandle_args phandle_args;
+ int i = 0;
priv = dev_get_priv(dev);
priv->dev = dev;
@@ -367,6 +370,32 @@
return -ENODEV;
for (vd = priv->vd_config->vds; vd->id >= 0; vd++) {
+ /* Get the clock and dev id for Jacinto platforms */
+ if (vd->id == J721E_VDD_MPU) {
+ node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc");
+ if (!ofnode_valid(node))
+ return -ENODEV;
+
+ i = ofnode_stringlist_search(node, "clock-names", "core");
+ if (i < 0)
+ return -ENODEV;
+
+ ret = ofnode_parse_phandle_with_args(node, "clocks",
+ "#clock-cells",
+ 0, i,
+ &phandle_args);
+ if (ret) {
+ printf("Couldn't get the clock node, ret = %d\n", ret);
+ return ret;
+ }
+
+ vd->dev_id = phandle_args.args[0];
+ vd->clk_id = phandle_args.args[1];
+
+ debug("%s: MPU dev_id: %d, clk_id: %d", __func__,
+ vd->dev_id, vd->clk_id);
+ }
+
if (!(readl(AM6_VTM_DEVINFO(vd->id)) &
AM6_VTM_AVS0_SUPPORTED)) {
dev_warn(dev, "AVS-class 0 not supported for VD%d\n",
@@ -391,7 +420,10 @@
if (vd->flags & VD_FLAG_INIT_DONE)
continue;
- k3_avs_program_voltage(priv, vd, vd->opp);
+ ret = k3_avs_program_voltage(priv, vd, vd->opp);
+ if (ret)
+ dev_warn(dev, "Could not program AVS voltage for VD%d, vd->opp=%d, ret=%d\n",
+ vd->id, vd->opp, ret);
}
if (!device_is_compatible(priv->dev, "ti,am654-avs"))
@@ -460,6 +492,12 @@
{
.id = J721E_VDD_MPU,
.opp = AM6_OPP_NOM,
+ /*
+ * XXX: DEPRECATION WARNING: Around 2 u-boot versions
+ *
+ * These values will be picked up from DT, kept for backward
+ * compatibility
+ */
.dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
.clk_id = 2, /* ARM clock */
.opps = {
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index fb410104..d7a45ef0 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1398,8 +1398,7 @@
struct udevice *vqmmc_dev;
int ret;
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ ofnode node = dev_ofnode(dev);
fdt_addr_t addr;
unsigned int val;
@@ -1413,15 +1412,15 @@
priv->dev = dev;
priv->mode = -1;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+ val = ofnode_read_u32_default(node, "fsl,tuning-step", 1);
priv->tuning_step = val;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
- ESDHC_TUNING_START_TAP_DEFAULT);
+ val = ofnode_read_u32_default(node, "fsl,tuning-start-tap",
+ ESDHC_TUNING_START_TAP_DEFAULT);
priv->tuning_start_tap = val;
- val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ val = ofnode_read_u32_default(node, "fsl,strobe-dll-delay-target",
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
priv->strobe_dll_delay_target = val;
- val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
+ val = ofnode_read_u32_default(node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
priv->signal_voltage_switch_extra_delay_ms = val;
if (dev_read_bool(dev, "broken-cd"))
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 23db2a7..92afa6a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -864,6 +864,7 @@
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,rzg2l-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
};
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 63b0fd8..ca60a42 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -176,6 +176,11 @@
help
Add support for various Macronix SPI flash chips (MX25Lxxx)
+config SPI_FLASH_PUYA
+ bool "Puya Semiconductor SPI flash support"
+ help
+ Add support for various Puya Semiconductor SPI flash chips (P25xxx)
+
config SPI_FLASH_SILICONKAISER
bool "Silicon Kaiser SPI flash support"
help
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f5c9868..ec841fb 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1134,12 +1134,10 @@
offset /= 2;
if (nor->flags & SNOR_F_HAS_STACKED) {
- if (offset >= (mtd->size / 2)) {
- offset = offset - (mtd->size / 2);
+ if (offset >= (mtd->size / 2))
nor->spi->flags |= SPI_XFER_U_PAGE;
- } else {
+ else
nor->spi->flags &= ~SPI_XFER_U_PAGE;
- }
}
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
@@ -1588,23 +1586,22 @@
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
if ((nor->flags & SNOR_F_HAS_PARALLEL) && (offset & 1)) {
- /* We can hit this case when we use file system like ubifs */
+ /* We can hit this case when we use file system like ubifs */
from--;
len++;
is_ofst_odd = true;
}
while (len) {
- if (nor->addr_width == 3) {
- if (nor->flags & SNOR_F_HAS_PARALLEL) {
- bank = (u32)from / (SZ_16M << 0x01);
- rem_bank_len = ((SZ_16M << 0x01) *
- (bank + 1)) - from;
- } else {
- bank = (u32)from / SZ_16M;
- rem_bank_len = (SZ_16M * (bank + 1)) - from;
- }
- }
+ bank = (u32)from / SZ_16M;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ bank /= 2;
+
+ rem_bank_len = SZ_16M * (bank + 1);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ rem_bank_len *= 2;
+ rem_bank_len -= from;
+
offset = from;
if (nor->flags & SNOR_F_HAS_STACKED) {
@@ -1619,13 +1616,11 @@
if (nor->flags & SNOR_F_HAS_PARALLEL)
offset /= 2;
- if (nor->addr_width == 3) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = write_bar(nor, offset);
- if (ret < 0)
- return log_ret(ret);
+ ret = write_bar(nor, offset);
+ if (ret < 0)
+ return log_ret(ret);
#endif
- }
if (len < rem_bank_len)
read_len = len;
@@ -1635,10 +1630,6 @@
if (read_len == 0)
return -EIO;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto read_err;
-
ret = nor->read(nor, offset, read_len, buf);
if (ret == 0) {
/* We shouldn't see 0-length reads */
@@ -1977,9 +1968,9 @@
return ret;
*retlen += 1; /* We've written only one actual byte */
- ++buf;
- --len;
- ++to;
+ buf++;
+ len--;
+ to++;
}
for (i = 0; i < len; ) {
@@ -1999,7 +1990,7 @@
page_offset = do_div(aux, nor->page_size);
}
- offset = (to + i);
+ offset = to + i;
if (nor->flags & SNOR_F_HAS_PARALLEL)
offset /= 2;
@@ -2012,21 +2003,16 @@
}
}
- if (nor->addr_width == 3) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = write_bar(nor, offset);
- if (ret < 0)
- return ret;
+ ret = write_bar(nor, offset);
+ if (ret < 0)
+ return ret;
#endif
- }
+
/* the size of data remaining on the first page */
page_remain = min_t(size_t,
nor->page_size - page_offset, len - i);
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto write_err;
-
write_enable(nor);
/*
* On DTR capable flashes like Micron Xcella the writes cannot
@@ -2086,10 +2072,6 @@
if (ret)
goto write_err;
- ret = write_disable(nor);
- if (ret)
- goto write_err;
-
*retlen += written;
i += written;
}
@@ -2130,10 +2112,6 @@
if (ret)
return ret;
- ret = write_disable(nor);
- if (ret)
- return ret;
-
ret = read_sr(nor);
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
@@ -2195,7 +2173,7 @@
return -EINVAL;
}
- return write_disable(nor);
+ return 0;
}
#endif
@@ -3069,13 +3047,6 @@
const struct flash_info *info,
struct spi_nor_flash_parameter *params)
{
-#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE)
- struct udevice *dev = nor->spi->dev;
- u64 flash_size[SNOR_FLASH_CNT_MAX] = {0};
- u32 idx = 0, i = 0;
- int rc;
-#endif
-
/* Set legacy flash parameters as default. */
memset(params, 0, sizeof(*params));
@@ -3194,62 +3165,71 @@
spi_nor_post_sfdp_fixups(nor, params);
}
-#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE)
- /*
- * The flashes that are connected in stacked mode should be of same make.
- * Except the flash size all other properties are identical for all the
- * flashes connected in stacked mode.
- * The flashes that are connected in parallel mode should be identical.
- */
- while (i < SNOR_FLASH_CNT_MAX) {
- rc = ofnode_read_u64_index(dev_ofnode(dev), "stacked-memories",
- idx, &flash_size[i]);
- if (rc == -EINVAL) {
- break;
- } else if (rc == -EOVERFLOW) {
- idx++;
- } else {
- idx++;
- i++;
- if (!(nor->flags & SNOR_F_HAS_STACKED))
- nor->flags |= SNOR_F_HAS_STACKED;
- if (!(nor->spi->flags & SPI_XFER_STACKED))
- nor->spi->flags |= SPI_XFER_STACKED;
+
+#if CONFIG_IS_ENABLED(DM_SPI)
+ if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) {
+ u64 flash_size[SNOR_FLASH_CNT_MAX] = { 0 };
+ struct udevice *dev = nor->spi->dev;
+ u32 idx = 0, i = 0;
+ int rc;
+
+ /*
+ * The flashes that are connected in stacked mode should be of same make.
+ * Except the flash size all other properties are identical for all the
+ * flashes connected in stacked mode.
+ * The flashes that are connected in parallel mode should be identical.
+ */
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = ofnode_read_u64_index(dev_ofnode(dev), "stacked-memories",
+ idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_STACKED))
+ nor->flags |= SNOR_F_HAS_STACKED;
+ if (!(nor->spi->flags & SPI_XFER_STACKED))
+ nor->spi->flags |= SPI_XFER_STACKED;
+ }
}
- }
- i = 0;
- idx = 0;
- while (i < SNOR_FLASH_CNT_MAX) {
- rc = ofnode_read_u64_index(dev_ofnode(dev), "parallel-memories",
- idx, &flash_size[i]);
- if (rc == -EINVAL) {
- break;
- } else if (rc == -EOVERFLOW) {
- idx++;
- } else {
- idx++;
- i++;
- if (!(nor->flags & SNOR_F_HAS_PARALLEL))
- nor->flags |= SNOR_F_HAS_PARALLEL;
+ i = 0;
+ idx = 0;
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = ofnode_read_u64_index(dev_ofnode(dev), "parallel-memories",
+ idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL))
+ nor->flags |= SNOR_F_HAS_PARALLEL;
+ }
}
- }
- if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
- params->size = 0;
- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++)
- params->size += flash_size[idx];
- }
- /*
- * In parallel-memories the erase operation is
- * performed on both the flashes simultaneously
- * so, double the erasesize.
- */
- if (nor->flags & SNOR_F_HAS_PARALLEL) {
- nor->mtd.erasesize <<= 1;
- params->page_size <<= 1;
+ if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
+ params->size = 0;
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++)
+ params->size += flash_size[idx];
+ }
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ nor->mtd.erasesize <<= 1;
+ params->page_size <<= 1;
+ }
}
#endif
+
spi_nor_late_init_fixups(nor, params);
return 0;
@@ -3599,19 +3579,6 @@
mtd->erasesize = info->sector_size;
}
- if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) {
- nor->erase_opcode = SPINOR_OP_BE_4K;
- /*
- * In parallel-memories the erase operation is
- * performed on both the flashes simultaneously
- * so, double the erasesize.
- */
- if (nor->flags & SNOR_F_HAS_PARALLEL)
- mtd->erasesize = 4096 * 2;
- else
- mtd->erasesize = 4096;
- }
-
return 0;
}
@@ -4606,7 +4573,6 @@
#else
/* Configure the BAR - discover bank cmds and read current bank */
nor->addr_width = 3;
- set_4byte(nor, info, 0);
ret = read_bar(nor, info);
if (ret < 0)
return ret;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index dfe92c3..91ae49c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -294,6 +294,36 @@
{ INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
#endif
+#ifdef CONFIG_SPI_FLASH_PUYA
+ /* Puya Semiconductor (Shanghai) Co., Ltd */
+ { INFO
+ ("p25q05h", 0x856010, 0, 64 * 1024, 1,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q10h", 0x856011, 0, 64 * 1024, 2,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q20h", 0x856012, 0, 64 * 1024, 4,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q40h", 0x856013, 0, 64 * 1024, 8,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q80h", 0x856014, 0, 64 * 1024, 16,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q16h", 0x856015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q32h", 0x856016, 0, 64 * 1024, 64,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q64h", 0x856017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO
+ ("p25q128h", 0x856018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+#endif
#ifdef CONFIG_SPI_FLASH_SILICONKAISER
{ INFO("sk25lp128", 0x257018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@@ -328,6 +358,7 @@
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
{ INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 88ef674..576cd2d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -48,6 +48,7 @@
bool "Enable Driver Model for DSA switches"
depends on DM_MDIO
depends on PHY_FIXED
+ depends on !NET_LWIP
help
Enable driver model for DSA switches
@@ -96,7 +97,7 @@
menuconfig NETDEVICES
bool "Network device support"
- depends on NET
+ depends on NET || NET_LWIP
select DM_ETH
help
You must select Y to enable any network device support
@@ -342,6 +343,7 @@
config ETH_SANDBOX
depends on SANDBOX
+ depends on NET
default y
bool "Sandbox: Mocked Ethernet driver"
help
@@ -363,6 +365,7 @@
config ETH_SANDBOX_RAW
depends on SANDBOX
+ depends on NET
default y
bool "Sandbox: Bridge to Linux Raw Sockets"
help
@@ -522,11 +525,11 @@
The Microchip KS8851 parallel bus external ethernet interface chip.
config KSZ9477
- bool "Microchip KSZ9477 I2C controller driver"
- depends on DM_DSA && DM_I2C
+ bool "Microchip KSZ9477 controller driver"
+ depends on DM_DSA && (DM_I2C || DM_SPI)
help
This driver implements a DSA switch driver for the KSZ9477 family
- of GbE switches using the I2C interface.
+ of GbE switches using the I2C or SPI interface.
config LITEETH
bool "LiteX LiteEth Ethernet MAC"
@@ -759,6 +762,38 @@
help
This driver supports DEC DC2114x Fast ethernet chips.
+config TULIP_SUPPORT_NON_PCI
+ bool "No PCI controller"
+ depends on TULIP
+ default n
+ help
+ Say Y to this and you can run this driver on platforms that do not
+ have PCI controllers.
+
+config TULIP_IGNORE_TX_NO_CARRIER
+ bool "Ignore tx no carrier error"
+ depends on TULIP
+ default n
+ help
+ Some IP cores of dc2114x or its variants do not comply so well with
+ the behaviors described by the official document. A packet could be
+ sent successfully but reported with No Carrier error. Latest drivers
+ of this IP core do not detect this error anymore. Say Y to this could
+ disable handling of this error.
+
+config TULIP_MULTIPLE_TX_DESC
+ bool "Use multiple tx descriptors"
+ depends on TULIP
+ default n
+ help
+ Some IP cores of dc2114x or its variants do not comply so well with
+ the behaviors described by the official document. Originally this
+ driver uses only one tx descriptor and organizes it as a ring buffer,
+ which would lead to a problem that one packet would be sent twice.
+ Say Y to this could prevent this bug if you are using IP cores with
+ this issue, by using multiple tx descriptors and organizing them as
+ a real well-defined ring buffer.
+
config XILINX_AXIEMAC
select PHYLIB
select MII
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index ce028f4..7c0665f 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
+#include <cpu_func.h>
#include <dm.h>
#include <malloc.h>
#include <net.h>
@@ -72,10 +73,20 @@
#define POLL_DEMAND 1
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+#define phys_to_bus(dev, a) virt_to_phys((volatile const void *)(a))
+#else
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
+#endif
+
+/* Number of TX descriptors */
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+#define NUM_TX_DESC 4
+#else
+#define NUM_TX_DESC 1
+#endif
#define NUM_RX_DESC PKTBUFSRX
-#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
@@ -89,9 +100,17 @@
u32 next;
};
+/* Assigned for network card's ring buffer:
+ * Some CPU might treat these memories as cached, and changes to these memories
+ * won't immediately be visible to each other. It is necessary to ensure that
+ * these memories between the CPU and the network card are marked as uncached.
+ */
+static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
+static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+
struct dc2114x_priv {
- struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
- struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+ struct de4x5_desc *rx_ring; /* Must be uncached to CPU */
+ struct de4x5_desc *tx_ring; /* Must be uncached to CPU */
int rx_new; /* RX descriptor ring pointer */
int tx_new; /* TX descriptor ring pointer */
char rx_ring_size;
@@ -271,7 +290,12 @@
static void send_setup_frame(struct dc2114x_priv *priv)
{
- char setup_frame[SETUP_FRAME_LEN];
+ /* We are writing setup frame and these changes should be visible to the
+ * network card immediately. So let's directly read/write through the
+ * uncached window.
+ */
+ char __setup_frame[SETUP_FRAME_LEN] __aligned(32);
+ char *setup_frame = (char *)map_physmem((phys_addr_t)virt_to_phys(__setup_frame), 0, MAP_NOCACHE);
char *pa = &setup_frame[0];
int i;
@@ -292,8 +316,13 @@
}
priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)&setup_frame[0]));
+ (phys_addr_t)&setup_frame[0]));
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+ priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_SET | SETUP_FRAME_LEN);
+ priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+#else
priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
+#endif
priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
@@ -307,7 +336,7 @@
}
if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
- printf("TX error status2 = 0x%08X\n",
+ debug("TX error status2 = 0x%08X\n",
le32_to_cpu(priv->tx_ring[priv->tx_new].status));
}
@@ -332,9 +361,17 @@
goto done;
}
+ /* Packet should be visible to the network card */
+ flush_dcache_range((phys_addr_t)packet, (phys_addr_t)(packet + RX_BUFF_SZ));
+
priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)packet));
+ (phys_addr_t)packet));
+#if CONFIG_IS_ENABLED(TULIP_MULTIPLE_TX_DESC)
+ priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_LS | TD_FS | length);
+ priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+#else
priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+#endif
priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
@@ -349,7 +386,9 @@
if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
priv->tx_ring[priv->tx_new].status = 0x0;
+#if !CONFIG_IS_ENABLED(TULIP_IGNORE_TX_NO_CARRIER)
goto done;
+#endif
}
status = length;
@@ -398,13 +437,22 @@
return -1;
}
- dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+ /* 2024-07:
+ * Remove the OMR_PM flag and choose 16 perfect filtering mode since in
+ * modern networks there're plenty of multicasts and set ORM_PM flag will
+ * increase the dc2114x's workload and ask the U-Boot to handle packets
+ * not related to itself. And most of the time, U-Boot does not need this
+ * feature.
+ *
+ * A better way: let user to decide whether to have this flag.
+ */
+ dc2114x_outl(priv, OMR_SDP | OMR_PS, DE4X5_OMR);
for (i = 0; i < NUM_RX_DESC; i++) {
priv->rx_ring[i].status = cpu_to_le32(R_OWN);
priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
- (u32)net_rx_packets[i]));
+ (phys_addr_t)net_rx_packets[i]));
priv->rx_ring[i].next = 0;
}
@@ -423,9 +471,9 @@
priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
/* Tell the adapter where the TX/RX rings are located. */
- dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
+ dc2114x_outl(priv, phys_to_bus(priv->devno, (phys_addr_t)priv->rx_ring),
DE4X5_RRBA);
- dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
+ dc2114x_outl(priv, phys_to_bus(priv->devno, (phys_addr_t)priv->tx_ring),
DE4X5_TRBA);
start_de4x5(priv);
@@ -461,21 +509,32 @@
}
}
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
static struct pci_device_id supported[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
{ PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
{ }
};
+#endif
static int dc2114x_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
+ int rval;
- memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+ if (!priv->enetaddr) {
+ rval = eth_env_get_enetaddr("ethaddr", priv->enetaddr);
+ if (!rval) {
+ printf("dc2114x: Err: please set a valid MAC address\n");
+ return -EINVAL;
+ }
+ }
+
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
/* Ensure we're not sleeping. */
dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
+#endif
return dc21x4x_init_common(priv);
}
@@ -485,8 +544,9 @@
struct dc2114x_priv *priv = dev_get_priv(dev);
dc21x4x_halt_common(priv);
-
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
+#endif
}
static int dc2114x_send(struct udevice *dev, void *packet, int length)
@@ -515,7 +575,8 @@
if (!ret)
return 0;
- *packetp = net_rx_packets[priv->rx_new];
+ invalidate_dcache_range((phys_addr_t)net_rx_packets[priv->rx_new], (phys_addr_t)(net_rx_packets[priv->rx_new] + RX_BUFF_SZ));
+ *packetp = (uchar *)net_rx_packets[priv->rx_new];
return ret - 4;
}
@@ -543,7 +604,7 @@
static int dc2114x_bind(struct udevice *dev)
{
- static int card_number;
+ static int card_number = 0;
char name[16];
sprintf(name, "dc2114x#%u", card_number++);
@@ -555,6 +616,8 @@
{
struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
+
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
u16 command, status;
u32 iobase;
@@ -562,9 +625,6 @@
iobase &= ~0xf;
debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
-
- priv->devno = dev;
- priv->enetaddr = plat->enetaddr;
priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
@@ -576,10 +636,29 @@
}
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
+#endif
+
+ priv->devno = dev;
+ priv->enetaddr = plat->enetaddr;
+ priv->rx_ring = (struct de4x5_desc *)map_physmem((phys_addr_t)virt_to_phys(rx_ring), 0, MAP_NOCACHE);
+ priv->tx_ring = (struct de4x5_desc *)map_physmem((phys_addr_t)virt_to_phys(tx_ring), 0, MAP_NOCACHE);
return 0;
}
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+static int dc2114x_of_to_plat(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_plat(dev);
+ struct dc2114x_priv *priv = dev_get_priv(dev);
+
+ plat->iobase = (phys_addr_t)map_physmem((phys_addr_t)devfdt_get_addr(dev), 0, MAP_NOCACHE);
+ priv->iobase = (void *)plat->iobase;
+
+ return 0;
+}
+#endif
+
static const struct eth_ops dc2114x_ops = {
.start = dc2114x_start,
.send = dc2114x_send,
@@ -589,9 +668,23 @@
.read_rom_hwaddr = dc2114x_read_rom_hwaddr,
};
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+static const struct udevice_id dc2114x_eth_ids[] = {
+ { .compatible = "dec,dmfe" },
+ { .compatible = "tulip,dmfe" },
+ { .compatible = "dec,dc2114x" },
+ { .compatible = "tulip,dc2114x" },
+ { }
+};
+#endif
+
U_BOOT_DRIVER(eth_dc2114x) = {
.name = "eth_dc2114x",
.id = UCLASS_ETH,
+#if CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
+ .of_match = dc2114x_eth_ids,
+ .of_to_plat = dc2114x_of_to_plat,
+#endif
.bind = dc2114x_bind,
.probe = dc2114x_probe,
.ops = &dc2114x_ops,
@@ -599,4 +692,6 @@
.plat_auto = sizeof(struct eth_pdata),
};
+#if !CONFIG_IS_ENABLED(TULIP_SUPPORT_NON_PCI)
U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
+#endif
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 3415c41..2279481 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -47,10 +47,6 @@
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#ifdef CONFIG_ARCH_IMX8M
-#include <asm/arch/clock.h>
-#include <asm/mach-imx/sys_proto.h>
-#endif
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/printk.h>
@@ -712,6 +708,9 @@
*/
setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+ if (eqos->config->ops->eqos_fix_soc_reset)
+ eqos->config->ops->eqos_fix_soc_reset(dev);
+
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce57e22..123f98d 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -248,6 +248,7 @@
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
int (*eqos_get_enetaddr)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ void (*eqos_fix_soc_reset)(struct udevice *dev);
};
struct eqos_priv {
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 6424328..af42f74 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -216,6 +216,27 @@
return 0;
}
+static void eqos_fix_soc_reset_imx(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ if (IS_ENABLED(CONFIG_IMX93)) {
+ /*
+ * Workaround for ERR051683 in i.MX93
+ * The i.MX93 requires speed configuration bits to be set to
+ * complete the reset procedure in RMII mode.
+ * See b536f32b5b03 ("net: stmmac: dwmac-imx: use platform
+ * specific reset for imx93 SoCs") in linux
+ */
+ if (eqos->config->interface(dev) == PHY_INTERFACE_MODE_RMII) {
+ udelay(200);
+ setbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_PS |
+ EQOS_MAC_CONFIGURATION_FES);
+ }
+ }
+}
+
static struct eqos_ops eqos_imx_ops = {
.eqos_inval_desc = eqos_inval_desc_generic,
.eqos_flush_desc = eqos_flush_desc_generic,
@@ -232,6 +253,7 @@
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
.eqos_get_enetaddr = eqos_get_enetaddr_imx,
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
+ .eqos_fix_soc_reset = eqos_fix_soc_reset_imx,
};
struct eqos_config __maybe_unused eqos_imx_config = {
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index d18a8d5..f64dbb7 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -678,7 +678,7 @@
status = le16_to_cpu(desc->status);
if (!(status & RFD_STATUS_C))
- return 0;
+ return -EAGAIN;
/* Valid frame status. */
if (status & RFD_STATUS_OK) {
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index 43baa69..7ebbe19 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -11,7 +11,12 @@
#include <eth_phy.h>
#include <linux/delay.h>
#include <miiphy.h>
-#include <i2c.h>
+#if CONFIG_IS_ENABLED(DM_I2C)
+# include <i2c.h>
+#endif
+#if CONFIG_IS_ENABLED(DM_SPI)
+# include <spi.h>
+#endif
#include <net/dsa.h>
#include <asm-generic/gpio.h>
@@ -71,15 +76,157 @@
#define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
+/* SPI specific define (opcodes) */
+#define KSZ_SPI_OP_RD 3
+#define KSZ_SPI_OP_WR 2
+
+#define KSZ9477_SPI_ADDR_SHIFT 24
+#define KSZ9477_SPI_ADDR_ALIGN 3
+#define KSZ9477_SPI_TURNAROUND_SHIFT 5
+
+/**
+ * struct ksz_phy_ops - low-level KSZ bus operations
+ */
+struct ksz_phy_ops {
+ /* read() - Read bytes from the device
+ *
+ * @udev: bus device
+ * @reg: register offset
+ * @val: data read
+ * @len: Number of bytes to read
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*read)(struct udevice *udev, u32 reg, u8 *val, int len);
+
+ /* write() - Write bytes to the device
+ *
+ * @udev: bus device
+ * @reg: register offset
+ * @val: data to write
+ * @len: Number of bytes to write
+ *
+ * @return: 0 on success, negative on failure
+ */
+ int (*write)(struct udevice *udev, u32 reg, u8 *val, int len);
+};
+
struct ksz_dsa_priv {
struct udevice *dev;
+ struct ksz_phy_ops *phy_ops;
u32 features; /* chip specific features */
};
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+static inline int ksz_i2c_read(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return dm_i2c_read(dev, reg, val, len);
+}
+
+static inline int ksz_i2c_write(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return dm_i2c_write(dev, reg, val, len);
+}
+
+static struct ksz_phy_ops phy_i2c_ops = {
+ .read = ksz_i2c_read,
+ .write = ksz_i2c_write,
+};
+#endif
+
+#if CONFIG_IS_ENABLED(DM_SPI)
+/**
+ * ksz_spi_xfer() - only used for 8/16/32 bits bus access
+ *
+ * @dev: The SPI slave device which will be sending/receiving the data.
+ * @reg: register address.
+ * @out: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * @in: Pointer to a string of bits that will be filled in.
+ * @len: number of bytes to read.
+ *
+ * Return: 0 on success, not 0 on failure
+ */
+static int ksz_spi_xfer(struct udevice *dev, u32 reg, const u8 *out,
+ u8 *in, u16 len)
+{
+ int ret;
+ u32 addr = 0;
+ u8 opcode;
+
+ if (in && out) {
+ printf("%s: can't do full duplex\n", __func__);
+ return -EINVAL;
+ }
+
+ if (len > 4 || len == 0) {
+ printf("%s: only 8/16/32 bits bus access supported\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret < 0) {
+ printf("%s: could not claim bus\n", __func__);
+ return ret;
+ }
+
+ opcode = (in ? KSZ_SPI_OP_RD : KSZ_SPI_OP_WR);
+
+ /* The actual device address space is 16 bits (A15 - A0),
+ * so the values of address bits A23 - A16 in the SPI
+ * command/address phase are “don't care”.
+ */
+ addr |= opcode << (KSZ9477_SPI_ADDR_SHIFT + KSZ9477_SPI_TURNAROUND_SHIFT);
+ addr |= reg << KSZ9477_SPI_TURNAROUND_SHIFT;
+
+ addr = __swab32(addr);
+
+ ret = dm_spi_xfer(dev, 32, &addr, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ printf("%s ERROR: dm_spi_xfer addr (%u)\n", __func__, ret);
+ goto release_bus;
+ }
+
+ ret = dm_spi_xfer(dev, len * 8, out, in, SPI_XFER_END);
+ if (ret) {
+ printf("%s ERROR: dm_spi_xfer data (%u)\n", __func__, ret);
+ goto release_bus;
+ }
+
+release_bus:
+ /* If an error occurred, release the chip by deasserting the CS */
+ if (ret < 0)
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
+}
+
+static inline int ksz_spi_read(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return ksz_spi_xfer(dev, reg, NULL, val, len);
+}
+
+static inline int ksz_spi_write(struct udevice *dev, u32 reg, u8 *val, int len)
+{
+ return ksz_spi_xfer(dev, reg, val, NULL, len);
+}
+
+static struct ksz_phy_ops phy_spi_ops = {
+ .read = ksz_spi_read,
+ .write = ksz_spi_write,
+};
+#endif
static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
{
- int ret = dm_i2c_read(dev, reg, val, 1);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
+ int ret = phy_ops->read(dev, reg, val, 1);
dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val);
@@ -93,8 +240,11 @@
static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, &val, 1);
+ return phy_ops->write(dev, reg, &val, 1);
}
static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val)
@@ -104,13 +254,15 @@
static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[2];
buf[1] = val & 0xff;
buf[0] = val >> 8;
dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, buf, 2);
+ return phy_ops->write(dev, reg, buf, 2);
}
static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val)
@@ -120,10 +272,12 @@
static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[2];
int ret;
- ret = dm_i2c_read(dev, reg, buf, 2);
+ ret = phy_ops->read(dev, reg, buf, 2);
*val = (buf[0] << 8) | buf[1];
dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val);
@@ -137,7 +291,10 @@
static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val)
{
- return dm_i2c_read(dev, reg, (u8 *)val, 4);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
+
+ return phy_ops->read(dev, reg, (u8 *)val, 4);
}
static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val)
@@ -147,6 +304,8 @@
static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val)
{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct ksz_phy_ops *phy_ops = priv->phy_ops;
u8 buf[4];
buf[3] = val & 0xff;
@@ -155,7 +314,7 @@
buf[0] = (val >> 8) & 0xff;
dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
- return dm_i2c_write(dev, reg, buf, 4);
+ return phy_ops->write(dev, reg, buf, 4);
}
static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val)
@@ -276,7 +435,7 @@
struct ksz_mdio_priv *priv = dev_get_priv(dev);
dev_dbg(dev, "%s\n", __func__);
- priv->ksz = dev_get_parent_priv(dev->parent);
+ priv->ksz = dev_get_priv(dev->parent);
return 0;
}
@@ -355,12 +514,12 @@
phy_interface_t interface)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
u8 data8;
dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
(port == pdata->cpu_port) ? "cpu" : "");
- struct ksz_dsa_priv *priv = dev_get_priv(dev);
if (port != pdata->cpu_port) {
if (priv->features & NEW_XMII)
/* phy port: config errata and leds */
@@ -503,25 +662,61 @@
return 0;
}
-/*
- * I2C driver
- */
-static int ksz_i2c_probe(struct udevice *dev)
+static void ksz_ops_register(struct udevice *dev, struct ksz_phy_ops *ops)
+{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+
+ priv->phy_ops = ops;
+}
+
+static bool dsa_ksz_check_ops(struct ksz_phy_ops *phy_ops)
+{
+ if (!phy_ops || !phy_ops->read || !phy_ops->write)
+ return false;
+
+ return true;
+}
+
+static int ksz_probe(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ enum uclass_id parent_id = UCLASS_INVALID;
int i, ret;
u8 data8;
u32 id;
- dev_set_parent_priv(dev, priv);
+ parent_id = device_get_uclass_id(dev_get_parent(dev));
+ switch (parent_id) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ case UCLASS_I2C: {
+ ksz_ops_register(dev, &phy_i2c_ops);
- ret = i2c_set_chip_offset_len(dev, 2);
- if (ret) {
- printf("i2c_set_chip_offset_len failed: %d\n", ret);
- return ret;
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret) {
+ printf("i2c_set_chip_offset_len failed: %d\n", ret);
+ return ret;
+ }
+ break;
+ }
+#endif
+#if CONFIG_IS_ENABLED(DM_SPI)
+ case UCLASS_SPI: {
+ ksz_ops_register(dev, &phy_spi_ops);
+ break;
+ }
+#endif
+ default:
+ dev_err(dev, "invalid parent bus (%s)\n",
+ uclass_get_name(parent_id));
+ return -EINVAL;
}
+ if (!dsa_ksz_check_ops(priv->phy_ops)) {
+ printf("Driver bug. No bus ops defined\n");
+ return -EINVAL;
+ }
+
/* default config */
priv->dev = dev;
@@ -543,6 +738,9 @@
case 0x00956700:
puts("KSZ9567R: ");
break;
+ case 0x00989600:
+ puts("KSZ9896C: ");
+ break;
case 0x00989700:
puts("KSZ9897S: ");
break;
@@ -573,19 +771,20 @@
return 0;
};
-static const struct udevice_id ksz_i2c_ids[] = {
+static const struct udevice_id ksz_ids[] = {
{ .compatible = "microchip,ksz9897" },
{ .compatible = "microchip,ksz9477" },
{ .compatible = "microchip,ksz9567" },
{ .compatible = "microchip,ksz9893" },
+ { .compatible = "microchip,ksz9896" },
{ }
};
U_BOOT_DRIVER(ksz) = {
.name = "ksz-switch",
.id = UCLASS_DSA,
- .of_match = ksz_i2c_ids,
- .probe = ksz_i2c_probe,
+ .of_match = ksz_ids,
+ .probe = ksz_probe,
.ops = &ksz_dsa_ops,
.priv_auto = sizeof(struct ksz_dsa_priv),
};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index a9efc50..13e7381 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -11,7 +11,7 @@
menuconfig PHYLIB
bool "Ethernet PHY (physical media interface) support"
- depends on NET
+ depends on NET || NET_LWIP
help
Enable Ethernet PHY (physical media interface) support.
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index a96430c..4d67203 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -12,6 +12,7 @@
#define PHY_ID_YT8511 0x0000010a
#define PHY_ID_YT8531 0x4f51e91b
+#define PHY_ID_YT8821 0x4f51ea19
#define PHY_ID_MASK GENMASK(31, 0)
/* Extended Register's Address Offset Register */
@@ -102,8 +103,12 @@
#define YTPHY_SPECIFIC_STATUS_REG 0x11
#define YTPHY_DUPLEX_MASK BIT(13)
#define YTPHY_DUPLEX_SHIFT 13
-#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14)
-#define YTPHY_SPEED_MODE_SHIFT 14
+#define YTPHY_SPEED_MASK ((0x3 << 14) | BIT(9))
+#define YTPHY_SPEED_10M ((0x0 << 14))
+#define YTPHY_SPEED_100M ((0x1 << 14))
+#define YTPHY_SPEED_1000M ((0x2 << 14))
+#define YTPHY_SPEED_10G ((0x3 << 14))
+#define YTPHY_SPEED_2500M ((0x0 << 14) | BIT(9))
#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27
#define YT8531_ESC1R_SLEEP_SW BIT(15)
@@ -131,6 +136,91 @@
#define TX_CLK_100_INVERTED BIT(4)
#define TX_CLK_1000_INVERTED BIT(5)
+#define YT8821_SDS_EXT_CSR_CTRL_REG 0x23
+#define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15)
+#define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8)
+
+#define YT8821_UTP_EXT_PI_CTRL_REG 0x56
+#define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5)
+#define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4)
+#define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3)
+#define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2)
+#define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1)
+#define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0)
+
+#define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97
+#define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8)
+
+#define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336
+#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8)
+
+#define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340
+#define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E
+#define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15)
+#define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7)
+#define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A
+#define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0)
+
+#define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372
+#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8)
+#define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374
+#define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8)
+#define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_PLL_CTRL_REG 0x450
+#define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0)
+
+#define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466
+#define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467
+#define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468
+#define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469
+#define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8)
+#define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0)
+
+#define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3
+#define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12)
+#define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8)
+
+#define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5
+#define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12)
+#define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8)
+
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4)
+#define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0)
+
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4)
+#define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0)
+
+#define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660
+#define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3)
+
+#define YT8821_CHIP_MODE_FORCE_BX2500 1
+
+/* chip config register */
+#define YTPHY_CCR_MODE_SEL_MASK GENMASK(2, 0)
+
+#define YTPHY_REG_SPACE_SELECT_REG 0xA000
+#define YTPHY_RSSR_SPACE_MASK BIT(1)
+#define YTPHY_RSSR_FIBER_SPACE (0x1 << 1)
+#define YTPHY_RSSR_UTP_SPACE (0x0 << 1)
+
struct ytphy_plat_priv {
u32 rx_delay_ps;
u32 tx_delay_ps;
@@ -295,15 +385,15 @@
if (val < 0)
return val;
- speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
+ speed_mode = (val & YTPHY_SPEED_MASK);
switch (speed_mode) {
- case 2:
+ case YTPHY_SPEED_1000M:
speed = SPEED_1000;
break;
- case 1:
+ case YTPHY_SPEED_100M:
speed = SPEED_100;
break;
- default:
+ case YTPHY_SPEED_10M:
speed = SPEED_10;
break;
}
@@ -632,6 +722,398 @@
return 0;
}
+static int ytphy_save_page(struct phy_device *phydev)
+{
+ int old_page;
+
+ old_page = ytphy_read_ext(phydev, YTPHY_REG_SPACE_SELECT_REG);
+ if (old_page < 0)
+ return old_page;
+
+ if ((old_page & YTPHY_RSSR_SPACE_MASK) == YTPHY_RSSR_FIBER_SPACE)
+ return YTPHY_RSSR_FIBER_SPACE;
+
+ return YTPHY_RSSR_UTP_SPACE;
+};
+
+static int ytphy_restore_page(struct phy_device *phydev, int page,
+ int ret)
+{
+ int mask = YTPHY_RSSR_SPACE_MASK;
+ int set;
+ int r;
+
+ if ((page & YTPHY_RSSR_SPACE_MASK) == YTPHY_RSSR_FIBER_SPACE)
+ set = YTPHY_RSSR_FIBER_SPACE;
+ else
+ set = YTPHY_RSSR_UTP_SPACE;
+
+ r = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG, mask,
+ set);
+ if (ret >= 0 && r < 0)
+ ret = r;
+
+ return ret;
+};
+
+static int ytphy_write_ext(struct phy_device *phydev, u16 regnum,
+ u16 val)
+{
+ int ret;
+
+ ret = phy_write(phydev, MDIO_DEVAD_NONE,
+ YTPHY_PAGE_SELECT, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, val);
+}
+
+static int yt8821_probe(struct phy_device *phydev)
+{
+ phydev->advertising = PHY_GBIT_FEATURES |
+ SUPPORTED_2500baseX_Full |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause;
+ phydev->supported = phydev->advertising;
+
+ return 0;
+}
+
+static int yt8821_serdes_init(struct phy_device *phydev)
+{
+ int old_page;
+ u16 mask;
+ u16 set;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_FIBER_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = phy_modify(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+ BMCR_ANENABLE, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN |
+ YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN;
+ set = YT8821_SDS_EXT_CSR_VCO_LDO_EN;
+ ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask,
+ set);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_utp_init(struct phy_device *phydev)
+{
+ int old_page;
+ u16 mask;
+ u16 save;
+ u16 set;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
+ YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 |
+ YT8821_UTP_EXT_RPDN_IPR_SHT_2500;
+ set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 |
+ YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500;
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER |
+ YT8821_UTP_EXT_VGA_LPF1_CAP_2500;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER |
+ YT8821_UTP_EXT_VGA_LPF2_CAP_2500;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 |
+ YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) |
+ FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_IPR_LNG_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000;
+ set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_TH_20DB_2500;
+ set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE |
+ YT8821_UTP_EXT_MU_COARSE_FR_F_FBE;
+ set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) |
+ FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE |
+ YT8821_UTP_EXT_MU_FINE_FR_F_FBE;
+ set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) |
+ FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */
+ ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG);
+ if (ret < 0)
+ goto err_restore_page;
+
+ save = ret;
+
+ mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE |
+ YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE;
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG,
+ mask, 0);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */
+ ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE;
+ set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_NFR_TX_ABILITY;
+ set = YT8821_UTP_EXT_NFR_TX_ABILITY;
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_PLL_SPARE_CFG;
+ set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9);
+ ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG |
+ YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG |
+ YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG |
+ YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG,
+ mask, set);
+ if (ret < 0)
+ goto err_restore_page;
+
+ mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG |
+ YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG;
+ set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) |
+ FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64);
+ ret = ytphy_modify_ext(phydev,
+ YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG,
+ mask, set);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_auto_sleep_config(struct phy_device *phydev,
+ bool enable)
+{
+ int old_page;
+ int ret;
+
+ old_page = ytphy_save_page(phydev);
+ if (old_page < 0)
+ return old_page;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = ytphy_modify_ext(phydev,
+ YT8531_EXTREG_SLEEP_CONTROL1_REG,
+ YT8531_ESC1R_SLEEP_SW,
+ enable ? 1 : 0);
+
+err_restore_page:
+ return ytphy_restore_page(phydev, old_page, ret);
+}
+
+static int yt8821_soft_reset(struct phy_device *phydev)
+{
+ return ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
+ YT8531_CCR_SW_RST, 0);
+}
+
+static int yt8821_config(struct phy_device *phydev)
+{
+ u8 mode = YT8821_CHIP_MODE_FORCE_BX2500;
+ int ret;
+ u16 set;
+
+ set = FIELD_PREP(YTPHY_CCR_MODE_SEL_MASK, mode);
+ ret = ytphy_modify_ext(phydev,
+ YT8531_CHIP_CONFIG_REG,
+ YTPHY_CCR_MODE_SEL_MASK,
+ set);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_serdes_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_utp_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8821_auto_sleep_config(phydev, false);
+ if (ret < 0)
+ return ret;
+
+ return yt8821_soft_reset(phydev);
+}
+
+static void yt8821_parse_status(struct phy_device *phydev, int val)
+{
+ int speed_mode;
+ int speed;
+
+ speed_mode = val & YTPHY_SPEED_MASK;
+ switch (speed_mode) {
+ case YTPHY_SPEED_2500M:
+ speed = SPEED_2500;
+ break;
+ case YTPHY_SPEED_1000M:
+ speed = SPEED_1000;
+ break;
+ case YTPHY_SPEED_100M:
+ speed = SPEED_100;
+ break;
+ case YTPHY_SPEED_10M:
+ speed = SPEED_10;
+ break;
+ }
+
+ phydev->speed = speed;
+ phydev->duplex = FIELD_GET(YTPHY_DUPLEX_MASK, val);
+}
+
+static int yt8821_startup(struct phy_device *phydev)
+{
+ u16 val;
+ int ret;
+
+ ret = ytphy_modify_ext(phydev, YTPHY_REG_SPACE_SELECT_REG,
+ YTPHY_RSSR_SPACE_MASK,
+ YTPHY_RSSR_UTP_SPACE);
+ if (ret)
+ return ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ ret = phy_read(phydev, MDIO_DEVAD_NONE,
+ YTPHY_SPECIFIC_STATUS_REG);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (phydev->link)
+ yt8821_parse_status(phydev, val);
+
+ return 0;
+}
+
U_BOOT_PHY_DRIVER(motorcomm8511) = {
.name = "YT8511 Gigabit Ethernet",
.uid = PHY_ID_YT8511,
@@ -652,3 +1134,14 @@
.startup = &yt8531_startup,
.shutdown = &genphy_shutdown,
};
+
+U_BOOT_PHY_DRIVER(motorcomm8821) = {
+ .name = "YT8821 2.5G Ethernet",
+ .uid = PHY_ID_YT8821,
+ .mask = PHY_ID_MASK,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_AN),
+ .probe = &yt8821_probe,
+ .config = &yt8821_config,
+ .startup = &yt8821_startup,
+ .shutdown = &genphy_shutdown,
+};
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 2e0afad..5f4b1e2 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -433,7 +433,7 @@
int length = 0;
if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
- return 0;
+ return -EAGAIN;
priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
/* See below for the rest of the interrupt acknowledges. */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 22a56f4..876a5fa 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -137,6 +137,12 @@
bool "GT64120 PCI support"
depends on MIPS
+config PCIE_CDNS_TI
+ bool "TI K3 PCIe support"
+ help
+ Say Y here to enable support for the Cadence PCIe Controller
+ on TI's K3 SoCs.
+
config PCI_PHYTIUM
bool "Phytium PCIe support"
help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 5b2d296..bf361cd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_PCIE_APPLE) += pcie_apple.o
+obj-$(CONFIG_PCIE_CDNS_TI) += pcie_cdns_ti.o
obj-$(CONFIG_PCI_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
index f978c64..f089c48 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -12,6 +12,7 @@
* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
*/
+#include <asm/arch/acpi/bcm2711.h>
#include <errno.h>
#include <dm.h>
#include <dm/ofnode.h>
@@ -21,88 +22,6 @@
#include <linux/log2.h>
#include <linux/iopoll.h>
-/* Offset of the mandatory PCIe capability config registers */
-#define BRCM_PCIE_CAP_REGS 0x00ac
-
-/* The PCIe controller register offsets */
-#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
-#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
-#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
-
-#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
-#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
-
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
-
-#define PCIE_RC_DL_MDIO_ADDR 0x1100
-#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
-#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
-
-#define PCIE_MISC_MISC_CTRL 0x4008
-#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
-#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
-#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
-#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
-#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
-#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
-#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
-
-#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
-#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
-#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
-#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
-
-#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
-#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_PCIE_STATUS 0x4068
-#define STATUS_PCIE_PORT_MASK 0x80
-#define STATUS_PCIE_PORT_SHIFT 7
-#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
-#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
-#define STATUS_PCIE_PHYLINKUP_MASK 0x10
-#define STATUS_PCIE_PHYLINKUP_SHIFT 4
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
-#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
-#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
-#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
-#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
-#define PCIE_MEM_WIN0_BASE_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
-#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
-#define PCIE_MEM_WIN0_LIMIT_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
-
-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
-#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
-
-#define PCIE_MSI_INTR2_CLR 0x4508
-#define PCIE_MSI_INTR2_MASK_SET 0x4510
-
-#define PCIE_EXT_CFG_DATA 0x8000
-
-#define PCIE_EXT_CFG_INDEX 0x9000
-
-#define PCIE_RGR1_SW_INIT_1 0x9210
-#define RGR1_SW_INIT_1_PERST_MASK 0x1
-#define RGR1_SW_INIT_1_INIT_MASK 0x2
-
/* PCIe parameters */
#define BRCM_NUM_PCIE_OUT_WINS 4
@@ -447,7 +366,7 @@
* This will need to be changed when support for other SoCs is added.
*/
setbits_le32(base + PCIE_RGR1_SW_INIT_1,
- RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
+ PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK);
/*
* The delay is a safety precaution to preclude the reset signal
* from looking like a glitch.
@@ -455,7 +374,7 @@
udelay(100);
/* Take the bridge out of reset */
- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
+ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
@@ -508,7 +427,7 @@
/* Unassert the fundamental reset */
clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
- RGR1_SW_INIT_1_PERST_MASK);
+ PCIE_RGR1_SW_INIT_1_PERST_MASK);
/*
* Wait for 100ms after PERST# deassertion; see PCIe CEM specification
@@ -552,7 +471,7 @@
* a PCIe-PCIe bridge (the default setting is to be EP mode).
*/
clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
- CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
+ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
if (pcie->ssc) {
ret = brcm_pcie_set_ssc(pcie->base);
@@ -570,8 +489,8 @@
nlw, ssc_good ? "(SSC)" : "(!SSC)");
/* PCIe->SCB endian mode for BAR */
- clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
- VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
+ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
+ PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
/*
@@ -584,7 +503,7 @@
* let's instead just unadvertise ASPM support.
*/
clrbits_le32(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY,
- PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ LINK_CAPABILITY_ASPM_SUPPORT_MASK);
return 0;
}
@@ -595,14 +514,14 @@
void __iomem *base = pcie->base;
/* Assert fundamental reset */
- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK);
/* Turn off SerDes */
setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
/* Shutdown bridge */
- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);
return 0;
}
diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c
new file mode 100644
index 0000000..41469a1
--- /dev/null
+++ b/drivers/pci/pcie_cdns_ti.c
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com
+ *
+ * PCIe controller driver for TI's K3 SoCs with Cadence PCIe controller
+ *
+ * Ported from the Linux driver - drivers/pci/controller/cadence/pci-j721e.c
+ *
+ * Author: Siddharth Vadapalli <s-vadapalli@ti.com>
+ *
+ */
+
+#include <asm/gpio.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/log2.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define CDNS_PCIE_LM_BASE 0x00100000
+#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
+#define CDNS_PCIE_LTSSM_CTRL_CAP (CDNS_PCIE_LM_BASE + 0x0054)
+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
+
+#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
+#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
+#define CDNS_PCIE_LM_ID_VENDOR(vid) \
+ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
+#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
+#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
+#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
+ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
+
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
+ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
+
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
+ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
+
+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
+
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
+
+#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
+#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
+#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
+ (((aperture) - 2) << ((bar) * 8))
+
+#define CDNS_PCIE_RP_BASE 0x00200000
+#define CDNS_PCIE_RP_CAP_OFFSET 0xc0
+
+/*
+ * Address Translation Registers
+ */
+#define CDNS_PCIE_AT_BASE 0x00400000
+
+/* Region r Outbound AXI to PCIe Address Translation Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
+ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
+ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
+
+/* Region r Outbound AXI to PCIe Address Translation Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
+ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
+
+/* Region r Outbound PCIe Descriptor Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
+
+/* Bit 23 MUST be set in RC mode. */
+#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
+ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
+
+/* Region r Outbound PCIe Descriptor Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
+ (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
+ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
+
+/* Region r AXI Region Base Address Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
+
+/* Region r AXI Region Base Address Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
+ (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
+
+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
+ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
+ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
+
+/* AXI link down register */
+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
+
+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)
+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1
+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \
+ (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
+ CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
+
+#define CDNS_PCIE_RP_MAX_IB 0x3
+
+#define LINK_TRAINING_ENABLE BIT(0)
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_UDELAY_MAX 100000
+#define LINK_RETRAIN_MAX_RETRIES 1000
+
+#define PCIE_USER_CMD_STATUS_REG_OFFSET 0x4
+#define PCIE_USER_LINK_STATUS_REG_OFFSET 0x14
+#define PCIE_USER_LINK_STATUS_MASK GENMASK(1, 0)
+
+#define CDNS_TI_PCIE_MODE_RC BIT(7)
+#define PCIE_MODE_SEL_MASK BIT(7)
+#define PCIE_GEN_SEL_MASK GENMASK(1, 0)
+#define PCIE_LINK_WIDTH_MASK GENMASK(9, 8)
+
+enum cdns_ti_pcie_mode {
+ PCIE_MODE_RC,
+ PCIE_MODE_EP,
+};
+
+enum cdns_pcie_rp_bar {
+ RP_BAR_UNDEFINED = -1,
+ RP_BAR0,
+ RP_BAR1,
+ RP_NO_BAR
+};
+
+static u8 bar_aperture_mask[] = {
+ [RP_BAR0] = 0x1F,
+ [RP_BAR1] = 0xF,
+};
+
+enum link_status {
+ NO_RECEIVERS_DETECTED,
+ LINK_TRAINING_IN_PROGRESS,
+ LINK_UP_DL_IN_PROGRESS,
+ LINK_UP_DL_COMPLETED,
+};
+
+struct pcie_cdns_ti_data {
+ enum cdns_ti_pcie_mode mode;
+ unsigned int quirk_retrain_flag:1;
+ unsigned int quirk_detect_quiet_flag:1;
+ unsigned int max_lanes;
+};
+
+struct pcie_cdns_ti {
+ struct udevice *dev;
+ void __iomem *intd_cfg_base;
+ void __iomem *user_cfg_base;
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+ fdt_size_t cfg_size;
+ struct regmap *syscon_base;
+ struct pci_controller *host_bridge;
+ u32 device_id;
+ u32 max_link_speed;
+ u32 num_lanes;
+ u32 pcie_ctrl_offset;
+ u32 vendor_id;
+ u32 mode;
+ unsigned int quirk_retrain_flag:1;
+ unsigned int quirk_detect_quiet_flag:1;
+ bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
+
+ /* IO, MEM & PREFETCH PCI regions */
+ struct pci_region io;
+ struct pci_region mem;
+ struct pci_region prefetch;
+};
+
+/* Cadence PCIe Controller register access helpers */
+static inline void pcie_cdns_ti_writel(struct pcie_cdns_ti *pcie, u32 reg, u32 val)
+{
+ writel(val, pcie->reg_base + reg);
+}
+
+static inline u32 pcie_cdns_ti_readl(struct pcie_cdns_ti *pcie, u32 reg)
+{
+ return readl(pcie->reg_base + reg);
+}
+
+/* Root Port register access helpers */
+static inline void pcie_cdns_ti_rp_writeb(struct pcie_cdns_ti *pcie,
+ u32 reg, u8 val)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ writeb(val, addr);
+}
+
+static inline void pcie_cdns_ti_rp_writew(struct pcie_cdns_ti *pcie,
+ u32 reg, u16 val)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ writew(val, addr);
+}
+
+static inline u16 pcie_cdns_ti_rp_readw(struct pcie_cdns_ti *pcie, u32 reg)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ return readw(addr);
+}
+
+/* User register access helpers */
+static inline u32 pcie_cdns_ti_user_readl(struct pcie_cdns_ti *pcie, u32 offset)
+{
+ return readl(pcie->user_cfg_base + offset);
+}
+
+static inline void pcie_cdns_ti_user_writel(struct pcie_cdns_ti *pcie, u32 offset,
+ u32 val)
+{
+ writel(val, pcie->user_cfg_base + offset);
+}
+
+void __iomem *pcie_cdns_ti_map_bus(struct pcie_cdns_ti *pcie, pci_dev_t bdf,
+ uint offset)
+{
+ int busnr, devnr, funcnr, devfn;
+ u32 addr0, desc0;
+
+ busnr = PCI_BUS(bdf);
+ devnr = PCI_DEV(bdf);
+ funcnr = PCI_FUNC(bdf);
+ devfn = (devnr << 3) | funcnr;
+
+ if (busnr == 0) {
+ if (devfn)
+ return NULL;
+ return pcie->reg_base + (offset & 0xfff);
+ }
+
+ if (!(pcie_cdns_ti_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
+ return NULL;
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
+
+ addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
+ CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
+ CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busnr);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
+
+ desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+ CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+
+ if (busnr == 1)
+ desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
+ else
+ desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
+
+ return pcie->cfg_base + (offset & 0xfff);
+}
+
+static int pcie_cdns_ti_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_cdns_ti *pcie = dev_get_priv(bus);
+ void __iomem *addr;
+ ulong value;
+
+ addr = pcie_cdns_ti_map_bus(pcie, bdf, offset & ~0x3);
+ if (!addr) {
+ debug("%s: bdf out of range\n", __func__);
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ value = readl(addr);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+
+ return 0;
+}
+
+static int pcie_cdns_ti_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct pcie_cdns_ti *pcie = dev_get_priv(bus);
+ void __iomem *addr;
+ ulong prev;
+
+ addr = pcie_cdns_ti_map_bus(pcie, bdf, offset & ~0x3);
+ if (!addr) {
+ debug("%s: bdf out of range\n", __func__);
+ return 0;
+ }
+
+ prev = readl(addr);
+ value = pci_conv_size_to_32(prev, value, offset, size);
+ writel(value, addr);
+
+ return 0;
+}
+
+static int pcie_cdns_ti_ctrl_init(struct pcie_cdns_ti *pcie)
+{
+ struct regmap *syscon = pcie->syscon_base;
+ u32 val = 0;
+
+ if (pcie->mode == PCIE_MODE_RC)
+ val = CDNS_TI_PCIE_MODE_RC;
+
+ /* Set mode of operation */
+ regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_MODE_SEL_MASK,
+ val);
+
+ /* Set link speed */
+ regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_GEN_SEL_MASK,
+ pcie->max_link_speed - 1);
+
+ /* Set link width */
+ regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_LINK_WIDTH_MASK,
+ (pcie->num_lanes - 1) << 8);
+ return 0;
+}
+
+static void pcie_cdns_ti_detect_quiet_quirk(struct pcie_cdns_ti *pcie)
+{
+ u32 delay = 0x3;
+ u32 ltssm_ctrl_cap;
+
+ ltssm_ctrl_cap = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LTSSM_CTRL_CAP);
+ ltssm_ctrl_cap = ((ltssm_ctrl_cap &
+ ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) |
+ CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay));
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_LTSSM_CTRL_CAP, ltssm_ctrl_cap);
+ ltssm_ctrl_cap = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LTSSM_CTRL_CAP);
+}
+
+static void pcie_cdns_ti_start_user_link(struct pcie_cdns_ti *pcie)
+{
+ u32 reg;
+
+ reg = pcie_cdns_ti_user_readl(pcie, PCIE_USER_CMD_STATUS_REG_OFFSET);
+ reg |= LINK_TRAINING_ENABLE;
+ pcie_cdns_ti_user_writel(pcie, PCIE_USER_CMD_STATUS_REG_OFFSET, reg);
+}
+
+static bool pcie_cdns_ti_user_link_up(struct pcie_cdns_ti *pcie)
+{
+ u32 reg;
+
+ reg = pcie_cdns_ti_user_readl(pcie, PCIE_USER_LINK_STATUS_REG_OFFSET);
+ reg &= PCIE_USER_LINK_STATUS_MASK;
+ if (reg == LINK_UP_DL_COMPLETED)
+ return true;
+
+ return false;
+}
+
+static int pcie_cdns_ti_host_wait_for_link(struct pcie_cdns_ti *pcie)
+{
+ int retries;
+
+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ if (pcie_cdns_ti_user_link_up(pcie)) {
+ dev_info(pcie->dev, "link up\n");
+ return 0;
+ }
+ udelay(LINK_WAIT_UDELAY_MAX);
+ }
+
+ dev_err(pcie->dev, "failed to bring up link\n");
+ return -ETIMEDOUT;
+}
+
+static int pcie_cdns_ti_host_training_complete(struct pcie_cdns_ti *pcie)
+{
+ u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
+ int retries;
+ u16 lnk_stat;
+
+ /* Wait for link training to complete */
+ for (retries = 0; retries < LINK_RETRAIN_MAX_RETRIES; retries++) {
+ lnk_stat = pcie_cdns_ti_rp_readw(pcie, pcie_cap_off +
+ PCI_EXP_LNKSTA);
+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
+ break;
+ udelay(1000);
+ }
+
+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
+ return 0;
+
+ return -ETIMEDOUT;
+}
+
+static int pcie_cdns_ti_retrain_link(struct pcie_cdns_ti *pcie)
+{
+ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
+ u16 lnk_stat, lnk_ctl;
+ int ret = 0;
+
+ lnk_cap_sls = pcie_cdns_ti_readl(pcie, (CDNS_PCIE_RP_BASE +
+ pcie_cap_off +
+ PCI_EXP_LNKCAP));
+ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+ return ret;
+
+ lnk_stat = pcie_cdns_ti_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
+ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
+ lnk_ctl = pcie_cdns_ti_rp_readw(pcie,
+ pcie_cap_off + PCI_EXP_LNKCTL);
+ lnk_ctl |= PCI_EXP_LNKCTL_RL;
+ pcie_cdns_ti_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
+ lnk_ctl);
+
+ ret = pcie_cdns_ti_host_training_complete(pcie);
+ if (ret)
+ return ret;
+
+ ret = pcie_cdns_ti_host_wait_for_link(pcie);
+ }
+ return ret;
+}
+
+static int pcie_cdns_ti_start_host_link(struct pcie_cdns_ti *pcie)
+{
+ int ret;
+
+ ret = pcie_cdns_ti_host_wait_for_link(pcie);
+ if (!ret && pcie->quirk_retrain_flag)
+ ret = pcie_cdns_ti_retrain_link(pcie);
+
+ return ret;
+}
+
+static void pcie_cdns_ti_init_root_port(struct pcie_cdns_ti *pcie)
+{
+ u32 val, ctrl, id;
+
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
+ val = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
+ CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
+ CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
+ CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
+ CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
+ CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, val);
+
+ if (pcie->vendor_id != 0xffff) {
+ id = CDNS_PCIE_LM_ID_VENDOR(pcie->vendor_id) |
+ CDNS_PCIE_LM_ID_SUBSYS(pcie->vendor_id);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_ID, id);
+ }
+
+ if (pcie->device_id != 0xffff)
+ pcie_cdns_ti_rp_writew(pcie, PCI_DEVICE_ID, pcie->device_id);
+
+ pcie_cdns_ti_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
+ pcie_cdns_ti_rp_writeb(pcie, PCI_CLASS_PROG, 0);
+ pcie_cdns_ti_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
+}
+
+void pcie_cdns_ti_set_outbound_region(struct pcie_cdns_ti *pcie, u8 busnr,
+ u8 fn, u32 r, bool is_io, u64 cpu_addr,
+ u64 pci_addr, u32 size)
+{
+ u64 sz = 1ULL << fls64(size - 1);
+ int nbits = ilog2(sz);
+ u32 addr0, addr1, desc0, desc1;
+
+ if (nbits < 8)
+ nbits = 8;
+
+ addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
+ (lower_32_bits(pci_addr) & GENMASK(31, 8));
+ addr1 = upper_32_bits(pci_addr);
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
+
+ if (is_io)
+ desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
+ else
+ desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
+ desc1 = 0;
+
+ desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+ CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+ desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
+
+ addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
+ (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+ addr1 = upper_32_bits(cpu_addr);
+
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
+}
+
+static int pcie_cdns_ti_bar_ib_config(struct pcie_cdns_ti *pcie,
+ enum cdns_pcie_rp_bar bar,
+ u64 cpu_addr, u64 size,
+ unsigned long flags)
+{
+ u32 addr0, addr1, aperture, value;
+
+ if (!pcie->avail_ib_bar[bar])
+ return -EBUSY;
+
+ pcie->avail_ib_bar[bar] = false;
+
+ aperture = ilog2(size);
+ addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(aperture) |
+ (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+ addr1 = upper_32_bits(cpu_addr);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1);
+
+ if (bar == RP_NO_BAR)
+ return 0;
+
+ value = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LM_RC_BAR_CFG);
+ value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
+ LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
+ LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
+ LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
+ LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
+ if (size + cpu_addr >= SZ_4G) {
+ if (!(flags & IORESOURCE_PREFETCH))
+ value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
+ value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
+ } else {
+ if (!(flags & IORESOURCE_PREFETCH))
+ value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
+ value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
+ }
+
+ value |= LM_RC_BAR_CFG_APERTURE(bar, aperture);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
+
+ return 0;
+}
+
+static int pcie_cdns_ti_map_dma_ranges(struct pcie_cdns_ti *pcie)
+{
+ u32 no_bar_nbits = 32;
+ int ret;
+
+ /*
+ * Assume that DMA-Ranges have not been specified.
+ * TODO: Add support for "dma-ranges".
+ */
+ dev_read_u32(pcie->dev, "cdns,no-bar-match-nbits",
+ &no_bar_nbits);
+ ret = pcie_cdns_ti_bar_ib_config(pcie, RP_NO_BAR, 0x0,
+ (u64)1 << no_bar_nbits, 0);
+ if (ret)
+ dev_err(pcie->dev, "IB BAR: %d config failed\n",
+ RP_NO_BAR);
+ return ret;
+}
+
+static int pcie_cdns_ti_init_address_translation(struct pcie_cdns_ti *pcie)
+{
+ struct pci_controller *hb = pcie->host_bridge;
+ u32 addr0, addr1, desc1, region = 1;
+ u64 cpu_addr = (u64)pcie->cfg_base;
+ int i, busnr = 0;
+
+ /*
+ * Reserve region 0 for PCI configure space accesses:
+ * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
+ * cdns_pci_map_bus(), other region registers are set here once for all.
+ */
+ addr1 = 0; /* Should be programmed to zero. */
+ desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
+
+ addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
+ (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+ addr1 = upper_32_bits(cpu_addr);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
+ pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
+
+ for (i = 0; i < hb->region_count; i++) {
+ if (hb->regions[i].flags == PCI_REGION_IO) {
+ pcie->io.phys_start = hb->regions[i].phys_start; /* IO base */
+ pcie->io.bus_start = hb->regions[i].bus_start; /* IO_bus_addr */
+ pcie->io.size = hb->regions[i].size; /* IO size */
+
+ pcie_cdns_ti_set_outbound_region(pcie, busnr, 0, region,
+ true, pcie->io.phys_start,
+ pcie->io.bus_start,
+ pcie->io.size);
+ } else {
+ pcie->mem.phys_start = hb->regions[i].phys_start; /* MEM base */
+ pcie->mem.bus_start = hb->regions[i].bus_start; /* MEM_bus_addr */
+ pcie->mem.size = hb->regions[i].size; /* MEM size */
+
+ pcie_cdns_ti_set_outbound_region(pcie, busnr, 0, region,
+ false, pcie->mem.phys_start,
+ pcie->mem.bus_start,
+ pcie->mem.size);
+ }
+ region++;
+ }
+
+ return pcie_cdns_ti_map_dma_ranges(pcie);
+}
+
+static int pcie_cdns_ti_host_init(struct pcie_cdns_ti *pcie)
+{
+ pcie_cdns_ti_init_root_port(pcie);
+
+ return pcie_cdns_ti_init_address_translation(pcie);
+}
+
+static int pcie_cdns_ti_setup_host(struct pcie_cdns_ti *pcie)
+{
+ enum cdns_pcie_rp_bar bar;
+ int ret;
+
+ if (pcie->quirk_detect_quiet_flag)
+ pcie_cdns_ti_detect_quiet_quirk(pcie);
+
+ pcie_cdns_ti_start_user_link(pcie);
+
+ ret = pcie_cdns_ti_start_host_link(pcie);
+ if (ret)
+ return ret;
+
+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
+ pcie->avail_ib_bar[bar] = true;
+
+ ret = pcie_cdns_ti_host_init(pcie);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int pcie_cdns_ti_probe(struct udevice *dev)
+{
+ struct pcie_cdns_ti *pcie = dev_get_priv(dev);
+ struct udevice *pci_ctlr = pci_get_controller(dev);
+ struct pci_controller *host_bridge = dev_get_uclass_priv(pci_ctlr);
+ const struct pcie_cdns_ti_data *data;
+ struct power_domain pci_pwrdmn;
+ struct gpio_desc *gpiod;
+ struct phy serdes;
+ struct clk *clk;
+ int ret;
+
+ pcie->dev = dev;
+ pcie->host_bridge = host_bridge;
+
+ data = (struct pcie_cdns_ti_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ pcie->mode = data->mode;
+ pcie->quirk_retrain_flag = data->quirk_retrain_flag;
+ pcie->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
+
+ if (pcie->num_lanes > data->max_lanes) {
+ dev_warn(dev, "cannot support %d lanes, defaulting to %d\n",
+ pcie->num_lanes, data->max_lanes);
+ pcie->num_lanes = data->max_lanes;
+ }
+
+ ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "failed to get power domain\n");
+ return ret;
+ }
+
+ ret = power_domain_on(&pci_pwrdmn);
+ if (ret) {
+ dev_err(dev, "failed to power on\n");
+ return ret;
+ }
+
+ clk = devm_clk_get(dev, "fck");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(dev, "failed to get functional clock\n");
+ return ret;
+ }
+
+ ret = generic_phy_get_by_name(dev, "pcie-phy", &serdes);
+ if (ret) {
+ dev_err(dev, "unable to get serdes");
+ return ret;
+ }
+ generic_phy_reset(&serdes);
+ generic_phy_init(&serdes);
+ generic_phy_power_on(&serdes);
+
+ ret = pcie_cdns_ti_ctrl_init(pcie);
+ if (ret)
+ return ret;
+
+ gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT);
+ if (IS_ERR(gpiod)) {
+ ret = PTR_ERR(gpiod);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get reset GPIO\n");
+ return ret;
+ }
+
+ if (gpiod) {
+ ret = dm_gpio_set_value(gpiod, 0);
+ udelay(200);
+ ret = dm_gpio_set_value(gpiod, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = pcie_cdns_ti_setup_host(pcie);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int pcie_cdns_ti_of_to_plat(struct udevice *dev)
+{
+ struct pcie_cdns_ti *pcie = dev_get_priv(dev);
+ struct regmap *syscon;
+ u32 offset;
+ int ret;
+
+ pcie->intd_cfg_base = dev_remap_addr_name(dev, "intd_cfg");
+ if (!pcie->intd_cfg_base)
+ return -EINVAL;
+
+ pcie->user_cfg_base = dev_remap_addr_name(dev, "user_cfg");
+ if (!pcie->user_cfg_base)
+ return -EINVAL;
+
+ pcie->reg_base = dev_remap_addr_name(dev, "reg");
+ if (!pcie->reg_base)
+ return -EINVAL;
+
+ pcie->cfg_base = dev_remap_addr_name(dev, "cfg");
+ if (!pcie->cfg_base)
+ return -EINVAL;
+
+ pcie->vendor_id = 0xffff;
+ pcie->device_id = 0xffff;
+ dev_read_u32(dev, "vendor-id", &pcie->vendor_id);
+ dev_read_u32(dev, "device-id", &pcie->device_id);
+
+ ret = dev_read_u32(dev, "num-lanes", &pcie->num_lanes);
+ if (ret)
+ return ret;
+
+ ret = dev_read_u32(dev, "max-link-speed", &pcie->max_link_speed);
+ if (ret)
+ return ret;
+
+ syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-pcie-ctrl");
+ if (IS_ERR(syscon)) {
+ if (PTR_ERR(syscon) == -ENODEV)
+ return 0;
+ return PTR_ERR(syscon);
+ }
+
+ ret = dev_read_u32_index(dev, "ti,syscon-pcie-ctrl", 1, &offset);
+ if (ret)
+ return ret;
+
+ pcie->syscon_base = syscon;
+ pcie->pcie_ctrl_offset = offset;
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_cdns_ti_ops = {
+ .read_config = pcie_cdns_ti_read_config,
+ .write_config = pcie_cdns_ti_write_config,
+};
+
+static const struct pcie_cdns_ti_data j7200_pcie_rc_data = {
+ .mode = PCIE_MODE_RC,
+ .quirk_detect_quiet_flag = true,
+ .max_lanes = 2,
+};
+
+static const struct udevice_id pcie_cdns_ti_ids[] = {
+ {
+ .compatible = "ti,j7200-pcie-host",
+ .data = (ulong)&j7200_pcie_rc_data,
+ },
+ {},
+};
+
+U_BOOT_DRIVER(pcie_cdns_ti) = {
+ .name = "pcie_cdns_ti",
+ .id = UCLASS_PCI,
+ .of_match = pcie_cdns_ti_ids,
+ .ops = &pcie_cdns_ti_ops,
+ .of_to_plat = pcie_cdns_ti_of_to_plat,
+ .probe = pcie_cdns_ti_probe,
+ .priv_auto = sizeof(struct pcie_cdns_ti),
+};
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index 9e7c347..5ecd3f2 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -62,6 +62,7 @@
{ "SD2", 5, (1 << 1) },
{ "FWSPICS1", 3, (1 << 24) },
{ "SPI1CS1", 1, (1 << 15) },
+ { "SGPM", 2, (1 << 11) | (1 << 10) | (1 << 9) | (1 << 8) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
index bc12590..f4bec6f 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
@@ -454,6 +454,14 @@
{0x41c, BIT(31), 0},
};
+static struct aspeed_sig_desc sgpm1[] = {
+ {0x414, GENMASK(27, 24), 0},
+};
+
+static struct aspeed_sig_desc sgpm2[] = {
+ {0x6d0, GENMASK(7, 4), 0},
+};
+
static const struct aspeed_group_config ast2600_groups[] = {
{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
@@ -543,6 +551,8 @@
{ "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 },
{ "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 },
{ "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 },
+ { "SGPM1", ARRAY_SIZE(sgpm1), sgpm1 },
+ { "SGPM2", ARRAY_SIZE(sgpm2), sgpm2 },
};
static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
index ff466c4..b1960c5 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -22,7 +22,7 @@
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
struct imx_pinctrl_soc_info *info = priv->info;
- int node = dev_of_offset(config);
+ ofnode node = dev_ofnode(config);
const struct fdt_property *prop;
u32 *pin_data;
int npins, size, pin_size;
@@ -40,7 +40,7 @@
else
pin_size = FSL_PIN_SIZE;
- prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
+ prop = ofnode_get_property(node, "fsl,pins", &size);
if (!prop) {
dev_err(dev, "No fsl,pins property in node %s\n", config->name);
return -EINVAL;
@@ -56,8 +56,8 @@
if (!pin_data)
return -ENOMEM;
- if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
- pin_data, size >> 2)) {
+ if (ofnode_read_u32_array(node, "fsl,pins",
+ pin_data, size >> 2)) {
dev_err(dev, "Error reading pin data.\n");
devm_kfree(dev, pin_data);
return -EINVAL;
@@ -202,10 +202,11 @@
struct imx_pinctrl_soc_info *info)
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev), ret;
- struct fdtdec_phandle_args arg;
+ struct ofnode_phandle_args arg;
+ ofnode node = dev_ofnode(dev);
fdt_addr_t addr;
fdt_size_t size;
+ int ret;
if (!info) {
dev_err(dev, "wrong pinctrl info\n");
@@ -218,7 +219,7 @@
if (info->flags & IMX8_USE_SCU)
return 0;
- addr = devfdt_get_addr_size_index(dev, 0, &size);
+ addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -227,22 +228,20 @@
return -ENOMEM;
priv->info = info;
- info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
+ info->mux_mask = ofnode_read_u32(node, "fsl,mux_mask", 0);
/*
* Refer to linux documentation for details:
* Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
*/
- if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
- node, "fsl,input-sel",
+ if (ofnode_read_bool(node, "fsl,input-sel")) {
+ ret = ofnode_parse_phandle_with_args(node, "fsl,input-sel",
NULL, 0, 0, &arg);
if (ret) {
dev_err(dev, "iomuxc fsl,input-sel property not found\n");
return -EINVAL;
}
- addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
- &size);
+ addr = ofnode_get_addr_size(arg.node, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c
index 8b6870c..c22fbe6 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -456,25 +456,22 @@
static int imx8m_power_domain_bind(struct udevice *dev)
{
- int offset;
+ ofnode subnode;
const char *name;
int ret = 0;
- offset = dev_of_offset(dev);
- for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
- offset = fdt_next_subnode(gd->fdt_blob, offset)) {
+ ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
/* Bind the subnode to this driver */
- name = fdt_get_name(gd->fdt_blob, offset, NULL);
+ name = ofnode_get_name(subnode);
/* Descend into 'pgc' subnode */
if (!strstr(name, "power-domain")) {
- offset = fdt_first_subnode(gd->fdt_blob, offset);
- name = fdt_get_name(gd->fdt_blob, offset, NULL);
+ subnode = ofnode_first_subnode(subnode);
+ name = ofnode_get_name(subnode);
}
-
ret = device_bind_with_driver_data(dev, dev->driver, name,
dev->driver_data,
- offset_to_ofnode(offset),
+ subnode,
NULL);
if (ret == -ENODEV)
@@ -514,8 +511,7 @@
struct imx_pgc_domain_data *domain_data =
(struct imx_pgc_domain_data *)dev_get_driver_data(dev);
- pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "reg", -1);
+ pdata->resource_id = ofnode_read_u32_default(dev_ofnode(dev), "reg", -1);
pdata->domain = &domain_data->domains[pdata->resource_id];
pdata->regs = domain_data->pgc_regs;
pdata->base = dev_read_addr_ptr(dev->parent);
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 562c1a3..bbcbcee 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -394,6 +394,7 @@
config PMIC_TPS65941
bool "Enable driver for Texas Instruments TPS65941 PMIC"
+ depends on DM_PMIC
help
The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 51cacf3..bcdeda9 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -309,6 +309,7 @@
((unsigned long)pccb->pdata[5] << 16) |
((unsigned long)pccb->pdata[6] << 8) |
((unsigned long)pccb->pdata[7]);
+ *capacity += 1;
return 0;
}
@@ -332,6 +333,7 @@
((uint64_t)pccb->pdata[5] << 16) |
((uint64_t)pccb->pdata[6] << 8) |
((uint64_t)pccb->pdata[7]);
+ *capacity += 1;
*blksz = ((uint64_t)pccb->pdata[8] << 56) |
((uint64_t)pccb->pdata[9] << 48) |
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 9feaa1e..a08678d 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -18,6 +18,7 @@
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <dm/of_access.h>
+#include <linux/build_bug.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -328,11 +329,15 @@
static int _serial_tstc(struct udevice *dev)
{
struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
+ uint wr, avail;
- /* Read all available chars into the RX buffer */
- while (__serial_tstc(dev)) {
- upriv->buf[upriv->wr_ptr++] = __serial_getc(dev);
- upriv->wr_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+ BUILD_BUG_ON_NOT_POWER_OF_2(CONFIG_SERIAL_RX_BUFFER_SIZE);
+
+ /* Read all available chars into the RX buffer while there's room */
+ avail = CONFIG_SERIAL_RX_BUFFER_SIZE - (upriv->wr_ptr - upriv->rd_ptr);
+ while (avail-- && __serial_tstc(dev)) {
+ wr = upriv->wr_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE;
+ upriv->buf[wr] = __serial_getc(dev);
}
return upriv->rd_ptr != upriv->wr_ptr ? 1 : 0;
@@ -342,12 +347,13 @@
{
struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
char val;
+ uint rd;
if (upriv->rd_ptr == upriv->wr_ptr)
return __serial_getc(dev);
- val = upriv->buf[upriv->rd_ptr++];
- upriv->rd_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+ rd = upriv->rd_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE;
+ val = upriv->buf[rd];
return val;
}
@@ -582,11 +588,6 @@
sdev.getc = serial_stub_getc;
sdev.tstc = serial_stub_tstc;
-#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
- /* Allocate the RX buffer */
- upriv->buf = malloc(CONFIG_SERIAL_RX_BUFFER_SIZE);
-#endif
-
stdio_register_dev(&sdev, &upriv->sdev);
#endif
return 0;
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 80c3596..e6bf0c2 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -19,6 +19,7 @@
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
+#include <spl.h>
#include <dm/device_compat.h>
#include <dm/platform_data/serial_pl01x.h>
#include <linux/compiler.h>
@@ -272,6 +273,28 @@
return &pl01x_serial_drv;
}
#else
+
+static int pl01x_serial_getinfo(struct udevice *dev,
+ struct serial_device_info *info)
+{
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
+
+ /* save code size */
+ if (!not_xpl())
+ return -ENOSYS;
+
+ info->type = SERIAL_CHIP_PL01X;
+ info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
+ info->addr = plat->base;
+ info->size = 0x1000;
+ info->reg_width = 4;
+ info->reg_shift = 2;
+ info->reg_offset = 0;
+ info->clock = plat->clock;
+
+ return 0;
+}
+
int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
struct pl01x_serial_plat *plat = dev_get_plat(dev);
@@ -341,6 +364,7 @@
.pending = pl01x_serial_pending,
.getc = pl01x_serial_getc,
.setbrg = pl01x_serial_setbrg,
+ .getinfo = pl01x_serial_getinfo,
};
#if CONFIG_IS_ENABLED(OF_REAL)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fa817ec..fd5cb36 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -20,12 +20,6 @@
if SPI
-config SPI_ADVANCE
- bool "Enable the advance feature"
- help
- Enable the SPI advance feature support. By default this is disabled.
- If you intend to use the advance feature support you should enable.
-
config DM_SPI
bool "Enable Driver Model for SPI drivers"
depends on DM
@@ -615,6 +609,12 @@
This option is used to enable ZynqMP QSPI controller driver which
is used to communicate with qspi flash devices.
+config SPI_STACKED_PARALLEL
+ bool "Enable support for stacked or parallel memories"
+ help
+ Enable support for stacked/or parallel memories. This functionality
+ may appear on Xilinx hardware. By default this is disabled.
+
endif # if DM_SPI
config FSL_ESPI
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index f5b3fb5..4aad324 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -734,7 +734,7 @@
return 0;
}
-bool update_stripe(const struct spi_mem_op *op)
+static bool update_stripe(const struct spi_mem_op *op)
{
if (op->cmd.opcode == SPINOR_OP_BE_4K ||
op->cmd.opcode == SPINOR_OP_CHIP_ERASE ||
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 80c084f..dd16ab3 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -83,7 +83,7 @@
if (cpuid_eax(0) < 0x16)
return 0;
- return cpuid_eax(0x16);
+ return cpuid_eax(0x15);
}
/*
@@ -299,10 +299,19 @@
if (!pit_expect_msb(0xff-i, &delta, &d2))
break;
+ delta -= tsc;
+
+ /*
+ * Extrapolate the error and fail fast if the error will
+ * never be below 500 ppm.
+ */
+ if (i == 1 &&
+ d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
+ return 0;
+
/*
* Iterate until the error is less than 500 ppm
*/
- delta -= tsc;
if (d1+d2 >= delta >> 11)
continue;
@@ -403,6 +412,10 @@
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
+ /* deal with this being called before x86_cpu_init_f() */
+ if (!gd->arch.x86_vendor)
+ x86_get_identity_for_timer();
+
/**
* There is no obvious way to obtain this information from EFI
* boot services. This value was measured on a Framework Laptop
@@ -438,6 +451,7 @@
return;
done:
+ fast_calibrate = min(fast_calibrate, 4000UL);
if (!gd->arch.clock_rate)
gd->arch.clock_rate = fast_calibrate * 1000000;
}
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 311aaa7..960b6a9 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -85,6 +85,8 @@
source "drivers/usb/phy/Kconfig"
+source "drivers/usb/tcpm/Kconfig"
+
source "drivers/usb/ulpi/Kconfig"
if USB_HOST
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index ac7e469..a30c40e 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1637,6 +1637,14 @@
else
priv_ep->trb_burst_size = 16;
+ /*
+ * The Endpoint is configured to handle a maximum packet size of
+ * max_packet_size. Hence, set priv_ep->endpoint.maxpacket to
+ * max_packet_size. This is necessary to ensure that the TD_SIZE
+ * is calculated correctly in cdns3_ep_run_transfer().
+ */
+ priv_ep->endpoint.maxpacket = max_packet_size;
+
ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
!!priv_ep->dir);
if (ret) {
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7374ce9..b572ea3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -670,6 +670,7 @@
* @ep0_trb: dma address of ep0_trb
* @ep0_usb_req: dummy req used while handling STD USB requests
* @ep0_bounce_addr: dma address of ep0_bounce
+ * @setup_buf_addr: dma address of setup_buf
* @scratch_addr: dma address of scratchbuf
* @lock: for synchronizing
* @dev: pointer to our struct device
@@ -757,6 +758,7 @@
dma_addr_t ep0_trb_addr;
dma_addr_t ep0_bounce_addr;
dma_addr_t scratch_addr;
+ dma_addr_t setup_buf_addr;
struct dwc3_request ep0_usb_req;
/* device lock */
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 24f516a..531f0b5 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -380,7 +380,7 @@
dep = dwc->eps[0];
dwc->ep0_usb_req.dep = dep;
dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
- dwc->ep0_usb_req.request.buf = dwc->setup_buf;
+ dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr;
dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
@@ -662,7 +662,7 @@
dep = dwc->eps[0];
dwc->ep0_usb_req.dep = dep;
dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
- dwc->ep0_usb_req.request.buf = dwc->setup_buf;
+ dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr;
dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
@@ -742,6 +742,8 @@
if (!dwc->gadget_driver)
goto out;
+ dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl));
+
len = le16_to_cpu(ctrl->wLength);
if (!len) {
dwc->three_stage_setup = false;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index fe33e30..e5a3834 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2534,6 +2534,8 @@
while (left > 0) {
union dwc3_event event;
+ dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length);
+
event.raw = *(u32 *) (evt->buf + evt->lpos);
dwc3_process_event_entry(dwc, &event);
@@ -2653,8 +2655,8 @@
goto err1;
}
- dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
- DWC3_EP0_BOUNCE_SIZE);
+ dwc->setup_buf = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
+ (unsigned long *)&dwc->setup_buf_addr);
if (!dwc->setup_buf) {
ret = -ENOMEM;
goto err2;
@@ -2701,7 +2703,7 @@
dma_free_coherent(dwc->ep0_bounce);
err3:
- kfree(dwc->setup_buf);
+ dma_free_coherent(dwc->setup_buf);
err2:
dma_free_coherent(dwc->ep0_trb);
@@ -2723,7 +2725,7 @@
dma_free_coherent(dwc->ep0_bounce);
- kfree(dwc->setup_buf);
+ dma_free_coherent(dwc->setup_buf);
dma_free_coherent(dwc->ep0_trb);
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
index 04791d4..c1ab028 100644
--- a/drivers/usb/dwc3/io.h
+++ b/drivers/usb/dwc3/io.h
@@ -50,6 +50,17 @@
static inline void dwc3_flush_cache(uintptr_t addr, int length)
{
- flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+ uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1);
+ uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE);
+
+ flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr);
+}
+
+static inline void dwc3_invalidate_cache(uintptr_t addr, int length)
+{
+ uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1);
+ uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE);
+
+ invalidate_dcache_range((unsigned long)start_addr, (unsigned long)end_addr);
}
#endif /* __DRIVERS_USB_DWC3_IO_H */
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1694ad0..010084e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -233,7 +233,7 @@
config USB_ETHER
bool "USB Ethernet Gadget"
- depends on NET
+ depends on NET || NET_LWIP
default y if ARCH_SUNXI && USB_MUSB_GADGET
help
Creates an Ethernet network device through a USB peripheral
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6e10b62..bb5893d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -68,6 +68,14 @@
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_GENERIC
+ bool "Generic SoC USB 3.0 support"
+ depends on OF_CONTROL
+ default n
+ help
+ Choose this option to add support for USB 3.0 driver for SoCs
+ that do not need platform specific code, like on emulated targets.
+
config USB_XHCI_OCTEON
bool "Support for Marvell Octeon family on-chip xHCI USB controller"
depends on ARCH_OCTEON
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 792956e..301bb9f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -50,6 +50,7 @@
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
+obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
diff --git a/drivers/usb/host/xhci-generic.c b/drivers/usb/host/xhci-generic.c
new file mode 100644
index 0000000..355d488
--- /dev/null
+++ b/drivers/usb/host/xhci-generic.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 9elements GmbH
+ *
+ * GENERIC USB HOST xHCI Controller
+ */
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <usb/xhci.h>
+
+struct generic_xhci_plat {
+ fdt_addr_t hcd_base;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct generic_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_plat usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct generic_xhci_plat *plat = dev_get_plat(dev);
+ struct generic_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len;
+
+ ctx->hcd = (struct xhci_hccr *)phys_to_virt(plat->hcd_base);
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_of_to_plat(struct udevice *dev)
+{
+ struct generic_xhci_plat *plat = dev_get_plat(dev);
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ plat->hcd_base = dev_read_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ dev_dbg(dev, "Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+ { .compatible = "generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_generic",
+ .id = UCLASS_USB,
+ .of_match = xhci_usb_ids,
+ .of_to_plat = xhci_usb_of_to_plat,
+ .probe = xhci_usb_probe,
+ .remove = xhci_deregister,
+ .ops = &xhci_usb_ops,
+ .plat_auto = sizeof(struct generic_xhci_plat),
+ .priv_auto = sizeof(struct generic_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/usb/tcpm/Kconfig b/drivers/usb/tcpm/Kconfig
new file mode 100644
index 0000000..9be4b49
--- /dev/null
+++ b/drivers/usb/tcpm/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config TYPEC_TCPM
+ tristate "USB Type-C Port Controller Manager"
+ depends on DM
+ help
+ The Type-C Port Controller Manager provides a USB PD and USB Type-C
+ state machine for use with Type-C Port Controllers.
+
+config TYPEC_FUSB302
+ tristate "Fairchild FUSB302 Type-C chip driver"
+ depends on DM && DM_I2C && TYPEC_TCPM
+ help
+ The Fairchild FUSB302 Type-C chip driver that works with
+ Type-C Port Controller Manager to provide USB PD and USB
+ Type-C functionalities.
diff --git a/drivers/usb/tcpm/Makefile b/drivers/usb/tcpm/Makefile
new file mode 100644
index 0000000..668d331
--- /dev/null
+++ b/drivers/usb/tcpm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_TYPEC_TCPM) += tcpm.o tcpm-uclass.o
+obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o
diff --git a/drivers/usb/tcpm/fusb302.c b/drivers/usb/tcpm/fusb302.c
new file mode 100644
index 0000000..fe93ff3
--- /dev/null
+++ b/drivers/usb/tcpm/fusb302.c
@@ -0,0 +1,1323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016-2017 Google, Inc
+ *
+ * Fairchild FUSB302 Type-C Chip Driver
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <dm/device_compat.h>
+#include <usb/tcpm.h>
+#include "fusb302_reg.h"
+
+#define FUSB302_MAX_MSG_LEN 0x1F
+
+enum toggling_mode {
+ TOGGLING_MODE_OFF,
+ TOGGLING_MODE_DRP,
+ TOGGLING_MODE_SNK,
+ TOGGLING_MODE_SRC,
+};
+
+enum src_current_status {
+ SRC_CURRENT_DEFAULT,
+ SRC_CURRENT_MEDIUM,
+ SRC_CURRENT_HIGH,
+};
+
+static const u8 ra_mda_value[] = {
+ [SRC_CURRENT_DEFAULT] = 4, /* 210mV */
+ [SRC_CURRENT_MEDIUM] = 9, /* 420mV */
+ [SRC_CURRENT_HIGH] = 18, /* 798mV */
+};
+
+static const u8 rd_mda_value[] = {
+ [SRC_CURRENT_DEFAULT] = 38, /* 1638mV */
+ [SRC_CURRENT_MEDIUM] = 38, /* 1638mV */
+ [SRC_CURRENT_HIGH] = 61, /* 2604mV */
+};
+
+struct fusb302_chip {
+ enum toggling_mode toggling_mode;
+ enum src_current_status src_current_status;
+ bool intr_togdone;
+ bool intr_bc_lvl;
+ bool intr_comp_chng;
+
+ /* port status */
+ bool vconn_on;
+ bool vbus_present;
+ enum typec_cc_polarity cc_polarity;
+ enum typec_cc_status cc1;
+ enum typec_cc_status cc2;
+};
+
+static int fusb302_i2c_write(struct udevice *dev, u8 address, u8 data)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, address, &data, 1);
+ if (ret)
+ dev_err(dev, "cannot write 0x%02x to 0x%02x, ret=%d\n",
+ data, address, ret);
+
+ return ret;
+}
+
+static int fusb302_i2c_block_write(struct udevice *dev, u8 address,
+ u8 length, const u8 *data)
+{
+ int ret;
+
+ if (!length)
+ return 0;
+
+ ret = dm_i2c_write(dev, address, data, length);
+ if (ret)
+ dev_err(dev, "cannot block write 0x%02x, len=%d, ret=%d\n",
+ address, length, ret);
+
+ return ret;
+}
+
+static int fusb302_i2c_read(struct udevice *dev, u8 address, u8 *data)
+{
+ int ret, retries;
+
+ for (retries = 0; retries < 3; retries++) {
+ ret = dm_i2c_read(dev, address, data, 1);
+ if (ret == 0)
+ return ret;
+ dev_err(dev, "cannot read %02x, ret=%d\n", address, ret);
+ }
+
+ return ret;
+}
+
+static int fusb302_i2c_block_read(struct udevice *dev, u8 address,
+ u8 length, u8 *data)
+{
+ int ret;
+
+ if (!length)
+ return 0;
+
+ ret = dm_i2c_read(dev, address, data, length);
+ if (ret)
+ dev_err(dev, "cannot block read 0x%02x, len=%d, ret=%d\n",
+ address, length, ret);
+ return ret;
+}
+
+static int fusb302_i2c_mask_write(struct udevice *dev, u8 address,
+ u8 mask, u8 value)
+{
+ int ret;
+ u8 data;
+
+ ret = fusb302_i2c_read(dev, address, &data);
+ if (ret)
+ return ret;
+ data &= ~mask;
+ data |= value;
+ ret = fusb302_i2c_write(dev, address, data);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int fusb302_i2c_set_bits(struct udevice *dev, u8 address, u8 set_bits)
+{
+ return fusb302_i2c_mask_write(dev, address, 0x00, set_bits);
+}
+
+static int fusb302_i2c_clear_bits(struct udevice *dev, u8 address, u8 clear_bits)
+{
+ return fusb302_i2c_mask_write(dev, address, clear_bits, 0x00);
+}
+
+static int fusb302_sw_reset(struct udevice *dev)
+{
+ int ret = fusb302_i2c_write(dev, FUSB_REG_RESET, FUSB_REG_RESET_SW_RESET);
+
+ if (ret)
+ dev_err(dev, "cannot sw reset the fusb302: %d\n", ret);
+
+ return ret;
+}
+
+static int fusb302_enable_tx_auto_retries(struct udevice *dev, u8 retry_count)
+{
+ int ret;
+
+ ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3, retry_count |
+ FUSB_REG_CONTROL3_AUTO_RETRY);
+
+ return ret;
+}
+
+/*
+ * mask all interrupt on the chip
+ */
+static int fusb302_mask_interrupt(struct udevice *dev)
+{
+ int ret;
+
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASK, 0xFF);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_INT_MASK);
+ return ret;
+}
+
+/*
+ * initialize interrupt on the chip
+ * - unmasked interrupt: VBUS_OK
+ */
+static int fusb302_init_interrupt(struct udevice *dev)
+{
+ int ret;
+
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASK,
+ 0xFF & ~FUSB_REG_MASK_VBUSOK);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_INT_MASK);
+ return ret;
+}
+
+static int fusb302_set_power_mode(struct udevice *dev, u8 power_mode)
+{
+ int ret;
+
+ ret = fusb302_i2c_write(dev, FUSB_REG_POWER, power_mode);
+
+ return ret;
+}
+
+static int fusb302_init(struct udevice *dev)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+ u8 data;
+
+ ret = fusb302_sw_reset(dev);
+ if (ret)
+ return ret;
+ ret = fusb302_enable_tx_auto_retries(dev, FUSB_REG_CONTROL3_N_RETRIES_3);
+ if (ret)
+ return ret;
+ ret = fusb302_init_interrupt(dev);
+ if (ret)
+ return ret;
+ ret = fusb302_set_power_mode(dev, FUSB_REG_POWER_PWR_ALL);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &data);
+ if (ret)
+ return ret;
+ chip->vbus_present = !!(data & FUSB_REG_STATUS0_VBUSOK);
+ ret = fusb302_i2c_read(dev, FUSB_REG_DEVICE_ID, &data);
+ if (ret)
+ return ret;
+ dev_info(dev, "fusb302 device ID: 0x%02x\n", data);
+
+ return ret;
+}
+
+static int fusb302_get_vbus(struct udevice *dev)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+
+ return chip->vbus_present ? 1 : 0;
+}
+
+static int fusb302_set_src_current(struct udevice *dev,
+ enum src_current_status status)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+
+ chip->src_current_status = status;
+ switch (status) {
+ case SRC_CURRENT_DEFAULT:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_HOST_CUR_MASK,
+ FUSB_REG_CONTROL0_HOST_CUR_DEF);
+ break;
+ case SRC_CURRENT_MEDIUM:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_HOST_CUR_MASK,
+ FUSB_REG_CONTROL0_HOST_CUR_MED);
+ break;
+ case SRC_CURRENT_HIGH:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_HOST_CUR_MASK,
+ FUSB_REG_CONTROL0_HOST_CUR_HIGH);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int fusb302_set_toggling(struct udevice *dev,
+ enum toggling_mode mode)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+
+ /* first disable toggling */
+ ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_TOGGLE);
+ if (ret)
+ return ret;
+ /* mask interrupts for SRC or SNK */
+ ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASK,
+ FUSB_REG_MASK_BC_LVL |
+ FUSB_REG_MASK_COMP_CHNG);
+ if (ret)
+ return ret;
+ chip->intr_bc_lvl = false;
+ chip->intr_comp_chng = false;
+ /* configure toggling mode: none/snk/src/drp */
+ switch (mode) {
+ case TOGGLING_MODE_OFF:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_MODE_MASK,
+ FUSB_REG_CONTROL2_MODE_NONE);
+ break;
+ case TOGGLING_MODE_SNK:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_MODE_MASK,
+ FUSB_REG_CONTROL2_MODE_UFP);
+ break;
+ case TOGGLING_MODE_SRC:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_MODE_MASK,
+ FUSB_REG_CONTROL2_MODE_DFP);
+ break;
+ case TOGGLING_MODE_DRP:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_MODE_MASK,
+ FUSB_REG_CONTROL2_MODE_DRP);
+ break;
+ default:
+ break;
+ }
+
+ if (ret)
+ return ret;
+
+ if (mode == TOGGLING_MODE_OFF) {
+ /* mask TOGDONE interrupt */
+ ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASKA,
+ FUSB_REG_MASKA_TOGDONE);
+ if (ret)
+ return ret;
+ chip->intr_togdone = false;
+ } else {
+ /* Datasheet says vconn MUST be off when toggling */
+ if (chip->vconn_on)
+ dev_warn(dev, "Vconn is on during toggle start\n");
+ /* unmask TOGDONE interrupt */
+ ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA,
+ FUSB_REG_MASKA_TOGDONE);
+ if (ret)
+ return ret;
+ chip->intr_togdone = true;
+ /* start toggling */
+ ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL2,
+ FUSB_REG_CONTROL2_TOGGLE);
+ if (ret)
+ return ret;
+ /* during toggling, consider cc as Open */
+ chip->cc1 = TYPEC_CC_OPEN;
+ chip->cc2 = TYPEC_CC_OPEN;
+ }
+ chip->toggling_mode = mode;
+
+ return ret;
+}
+
+static const enum src_current_status cc_src_current[] = {
+ [TYPEC_CC_OPEN] = SRC_CURRENT_DEFAULT,
+ [TYPEC_CC_RA] = SRC_CURRENT_DEFAULT,
+ [TYPEC_CC_RD] = SRC_CURRENT_DEFAULT,
+ [TYPEC_CC_RP_DEF] = SRC_CURRENT_DEFAULT,
+ [TYPEC_CC_RP_1_5] = SRC_CURRENT_MEDIUM,
+ [TYPEC_CC_RP_3_0] = SRC_CURRENT_HIGH,
+};
+
+static int fusb302_set_cc(struct udevice *dev, enum typec_cc_status cc)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ const u8 switches0_mask = FUSB_REG_SWITCHES0_CC1_PU_EN |
+ FUSB_REG_SWITCHES0_CC2_PU_EN |
+ FUSB_REG_SWITCHES0_CC1_PD_EN |
+ FUSB_REG_SWITCHES0_CC2_PD_EN;
+ u8 rd_mda, switches0_data = 0x00;
+ int ret;
+
+ switch (cc) {
+ case TYPEC_CC_OPEN:
+ break;
+ case TYPEC_CC_RD:
+ switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN |
+ FUSB_REG_SWITCHES0_CC2_PD_EN;
+ break;
+ case TYPEC_CC_RP_DEF:
+ case TYPEC_CC_RP_1_5:
+ case TYPEC_CC_RP_3_0:
+ switches0_data |= (chip->cc_polarity == TYPEC_POLARITY_CC1) ?
+ FUSB_REG_SWITCHES0_CC1_PU_EN :
+ FUSB_REG_SWITCHES0_CC2_PU_EN;
+ break;
+ default:
+ dev_err(dev, "unsupported CC value: %s\n",
+ typec_cc_status_name[cc]);
+ ret = -EINVAL;
+ goto done;
+ }
+
+ ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+ if (ret) {
+ dev_err(dev, "cannot set toggling mode: %d\n", ret);
+ goto done;
+ }
+
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0,
+ switches0_mask, switches0_data);
+ if (ret) {
+ dev_err(dev, "cannot set pull-up/-down: %d\n", ret);
+ goto done;
+ }
+ /* reset the cc status */
+ chip->cc1 = TYPEC_CC_OPEN;
+ chip->cc2 = TYPEC_CC_OPEN;
+
+ /* adjust current for SRC */
+ ret = fusb302_set_src_current(dev, cc_src_current[cc]);
+ if (ret) {
+ dev_err(dev, "cannot set src current %s: %d\n",
+ typec_cc_status_name[cc], ret);
+ goto done;
+ }
+
+ /* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
+ switch (cc) {
+ case TYPEC_CC_RP_DEF:
+ case TYPEC_CC_RP_1_5:
+ case TYPEC_CC_RP_3_0:
+ rd_mda = rd_mda_value[cc_src_current[cc]];
+ ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+ if (ret) {
+ dev_err(dev, "cannot set SRC measure value: %d\n", ret);
+ goto done;
+ }
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK,
+ FUSB_REG_MASK_BC_LVL |
+ FUSB_REG_MASK_COMP_CHNG,
+ FUSB_REG_MASK_BC_LVL);
+ if (ret) {
+ dev_err(dev, "cannot set SRC irq: %d\n", ret);
+ goto done;
+ }
+ chip->intr_comp_chng = true;
+ break;
+ case TYPEC_CC_RD:
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK,
+ FUSB_REG_MASK_BC_LVL |
+ FUSB_REG_MASK_COMP_CHNG,
+ FUSB_REG_MASK_COMP_CHNG);
+ if (ret) {
+ dev_err(dev, "cannot set SRC irq: %d\n", ret);
+ goto done;
+ }
+ chip->intr_bc_lvl = true;
+ break;
+ default:
+ break;
+ }
+done:
+ return ret;
+}
+
+static int fusb302_get_cc(struct udevice *dev, enum typec_cc_status *cc1,
+ enum typec_cc_status *cc2)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+
+ *cc1 = chip->cc1;
+ *cc2 = chip->cc2;
+ dev_dbg(dev, "get cc1 = %s, cc2 = %s\n", typec_cc_status_name[*cc1],
+ typec_cc_status_name[*cc2]);
+
+ return 0;
+}
+
+static int fusb302_set_vconn(struct udevice *dev, bool on)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+ u8 switches0_data = 0x00;
+ u8 switches0_mask = FUSB_REG_SWITCHES0_VCONN_CC1 |
+ FUSB_REG_SWITCHES0_VCONN_CC2;
+
+ if (chip->vconn_on == on) {
+ ret = 0;
+ dev_dbg(dev, "vconn is already %s\n", on ? "on" : "off");
+ goto done;
+ }
+ if (on) {
+ switches0_data = (chip->cc_polarity == TYPEC_POLARITY_CC1) ?
+ FUSB_REG_SWITCHES0_VCONN_CC2 :
+ FUSB_REG_SWITCHES0_VCONN_CC1;
+ }
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0,
+ switches0_mask, switches0_data);
+ if (ret)
+ goto done;
+ dev_dbg(dev, "set vconn = %s\n", on ? "on" : "off");
+done:
+ return ret;
+}
+
+static int fusb302_set_vbus(struct udevice *dev, bool on, bool charge)
+{
+ return 0;
+}
+
+static int fusb302_pd_tx_flush(struct udevice *dev)
+{
+ return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0,
+ FUSB_REG_CONTROL0_TX_FLUSH);
+}
+
+static int fusb302_pd_rx_flush(struct udevice *dev)
+{
+ return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL1,
+ FUSB_REG_CONTROL1_RX_FLUSH);
+}
+
+static int fusb302_pd_set_auto_goodcrc(struct udevice *dev, bool on)
+{
+ if (on)
+ return fusb302_i2c_set_bits(dev, FUSB_REG_SWITCHES1,
+ FUSB_REG_SWITCHES1_AUTO_GCRC);
+ return fusb302_i2c_clear_bits(dev, FUSB_REG_SWITCHES1,
+ FUSB_REG_SWITCHES1_AUTO_GCRC);
+}
+
+static int fusb302_pd_set_interrupts(struct udevice *dev, bool on)
+{
+ int ret;
+ u8 mask_interrupts = FUSB_REG_MASK_COLLISION;
+ u8 maska_interrupts = FUSB_REG_MASKA_RETRYFAIL |
+ FUSB_REG_MASKA_HARDSENT |
+ FUSB_REG_MASKA_TX_SUCCESS |
+ FUSB_REG_MASKA_HARDRESET;
+ u8 maskb_interrupts = FUSB_REG_MASKB_GCRCSENT;
+
+ ret = on ?
+ fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, mask_interrupts) :
+ fusb302_i2c_set_bits(dev, FUSB_REG_MASK, mask_interrupts);
+ if (ret)
+ return ret;
+ ret = on ?
+ fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA, maska_interrupts) :
+ fusb302_i2c_set_bits(dev, FUSB_REG_MASKA, maska_interrupts);
+ if (ret)
+ return ret;
+ ret = on ?
+ fusb302_i2c_clear_bits(dev, FUSB_REG_MASKB, maskb_interrupts) :
+ fusb302_i2c_set_bits(dev, FUSB_REG_MASKB, maskb_interrupts);
+ return ret;
+}
+
+static int fusb302_set_pd_rx(struct udevice *dev, bool on)
+{
+ int ret;
+
+ ret = fusb302_pd_rx_flush(dev);
+ if (ret) {
+ dev_err(dev, "cannot flush pd rx buffer: %d\n", ret);
+ goto done;
+ }
+ ret = fusb302_pd_tx_flush(dev);
+ if (ret) {
+ dev_err(dev, "cannot flush pd tx buffer: %d\n", ret);
+ goto done;
+ }
+ ret = fusb302_pd_set_auto_goodcrc(dev, on);
+ if (ret) {
+ dev_err(dev, "cannot turn %s auto GoodCRC: %d\n",
+ on ? "on" : "off", ret);
+ goto done;
+ }
+ ret = fusb302_pd_set_interrupts(dev, on);
+ if (ret) {
+ dev_err(dev, "cannot turn %s pd interrupts: %d\n",
+ on ? "on" : "off", ret);
+ goto done;
+ }
+ dev_dbg(dev, "set pd RX %s\n", on ? "on" : "off");
+done:
+ return ret;
+}
+
+static int fusb302_set_roles(struct udevice *dev, bool attached,
+ enum typec_role pwr, enum typec_data_role data)
+{
+ int ret;
+ u8 switches1_mask = FUSB_REG_SWITCHES1_POWERROLE |
+ FUSB_REG_SWITCHES1_DATAROLE;
+ u8 switches1_data = 0x00;
+
+ if (pwr == TYPEC_SOURCE)
+ switches1_data |= FUSB_REG_SWITCHES1_POWERROLE;
+ if (data == TYPEC_HOST)
+ switches1_data |= FUSB_REG_SWITCHES1_DATAROLE;
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1,
+ switches1_mask, switches1_data);
+ if (ret) {
+ dev_err(dev, "unable to set pd header %s, %s, ret=%d\n",
+ typec_role_name[pwr], typec_data_role_name[data], ret);
+ goto done;
+ }
+ dev_dbg(dev, "pd header : %s, %s\n", typec_role_name[pwr],
+ typec_data_role_name[data]);
+done:
+
+ return ret;
+}
+
+static int fusb302_start_toggling(struct udevice *dev,
+ enum typec_port_type port_type,
+ enum typec_cc_status cc)
+{
+ enum toggling_mode mode = TOGGLING_MODE_OFF;
+ int ret;
+
+ switch (port_type) {
+ case TYPEC_PORT_SRC:
+ mode = TOGGLING_MODE_SRC;
+ break;
+ case TYPEC_PORT_SNK:
+ mode = TOGGLING_MODE_SNK;
+ break;
+ case TYPEC_PORT_DRP:
+ mode = TOGGLING_MODE_DRP;
+ break;
+ }
+
+ ret = fusb302_set_src_current(dev, cc_src_current[cc]);
+ if (ret) {
+ dev_err(dev, "unable to set src current %s, ret=%d",
+ typec_cc_status_name[cc], ret);
+ goto done;
+ }
+ ret = fusb302_set_toggling(dev, mode);
+ if (ret) {
+ dev_err(dev, "unable to start drp toggling: %d\n", ret);
+ goto done;
+ }
+ dev_info(dev, "fusb302 start drp toggling\n");
+done:
+
+ return ret;
+}
+
+static int fusb302_pd_send_message(struct udevice *dev,
+ const struct pd_message *msg)
+{
+ int ret;
+ /* SOP tokens */
+ u8 buf[40] = {FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1,
+ FUSB302_TKN_SYNC2};
+ u8 pos = 4;
+ int len;
+
+ len = pd_header_cnt_le(msg->header) * 4;
+ /* plug 2 for header */
+ len += 2;
+ if (len > FUSB302_MAX_MSG_LEN) {
+ dev_err(dev, "PD message too long %d (incl. header)", len);
+ return -EINVAL;
+ }
+ /* packsym tells the FUSB302 chip that the next X bytes are payload */
+ buf[pos++] = FUSB302_TKN_PACKSYM | (len & FUSB302_MAX_MSG_LEN);
+ memcpy(&buf[pos], &msg->header, sizeof(msg->header));
+ pos += sizeof(msg->header);
+
+ len -= 2;
+ memcpy(&buf[pos], msg->payload, len);
+ pos += len;
+
+ /* CRC */
+ buf[pos++] = FUSB302_TKN_JAMCRC;
+ /* EOP */
+ buf[pos++] = FUSB302_TKN_EOP;
+ /* turn tx off after sending message */
+ buf[pos++] = FUSB302_TKN_TXOFF;
+ /* start transmission */
+ buf[pos++] = FUSB302_TKN_TXON;
+
+ ret = fusb302_i2c_block_write(dev, FUSB_REG_FIFOS, pos, buf);
+ if (ret)
+ return ret;
+ dev_dbg(dev, "Send PD message (header=0x%x len=%d)\n", msg->header, len);
+
+ return ret;
+}
+
+static int fusb302_pd_send_hardreset(struct udevice *dev)
+{
+ return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3,
+ FUSB_REG_CONTROL3_SEND_HARDRESET);
+}
+
+static const char * const transmit_type_name[] = {
+ [TCPC_TX_SOP] = "SOP",
+ [TCPC_TX_SOP_PRIME] = "SOP'",
+ [TCPC_TX_SOP_PRIME_PRIME] = "SOP''",
+ [TCPC_TX_SOP_DEBUG_PRIME] = "DEBUG'",
+ [TCPC_TX_SOP_DEBUG_PRIME_PRIME] = "DEBUG''",
+ [TCPC_TX_HARD_RESET] = "HARD_RESET",
+ [TCPC_TX_CABLE_RESET] = "CABLE_RESET",
+ [TCPC_TX_BIST_MODE_2] = "BIST_MODE_2",
+};
+
+static int fusb302_pd_transmit(struct udevice *dev, enum tcpm_transmit_type type,
+ const struct pd_message *msg, unsigned int negotiated_rev)
+{
+ int ret;
+
+ switch (type) {
+ case TCPC_TX_SOP:
+ /* nRetryCount 3 in P2.0 spec, whereas 2 in PD3.0 spec */
+ ret = fusb302_enable_tx_auto_retries(dev, negotiated_rev > PD_REV20 ?
+ FUSB_REG_CONTROL3_N_RETRIES_2 :
+ FUSB_REG_CONTROL3_N_RETRIES_3);
+ if (ret)
+ dev_err(dev, "cannot update retry count: %d\n", ret);
+
+ ret = fusb302_pd_send_message(dev, msg);
+ if (ret)
+ dev_err(dev, "cannot send PD message: %d\n", ret);
+ break;
+ case TCPC_TX_HARD_RESET:
+ ret = fusb302_pd_send_hardreset(dev);
+ if (ret)
+ dev_err(dev, "cannot send hardreset: %d\n", ret);
+ break;
+ default:
+ dev_err(dev, "type %s not supported", transmit_type_name[type]);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static enum typec_cc_status fusb302_bc_lvl_to_cc(u8 bc_lvl)
+{
+ if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_1230_MAX)
+ return TYPEC_CC_RP_3_0;
+ if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_600_1230)
+ return TYPEC_CC_RP_1_5;
+ if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_200_600)
+ return TYPEC_CC_RP_DEF;
+ return TYPEC_CC_OPEN;
+}
+
+static void fusb302_bc_lvl_handler(struct udevice *dev)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ enum typec_cc_status cc_status;
+ u8 status0, bc_lvl;
+ int ret;
+
+ if (!chip->intr_bc_lvl) {
+ dev_err(dev, "BC_LVL interrupt is turned off, abort\n");
+ goto done;
+ }
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+ if (ret)
+ goto done;
+
+ dev_dbg(dev, "BC_LVL handler, status0 = 0x%02x\n", status0);
+ if (status0 & FUSB_REG_STATUS0_ACTIVITY)
+ dev_info(dev, "CC activities detected, delay handling\n");
+ bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK;
+ cc_status = fusb302_bc_lvl_to_cc(bc_lvl);
+ if (chip->cc_polarity == TYPEC_POLARITY_CC1) {
+ if (chip->cc1 != cc_status) {
+ dev_dbg(dev, "cc1: %s -> %s\n",
+ typec_cc_status_name[chip->cc1],
+ typec_cc_status_name[cc_status]);
+ chip->cc1 = cc_status;
+ tcpm_cc_change(dev);
+ }
+ } else {
+ if (chip->cc2 != cc_status) {
+ dev_dbg(dev, "cc2: %s -> %s\n",
+ typec_cc_status_name[chip->cc2],
+ typec_cc_status_name[cc_status]);
+ chip->cc2 = cc_status;
+ tcpm_cc_change(dev);
+ }
+ }
+
+done:
+ return;
+}
+
+static int fusb302_enter_low_power_mode(struct udevice *dev,
+ bool attached, bool pd_capable)
+{
+ unsigned int reg;
+ int ret;
+
+ ret = fusb302_mask_interrupt(dev);
+ if (ret)
+ return ret;
+ if (attached && pd_capable)
+ reg = FUSB_REG_POWER_PWR_MEDIUM;
+ else if (attached)
+ reg = FUSB_REG_POWER_PWR_LOW;
+ else
+ reg = 0;
+
+ return fusb302_set_power_mode(dev, reg);
+}
+
+static const char * const cc_polarity_name[] = {
+ [TYPEC_POLARITY_CC1] = "Polarity_CC1",
+ [TYPEC_POLARITY_CC2] = "Polarity_CC2",
+};
+
+static int fusb302_set_cc_polarity_and_pull(struct udevice *dev,
+ enum typec_cc_polarity cc_polarity,
+ bool pull_up, bool pull_down)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+ u8 switches0_data = 0x00;
+ u8 switches1_mask = FUSB_REG_SWITCHES1_TXCC1_EN |
+ FUSB_REG_SWITCHES1_TXCC2_EN;
+ u8 switches1_data = 0x00;
+
+ if (pull_down)
+ switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN |
+ FUSB_REG_SWITCHES0_CC2_PD_EN;
+
+ if (cc_polarity == TYPEC_POLARITY_CC1) {
+ switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC1;
+ if (chip->vconn_on)
+ switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC2;
+ if (pull_up)
+ switches0_data |= FUSB_REG_SWITCHES0_CC1_PU_EN;
+ switches1_data = FUSB_REG_SWITCHES1_TXCC1_EN;
+ } else {
+ switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC2;
+ if (chip->vconn_on)
+ switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC1;
+ if (pull_up)
+ switches0_data |= FUSB_REG_SWITCHES0_CC2_PU_EN;
+ switches1_data = FUSB_REG_SWITCHES1_TXCC2_EN;
+ }
+ ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1,
+ switches1_mask, switches1_data);
+ if (ret)
+ return ret;
+ chip->cc_polarity = cc_polarity;
+
+ return ret;
+}
+
+static int fusb302_handle_togdone_snk(struct udevice *dev,
+ u8 togdone_result)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ int ret;
+ u8 status0;
+ u8 bc_lvl;
+ enum typec_cc_polarity cc_polarity;
+ enum typec_cc_status cc_status_active, cc1, cc2;
+
+ /* set polarity and pull_up, pull_down */
+ cc_polarity = (togdone_result == FUSB_REG_STATUS1A_TOGSS_SNK1) ?
+ TYPEC_POLARITY_CC1 : TYPEC_POLARITY_CC2;
+ ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, false, true);
+ if (ret) {
+ dev_err(dev, "cannot set cc polarity %s, ret = %d\n",
+ cc_polarity_name[cc_polarity], ret);
+ return ret;
+ }
+ /* fusb302_set_cc_polarity() has set the correct measure block */
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+ if (ret < 0)
+ return ret;
+ bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK;
+ cc_status_active = fusb302_bc_lvl_to_cc(bc_lvl);
+ /* restart toggling if the cc status on the active line is OPEN */
+ if (cc_status_active == TYPEC_CC_OPEN) {
+ dev_info(dev, "restart toggling as CC_OPEN detected\n");
+ ret = fusb302_set_toggling(dev, chip->toggling_mode);
+ return ret;
+ }
+ /* update tcpm with the new cc value */
+ cc1 = (cc_polarity == TYPEC_POLARITY_CC1) ?
+ cc_status_active : TYPEC_CC_OPEN;
+ cc2 = (cc_polarity == TYPEC_POLARITY_CC2) ?
+ cc_status_active : TYPEC_CC_OPEN;
+ if (chip->cc1 != cc1 || chip->cc2 != cc2) {
+ chip->cc1 = cc1;
+ chip->cc2 = cc2;
+ tcpm_cc_change(dev);
+ }
+ /* turn off toggling */
+ ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+ if (ret) {
+ dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret);
+ return ret;
+ }
+ /* unmask bc_lvl interrupt */
+ ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, FUSB_REG_MASK_BC_LVL);
+ if (ret) {
+ dev_err(dev, "cannot unmask bc_lcl irq, ret=%d\n", ret);
+ return ret;
+ }
+ chip->intr_bc_lvl = true;
+ dev_dbg(dev, "detected cc1=%s, cc2=%s\n",
+ typec_cc_status_name[cc1],
+ typec_cc_status_name[cc2]);
+
+ return ret;
+}
+
+/* On error returns < 0, otherwise a typec_cc_status value */
+static int fusb302_get_src_cc_status(struct udevice *dev,
+ enum typec_cc_polarity cc_polarity,
+ enum typec_cc_status *cc)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ u8 ra_mda = ra_mda_value[chip->src_current_status];
+ u8 rd_mda = rd_mda_value[chip->src_current_status];
+ u8 switches0_data, status0;
+ int ret;
+
+ /* Step 1: Set switches so that we measure the right CC pin */
+ switches0_data = (cc_polarity == TYPEC_POLARITY_CC1) ?
+ FUSB_REG_SWITCHES0_CC1_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC1 :
+ FUSB_REG_SWITCHES0_CC2_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC2;
+ ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data);
+ if (ret < 0)
+ return ret;
+
+ fusb302_i2c_read(dev, FUSB_REG_SWITCHES0, &status0);
+ dev_dbg(dev, "get_src_cc_status switches: 0x%0x", status0);
+
+ /* Step 2: Set compararator volt to differentiate between Open and Rd */
+ ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+ if (ret)
+ return ret;
+
+ udelay(100);
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "get_src_cc_status rd_mda status0: 0x%0x", status0);
+ if (status0 & FUSB_REG_STATUS0_COMP) {
+ *cc = TYPEC_CC_OPEN;
+ return 0;
+ }
+
+ /* Step 3: Set compararator input to differentiate between Rd and Ra. */
+ ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, ra_mda);
+ if (ret)
+ return ret;
+
+ udelay(100);
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "get_src_cc_status ra_mda status0: 0x%0x", status0);
+ if (status0 & FUSB_REG_STATUS0_COMP)
+ *cc = TYPEC_CC_RD;
+ else
+ *cc = TYPEC_CC_RA;
+
+ return 0;
+}
+
+static int fusb302_handle_togdone_src(struct udevice *dev,
+ u8 togdone_result)
+{
+ /*
+ * - set polarity (measure cc, vconn, tx)
+ * - set pull_up, pull_down
+ * - set cc1, cc2, and update to tcpm state machine
+ * - set I_COMP interrupt on
+ */
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ u8 rd_mda = rd_mda_value[chip->src_current_status];
+ enum toggling_mode toggling_mode = chip->toggling_mode;
+ enum typec_cc_polarity cc_polarity;
+ enum typec_cc_status cc1, cc2;
+ int ret;
+
+ /*
+ * The toggle-engine will stop in a src state if it sees either Ra or
+ * Rd. Determine the status for both CC pins, starting with the one
+ * where toggling stopped, as that is where the switches point now.
+ */
+ if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1)
+ ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1);
+ else
+ ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2);
+ if (ret)
+ return ret;
+ /* we must turn off toggling before we can measure the other pin */
+ ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF);
+ if (ret) {
+ dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret);
+ return ret;
+ }
+ /* get the status of the other pin */
+ if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1)
+ ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2);
+ else
+ ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1);
+ if (ret)
+ return ret;
+
+ /* determine polarity based on the status of both pins */
+ if (cc1 == TYPEC_CC_RD && (cc2 == TYPEC_CC_OPEN || cc2 == TYPEC_CC_RA)) {
+ cc_polarity = TYPEC_POLARITY_CC1;
+ } else if (cc2 == TYPEC_CC_RD &&
+ (cc1 == TYPEC_CC_OPEN || cc1 == TYPEC_CC_RA)) {
+ cc_polarity = TYPEC_POLARITY_CC2;
+ } else {
+ dev_err(dev, "unexpected CC status cc1=%s, cc2=%s, restarting toggling\n",
+ typec_cc_status_name[cc1],
+ typec_cc_status_name[cc2]);
+ return fusb302_set_toggling(dev, toggling_mode);
+ }
+ /* set polarity and pull_up, pull_down */
+ ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, true, false);
+ if (ret < 0) {
+ dev_err(dev, "cannot set cc polarity %s, ret=%d\n",
+ cc_polarity_name[cc_polarity], ret);
+ return ret;
+ }
+ /* update tcpm with the new cc value */
+ if (chip->cc1 != cc1 || chip->cc2 != cc2) {
+ chip->cc1 = cc1;
+ chip->cc2 = cc2;
+ tcpm_cc_change(dev);
+ }
+ /* set MDAC to Rd threshold, and unmask I_COMP for unplug detection */
+ ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda);
+ if (ret)
+ return ret;
+ /* unmask comp_chng interrupt */
+ ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK,
+ FUSB_REG_MASK_COMP_CHNG);
+ if (ret) {
+ dev_err(dev, "cannot unmask comp_chng irq, ret=%d\n", ret);
+ return ret;
+ }
+ chip->intr_comp_chng = true;
+ dev_dbg(dev, "detected cc1=%s, cc2=%s\n",
+ typec_cc_status_name[cc1],
+ typec_cc_status_name[cc2]);
+
+ return ret;
+}
+
+static int fusb302_handle_togdone(struct udevice *dev)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ u8 togdone_result, status1a;
+ int ret;
+
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS1A, &status1a);
+ if (ret < 0)
+ return ret;
+ togdone_result = (status1a >> FUSB_REG_STATUS1A_TOGSS_POS) &
+ FUSB_REG_STATUS1A_TOGSS_MASK;
+ switch (togdone_result) {
+ case FUSB_REG_STATUS1A_TOGSS_SNK1:
+ case FUSB_REG_STATUS1A_TOGSS_SNK2:
+ return fusb302_handle_togdone_snk(dev, togdone_result);
+ case FUSB_REG_STATUS1A_TOGSS_SRC1:
+ case FUSB_REG_STATUS1A_TOGSS_SRC2:
+ return fusb302_handle_togdone_src(dev, togdone_result);
+ case FUSB_REG_STATUS1A_TOGSS_AA:
+ /* doesn't support */
+ dev_err(dev, "AudioAccessory not supported\n");
+ fusb302_set_toggling(dev, chip->toggling_mode);
+ break;
+ default:
+ dev_err(dev, "TOGDONE with an invalid state: %d\n",
+ togdone_result);
+ fusb302_set_toggling(dev, chip->toggling_mode);
+ break;
+ }
+ return ret;
+}
+
+static int fusb302_pd_reset(struct udevice *dev)
+{
+ return fusb302_i2c_set_bits(dev, FUSB_REG_RESET,
+ FUSB_REG_RESET_PD_RESET);
+}
+
+static int fusb302_pd_read_message(struct udevice *dev,
+ struct pd_message *msg)
+{
+ int len, ret;
+ u8 crc[4];
+ u8 token;
+
+ /* first SOP token */
+ ret = fusb302_i2c_read(dev, FUSB_REG_FIFOS, &token);
+ if (ret)
+ return ret;
+ ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 2,
+ (u8 *)&msg->header);
+ if (ret)
+ return ret;
+ len = pd_header_cnt_le(msg->header) * 4;
+ /* add 4 to length to include the CRC */
+ if (len > PD_MAX_PAYLOAD * 4) {
+ dev_err(dev, "PD message too long %d\n", len);
+ return -EINVAL;
+ }
+ if (len > 0) {
+ ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, len,
+ (u8 *)msg->payload);
+ if (ret)
+ return ret;
+ }
+ /* another 4 bytes to read CRC out */
+ ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 4, crc);
+ if (ret)
+ return ret;
+ dev_dbg(dev, "Received PD message (header=0x%x len=%d)\n", msg->header, len);
+
+ /*
+ * Check if we've read off a GoodCRC message. If so then indicate to
+ * TCPM that the previous transmission has completed. Otherwise we pass
+ * the received message over to TCPM for processing.
+ *
+ * We make this check here instead of basing the reporting decision on
+ * the IRQ event type, as it's possible for the chip to report the
+ * TX_SUCCESS and GCRCSENT events out of order on occasion, so we need
+ * to check the message type to ensure correct reporting to TCPM.
+ */
+ if (!len && (pd_header_type_le(msg->header) == PD_CTRL_GOOD_CRC))
+ tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS);
+ else
+ tcpm_pd_receive(dev, msg);
+
+ return ret;
+}
+
+static void fusb302_interrupt_handle(struct udevice *dev)
+{
+ struct fusb302_chip *chip = dev_get_priv(dev);
+ u8 interrupt;
+ u8 interrupta;
+ u8 interruptb;
+ u8 status0;
+ bool vbus_present;
+ bool comp_result;
+ bool intr_togdone;
+ bool intr_bc_lvl;
+ bool intr_comp_chng;
+ struct pd_message pd_msg;
+ int ret;
+
+ /* grab a snapshot of intr flags */
+ intr_togdone = chip->intr_togdone;
+ intr_bc_lvl = chip->intr_bc_lvl;
+ intr_comp_chng = chip->intr_comp_chng;
+
+ ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPT, &interrupt);
+ if (ret)
+ return;
+ ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTA, &interrupta);
+ if (ret)
+ return;
+ ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTB, &interruptb);
+ if (ret)
+ return;
+ ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0);
+ if (ret)
+ return;
+
+ /*
+ * Since we are polling the IRQs, avoid printing messages when there
+ * no interrupts at all to avoid spamming the log.
+ */
+ if (interrupt != 0 || interrupta != 0 || interruptb != 0)
+ dev_dbg(dev, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x\n",
+ interrupt, interrupta, interruptb, status0);
+
+ if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+ vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
+ dev_dbg(dev, "IRQ: VBUS_OK, vbus=%s\n",
+ vbus_present ? "On" : "Off");
+ if (vbus_present != chip->vbus_present) {
+ chip->vbus_present = vbus_present;
+ tcpm_vbus_change(dev);
+ }
+ }
+
+ if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
+ dev_dbg(dev, "IRQ: TOGDONE\n");
+ ret = fusb302_handle_togdone(dev);
+ if (ret) {
+ dev_err(dev, "handle togdone error: %d\n", ret);
+ return;
+ }
+ }
+
+ if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) {
+ dev_dbg(dev, "IRQ: BC_LVL, handler pending\n");
+ fusb302_bc_lvl_handler(dev);
+ }
+
+ if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) {
+ comp_result = !!(status0 & FUSB_REG_STATUS0_COMP);
+ dev_dbg(dev, "IRQ: COMP_CHNG, comp=%s\n",
+ comp_result ? "true" : "false");
+ if (comp_result) {
+ /* cc level > Rd_threshold, detach */
+ chip->cc1 = TYPEC_CC_OPEN;
+ chip->cc2 = TYPEC_CC_OPEN;
+ tcpm_cc_change(dev);
+ }
+ }
+
+ if (interrupt & FUSB_REG_INTERRUPT_COLLISION) {
+ dev_dbg(dev, "IRQ: PD collision\n");
+ tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED);
+ }
+
+ if (interrupta & FUSB_REG_INTERRUPTA_RETRYFAIL) {
+ dev_dbg(dev, "IRQ: PD retry failed\n");
+ tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED);
+ }
+
+ if (interrupta & FUSB_REG_INTERRUPTA_HARDSENT) {
+ dev_dbg(dev, "IRQ: PD hardreset sent\n");
+ ret = fusb302_pd_reset(dev);
+ if (ret) {
+ dev_err(dev, "cannot PD reset, ret=%d\n", ret);
+ return;
+ }
+ tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS);
+ }
+
+ if (interrupta & FUSB_REG_INTERRUPTA_TX_SUCCESS) {
+ dev_dbg(dev, "IRQ: PD tx success\n");
+ ret = fusb302_pd_read_message(dev, &pd_msg);
+ if (ret) {
+ dev_err(dev, "cannot read in PD message, ret=%d\n", ret);
+ return;
+ }
+ }
+
+ if (interrupta & FUSB_REG_INTERRUPTA_HARDRESET) {
+ dev_dbg(dev, "IRQ: PD received hardreset\n");
+ ret = fusb302_pd_reset(dev);
+ if (ret) {
+ dev_err(dev, "cannot PD reset, ret=%d\n", ret);
+ return;
+ }
+ tcpm_pd_hard_reset(dev);
+ }
+
+ if (interruptb & FUSB_REG_INTERRUPTB_GCRCSENT) {
+ dev_dbg(dev, "IRQ: PD sent good CRC\n");
+ ret = fusb302_pd_read_message(dev, &pd_msg);
+ if (ret) {
+ dev_err(dev, "cannot read in PD message, ret=%d\n", ret);
+ return;
+ }
+ }
+}
+
+static void fusb302_poll_event(struct udevice *dev)
+{
+ fusb302_interrupt_handle(dev);
+}
+
+static int fusb302_get_connector_node(struct udevice *dev, ofnode *connector_node)
+{
+ *connector_node = dev_read_subnode(dev, "connector");
+ if (!ofnode_valid(*connector_node)) {
+ dev_err(dev, "'connector' node is not found\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct dm_tcpm_ops fusb302_ops = {
+ .get_connector_node = fusb302_get_connector_node,
+ .init = fusb302_init,
+ .get_vbus = fusb302_get_vbus,
+ .set_cc = fusb302_set_cc,
+ .get_cc = fusb302_get_cc,
+ .set_vconn = fusb302_set_vconn,
+ .set_vbus = fusb302_set_vbus,
+ .set_pd_rx = fusb302_set_pd_rx,
+ .set_roles = fusb302_set_roles,
+ .start_toggling = fusb302_start_toggling,
+ .pd_transmit = fusb302_pd_transmit,
+ .poll_event = fusb302_poll_event,
+ .enter_low_power_mode = fusb302_enter_low_power_mode,
+};
+
+static const struct udevice_id fusb302_ids[] = {
+ { .compatible = "fcs,fusb302" },
+ { }
+};
+
+U_BOOT_DRIVER(fusb302) = {
+ .name = "fusb302",
+ .id = UCLASS_TCPM,
+ .of_match = fusb302_ids,
+ .ops = &fusb302_ops,
+ .priv_auto = sizeof(struct fusb302_chip),
+};
diff --git a/drivers/usb/tcpm/fusb302_reg.h b/drivers/usb/tcpm/fusb302_reg.h
new file mode 100644
index 0000000..edc0e4b0
--- /dev/null
+++ b/drivers/usb/tcpm/fusb302_reg.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016-2017 Google, Inc
+ *
+ * Fairchild FUSB302 Type-C Chip Driver
+ */
+
+#ifndef FUSB302_REG_H
+#define FUSB302_REG_H
+
+#define FUSB_REG_DEVICE_ID 0x01
+#define FUSB_REG_SWITCHES0 0x02
+#define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
+#define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
+#define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
+#define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
+#define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
+#define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
+#define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
+#define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0)
+#define FUSB_REG_SWITCHES1 0x03
+#define FUSB_REG_SWITCHES1_POWERROLE BIT(7)
+#define FUSB_REG_SWITCHES1_SPECREV1 BIT(6)
+#define FUSB_REG_SWITCHES1_SPECREV0 BIT(5)
+#define FUSB_REG_SWITCHES1_DATAROLE BIT(4)
+#define FUSB_REG_SWITCHES1_AUTO_GCRC BIT(2)
+#define FUSB_REG_SWITCHES1_TXCC2_EN BIT(1)
+#define FUSB_REG_SWITCHES1_TXCC1_EN BIT(0)
+#define FUSB_REG_MEASURE 0x04
+#define FUSB_REG_MEASURE_MDAC5 BIT(7)
+#define FUSB_REG_MEASURE_MDAC4 BIT(6)
+#define FUSB_REG_MEASURE_MDAC3 BIT(5)
+#define FUSB_REG_MEASURE_MDAC2 BIT(4)
+#define FUSB_REG_MEASURE_MDAC1 BIT(3)
+#define FUSB_REG_MEASURE_MDAC0 BIT(2)
+#define FUSB_REG_MEASURE_VBUS BIT(1)
+#define FUSB_REG_MEASURE_XXXX5 BIT(0)
+#define FUSB_REG_CONTROL0 0x06
+#define FUSB_REG_CONTROL0_TX_FLUSH BIT(6)
+#define FUSB_REG_CONTROL0_INT_MASK BIT(5)
+#define FUSB_REG_CONTROL0_HOST_CUR_MASK (0xC)
+#define FUSB_REG_CONTROL0_HOST_CUR_HIGH (0xC)
+#define FUSB_REG_CONTROL0_HOST_CUR_MED (0x8)
+#define FUSB_REG_CONTROL0_HOST_CUR_DEF (0x4)
+#define FUSB_REG_CONTROL0_TX_START BIT(0)
+#define FUSB_REG_CONTROL1 0x07
+#define FUSB_REG_CONTROL1_ENSOP2DB BIT(6)
+#define FUSB_REG_CONTROL1_ENSOP1DB BIT(5)
+#define FUSB_REG_CONTROL1_BIST_MODE2 BIT(4)
+#define FUSB_REG_CONTROL1_RX_FLUSH BIT(2)
+#define FUSB_REG_CONTROL1_ENSOP2 BIT(1)
+#define FUSB_REG_CONTROL1_ENSOP1 BIT(0)
+#define FUSB_REG_CONTROL2 0x08
+#define FUSB_REG_CONTROL2_MODE BIT(1)
+#define FUSB_REG_CONTROL2_MODE_MASK (0x6)
+#define FUSB_REG_CONTROL2_MODE_DFP (0x6)
+#define FUSB_REG_CONTROL2_MODE_UFP (0x4)
+#define FUSB_REG_CONTROL2_MODE_DRP (0x2)
+#define FUSB_REG_CONTROL2_MODE_NONE (0x0)
+#define FUSB_REG_CONTROL2_TOGGLE BIT(0)
+#define FUSB_REG_CONTROL3 0x09
+#define FUSB_REG_CONTROL3_SEND_HARDRESET BIT(6)
+#define FUSB_REG_CONTROL3_BIST_TMODE BIT(5) /* 302B Only */
+#define FUSB_REG_CONTROL3_AUTO_HARDRESET BIT(4)
+#define FUSB_REG_CONTROL3_AUTO_SOFTRESET BIT(3)
+#define FUSB_REG_CONTROL3_N_RETRIES BIT(1)
+#define FUSB_REG_CONTROL3_N_RETRIES_MASK (0x6)
+#define FUSB_REG_CONTROL3_N_RETRIES_3 (0x6)
+#define FUSB_REG_CONTROL3_N_RETRIES_2 (0x4)
+#define FUSB_REG_CONTROL3_N_RETRIES_1 (0x2)
+#define FUSB_REG_CONTROL3_AUTO_RETRY BIT(0)
+#define FUSB_REG_MASK 0x0A
+#define FUSB_REG_MASK_VBUSOK BIT(7)
+#define FUSB_REG_MASK_ACTIVITY BIT(6)
+#define FUSB_REG_MASK_COMP_CHNG BIT(5)
+#define FUSB_REG_MASK_CRC_CHK BIT(4)
+#define FUSB_REG_MASK_ALERT BIT(3)
+#define FUSB_REG_MASK_WAKE BIT(2)
+#define FUSB_REG_MASK_COLLISION BIT(1)
+#define FUSB_REG_MASK_BC_LVL BIT(0)
+#define FUSB_REG_POWER 0x0B
+#define FUSB_REG_POWER_PWR BIT(0)
+#define FUSB_REG_POWER_PWR_LOW 0x1
+#define FUSB_REG_POWER_PWR_MEDIUM 0x3
+#define FUSB_REG_POWER_PWR_HIGH 0x7
+#define FUSB_REG_POWER_PWR_ALL 0xF
+#define FUSB_REG_RESET 0x0C
+#define FUSB_REG_RESET_PD_RESET BIT(1)
+#define FUSB_REG_RESET_SW_RESET BIT(0)
+#define FUSB_REG_MASKA 0x0E
+#define FUSB_REG_MASKA_OCP_TEMP BIT(7)
+#define FUSB_REG_MASKA_TOGDONE BIT(6)
+#define FUSB_REG_MASKA_SOFTFAIL BIT(5)
+#define FUSB_REG_MASKA_RETRYFAIL BIT(4)
+#define FUSB_REG_MASKA_HARDSENT BIT(3)
+#define FUSB_REG_MASKA_TX_SUCCESS BIT(2)
+#define FUSB_REG_MASKA_SOFTRESET BIT(1)
+#define FUSB_REG_MASKA_HARDRESET BIT(0)
+#define FUSB_REG_MASKB 0x0F
+#define FUSB_REG_MASKB_GCRCSENT BIT(0)
+#define FUSB_REG_STATUS0A 0x3C
+#define FUSB_REG_STATUS0A_SOFTFAIL BIT(5)
+#define FUSB_REG_STATUS0A_RETRYFAIL BIT(4)
+#define FUSB_REG_STATUS0A_POWER BIT(2)
+#define FUSB_REG_STATUS0A_RX_SOFT_RESET BIT(1)
+#define FUSB_REG_STATUS0A_RX_HARD_RESET BIT(0)
+#define FUSB_REG_STATUS1A 0x3D
+#define FUSB_REG_STATUS1A_TOGSS BIT(3)
+#define FUSB_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define FUSB_REG_STATUS1A_TOGSS_SRC1 0x1
+#define FUSB_REG_STATUS1A_TOGSS_SRC2 0x2
+#define FUSB_REG_STATUS1A_TOGSS_SNK1 0x5
+#define FUSB_REG_STATUS1A_TOGSS_SNK2 0x6
+#define FUSB_REG_STATUS1A_TOGSS_AA 0x7
+#define FUSB_REG_STATUS1A_TOGSS_POS (3)
+#define FUSB_REG_STATUS1A_TOGSS_MASK (0x7)
+#define FUSB_REG_STATUS1A_RXSOP2DB BIT(2)
+#define FUSB_REG_STATUS1A_RXSOP1DB BIT(1)
+#define FUSB_REG_STATUS1A_RXSOP BIT(0)
+#define FUSB_REG_INTERRUPTA 0x3E
+#define FUSB_REG_INTERRUPTA_OCP_TEMP BIT(7)
+#define FUSB_REG_INTERRUPTA_TOGDONE BIT(6)
+#define FUSB_REG_INTERRUPTA_SOFTFAIL BIT(5)
+#define FUSB_REG_INTERRUPTA_RETRYFAIL BIT(4)
+#define FUSB_REG_INTERRUPTA_HARDSENT BIT(3)
+#define FUSB_REG_INTERRUPTA_TX_SUCCESS BIT(2)
+#define FUSB_REG_INTERRUPTA_SOFTRESET BIT(1)
+#define FUSB_REG_INTERRUPTA_HARDRESET BIT(0)
+#define FUSB_REG_INTERRUPTB 0x3F
+#define FUSB_REG_INTERRUPTB_GCRCSENT BIT(0)
+#define FUSB_REG_STATUS0 0x40
+#define FUSB_REG_STATUS0_VBUSOK BIT(7)
+#define FUSB_REG_STATUS0_ACTIVITY BIT(6)
+#define FUSB_REG_STATUS0_COMP BIT(5)
+#define FUSB_REG_STATUS0_CRC_CHK BIT(4)
+#define FUSB_REG_STATUS0_ALERT BIT(3)
+#define FUSB_REG_STATUS0_WAKE BIT(2)
+#define FUSB_REG_STATUS0_BC_LVL_MASK 0x03
+#define FUSB_REG_STATUS0_BC_LVL_0_200 0x0
+#define FUSB_REG_STATUS0_BC_LVL_200_600 0x1
+#define FUSB_REG_STATUS0_BC_LVL_600_1230 0x2
+#define FUSB_REG_STATUS0_BC_LVL_1230_MAX 0x3
+#define FUSB_REG_STATUS0_BC_LVL1 BIT(1)
+#define FUSB_REG_STATUS0_BC_LVL0 BIT(0)
+#define FUSB_REG_STATUS1 0x41
+#define FUSB_REG_STATUS1_RXSOP2 BIT(7)
+#define FUSB_REG_STATUS1_RXSOP1 BIT(6)
+#define FUSB_REG_STATUS1_RX_EMPTY BIT(5)
+#define FUSB_REG_STATUS1_RX_FULL BIT(4)
+#define FUSB_REG_STATUS1_TX_EMPTY BIT(3)
+#define FUSB_REG_STATUS1_TX_FULL BIT(2)
+#define FUSB_REG_INTERRUPT 0x42
+#define FUSB_REG_INTERRUPT_VBUSOK BIT(7)
+#define FUSB_REG_INTERRUPT_ACTIVITY BIT(6)
+#define FUSB_REG_INTERRUPT_COMP_CHNG BIT(5)
+#define FUSB_REG_INTERRUPT_CRC_CHK BIT(4)
+#define FUSB_REG_INTERRUPT_ALERT BIT(3)
+#define FUSB_REG_INTERRUPT_WAKE BIT(2)
+#define FUSB_REG_INTERRUPT_COLLISION BIT(1)
+#define FUSB_REG_INTERRUPT_BC_LVL BIT(0)
+#define FUSB_REG_FIFOS 0x43
+
+/* Tokens defined for the FUSB302 TX FIFO */
+enum fusb302_txfifo_tokens {
+ FUSB302_TKN_TXON = 0xA1,
+ FUSB302_TKN_SYNC1 = 0x12,
+ FUSB302_TKN_SYNC2 = 0x13,
+ FUSB302_TKN_SYNC3 = 0x1B,
+ FUSB302_TKN_RST1 = 0x15,
+ FUSB302_TKN_RST2 = 0x16,
+ FUSB302_TKN_PACKSYM = 0x80,
+ FUSB302_TKN_JAMCRC = 0xFF,
+ FUSB302_TKN_EOP = 0x14,
+ FUSB302_TKN_TXOFF = 0xFE,
+};
+
+#endif
diff --git a/drivers/usb/tcpm/tcpm-internal.h b/drivers/usb/tcpm/tcpm-internal.h
new file mode 100644
index 0000000..5614420
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm-internal.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ * Copyright 2024 Collabora
+ */
+
+#ifndef __LINUX_USB_TCPM_INTERNAL_H
+#define __LINUX_USB_TCPM_INTERNAL_H
+
+#define FOREACH_TCPM_STATE(S) \
+ S(INVALID_STATE), \
+ S(TOGGLING), \
+ S(SRC_UNATTACHED), \
+ S(SRC_ATTACH_WAIT), \
+ S(SRC_ATTACHED), \
+ S(SRC_STARTUP), \
+ S(SRC_SEND_CAPABILITIES), \
+ S(SRC_SEND_CAPABILITIES_TIMEOUT), \
+ S(SRC_NEGOTIATE_CAPABILITIES), \
+ S(SRC_TRANSITION_SUPPLY), \
+ S(SRC_READY), \
+ S(SRC_WAIT_NEW_CAPABILITIES), \
+ \
+ S(SNK_UNATTACHED), \
+ S(SNK_ATTACH_WAIT), \
+ S(SNK_DEBOUNCED), \
+ S(SNK_ATTACHED), \
+ S(SNK_STARTUP), \
+ S(SNK_DISCOVERY), \
+ S(SNK_DISCOVERY_DEBOUNCE), \
+ S(SNK_DISCOVERY_DEBOUNCE_DONE), \
+ S(SNK_WAIT_CAPABILITIES), \
+ S(SNK_NEGOTIATE_CAPABILITIES), \
+ S(SNK_TRANSITION_SINK), \
+ S(SNK_TRANSITION_SINK_VBUS), \
+ S(SNK_READY), \
+ \
+ S(HARD_RESET_SEND), \
+ S(HARD_RESET_START), \
+ S(SRC_HARD_RESET_VBUS_OFF), \
+ S(SRC_HARD_RESET_VBUS_ON), \
+ S(SNK_HARD_RESET_SINK_OFF), \
+ S(SNK_HARD_RESET_WAIT_VBUS), \
+ S(SNK_HARD_RESET_SINK_ON), \
+ \
+ S(SOFT_RESET), \
+ S(SOFT_RESET_SEND), \
+ \
+ S(DR_SWAP_ACCEPT), \
+ S(DR_SWAP_CHANGE_DR), \
+ \
+ S(ERROR_RECOVERY), \
+ S(PORT_RESET), \
+ S(PORT_RESET_WAIT_OFF)
+
+#define GENERATE_TCPM_ENUM(e) e
+#define GENERATE_TCPM_STRING(s) #s
+#define TCPM_POLL_EVENT_TIME_OUT 2000
+
+enum tcpm_state {
+ FOREACH_TCPM_STATE(GENERATE_TCPM_ENUM)
+};
+
+enum pd_msg_request {
+ PD_MSG_NONE = 0,
+ PD_MSG_CTRL_REJECT,
+ PD_MSG_CTRL_WAIT,
+ PD_MSG_CTRL_NOT_SUPP,
+ PD_MSG_DATA_SINK_CAP,
+ PD_MSG_DATA_SOURCE_CAP,
+};
+
+struct tcpm_port {
+ enum typec_port_type typec_type;
+ int typec_prefer_role;
+
+ enum typec_role vconn_role;
+ enum typec_role pwr_role;
+ enum typec_data_role data_role;
+
+ struct typec_partner *partner;
+
+ enum typec_cc_status cc_req;
+ enum typec_cc_status cc1;
+ enum typec_cc_status cc2;
+ enum typec_cc_polarity polarity;
+
+ bool attached;
+ bool connected;
+ int poll_event_cnt;
+ enum typec_port_type port_type;
+
+ /*
+ * Set to true when vbus is greater than VSAFE5V min.
+ * Set to false when vbus falls below vSinkDisconnect max threshold.
+ */
+ bool vbus_present;
+
+ /*
+ * Set to true when vbus is less than VSAFE0V max.
+ * Set to false when vbus is greater than VSAFE0V max.
+ */
+ bool vbus_vsafe0v;
+
+ bool vbus_never_low;
+ bool vbus_source;
+ bool vbus_charge;
+
+ int try_role;
+
+ enum pd_msg_request queued_message;
+
+ enum tcpm_state enter_state;
+ enum tcpm_state prev_state;
+ enum tcpm_state state;
+ enum tcpm_state delayed_state;
+ unsigned long delay_ms;
+
+ bool state_machine_running;
+
+ bool tx_complete;
+ enum tcpm_transmit_status tx_status;
+
+ unsigned int negotiated_rev;
+ unsigned int message_id;
+ unsigned int caps_count;
+ unsigned int hard_reset_count;
+ bool pd_capable;
+ bool explicit_contract;
+ unsigned int rx_msgid;
+
+ /* Partner capabilities/requests */
+ u32 sink_request;
+ u32 source_caps[PDO_MAX_OBJECTS];
+ unsigned int nr_source_caps;
+ u32 sink_caps[PDO_MAX_OBJECTS];
+ unsigned int nr_sink_caps;
+
+ /*
+ * whether to wait for the Type-C device to send the DR_SWAP Message flag
+ * For Type-C device with Dual-Role Power and Dual-Role Data, the port side
+ * is used as sink + ufp, then the tcpm framework needs to wait for Type-C
+ * device to initiate DR_swap Message.
+ */
+ bool wait_dr_swap_message;
+
+ /* Local capabilities */
+ u32 src_pdo[PDO_MAX_OBJECTS];
+ unsigned int nr_src_pdo;
+ u32 snk_pdo[PDO_MAX_OBJECTS];
+ unsigned int nr_snk_pdo;
+
+ unsigned int operating_snk_mw;
+ bool update_sink_caps;
+
+ /* Requested current / voltage to the port partner */
+ u32 req_current_limit;
+ u32 req_supply_voltage;
+ /* Actual current / voltage limit of the local port */
+ u32 current_limit;
+ u32 supply_voltage;
+
+ /* port belongs to a self powered device */
+ bool self_powered;
+
+ unsigned long delay_target;
+};
+
+extern const char * const tcpm_states[];
+
+int tcpm_post_probe(struct udevice *dev);
+
+#endif
diff --git a/drivers/usb/tcpm/tcpm-uclass.c b/drivers/usb/tcpm/tcpm-uclass.c
new file mode 100644
index 0000000..d4fe260
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm-uclass.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Collabora Ltd.
+ *
+ * USB Power Delivery protocol stack.
+ */
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <usb/tcpm.h>
+#include "tcpm-internal.h"
+
+int tcpm_get_voltage(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->supply_voltage;
+}
+
+int tcpm_get_current(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->current_limit;
+}
+
+enum typec_orientation tcpm_get_orientation(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ switch (port->polarity) {
+ case TYPEC_POLARITY_CC1:
+ return TYPEC_ORIENTATION_NORMAL;
+ case TYPEC_POLARITY_CC2:
+ return TYPEC_ORIENTATION_REVERSE;
+ default:
+ return TYPEC_ORIENTATION_NONE;
+ }
+}
+
+const char *tcpm_get_state(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return tcpm_states[port->state];
+}
+
+int tcpm_get_pd_rev(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->negotiated_rev;
+}
+
+enum typec_role tcpm_get_pwr_role(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->pwr_role;
+}
+
+enum typec_data_role tcpm_get_data_role(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->data_role;
+}
+
+bool tcpm_is_connected(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return port->connected;
+}
+
+int tcpm_get(int index, struct udevice **devp)
+{
+ return uclass_get_device(UCLASS_TCPM, index, devp);
+}
+
+static int tcpm_post_bind(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ const char *cap_str;
+ ofnode node;
+ int ret;
+
+ /*
+ * USB Power Delivery (USB PD) specification requires, that communication
+ * with a sink happens within roughly 5 seconds. Otherwise the source
+ * might assume that the sink does not support USB PD. Starting to do
+ * USB PD communication after that results in a hard reset, which briefly
+ * removes any power from the USB-C port.
+ *
+ * On systems with alternative power supplies this is not an issue, but
+ * systems, which get soleley powered through their USB-C port will end
+ * up losing their power supply and doing a board level reset. The hard
+ * reset will also restart the 5 second timeout. That means a operating
+ * system initializing USB PD will put the system into a boot loop when
+ * it takes more than 5 seconds from cold boot to the operating system
+ * starting to transmit USB PD messages.
+ *
+ * The issue can be avoided by doing the initial USB PD communication
+ * in U-Boot. The operating system can then re-negotiate by doing a
+ * soft reset, which does not trigger removal of the supply voltage.
+ *
+ * Since the TCPM state machine is quite complex and depending on the
+ * remote side can take quite some time to finish, this tries to limit
+ * the automatic probing to systems probably relying on power being
+ * provided by the USB-C port(s):
+ *
+ * 1. self-powered devices won't reset when the USB-C port looses power
+ * 2. if the power is allowed to go into anything else than sink mode
+ * it is not the only power source
+ */
+ ret = drvops->get_connector_node(dev, &node);
+ if (ret)
+ return ret;
+
+ if (ofnode_read_bool(node, "self-powered"))
+ return 0;
+
+ cap_str = ofnode_read_string(node, "power-role");
+ if (!cap_str)
+ return -EINVAL;
+
+ if (strcmp("sink", cap_str))
+ return 0;
+
+ /* Do not auto-probe PD controller when PD is disabled */
+ if (ofnode_read_bool(node, "pd-disable"))
+ return 0;
+
+ dev_info(dev, "probing Type-C port manager...");
+
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+ return 0;
+}
+
+UCLASS_DRIVER(tcpm) = {
+ .id = UCLASS_TCPM,
+ .name = "tcpm",
+ .per_device_plat_auto = sizeof(struct tcpm_port),
+ .post_bind = tcpm_post_bind,
+ .post_probe = tcpm_post_probe,
+};
diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c
new file mode 100644
index 0000000..0aee57c
--- /dev/null
+++ b/drivers/usb/tcpm/tcpm.c
@@ -0,0 +1,2288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2017 Google, Inc
+ *
+ * USB Power Delivery protocol stack.
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/devres.h>
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <time.h>
+#include <usb/tcpm.h>
+#include "tcpm-internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char * const tcpm_states[] = {
+ FOREACH_TCPM_STATE(GENERATE_TCPM_STRING)
+};
+
+const char * const typec_pd_rev_name[] = {
+ [PD_REV10] = "rev1",
+ [PD_REV20] = "rev2",
+ [PD_REV30] = "rev3",
+};
+
+const char * const typec_role_name[] = {
+ [TYPEC_SINK] = "sink",
+ [TYPEC_SOURCE] = "source",
+};
+
+const char * const typec_data_role_name[] = {
+ [TYPEC_DEVICE] = "device",
+ [TYPEC_HOST] = "host",
+};
+
+const char * const typec_orientation_name[] = {
+ [TYPEC_ORIENTATION_NONE] = "none",
+ [TYPEC_ORIENTATION_NORMAL] = "normal",
+ [TYPEC_ORIENTATION_REVERSE] = "reverse",
+};
+
+const char * const typec_cc_status_name[] = {
+ [TYPEC_CC_OPEN] = "open",
+ [TYPEC_CC_RA] = "ra",
+ [TYPEC_CC_RD] = "rd",
+ [TYPEC_CC_RP_DEF] = "rp-def",
+ [TYPEC_CC_RP_1_5] = "rp-1.5",
+ [TYPEC_CC_RP_3_0] = "rp-3.0",
+};
+
+static inline bool tcpm_cc_is_sink(enum typec_cc_status cc)
+{
+ return cc == TYPEC_CC_RP_DEF ||
+ cc == TYPEC_CC_RP_1_5 ||
+ cc == TYPEC_CC_RP_3_0;
+}
+
+static inline bool tcpm_port_is_sink(struct tcpm_port *port)
+{
+ bool cc1_is_snk = tcpm_cc_is_sink(port->cc1);
+ bool cc2_is_snk = tcpm_cc_is_sink(port->cc2);
+
+ return (cc1_is_snk && !cc2_is_snk) ||
+ (cc2_is_snk && !cc1_is_snk);
+}
+
+static inline bool tcpm_cc_is_source(enum typec_cc_status cc)
+{
+ return cc == TYPEC_CC_RD;
+}
+
+static inline bool tcpm_port_is_source(struct tcpm_port *port)
+{
+ bool cc1_is_src = tcpm_cc_is_source(port->cc1);
+ bool cc2_is_src = tcpm_cc_is_source(port->cc2);
+
+ return (cc1_is_src && !cc2_is_src) ||
+ (cc2_is_src && !cc1_is_src);
+}
+
+static inline bool tcpm_try_src(struct tcpm_port *port)
+{
+ return port->try_role == TYPEC_SOURCE &&
+ port->port_type == TYPEC_PORT_DRP;
+}
+
+static inline void tcpm_reset_event_cnt(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ port->poll_event_cnt = 0;
+}
+
+static enum tcpm_state tcpm_default_state(struct tcpm_port *port)
+{
+ if (port->port_type == TYPEC_PORT_DRP) {
+ if (port->try_role == TYPEC_SINK)
+ return SNK_UNATTACHED;
+ else if (port->try_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ } else if (port->port_type == TYPEC_PORT_SNK) {
+ return SNK_UNATTACHED;
+ }
+ return SRC_UNATTACHED;
+}
+
+static bool tcpm_port_is_disconnected(struct tcpm_port *port)
+{
+ return (!port->attached && port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN) ||
+ (port->attached && ((port->polarity == TYPEC_POLARITY_CC1 &&
+ port->cc1 == TYPEC_CC_OPEN) ||
+ (port->polarity == TYPEC_POLARITY_CC2 &&
+ port->cc2 == TYPEC_CC_OPEN)));
+}
+
+static void tcpm_set_cc(struct udevice *dev, enum typec_cc_status cc)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ dev_dbg(dev, "TCPM: set cc = %d\n", cc);
+ port->cc_req = cc;
+ drvops->set_cc(dev, cc);
+}
+
+/*
+ * Determine RP value to set based on maximum current supported
+ * by a port if configured as source.
+ * Returns CC value to report to link partner.
+ */
+static enum typec_cc_status tcpm_rp_cc(struct tcpm_port *port)
+{
+ const u32 *src_pdo = port->src_pdo;
+ int nr_pdo = port->nr_src_pdo;
+ int i;
+
+ /*
+ * Search for first entry with matching voltage.
+ * It should report the maximum supported current.
+ */
+ for (i = 0; i < nr_pdo; i++) {
+ const u32 pdo = src_pdo[i];
+
+ if (pdo_type(pdo) == PDO_TYPE_FIXED &&
+ pdo_fixed_voltage(pdo) == 5000) {
+ unsigned int curr = pdo_max_current(pdo);
+
+ if (curr >= 3000)
+ return TYPEC_CC_RP_3_0;
+ else if (curr >= 1500)
+ return TYPEC_CC_RP_1_5;
+ return TYPEC_CC_RP_DEF;
+ }
+ }
+
+ return TYPEC_CC_RP_DEF;
+}
+
+static void tcpm_check_and_run_delayed_work(struct udevice *dev);
+
+static bool tcpm_transmit_helper(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ drvops->poll_event(dev);
+ udelay(500);
+ tcpm_check_and_run_delayed_work(dev);
+ return port->tx_complete;
+}
+
+static int tcpm_pd_transmit(struct udevice *dev,
+ enum tcpm_transmit_type type,
+ const struct pd_message *msg)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ u32 timeout_us = PD_T_TCPC_TX_TIMEOUT * 1000;
+ bool tx_complete;
+ int ret;
+
+ if (msg)
+ dev_dbg(dev, "TCPM: PD TX, header: %#x\n",
+ le16_to_cpu(msg->header));
+ else
+ dev_dbg(dev, "TCPM: PD TX, type: %#x\n", type);
+
+ port->tx_complete = false;
+ ret = drvops->pd_transmit(dev, type, msg, port->negotiated_rev);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * At this point we basically need to block until the TCPM controller
+ * returns successful transmission. Since this is usually done using
+ * the generic interrupt status bits, we poll for any events. That
+ * will clear the interrupt status, so we also need to process any
+ * of the incoming events. This means we will do more processing and
+ * thus let's give everything a bit more time.
+ */
+ timeout_us *= 5;
+ ret = read_poll_timeout(tcpm_transmit_helper, tx_complete,
+ !tx_complete, false, timeout_us, dev);
+ if (ret < 0) {
+ dev_err(dev, "TCPM: PD transmit data failed: %d\n", ret);
+ return ret;
+ }
+
+ switch (port->tx_status) {
+ case TCPC_TX_SUCCESS:
+ port->message_id = (port->message_id + 1) & PD_HEADER_ID_MASK;
+ break;
+ case TCPC_TX_DISCARDED:
+ ret = -EAGAIN;
+ break;
+ case TCPC_TX_FAILED:
+ default:
+ ret = -EIO;
+ break;
+ }
+
+ return ret;
+}
+
+void tcpm_pd_transmit_complete(struct udevice *dev,
+ enum tcpm_transmit_status status)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ dev_dbg(dev, "TCPM: PD TX complete, status: %u\n", status);
+ tcpm_reset_event_cnt(dev);
+ port->tx_status = status;
+ port->tx_complete = true;
+}
+
+static int tcpm_set_polarity(struct udevice *dev,
+ enum typec_cc_polarity polarity)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ int ret;
+
+ dev_dbg(dev, "TCPM: set polarity = %d\n", polarity);
+
+ if (drvops->set_polarity) {
+ ret = drvops->set_polarity(dev, polarity);
+ if (ret < 0)
+ return ret;
+ }
+
+ port->polarity = polarity;
+
+ return 0;
+}
+
+static int tcpm_set_vconn(struct udevice *dev, bool enable)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ dev_dbg(dev, "TCPM: set vconn = %d\n", enable);
+
+ ret = drvops->set_vconn(dev, enable);
+ if (!ret)
+ port->vconn_role = enable ? TYPEC_SOURCE : TYPEC_SINK;
+
+ return ret;
+}
+
+static inline u32 tcpm_get_current_limit(struct tcpm_port *port)
+{
+ switch (port->polarity ? port->cc2 : port->cc1) {
+ case TYPEC_CC_RP_1_5:
+ return 1500;
+ case TYPEC_CC_RP_3_0:
+ return 3000;
+ case TYPEC_CC_RP_DEF:
+ default:
+ return 0;
+ }
+}
+
+static int tcpm_set_current_limit(struct udevice *dev, u32 max_ma, u32 mv)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret = -EOPNOTSUPP;
+
+ dev_info(dev, "TCPM: set voltage limit = %u mV\n", mv);
+ dev_info(dev, "TCPM: set current limit = %u mA\n", max_ma);
+
+ port->supply_voltage = mv;
+ port->current_limit = max_ma;
+
+ return ret;
+}
+
+static int tcpm_set_attached_state(struct udevice *dev, bool attached)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ return drvops->set_roles(dev, attached, port->pwr_role,
+ port->data_role);
+}
+
+static int tcpm_set_roles(struct udevice *dev, bool attached,
+ enum typec_role role, enum typec_data_role data)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ ret = drvops->set_roles(dev, attached, role, data);
+ if (ret < 0)
+ return ret;
+
+ port->pwr_role = role;
+ port->data_role = data;
+
+ return 0;
+}
+
+static int tcpm_pd_send_source_caps(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ struct pd_message msg;
+ int i;
+
+ memset(&msg, 0, sizeof(msg));
+
+ if (!port->nr_src_pdo) {
+ /* No source capabilities defined, sink only */
+ msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+ } else {
+ msg.header = PD_HEADER_LE(PD_DATA_SOURCE_CAP,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id,
+ port->nr_src_pdo);
+ }
+
+ for (i = 0; i < port->nr_src_pdo; i++)
+ msg.payload[i] = cpu_to_le32(port->src_pdo[i]);
+
+ return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_pd_send_sink_caps(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ struct pd_message msg;
+ unsigned int i;
+
+ memset(&msg, 0, sizeof(msg));
+
+ if (!port->nr_snk_pdo) {
+ /* No sink capabilities defined, source only */
+ msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+ } else {
+ msg.header = PD_HEADER_LE(PD_DATA_SINK_CAP,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id,
+ port->nr_snk_pdo);
+ }
+
+ for (i = 0; i < port->nr_snk_pdo; i++)
+ msg.payload[i] = cpu_to_le32(port->snk_pdo[i]);
+
+ return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static void tcpm_state_machine(struct udevice *dev);
+
+static inline void tcpm_timer_uninit(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ port->delay_target = 0;
+}
+
+static void tcpm_timer_init(struct udevice *dev, uint32_t ms)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ unsigned long time_us = ms * 1000;
+
+ port->delay_target = timer_get_us() + time_us;
+}
+
+static void tcpm_check_and_run_delayed_work(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ /* no delayed state changes scheduled */
+ if (port->delay_target == 0)
+ return;
+
+ /* it's not yet time */
+ if (timer_get_us() < port->delay_target)
+ return;
+
+ tcpm_timer_uninit(dev);
+ tcpm_state_machine(dev);
+}
+
+static void mod_tcpm_delayed_work(struct udevice *dev, unsigned int delay_ms)
+{
+ if (delay_ms) {
+ tcpm_timer_init(dev, delay_ms);
+ } else {
+ tcpm_timer_uninit(dev);
+ tcpm_state_machine(dev);
+ }
+}
+
+static void tcpm_set_state(struct udevice *dev, enum tcpm_state state,
+ unsigned int delay_ms)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ if (delay_ms) {
+ dev_dbg(dev, "TCPM: pending state change %s -> %s @ %u ms [%s]\n",
+ tcpm_states[port->state], tcpm_states[state], delay_ms,
+ typec_pd_rev_name[port->negotiated_rev]);
+ port->delayed_state = state;
+ mod_tcpm_delayed_work(dev, delay_ms);
+ port->delay_ms = delay_ms;
+ } else {
+ dev_dbg(dev, "TCPM: state change %s -> %s\n",
+ tcpm_states[port->state], tcpm_states[state]);
+ port->delayed_state = INVALID_STATE;
+ port->prev_state = port->state;
+ port->state = state;
+ /*
+ * Don't re-queue the state machine work item if we're currently
+ * in the state machine and we're immediately changing states.
+ * tcpm_state_machine_work() will continue running the state
+ * machine.
+ */
+ if (!port->state_machine_running)
+ mod_tcpm_delayed_work(dev, 0);
+ }
+}
+
+static void tcpm_set_state_cond(struct udevice *dev, enum tcpm_state state,
+ unsigned int delay_ms)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ if (port->enter_state == port->state)
+ tcpm_set_state(dev, state, delay_ms);
+ else
+ dev_dbg(dev, "TCPM: skipped %sstate change %s -> %s [%u ms], context state %s [%s]\n",
+ delay_ms ? "delayed " : "",
+ tcpm_states[port->state], tcpm_states[state],
+ delay_ms, tcpm_states[port->enter_state],
+ typec_pd_rev_name[port->negotiated_rev]);
+}
+
+static void tcpm_queue_message(struct udevice *dev,
+ enum pd_msg_request message)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ port->queued_message = message;
+ mod_tcpm_delayed_work(dev, 0);
+}
+
+enum pdo_err {
+ PDO_NO_ERR,
+ PDO_ERR_NO_VSAFE5V,
+ PDO_ERR_VSAFE5V_NOT_FIRST,
+ PDO_ERR_PDO_TYPE_NOT_IN_ORDER,
+ PDO_ERR_FIXED_NOT_SORTED,
+ PDO_ERR_VARIABLE_BATT_NOT_SORTED,
+ PDO_ERR_DUPE_PDO,
+ PDO_ERR_PPS_APDO_NOT_SORTED,
+ PDO_ERR_DUPE_PPS_APDO,
+};
+
+static const char * const pdo_err_msg[] = {
+ [PDO_ERR_NO_VSAFE5V] =
+ " err: source/sink caps should at least have vSafe5V",
+ [PDO_ERR_VSAFE5V_NOT_FIRST] =
+ " err: vSafe5V Fixed Supply Object Shall always be the first object",
+ [PDO_ERR_PDO_TYPE_NOT_IN_ORDER] =
+ " err: PDOs should be in the following order: Fixed; Battery; Variable",
+ [PDO_ERR_FIXED_NOT_SORTED] =
+ " err: Fixed supply pdos should be in increasing order of their fixed voltage",
+ [PDO_ERR_VARIABLE_BATT_NOT_SORTED] =
+ " err: Variable/Battery supply pdos should be in increasing order of their minimum voltage",
+ [PDO_ERR_DUPE_PDO] =
+ " err: Variable/Batt supply pdos cannot have same min/max voltage",
+ [PDO_ERR_PPS_APDO_NOT_SORTED] =
+ " err: Programmable power supply apdos should be in increasing order of their maximum voltage",
+ [PDO_ERR_DUPE_PPS_APDO] =
+ " err: Programmable power supply apdos cannot have same min/max voltage and max current",
+};
+
+static enum pdo_err tcpm_caps_err(struct udevice *dev, const u32 *pdo,
+ unsigned int nr_pdo)
+{
+ unsigned int i;
+
+ /* Should at least contain vSafe5v */
+ if (nr_pdo < 1)
+ return PDO_ERR_NO_VSAFE5V;
+
+ /* The vSafe5V Fixed Supply Object Shall always be the first object */
+ if (pdo_type(pdo[0]) != PDO_TYPE_FIXED ||
+ pdo_fixed_voltage(pdo[0]) != VSAFE5V)
+ return PDO_ERR_VSAFE5V_NOT_FIRST;
+
+ for (i = 1; i < nr_pdo; i++) {
+ if (pdo_type(pdo[i]) < pdo_type(pdo[i - 1])) {
+ return PDO_ERR_PDO_TYPE_NOT_IN_ORDER;
+ } else if (pdo_type(pdo[i]) == pdo_type(pdo[i - 1])) {
+ enum pd_pdo_type type = pdo_type(pdo[i]);
+
+ switch (type) {
+ /*
+ * The remaining Fixed Supply Objects, if
+ * present, shall be sent in voltage order;
+ * lowest to highest.
+ */
+ case PDO_TYPE_FIXED:
+ if (pdo_fixed_voltage(pdo[i]) <=
+ pdo_fixed_voltage(pdo[i - 1]))
+ return PDO_ERR_FIXED_NOT_SORTED;
+ break;
+ /*
+ * The Battery Supply Objects and Variable
+ * supply, if present shall be sent in Minimum
+ * Voltage order; lowest to highest.
+ */
+ case PDO_TYPE_VAR:
+ case PDO_TYPE_BATT:
+ if (pdo_min_voltage(pdo[i]) <
+ pdo_min_voltage(pdo[i - 1]))
+ return PDO_ERR_VARIABLE_BATT_NOT_SORTED;
+ else if ((pdo_min_voltage(pdo[i]) ==
+ pdo_min_voltage(pdo[i - 1])) &&
+ (pdo_max_voltage(pdo[i]) ==
+ pdo_max_voltage(pdo[i - 1])))
+ return PDO_ERR_DUPE_PDO;
+ break;
+ /*
+ * The Programmable Power Supply APDOs, if present,
+ * shall be sent in Maximum Voltage order;
+ * lowest to highest.
+ */
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo[i]) != APDO_TYPE_PPS)
+ break;
+
+ if (pdo_pps_apdo_max_voltage(pdo[i]) <
+ pdo_pps_apdo_max_voltage(pdo[i - 1]))
+ return PDO_ERR_PPS_APDO_NOT_SORTED;
+ else if (pdo_pps_apdo_min_voltage(pdo[i]) ==
+ pdo_pps_apdo_min_voltage(pdo[i - 1]) &&
+ pdo_pps_apdo_max_voltage(pdo[i]) ==
+ pdo_pps_apdo_max_voltage(pdo[i - 1]) &&
+ pdo_pps_apdo_max_current(pdo[i]) ==
+ pdo_pps_apdo_max_current(pdo[i - 1]))
+ return PDO_ERR_DUPE_PPS_APDO;
+ break;
+ default:
+ dev_err(dev, "TCPM: Unknown pdo type\n");
+ }
+ }
+ }
+
+ return PDO_NO_ERR;
+}
+
+static int tcpm_validate_caps(struct udevice *dev, const u32 *pdo,
+ unsigned int nr_pdo)
+{
+ enum pdo_err err_index = tcpm_caps_err(dev, pdo, nr_pdo);
+
+ if (err_index != PDO_NO_ERR) {
+ dev_err(dev, "TCPM:%s\n", pdo_err_msg[err_index]);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * PD (data, control) command handling functions
+ */
+static inline enum tcpm_state ready_state(struct tcpm_port *port)
+{
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_READY;
+ else
+ return SNK_READY;
+}
+
+static void tcpm_pd_data_request(struct udevice *dev,
+ const struct pd_message *msg)
+{
+ enum pd_data_msg_type type = pd_header_type_le(msg->header);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ unsigned int cnt = pd_header_cnt_le(msg->header);
+ unsigned int rev = pd_header_rev_le(msg->header);
+ unsigned int i;
+
+ switch (type) {
+ case PD_DATA_SOURCE_CAP:
+ for (i = 0; i < cnt; i++)
+ port->source_caps[i] = le32_to_cpu(msg->payload[i]);
+
+ port->nr_source_caps = cnt;
+
+ tcpm_validate_caps(dev, port->source_caps,
+ port->nr_source_caps);
+
+ /*
+ * Adjust revision in subsequent message headers, as required,
+ * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+ * support Rev 1.0 so just do nothing in that scenario.
+ */
+ if (rev == PD_REV10)
+ break;
+
+ if (rev < PD_MAX_REV)
+ port->negotiated_rev = rev;
+
+ if ((pdo_type(port->source_caps[0]) == PDO_TYPE_FIXED) &&
+ (port->source_caps[0] & PDO_FIXED_DUAL_ROLE) &&
+ (port->source_caps[0] & PDO_FIXED_DATA_SWAP)) {
+ /* Dual role power and data, eg: self-powered Type-C */
+ port->wait_dr_swap_message = true;
+ } else {
+ /* Non-Dual role power, eg: adapter */
+ port->wait_dr_swap_message = false;
+ }
+
+ /*
+ * This message may be received even if VBUS is not
+ * present. This is quite unexpected; see USB PD
+ * specification, sections 8.3.3.6.3.1 and 8.3.3.6.3.2.
+ * However, at the same time, we must be ready to
+ * receive this message and respond to it 15ms after
+ * receiving PS_RDY during power swap operations, no matter
+ * if VBUS is available or not (USB PD specification,
+ * section 6.5.9.2).
+ * So we need to accept the message either way,
+ * but be prepared to keep waiting for VBUS after it was
+ * handled.
+ */
+ tcpm_set_state(dev, SNK_NEGOTIATE_CAPABILITIES, 0);
+ break;
+ case PD_DATA_REQUEST:
+ /*
+ * Adjust revision in subsequent message headers, as required,
+ * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+ * support Rev 1.0 so just reject in that scenario.
+ */
+ if (rev == PD_REV10) {
+ tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+ break;
+ }
+
+ if (rev < PD_MAX_REV)
+ port->negotiated_rev = rev;
+
+ port->sink_request = le32_to_cpu(msg->payload[0]);
+
+ tcpm_set_state(dev, SRC_NEGOTIATE_CAPABILITIES, 0);
+ break;
+ case PD_DATA_SINK_CAP:
+ /* We don't do anything with this at the moment... */
+ for (i = 0; i < cnt; i++)
+ port->sink_caps[i] = le32_to_cpu(msg->payload[i]);
+
+ port->nr_sink_caps = cnt;
+ break;
+ default:
+ break;
+ }
+}
+
+static void tcpm_pd_ctrl_request(struct udevice *dev,
+ const struct pd_message *msg)
+{
+ enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum tcpm_state next_state;
+
+ switch (type) {
+ case PD_CTRL_GOOD_CRC:
+ case PD_CTRL_PING:
+ break;
+ case PD_CTRL_GET_SOURCE_CAP:
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_queue_message(dev, PD_MSG_DATA_SOURCE_CAP);
+ break;
+ default:
+ tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ break;
+ case PD_CTRL_GET_SINK_CAP:
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_queue_message(dev, PD_MSG_DATA_SINK_CAP);
+ break;
+ default:
+ tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ break;
+ case PD_CTRL_GOTO_MIN:
+ break;
+ case PD_CTRL_PS_RDY:
+ switch (port->state) {
+ case SNK_TRANSITION_SINK:
+ if (port->vbus_present) {
+ tcpm_set_current_limit(dev,
+ port->req_current_limit,
+ port->req_supply_voltage);
+ port->explicit_contract = true;
+ tcpm_set_state(dev, SNK_READY, 0);
+ } else {
+ /*
+ * Seen after power swap. Keep waiting for VBUS
+ * in a transitional state.
+ */
+ tcpm_set_state(dev,
+ SNK_TRANSITION_SINK_VBUS, 0);
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_REJECT:
+ case PD_CTRL_WAIT:
+ case PD_CTRL_NOT_SUPP:
+ switch (port->state) {
+ case SNK_NEGOTIATE_CAPABILITIES:
+ /* USB PD specification, Figure 8-43 */
+ if (port->explicit_contract)
+ next_state = SNK_READY;
+ else
+ next_state = SNK_WAIT_CAPABILITIES;
+
+ tcpm_set_state(dev, next_state, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_ACCEPT:
+ switch (port->state) {
+ case SNK_NEGOTIATE_CAPABILITIES:
+ tcpm_set_state(dev, SNK_TRANSITION_SINK, 0);
+ break;
+ case SOFT_RESET_SEND:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ if (port->pwr_role == TYPEC_SOURCE)
+ next_state = SRC_SEND_CAPABILITIES;
+ else
+ next_state = SNK_WAIT_CAPABILITIES;
+ tcpm_set_state(dev, next_state, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_SOFT_RESET:
+ tcpm_set_state(dev, SOFT_RESET, 0);
+ break;
+ case PD_CTRL_DR_SWAP:
+ if (port->port_type != TYPEC_PORT_DRP) {
+ tcpm_queue_message(dev, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ /*
+ * 6.3.9: If an alternate mode is active, a request to swap
+ * alternate modes shall trigger a port reset.
+ */
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_set_state(dev, DR_SWAP_ACCEPT, 0);
+ break;
+ default:
+ tcpm_queue_message(dev, PD_MSG_CTRL_WAIT);
+ break;
+ }
+ break;
+ case PD_CTRL_PR_SWAP:
+ case PD_CTRL_VCONN_SWAP:
+ case PD_CTRL_GET_SOURCE_CAP_EXT:
+ case PD_CTRL_GET_STATUS:
+ case PD_CTRL_FR_SWAP:
+ case PD_CTRL_GET_PPS_STATUS:
+ case PD_CTRL_GET_COUNTRY_CODES:
+ /* Currently not supported */
+ dev_err(dev, "TCPM: Currently not supported type %#x\n", type);
+ tcpm_queue_message(dev, PD_MSG_CTRL_NOT_SUPP);
+ break;
+ default:
+ dev_err(dev, "TCPM: Unrecognized ctrl message type %#x\n", type);
+ break;
+ }
+}
+
+static void tcpm_pd_rx_handler(struct udevice *dev,
+ const struct pd_message *msg)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ unsigned int cnt = pd_header_cnt_le(msg->header);
+ bool remote_is_host, local_is_host;
+
+ dev_dbg(dev, "TCPM: PD RX, header: %#x [%d]\n",
+ le16_to_cpu(msg->header), port->attached);
+
+ if (port->attached) {
+ enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+ unsigned int msgid = pd_header_msgid_le(msg->header);
+
+ /*
+ * USB PD standard, 6.6.1.2:
+ * "... if MessageID value in a received Message is the
+ * same as the stored value, the receiver shall return a
+ * GoodCRC Message with that MessageID value and drop
+ * the Message (this is a retry of an already received
+ * Message). Note: this shall not apply to the Soft_Reset
+ * Message which always has a MessageID value of zero."
+ */
+ if (msgid == port->rx_msgid && type != PD_CTRL_SOFT_RESET)
+ return;
+ port->rx_msgid = msgid;
+
+ /*
+ * If both ends believe to be DFP/host, we have a data role
+ * mismatch.
+ */
+ remote_is_host = !!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE);
+ local_is_host = port->data_role == TYPEC_HOST;
+ if (remote_is_host == local_is_host) {
+ dev_err(dev, "TCPM: data role mismatch, initiating error recovery\n");
+ tcpm_set_state(dev, ERROR_RECOVERY, 0);
+ } else {
+ if (cnt)
+ tcpm_pd_data_request(dev, msg);
+ else
+ tcpm_pd_ctrl_request(dev, msg);
+ }
+ }
+}
+
+void tcpm_pd_receive(struct udevice *dev, const struct pd_message *msg)
+{
+ tcpm_reset_event_cnt(dev);
+ tcpm_pd_rx_handler(dev, msg);
+}
+
+static int tcpm_pd_send_control(struct udevice *dev,
+ enum pd_ctrl_msg_type type)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ struct pd_message msg;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.header = PD_HEADER_LE(type, port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+
+ return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+/*
+ * Send queued message without affecting state.
+ * Return true if state machine should go back to sleep,
+ * false otherwise.
+ */
+static bool tcpm_send_queued_message(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum pd_msg_request queued_message;
+ int max_messages = 100;
+
+ do {
+ queued_message = port->queued_message;
+ port->queued_message = PD_MSG_NONE;
+ max_messages--;
+
+ switch (queued_message) {
+ case PD_MSG_CTRL_WAIT:
+ tcpm_pd_send_control(dev, PD_CTRL_WAIT);
+ break;
+ case PD_MSG_CTRL_REJECT:
+ tcpm_pd_send_control(dev, PD_CTRL_REJECT);
+ break;
+ case PD_MSG_CTRL_NOT_SUPP:
+ tcpm_pd_send_control(dev, PD_CTRL_NOT_SUPP);
+ break;
+ case PD_MSG_DATA_SINK_CAP:
+ tcpm_pd_send_sink_caps(dev);
+ break;
+ case PD_MSG_DATA_SOURCE_CAP:
+ tcpm_pd_send_source_caps(dev);
+ break;
+ default:
+ break;
+ }
+ } while (max_messages > 0 && port->queued_message != PD_MSG_NONE);
+
+ if (!max_messages)
+ dev_err(dev, "Aborted sending of too many queued messages\n");
+
+ return false;
+}
+
+static int tcpm_pd_check_request(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ u32 pdo, rdo = port->sink_request;
+ unsigned int max, op, pdo_max, index;
+ enum pd_pdo_type type;
+
+ index = rdo_index(rdo);
+ if (!index || index > port->nr_src_pdo)
+ return -EINVAL;
+
+ pdo = port->src_pdo[index - 1];
+ type = pdo_type(pdo);
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ case PDO_TYPE_VAR:
+ max = rdo_max_current(rdo);
+ op = rdo_op_current(rdo);
+ pdo_max = pdo_max_current(pdo);
+
+ if (op > pdo_max)
+ return -EINVAL;
+ if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+ return -EINVAL;
+
+ if (type == PDO_TYPE_FIXED)
+ dev_dbg(dev, "TCPM: Requested %u mV, %u mA for %u / %u mA\n",
+ pdo_fixed_voltage(pdo), pdo_max, op, max);
+ else
+ dev_dbg(dev, "TCPM: Requested %u -> %u mV, %u mA for %u / %u mA\n",
+ pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+ pdo_max, op, max);
+ break;
+ case PDO_TYPE_BATT:
+ max = rdo_max_power(rdo);
+ op = rdo_op_power(rdo);
+ pdo_max = pdo_max_power(pdo);
+
+ if (op > pdo_max)
+ return -EINVAL;
+ if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+ return -EINVAL;
+ dev_info(dev, "TCPM: Requested %u -> %u mV, %u mW for %u / %u mW\n",
+ pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+ pdo_max, op, max);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#define min_power(x, y) min(pdo_max_power(x), pdo_max_power(y))
+#define min_current(x, y) min(pdo_max_current(x), pdo_max_current(y))
+
+static int tcpm_pd_select_pdo(struct udevice *dev, int *sink_pdo,
+ int *src_pdo)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ unsigned int i, j, max_src_mv = 0, min_src_mv = 0, max_mw = 0,
+ max_mv = 0, src_mw = 0, src_ma = 0, max_snk_mv = 0,
+ min_snk_mv = 0;
+ int ret = -EINVAL;
+
+ /*
+ * Select the source PDO providing the most power which has a
+ * matchig sink cap.
+ */
+ for (i = 0; i < port->nr_source_caps; i++) {
+ u32 pdo = port->source_caps[i];
+ enum pd_pdo_type type = pdo_type(pdo);
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ max_src_mv = pdo_fixed_voltage(pdo);
+ min_src_mv = max_src_mv;
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ max_src_mv = pdo_max_voltage(pdo);
+ min_src_mv = pdo_min_voltage(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ continue;
+ default:
+ dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n");
+ continue;
+ }
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ case PDO_TYPE_VAR:
+ src_ma = pdo_max_current(pdo);
+ src_mw = src_ma * min_src_mv / 1000;
+ break;
+ case PDO_TYPE_BATT:
+ src_mw = pdo_max_power(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ continue;
+ default:
+ dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n");
+ continue;
+ }
+
+ for (j = 0; j < port->nr_snk_pdo; j++) {
+ pdo = port->snk_pdo[j];
+
+ switch (pdo_type(pdo)) {
+ case PDO_TYPE_FIXED:
+ max_snk_mv = pdo_fixed_voltage(pdo);
+ min_snk_mv = max_snk_mv;
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ max_snk_mv = pdo_max_voltage(pdo);
+ min_snk_mv = pdo_min_voltage(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ continue;
+ default:
+ dev_err(dev, "TCPM: Invalid sink PDO type, ignoring\n");
+ continue;
+ }
+
+ if (max_src_mv <= max_snk_mv && min_src_mv >= min_snk_mv) {
+ /* Prefer higher voltages if available */
+ if ((src_mw == max_mw && min_src_mv > max_mv) ||
+ src_mw > max_mw) {
+ *src_pdo = i;
+ *sink_pdo = j;
+ max_mw = src_mw;
+ max_mv = min_src_mv;
+ ret = 0;
+ }
+ }
+ }
+ }
+
+ return ret;
+}
+
+static int tcpm_pd_build_request(struct udevice *dev, u32 *rdo)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ unsigned int mv, ma, mw, flags;
+ unsigned int max_ma, max_mw;
+ enum pd_pdo_type type;
+ u32 pdo, matching_snk_pdo;
+ int src_pdo_index = 0;
+ int snk_pdo_index = 0;
+ int ret;
+
+ ret = tcpm_pd_select_pdo(dev, &snk_pdo_index, &src_pdo_index);
+ if (ret < 0)
+ return ret;
+
+ pdo = port->source_caps[src_pdo_index];
+ matching_snk_pdo = port->snk_pdo[snk_pdo_index];
+ type = pdo_type(pdo);
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ mv = pdo_fixed_voltage(pdo);
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ mv = pdo_min_voltage(pdo);
+ break;
+ default:
+ dev_err(dev, "TCPM: Invalid PDO selected!\n");
+ return -EINVAL;
+ }
+
+ /* Select maximum available current within the sink pdo's limit */
+ if (type == PDO_TYPE_BATT) {
+ mw = min_power(pdo, matching_snk_pdo);
+ ma = 1000 * mw / mv;
+ } else {
+ ma = min_current(pdo, matching_snk_pdo);
+ mw = ma * mv / 1000;
+ }
+
+ flags = RDO_USB_COMM | RDO_NO_SUSPEND;
+
+ /* Set mismatch bit if offered power is less than operating power */
+ max_ma = ma;
+ max_mw = mw;
+ if (mw < port->operating_snk_mw) {
+ flags |= RDO_CAP_MISMATCH;
+ if (type == PDO_TYPE_BATT &&
+ (pdo_max_power(matching_snk_pdo) > pdo_max_power(pdo)))
+ max_mw = pdo_max_power(matching_snk_pdo);
+ else if (pdo_max_current(matching_snk_pdo) >
+ pdo_max_current(pdo))
+ max_ma = pdo_max_current(matching_snk_pdo);
+ }
+
+ dev_dbg(dev, "TCPM: cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d\n",
+ port->cc_req, port->cc1, port->cc2, port->vbus_source,
+ port->vconn_role == TYPEC_SOURCE ? "source" : "sink",
+ port->polarity);
+
+ if (type == PDO_TYPE_BATT) {
+ *rdo = RDO_BATT(src_pdo_index + 1, mw, max_mw, flags);
+
+ dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mW%s\n",
+ src_pdo_index, mv, mw,
+ flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+ } else {
+ *rdo = RDO_FIXED(src_pdo_index + 1, ma, max_ma, flags);
+
+ dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mA%s\n",
+ src_pdo_index, mv, ma,
+ flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+ }
+
+ port->req_current_limit = ma;
+ port->req_supply_voltage = mv;
+
+ return 0;
+}
+
+static int tcpm_pd_send_request(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ struct pd_message msg;
+ int ret;
+ u32 rdo;
+
+ ret = tcpm_pd_build_request(dev, &rdo);
+ if (ret < 0)
+ return ret;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.header = PD_HEADER_LE(PD_DATA_REQUEST,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 1);
+ msg.payload[0] = cpu_to_le32(rdo);
+
+ return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_set_vbus(struct udevice *dev, bool enable)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ int ret;
+
+ if (enable && port->vbus_charge)
+ return -EINVAL;
+
+ dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n",
+ enable, port->vbus_charge);
+
+ ret = drvops->set_vbus(dev, enable, port->vbus_charge);
+ if (ret < 0)
+ return ret;
+
+ port->vbus_source = enable;
+ return 0;
+}
+
+static int tcpm_set_charge(struct udevice *dev, bool charge)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ if (charge && port->vbus_source)
+ return -EINVAL;
+
+ if (charge != port->vbus_charge) {
+ dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n",
+ port->vbus_source, charge);
+ ret = drvops->set_vbus(dev, port->vbus_source,
+ charge);
+ if (ret < 0)
+ return ret;
+ }
+ port->vbus_charge = charge;
+ return 0;
+}
+
+static bool tcpm_start_toggling(struct udevice *dev, enum typec_cc_status cc)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ if (!drvops->start_toggling)
+ return false;
+
+ dev_dbg(dev, "TCPM: Start toggling\n");
+ ret = drvops->start_toggling(dev, port->port_type, cc);
+ return ret == 0;
+}
+
+static int tcpm_init_vbus(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ ret = drvops->set_vbus(dev, false, false);
+ port->vbus_source = false;
+ port->vbus_charge = false;
+ return ret;
+}
+
+static int tcpm_init_vconn(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ ret = drvops->set_vconn(dev, false);
+ port->vconn_role = TYPEC_SINK;
+ return ret;
+}
+
+static inline void tcpm_typec_connect(struct tcpm_port *port)
+{
+ if (!port->connected)
+ port->connected = true;
+}
+
+static int tcpm_src_attach(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum typec_cc_polarity polarity =
+ port->cc2 == TYPEC_CC_RD ? TYPEC_POLARITY_CC2
+ : TYPEC_POLARITY_CC1;
+ int ret;
+
+ if (port->attached)
+ return 0;
+
+ ret = tcpm_set_polarity(dev, polarity);
+ if (ret < 0)
+ return ret;
+
+ ret = tcpm_set_roles(dev, true, TYPEC_SOURCE, TYPEC_HOST);
+ if (ret < 0)
+ return ret;
+
+ ret = drvops->set_pd_rx(dev, true);
+ if (ret < 0)
+ goto out_disable_mux;
+
+ /*
+ * USB Type-C specification, version 1.2,
+ * chapter 4.5.2.2.8.1 (Attached.SRC Requirements)
+ * Enable VCONN only if the non-RD port is set to RA.
+ */
+ if ((polarity == TYPEC_POLARITY_CC1 && port->cc2 == TYPEC_CC_RA) ||
+ (polarity == TYPEC_POLARITY_CC2 && port->cc1 == TYPEC_CC_RA)) {
+ ret = tcpm_set_vconn(dev, true);
+ if (ret < 0)
+ goto out_disable_pd;
+ }
+
+ ret = tcpm_set_vbus(dev, true);
+ if (ret < 0)
+ goto out_disable_vconn;
+
+ port->pd_capable = false;
+
+ port->partner = NULL;
+
+ port->attached = true;
+
+ return 0;
+
+out_disable_vconn:
+ tcpm_set_vconn(dev, false);
+out_disable_pd:
+ drvops->set_pd_rx(dev, false);
+out_disable_mux:
+ dev_err(dev, "TCPM: CC connected in %s as DFP\n",
+ polarity ? "CC2" : "CC1");
+ return 0;
+}
+
+static inline void tcpm_typec_disconnect(struct tcpm_port *port)
+{
+ if (port->connected) {
+ port->partner = NULL;
+ port->connected = false;
+ }
+}
+
+static void tcpm_reset_port(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ tcpm_timer_uninit(dev);
+ tcpm_typec_disconnect(port);
+ tcpm_reset_event_cnt(dev);
+ port->wait_dr_swap_message = false;
+ port->attached = false;
+ port->pd_capable = false;
+
+ /*
+ * First Rx ID should be 0; set this to a sentinel of -1 so that
+ * we can check tcpm_pd_rx_handler() if we had seen it before.
+ */
+ port->rx_msgid = -1;
+
+ drvops->set_pd_rx(dev, false);
+ tcpm_init_vbus(dev); /* also disables charging */
+ tcpm_init_vconn(dev);
+ tcpm_set_current_limit(dev, 0, 0);
+ tcpm_set_polarity(dev, TYPEC_POLARITY_CC1);
+ tcpm_set_attached_state(dev, false);
+ port->nr_sink_caps = 0;
+}
+
+static void tcpm_detach(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ if (tcpm_port_is_disconnected(port))
+ port->hard_reset_count = 0;
+
+ if (!port->attached)
+ return;
+
+ tcpm_reset_port(dev);
+}
+
+static void tcpm_src_detach(struct udevice *dev)
+{
+ tcpm_detach(dev);
+}
+
+static int tcpm_snk_attach(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ if (port->attached)
+ return 0;
+
+ ret = tcpm_set_polarity(dev, port->cc2 != TYPEC_CC_OPEN ?
+ TYPEC_POLARITY_CC2 : TYPEC_POLARITY_CC1);
+ if (ret < 0)
+ return ret;
+
+ ret = tcpm_set_roles(dev, true, TYPEC_SINK, TYPEC_DEVICE);
+ if (ret < 0)
+ return ret;
+
+ port->pd_capable = false;
+
+ port->partner = NULL;
+
+ port->attached = true;
+ dev_info(dev, "TCPM: CC connected in %s as UFP\n",
+ port->cc1 != TYPEC_CC_OPEN ? "CC1" : "CC2");
+
+ return 0;
+}
+
+static void tcpm_snk_detach(struct udevice *dev)
+{
+ tcpm_detach(dev);
+}
+
+static inline enum tcpm_state hard_reset_state(struct tcpm_port *port)
+{
+ if (port->hard_reset_count < PD_N_HARD_RESET_COUNT)
+ return HARD_RESET_SEND;
+ if (port->pd_capable)
+ return ERROR_RECOVERY;
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ if (port->state == SNK_WAIT_CAPABILITIES)
+ return SNK_READY;
+ return SNK_UNATTACHED;
+}
+
+static inline enum tcpm_state unattached_state(struct tcpm_port *port)
+{
+ if (port->port_type == TYPEC_PORT_DRP) {
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ else
+ return SNK_UNATTACHED;
+ } else if (port->port_type == TYPEC_PORT_SRC) {
+ return SRC_UNATTACHED;
+ }
+
+ return SNK_UNATTACHED;
+}
+
+static void run_state_machine(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int ret;
+
+ port->enter_state = port->state;
+ switch (port->state) {
+ case TOGGLING:
+ break;
+ /* SRC states */
+ case SRC_UNATTACHED:
+ tcpm_src_detach(dev);
+ if (tcpm_start_toggling(dev, tcpm_rp_cc(port))) {
+ tcpm_set_state(dev, TOGGLING, 0);
+ break;
+ }
+ tcpm_set_cc(dev, tcpm_rp_cc(port));
+ if (port->port_type == TYPEC_PORT_DRP)
+ tcpm_set_state(dev, SNK_UNATTACHED, PD_T_DRP_SNK);
+ break;
+ case SRC_ATTACH_WAIT:
+ if (tcpm_port_is_source(port))
+ tcpm_set_state(dev, SRC_ATTACHED, PD_T_CC_DEBOUNCE);
+ break;
+
+ case SRC_ATTACHED:
+ ret = tcpm_src_attach(dev);
+ /*
+ * Currently, vbus control is not implemented,
+ * and the SRC detection process cannot be fully implemented.
+ */
+ tcpm_set_state(dev, SRC_READY, 0);
+ break;
+ case SRC_STARTUP:
+ port->caps_count = 0;
+ port->negotiated_rev = PD_MAX_REV;
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ port->explicit_contract = false;
+ tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+ break;
+ case SRC_SEND_CAPABILITIES:
+ port->caps_count++;
+ if (port->caps_count > PD_N_CAPS_COUNT) {
+ tcpm_set_state(dev, SRC_READY, 0);
+ break;
+ }
+ ret = tcpm_pd_send_source_caps(dev);
+ if (ret < 0) {
+ tcpm_set_state(dev, SRC_SEND_CAPABILITIES,
+ PD_T_SEND_SOURCE_CAP);
+ } else {
+ /*
+ * Per standard, we should clear the reset counter here.
+ * However, that can result in state machine hang-ups.
+ * Reset it only in READY state to improve stability.
+ */
+ /* port->hard_reset_count = 0; */
+ port->caps_count = 0;
+ port->pd_capable = true;
+ tcpm_set_state_cond(dev, SRC_SEND_CAPABILITIES_TIMEOUT,
+ PD_T_SEND_SOURCE_CAP);
+ }
+ break;
+ case SRC_SEND_CAPABILITIES_TIMEOUT:
+ /*
+ * Error recovery for a PD_DATA_SOURCE_CAP reply timeout.
+ *
+ * PD 2.0 sinks are supposed to accept src-capabilities with a
+ * 3.0 header and simply ignore any src PDOs which the sink does
+ * not understand such as PPS but some 2.0 sinks instead ignore
+ * the entire PD_DATA_SOURCE_CAP message, causing contract
+ * negotiation to fail.
+ *
+ * After PD_N_HARD_RESET_COUNT hard-reset attempts, we try
+ * sending src-capabilities with a lower PD revision to
+ * make these broken sinks work.
+ */
+ if (port->hard_reset_count < PD_N_HARD_RESET_COUNT) {
+ tcpm_set_state(dev, HARD_RESET_SEND, 0);
+ } else if (port->negotiated_rev > PD_REV20) {
+ port->negotiated_rev--;
+ port->hard_reset_count = 0;
+ tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state(dev, hard_reset_state(port), 0);
+ }
+ break;
+ case SRC_NEGOTIATE_CAPABILITIES:
+ ret = tcpm_pd_check_request(dev);
+ if (ret < 0) {
+ tcpm_pd_send_control(dev, PD_CTRL_REJECT);
+ if (!port->explicit_contract) {
+ tcpm_set_state(dev,
+ SRC_WAIT_NEW_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state(dev, SRC_READY, 0);
+ }
+ } else {
+ tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+ tcpm_set_state(dev, SRC_TRANSITION_SUPPLY,
+ PD_T_SRC_TRANSITION);
+ }
+ break;
+ case SRC_TRANSITION_SUPPLY:
+ /* XXX: regulator_set_voltage(vbus, ...) */
+ tcpm_pd_send_control(dev, PD_CTRL_PS_RDY);
+ port->explicit_contract = true;
+ tcpm_set_state_cond(dev, SRC_READY, 0);
+ break;
+ case SRC_READY:
+ port->hard_reset_count = 0;
+
+ tcpm_typec_connect(port);
+ break;
+ case SRC_WAIT_NEW_CAPABILITIES:
+ /* Nothing to do... */
+ break;
+
+ /* SNK states */
+ case SNK_UNATTACHED:
+ tcpm_snk_detach(dev);
+ if (tcpm_start_toggling(dev, TYPEC_CC_RD)) {
+ tcpm_set_state(dev, TOGGLING, 0);
+ break;
+ }
+ tcpm_set_cc(dev, TYPEC_CC_RD);
+ if (port->port_type == TYPEC_PORT_DRP)
+ tcpm_set_state(dev, SRC_UNATTACHED, PD_T_DRP_SRC);
+ break;
+ case SNK_ATTACH_WAIT:
+ if ((port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 != TYPEC_CC_OPEN) ||
+ (port->cc1 != TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN))
+ tcpm_set_state(dev, SNK_DEBOUNCED,
+ PD_T_CC_DEBOUNCE);
+ else if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, SNK_UNATTACHED,
+ PD_T_CC_DEBOUNCE);
+ break;
+ case SNK_DEBOUNCED:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, SNK_UNATTACHED, PD_T_PD_DEBOUNCE);
+ else if (port->vbus_present)
+ tcpm_set_state(dev, SNK_ATTACHED, 0);
+ else
+ /* Wait for VBUS, but not forever */
+ tcpm_set_state(dev, PORT_RESET, PD_T_PS_SOURCE_ON);
+ break;
+ case SNK_ATTACHED:
+ ret = tcpm_snk_attach(dev);
+ if (ret < 0)
+ tcpm_set_state(dev, SNK_UNATTACHED, 0);
+ else
+ tcpm_set_state(dev, SNK_STARTUP, 0);
+ break;
+ case SNK_STARTUP:
+ port->negotiated_rev = PD_MAX_REV;
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ port->explicit_contract = false;
+ tcpm_set_state(dev, SNK_DISCOVERY, 0);
+ break;
+ case SNK_DISCOVERY:
+ if (port->vbus_present) {
+ tcpm_set_current_limit(dev,
+ tcpm_get_current_limit(port),
+ 5000);
+ tcpm_set_charge(dev, true);
+ tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+ break;
+ }
+ /*
+ * For DRP, timeouts differ. Also, handling is supposed to be
+ * different and much more complex (dead battery detection;
+ * see USB power delivery specification, section 8.3.3.6.1.5.1).
+ */
+ tcpm_set_state(dev, hard_reset_state(port),
+ port->port_type == TYPEC_PORT_DRP ?
+ PD_T_DB_DETECT : PD_T_NO_RESPONSE);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE:
+ tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE_DONE,
+ PD_T_CC_DEBOUNCE);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE_DONE:
+ tcpm_set_state(dev, unattached_state(port), 0);
+ break;
+ case SNK_WAIT_CAPABILITIES:
+ ret = drvops->set_pd_rx(dev, true);
+ if (ret < 0) {
+ tcpm_set_state(dev, SNK_READY, 0);
+ break;
+ }
+ /*
+ * If VBUS has never been low, and we time out waiting
+ * for source cap, try a soft reset first, in case we
+ * were already in a stable contract before this boot.
+ * Do this only once.
+ */
+ if (port->vbus_never_low) {
+ port->vbus_never_low = false;
+ tcpm_set_state(dev, SOFT_RESET_SEND,
+ PD_T_SINK_WAIT_CAP);
+ } else {
+ tcpm_set_state(dev, hard_reset_state(port),
+ PD_T_SINK_WAIT_CAP);
+ }
+ break;
+ case SNK_NEGOTIATE_CAPABILITIES:
+ port->pd_capable = true;
+ port->hard_reset_count = 0;
+ ret = tcpm_pd_send_request(dev);
+ if (ret < 0) {
+ /* Let the Source send capabilities again. */
+ tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state_cond(dev, hard_reset_state(port),
+ PD_T_SENDER_RESPONSE);
+ }
+ break;
+ case SNK_TRANSITION_SINK:
+ case SNK_TRANSITION_SINK_VBUS:
+ tcpm_set_state(dev, hard_reset_state(port),
+ PD_T_PS_TRANSITION);
+ break;
+ case SNK_READY:
+ port->update_sink_caps = false;
+ tcpm_typec_connect(port);
+ /*
+ * Here poll_event_cnt is cleared, waiting for self-powered Type-C devices
+ * to send DR_swap Messge until 1s (TCPM_POLL_EVENT_TIME_OUT * 500us)timeout
+ */
+ if (port->wait_dr_swap_message)
+ tcpm_reset_event_cnt(dev);
+
+ break;
+
+ /* Hard_Reset states */
+ case HARD_RESET_SEND:
+ tcpm_pd_transmit(dev, TCPC_TX_HARD_RESET, NULL);
+ tcpm_set_state(dev, HARD_RESET_START, 0);
+ port->wait_dr_swap_message = false;
+ break;
+ case HARD_RESET_START:
+ port->hard_reset_count++;
+ drvops->set_pd_rx(dev, false);
+ port->nr_sink_caps = 0;
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(dev, SRC_HARD_RESET_VBUS_OFF,
+ PD_T_PS_HARD_RESET);
+ else
+ tcpm_set_state(dev, SNK_HARD_RESET_SINK_OFF, 0);
+ break;
+ case SRC_HARD_RESET_VBUS_OFF:
+ tcpm_set_vconn(dev, true);
+ tcpm_set_vbus(dev, false);
+ tcpm_set_roles(dev, port->self_powered, TYPEC_SOURCE,
+ TYPEC_HOST);
+ tcpm_set_state(dev, SRC_HARD_RESET_VBUS_ON, PD_T_SRC_RECOVER);
+ break;
+ case SRC_HARD_RESET_VBUS_ON:
+ tcpm_set_vconn(dev, true);
+ tcpm_set_vbus(dev, true);
+ drvops->set_pd_rx(dev, true);
+ tcpm_set_attached_state(dev, true);
+ tcpm_set_state(dev, SRC_UNATTACHED, PD_T_PS_SOURCE_ON);
+ break;
+ case SNK_HARD_RESET_SINK_OFF:
+ tcpm_set_vconn(dev, false);
+ if (port->pd_capable)
+ tcpm_set_charge(dev, false);
+ tcpm_set_roles(dev, port->self_powered, TYPEC_SINK,
+ TYPEC_DEVICE);
+ /*
+ * VBUS may or may not toggle, depending on the adapter.
+ * If it doesn't toggle, transition to SNK_HARD_RESET_SINK_ON
+ * directly after timeout.
+ */
+ tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, PD_T_SAFE_0V);
+ break;
+ case SNK_HARD_RESET_WAIT_VBUS:
+ /* Assume we're disconnected if VBUS doesn't come back. */
+ tcpm_set_state(dev, SNK_UNATTACHED,
+ PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON);
+ break;
+ case SNK_HARD_RESET_SINK_ON:
+ /* Note: There is no guarantee that VBUS is on in this state */
+ /*
+ * XXX:
+ * The specification suggests that dual mode ports in sink
+ * mode should transition to state PE_SRC_Transition_to_default.
+ * See USB power delivery specification chapter 8.3.3.6.1.3.
+ * This would mean to
+ * - turn off VCONN, reset power supply
+ * - request hardware reset
+ * - turn on VCONN
+ * - Transition to state PE_Src_Startup
+ * SNK only ports shall transition to state Snk_Startup
+ * (see chapter 8.3.3.3.8).
+ * Similar, dual-mode ports in source mode should transition
+ * to PE_SNK_Transition_to_default.
+ */
+ if (port->pd_capable) {
+ tcpm_set_current_limit(dev,
+ tcpm_get_current_limit(port),
+ 5000);
+ tcpm_set_charge(dev, true);
+ }
+ tcpm_set_attached_state(dev, true);
+ tcpm_set_state(dev, SNK_STARTUP, 0);
+ break;
+
+ /* Soft_Reset states */
+ case SOFT_RESET:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0);
+ else
+ tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0);
+ break;
+ case SOFT_RESET_SEND:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ if (tcpm_pd_send_control(dev, PD_CTRL_SOFT_RESET))
+ tcpm_set_state_cond(dev, hard_reset_state(port), 0);
+ else
+ tcpm_set_state_cond(dev, hard_reset_state(port),
+ PD_T_SENDER_RESPONSE);
+ break;
+
+ /* DR_Swap states */
+ case DR_SWAP_ACCEPT:
+ tcpm_pd_send_control(dev, PD_CTRL_ACCEPT);
+ tcpm_set_state_cond(dev, DR_SWAP_CHANGE_DR, 0);
+ break;
+ case DR_SWAP_CHANGE_DR:
+ if (port->data_role == TYPEC_HOST) {
+ tcpm_set_roles(dev, true, port->pwr_role,
+ TYPEC_DEVICE);
+ } else {
+ tcpm_set_roles(dev, true, port->pwr_role,
+ TYPEC_HOST);
+ }
+ /* DR_swap process complete, wait_dr_swap_message is cleared */
+ port->wait_dr_swap_message = false;
+ tcpm_set_state(dev, ready_state(port), 0);
+ break;
+ case ERROR_RECOVERY:
+ tcpm_set_state(dev, PORT_RESET, 0);
+ break;
+ case PORT_RESET:
+ tcpm_reset_port(dev);
+ if (port->self_powered)
+ tcpm_set_cc(dev, TYPEC_CC_OPEN);
+ else
+ tcpm_set_cc(dev, tcpm_default_state(port) == SNK_UNATTACHED ?
+ TYPEC_CC_RD : tcpm_rp_cc(port));
+ tcpm_set_state(dev, PORT_RESET_WAIT_OFF,
+ PD_T_ERROR_RECOVERY);
+ break;
+ case PORT_RESET_WAIT_OFF:
+ tcpm_set_state(dev,
+ tcpm_default_state(port),
+ port->vbus_present ? PD_T_PS_SOURCE_OFF : 0);
+ break;
+ default:
+ dev_err(dev, "TCPM: Unexpected port state %d\n", port->state);
+ break;
+ }
+}
+
+static void tcpm_state_machine(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum tcpm_state prev_state;
+
+ mutex_lock(&port->lock);
+ port->state_machine_running = true;
+
+ if (port->queued_message && tcpm_send_queued_message(dev))
+ goto done;
+
+ /* If we were queued due to a delayed state change, update it now */
+ if (port->delayed_state) {
+ dev_dbg(dev, "TCPM: state change %s -> %s [delayed %ld ms]\n",
+ tcpm_states[port->state],
+ tcpm_states[port->delayed_state], port->delay_ms);
+ port->prev_state = port->state;
+ port->state = port->delayed_state;
+ port->delayed_state = INVALID_STATE;
+ }
+
+ /*
+ * Continue running as long as we have (non-delayed) state changes
+ * to make.
+ */
+ do {
+ prev_state = port->state;
+ run_state_machine(dev);
+ if (port->queued_message)
+ tcpm_send_queued_message(dev);
+ } while (port->state != prev_state && !port->delayed_state);
+
+done:
+ port->state_machine_running = false;
+ mutex_unlock(&port->lock);
+}
+
+static void _tcpm_cc_change(struct udevice *dev, enum typec_cc_status cc1,
+ enum typec_cc_status cc2)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum typec_cc_status old_cc1, old_cc2;
+ enum tcpm_state new_state;
+
+ old_cc1 = port->cc1;
+ old_cc2 = port->cc2;
+ port->cc1 = cc1;
+ port->cc2 = cc2;
+
+ dev_dbg(dev, "TCPM: CC1: %u -> %u, CC2: %u -> %u [state %s, polarity %d, %s]\n",
+ old_cc1, cc1, old_cc2, cc2, tcpm_states[port->state],
+ port->polarity,
+ tcpm_port_is_disconnected(port) ? "disconnected" : "connected");
+
+ switch (port->state) {
+ case TOGGLING:
+ if (tcpm_port_is_source(port))
+ tcpm_set_state(dev, SRC_ATTACH_WAIT, 0);
+ else if (tcpm_port_is_sink(port))
+ tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+ break;
+ case SRC_UNATTACHED:
+ case SRC_ATTACH_WAIT:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, SRC_UNATTACHED, 0);
+ else if (cc1 != old_cc1 || cc2 != old_cc2)
+ tcpm_set_state(dev, SRC_ATTACH_WAIT, 0);
+ break;
+ case SRC_ATTACHED:
+ case SRC_SEND_CAPABILITIES:
+ case SRC_READY:
+ if (tcpm_port_is_disconnected(port) ||
+ !tcpm_port_is_source(port))
+ tcpm_set_state(dev, SRC_UNATTACHED, 0);
+ break;
+ case SNK_UNATTACHED:
+ if (tcpm_port_is_sink(port))
+ tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+ break;
+ case SNK_ATTACH_WAIT:
+ if ((port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 != TYPEC_CC_OPEN) ||
+ (port->cc1 != TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN))
+ new_state = SNK_DEBOUNCED;
+ else if (tcpm_port_is_disconnected(port))
+ new_state = SNK_UNATTACHED;
+ else
+ break;
+ if (new_state != port->delayed_state)
+ tcpm_set_state(dev, SNK_ATTACH_WAIT, 0);
+ break;
+ case SNK_DEBOUNCED:
+ if (tcpm_port_is_disconnected(port))
+ new_state = SNK_UNATTACHED;
+ else if (port->vbus_present)
+ new_state = tcpm_try_src(port) ? INVALID_STATE : SNK_ATTACHED;
+ else
+ new_state = SNK_UNATTACHED;
+ if (new_state != port->delayed_state)
+ tcpm_set_state(dev, SNK_DEBOUNCED, 0);
+ break;
+ case SNK_READY:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, unattached_state(port), 0);
+ else if (!port->pd_capable &&
+ (cc1 != old_cc1 || cc2 != old_cc2))
+ tcpm_set_current_limit(dev,
+ tcpm_get_current_limit(port),
+ 5000);
+ break;
+
+ case SNK_DISCOVERY:
+ /* CC line is unstable, wait for debounce */
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE, 0);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE:
+ break;
+
+ case PORT_RESET:
+ case PORT_RESET_WAIT_OFF:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore CC changes here.
+ */
+ break;
+ default:
+ /*
+ * While acting as sink and auto vbus discharge is enabled, Allow disconnect
+ * to be driven by vbus disconnect.
+ */
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(dev, unattached_state(port), 0);
+ break;
+ }
+}
+
+static void _tcpm_pd_vbus_on(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ dev_dbg(dev, "TCPM: VBUS on event\n");
+ port->vbus_present = true;
+ /*
+ * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly
+ * states that vbus is not at VSAFE0V, hence clear the vbus_vsafe0v flag here.
+ */
+ port->vbus_vsafe0v = false;
+
+ switch (port->state) {
+ case SNK_TRANSITION_SINK_VBUS:
+ port->explicit_contract = true;
+ tcpm_set_state(dev, SNK_READY, 0);
+ break;
+ case SNK_DISCOVERY:
+ tcpm_set_state(dev, SNK_DISCOVERY, 0);
+ break;
+ case SNK_DEBOUNCED:
+ tcpm_set_state(dev, SNK_ATTACHED, 0);
+ break;
+ case SNK_HARD_RESET_WAIT_VBUS:
+ tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, 0);
+ break;
+ case SRC_ATTACHED:
+ tcpm_set_state(dev, SRC_STARTUP, 0);
+ break;
+ case SRC_HARD_RESET_VBUS_ON:
+ tcpm_set_state(dev, SRC_STARTUP, 0);
+ break;
+
+ case PORT_RESET:
+ case PORT_RESET_WAIT_OFF:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore vbus changes here.
+ */
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void _tcpm_pd_vbus_off(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ dev_dbg(dev, "TCPM: VBUS off event\n");
+ port->vbus_present = false;
+ port->vbus_never_low = false;
+ switch (port->state) {
+ case SNK_HARD_RESET_SINK_OFF:
+ tcpm_set_state(dev, SNK_HARD_RESET_WAIT_VBUS, 0);
+ break;
+ case HARD_RESET_SEND:
+ break;
+ case SNK_ATTACH_WAIT:
+ tcpm_set_state(dev, SNK_UNATTACHED, 0);
+ break;
+
+ case SNK_NEGOTIATE_CAPABILITIES:
+ break;
+
+ case PORT_RESET_WAIT_OFF:
+ tcpm_set_state(dev, tcpm_default_state(port), 0);
+ break;
+
+ case PORT_RESET:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore vbus changes here.
+ */
+ break;
+
+ default:
+ if (port->pwr_role == TYPEC_SINK && port->attached)
+ tcpm_set_state(dev, SNK_UNATTACHED, 0);
+ break;
+ }
+}
+
+void tcpm_cc_change(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ enum typec_cc_status cc1, cc2;
+
+ tcpm_reset_event_cnt(dev);
+ if (drvops->get_cc(dev, &cc1, &cc2) == 0)
+ _tcpm_cc_change(dev, cc1, cc2);
+}
+
+void tcpm_vbus_change(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ bool vbus;
+
+ tcpm_reset_event_cnt(dev);
+ vbus = drvops->get_vbus(dev);
+ if (vbus)
+ _tcpm_pd_vbus_on(dev);
+ else
+ _tcpm_pd_vbus_off(dev);
+}
+
+void tcpm_pd_hard_reset(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ tcpm_reset_event_cnt(dev);
+ dev_dbg(dev, "TCPM: Received hard reset\n");
+
+ /* If a hard reset message is received during the port reset process,
+ * we should ignore it, that is, do not set port->state to HARD_RESET_START.
+ */
+ if (port->state == PORT_RESET || port->state == PORT_RESET_WAIT_OFF)
+ return;
+
+ /*
+ * If we keep receiving hard reset requests, executing the hard reset
+ * must have failed. Revert to error recovery if that happens.
+ */
+ tcpm_set_state(dev,
+ port->hard_reset_count < PD_N_HARD_RESET_COUNT ?
+ HARD_RESET_START : ERROR_RECOVERY,
+ 0);
+}
+
+static void tcpm_init(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ enum typec_cc_status cc1, cc2;
+
+ drvops->init(dev);
+
+ tcpm_reset_port(dev);
+
+ /*
+ * XXX
+ * Should possibly wait for VBUS to settle if it was enabled locally
+ * since tcpm_reset_port() will disable VBUS.
+ */
+ port->vbus_present = drvops->get_vbus(dev);
+ if (port->vbus_present)
+ port->vbus_never_low = true;
+
+ /*
+ * 1. When vbus_present is true, voltage on VBUS is already at VSAFE5V.
+ * So implicitly vbus_vsafe0v = false.
+ *
+ * 2. When vbus_present is false and TCPC does NOT support querying
+ * vsafe0v status, then, it's best to assume vbus is at VSAFE0V i.e.
+ * vbus_vsafe0v is true.
+ *
+ * 3. When vbus_present is false and TCPC does support querying vsafe0v,
+ * then, query tcpc for vsafe0v status.
+ */
+ if (port->vbus_present)
+ port->vbus_vsafe0v = false;
+ else
+ port->vbus_vsafe0v = true;
+
+ tcpm_set_state(dev, tcpm_default_state(port), 0);
+
+ if (drvops->get_cc(dev, &cc1, &cc2) == 0)
+ _tcpm_cc_change(dev, cc1, cc2);
+}
+
+static int tcpm_fw_get_caps(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ ofnode node;
+ const char *cap_str;
+ int ret;
+ u32 mw;
+
+ ret = drvops->get_connector_node(dev, &node);
+ if (ret)
+ return ret;
+
+ cap_str = ofnode_read_string(node, "power-role");
+ if (!cap_str)
+ return -EINVAL;
+
+ if (!strcmp("dual", cap_str))
+ port->typec_type = TYPEC_PORT_DRP;
+ else if (!strcmp("source", cap_str))
+ port->typec_type = TYPEC_PORT_SRC;
+ else if (!strcmp("sink", cap_str))
+ port->typec_type = TYPEC_PORT_SNK;
+ else
+ return -EINVAL;
+
+ port->port_type = port->typec_type;
+
+ if (port->port_type == TYPEC_PORT_SNK)
+ goto sink;
+
+ /* Get source pdos */
+ ret = ofnode_read_size(node, "source-pdos") / sizeof(u32);
+ if (ret <= 0)
+ return -EINVAL;
+
+ port->nr_src_pdo = min(ret, PDO_MAX_OBJECTS);
+ ret = ofnode_read_u32_array(node, "source-pdos",
+ port->src_pdo, port->nr_src_pdo);
+ if (ret || tcpm_validate_caps(dev, port->src_pdo, port->nr_src_pdo))
+ return -EINVAL;
+
+ if (port->port_type == TYPEC_PORT_SRC)
+ return 0;
+
+ /* Get the preferred power role for DRP */
+ cap_str = ofnode_read_string(node, "try-power-role");
+ if (!cap_str)
+ return -EINVAL;
+
+ if (!strcmp("sink", cap_str))
+ port->typec_prefer_role = TYPEC_SINK;
+ else if (!strcmp("source", cap_str))
+ port->typec_prefer_role = TYPEC_SOURCE;
+ else
+ return -EINVAL;
+
+ if (port->typec_prefer_role < 0)
+ return -EINVAL;
+sink:
+ /* Get sink pdos */
+ ret = ofnode_read_size(node, "sink-pdos") / sizeof(u32);
+ if (ret <= 0)
+ return -EINVAL;
+
+ port->nr_snk_pdo = min(ret, PDO_MAX_OBJECTS);
+ ret = ofnode_read_u32_array(node, "sink-pdos",
+ port->snk_pdo, port->nr_snk_pdo);
+ if (ret || tcpm_validate_caps(dev, port->snk_pdo, port->nr_snk_pdo))
+ return -EINVAL;
+
+ if (ofnode_read_u32_array(node, "op-sink-microwatt", &mw, 1))
+ return -EINVAL;
+ port->operating_snk_mw = mw / 1000;
+
+ port->self_powered = ofnode_read_bool(node, "self-powered");
+
+ return 0;
+}
+
+static int tcpm_port_init(struct udevice *dev)
+{
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+ int err;
+
+ err = tcpm_fw_get_caps(dev);
+ if (err < 0) {
+ dev_err(dev, "TCPM: please check the dts config: %d\n", err);
+ return err;
+ }
+
+ port->try_role = port->typec_prefer_role;
+ port->port_type = port->typec_type;
+
+ tcpm_init(dev);
+
+ dev_info(dev, "TCPM: init finished\n");
+
+ return 0;
+}
+
+static void tcpm_poll_event(struct udevice *dev)
+{
+ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev);
+ struct tcpm_port *port = dev_get_uclass_plat(dev);
+
+ if (!drvops->get_vbus(dev))
+ return;
+
+ while (port->poll_event_cnt < TCPM_POLL_EVENT_TIME_OUT) {
+ if (!port->wait_dr_swap_message &&
+ (port->state == SNK_READY || port->state == SRC_READY))
+ break;
+
+ drvops->poll_event(dev);
+ port->poll_event_cnt++;
+ udelay(500);
+ tcpm_check_and_run_delayed_work(dev);
+ }
+
+ if (port->state != SNK_READY && port->state != SRC_READY)
+ dev_warn(dev, "TCPM: exit in state %s\n",
+ tcpm_states[port->state]);
+
+ /*
+ * At this time, call the callback function of the respective pd chip
+ * to enter the low-power mode. In order to reduce the time spent on
+ * the PD chip driver as much as possible, the tcpm framework does not
+ * fully process the communication initiated by the device,so it should
+ * be noted that we can disable the internal oscillator, etc., but do
+ * not turn off the power of the transceiver module, otherwise the
+ * self-powered Type-C device will initiate a Message(eg: self-powered
+ * Type-C hub initiates a SINK capability request(PD_CTRL_GET_SINK_CAP))
+ * and the pd chip cannot reply to GoodCRC, causing the self-powered Type-C
+ * device to switch vbus to vSafe5v, or even turn off vbus.
+ */
+ if (!drvops->enter_low_power_mode)
+ return;
+
+ if (drvops->enter_low_power_mode(dev, port->attached, port->pd_capable))
+ dev_err(dev, "TCPM: failed to enter low power\n");
+ else
+ dev_info(dev, "TCPM: PD chip enter low power mode\n");
+}
+
+int tcpm_post_probe(struct udevice *dev)
+{
+ int ret = tcpm_port_init(dev);
+
+ if (ret < 0) {
+ dev_err(dev, "failed to tcpm port init\n");
+ return ret;
+ }
+
+ tcpm_poll_event(dev);
+
+ return 0;
+}
diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c
index cb518b1..239b006 100644
--- a/drivers/video/simplefb.c
+++ b/drivers/video/simplefb.c
@@ -27,7 +27,8 @@
return -EINVAL;
}
- debug("%s: base=%llx, size=%llu\n", __func__, base, size);
+ debug("%s: base=%llx, size=%llu\n",
+ __func__, (unsigned long long)base, (unsigned long long)size);
/*
* TODO is there some way to reserve the framebuffer
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 80e7adf..ebe96bf 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -94,7 +94,9 @@
priv->ycur += priv->y_charsize;
/* Check if we need to scroll the terminal */
- if ((priv->ycur + priv->y_charsize) / priv->y_charsize > priv->rows) {
+ if (vid_priv->rot % 2 ?
+ priv->ycur + priv->x_charsize > vid_priv->xsize :
+ priv->ycur + priv->y_charsize > vid_priv->ysize) {
vidconsole_move_rows(dev, 0, rows, priv->rows - rows);
for (i = 0; i < rows; i++)
vidconsole_set_row(dev, priv->rows - i - 1,
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 9823673..a5b3e89 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -294,6 +294,9 @@
{ 0xff, 0x00, 0xff }, /* bright magenta */
{ 0x00, 0xff, 0xff }, /* bright cyan */
{ 0xff, 0xff, 0xff }, /* white */
+
+ /* an extra one for menus */
+ { 0x40, 0x40, 0x40 }, /* dark gray */
};
u32 video_index_to_colour(struct video_priv *priv, enum colour_idx idx)
diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c
index 3404f61..2f999fc 100644
--- a/drivers/virtio/virtio_blk.c
+++ b/drivers/virtio/virtio_blk.c
@@ -18,30 +18,82 @@
struct virtqueue *vq;
};
+static const u32 feature[] = {
+ VIRTIO_BLK_F_WRITE_ZEROES
+};
+
+static void virtio_blk_init_header_sg(struct udevice *dev, u64 sector, u32 type,
+ struct virtio_blk_outhdr *out_hdr, struct virtio_sg *sg)
+{
+ const bool sector_is_needed = type == VIRTIO_BLK_T_IN ||
+ type == VIRTIO_BLK_T_OUT;
+
+ out_hdr->type = cpu_to_virtio32(dev, type);
+ out_hdr->sector = cpu_to_virtio64(dev, sector_is_needed ? sector : 0);
+
+ sg->addr = out_hdr;
+ sg->length = sizeof(*out_hdr);
+}
+
+static void virtio_blk_init_write_zeroes_sg(struct udevice *dev, u64 sector, lbaint_t blkcnt,
+ struct virtio_blk_discard_write_zeroes *wz,
+ struct virtio_sg *sg)
+{
+ wz->sector = cpu_to_virtio64(dev, sector);
+ wz->num_sectors = cpu_to_virtio32(dev, blkcnt);
+ wz->flags = cpu_to_virtio32(dev, 0);
+
+ sg->addr = wz;
+ sg->length = sizeof(*wz);
+}
+
+static void virtio_blk_init_status_sg(u8 *status, struct virtio_sg *sg)
+{
+ sg->addr = status;
+ sg->length = sizeof(*status);
+}
+
+static void virtio_blk_init_data_sg(void *buffer, lbaint_t blkcnt, struct virtio_sg *sg)
+{
+ sg->addr = buffer;
+ sg->length = blkcnt * 512;
+}
+
static ulong virtio_blk_do_req(struct udevice *dev, u64 sector,
lbaint_t blkcnt, void *buffer, u32 type)
{
struct virtio_blk_priv *priv = dev_get_priv(dev);
+ struct virtio_blk_outhdr out_hdr;
+ struct virtio_blk_discard_write_zeroes wz_hdr;
unsigned int num_out = 0, num_in = 0;
+ struct virtio_sg hdr_sg, wz_sg, data_sg, status_sg;
struct virtio_sg *sgs[3];
u8 status;
int ret;
- struct virtio_blk_outhdr out_hdr = {
- .type = cpu_to_virtio32(dev, type),
- .sector = cpu_to_virtio64(dev, sector),
- };
- struct virtio_sg hdr_sg = { &out_hdr, sizeof(out_hdr) };
- struct virtio_sg data_sg = { buffer, blkcnt * 512 };
- struct virtio_sg status_sg = { &status, sizeof(status) };
-
+ virtio_blk_init_header_sg(dev, sector, type, &out_hdr, &hdr_sg);
sgs[num_out++] = &hdr_sg;
- if (type & VIRTIO_BLK_T_OUT)
- sgs[num_out++] = &data_sg;
- else
- sgs[num_out + num_in++] = &data_sg;
+ switch (type) {
+ case VIRTIO_BLK_T_IN:
+ case VIRTIO_BLK_T_OUT:
+ virtio_blk_init_data_sg(buffer, blkcnt, &data_sg);
+ if (type & VIRTIO_BLK_T_OUT)
+ sgs[num_out++] = &data_sg;
+ else
+ sgs[num_out + num_in++] = &data_sg;
+ break;
+ case VIRTIO_BLK_T_WRITE_ZEROES:
+ virtio_blk_init_write_zeroes_sg(dev, sector, blkcnt, &wz_hdr, &wz_sg);
+ sgs[num_out++] = &wz_sg;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ virtio_blk_init_status_sg(&status, &status_sg);
sgs[num_out + num_in++] = &status_sg;
log_debug("dev=%s, active=%d, priv=%p, priv->vq=%p\n", dev->name,
device_active(dev), priv, priv->vq);
@@ -75,6 +127,15 @@
VIRTIO_BLK_T_OUT);
}
+static ulong virtio_blk_erase(struct udevice *dev, lbaint_t start,
+ lbaint_t blkcnt)
+{
+ if (!virtio_has_feature(dev, VIRTIO_BLK_F_WRITE_ZEROES))
+ return -EOPNOTSUPP;
+
+ return virtio_blk_do_req(dev, start, blkcnt, NULL, VIRTIO_BLK_T_WRITE_ZEROES);
+}
+
static int virtio_blk_bind(struct udevice *dev)
{
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent);
@@ -104,7 +165,8 @@
desc->bdev = dev;
/* Indicate what driver features we support */
- virtio_driver_features_init(uc_priv, NULL, 0, NULL, 0);
+ virtio_driver_features_init(uc_priv, feature, ARRAY_SIZE(feature),
+ NULL, 0);
return 0;
}
@@ -131,6 +193,7 @@
static const struct blk_ops virtio_blk_ops = {
.read = virtio_blk_read,
.write = virtio_blk_write,
+ .erase = virtio_blk_erase,
};
U_BOOT_DRIVER(virtio_blk) = {
diff --git a/drivers/virtio/virtio_blk.h b/drivers/virtio/virtio_blk.h
index 8d8e02f..b37ba26 100644
--- a/drivers/virtio/virtio_blk.h
+++ b/drivers/virtio/virtio_blk.h
@@ -17,6 +17,8 @@
#define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available */
#define VIRTIO_BLK_F_TOPOLOGY 10 /* Topology information is available */
#define VIRTIO_BLK_F_MQ 12 /* Support more than one vq */
+#define VIRTIO_BLK_F_DISCARD 13 /* Discard is supported */
+#define VIRTIO_BLK_F_WRITE_ZEROES 14 /* Write zeroes is supported */
/* Legacy feature bits */
#ifndef VIRTIO_BLK_NO_LEGACY
@@ -65,6 +67,39 @@
/* number of vqs, only available when VIRTIO_BLK_F_MQ is set */
__u16 num_queues;
+
+ /* the next 3 entries are guarded by VIRTIO_BLK_F_DISCARD */
+ /*
+ * The maximum discard sectors (in 512-byte sectors) for
+ * one segment.
+ */
+ __u32 max_discard_sectors;
+ /*
+ * The maximum number of discard segments in a
+ * discard command.
+ */
+ __u32 max_discard_seg;
+ /* Discard commands must be aligned to this number of sectors. */
+ __u32 discard_sector_alignment;
+
+ /* the next 3 entries are guarded by VIRTIO_BLK_F_WRITE_ZEROES */
+ /*
+ * The maximum number of write zeroes sectors (in 512-byte sectors) in
+ * one segment.
+ */
+ __u32 max_write_zeroes_sectors;
+ /*
+ * The maximum number of segments in a write zeroes
+ * command.
+ */
+ __u32 max_write_zeroes_seg;
+ /*
+ * Set if a VIRTIO_BLK_T_WRITE_ZEROES request may result in the
+ * deallocation of one or more of the sectors.
+ */
+ __u8 write_zeroes_may_unmap;
+
+ __u8 unused1[3];
};
/*
@@ -93,6 +128,9 @@
/* Get device ID command */
#define VIRTIO_BLK_T_GET_ID 8
+/* Write zeroes command */
+#define VIRTIO_BLK_T_WRITE_ZEROES 13
+
#ifndef VIRTIO_BLK_NO_LEGACY
/* Barrier before this op */
#define VIRTIO_BLK_T_BARRIER 0x80000000
@@ -112,6 +150,15 @@
__virtio64 sector;
};
+struct virtio_blk_discard_write_zeroes {
+ /* discard/write zeroes start sector */
+ __virtio64 sector;
+ /* number of discard/write zeroes sectors */
+ __virtio32 num_sectors;
+ /* flags for this range */
+ __virtio32 flags;
+};
+
#ifndef VIRTIO_BLK_NO_LEGACY
struct virtio_scsi_inhdr {
__virtio32 errors;
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 90bc565..0e45f0a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -175,6 +175,13 @@
help
Enable support for the watchdog timer in Dialog DA9063.
+config WDT_DAVINCI
+ bool "DaVinci watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable the watchdog timer for DaVinci SoCs such as the
+ OMAP-L138.
+
config WDT_GPIO
bool "External gpio watchdog support"
depends on WDT
@@ -184,6 +191,15 @@
doc/device-tree-bindings/watchdog/gpio-wdt.txt for
information on how to describe the watchdog in device tree.
+config SPL_WDT_GPIO
+ bool "External gpio watchdog support in SPL"
+ depends on SPL_WDT
+ depends on SPL_DM_GPIO
+ depends on SPL_OF_REAL
+ default WDT_GPIO
+ help
+ Support for external watchdog fed by toggling a gpio in SPL.
+
config WDT_MAX6370
bool "MAX6370 watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 51be6ab..0b107c0 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -30,8 +30,9 @@
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_DA9063) += da9063-wdt.o
+obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o
obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
-obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
+obj-$(CONFIG_$(SPL_TPL_)WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
obj-$(CONFIG_WDT_MCF) += mcf_wdt.o
obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
new file mode 100644
index 0000000..fa8d784
--- /dev/null
+++ b/drivers/watchdog/davinci_wdt.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DaVinci Watchdog driver
+ *
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <wdt.h>
+
+/* Control Register */
+#define DAVINCI_WDT_ID 0x00
+#define DAVINCI_WDT_TIM12 0x10
+#define DAVINCI_WDT_TIM34 0x14
+#define DAVINCI_WDT_PRD12 0x18
+#define DAVINCI_WDT_PRD34 0x1C
+#define DAVINCI_WDT_TCR 0x20
+#define DAVINCI_WDT_TGCR 0x24
+#define DAVINCI_WDT_WDTCR 0x28
+
+#define DAVINCI_TCR_CONT_EN BIT(7)
+
+#define DAVINCI_TGCR_PLUSEN BIT(4)
+#define DAVINCI_TGCR_WDT_MODE BIT(3)
+#define DAVINCI_TGCR_TIM34RS BIT(1)
+#define DAVINCI_TGCR_TIM12RS BIT(0)
+
+#define DAVINCI_WDTCR_INVALID_KEY (0x5555 << 16)
+#define DAVINCI_WDTCR_WDKEY0 (0xA5C6 << 16)
+#define DAVINCI_WDTCR_WDKEY1 (0xDA7E << 16)
+#define DAVINCI_WDTCR_WDFLAG BIT(15)
+#define DAVINCI_WDTCR_WDEN BIT(14)
+
+#define DEFAULT_THRESHOLD 0xA03200000
+
+struct davinci_wdt_priv {
+ void __iomem *base;
+ struct clk *ref_clk;
+};
+
+static int davinci_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct davinci_wdt_priv *priv = dev_get_priv(dev);
+ ulong rate = clk_get_rate(priv->ref_clk);
+ u64 threshold;
+
+ if (!rate)
+ threshold = DEFAULT_THRESHOLD;
+ else
+ threshold = rate * timeout_ms / 1000;
+
+ /* Reset control registers */
+ writel(0, priv->base + DAVINCI_WDT_TCR);
+ writel(0, priv->base + DAVINCI_WDT_TGCR);
+
+ /* Enable watchdog mode and timers */
+ writel(DAVINCI_TGCR_WDT_MODE | DAVINCI_TGCR_TIM12RS | DAVINCI_TGCR_TIM34RS,
+ priv->base + DAVINCI_WDT_TGCR);
+
+ /* Reset counters */
+ writel(0, priv->base + DAVINCI_WDT_TIM12);
+ writel(0, priv->base + DAVINCI_WDT_TIM34);
+
+ /* Set timeout threshold */
+ writel(threshold & 0xFFFFFFFF, priv->base + DAVINCI_WDT_PRD12);
+ writel(threshold >> 32, priv->base + DAVINCI_WDT_PRD34);
+
+ /* Enable counter */
+ writel(DAVINCI_TCR_CONT_EN, priv->base + DAVINCI_WDT_TCR);
+
+ /* Go to watchdog's active state */
+ writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY0, priv->base + DAVINCI_WDT_WDTCR);
+ writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY1, priv->base + DAVINCI_WDT_WDTCR);
+
+ return 0;
+}
+
+static int davinci_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct davinci_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(DAVINCI_WDTCR_INVALID_KEY, priv->base + DAVINCI_WDT_WDTCR);
+
+ return 0;
+}
+
+static int davinci_wdt_restart(struct udevice *dev)
+{
+ struct davinci_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY0, priv->base + DAVINCI_WDT_WDTCR);
+ writel(DAVINCI_WDTCR_WDEN | DAVINCI_WDTCR_WDKEY1, priv->base + DAVINCI_WDT_WDTCR);
+
+ return 0;
+}
+
+static int davinci_wdt_probe(struct udevice *dev)
+{
+ struct davinci_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr_index(dev, 0);
+ if (!priv->base)
+ return -EFAULT;
+
+ priv->ref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(priv->ref_clk))
+ return PTR_ERR(priv->ref_clk);
+
+ return 0;
+}
+
+static const struct wdt_ops davinci_wdt_ops = {
+ .start = davinci_wdt_start,
+ .reset = davinci_wdt_restart,
+ .expire_now = davinci_wdt_expire_now,
+};
+
+static const struct udevice_id davinci_wdt_ids[] = {
+ {.compatible = "ti,davinci-wdt"},
+ {}
+};
+
+U_BOOT_DRIVER(davinci_wdt) = {
+ .name = "davinci_wdt",
+ .id = UCLASS_WDT,
+ .probe = davinci_wdt_probe,
+ .of_match = davinci_wdt_ids,
+ .ops = &davinci_wdt_ops,
+ .priv_auto = sizeof(struct davinci_wdt_priv),
+};
diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c
index 2920c2c..e889861 100644
--- a/drivers/watchdog/gpio_wdt.c
+++ b/drivers/watchdog/gpio_wdt.c
@@ -45,14 +45,32 @@
if (priv->always_running)
return 0;
- return -ENOSYS;
+ dm_gpio_set_dir_flags(&priv->gpio, GPIOD_IS_OUT);
+ gpio_wdt_reset(dev);
+
+ return 0;
+}
+
+static int gpio_wdt_stop(struct udevice *dev)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+
+ if (priv->always_running)
+ return -EOPNOTSUPP;
+
+ if (priv->hw_algo == HW_ALGO_TOGGLE)
+ dm_gpio_set_dir_flags(&priv->gpio, GPIOD_IS_IN);
+ else
+ dm_gpio_set_value(&priv->gpio, 1);
+
+ return 0;
}
static int dm_probe(struct udevice *dev)
{
struct gpio_wdt_priv *priv = dev_get_priv(dev);
- int ret;
const char *algo = dev_read_string(dev, "hw_algo");
+ int ret, flags;
if (!algo)
return -EINVAL;
@@ -64,7 +82,9 @@
return -EINVAL;
priv->always_running = dev_read_bool(dev, "always-running");
- ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT);
+ flags = priv->always_running || priv->hw_algo == HW_ALGO_LEVEL ?
+ GPIOD_IS_OUT : GPIOD_IS_IN;
+ ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, flags);
if (ret < 0) {
dev_err(dev, "Request for wdt gpio failed: %d\n", ret);
return ret;
@@ -78,6 +98,7 @@
static const struct wdt_ops gpio_wdt_ops = {
.start = gpio_wdt_start,
+ .stop = gpio_wdt_stop,
.reset = gpio_wdt_reset,
};
diff --git a/dts/Kconfig b/dts/Kconfig
index 569d4be..ffd50c04 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -125,6 +125,22 @@
help
Select the vendor to build all devicetree files for.
+config OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS
+ bool "Build local DTBOs as fallback for DTBOs missing upstream"
+ default n
+ depends on OF_UPSTREAM
+ help
+ Enable building DTBOs from arch/$(ARCH)/dts as a fallback for
+ DTBOs which are not part of Linux kernel upstream yet. This is
+ a stopgap measure to expedite OF_UPSTREAM switch for platforms
+ which already have main DT in Linux kernel upstream, but still
+ have leftover DTBOs in U-Boot tree.
+
+ Do not use this option, upstream your DTs and DTBOs instead.
+ If the upstreaming is in progress, use with utmost caution.
+
+ If unsure, say N.
+
choice
prompt "Provider of DTB for DT control"
depends on OF_CONTROL
@@ -226,11 +242,11 @@
config OF_OVERLAY_LIST
string "List of device tree overlays to include for DT control"
- depends on SPL_LOAD_FIT_APPLY_OVERLAY
help
This option specifies a list of device tree overlays to use for DT
control. This option can then be used by a FIT generator to include
- the overlays in the FIT image.
+ the overlays in the FIT image or by binman when assembling an image
+ that uses overlays during DT fixup.
choice
prompt "OF LIST compression"
diff --git a/dts/Makefile b/dts/Makefile
index 62a6568..86bf8dc 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -20,6 +20,12 @@
dt_dir := arch/$(ARCH)/dts
endif
+ifneq ($(CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS),)
+local_dtbos := local-dtbos
+else
+local_dtbos :=
+endif
+
ifneq ($(EXT_DTB),)
DTB := $(EXT_DTB)
else
@@ -40,7 +46,7 @@
targets += dt.dtb
-$(DTB): arch-dtbs
+$(DTB): arch-dtbs $(local_dtbos)
$(Q)test -e $@ || ( \
echo >&2; \
echo >&2 "Device Tree Source ($@) is not correctly specified."; \
@@ -53,6 +59,12 @@
arch-dtbs:
$(Q)$(MAKE) $(build)=$(dt_dir) dtbs
+ifneq ($(CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS),)
+PHONY += local-dtbos
+local-dtbos:
+ $(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbos
+endif
+
ifeq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_OF_EMBED) := dt-spl.dtb.o
# support "out-of-tree" build for dtb-spl
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-odroid-m1s.dts b/dts/upstream/src/arm64/rockchip/rk3566-odroid-m1s.dts
new file mode 100644
index 0000000..33bc524
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-odroid-m1s.dts
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Hardkernel ODROID-M1S";
+ compatible = "hardkernel,odroid-m1s", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_led>, <&sys_led>;
+
+ led_pwr: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ led_sys: led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc3v3_lcd: regulator-3v3-vcc-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren>;
+ regulator-name = "vcc3v3_lcd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_pcie: regulator-3v3-vcc-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: regulator-3v3-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb2_host: regulator-5v0-vcc-usb2-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_host_pwren>;
+ regulator-name = "vcc5v0_usb2_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb2_otg: regulator-5v0-vcc-usb2-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_otg_pwren>;
+ regulator-name = "vcc5v0_usb2_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb3_host: regulator-5v0-vcc-usb3-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_host_pwren>;
+ regulator-name = "vcc5v0_usb3_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1m1_clkinout>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ clock-names = "mclk";
+ clock-output-names = "rk809-clkout1", "rk809-clkout2";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ #sound-dai-cells = <0>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_pins>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd {
+ lcd_pwren: lcd-pwren {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ pwr_led: pwr-led {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led: sys-led {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20_pins: pcie20-pins {
+ rockchip,pins =
+ <1 RK_PB0 4 &pcfg_pull_none>,
+ <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ pcie_pwren: pcie-pwren {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ usb2_host_pwren: usb2-host-pwren {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb2_otg_pwren: usb2-otg-pwren {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb3_host_pwren: usb3-host-pwren {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb3_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb2_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb2_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb2_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-odroid-m1.dts b/dts/upstream/src/arm64/rockchip/rk3568-odroid-m1.dts
index a337f54..6a02db4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-odroid-m1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-odroid-m1.dts
@@ -13,7 +13,7 @@
/ {
model = "Hardkernel ODROID-M1";
- compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
+ compatible = "hardkernel,odroid-m1", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6-lts.dts b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6-lts.dts
new file mode 100644
index 0000000..2d92bbb
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6-lts.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Thomas McKahan
+ * Copyright (c) 2024 Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-nanopc-t6.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T6 LTS";
+ compatible = "friendlyarm,nanopc-t6-lts", "rockchip,rk3588";
+
+ /* provide power for on-board USB 2.0 hub */
+ vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb20_host_pwren>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_usb20_host";
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&pinctrl {
+ usb {
+ usb20_host_pwren: usb20-host-pwren {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb20_host>;
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
index ad8e36a..92321c1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
@@ -2,175 +2,18 @@
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Thomas McKahan
+ * Copyright (c) 2024 Linaro Ltd.
*
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
+#include "rk3588-nanopc-t6.dtsi"
/ {
model = "FriendlyElec NanoPC-T6";
compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- sys_led: led-0 {
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- label = "system-led";
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&sys_led_pin>;
- };
-
- usr_led: led-1 {
- gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
- label = "user-led";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pin>;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det>;
-
- simple-audio-card,name = "realtek,rt5616-codec";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
- simple-audio-card,hp-pin-name = "Headphones";
-
- simple-audio-card,widgets =
- "Headphone", "Headphones",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "MIC1", "Microphone Jack",
- "Microphone Jack", "micbias1";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- };
- simple-audio-card,codec {
- sound-dai = <&rt5616>;
- };
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* vcc5v0_sys powers peripherals */
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- /* vcc4v0_sys powers the RK806, RK860's */
- vcc4v0_sys: vcc4v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc4v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <4000000>;
- regulator-max-microvolt = <4000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc-1v1-nldo-s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc4v0_sys>;
- };
-
- vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_pcie20";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vbus5v0_typec: vbus5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_m2_1_pwren>;
- regulator-name = "vcc3v3_pcie2x1l0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_m2_0_pwren>;
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
- compatible = "regulator-fixed";
- enable-active-low;
- gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "vcc3v3_sd_s0";
- vin-supply = <&vcc_3v3_s3>;
- };
-
vdd_4g_3v3: vdd-4g-3v3-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -184,762 +27,14 @@
};
};
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&gpio0 {
- gpio-line-names = /* GPIO0 A0-A7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO0 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO0 C0-C7 */
- "", "", "", "",
- "HEADER_10", "HEADER_08", "HEADER_32", "",
- /* GPIO0 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio1 {
- gpio-line-names = /* GPIO1 A0-A7 */
- "HEADER_27", "HEADER_28", "", "",
- "", "", "", "HEADER_15",
- /* GPIO1 B0-B7 */
- "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
- "HEADER_24", "HEADER_22", "", "",
- /* GPIO1 C0-C7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO1 D0-D7 */
- "", "", "", "",
- "", "", "HEADER_05", "HEADER_03";
-};
-
-&gpio2 {
- gpio-line-names = /* GPIO2 A0-A7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO2 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO2 C0-C7 */
- "", "CSI1_11", "CSI1_12", "",
- "", "", "", "",
- /* GPIO2 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names = /* GPIO3 A0-A7 */
- "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
- "HEADER_37", "", "DSI0_12", "",
- /* GPIO3 B0-B7 */
- "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
- "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
- /* GPIO3 C0-C7 */
- "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
- "", "", "", "",
- /* GPIO3 D0-D7 */
- "", "", "", "",
- "", "DSI1_10", "", "";
-};
-
-&gpio4 {
- gpio-line-names = /* GPIO4 A0-A7 */
- "DSI1_08", "DSI1_14", "", "DSI1_12",
- "", "", "", "",
- /* GPIO4 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO4 C0-C7 */
- "", "", "", "",
- "CSI0_11", "CSI0_12", "", "",
- /* GPIO4 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- clock-frequency = <200000>;
- status = "okay";
-
- fusb302: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&usbc0_int>;
- pinctrl-names = "default";
- vbus-supply = <&vbus5v0_typec>;
-
- connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- op-sink-microwatt = <1000000>;
- };
- };
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- clock-frequency = <200000>;
- status = "okay";
-
- rt5616: codec@1b {
- compatible = "realtek,rt5616";
- reg = <0x1b>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
-
- port {
- rt5616_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-
- /* connected with MIPI-CSI1 */
-};
-
-&i2c8 {
- pinctrl-0 = <&i2c8m2_xfer>;
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&rt5616_p0_0>;
- };
- };
-};
-
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc_3v3_pcie20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_rst>;
- status = "okay";
-};
-
-&pcie2x1l1 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_1_rst>;
- status = "okay";
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc_3v3_pcie20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_2_rst>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
&pinctrl {
- gpio-leds {
- sys_led_pin: sys-led-pin {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- usr_led_pin: usr-led-pin {
- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pcie {
- pcie2_0_rst: pcie2-0-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_1_rst: pcie2-1-rst {
- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_2_rst: pcie2-2-rst {
- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_m2_0_pwren: pcie-m20-pwren {
- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_m2_1_pwren: pcie-m21-pwren {
- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
usb {
pin_4g_lte_pwren: 4g-lte-pwren {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm1 {
- pinctrl-0 = <&pwm1m1_pins>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&avcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- no-mmc;
- no-sdio;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- system-power-controller;
-
- vcc1-supply = <&vcc4v0_sys>;
- vcc2-supply = <&vcc4v0_sys>;
- vcc3-supply = <&vcc4v0_sys>;
- vcc4-supply = <&vcc4v0_sys>;
- vcc5-supply = <&vcc4v0_sys>;
- vcc6-supply = <&vcc4v0_sys>;
- vcc7-supply = <&vcc4v0_sys>;
- vcc8-supply = <&vcc4v0_sys>;
- vcc9-supply = <&vcc4v0_sys>;
- vcc10-supply = <&vcc4v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc4v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc4v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
};
};
-&tsadc {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
&u2phy2_host {
phy-supply = <&vdd_4g_3v3>;
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi
new file mode 100644
index 0000000..77580c6
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi
@@ -0,0 +1,943 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Thomas McKahan
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T6";
+ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys_led: led-0 {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "system-led";
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
+
+ usr_led: led-1 {
+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ label = "user-led";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_led_pin>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+
+ simple-audio-card,name = "realtek,rt5616-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+ simple-audio-card,hp-pin-name = "Headphones";
+
+ simple-audio-card,widgets =
+ "Headphone", "Headphones",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "MIC1", "Microphone Jack",
+ "Microphone Jack", "micbias1";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rt5616>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* vcc5v0_sys powers peripherals */
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ /* vcc4v0_sys powers the RK806, RK860's */
+ vcc4v0_sys: vcc4v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-1v1-nldo-s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc4v0_sys>;
+ };
+
+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_pcie20";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_m2_1_pwren>;
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_m2_0_pwren>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd_s0";
+ vin-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&gpio0 {
+ gpio-line-names = /* GPIO0 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO0 C0-C7 */
+ "", "", "", "",
+ "HEADER_10", "HEADER_08", "HEADER_32", "",
+ /* GPIO0 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A0-A7 */
+ "HEADER_27", "HEADER_28", "", "",
+ "", "", "", "HEADER_15",
+ /* GPIO1 B0-B7 */
+ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
+ "HEADER_24", "HEADER_22", "", "",
+ /* GPIO1 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO1 D0-D7 */
+ "", "", "", "",
+ "", "", "HEADER_05", "HEADER_03";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 C0-C7 */
+ "", "CSI1_11", "CSI1_12", "",
+ "", "", "", "",
+ /* GPIO2 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A0-A7 */
+ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
+ "HEADER_37", "", "DSI0_12", "",
+ /* GPIO3 B0-B7 */
+ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
+ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
+ /* GPIO3 C0-C7 */
+ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
+ "", "", "", "",
+ /* GPIO3 D0-D7 */
+ "", "", "", "",
+ "", "DSI1_10", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A0-A7 */
+ "DSI1_08", "DSI1_14", "", "DSI1_12",
+ "", "", "", "",
+ /* GPIO4 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO4 C0-C7 */
+ "", "", "", "",
+ "CSI0_11", "CSI0_12", "", "",
+ /* GPIO4 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <200000>;
+ status = "okay";
+
+ fusb302: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&usbc0_int>;
+ pinctrl-names = "default";
+ vbus-supply = <&vbus5v0_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <1000000>;
+ };
+ };
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ clock-frequency = <200000>;
+ status = "okay";
+
+ rt5616: codec@1b {
+ compatible = "realtek,rt5616";
+ reg = <0x1b>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+
+ port {
+ rt5616_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+
+ /* connected with MIPI-CSI1 */
+};
+
+&i2c8 {
+ pinctrl-0 = <&i2c8m2_xfer>;
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&rt5616_p0_0>;
+ };
+ };
+};
+
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ status = "okay";
+};
+
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_2_rst>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usr_led_pin: usr-led-pin {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_m2_0_pwren: pcie-m20-pwren {
+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_m2_1_pwren: pcie-m21-pwren {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1m1_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+/* optional on non-LTS, populated on LTS version */
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim1_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ system-power-controller;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts
new file mode 100644
index 0000000..63d9123
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts
@@ -0,0 +1,903 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Hardkernel ODROID-M2";
+ compatible = "hardkernel,odroid-m2", "rockchip,rk3588s";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_led>, <&sys_led>;
+
+ led_pwr: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led_sys: led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 192 224 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm0 0 22222 0>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-1v1-vcc-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc4v0_sys>;
+ };
+
+ vcc3v3_lcd: regulator-3v3-vcc-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren>;
+ regulator-name = "vcc3v3_lcd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie: regulator-3v3-vcc-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_3v3_s0: regulator-3v3-vcc-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc4v0_sys: regulator-4v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4800000>;
+ regulator-max-microvolt = <4800000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_pwren>;
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb2_host: regulator-5v0-vcc-usb2-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_host_pwren>;
+ regulator-name = "vcc5v0_usb2_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb3_host: regulator-5v0-vcc-usb3-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_host_pwren>;
+ regulator-name = "vcc5v0_usb3_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb3_typec: regulator-5v0-vcc-usb3-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_typec_pwren>;
+ regulator-name = "vcc5v0_usb3_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcca: regulator-5v0-vcca {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc12v_dcin: regulator-12v0-vcc-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3_s0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus
+ &gmac1_clkinout>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc4v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8m2_xfer>;
+ status = "okay";
+
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vcc5v0_usb3_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "source";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usbc0_role_switch: endpoint {
+ remote-endpoint = <&usb_host0_xhci_role_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usbc0_orientation_switch: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usbc0_dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcf8563_int>;
+ wakeup-source;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&package_thermal {
+ polling-delay = <1000>;
+
+ trips {
+ package_fan0: package-fan0 {
+ hysteresis = <2000>;
+ temperature = <60000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 THERMAL_NO_LIMIT>;
+ trip = <&package_fan0>;
+ };
+ };
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_pins>;
+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd {
+ lcd_pwren: lcd-pwren {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ pwr_led: pwr-led {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led: sys-led {
+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20x1_pins: pcie20x1-pins {
+ rockchip,pins =
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ pcie_pwren: pcie-pwren {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ regulator {
+ vcc5v0_pwren: vcc5v0-pwren {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtc {
+ pcf8563_int: pcf8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb2_host_pwren: usb2-host-pwren {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb3_host_pwren: usb3-host-pwren {
+ rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb3_typec_pwren: usb3-typec-pwren {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0m2_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3_s0>;
+ vqmmc-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0>, <&spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcca>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg3 {
+ regulator-name = "vdd_logic_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3_pldo6: pldo-reg6 {
+ regulator-name = "vcc_1v8_s3_pldo6";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* Schematics show not in use */
+ nldo-reg5 {
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb2_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb3_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb_host0_xhci_role_switch: endpoint {
+ remote-endpoint = <&usbc0_role_switch>;
+ };
+ };
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ mode-switch;
+ orientation-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orientation_switch>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_dp_altmode_mux>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
index e2584a5..b3c4c0e 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
@@ -9,11 +9,6 @@
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
-&mcu_r5fss0 {
- /* lock-step mode not supported on PG2 boards */
- ti,cluster-mode = <0>;
-};
-
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
index ef34b85..e76828c 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
@@ -635,3 +635,8 @@
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on iot2050 boards */
+ ti,cluster-mode = <0>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
index 29a3189..4968a47 100644
--- a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
+++ b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts
@@ -22,8 +22,3 @@
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
similarity index 91%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
rename to dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
index c9e7360..666237f 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0
- * Copyright (c) Siemens AG, 2022
+ * Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
similarity index 95%
rename from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
rename to dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
index 72fc011..0f86235 100644
--- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
- * Copyright (c) Siemens AG, 2022
+ * Copyright (c) Siemens AG, 2022-2024
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
diff --git a/dts/upstream/src/riscv/Makefile b/dts/upstream/src/riscv/Makefile
new file mode 100644
index 0000000..980617e
--- /dev/null
+++ b/dts/upstream/src/riscv/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+DTC_FLAGS += -R 4 -p 0x1000
+
diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c
index 2141edf..97af8cb 100644
--- a/fs/cramfs/uncompress.c
+++ b/fs/cramfs/uncompress.c
@@ -21,9 +21,9 @@
*/
#include <stdio.h>
-#include <cyclic.h>
#include <malloc.h>
#include <watchdog.h>
+#include <u-boot/schedule.h>
#include <u-boot/zlib.h>
static z_stream stream;
@@ -63,7 +63,7 @@
stream.avail_in = 0;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- stream.outcb = (cb_func)cyclic_run;
+ stream.outcb = (cb_func)schedule;
#else
stream.outcb = Z_NULL;
#endif /* CONFIG_HW_WATCHDOG */
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 76f7102..cc150cf 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2046,24 +2046,23 @@
unsigned int fpos = 0;
int status;
loff_t actread;
- struct ext2fs_node *diro = (struct ext2fs_node *) dir;
#ifdef DEBUG
if (name != NULL)
printf("Iterate dir %s\n", name);
#endif /* of DEBUG */
- if (!diro->inode_read) {
- status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
+ if (!dir->inode_read) {
+ status = ext4fs_read_inode(dir->data, dir->ino, &dir->inode);
if (status == 0)
return 0;
}
/* Search the file. */
- while (fpos < le32_to_cpu(diro->inode.size)) {
+ while (fpos < le32_to_cpu(dir->inode.size)) {
struct ext2_dirent dirent;
- status = ext4fs_read_file(diro, fpos,
- sizeof(struct ext2_dirent),
- (char *)&dirent, &actread);
+ status = ext4fs_read_file(dir, fpos,
+ sizeof(struct ext2_dirent),
+ (char *)&dirent, &actread);
if (status < 0)
return 0;
@@ -2077,7 +2076,7 @@
struct ext2fs_node *fdiro;
int type = FILETYPE_UNKNOWN;
- status = ext4fs_read_file(diro,
+ status = ext4fs_read_file(dir,
fpos +
sizeof(struct ext2_dirent),
dirent.namelen, filename,
@@ -2089,7 +2088,7 @@
if (!fdiro)
return 0;
- fdiro->data = diro->data;
+ fdiro->data = dir->data;
fdiro->ino = le32_to_cpu(dirent.inode);
filename[dirent.namelen] = '\0';
@@ -2104,7 +2103,7 @@
else if (dirent.filetype == FILETYPE_REG)
type = FILETYPE_REG;
} else {
- status = ext4fs_read_inode(diro->data,
+ status = ext4fs_read_inode(dir->data,
le32_to_cpu
(dirent.inode),
&fdiro->inode);
@@ -2138,35 +2137,6 @@
*fnode = fdiro;
return 1;
}
- } else {
- if (fdiro->inode_read == 0) {
- status = ext4fs_read_inode(diro->data,
- le32_to_cpu(
- dirent.inode),
- &fdiro->inode);
- if (status == 0) {
- free(fdiro);
- return 0;
- }
- fdiro->inode_read = 1;
- }
- switch (type) {
- case FILETYPE_DIRECTORY:
- printf("<DIR> ");
- break;
- case FILETYPE_SYMLINK:
- printf("<SYM> ");
- break;
- case FILETYPE_REG:
- printf(" ");
- break;
- default:
- printf("< ? > ");
- break;
- }
- printf("%10u %s\n",
- le32_to_cpu(fdiro->inode.size),
- filename);
}
free(fdiro);
}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 15587e9..dfecfa0 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -21,17 +21,36 @@
*/
#include <blk.h>
+#include <div64.h>
+#include <errno.h>
#include <ext_common.h>
#include <ext4fs.h>
-#include "ext4_common.h"
-#include <div64.h>
#include <malloc.h>
#include <part.h>
#include <u-boot/uuid.h>
+#include "ext4_common.h"
int ext4fs_symlinknest;
struct ext_filesystem ext_fs;
+/**
+ * struct ext4_dir_stream - ext4 directory stream
+ *
+ * @parent: partition data used by fs layer.
+ * This field must be at the beginning of the structure.
+ * All other fields are private to the ext4 driver.
+ * @root: root directory node
+ * @dir: directory node
+ * @dirent: directory stream entry
+ * @fpos: file position in directory
+ */
+struct ext4_dir_stream {
+ struct fs_dir_stream parent;
+ char *dirname;
+ struct fs_dirent dirent;
+ unsigned int fpos;
+};
+
struct ext_filesystem *get_fs(void)
{
return &ext_fs;
@@ -182,39 +201,159 @@
return 0;
}
-int ext4fs_ls(const char *dirname)
+int ext4fs_opendir(const char *dirname, struct fs_dir_stream **dirsp)
{
- struct ext2fs_node *dirnode = NULL;
- int status;
+ struct ext4_dir_stream *dirs;
+ struct ext2fs_node *dir = NULL;
+ int ret;
- if (dirname == NULL)
- return 0;
+ *dirsp = NULL;
- status = ext4fs_find_file(dirname, &ext4fs_root->diropen, &dirnode,
- FILETYPE_DIRECTORY);
- if (status != 1) {
- printf("** Can not find directory. **\n");
- if (dirnode)
- ext4fs_free_node(dirnode, &ext4fs_root->diropen);
- return 1;
+ dirs = calloc(1, sizeof(struct ext4_dir_stream));
+ if (!dirs)
+ return -ENOMEM;
+ dirs->dirname = strdup(dirname);
+ if (!dirs) {
+ free(dirs);
+ return -ENOMEM;
}
- ext4fs_iterate_dir(dirnode, NULL, NULL, NULL);
- ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+ ret = ext4fs_find_file(dirname, &ext4fs_root->diropen, &dir,
+ FILETYPE_DIRECTORY);
+ if (ret == 1) {
+ ret = 0;
+ *dirsp = (struct fs_dir_stream *)dirs;
+ } else {
+ ret = -ENOENT;
+ }
- return 0;
+ if (dir)
+ ext4fs_free_node(dir, &ext4fs_root->diropen);
+
+ return ret;
}
+int ext4fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
+ struct ext4_dir_stream *dirs = (struct ext4_dir_stream *)fs_dirs;
+ struct fs_dirent *dent = &dirs->dirent;
+ struct ext2fs_node *dir = NULL;
+ int ret;
+ loff_t actread;
+ struct ext2fs_node fdiro;
+ int len;
+ struct ext2_dirent dirent;
+
+ *dentp = NULL;
+
+ ret = ext4fs_find_file(dirs->dirname, &ext4fs_root->diropen, &dir,
+ FILETYPE_DIRECTORY);
+ if (ret != 1) {
+ ret = -ENOENT;
+ goto out;
+ }
+ if (!dir->inode_read) {
+ ret = ext4fs_read_inode(dir->data, dir->ino, &dir->inode);
+ if (!ret) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+ if (dirs->fpos >= le32_to_cpu(dir->inode.size))
+ return -ENOENT;
+
+ memset(dent, 0, sizeof(struct fs_dirent));
+
+ while (dirs->fpos < le32_to_cpu(dir->inode.size)) {
+ ret = ext4fs_read_file(dir, dirs->fpos,
+ sizeof(struct ext2_dirent),
+ (char *)&dirent, &actread);
+ if (ret < 0)
+ return -ret;
+
+ if (!dirent.direntlen)
+ return -EIO;
+
+ if (dirent.namelen)
+ break;
+
+ dirs->fpos += le16_to_cpu(dirent.direntlen);
+ }
+
+ len = min(FS_DIRENT_NAME_LEN - 1, (int)dirent.namelen);
+
+ ret = ext4fs_read_file(dir, dirs->fpos + sizeof(struct ext2_dirent),
+ len, dent->name, &actread);
+ if (ret < 0)
+ goto out;
+ dent->name[len] = '\0';
+
+ fdiro.data = dir->data;
+ fdiro.ino = le32_to_cpu(dirent.inode);
+
+ ret = ext4fs_read_inode(dir->data, fdiro.ino, &fdiro.inode);
+ if (!ret) {
+ ret = -EIO;
+ goto out;
+ }
+
+ switch (le16_to_cpu(fdiro.inode.mode) & FILETYPE_INO_MASK) {
+ case FILETYPE_INO_DIRECTORY:
+ dent->type = FS_DT_DIR;
+ break;
+ case FILETYPE_INO_SYMLINK:
+ dent->type = FS_DT_LNK;
+ break;
+ case FILETYPE_INO_REG:
+ dent->type = FS_DT_REG;
+ break;
+ default:
+ dent->type = FILETYPE_UNKNOWN;
+ }
+
+ rtc_to_tm(fdiro.inode.atime, &dent->access_time);
+ rtc_to_tm(fdiro.inode.ctime, &dent->create_time);
+ rtc_to_tm(fdiro.inode.mtime, &dent->change_time);
+
+ dirs->fpos += le16_to_cpu(dirent.direntlen);
+ dent->size = fdiro.inode.size;
+ *dentp = dent;
+ ret = 0;
+
+out:
+ if (dir)
+ ext4fs_free_node(dir, &ext4fs_root->diropen);
+
+ return ret;
+}
+
+void ext4fs_closedir(struct fs_dir_stream *fs_dirs)
+{
+ struct ext4_dir_stream *dirs = (struct ext4_dir_stream *)fs_dirs;
+
+ if (!dirs)
+ return;
+
+ free(dirs->dirname);
+ free(dirs);
+}
+
int ext4fs_exists(const char *filename)
{
struct ext2fs_node *dirnode = NULL;
int filetype;
+ int ret;
if (!filename)
return 0;
- return ext4fs_find_file1(filename, &ext4fs_root->diropen, &dirnode,
- &filetype);
+ ret = ext4fs_find_file1(filename, &ext4fs_root->diropen, &dirnode,
+ &filetype);
+ if (dirnode)
+ ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+
+ return ret;
}
int ext4fs_size(const char *filename, loff_t *size)
diff --git a/fs/fs.c b/fs/fs.c
index e2915e7..1afa0fb 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -220,7 +220,7 @@
.null_dev_desc_ok = false,
.probe = ext4fs_probe,
.close = ext4fs_close,
- .ls = ext4fs_ls,
+ .ls = fs_ls_generic,
.exists = ext4fs_exists,
.size = ext4fs_size,
.read = ext4_read_file,
@@ -232,7 +232,9 @@
.ln = fs_ln_unsupported,
#endif
.uuid = ext4fs_uuid,
- .opendir = fs_opendir_unsupported,
+ .opendir = ext4fs_opendir,
+ .readdir = ext4fs_readdir,
+ .closedir = ext4fs_closedir,
.unlink = fs_unlink_unsupported,
.mkdir = fs_mkdir_unsupported,
},
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 15fd61a..b8b1f133 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -290,7 +290,8 @@
#define ACPI_MADT_REV_ACPI_3_0 2
#define ACPI_MADT_REV_ACPI_4_0 3
#define ACPI_MADT_REV_ACPI_5_0 3
-#define ACPI_MADT_REV_ACPI_6_0 5
+#define ACPI_MADT_REV_ACPI_6_2 4
+#define ACPI_MADT_REV_ACPI_6_3 5
#define ACPI_MCFG_REV_ACPI_3_0 1
@@ -342,7 +343,10 @@
ACPI_APIC_LX2APIC, /* Processor local x2APIC */
ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */
ACPI_APIC_GICC, /* Generic Interrupt Ctlr CPU i/f */
- ACPI_APIC_GICD /* Generic Interrupt Ctlr Distributor */
+ ACPI_APIC_GICD, /* Generic Interrupt Ctlr Distributor */
+ ACPI_APIC_MSI_FRAME, /* Generic Interrupt MSI Frame */
+ ACPI_APIC_GICR, /* Generic Interrupt Ctlr Redistributor */
+ ACPI_APIC_ITS, /* Interrupt Translation Service */
};
/* MADT: Processor Local APIC Structure */
@@ -386,20 +390,20 @@
u8 lint; /* Local APIC LINT# */
};
-/* flags for acpi_madr_gicc flags word */
+/* flags for acpi_madt_gicc flags word */
enum {
- ACPI_MADRF_ENABLED = BIT(0),
- ACPI_MADRF_PERF = BIT(1),
- ACPI_MADRF_VGIC = BIT(2),
+ ACPI_MADTF_ENABLED = BIT(0),
+ ACPI_MADTF_PERF = BIT(1),
+ ACPI_MADTF_VGIC = BIT(2),
};
/**
- * struct __packed acpi_madr_gicc - GIC CPU interface (type 0xb)
+ * struct __packed acpi_madt_gicc - GIC CPU interface (type 0xb)
*
* This holds information about the Generic Interrupt Controller (GIC) CPU
* interface. See ACPI Spec v6.3 section 5.2.12.14
*/
-struct acpi_madr_gicc {
+struct acpi_madt_gicc {
u8 type;
u8 length;
u16 reserved;
@@ -421,12 +425,12 @@
} __packed;
/**
- * struct __packed acpi_madr_gicc - GIC distributor (type 0xc)
+ * struct __packed acpi_madt_gicc - GIC distributor (type 0xc)
*
* This holds information about the Generic Interrupt Controller (GIC)
* Distributor interface. See ACPI Spec v6.3 section 5.2.12.15
*/
-struct acpi_madr_gicd {
+struct acpi_madt_gicd {
u8 type;
u8 length;
u16 reserved;
@@ -437,6 +441,35 @@
u8 reserved3[3];
} __packed;
+/**
+ * struct __packed acpi_madt_gicr - GIC Redistributor (type 0xe)
+ *
+ * This holds information about the Generic Interrupt Controller (GIC)
+ * Redistributor interface. See ACPI Spec v6.3 section 5.2.12.17
+ */
+struct acpi_madt_gicr {
+ u8 type;
+ u8 length;
+ u16 reserved;
+ u64 discovery_range_base_address;
+ u32 discovery_range_length;
+} __packed;
+
+/**
+ * struct __packed acpi_madt_its - GIC Interrupt Translation Service (type 0xf)
+ *
+ * This holds information about the Interrupt Translation Service (ITS)
+ * Structure. See ACPI Spec v6.3 section 5.2.12.18
+ */
+struct acpi_madt_its {
+ u8 type;
+ u8 length;
+ u16 reserved;
+ u32 gic_its_id;
+ u64 physical_base_address;
+ u32 reserved2;
+} __packed;
+
/* MCFG (PCI Express MMIO config space BAR description table) */
struct acpi_mcfg {
struct acpi_table_header header;
@@ -707,6 +740,8 @@
u32 virt_el2_flags;
} __packed;
+#define GTDT_FLAG_INT_ACTIVE_LOW BIT(1)
+
/**
* struct acpi_bgrt - Boot Graphics Resource Table (BGRT)
*
@@ -797,6 +832,117 @@
u16 line_size;
} __packed;
+/** IORT - IO Remapping Table revision 6
+ * Document number: ARM DEN 0049E.e, Sep 2022
+ */
+struct acpi_table_iort {
+ struct acpi_table_header header;
+ u32 node_count;
+ u32 node_offset;
+ u32 reserved;
+} __packed;
+
+/*
+ * IORT subtables
+ */
+struct acpi_iort_node {
+ u8 type;
+ u16 length;
+ u8 revision;
+ u32 identifier;
+ u32 mapping_count;
+ u32 mapping_offset;
+ char node_data[];
+} __packed;
+
+/* Values for subtable Type above */
+enum acpi_iort_node_type {
+ ACPI_IORT_NODE_ITS_GROUP = 0x00,
+ ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
+ ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
+ ACPI_IORT_NODE_SMMU = 0x03,
+ ACPI_IORT_NODE_SMMU_V3 = 0x04,
+ ACPI_IORT_NODE_PMCG = 0x05,
+ ACPI_IORT_NODE_RMR = 0x06,
+};
+
+/* ITS Group revision 1 */
+struct acpi_iort_its_group {
+ u32 its_count;
+ u32 identifiers[]; /* GIC ITS identifier array */
+} __packed;
+
+/* PCI root complex node revision 2 */
+struct acpi_iort_rc {
+ u64 mem_access_properties;
+ u32 ats_attributes;
+ u32 pci_segment_number;
+ u8 memory_address_size_limit;
+ u8 reserved[3];
+} __packed;
+
+/* SMMUv3 revision 5 */
+struct acpi_iort_smmu_v3 {
+ u64 base_address; /* SMMUv3 base address */
+ u32 flags;
+ u32 reserved;
+ u64 vatos_address;
+ u32 model;
+ u32 event_gsiv;
+ u32 pri_gsiv;
+ u32 gerr_gsiv;
+ u32 sync_gsiv;
+ u32 pxm;
+ u32 id_mapping_index;
+} __packed;
+
+/* Masks for Flags field above */
+#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
+#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3 << 1)
+#define ACPI_IORT_SMMU_V3_PXM_VALID (1 << 3)
+#define ACPI_IORT_SMMU_V3_DEVICEID_VALID (1 << 4)
+
+struct acpi_iort_id_mapping {
+ u32 input_base; /* Lowest value in input range */
+ u32 id_count; /* Number of IDs */
+ u32 output_base; /* Lowest value in output range */
+ u32 output_reference; /* A reference to the output node */
+ u32 flags;
+} __packed;
+
+/* Masks for Flags field above for IORT subtable */
+#define ACPI_IORT_ID_SINGLE_MAPPING (1)
+
+/* Named Component revision 4 */
+struct acpi_iort_named_component {
+ u32 node_flags;
+ u64 memory_properties; /* Memory access properties */
+ u8 memory_address_limit; /* Memory address size limit */
+ char device_name[]; /* Path of namespace object */
+} __packed;
+
+/* Masks for Flags field above */
+#define ACPI_IORT_NC_STALL_SUPPORTED (1)
+#define ACPI_IORT_NC_PASID_BITS (31 << 1)
+
+struct acpi_iort_root_complex {
+ u64 memory_properties; /* Memory access properties */
+ u32 ats_attribute;
+ u32 pci_segment_number;
+ u8 memory_address_limit;/* Memory address size limit */
+ u16 pasid_capabilities; /* PASID Capabilities */
+ u8 reserved; /* Reserved, must be zero */
+ u32 flags; /* Flags */
+} __packed;
+
+/* Masks for ats_attribute field above */
+#define ACPI_IORT_ATS_SUPPORTED (1) /* The root complex ATS support */
+#define ACPI_IORT_PRI_SUPPORTED (1 << 1) /* The root complex PRI support */
+#define ACPI_IORT_PASID_FWD_SUPPORTED (1 << 2) /* The root complex PASID forward support */
+
+/* Masks for pasid_capabilities field above */
+#define ACPI_IORT_PASID_MAX_WIDTH (0x1F) /* Bits 0-4 */
+
/* Tables defined/reserved by ACPI and generated by U-Boot */
enum acpi_tables {
ACPITAB_BERT,
@@ -806,12 +952,14 @@
ACPITAB_ECDT,
ACPITAB_FACS,
ACPITAB_FADT,
+ ACPITAB_GTDT,
ACPITAB_HEST,
ACPITAB_HPET,
ACPITAB_IVRS,
ACPITAB_MADT,
ACPITAB_MCFG,
ACPITAB_NHLT,
+ ACPITAB_PPTT,
ACPITAB_RSDP,
ACPITAB_RSDT,
ACPITAB_SLIT,
@@ -847,6 +995,19 @@
int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);
/**
+ * acpi_create_mcfg_mmconfig() - Create a MCFG table entry
+ *
+ * @mmconfig: Place to put the table
+ * @base: Base address of the ECAM space
+ * @seg_nr: PCI segment number
+ * @start: PCI bus start number
+ * @end: PCI bus end number
+ * Return: size of data written in bytes
+ */
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end);
+
+/**
* acpi_create_dbg2() - Create a DBG2 table
*
* This table describes how to access the debug UART
@@ -914,6 +1075,17 @@
}
/**
+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
+ *
+ * @ctx: Current ACPI context
+ * @dev: Debug UART device to describe
+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
+ * Return: 0 if OK, -ve on error
+ */
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+ uint access_size);
+
+/**
* acpi_write_rsdp() - Write out an RSDP indicating where the ACPI tables are
*
* @rsdp: Address to write RSDP
@@ -944,6 +1116,138 @@
int acpi_fill_csrt(struct acpi_ctx *ctx);
/**
+ * acpi_fill_fadt() - Fill out the body of the FADT
+ *
+ * Must be implemented in SoC specific code or in mainboard code.
+ *
+ * @fadt: Pointer to FADT to update
+ */
+void acpi_fill_fadt(struct acpi_fadt *fadt);
+
+/**
+ * acpi_fill_iort() - Fill out the body of the IORT table
+ *
+ * Should be implemented in SoC specific code.
+ *
+ * @ctx: ACPI context to write to
+ * @offset: Offset from the start of the IORT
+ */
+int acpi_fill_iort(struct acpi_ctx *ctx);
+
+/**
+ * acpi_iort_add_its_group() - Add ITS group node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @its_count: Elements in identifiers
+ * @identifiers: The array of ITS identifiers. These IDs must match the value
+ * used in the Multiple APIC Description Table (MADT) GIC ITS
+ * structure for each relevant ITS unit.
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_its_group(struct acpi_ctx *ctx,
+ const u32 its_count,
+ const u32 *identifiers);
+
+/**
+ * acpi_iort_add_named_component() - Add named component to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @node_flags: Node flags
+ * @memory_properties: Memory properties
+ * @memory_address_limit: Memory address limit
+ * @device_name: ACPI device path
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_named_component(struct acpi_ctx *ctx,
+ const u32 node_flags,
+ const u64 memory_properties,
+ const u8 memory_address_limit,
+ const char *device_name);
+
+/**
+ * acpi_iort_add_rc() - Add PCI root complex node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @mem_access_properties: Memory access properties
+ * @ats_attributes: Support for ATS and its ancillary feature
+ * @pci_segment_number: The PCI segment number, as in MCFG
+ * @memory_address_size_limit: The number of address bits, starting from LSB
+ * @num_mappings: Number of elements in map
+ * @map: ID mappings for this node
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_rc(struct acpi_ctx *ctx,
+ const u64 mem_access_properties,
+ const u32 ats_attributes,
+ const u32 pci_segment_number,
+ const u8 memory_address_size_limit,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map);
+
+/**
+ * acpi_iort_add_smmu_v3() - Add PCI root complex node to IORT table
+ *
+ * Called by SoC specific code within acpi_fill_iort().
+ *
+ * @ctx: ACPI context to write to
+ * @base_address: Base address of SMMU
+ * @flags: SMMUv3 flags
+ * @vatos_address: Optional, set to zero if not supported
+ * @model: Model ID
+ * @event_gsiv: GSIV of the Event interrupt if SPI based
+ * @pri_gsiv: GSIV of the PRI interrupt if SPI based
+ * @gerr_gsiv: GSIV of the GERR interrupt if GSIV based
+ * @sync_gsiv: TGSIV of the Sync interrupt if GSIV based
+ * @pxm: Proximity Domain
+ * @id_mapping_index: If all the SMMU control interrupts are GSIV based,
+ * this field is ignored. Index into the array of ID
+ * mapping otherwise.
+ * @num_mappings: Number of elements in map
+ * @map: ID mappings for this node
+ * @return Offset of table within parent
+ */
+int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
+ const u64 base_address,
+ const u32 flags,
+ const u64 vatos_address,
+ const u32 model,
+ const u32 event_gsiv,
+ const u32 pri_gsiv,
+ const u32 gerr_gsiv,
+ const u32 sync_gsiv,
+ const u32 pxm,
+ const u32 id_mapping_index,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map);
+
+/**
+ * acpi_fill_madt() - Fill out the body of the MADT
+ *
+ * Must be implemented in SoC specific code.
+ *
+ * @madt: The MADT to update
+ * @ctx: ACPI context to write MADT sub-tables to
+ * @return Pointer to the end of tables, where the next tables can be written
+ */
+void *acpi_fill_madt(struct acpi_madt *madt, struct acpi_ctx *ctx);
+
+/**
+ * acpi_write_park() - Installs the ACPI parking protocol.
+ *
+ * Sets up the ACPI parking protocol and installs the spinning code for
+ * secondary CPUs.
+ *
+ * @madt: The MADT to update
+ */
+void acpi_write_park(struct acpi_madt *madt);
+
+/**
* acpi_get_rsdp_addr() - get ACPI RSDP table address
*
* This routine returns the ACPI RSDP table address in the system memory.
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 3aa94d7..16df85b 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -833,6 +833,7 @@
*
* This emits a Processor package header with the required information. The
* caller must complete the information and call acpigen_pop_len() at the end
+ * Deprecated since ACPI 6.0.
*
* @ctx: ACPI context pointer
* @cpuindex: CPU number
@@ -843,6 +844,17 @@
u32 pblock_addr, uint pblock_len);
/**
+ * acpigen_write_processor_device() - Write a Processor device
+ *
+ * Write a device with _HID ACPI0007 identifying a processor.
+ * Replacement for the Processor OpCode.
+ *
+ * @ctx: ACPI context pointer
+ * @cpuindex: CPU number
+ */
+void acpigen_write_processor_device(struct acpi_ctx *ctx, uint cpuindex);
+
+/**
* acpigen_write_processor_package() - Write a package containing the processors
*
* The package containins the name of each processor in the SoC
diff --git a/include/alist.h b/include/alist.h
index 68d268f..b00d9ea 100644
--- a/include/alist.h
+++ b/include/alist.h
@@ -72,6 +72,21 @@
}
/**
+ * alist_calc_index() - Calculate the index of an item in the list
+ *
+ * The returned element number will be -1 if the list is empty or the pointer
+ * pointers to before the list starts.
+ *
+ * If the pointer points to after the last item, the calculated element-number
+ * will be returned, even though it is greater than lst->count
+ *
+ * @lst: alist to check
+ * @ptr: pointer to check
+ * Return: element number of the pointer
+ */
+int alist_calc_index(const struct alist *lst, const void *ptr);
+
+/**
* alist_err() - Check if the alist is still valid
*
* @lst: List to check
@@ -116,7 +131,12 @@
return lst->data + index * lst->obj_size;
}
-/** get an entry as a constant */
+/**
+ * alist_get() - get an entry as a constant
+ *
+ * Use as (to obtain element 2 of the list):
+ * const struct my_struct *ptr = alist_get(lst, 2, struct my_struct)
+ */
#define alist_get(_lst, _index, _struct) \
((const _struct *)alist_get_ptr(_lst, _index))
@@ -151,8 +171,9 @@
* alist_add_placeholder() - Add a new item to the end of the list
*
* @lst: alist to add to
- * Return: Pointer to the newly added position. Note that this is not inited so
- * the caller must copy the requested struct to the returned pointer
+ * Return: Pointer to the newly added position, or NULL if out of memory. Note
+ * that this is not inited so the caller must copy the requested struct to the
+ * returned pointer
*/
void *alist_add_placeholder(struct alist *lst);
@@ -184,7 +205,113 @@
#define alist_add(_lst, _obj) \
((typeof(_obj) *)alist_add_ptr(_lst, &(_obj)))
+/** get next entry as a constant */
+#define alist_next(_lst, _objp) \
+ ((const typeof(_objp))alist_next_ptrd(_lst, _objp))
+
+/** get next entry, which can be written to */
+#define alist_nextw(_lst, _objp) \
+ ((typeof(_objp))alist_next_ptrd(_lst, _objp))
+
+/**
+ * alist_next_ptrd() - Get a pointer to the next list element
+ *
+ * This returns NULL if the requested element is beyond lst->count
+ *
+ * @lst: List to check
+ * @ptr: Pointer to current element (must be valid)
+ * Return: Pointer to next element, or NULL if @ptr is the last
+ */
+const void *alist_next_ptrd(const struct alist *lst, const void *ptr);
+
+/**
+ * alist_chk_ptr() - Check whether a pointer is within a list
+ *
+ * Checks if the pointer points to an existing element of the list. The pointer
+ * must point to the start of an element, either in the list, or just outside of
+ * it. This function is only useful for handling for() loops
+ *
+ * Return: true if @ptr is within the list (0..count-1), else false
+ */
+bool alist_chk_ptr(const struct alist *lst, const void *ptr);
+
+/**
+ * alist_start() - Get the start of the list (first element)
+ *
+ * Note that this will always return ->data even if it is not NULL
+ *
+ * Usage:
+ * const struct my_struct *obj; # 'const' is optional
+ *
+ * alist_start(&lst, struct my_struct)
+ */
+#define alist_start(_lst, _struct) \
+ ((_struct *)(_lst)->data)
+
/**
+ * alist_end() - Get the end of the list (just after last element)
+ *
+ * Usage:
+ * const struct my_struct *obj; # 'const' is optional
+ *
+ * alist_end(&lst, struct my_struct)
+ */
+#define alist_end(_lst, _struct) \
+ ((_struct *)(_lst)->data + (_lst)->count)
+
+/**
+ * alist_for_each() - Iterate over an alist (with constant pointer)
+ *
+ * Use as:
+ * const struct my_struct *obj; # 'const' is optional
+ *
+ * alist_for_each(obj, &lst) {
+ * obj->...
+ * }
+ */
+#define alist_for_each(_pos, _lst) \
+ for (_pos = alist_start(_lst, typeof(*(_pos))); \
+ _pos < alist_end(_lst, typeof(*(_pos))); \
+ _pos++)
+
+/**
+ * alist_for_each_filter() - version which sets up a 'from' pointer too
+ *
+ * This is used for filtering out information in the list. It works by iterating
+ * through the list, copying elements down over the top of elements to be
+ * deleted.
+ *
+ * In this example, 'from' iterates through the list from start to end,, 'to'
+ * also begins at the start, but only increments if the element at 'from' should
+ * be kept. This provides an O(n) filtering operation. Note that
+ * alist_update_end() must be called after the loop, to update the count.
+ *
+ * alist_for_each_filter(from, to, &lst) {
+ * if (from->val != 2)
+ * *to++ = *from;
+ * }
+ * alist_update_end(&lst, to);
+ */
+#define alist_for_each_filter(_pos, _from, _lst) \
+ for (_pos = _from = alist_start(_lst, typeof(*(_pos))); \
+ _pos < alist_end(_lst, typeof(*(_pos))); \
+ _pos++)
+
+/**
+ * alist_update_end() - Set the element count based on a given pointer
+ *
+ * Set the given element as the final one
+ */
+void alist_update_end(struct alist *lst, const void *end);
+
+/**
+ * alist_empty() - Empty an alist
+ *
+ * This removes all entries from the list, without changing the allocated size
+ */
+void alist_empty(struct alist *lst);
+
+/**
* alist_init() - Set up a new object list
*
* Sets up a list of objects, initially empty
@@ -197,6 +324,12 @@
*/
bool alist_init(struct alist *lst, uint obj_size, uint alloc_size);
+/**
+ * alist_init_struct() - Typed version of alist_init()
+ *
+ * Use as:
+ * alist_init(&lst, struct my_struct);
+ */
#define alist_init_struct(_lst, _struct) \
alist_init(_lst, sizeof(_struct), 0)
diff --git a/include/android_ab.h b/include/android_ab.h
index dbf2034..838230e 100644
--- a/include/android_ab.h
+++ b/include/android_ab.h
@@ -18,7 +18,10 @@
#define NUM_SLOTS 2
/**
- * Select the slot where to boot from.
+ * ab_select_slot() - Select the slot where to boot from.
+ *
+ * @dev_desc: Place to store the device description pointer
+ * @part_info: Place to store the partition information
*
* On Android devices with more than one boot slot (multiple copies of the
* kernel and system images) selects which slot should be used to boot from and
@@ -28,11 +31,19 @@
* registered before returning from this function so it isn't selected
* indefinitely.
*
- * @param[in] dev_desc Place to store the device description pointer
- * @param[in] part_info Place to store the partition information
* Return: The slot number (>= 0) on success, or a negative on error
*/
int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info,
bool dec_tries);
+/**
+ * ab_dump_abc() - Dump ABC information for specific partition.
+ *
+ * @dev_desc: Device description pointer
+ * @part_info: Partition information
+ *
+ * Return: 0 on success, or a negative on error
+ */
+int ab_dump_abc(struct blk_desc *dev_desc, struct disk_partition *part_info);
+
#endif /* __ANDROID_AB_H */
diff --git a/include/android_image.h b/include/android_image.h
index d503c98..9682070 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -348,7 +348,7 @@
ulong bootconfig_addr; /* bootconfig image address */
ulong bootconfig_size; /* bootconfig image size */
- u32 kernel_addr; /* physical load addr */
+ ulong kernel_addr; /* physical load addr */
ulong ramdisk_addr; /* physical load addr */
ulong ramdisk_ptr; /* ramdisk address */
ulong dtb_load_addr; /* physical load address for DTB image */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 644a0d7..26277b9 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -21,7 +21,6 @@
#ifndef __ASSEMBLY__
#include <board_f.h>
-#include <cyclic.h>
#include <event_internal.h>
#include <fdtdec.h>
#include <membuff.h>
@@ -544,6 +543,38 @@
#define gd_set_upl(val)
#endif
+#if CONFIG_IS_ENABLED(BLOBLIST)
+#define gd_bloblist() gd->bloblist
+#define gd_set_bloblist(_val) gd->bloblist = (_val)
+#else
+#define gd_bloblist() NULL
+#define gd_set_bloblist(_val)
+#endif
+
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#define gd_bootstage() gd->bootstage
+#else
+#define gd_bootstage() NULL
+#endif
+
+#if CONFIG_IS_ENABLED(TRACE)
+#define gd_trace_buff() gd->trace_buff
+#define gd_trace_size() CONFIG_TRACE_BUFFER_SIZE
+#else
+#define gd_trace_buff() NULL
+#define gd_trace_size() 0
+#endif
+
+#if CONFIG_IS_ENABLED(VIDEO)
+#define gd_video_top() gd->video_top
+#define gd_video_bottom() gd->video_bottom
+#define gd_video_size() (gd->video_top - gd->video_bottom)
+#else
+#define gd_video_top() 0
+#define gd_video_bottom() 0
+#define gd_video_size() 0
+#endif
+
/**
* enum gd_flags - global data flags
*
diff --git a/include/blk.h b/include/blk.h
index 1fc9a5b..488d04c 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -197,7 +197,6 @@
#endif
-#if CONFIG_IS_ENABLED(BLK)
struct udevice;
/* Operations on block devices */
@@ -278,6 +277,8 @@
#endif /* CONFIG_BOUNCE_BUFFER */
};
+#if CONFIG_IS_ENABLED(BLK)
+
/*
* These functions should take struct udevice instead of struct blk_desc,
* but this is convenient for migration to driver model. Add a 'd' prefix
@@ -291,6 +292,8 @@
unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt);
+#endif /* BLK */
+
/**
* blk_read() - Read from a block device
*
@@ -377,23 +380,6 @@
int blk_next_device(struct udevice **devp);
/**
- * blk_create_device() - Create a new block device
- *
- * @parent: Parent of the new device
- * @drv_name: Driver name to use for the block device
- * @name: Name for the device
- * @uclass_id: Interface type (enum uclass_id_t)
- * @devnum: Device number, specific to the interface type, or -1 to
- * allocate the next available number
- * @blksz: Block size of the device in bytes (typically 512)
- * @lba: Total number of blocks of the device
- * @devp: the new device (which has not been probed)
- */
-int blk_create_device(struct udevice *parent, const char *drv_name,
- const char *name, int uclass_id, int devnum, int blksz,
- lbaint_t lba, struct udevice **devp);
-
-/**
* blk_create_devicef() - Create a new named block device
*
* @parent: Parent of the new device
@@ -528,8 +514,10 @@
*/
int blk_get_desc(enum uclass_id uclass_id, int devnum, struct blk_desc **descp);
-#else
+#if !CONFIG_IS_ENABLED(BLK)
+
#include <errno.h>
+
/*
* These functions should take struct udevice instead of struct blk_desc,
* but this is convenient for migration to driver model. Add a 'd' prefix
diff --git a/include/bloblist.h b/include/bloblist.h
index b0706b5..ff32d3f 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -110,6 +110,7 @@
BLOBLISTT_ACPI_TABLES = 4,
BLOBLISTT_TPM_EVLOG = 5,
BLOBLISTT_TPM_CRB_BASE = 6,
+ BLOBLISTT_ACPI_PP = 7,
/* Standard area to allocate blobs used across firmware components */
BLOBLISTT_AREA_FIRMWARE = 0x10,
diff --git a/include/bootstage.h b/include/bootstage.h
index 5779264..3300ca0 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -371,9 +371,10 @@
/**
* bootstage_get_size() - Get the size of the bootstage data
*
+ * @add_strings: true to add the size of attached strings (for stashing)
* Return: size of boostage data in bytes
*/
-int bootstage_get_size(void);
+int bootstage_get_size(bool add_strings);
/**
* bootstage_init() - Prepare bootstage for use
@@ -444,7 +445,7 @@
return 0; /* Pretend to succeed */
}
-static inline int bootstage_get_size(void)
+static inline int bootstage_get_size(bool add_strings)
{
return 0;
}
diff --git a/include/cedit.h b/include/cedit.h
index a31b424..856509f 100644
--- a/include/cedit.h
+++ b/include/cedit.h
@@ -14,6 +14,7 @@
struct abuf;
struct expo;
struct scene;
+struct udevice;
struct video_priv;
struct udevice;
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 9b6f03f..0935493 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -36,10 +36,9 @@
#endif
#define CFG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
"console=ttymxc0,115200\0" \
"fdt_addr=0x18000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
"kernel_addr_r=0x10008000\0" \
"fdt_addr_r=0x13000000\0" \
"ramdisk_addr_r=0x18000000\0" \
diff --git a/include/configs/imx8mp_navqp.h b/include/configs/imx8mp_navqp.h
new file mode 100644
index 0000000..802438a
--- /dev/null
+++ b/include/configs/imx8mp_navqp.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
+ */
+
+#ifndef __IMX8MP_NAVQP_H
+#define __IMX8MP_NAVQP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS \
+ BOOTENV
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
+
+/* 8GB DDR */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x140000000 /* 5 GB */
+
+#endif
diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h
new file mode 100644
index 0000000..5ddc191
--- /dev/null
+++ b/include/configs/imx93_qsb.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __IMX93_QSB_H
+#define __IMX93_QSB_H
+
+#define CFG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CFG_MALLOC_F_ADDR 0x204D0000
+#endif
+
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#endif
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index b370e25..c520c2f 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -18,13 +18,6 @@
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
-#ifdef CONFIG_VIDEO
-#define CFG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-#endif
-
/*
* Address of U-Boot for SPI NOR boot
*/
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 94a9c76..5c58c7b 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -24,6 +24,9 @@
func(USB, usb, 2)
#endif
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE1 0x880000000
+
/*
* This defines all MMC devices, even if the basic variant has no mmc1.
* The non-supported device will be removed from the boot targets during
@@ -39,7 +42,7 @@
#define CFG_ENV_FLAGS_LIST_STATIC \
"board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \
"mlfb:sw,fw_version:sw,seboot_version:sw," \
- "m2_manuel_config:sw," \
+ "m2_manual_config:sw," \
"eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw"
#endif
diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h
index b76e049..fc89efb 100644
--- a/include/configs/khadas-vim3_android.h
+++ b/include/configs/khadas-vim3_android.h
@@ -12,7 +12,7 @@
#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
-#if defined(CONFIG_CMD_AB_SELECT)
+#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB)
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h
index 0ab8ffd..5b2aed1 100644
--- a/include/configs/khadas-vim3l_android.h
+++ b/include/configs/khadas-vim3l_android.h
@@ -12,7 +12,7 @@
#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
-#if defined(CONFIG_CMD_AB_SELECT)
+#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB)
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=logo,start=512K,size=2M,uuid=" LOGO_UUID \
diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h
index fa52026..77364bb 100644
--- a/include/configs/meson64_android.h
+++ b/include/configs/meson64_android.h
@@ -47,13 +47,13 @@
#define AVB_VERIFY_CMD ""
#endif
-#if defined(CONFIG_CMD_AB_SELECT)
+#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB)
#define ANDROIDBOOT_GET_CURRENT_SLOT_CMD "get_current_slot=" \
"if part number mmc ${mmcdev} " CONTROL_PARTITION " control_part_number; " \
"then " \
"echo " CONTROL_PARTITION \
" partition number:${control_part_number};" \
- "ab_select current_slot mmc ${mmcdev}:${control_part_number};" \
+ "bcb ab_select current_slot mmc ${mmcdev}:${control_part_number};" \
"else " \
"echo " CONTROL_PARTITION " partition not found;" \
"fi;\0"
diff --git a/include/configs/odroid_m2.h b/include/configs/odroid_m2.h
new file mode 100644
index 0000000..c5ed42c
--- /dev/null
+++ b/include/configs/odroid_m2.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ODROID_M2_H
+#define __ODROID_M2_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "cramfsaddr=0x0c000000\0"
+
+#include <configs/rk3588_common.h>
+
+#endif
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 2f594bf..cf4fcb9 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -22,6 +22,7 @@
"stderr=serial,vidconsole\0"
#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
func(VIRTIO, virtio, 0) \
func(VIRTIO, virtio, 1) \
func(SCSI, scsi, 0) \
diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
new file mode 100644
index 0000000..aff7816
--- /dev/null
+++ b/include/configs/qemu-sbsa.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 9elements GmbH
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Physical memory map */
+
+/* SECURE_FLASH */
+#define SBSA_SECURE_FLASH_BASE_ADDR 0x00000000
+#define SBSA_SECURE_FLASH_LENGTH 0x10000000
+
+/* FLASH */
+#define SBSA_FLASH_BASE_ADDR 0x10000000
+#define SBSA_FLASH_LENGTH 0x10000000
+
+/* PERIPH */
+#define SBSA_PERIPH_BASE_ADDR 0x40000000
+
+/* GIC_DIST */
+#define SBSA_GIC_DIST_BASE_ADDR 0x40060000
+#define SBSA_GIC_DIST_LENGTH 0x00020000
+
+#define SBSA_GIC_VBASE_ADDR 0x2c020000
+#define SBSA_GIC_VBASE_LENGTH 0x00010000
+
+#define SBSA_GIC_HBASE_ADDR 0x2c010000
+#define SBSA_GIC_HBASE_LENGTH 0x00010000
+
+/* GIC_REDIST */
+#define SBSA_GIC_REDIST_BASE_ADDR 0x40080000
+#define SBSA_GIC_REDIST_LENGTH 0x04000000
+
+/* GIC_ITS */
+#define SBSA_GIC_ITS_BASE_ADDR 0x44081000
+
+/* UART */
+#define SBSA_UART_BASE_ADDR 0x60000000
+#define SBSA_UART_LENGTH 0x00001000
+
+/* SMMU */
+#define SBSA_SMMU_BASE_ADDR 0x60050000
+
+/* SATA */
+#define SBSA_AHCI_BASE_ADDR 0x60100000
+#define SBSA_AHCI_LENGTH 0x00010000
+
+/* xHCI */
+#define SBSA_XHCI_BASE_ADDR 0x60110000
+#define SBSA_XHCI_LENGTH 0x00010000
+
+/* PIO */
+#define SBSA_PIO_BASE_ADDR 0x7fff0000
+#define SBSA_PIO_LENGTH 0x00010000
+
+/* PCIE_MMIO */
+#define SBSA_PCIE_MMIO_BASE_ADDR 0x80000000
+#define SBSA_PCIE_MMIO_LENGTH 0x70000000
+#define SBSA_PCIE_MMIO_END 0xefffffff
+
+/* PCIE_ECAM */
+#define SBSA_PCIE_ECAM_BASE_ADDR 0xf0000000
+#define SBSA_PCIE_ECAM_LENGTH 0x10000000
+#define SBSA_PCIE_ECAM_END 0xffffffff
+
+/* PCIE_MMIO_HIGH */
+#ifdef __ACPI__
+#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000
+#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000
+#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFF
+#else
+#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000ULL
+#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000ULL
+#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFFULL
+#endif
+
+/* MEM */
+#ifdef __ACPI__
+#define SBSA_MEM_BASE_ADDR 0x10000000000
+#else
+#define SBSA_MEM_BASE_ADDR 0x10000000000ULL
+#endif
+
+#define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE 0x1000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 5b0658c..3e3f49a 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -21,8 +21,6 @@
*/
#define CFG_SYS_BOOTMAPSZ SZ_256M
-/* NAND support */
-
/*****************************************************************************/
#ifdef CONFIG_DISTRO_DEFAULTS
/*****************************************************************************/
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index af6dd4a..9cac31b 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -21,10 +21,6 @@
*/
#define CFG_SYS_BOOTMAPSZ SZ_256M
-/* NAND support */
-
-/* Ethernet need */
-
#define STM32MP_FIP_IMAGE_GUID \
EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \
0x75, 0x59, 0xc1, 0x31, 0x42, 0xa5)
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index 0f46671..2797fc6 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -37,16 +37,26 @@
"setenv loadaddr1 && " \
"setenv sblkcnt && " \
"setenv ublkcnt\0" \
- "dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "dh_update_block_to_sf=" /* Erase SPI NOR and install U-Boot from block device */ \
"setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
- "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \
+ "load ${dh_update_iface} ${dh_update_dev} " \
+ "${loadaddr1} /boot/u-boot-spl.stm32 && " \
"env set filesize1 ${filesize} && " \
- "load mmc 0:4 ${loadaddr} /boot/u-boot.itb && " \
+ "load ${dh_update_iface} ${dh_update_dev} " \
+ "${loadaddr} /boot/u-boot.itb && " \
"sf probe && sf erase 0 0x200000 && " \
"sf update ${loadaddr1} 0 ${filesize1} && " \
"sf update ${loadaddr1} 0x40000 ${filesize1} && " \
"sf update ${loadaddr} 0x80000 ${filesize} && " \
"env set filesize1 && env set loadaddr1\0" \
+ "dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "setenv dh_update_iface mmc && " \
+ "setenv dh_update_dev 0:4 && " \
+ "run dh_update_block_to_sf\0" \
+ "dh_update_emmc_to_sf=" /* Erase SPI NOR and install U-Boot from eMMC */ \
+ "setenv dh_update_iface mmc && " \
+ "setenv dh_update_dev 1:4 && " \
+ "run dh_update_block_to_sf\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 26494ae..26b6c1c 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -93,13 +93,13 @@
#define CONTROL_PARTITION "misc"
-#if defined(CONFIG_CMD_AB_SELECT)
+#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB)
#define AB_SELECT_SLOT \
"if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \
"then " \
"echo " CONTROL_PARTITION \
" partition number:${control_part_number};" \
- "ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
+ "bcb ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
"else " \
"echo " CONTROL_PARTITION " partition not found;" \
"exit;" \
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index dc3f41b..64f1234 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -48,6 +48,12 @@
# define BOOT_TARGET_DEVICES_MMC(func)
#endif
+#if defined(CONFIG_USB_STORAGE)
+# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
@@ -85,7 +91,7 @@
"jtag "
#define BOOT_TARGET_DEVICES_USB_DFU(func) \
- func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1)
+ func(USB_DFU, usb_dfu, 0)
#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
@@ -99,7 +105,7 @@
""
#define BOOT_TARGET_DEVICES_USB_THOR(func) \
- func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1)
+ func(USB_THOR, usb_thor, 0)
#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
@@ -118,6 +124,7 @@
BOOT_TARGET_DEVICES_XSPI(func) \
BOOT_TARGET_DEVICES_USB_DFU(func) \
BOOT_TARGET_DEVICES_USB_THOR(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
diff --git a/include/cpu_func.h b/include/cpu_func.h
index 45e8a0a..7e81c43 100644
--- a/include/cpu_func.h
+++ b/include/cpu_func.h
@@ -69,6 +69,20 @@
void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
+/**
+ * noncached_init() - Initialize non-cached memory region
+ *
+ * Initialize non-cached memory area. This memory region will be typically
+ * located right below the malloc() area and mapped uncached in the MMU.
+ *
+ * It is called during the generic post-relocation init sequence.
+ *
+ * Return: 0 if OK
+ */
+int noncached_init(void);
+void noncached_set_region(void);
+
+phys_addr_t noncached_alloc(size_t size, size_t align);
enum {
/* Disable caches (else flush caches but leave them active) */
diff --git a/include/cyclic.h b/include/cyclic.h
index cd95b69..c6c463d 100644
--- a/include/cyclic.h
+++ b/include/cyclic.h
@@ -13,6 +13,7 @@
#include <linux/list.h>
#include <asm/types.h>
+#include <u-boot/schedule.h> // to be removed later
/**
* struct cyclic_info - Information about cyclic execution function
@@ -86,21 +87,6 @@
*/
struct hlist_head *cyclic_get_list(void);
-/**
- * cyclic_run() - Interate over all registered cyclic functions
- *
- * Interate over all registered cyclic functions and if the it's function
- * needs to be executed, then call into these registered functions.
- */
-void cyclic_run(void);
-
-/**
- * schedule() - Schedule all potentially waiting tasks
- *
- * Basically a wrapper for cyclic_run(), pontentially enhanced by some
- * other parts, that need to get handled periodically.
- */
-void schedule(void);
#else
static inline void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
@@ -112,14 +98,6 @@
{
}
-static inline void cyclic_run(void)
-{
-}
-
-static inline void schedule(void)
-{
-}
-
static inline int cyclic_unregister_all(void)
{
return 0;
diff --git a/include/dm/acpi.h b/include/dm/acpi.h
index 3adfe21..d6bc0c0 100644
--- a/include/dm/acpi.h
+++ b/include/dm/acpi.h
@@ -147,6 +147,22 @@
int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx);
/**
+ * fill_madt() - Generate MADT sub-tables for a device
+ *
+ * This is called to create the MADT table. The method should write out
+ * whatever sub-table is needed by this device. It will end up in the
+ * MADT table.
+ *
+ * Note that this is called 'fill' because the entire contents of the
+ * MADT is build by calling this method on all devices.
+ *
+ * @dev: Device to write
+ * @ctx: ACPI context to use
+ * @return 0 if OK, -ve on error
+ */
+ int (*fill_madt)(const struct udevice *dev, struct acpi_ctx *ctx);
+
+ /**
* fill_ssdt() - Generate SSDT code for a device
*
* This is called to create the SSDT code. The method should write out
@@ -232,6 +248,16 @@
int acpi_write_dev_tables(struct acpi_ctx *ctx);
/**
+ * acpi_fill_madt_subtbl() - Generate ACPI tables for MADT
+ *
+ * This is called to create the MADT sub-tables for all devices.
+ *
+ * @ctx: ACPI context to use
+ * Return: 0 if OK, -ve on error
+ */
+int acpi_fill_madt_subtbl(struct acpi_ctx *ctx);
+
+/**
* acpi_fill_ssdt() - Generate ACPI tables for SSDT
*
* This is called to create the SSDT code for all devices.
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 5271e64..270088a 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -139,6 +139,7 @@
UCLASS_SYSCON, /* System configuration device */
UCLASS_SYSINFO, /* Device information from hardware */
UCLASS_SYSRESET, /* System reset device */
+ UCLASS_TCPM, /* TypeC port manager */
UCLASS_TEE, /* Trusted Execution Environment device */
UCLASS_THERMAL, /* Thermal sensor */
UCLASS_TIMER, /* Timer device */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 456eef7..c279304 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -436,6 +436,17 @@
struct udevice **devp);
/**
+ * uclass_try_first_device()- See if there is a device for a uclass
+ *
+ * If the uclass exists, this returns the first device on that uclass, without
+ * probing it. If the uclass does not exist, it gives up
+ *
+ * @id: Uclass ID to check
+ * Return: Pointer to device, if found, else NULL
+ */
+struct udevice *uclass_try_first_device(enum uclass_id id);
+
+/**
* uclass_probe_all() - Probe all devices based on an uclass ID
*
* This function probes all devices associated with a uclass by
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
deleted file mode 100644
index e355363..0000000
--- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774a1 CPG Core Clocks */
-#define R8A774A1_CLK_Z 0
-#define R8A774A1_CLK_Z2 1
-#define R8A774A1_CLK_ZG 2
-#define R8A774A1_CLK_ZTR 3
-#define R8A774A1_CLK_ZTRD2 4
-#define R8A774A1_CLK_ZT 5
-#define R8A774A1_CLK_ZX 6
-#define R8A774A1_CLK_S0D1 7
-#define R8A774A1_CLK_S0D2 8
-#define R8A774A1_CLK_S0D3 9
-#define R8A774A1_CLK_S0D4 10
-#define R8A774A1_CLK_S0D6 11
-#define R8A774A1_CLK_S0D8 12
-#define R8A774A1_CLK_S0D12 13
-#define R8A774A1_CLK_S1D2 14
-#define R8A774A1_CLK_S1D4 15
-#define R8A774A1_CLK_S2D1 16
-#define R8A774A1_CLK_S2D2 17
-#define R8A774A1_CLK_S2D4 18
-#define R8A774A1_CLK_S3D1 19
-#define R8A774A1_CLK_S3D2 20
-#define R8A774A1_CLK_S3D4 21
-#define R8A774A1_CLK_LB 22
-#define R8A774A1_CLK_CL 23
-#define R8A774A1_CLK_ZB3 24
-#define R8A774A1_CLK_ZB3D2 25
-#define R8A774A1_CLK_ZB3D4 26
-#define R8A774A1_CLK_CR 27
-#define R8A774A1_CLK_CRD2 28
-#define R8A774A1_CLK_SD0H 29
-#define R8A774A1_CLK_SD0 30
-#define R8A774A1_CLK_SD1H 31
-#define R8A774A1_CLK_SD1 32
-#define R8A774A1_CLK_SD2H 33
-#define R8A774A1_CLK_SD2 34
-#define R8A774A1_CLK_SD3H 35
-#define R8A774A1_CLK_SD3 36
-#define R8A774A1_CLK_RPC 37
-#define R8A774A1_CLK_RPCD2 38
-#define R8A774A1_CLK_MSO 39
-#define R8A774A1_CLK_HDMI 40
-#define R8A774A1_CLK_CSI0 41
-#define R8A774A1_CLK_CP 42
-#define R8A774A1_CLK_CPEX 43
-#define R8A774A1_CLK_R 44
-#define R8A774A1_CLK_OSC 45
-#define R8A774A1_CLK_CANFD 46
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
deleted file mode 100644
index 1355451..0000000
--- a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774b1 CPG Core Clocks */
-#define R8A774B1_CLK_Z 0
-#define R8A774B1_CLK_ZG 1
-#define R8A774B1_CLK_ZTR 2
-#define R8A774B1_CLK_ZTRD2 3
-#define R8A774B1_CLK_ZT 4
-#define R8A774B1_CLK_ZX 5
-#define R8A774B1_CLK_S0D1 6
-#define R8A774B1_CLK_S0D2 7
-#define R8A774B1_CLK_S0D3 8
-#define R8A774B1_CLK_S0D4 9
-#define R8A774B1_CLK_S0D6 10
-#define R8A774B1_CLK_S0D8 11
-#define R8A774B1_CLK_S0D12 12
-#define R8A774B1_CLK_S1D2 13
-#define R8A774B1_CLK_S1D4 14
-#define R8A774B1_CLK_S2D1 15
-#define R8A774B1_CLK_S2D2 16
-#define R8A774B1_CLK_S2D4 17
-#define R8A774B1_CLK_S3D1 18
-#define R8A774B1_CLK_S3D2 19
-#define R8A774B1_CLK_S3D4 20
-#define R8A774B1_CLK_LB 21
-#define R8A774B1_CLK_CL 22
-#define R8A774B1_CLK_ZB3 23
-#define R8A774B1_CLK_ZB3D2 24
-#define R8A774B1_CLK_CR 25
-#define R8A774B1_CLK_DDR 26
-#define R8A774B1_CLK_SD0H 27
-#define R8A774B1_CLK_SD0 28
-#define R8A774B1_CLK_SD1H 29
-#define R8A774B1_CLK_SD1 30
-#define R8A774B1_CLK_SD2H 31
-#define R8A774B1_CLK_SD2 32
-#define R8A774B1_CLK_SD3H 33
-#define R8A774B1_CLK_SD3 34
-#define R8A774B1_CLK_RPC 35
-#define R8A774B1_CLK_RPCD2 36
-#define R8A774B1_CLK_MSO 37
-#define R8A774B1_CLK_HDMI 38
-#define R8A774B1_CLK_CSI0 39
-#define R8A774B1_CLK_CP 40
-#define R8A774B1_CLK_CPEX 41
-#define R8A774B1_CLK_R 42
-#define R8A774B1_CLK_OSC 43
-#define R8A774B1_CLK_CANFD 44
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
deleted file mode 100644
index 8ad9cd6..0000000
--- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a774c0 CPG Core Clocks */
-#define R8A774C0_CLK_Z2 0
-#define R8A774C0_CLK_ZG 1
-#define R8A774C0_CLK_ZTR 2
-#define R8A774C0_CLK_ZT 3
-#define R8A774C0_CLK_ZX 4
-#define R8A774C0_CLK_S0D1 5
-#define R8A774C0_CLK_S0D3 6
-#define R8A774C0_CLK_S0D6 7
-#define R8A774C0_CLK_S0D12 8
-#define R8A774C0_CLK_S0D24 9
-#define R8A774C0_CLK_S1D1 10
-#define R8A774C0_CLK_S1D2 11
-#define R8A774C0_CLK_S1D4 12
-#define R8A774C0_CLK_S2D1 13
-#define R8A774C0_CLK_S2D2 14
-#define R8A774C0_CLK_S2D4 15
-#define R8A774C0_CLK_S3D1 16
-#define R8A774C0_CLK_S3D2 17
-#define R8A774C0_CLK_S3D4 18
-#define R8A774C0_CLK_S0D6C 19
-#define R8A774C0_CLK_S3D1C 20
-#define R8A774C0_CLK_S3D2C 21
-#define R8A774C0_CLK_S3D4C 22
-#define R8A774C0_CLK_LB 23
-#define R8A774C0_CLK_CL 24
-#define R8A774C0_CLK_ZB3 25
-#define R8A774C0_CLK_ZB3D2 26
-#define R8A774C0_CLK_CR 27
-#define R8A774C0_CLK_CRD2 28
-#define R8A774C0_CLK_SD0H 29
-#define R8A774C0_CLK_SD0 30
-#define R8A774C0_CLK_SD1H 31
-#define R8A774C0_CLK_SD1 32
-#define R8A774C0_CLK_SD3H 33
-#define R8A774C0_CLK_SD3 34
-#define R8A774C0_CLK_RPC 35
-#define R8A774C0_CLK_RPCD2 36
-#define R8A774C0_CLK_ZA2 37
-#define R8A774C0_CLK_ZA8 38
-#define R8A774C0_CLK_Z2D 39
-#define R8A774C0_CLK_MSO 40
-#define R8A774C0_CLK_R 41
-#define R8A774C0_CLK_OSC 42
-#define R8A774C0_CLK_LV0 43
-#define R8A774C0_CLK_LV1 44
-#define R8A774C0_CLK_CSI0 45
-#define R8A774C0_CLK_CP 46
-#define R8A774C0_CLK_CPEX 47
-#define R8A774C0_CLK_CANFD 48
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
deleted file mode 100644
index b2fc1d1..0000000
--- a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* R8A774E1 CPG Core Clocks */
-#define R8A774E1_CLK_Z 0
-#define R8A774E1_CLK_Z2 1
-#define R8A774E1_CLK_ZG 2
-#define R8A774E1_CLK_ZTR 3
-#define R8A774E1_CLK_ZTRD2 4
-#define R8A774E1_CLK_ZT 5
-#define R8A774E1_CLK_ZX 6
-#define R8A774E1_CLK_S0D1 7
-#define R8A774E1_CLK_S0D2 8
-#define R8A774E1_CLK_S0D3 9
-#define R8A774E1_CLK_S0D4 10
-#define R8A774E1_CLK_S0D6 11
-#define R8A774E1_CLK_S0D8 12
-#define R8A774E1_CLK_S0D12 13
-#define R8A774E1_CLK_S1D2 14
-#define R8A774E1_CLK_S1D4 15
-#define R8A774E1_CLK_S2D1 16
-#define R8A774E1_CLK_S2D2 17
-#define R8A774E1_CLK_S2D4 18
-#define R8A774E1_CLK_S3D1 19
-#define R8A774E1_CLK_S3D2 20
-#define R8A774E1_CLK_S3D4 21
-#define R8A774E1_CLK_LB 22
-#define R8A774E1_CLK_CL 23
-#define R8A774E1_CLK_ZB3 24
-#define R8A774E1_CLK_ZB3D2 25
-#define R8A774E1_CLK_ZB3D4 26
-#define R8A774E1_CLK_CR 27
-#define R8A774E1_CLK_CRD2 28
-#define R8A774E1_CLK_SD0H 29
-#define R8A774E1_CLK_SD0 30
-#define R8A774E1_CLK_SD1H 31
-#define R8A774E1_CLK_SD1 32
-#define R8A774E1_CLK_SD2H 33
-#define R8A774E1_CLK_SD2 34
-#define R8A774E1_CLK_SD3H 35
-#define R8A774E1_CLK_SD3 36
-#define R8A774E1_CLK_RPC 37
-#define R8A774E1_CLK_RPCD2 38
-#define R8A774E1_CLK_MSO 39
-#define R8A774E1_CLK_HDMI 40
-#define R8A774E1_CLK_CSI0 41
-#define R8A774E1_CLK_CP 42
-#define R8A774E1_CLK_CPEX 43
-#define R8A774E1_CLK_R 44
-#define R8A774E1_CLK_OSC 45
-#define R8A774E1_CLK_CANFD 46
-
-#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
deleted file mode 100644
index c5955b5..0000000
--- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7790 CPG Core Clocks */
-#define R8A7790_CLK_Z 0
-#define R8A7790_CLK_Z2 1
-#define R8A7790_CLK_ZG 2
-#define R8A7790_CLK_ZTR 3
-#define R8A7790_CLK_ZTRD2 4
-#define R8A7790_CLK_ZT 5
-#define R8A7790_CLK_ZX 6
-#define R8A7790_CLK_ZS 7
-#define R8A7790_CLK_HP 8
-#define R8A7790_CLK_I 9
-#define R8A7790_CLK_B 10
-#define R8A7790_CLK_LB 11
-#define R8A7790_CLK_P 12
-#define R8A7790_CLK_CL 13
-#define R8A7790_CLK_M2 14
-#define R8A7790_CLK_ADSP 15
-#define R8A7790_CLK_IMP 16
-#define R8A7790_CLK_ZB3 17
-#define R8A7790_CLK_ZB3D2 18
-#define R8A7790_CLK_DDR 19
-#define R8A7790_CLK_SDH 20
-#define R8A7790_CLK_SD0 21
-#define R8A7790_CLK_SD1 22
-#define R8A7790_CLK_SD2 23
-#define R8A7790_CLK_SD3 24
-#define R8A7790_CLK_MMC0 25
-#define R8A7790_CLK_MMC1 26
-#define R8A7790_CLK_MP 27
-#define R8A7790_CLK_SSP 28
-#define R8A7790_CLK_SSPRS 29
-#define R8A7790_CLK_QSPI 30
-#define R8A7790_CLK_CP 31
-#define R8A7790_CLK_RCAN 32
-#define R8A7790_CLK_R 33
-#define R8A7790_CLK_OSC 34
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
deleted file mode 100644
index aadd06c..0000000
--- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7791 CPG Core Clocks */
-#define R8A7791_CLK_Z 0
-#define R8A7791_CLK_ZG 1
-#define R8A7791_CLK_ZTR 2
-#define R8A7791_CLK_ZTRD2 3
-#define R8A7791_CLK_ZT 4
-#define R8A7791_CLK_ZX 5
-#define R8A7791_CLK_ZS 6
-#define R8A7791_CLK_HP 7
-#define R8A7791_CLK_I 8
-#define R8A7791_CLK_B 9
-#define R8A7791_CLK_LB 10
-#define R8A7791_CLK_P 11
-#define R8A7791_CLK_CL 12
-#define R8A7791_CLK_M2 13
-#define R8A7791_CLK_ADSP 14
-#define R8A7791_CLK_ZB3 15
-#define R8A7791_CLK_ZB3D2 16
-#define R8A7791_CLK_DDR 17
-#define R8A7791_CLK_SDH 18
-#define R8A7791_CLK_SD0 19
-#define R8A7791_CLK_SD2 20
-#define R8A7791_CLK_SD3 21
-#define R8A7791_CLK_MMC0 22
-#define R8A7791_CLK_MP 23
-#define R8A7791_CLK_SSP 24
-#define R8A7791_CLK_SSPRS 25
-#define R8A7791_CLK_QSPI 26
-#define R8A7791_CLK_CP 27
-#define R8A7791_CLK_RCAN 28
-#define R8A7791_CLK_R 29
-#define R8A7791_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
deleted file mode 100644
index 829c44d..0000000
--- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7792 CPG Core Clocks */
-#define R8A7792_CLK_Z 0
-#define R8A7792_CLK_ZG 1
-#define R8A7792_CLK_ZTR 2
-#define R8A7792_CLK_ZTRD2 3
-#define R8A7792_CLK_ZT 4
-#define R8A7792_CLK_ZX 5
-#define R8A7792_CLK_ZS 6
-#define R8A7792_CLK_HP 7
-#define R8A7792_CLK_I 8
-#define R8A7792_CLK_B 9
-#define R8A7792_CLK_LB 10
-#define R8A7792_CLK_P 11
-#define R8A7792_CLK_CL 12
-#define R8A7792_CLK_M2 13
-#define R8A7792_CLK_IMP 14
-#define R8A7792_CLK_ZB3 15
-#define R8A7792_CLK_ZB3D2 16
-#define R8A7792_CLK_DDR 17
-#define R8A7792_CLK_SD 18
-#define R8A7792_CLK_MP 19
-#define R8A7792_CLK_QSPI 20
-#define R8A7792_CLK_CP 21
-#define R8A7792_CLK_CPEX 22
-#define R8A7792_CLK_RCAN 23
-#define R8A7792_CLK_R 24
-#define R8A7792_CLK_OSC 25
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
deleted file mode 100644
index d1ff646..0000000
--- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7793 CPG Core Clocks */
-#define R8A7793_CLK_Z 0
-#define R8A7793_CLK_ZG 1
-#define R8A7793_CLK_ZTR 2
-#define R8A7793_CLK_ZTRD2 3
-#define R8A7793_CLK_ZT 4
-#define R8A7793_CLK_ZX 5
-#define R8A7793_CLK_ZS 6
-#define R8A7793_CLK_HP 7
-#define R8A7793_CLK_I 8
-#define R8A7793_CLK_B 9
-#define R8A7793_CLK_LB 10
-#define R8A7793_CLK_P 11
-#define R8A7793_CLK_CL 12
-#define R8A7793_CLK_M2 13
-#define R8A7793_CLK_ADSP 14
-#define R8A7793_CLK_ZB3 15
-#define R8A7793_CLK_ZB3D2 16
-#define R8A7793_CLK_DDR 17
-#define R8A7793_CLK_SDH 18
-#define R8A7793_CLK_SD0 19
-#define R8A7793_CLK_SD2 20
-#define R8A7793_CLK_SD3 21
-#define R8A7793_CLK_MMC0 22
-#define R8A7793_CLK_MP 23
-#define R8A7793_CLK_SSP 24
-#define R8A7793_CLK_SSPRS 25
-#define R8A7793_CLK_QSPI 26
-#define R8A7793_CLK_CP 27
-#define R8A7793_CLK_RCAN 28
-#define R8A7793_CLK_R 29
-#define R8A7793_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
deleted file mode 100644
index 6314e23..0000000
--- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7794 CPG Core Clocks */
-#define R8A7794_CLK_Z2 0
-#define R8A7794_CLK_ZG 1
-#define R8A7794_CLK_ZTR 2
-#define R8A7794_CLK_ZTRD2 3
-#define R8A7794_CLK_ZT 4
-#define R8A7794_CLK_ZX 5
-#define R8A7794_CLK_ZS 6
-#define R8A7794_CLK_HP 7
-#define R8A7794_CLK_I 8
-#define R8A7794_CLK_B 9
-#define R8A7794_CLK_LB 10
-#define R8A7794_CLK_P 11
-#define R8A7794_CLK_CL 12
-#define R8A7794_CLK_CP 13
-#define R8A7794_CLK_M2 14
-#define R8A7794_CLK_ADSP 15
-#define R8A7794_CLK_ZB3 16
-#define R8A7794_CLK_ZB3D2 17
-#define R8A7794_CLK_DDR 18
-#define R8A7794_CLK_SDH 19
-#define R8A7794_CLK_SD0 20
-#define R8A7794_CLK_SD2 21
-#define R8A7794_CLK_SD3 22
-#define R8A7794_CLK_MMC0 23
-#define R8A7794_CLK_MP 24
-#define R8A7794_CLK_QSPI 25
-#define R8A7794_CLK_CPEX 26
-#define R8A7794_CLK_RCAN 27
-#define R8A7794_CLK_R 28
-#define R8A7794_CLK_OSC 29
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
deleted file mode 100644
index 92b3e2a..0000000
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7795 CPG Core Clocks */
-#define R8A7795_CLK_Z 0
-#define R8A7795_CLK_Z2 1
-#define R8A7795_CLK_ZR 2
-#define R8A7795_CLK_ZG 3
-#define R8A7795_CLK_ZTR 4
-#define R8A7795_CLK_ZTRD2 5
-#define R8A7795_CLK_ZT 6
-#define R8A7795_CLK_ZX 7
-#define R8A7795_CLK_S0D1 8
-#define R8A7795_CLK_S0D4 9
-#define R8A7795_CLK_S1D1 10
-#define R8A7795_CLK_S1D2 11
-#define R8A7795_CLK_S1D4 12
-#define R8A7795_CLK_S2D1 13
-#define R8A7795_CLK_S2D2 14
-#define R8A7795_CLK_S2D4 15
-#define R8A7795_CLK_S3D1 16
-#define R8A7795_CLK_S3D2 17
-#define R8A7795_CLK_S3D4 18
-#define R8A7795_CLK_LB 19
-#define R8A7795_CLK_CL 20
-#define R8A7795_CLK_ZB3 21
-#define R8A7795_CLK_ZB3D2 22
-#define R8A7795_CLK_CR 23
-#define R8A7795_CLK_CRD2 24
-#define R8A7795_CLK_SD0H 25
-#define R8A7795_CLK_SD0 26
-#define R8A7795_CLK_SD1H 27
-#define R8A7795_CLK_SD1 28
-#define R8A7795_CLK_SD2H 29
-#define R8A7795_CLK_SD2 30
-#define R8A7795_CLK_SD3H 31
-#define R8A7795_CLK_SD3 32
-#define R8A7795_CLK_SSP2 33
-#define R8A7795_CLK_SSP1 34
-#define R8A7795_CLK_SSPRS 35
-#define R8A7795_CLK_RPC 36
-#define R8A7795_CLK_RPCD2 37
-#define R8A7795_CLK_MSO 38
-#define R8A7795_CLK_CANFD 39
-#define R8A7795_CLK_HDMI 40
-#define R8A7795_CLK_CSI0 41
-/* CLK_CSIREF was removed */
-#define R8A7795_CLK_CP 43
-#define R8A7795_CLK_CPEX 44
-#define R8A7795_CLK_R 45
-#define R8A7795_CLK_OSC 46
-
-/* r8a7795 ES2.0 CPG Core Clocks */
-#define R8A7795_CLK_S0D2 47
-#define R8A7795_CLK_S0D3 48
-#define R8A7795_CLK_S0D6 49
-#define R8A7795_CLK_S0D8 50
-#define R8A7795_CLK_S0D12 51
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
deleted file mode 100644
index c0957cf..0000000
--- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7796 CPG Core Clocks */
-#define R8A7796_CLK_Z 0
-#define R8A7796_CLK_Z2 1
-#define R8A7796_CLK_ZR 2
-#define R8A7796_CLK_ZG 3
-#define R8A7796_CLK_ZTR 4
-#define R8A7796_CLK_ZTRD2 5
-#define R8A7796_CLK_ZT 6
-#define R8A7796_CLK_ZX 7
-#define R8A7796_CLK_S0D1 8
-#define R8A7796_CLK_S0D2 9
-#define R8A7796_CLK_S0D3 10
-#define R8A7796_CLK_S0D4 11
-#define R8A7796_CLK_S0D6 12
-#define R8A7796_CLK_S0D8 13
-#define R8A7796_CLK_S0D12 14
-#define R8A7796_CLK_S1D1 15
-#define R8A7796_CLK_S1D2 16
-#define R8A7796_CLK_S1D4 17
-#define R8A7796_CLK_S2D1 18
-#define R8A7796_CLK_S2D2 19
-#define R8A7796_CLK_S2D4 20
-#define R8A7796_CLK_S3D1 21
-#define R8A7796_CLK_S3D2 22
-#define R8A7796_CLK_S3D4 23
-#define R8A7796_CLK_LB 24
-#define R8A7796_CLK_CL 25
-#define R8A7796_CLK_ZB3 26
-#define R8A7796_CLK_ZB3D2 27
-#define R8A7796_CLK_ZB3D4 28
-#define R8A7796_CLK_CR 29
-#define R8A7796_CLK_CRD2 30
-#define R8A7796_CLK_SD0H 31
-#define R8A7796_CLK_SD0 32
-#define R8A7796_CLK_SD1H 33
-#define R8A7796_CLK_SD1 34
-#define R8A7796_CLK_SD2H 35
-#define R8A7796_CLK_SD2 36
-#define R8A7796_CLK_SD3H 37
-#define R8A7796_CLK_SD3 38
-#define R8A7796_CLK_SSP2 39
-#define R8A7796_CLK_SSP1 40
-#define R8A7796_CLK_SSPRS 41
-#define R8A7796_CLK_RPC 42
-#define R8A7796_CLK_RPCD2 43
-#define R8A7796_CLK_MSO 44
-#define R8A7796_CLK_CANFD 45
-#define R8A7796_CLK_HDMI 46
-#define R8A7796_CLK_CSI0 47
-/* CLK_CSIREF was removed */
-#define R8A7796_CLK_CP 49
-#define R8A7796_CLK_CPEX 50
-#define R8A7796_CLK_R 51
-#define R8A7796_CLK_OSC 52
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
deleted file mode 100644
index 7921d78..0000000
--- a/include/dt-bindings/clock/r8a77961-cpg-mssr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77961 CPG Core Clocks */
-#define R8A77961_CLK_Z 0
-#define R8A77961_CLK_Z2 1
-#define R8A77961_CLK_ZR 2
-#define R8A77961_CLK_ZG 3
-#define R8A77961_CLK_ZTR 4
-#define R8A77961_CLK_ZTRD2 5
-#define R8A77961_CLK_ZT 6
-#define R8A77961_CLK_ZX 7
-#define R8A77961_CLK_S0D1 8
-#define R8A77961_CLK_S0D2 9
-#define R8A77961_CLK_S0D3 10
-#define R8A77961_CLK_S0D4 11
-#define R8A77961_CLK_S0D6 12
-#define R8A77961_CLK_S0D8 13
-#define R8A77961_CLK_S0D12 14
-#define R8A77961_CLK_S1D1 15
-#define R8A77961_CLK_S1D2 16
-#define R8A77961_CLK_S1D4 17
-#define R8A77961_CLK_S2D1 18
-#define R8A77961_CLK_S2D2 19
-#define R8A77961_CLK_S2D4 20
-#define R8A77961_CLK_S3D1 21
-#define R8A77961_CLK_S3D2 22
-#define R8A77961_CLK_S3D4 23
-#define R8A77961_CLK_LB 24
-#define R8A77961_CLK_CL 25
-#define R8A77961_CLK_ZB3 26
-#define R8A77961_CLK_ZB3D2 27
-#define R8A77961_CLK_ZB3D4 28
-#define R8A77961_CLK_CR 29
-#define R8A77961_CLK_CRD2 30
-#define R8A77961_CLK_SD0H 31
-#define R8A77961_CLK_SD0 32
-#define R8A77961_CLK_SD1H 33
-#define R8A77961_CLK_SD1 34
-#define R8A77961_CLK_SD2H 35
-#define R8A77961_CLK_SD2 36
-#define R8A77961_CLK_SD3H 37
-#define R8A77961_CLK_SD3 38
-#define R8A77961_CLK_SSP2 39
-#define R8A77961_CLK_SSP1 40
-#define R8A77961_CLK_SSPRS 41
-#define R8A77961_CLK_RPC 42
-#define R8A77961_CLK_RPCD2 43
-#define R8A77961_CLK_MSO 44
-#define R8A77961_CLK_CANFD 45
-#define R8A77961_CLK_HDMI 46
-#define R8A77961_CLK_CSI0 47
-/* CLK_CSIREF was removed */
-#define R8A77961_CLK_CP 49
-#define R8A77961_CLK_CPEX 50
-#define R8A77961_CLK_R 51
-#define R8A77961_CLK_OSC 52
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
deleted file mode 100644
index 6d3b5a9..0000000
--- a/include/dt-bindings/clock/r8a77965-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77965 CPG Core Clocks */
-#define R8A77965_CLK_Z 0
-#define R8A77965_CLK_ZR 1
-#define R8A77965_CLK_ZG 2
-#define R8A77965_CLK_ZTR 3
-#define R8A77965_CLK_ZTRD2 4
-#define R8A77965_CLK_ZT 5
-#define R8A77965_CLK_ZX 6
-#define R8A77965_CLK_S0D1 7
-#define R8A77965_CLK_S0D2 8
-#define R8A77965_CLK_S0D3 9
-#define R8A77965_CLK_S0D4 10
-#define R8A77965_CLK_S0D6 11
-#define R8A77965_CLK_S0D8 12
-#define R8A77965_CLK_S0D12 13
-#define R8A77965_CLK_S1D1 14
-#define R8A77965_CLK_S1D2 15
-#define R8A77965_CLK_S1D4 16
-#define R8A77965_CLK_S2D1 17
-#define R8A77965_CLK_S2D2 18
-#define R8A77965_CLK_S2D4 19
-#define R8A77965_CLK_S3D1 20
-#define R8A77965_CLK_S3D2 21
-#define R8A77965_CLK_S3D4 22
-#define R8A77965_CLK_LB 23
-#define R8A77965_CLK_CL 24
-#define R8A77965_CLK_ZB3 25
-#define R8A77965_CLK_ZB3D2 26
-#define R8A77965_CLK_CR 27
-#define R8A77965_CLK_CRD2 28
-#define R8A77965_CLK_SD0H 29
-#define R8A77965_CLK_SD0 30
-#define R8A77965_CLK_SD1H 31
-#define R8A77965_CLK_SD1 32
-#define R8A77965_CLK_SD2H 33
-#define R8A77965_CLK_SD2 34
-#define R8A77965_CLK_SD3H 35
-#define R8A77965_CLK_SD3 36
-#define R8A77965_CLK_SSP2 37
-#define R8A77965_CLK_SSP1 38
-#define R8A77965_CLK_SSPRS 39
-#define R8A77965_CLK_RPC 40
-#define R8A77965_CLK_RPCD2 41
-#define R8A77965_CLK_MSO 42
-#define R8A77965_CLK_CANFD 43
-#define R8A77965_CLK_HDMI 44
-#define R8A77965_CLK_CSI0 45
-#define R8A77965_CLK_CP 46
-#define R8A77965_CLK_CPEX 47
-#define R8A77965_CLK_R 48
-#define R8A77965_CLK_OSC 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
deleted file mode 100644
index 6145ebe..0000000
--- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77970 CPG Core Clocks */
-#define R8A77970_CLK_Z2 0
-#define R8A77970_CLK_ZR 1
-#define R8A77970_CLK_ZTR 2
-#define R8A77970_CLK_ZTRD2 3
-#define R8A77970_CLK_ZT 4
-#define R8A77970_CLK_ZX 5
-#define R8A77970_CLK_S1D1 6
-#define R8A77970_CLK_S1D2 7
-#define R8A77970_CLK_S1D4 8
-#define R8A77970_CLK_S2D1 9
-#define R8A77970_CLK_S2D2 10
-#define R8A77970_CLK_S2D4 11
-#define R8A77970_CLK_LB 12
-#define R8A77970_CLK_CL 13
-#define R8A77970_CLK_ZB3 14
-#define R8A77970_CLK_ZB3D2 15
-#define R8A77970_CLK_DDR 16
-#define R8A77970_CLK_CR 17
-#define R8A77970_CLK_CRD2 18
-#define R8A77970_CLK_SD0H 19
-#define R8A77970_CLK_SD0 20
-#define R8A77970_CLK_RPC 21
-#define R8A77970_CLK_RPCD2 22
-#define R8A77970_CLK_MSO 23
-#define R8A77970_CLK_CANFD 24
-#define R8A77970_CLK_CSI0 25
-#define R8A77970_CLK_FRAY 26
-#define R8A77970_CLK_CP 27
-#define R8A77970_CLK_CPEX 28
-#define R8A77970_CLK_R 29
-#define R8A77970_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
deleted file mode 100644
index a4c0d76..0000000
--- a/include/dt-bindings/clock/r8a77980-cpg-mssr.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77980 CPG Core Clocks */
-#define R8A77980_CLK_Z2 0
-#define R8A77980_CLK_ZR 1
-#define R8A77980_CLK_ZTR 2
-#define R8A77980_CLK_ZTRD2 3
-#define R8A77980_CLK_ZT 4
-#define R8A77980_CLK_ZX 5
-#define R8A77980_CLK_S0D1 6
-#define R8A77980_CLK_S0D2 7
-#define R8A77980_CLK_S0D3 8
-#define R8A77980_CLK_S0D4 9
-#define R8A77980_CLK_S0D6 10
-#define R8A77980_CLK_S0D12 11
-#define R8A77980_CLK_S0D24 12
-#define R8A77980_CLK_S1D1 13
-#define R8A77980_CLK_S1D2 14
-#define R8A77980_CLK_S1D4 15
-#define R8A77980_CLK_S2D1 16
-#define R8A77980_CLK_S2D2 17
-#define R8A77980_CLK_S2D4 18
-#define R8A77980_CLK_S3D1 19
-#define R8A77980_CLK_S3D2 20
-#define R8A77980_CLK_S3D4 21
-#define R8A77980_CLK_LB 22
-#define R8A77980_CLK_CL 23
-#define R8A77980_CLK_ZB3 24
-#define R8A77980_CLK_ZB3D2 25
-#define R8A77980_CLK_ZB3D4 26
-#define R8A77980_CLK_SD0H 27
-#define R8A77980_CLK_SD0 28
-#define R8A77980_CLK_RPC 29
-#define R8A77980_CLK_RPCD2 30
-#define R8A77980_CLK_MSO 31
-#define R8A77980_CLK_CANFD 32
-#define R8A77980_CLK_CSI0 33
-#define R8A77980_CLK_CP 34
-#define R8A77980_CLK_CPEX 35
-#define R8A77980_CLK_R 36
-#define R8A77980_CLK_OSC 37
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
deleted file mode 100644
index a596a48..0000000
--- a/include/dt-bindings/clock/r8a77990-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77990 CPG Core Clocks */
-#define R8A77990_CLK_Z2 0
-#define R8A77990_CLK_ZR 1
-#define R8A77990_CLK_ZG 2
-#define R8A77990_CLK_ZTR 3
-#define R8A77990_CLK_ZT 4
-#define R8A77990_CLK_ZX 5
-#define R8A77990_CLK_S0D1 6
-#define R8A77990_CLK_S0D3 7
-#define R8A77990_CLK_S0D6 8
-#define R8A77990_CLK_S0D12 9
-#define R8A77990_CLK_S0D24 10
-#define R8A77990_CLK_S1D1 11
-#define R8A77990_CLK_S1D2 12
-#define R8A77990_CLK_S1D4 13
-#define R8A77990_CLK_S2D1 14
-#define R8A77990_CLK_S2D2 15
-#define R8A77990_CLK_S2D4 16
-#define R8A77990_CLK_S3D1 17
-#define R8A77990_CLK_S3D2 18
-#define R8A77990_CLK_S3D4 19
-#define R8A77990_CLK_S0D6C 20
-#define R8A77990_CLK_S3D1C 21
-#define R8A77990_CLK_S3D2C 22
-#define R8A77990_CLK_S3D4C 23
-#define R8A77990_CLK_LB 24
-#define R8A77990_CLK_CL 25
-#define R8A77990_CLK_ZB3 26
-#define R8A77990_CLK_ZB3D2 27
-#define R8A77990_CLK_CR 28
-#define R8A77990_CLK_CRD2 29
-#define R8A77990_CLK_SD0H 30
-#define R8A77990_CLK_SD0 31
-#define R8A77990_CLK_SD1H 32
-#define R8A77990_CLK_SD1 33
-#define R8A77990_CLK_SD3H 34
-#define R8A77990_CLK_SD3 35
-#define R8A77990_CLK_RPC 36
-#define R8A77990_CLK_RPCD2 37
-#define R8A77990_CLK_ZA2 38
-#define R8A77990_CLK_ZA8 39
-#define R8A77990_CLK_Z2D 40
-#define R8A77990_CLK_CANFD 41
-#define R8A77990_CLK_MSO 42
-#define R8A77990_CLK_R 43
-#define R8A77990_CLK_OSC 44
-#define R8A77990_CLK_LV0 45
-#define R8A77990_CLK_LV1 46
-#define R8A77990_CLK_CSI0 47
-#define R8A77990_CLK_CP 48
-#define R8A77990_CLK_CPEX 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
deleted file mode 100644
index fd701c4..0000000
--- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77995 CPG Core Clocks */
-#define R8A77995_CLK_Z2 0
-#define R8A77995_CLK_ZG 1
-#define R8A77995_CLK_ZTR 2
-#define R8A77995_CLK_ZT 3
-#define R8A77995_CLK_ZX 4
-#define R8A77995_CLK_S0D1 5
-#define R8A77995_CLK_S1D1 6
-#define R8A77995_CLK_S1D2 7
-#define R8A77995_CLK_S1D4 8
-#define R8A77995_CLK_S2D1 9
-#define R8A77995_CLK_S2D2 10
-#define R8A77995_CLK_S2D4 11
-#define R8A77995_CLK_S3D1 12
-#define R8A77995_CLK_S3D2 13
-#define R8A77995_CLK_S3D4 14
-#define R8A77995_CLK_S1D4C 15
-#define R8A77995_CLK_S3D1C 16
-#define R8A77995_CLK_S3D2C 17
-#define R8A77995_CLK_S3D4C 18
-#define R8A77995_CLK_LB 19
-#define R8A77995_CLK_CL 20
-#define R8A77995_CLK_ZB3 21
-#define R8A77995_CLK_ZB3D2 22
-#define R8A77995_CLK_CR 23
-#define R8A77995_CLK_CRD2 24
-#define R8A77995_CLK_SD0H 25
-#define R8A77995_CLK_SD0 26
-/* CLK_SSP2 was removed */
-/* CLK_SSP1 was removed */
-#define R8A77995_CLK_RPC 29
-#define R8A77995_CLK_RPCD2 30
-#define R8A77995_CLK_ZA2 31
-#define R8A77995_CLK_ZA8 32
-#define R8A77995_CLK_Z2D 33
-#define R8A77995_CLK_CANFD 34
-#define R8A77995_CLK_MSO 35
-#define R8A77995_CLK_R 36
-#define R8A77995_CLK_OSC 37
-#define R8A77995_CLK_LV0 38
-#define R8A77995_CLK_LV1 39
-#define R8A77995_CLK_CP 40
-#define R8A77995_CLK_CPEX 41
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
deleted file mode 100644
index f1d737c..0000000
--- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779A0 CPG Core Clocks */
-#define R8A779A0_CLK_Z0 0
-#define R8A779A0_CLK_ZX 1
-#define R8A779A0_CLK_Z1 2
-#define R8A779A0_CLK_ZR 3
-#define R8A779A0_CLK_ZS 4
-#define R8A779A0_CLK_ZT 5
-#define R8A779A0_CLK_ZTR 6
-#define R8A779A0_CLK_S1D1 7
-#define R8A779A0_CLK_S1D2 8
-#define R8A779A0_CLK_S1D4 9
-#define R8A779A0_CLK_S1D8 10
-#define R8A779A0_CLK_S1D12 11
-#define R8A779A0_CLK_S3D1 12
-#define R8A779A0_CLK_S3D2 13
-#define R8A779A0_CLK_S3D4 14
-#define R8A779A0_CLK_LB 15
-#define R8A779A0_CLK_CP 16
-#define R8A779A0_CLK_CL 17
-#define R8A779A0_CLK_CL16MCK 18
-#define R8A779A0_CLK_ZB30 19
-#define R8A779A0_CLK_ZB30D2 20
-#define R8A779A0_CLK_ZB30D4 21
-#define R8A779A0_CLK_ZB31 22
-#define R8A779A0_CLK_ZB31D2 23
-#define R8A779A0_CLK_ZB31D4 24
-#define R8A779A0_CLK_SD0H 25
-#define R8A779A0_CLK_SD0 26
-#define R8A779A0_CLK_RPC 27
-#define R8A779A0_CLK_RPCD2 28
-#define R8A779A0_CLK_MSO 29
-#define R8A779A0_CLK_CANFD 30
-#define R8A779A0_CLK_CSI0 31
-#define R8A779A0_CLK_FRAY 32
-#define R8A779A0_CLK_DSI 33
-#define R8A779A0_CLK_VIP 34
-#define R8A779A0_CLK_ADGH 35
-#define R8A779A0_CLK_CNNDSP 36
-#define R8A779A0_CLK_ICU 37
-#define R8A779A0_CLK_ICUD2 38
-#define R8A779A0_CLK_VCBUS 39
-#define R8A779A0_CLK_CBFUSA 40
-#define R8A779A0_CLK_R 41
-#define R8A779A0_CLK_OSC 42
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
deleted file mode 100644
index c34be56..0000000
--- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779f0 CPG Core Clocks */
-
-#define R8A779F0_CLK_ZX 0
-#define R8A779F0_CLK_ZS 1
-#define R8A779F0_CLK_ZT 2
-#define R8A779F0_CLK_ZTR 3
-#define R8A779F0_CLK_S0D2 4
-#define R8A779F0_CLK_S0D3 5
-#define R8A779F0_CLK_S0D4 6
-#define R8A779F0_CLK_S0D2_MM 7
-#define R8A779F0_CLK_S0D3_MM 8
-#define R8A779F0_CLK_S0D4_MM 9
-#define R8A779F0_CLK_S0D2_RT 10
-#define R8A779F0_CLK_S0D3_RT 11
-#define R8A779F0_CLK_S0D4_RT 12
-#define R8A779F0_CLK_S0D6_RT 13
-#define R8A779F0_CLK_S0D3_PER 14
-#define R8A779F0_CLK_S0D6_PER 15
-#define R8A779F0_CLK_S0D12_PER 16
-#define R8A779F0_CLK_S0D24_PER 17
-#define R8A779F0_CLK_S0D2_HSC 18
-#define R8A779F0_CLK_S0D3_HSC 19
-#define R8A779F0_CLK_S0D4_HSC 20
-#define R8A779F0_CLK_S0D6_HSC 21
-#define R8A779F0_CLK_S0D12_HSC 22
-#define R8A779F0_CLK_S0D2_CC 23
-#define R8A779F0_CLK_CL 24
-#define R8A779F0_CLK_CL16M 25
-#define R8A779F0_CLK_CL16M_MM 26
-#define R8A779F0_CLK_CL16M_RT 27
-#define R8A779F0_CLK_CL16M_PER 28
-#define R8A779F0_CLK_CL16M_HSC 29
-#define R8A779F0_CLK_Z0 30
-#define R8A779F0_CLK_Z1 31
-#define R8A779F0_CLK_ZB3 32
-#define R8A779F0_CLK_ZB3D2 33
-#define R8A779F0_CLK_ZB3D4 34
-#define R8A779F0_CLK_SD0H 35
-#define R8A779F0_CLK_SD0 36
-#define R8A779F0_CLK_RPC 37
-#define R8A779F0_CLK_RPCD2 38
-#define R8A779F0_CLK_MSO 39
-#define R8A779F0_CLK_SASYNCRT 40
-#define R8A779F0_CLK_SASYNCPERD1 41
-#define R8A779F0_CLK_SASYNCPERD2 42
-#define R8A779F0_CLK_SASYNCPERD4 43
-#define R8A779F0_CLK_DBGSOC_HSC 44
-#define R8A779F0_CLK_RSW2 45
-#define R8A779F0_CLK_OSC 46
-#define R8A779F0_CLK_ZR 47
-#define R8A779F0_CLK_CPEX 48
-#define R8A779F0_CLK_CBFUSA 49
-#define R8A779F0_CLK_R 50
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
deleted file mode 100644
index 7850cdc..0000000
--- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779g0 CPG Core Clocks */
-
-#define R8A779G0_CLK_ZX 0
-#define R8A779G0_CLK_ZS 1
-#define R8A779G0_CLK_ZT 2
-#define R8A779G0_CLK_ZTR 3
-#define R8A779G0_CLK_S0D2 4
-#define R8A779G0_CLK_S0D3 5
-#define R8A779G0_CLK_S0D4 6
-#define R8A779G0_CLK_S0D1_VIO 7
-#define R8A779G0_CLK_S0D2_VIO 8
-#define R8A779G0_CLK_S0D4_VIO 9
-#define R8A779G0_CLK_S0D8_VIO 10
-#define R8A779G0_CLK_S0D1_VC 11
-#define R8A779G0_CLK_S0D2_VC 12
-#define R8A779G0_CLK_S0D4_VC 13
-#define R8A779G0_CLK_S0D2_MM 14
-#define R8A779G0_CLK_S0D4_MM 15
-#define R8A779G0_CLK_S0D2_U3DG 16
-#define R8A779G0_CLK_S0D4_U3DG 17
-#define R8A779G0_CLK_S0D2_RT 18
-#define R8A779G0_CLK_S0D3_RT 19
-#define R8A779G0_CLK_S0D4_RT 20
-#define R8A779G0_CLK_S0D6_RT 21
-#define R8A779G0_CLK_S0D24_RT 22
-#define R8A779G0_CLK_S0D2_PER 23
-#define R8A779G0_CLK_S0D3_PER 24
-#define R8A779G0_CLK_S0D4_PER 25
-#define R8A779G0_CLK_S0D6_PER 26
-#define R8A779G0_CLK_S0D12_PER 27
-#define R8A779G0_CLK_S0D24_PER 28
-#define R8A779G0_CLK_S0D1_HSC 29
-#define R8A779G0_CLK_S0D2_HSC 30
-#define R8A779G0_CLK_S0D4_HSC 31
-#define R8A779G0_CLK_S0D2_CC 32
-#define R8A779G0_CLK_SVD1_IR 33
-#define R8A779G0_CLK_SVD2_IR 34
-#define R8A779G0_CLK_SVD1_VIP 35
-#define R8A779G0_CLK_SVD2_VIP 36
-#define R8A779G0_CLK_CL 37
-#define R8A779G0_CLK_CL16M 38
-#define R8A779G0_CLK_CL16M_MM 39
-#define R8A779G0_CLK_CL16M_RT 40
-#define R8A779G0_CLK_CL16M_PER 41
-#define R8A779G0_CLK_CL16M_HSC 42
-#define R8A779G0_CLK_Z0 43
-#define R8A779G0_CLK_ZB3 44
-#define R8A779G0_CLK_ZB3D2 45
-#define R8A779G0_CLK_ZB3D4 46
-#define R8A779G0_CLK_ZG 47
-#define R8A779G0_CLK_SD0H 48
-#define R8A779G0_CLK_SD0 49
-#define R8A779G0_CLK_RPC 50
-#define R8A779G0_CLK_RPCD2 51
-#define R8A779G0_CLK_MSO 52
-#define R8A779G0_CLK_CANFD 53
-#define R8A779G0_CLK_CSI 54
-#define R8A779G0_CLK_FRAY 55
-#define R8A779G0_CLK_IPC 56
-#define R8A779G0_CLK_SASYNCRT 57
-#define R8A779G0_CLK_SASYNCPERD1 58
-#define R8A779G0_CLK_SASYNCPERD2 59
-#define R8A779G0_CLK_SASYNCPERD4 60
-#define R8A779G0_CLK_VIOBUS 61
-#define R8A779G0_CLK_VIOBUSD2 62
-#define R8A779G0_CLK_VCBUS 63
-#define R8A779G0_CLK_VCBUSD2 64
-#define R8A779G0_CLK_DSIEXT 65
-#define R8A779G0_CLK_DSIREF 66
-#define R8A779G0_CLK_ADGH 67
-#define R8A779G0_CLK_OSC 68
-#define R8A779G0_CLK_ZR0 69
-#define R8A779G0_CLK_ZR1 70
-#define R8A779G0_CLK_ZR2 71
-#define R8A779G0_CLK_IMPA 72
-#define R8A779G0_CLK_IMPAD4 73
-#define R8A779G0_CLK_CPEX 74
-#define R8A779G0_CLK_CBFUSA 75
-#define R8A779G0_CLK_R 76
-#define R8A779G0_CLK_CP 77
-
-#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h
deleted file mode 100644
index 7ab6cfb..0000000
--- a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a779h0 CPG Core Clocks */
-
-#define R8A779H0_CLK_ZX 0
-#define R8A779H0_CLK_ZD 1
-#define R8A779H0_CLK_ZS 2
-#define R8A779H0_CLK_ZT 3
-#define R8A779H0_CLK_ZTR 4
-#define R8A779H0_CLK_S0D2 5
-#define R8A779H0_CLK_S0D3 6
-#define R8A779H0_CLK_S0D4 7
-#define R8A779H0_CLK_S0D1_VIO 8
-#define R8A779H0_CLK_S0D2_VIO 9
-#define R8A779H0_CLK_S0D4_VIO 10
-#define R8A779H0_CLK_S0D8_VIO 11
-#define R8A779H0_CLK_VIOBUSD1 12
-#define R8A779H0_CLK_VIOBUSD2 13
-#define R8A779H0_CLK_S0D1_VC 14
-#define R8A779H0_CLK_S0D2_VC 15
-#define R8A779H0_CLK_S0D4_VC 16
-#define R8A779H0_CLK_VCBUSD1 17
-#define R8A779H0_CLK_VCBUSD2 18
-#define R8A779H0_CLK_S0D2_MM 19
-#define R8A779H0_CLK_S0D4_MM 20
-#define R8A779H0_CLK_S0D2_U3DG 21
-#define R8A779H0_CLK_S0D4_U3DG 22
-#define R8A779H0_CLK_S0D2_RT 23
-#define R8A779H0_CLK_S0D3_RT 24
-#define R8A779H0_CLK_S0D4_RT 25
-#define R8A779H0_CLK_S0D6_RT 26
-#define R8A779H0_CLK_S0D2_PER 27
-#define R8A779H0_CLK_S0D3_PER 28
-#define R8A779H0_CLK_S0D4_PER 29
-#define R8A779H0_CLK_S0D6_PER 30
-#define R8A779H0_CLK_S0D12_PER 31
-#define R8A779H0_CLK_S0D24_PER 32
-#define R8A779H0_CLK_S0D1_HSC 33
-#define R8A779H0_CLK_S0D2_HSC 34
-#define R8A779H0_CLK_S0D4_HSC 35
-#define R8A779H0_CLK_S0D8_HSC 36
-#define R8A779H0_CLK_SVD1_IR 37
-#define R8A779H0_CLK_SVD2_IR 38
-#define R8A779H0_CLK_IMPAD1 39
-#define R8A779H0_CLK_IMPAD4 40
-#define R8A779H0_CLK_IMPB 41
-#define R8A779H0_CLK_SVD1_VIP 42
-#define R8A779H0_CLK_SVD2_VIP 43
-#define R8A779H0_CLK_CL 44
-#define R8A779H0_CLK_CL16M 45
-#define R8A779H0_CLK_CL16M_MM 46
-#define R8A779H0_CLK_CL16M_RT 47
-#define R8A779H0_CLK_CL16M_PER 48
-#define R8A779H0_CLK_CL16M_HSC 49
-#define R8A779H0_CLK_ZC0 50
-#define R8A779H0_CLK_ZC1 51
-#define R8A779H0_CLK_ZC2 52
-#define R8A779H0_CLK_ZC3 53
-#define R8A779H0_CLK_ZB3 54
-#define R8A779H0_CLK_ZB3D2 55
-#define R8A779H0_CLK_ZB3D4 56
-#define R8A779H0_CLK_ZG 57
-#define R8A779H0_CLK_SD0H 58
-#define R8A779H0_CLK_SD0 59
-#define R8A779H0_CLK_RPC 60
-#define R8A779H0_CLK_RPCD2 61
-#define R8A779H0_CLK_MSO 62
-#define R8A779H0_CLK_CANFD 63
-#define R8A779H0_CLK_CSI 64
-#define R8A779H0_CLK_FRAY 65
-#define R8A779H0_CLK_IPC 66
-#define R8A779H0_CLK_SASYNCRT 67
-#define R8A779H0_CLK_SASYNCPERD1 68
-#define R8A779H0_CLK_SASYNCPERD2 69
-#define R8A779H0_CLK_SASYNCPERD4 70
-#define R8A779H0_CLK_DSIEXT 71
-#define R8A779H0_CLK_DSIREF 72
-#define R8A779H0_CLK_ADGH 73
-#define R8A779H0_CLK_OSC 74
-#define R8A779H0_CLK_ZR0 75
-#define R8A779H0_CLK_ZR1 76
-#define R8A779H0_CLK_ZR2 77
-#define R8A779H0_CLK_RGMII 78
-#define R8A779H0_CLK_CPEX 79
-#define R8A779H0_CLK_CP 80
-#define R8A779H0_CLK_CBFUSA 81
-#define R8A779H0_CLK_R 82
-
-#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h
deleted file mode 100644
index 569a3cc..0000000
--- a/include/dt-bindings/clock/renesas-cpg-mssr.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-
-#define CPG_CORE 0 /* Core Clock */
-#define CPG_MOD 1 /* Module Clock */
-
-#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
deleted file mode 100644
index 580f431..0000000
--- a/include/dt-bindings/power/r8a774a1-sysc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774A1_PD_CA57_CPU0 0
-#define R8A774A1_PD_CA57_CPU1 1
-#define R8A774A1_PD_CA53_CPU0 5
-#define R8A774A1_PD_CA53_CPU1 6
-#define R8A774A1_PD_CA53_CPU2 7
-#define R8A774A1_PD_CA53_CPU3 8
-#define R8A774A1_PD_CA57_SCU 12
-#define R8A774A1_PD_A3VC 14
-#define R8A774A1_PD_3DG_A 17
-#define R8A774A1_PD_3DG_B 18
-#define R8A774A1_PD_CA53_SCU 21
-#define R8A774A1_PD_A2VC0 25
-#define R8A774A1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774A1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h
deleted file mode 100644
index 3737364..0000000
--- a/include/dt-bindings/power/r8a774b1-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774B1_PD_CA57_CPU0 0
-#define R8A774B1_PD_CA57_CPU1 1
-#define R8A774B1_PD_A3VP 9
-#define R8A774B1_PD_CA57_SCU 12
-#define R8A774B1_PD_A3VC 14
-#define R8A774B1_PD_3DG_A 17
-#define R8A774B1_PD_3DG_B 18
-#define R8A774B1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774B1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h
deleted file mode 100644
index 9922d4c..0000000
--- a/include/dt-bindings/power/r8a774c0-sysc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774C0_PD_CA53_CPU0 5
-#define R8A774C0_PD_CA53_CPU1 6
-#define R8A774C0_PD_A3VC 14
-#define R8A774C0_PD_3DG_A 17
-#define R8A774C0_PD_3DG_B 18
-#define R8A774C0_PD_CA53_SCU 21
-#define R8A774C0_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774C0_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h
deleted file mode 100644
index 7edb816..0000000
--- a/include/dt-bindings/power/r8a774e1-sysc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A774E1_PD_CA57_CPU0 0
-#define R8A774E1_PD_CA57_CPU1 1
-#define R8A774E1_PD_CA57_CPU2 2
-#define R8A774E1_PD_CA57_CPU3 3
-#define R8A774E1_PD_CA53_CPU0 5
-#define R8A774E1_PD_CA53_CPU1 6
-#define R8A774E1_PD_CA53_CPU2 7
-#define R8A774E1_PD_CA53_CPU3 8
-#define R8A774E1_PD_A3VP 9
-#define R8A774E1_PD_CA57_SCU 12
-#define R8A774E1_PD_A3VC 14
-#define R8A774E1_PD_3DG_A 17
-#define R8A774E1_PD_3DG_B 18
-#define R8A774E1_PD_3DG_C 19
-#define R8A774E1_PD_3DG_D 20
-#define R8A774E1_PD_CA53_SCU 21
-#define R8A774E1_PD_3DG_E 22
-#define R8A774E1_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A774E1_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
deleted file mode 100644
index bcb4905..0000000
--- a/include/dt-bindings/power/r8a7790-sysc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7790_PD_CA15_CPU0 0
-#define R8A7790_PD_CA15_CPU1 1
-#define R8A7790_PD_CA15_CPU2 2
-#define R8A7790_PD_CA15_CPU3 3
-#define R8A7790_PD_CA7_CPU0 5
-#define R8A7790_PD_CA7_CPU1 6
-#define R8A7790_PD_CA7_CPU2 7
-#define R8A7790_PD_CA7_CPU3 8
-#define R8A7790_PD_CA15_SCU 12
-#define R8A7790_PD_SH_4A 16
-#define R8A7790_PD_RGX 20
-#define R8A7790_PD_CA7_SCU 21
-#define R8A7790_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7790_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
deleted file mode 100644
index 1d20fae..0000000
--- a/include/dt-bindings/power/r8a7791-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7791_PD_CA15_CPU0 0
-#define R8A7791_PD_CA15_CPU1 1
-#define R8A7791_PD_CA15_SCU 12
-#define R8A7791_PD_SH_4A 16
-#define R8A7791_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7791_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
deleted file mode 100644
index dd3a466..0000000
--- a/include/dt-bindings/power/r8a7792-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7792_PD_CA15_CPU0 0
-#define R8A7792_PD_CA15_CPU1 1
-#define R8A7792_PD_CA15_SCU 12
-#define R8A7792_PD_SGX 20
-#define R8A7792_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7792_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
deleted file mode 100644
index 056998c..0000000
--- a/include/dt-bindings/power/r8a7793-sysc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- *
- * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
- */
-
-#define R8A7793_PD_CA15_CPU0 0
-#define R8A7793_PD_CA15_CPU1 1
-#define R8A7793_PD_CA15_SCU 12
-#define R8A7793_PD_SH_4A 16
-#define R8A7793_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7793_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
deleted file mode 100644
index 4d6c708..0000000
--- a/include/dt-bindings/power/r8a7794-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7794_PD_CA7_CPU0 5
-#define R8A7794_PD_CA7_CPU1 6
-#define R8A7794_PD_SH_4A 16
-#define R8A7794_PD_SGX 20
-#define R8A7794_PD_CA7_SCU 21
-
-/* Always-on power area */
-#define R8A7794_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
deleted file mode 100644
index ff53238..0000000
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7795_PD_CA57_CPU0 0
-#define R8A7795_PD_CA57_CPU1 1
-#define R8A7795_PD_CA57_CPU2 2
-#define R8A7795_PD_CA57_CPU3 3
-#define R8A7795_PD_CA53_CPU0 5
-#define R8A7795_PD_CA53_CPU1 6
-#define R8A7795_PD_CA53_CPU2 7
-#define R8A7795_PD_CA53_CPU3 8
-#define R8A7795_PD_A3VP 9
-#define R8A7795_PD_CA57_SCU 12
-#define R8A7795_PD_CR7 13
-#define R8A7795_PD_A3VC 14
-#define R8A7795_PD_3DG_A 17
-#define R8A7795_PD_3DG_B 18
-#define R8A7795_PD_3DG_C 19
-#define R8A7795_PD_3DG_D 20
-#define R8A7795_PD_CA53_SCU 21
-#define R8A7795_PD_3DG_E 22
-#define R8A7795_PD_A3IR 24
-#define R8A7795_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7795_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h
deleted file mode 100644
index 7e6fc06..0000000
--- a/include/dt-bindings/power/r8a7796-sysc.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7796_PD_CA57_CPU0 0
-#define R8A7796_PD_CA57_CPU1 1
-#define R8A7796_PD_CA53_CPU0 5
-#define R8A7796_PD_CA53_CPU1 6
-#define R8A7796_PD_CA53_CPU2 7
-#define R8A7796_PD_CA53_CPU3 8
-#define R8A7796_PD_CA57_SCU 12
-#define R8A7796_PD_CR7 13
-#define R8A7796_PD_A3VC 14
-#define R8A7796_PD_3DG_A 17
-#define R8A7796_PD_3DG_B 18
-#define R8A7796_PD_CA53_SCU 21
-#define R8A7796_PD_A3IR 24
-#define R8A7796_PD_A2VC0 25
-#define R8A7796_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7796_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h
deleted file mode 100644
index 7a38009..0000000
--- a/include/dt-bindings/power/r8a77961-sysc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2019 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77961_PD_CA57_CPU0 0
-#define R8A77961_PD_CA57_CPU1 1
-#define R8A77961_PD_CA53_CPU0 5
-#define R8A77961_PD_CA53_CPU1 6
-#define R8A77961_PD_CA53_CPU2 7
-#define R8A77961_PD_CA53_CPU3 8
-#define R8A77961_PD_CA57_SCU 12
-#define R8A77961_PD_CR7 13
-#define R8A77961_PD_A3VC 14
-#define R8A77961_PD_3DG_A 17
-#define R8A77961_PD_3DG_B 18
-#define R8A77961_PD_CA53_SCU 21
-#define R8A77961_PD_A3IR 24
-#define R8A77961_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77961_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
deleted file mode 100644
index de82d8a..0000000
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Glider bvba
- */
-
-#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77965_PD_CA57_CPU0 0
-#define R8A77965_PD_CA57_CPU1 1
-#define R8A77965_PD_A3VP 9
-#define R8A77965_PD_CA57_SCU 12
-#define R8A77965_PD_CR7 13
-#define R8A77965_PD_A3VC 14
-#define R8A77965_PD_3DG_A 17
-#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77965_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
deleted file mode 100644
index 9dcdbd5..0000000
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Cogent Embedded Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77970_PD_CA53_CPU0 5
-#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CA53_SCU 21
-#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
-#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2DP 28
-#define R8A77970_PD_A2CN 29
-#define R8A77970_PD_A2SC0 30
-#define R8A77970_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77970_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
deleted file mode 100644
index e12c858..0000000
--- a/include/dt-bindings/power/r8a77980-sysc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77980_PD_A2SC2 0
-#define R8A77980_PD_A2SC3 1
-#define R8A77980_PD_A2SC4 2
-#define R8A77980_PD_A2DP0 3
-#define R8A77980_PD_A2DP1 4
-#define R8A77980_PD_CA53_CPU0 5
-#define R8A77980_PD_CA53_CPU1 6
-#define R8A77980_PD_CA53_CPU2 7
-#define R8A77980_PD_CA53_CPU3 8
-#define R8A77980_PD_A2CN 10
-#define R8A77980_PD_A3VIP0 11
-#define R8A77980_PD_A2IR5 12
-#define R8A77980_PD_CR7 13
-#define R8A77980_PD_A2IR4 15
-#define R8A77980_PD_CA53_SCU 21
-#define R8A77980_PD_A2IR0 23
-#define R8A77980_PD_A3IR 24
-#define R8A77980_PD_A3VIP1 25
-#define R8A77980_PD_A3VIP2 26
-#define R8A77980_PD_A2IR1 27
-#define R8A77980_PD_A2IR2 28
-#define R8A77980_PD_A2IR3 29
-#define R8A77980_PD_A2SC0 30
-#define R8A77980_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77980_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
deleted file mode 100644
index 944d85b..0000000
--- a/include/dt-bindings/power/r8a77990-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77990_PD_CA53_CPU0 5
-#define R8A77990_PD_CA53_CPU1 6
-#define R8A77990_PD_CR7 13
-#define R8A77990_PD_A3VC 14
-#define R8A77990_PD_3DG_A 17
-#define R8A77990_PD_3DG_B 18
-#define R8A77990_PD_CA53_SCU 21
-#define R8A77990_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77990_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h
deleted file mode 100644
index f2b3550..0000000
--- a/include/dt-bindings/power/r8a77995-sysc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77995_PD_CA53_CPU0 5
-#define R8A77995_PD_CA53_SCU 21
-
-/* Always-on power area */
-#define R8A77995_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h
deleted file mode 100644
index 57929e4..0000000
--- a/include/dt-bindings/power/r8a779a0-sysc.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779A0_PD_A1E0D0C0 0
-#define R8A779A0_PD_A1E0D0C1 1
-#define R8A779A0_PD_A1E0D1C0 2
-#define R8A779A0_PD_A1E0D1C1 3
-#define R8A779A0_PD_A1E1D0C0 4
-#define R8A779A0_PD_A1E1D0C1 5
-#define R8A779A0_PD_A1E1D1C0 6
-#define R8A779A0_PD_A1E1D1C1 7
-#define R8A779A0_PD_A2E0D0 16
-#define R8A779A0_PD_A2E0D1 17
-#define R8A779A0_PD_A2E1D0 18
-#define R8A779A0_PD_A2E1D1 19
-#define R8A779A0_PD_A3E0 20
-#define R8A779A0_PD_A3E1 21
-#define R8A779A0_PD_3DG_A 24
-#define R8A779A0_PD_3DG_B 25
-#define R8A779A0_PD_A1CNN2 32
-#define R8A779A0_PD_A1DSP0 33
-#define R8A779A0_PD_A2IMP01 34
-#define R8A779A0_PD_A2DP0 35
-#define R8A779A0_PD_A2CV0 36
-#define R8A779A0_PD_A2CV1 37
-#define R8A779A0_PD_A2CV4 38
-#define R8A779A0_PD_A2CV6 39
-#define R8A779A0_PD_A2CN2 40
-#define R8A779A0_PD_A1CNN0 41
-#define R8A779A0_PD_A2CN0 42
-#define R8A779A0_PD_A3IR 43
-#define R8A779A0_PD_A1CNN1 44
-#define R8A779A0_PD_A1DSP1 45
-#define R8A779A0_PD_A2IMP23 46
-#define R8A779A0_PD_A2DP1 47
-#define R8A779A0_PD_A2CV2 48
-#define R8A779A0_PD_A2CV3 49
-#define R8A779A0_PD_A2CV5 50
-#define R8A779A0_PD_A2CV7 51
-#define R8A779A0_PD_A2CN1 52
-#define R8A779A0_PD_A3VIP0 56
-#define R8A779A0_PD_A3VIP1 57
-#define R8A779A0_PD_A3VIP2 58
-#define R8A779A0_PD_A3VIP3 59
-#define R8A779A0_PD_A3ISP01 60
-#define R8A779A0_PD_A3ISP23 61
-
-/* Always-on power area */
-#define R8A779A0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
deleted file mode 100644
index cde1536..0000000
--- a/include/dt-bindings/power/r8a779f0-sysc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779F0_PD_A1E0D0C0 0
-#define R8A779F0_PD_A1E0D0C1 1
-#define R8A779F0_PD_A1E0D1C0 2
-#define R8A779F0_PD_A1E0D1C1 3
-#define R8A779F0_PD_A1E1D0C0 4
-#define R8A779F0_PD_A1E1D0C1 5
-#define R8A779F0_PD_A1E1D1C0 6
-#define R8A779F0_PD_A1E1D1C1 7
-#define R8A779F0_PD_A2E0D0 16
-#define R8A779F0_PD_A2E0D1 17
-#define R8A779F0_PD_A2E1D0 18
-#define R8A779F0_PD_A2E1D1 19
-#define R8A779F0_PD_A3E0 20
-#define R8A779F0_PD_A3E1 21
-
-/* Always-on power area */
-#define R8A779F0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
deleted file mode 100644
index c7b139f..0000000
--- a/include/dt-bindings/power/r8a779g0-sysc.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779G0_PD_A1E0D0C0 0
-#define R8A779G0_PD_A1E0D0C1 1
-#define R8A779G0_PD_A1E0D1C0 2
-#define R8A779G0_PD_A1E0D1C1 3
-#define R8A779G0_PD_A2E0D0 16
-#define R8A779G0_PD_A2E0D1 17
-#define R8A779G0_PD_A3E0 20
-#define R8A779G0_PD_A33DGA 24
-#define R8A779G0_PD_A23DGB 25
-#define R8A779G0_PD_A1DSP0 33
-#define R8A779G0_PD_A2IMP01 34
-#define R8A779G0_PD_A2PSC 35
-#define R8A779G0_PD_A2CV0 36
-#define R8A779G0_PD_A2CV1 37
-#define R8A779G0_PD_A1CNN0 41
-#define R8A779G0_PD_A2CN0 42
-#define R8A779G0_PD_A3IR 43
-#define R8A779G0_PD_A1DSP1 45
-#define R8A779G0_PD_A2IMP23 46
-#define R8A779G0_PD_A2DMA 47
-#define R8A779G0_PD_A2CV2 48
-#define R8A779G0_PD_A2CV3 49
-#define R8A779G0_PD_A1DSP2 53
-#define R8A779G0_PD_A1DSP3 54
-#define R8A779G0_PD_A3VIP0 56
-#define R8A779G0_PD_A3VIP1 57
-#define R8A779G0_PD_A3VIP2 58
-#define R8A779G0_PD_A3ISP0 60
-#define R8A779G0_PD_A3ISP1 61
-#define R8A779G0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779G0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h
deleted file mode 100644
index f27976f..0000000
--- a/include/dt-bindings/power/renesas,r8a779h0-sysc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
-
-/*
- * These power domain indices match the Power Domain Register Numbers (PDR)
- */
-
-#define R8A779H0_PD_A1E0D0C0 0
-#define R8A779H0_PD_A1E0D0C1 1
-#define R8A779H0_PD_A1E0D0C2 2
-#define R8A779H0_PD_A1E0D0C3 3
-#define R8A779H0_PD_A2E0D0 16
-#define R8A779H0_PD_A3CR0 21
-#define R8A779H0_PD_A3CR1 22
-#define R8A779H0_PD_A3CR2 23
-#define R8A779H0_PD_A33DGA 24
-#define R8A779H0_PD_A23DGB 25
-#define R8A779H0_PD_C4 31
-#define R8A779H0_PD_A1DSP0 33
-#define R8A779H0_PD_A2IMP01 34
-#define R8A779H0_PD_A2PSC 35
-#define R8A779H0_PD_A2CV0 36
-#define R8A779H0_PD_A2CV1 37
-#define R8A779H0_PD_A3IMR0 38
-#define R8A779H0_PD_A3IMR1 39
-#define R8A779H0_PD_A3VC 40
-#define R8A779H0_PD_A2CN0 42
-#define R8A779H0_PD_A1CN0 44
-#define R8A779H0_PD_A1DSP1 45
-#define R8A779H0_PD_A2DMA 47
-#define R8A779H0_PD_A2CV2 48
-#define R8A779H0_PD_A2CV3 49
-#define R8A779H0_PD_A3IMR2 50
-#define R8A779H0_PD_A3IMR3 51
-#define R8A779H0_PD_A3PCI 52
-#define R8A779H0_PD_A2PCIPHY 53
-#define R8A779H0_PD_A3VIP0 56
-#define R8A779H0_PD_A3VIP2 58
-#define R8A779H0_PD_A3ISP0 60
-#define R8A779H0_PD_A3DUL 62
-
-/* Always-on power area */
-#define R8A779H0_PD_ALWAYS_ON 64
-
-#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */
diff --git a/include/expo.h b/include/expo.h
index c235fa2..3c383d2 100644
--- a/include/expo.h
+++ b/include/expo.h
@@ -16,6 +16,26 @@
#include <cli.h>
/**
+ * enum expo_id_t - standard expo IDs
+ *
+ * These are assumed to be in use at all times. Expos should use IDs starting
+ * from EXPOID_BASE_ID,
+ *
+ * @EXPOID_NONE: Not used, invalid ID 0
+ * @EXPOID_SAVE: User has requested that the expo data be saved
+ * @EXPOID_DISCARD: User has requested that the expo data be discarded
+ * @EXPOID_BASE_ID: First ID which can be used for expo objects
+ */
+enum expo_id_t {
+ EXPOID_NONE,
+
+ EXPOID_SAVE,
+ EXPOID_DISCARD,
+
+ EXPOID_BASE_ID = 5,
+};
+
+/**
* enum expoact_type - types of actions reported by the expo
*
* @EXPOACT_NONE: no action
@@ -59,11 +79,14 @@
* @font_size: Default font size for all text
* @menu_inset: Inset width (on each side and top/bottom) for menu items
* @menuitem_gap_y: Gap between menu items in pixels
+ * @menu_title_margin_x: Gap between right side of menu title and left size of
+ * menu label
*/
struct expo_theme {
u32 font_size;
u32 menu_inset;
u32 menuitem_gap_y;
+ u32 menu_title_margin_x;
};
/**
@@ -307,6 +330,7 @@
* @desc_id: ID of text object to use as the description text
* @preview_id: ID of the preview object, or 0 if none
* @flags: Flags for this item
+ * @value: Value for this item, or INT_MAX to use sequence
* @sibling: Node to link this item to its siblings
*/
struct scene_menitem {
@@ -317,6 +341,7 @@
uint desc_id;
uint preview_id;
uint flags;
+ int value;
struct list_head sibling;
};
@@ -342,6 +367,15 @@
};
/**
+ * struct expo_arrange_info - Information used when arranging a scene
+ *
+ * @label_width: Maximum width of labels in scene
+ */
+struct expo_arrange_info {
+ int label_width;
+};
+
+/**
* expo_new() - create a new expo
*
* Allocates a new expo
@@ -507,15 +541,6 @@
int scene_set_open(struct scene *scn, uint id, bool open);
/**
- * scene_title_set() - set the scene title
- *
- * @scn: Scene to update
- * @title_id: Title ID to set
- * Returns: 0 if OK
- */
-int scene_title_set(struct scene *scn, uint title_id);
-
-/**
* scene_obj_count() - Count the number of objects in a scene
*
* @scn: Scene to check
@@ -737,4 +762,12 @@
*/
int expo_build(ofnode root, struct expo **expp);
+/**
+ * cb_expo_build() - Build an expo for coreboot CMOS RAM
+ *
+ * @expp: Returns the expo created
+ * Return: 0 if OK, -ve on error
+ */
+int cb_expo_build(struct expo **expp);
+
#endif /*__EXPO_H */
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 41f9eb8..fe3fb30 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -27,6 +27,7 @@
#ifndef __EXT4__
#define __EXT4__
#include <ext_common.h>
+#include <fs.h>
struct disk_partition;
@@ -218,4 +219,7 @@
void ext_cache_init(struct ext_block_cache *cache);
void ext_cache_fini(struct ext_block_cache *cache);
int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size);
+int ext4fs_opendir(const char *dirname, struct fs_dir_stream **dirsp);
+int ext4fs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+void ext4fs_closedir(struct fs_dir_stream *dirs);
#endif
diff --git a/include/ext_common.h b/include/ext_common.h
index b09bbde..6e17fbd 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -173,20 +173,38 @@
__le32 bg_reserved;
};
-/* The ext2 inode. */
+/**
+ * struct ext2_inode - ext2 inode
+ *
+ * For details see Linux file
+ * Documentation/filesystems/ext4/inodes.rst.
+ */
struct ext2_inode {
+ /** @mode: file mode */
__le16 mode;
+ /** @uid: lower 16 bits of owner UID */
__le16 uid;
+ /** @size: lower 32 bits of file size */
__le32 size;
+ /** @atime: last access time */
__le32 atime;
+ /** @ctime: last change time */
__le32 ctime;
+ /** @mtime: last modification time */
__le32 mtime;
+ /** @dtime: deletion time */
__le32 dtime;
+ /** @gid: lower 16 bits of group ID */
__le16 gid;
+ /** @nlinks: number of hard links */
__le16 nlinks;
- __le32 blockcnt; /* Blocks of either 512 or block_size bytes */
+ /** @blockcnt: lower 32 bit of block count */
+ __le32 blockcnt;
+ /** @flags: inode flags */
__le32 flags;
+ /** @osd1: operating system specific data */
__le32 osd1;
+ /** @b: block map or extent tree */
union {
struct datablocks {
__le32 dir_blocks[INDIRECT_BLOCKS];
@@ -197,10 +215,19 @@
char symlink[60];
char inline_data[60];
} b;
+ /** @version: file version (for NFS) */
__le32 version;
+ /** @acl: lower 32 bit of extended attribute block */
__le32 acl;
- __le32 size_high; /* previously dir_acl, but never used */
+ /** @size_high - dir_acl on ext2/3, upper 32 size bits on ext4
+ *
+ * In ext2/3 this field was named i_dir_acl, though it was usually set
+ * to zero and never used.
+ */
+ __le32 size_high;
+ /** @fragment_addr - (obsolete) fragment address */
__le32 fragment_addr;
+ /** @osd2: operating system specific data */
__le32 osd2[3];
};
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 741e236..9447a64 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -202,7 +202,8 @@
*
* This function is called if CONFIG_BOARD_RNG_SEED is set, and must
* be provided by the board. It should return, via @buf, some suitable
- * seed value to pass to the kernel.
+ * seed value to pass to the kernel. Seed size could be set in a decimal
+ * environment variable rng_seed_size and it defaults to 64 bytes.
*
* @param buf A struct abuf for returning the seed and its size.
* @return 0 if ok, negative on error.
diff --git a/include/fs.h b/include/fs.h
index ef540e7..6372756 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -25,7 +25,7 @@
* do_fat_fsload - Run the fatload command
*
* @cmdtp: Command information for fatload
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
@@ -37,7 +37,7 @@
* do_ext2load - Run the ext2load command
*
* @cmdtp: Command information for ext2load
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
@@ -145,7 +145,7 @@
* @offset: offset in the file from where to start reading
* @len: the number of bytes to read. Use 0 to read entire file.
* @actread: returns the actual number of bytes read
- * Return: 0 if OK with valid *actread, -1 on error conditions
+ * Return: 0 if OK with valid @actread, -1 on error conditions
*/
int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actread);
@@ -160,7 +160,7 @@
* @offset: offset in the file from where to start writing
* @len: the number of bytes to write
* @actwrite: returns the actual number of bytes written
- * Return: 0 if OK with valid *actwrite, -1 on error conditions
+ * Return: 0 if OK with valid @actwrite, -1 on error conditions
*/
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite);
@@ -186,57 +186,73 @@
unsigned int type;
/** @size: file size */
loff_t size;
- /** @flags: attribute flags (FS_ATTR_*) */
+ /** @attr: attribute flags (FS_ATTR_*) */
u32 attr;
- /** create_time: time of creation */
+ /** @create_time: time of creation */
struct rtc_time create_time;
- /** access_time: time of last access */
+ /** @access_time: time of last access */
struct rtc_time access_time;
- /** change_time: time of last modification */
+ /** @change_time: time of last modification */
struct rtc_time change_time;
- /** name: file name */
+ /** @name: file name */
char name[FS_DIRENT_NAME_LEN];
};
-/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */
+/**
+ * struct fs_dir_stream - Structure representing an opened directory
+ *
+ * Struct fs_dir_stream should be treated opaque to the user of fs layer.
+ * The fields @desc and @part are used by the fs layer.
+ * File system drivers pass additional private fields with the pointers
+ * to this structure.
+ *
+ * @desc: block device descriptor
+ * @part: partition number
+ */
struct fs_dir_stream {
- /* private to fs. layer: */
struct blk_desc *desc;
int part;
};
-/*
+/**
* fs_opendir - Open a directory
*
- * @filename: the path to directory to open
- * Return: a pointer to the directory stream or NULL on error and errno
- * set appropriately
+ * .. note::
+ * The returned struct fs_dir_stream should be treated opaque to the
+ * user of the fs layer.
+ *
+ * @filename: path to the directory to open
+ * Return:
+ * A pointer to the directory stream or NULL on error and errno set
+ * appropriately
*/
struct fs_dir_stream *fs_opendir(const char *filename);
-/*
+/**
* fs_readdir - Read the next directory entry in the directory stream.
*
- * Works in an analogous way to posix readdir(). The previously returned
- * directory entry is no longer valid after calling fs_readdir() again.
+ * fs_readir works in an analogous way to posix readdir().
+ * The previously returned directory entry is no longer valid after calling
+ * fs_readdir() again.
* After fs_closedir() is called, the returned directory entry is no
* longer valid.
*
* @dirs: the directory stream
- * Return: the next directory entry (only valid until next fs_readdir() or
- * fs_closedir() call, do not attempt to free()) or NULL if the end of
- * the directory is reached.
+ * Return:
+ * the next directory entry (only valid until next fs_readdir() or
+ * fs_closedir() call, do not attempt to free()) or NULL if the end of
+ * the directory is reached.
*/
struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs);
-/*
+/**
* fs_closedir - close a directory stream
*
* @dirs: the directory stream
*/
void fs_closedir(struct fs_dir_stream *dirs);
-/*
+/**
* fs_unlink - delete a file or directory
*
* If a given name is a directory, it will be deleted only if it's empty
@@ -246,7 +262,7 @@
*/
int fs_unlink(const char *filename);
-/*
+/**
* fs_mkdir - Create a directory
*
* @filename: Name of directory to create
@@ -292,7 +308,7 @@
* do_fs_types - List supported filesystems.
*
* @cmdtp: Command information for fstypes
- * @flag: Command flags (CMD_FLAG_...)
+ * @flag: Command flags (CMD_FLAG\_...)
* @argc: Number of arguments
* @argv: List of arguments
* Return: result (see enum command_ret_t)
diff --git a/include/irq.h b/include/irq.h
index 5638c10..0fbc1a5 100644
--- a/include/irq.h
+++ b/include/irq.h
@@ -200,6 +200,20 @@
*/
int irq_read_and_clear(struct irq *irq);
+/**
+ * irq_get_interrupt_parent() - returns the interrupt parent
+ *
+ * Walks the devicetree and returns the interrupt parent's ofnode
+ * for the specified device.
+ *
+ * @dev: device
+ * @interrupt_parent: The interrupt parent's ofnode'
+ * Return: 0 success, or error value
+ *
+ */
+int irq_get_interrupt_parent(const struct udevice *dev,
+ struct udevice **interrupt_parent);
+
struct phandle_2_arg;
/**
* irq_get_by_phandle() - Get an irq by its phandle information (of-platadata)
diff --git a/include/irq_func.h b/include/irq_func.h
index c7c4bab..fb2c540 100644
--- a/include/irq_func.h
+++ b/include/irq_func.h
@@ -10,6 +10,7 @@
#define __IRQ_FUNC_H
struct pt_regs;
+struct cmd_tbl;
typedef void (interrupt_handler_t)(void *arg);
@@ -23,4 +24,7 @@
void enable_interrupts(void);
int disable_interrupts(void);
+/* Implemented in $(CPU)/interrupts.c */
+int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
#endif
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 1ae586b..b8b207f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -182,15 +182,15 @@
/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT7 BIT(7)
+/* Status Register 3 bits. */
+#define SR3_WPS BIT(2)
+
/*
* Maximum number of flashes that can be connected
* in stacked/parallel configuration
*/
#define SNOR_FLASH_CNT_MAX 2
-/* Status Register 3 bits. */
-#define SR3_WPS BIT(2)
-
/* For Cypress flash. */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
@@ -308,7 +308,7 @@
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_SOFT_RESET = BIT(7),
SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
-#if defined(CONFIG_SPI_ADVANCE)
+#if defined(CONFIG_SPI_STACKED_PARALLEL)
SNOR_F_HAS_STACKED = BIT(9),
SNOR_F_HAS_PARALLEL = BIT(10),
#else
diff --git a/include/lmb.h b/include/lmb.h
index e46abf4..2201d6f 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -14,6 +14,9 @@
* Copyright (C) 2001 Peter Bergner, IBM Corp.
*/
+#define LMB_ALLOC_ANYWHERE 0
+#define LMB_ALIST_INITIAL_SIZE 4
+
/**
* enum lmb_flags - definition of memory region attributes
* @LMB_NONE: no special request
@@ -95,32 +98,6 @@
phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size);
phys_size_t lmb_get_free_size(phys_addr_t addr);
-/**
- * lmb_alloc_flags() - Allocate memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter.
- *
- * Return: base address on success, 0 on error
- */
-phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags);
-
-/**
- * lmb_alloc_base_flags() - Allocate specified memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @max_addr: Maximum address of the requested region
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter. The max_addr parameter is used to specify the maximum address
- * below which the requested region should be allocated.
- *
- * Return: base address on success, 0 on error
- */
phys_addr_t lmb_alloc_base_flags(phys_size_t size, ulong align,
phys_addr_t max_addr, uint flags);
diff --git a/include/log.h b/include/log.h
index bf81a27..4f6d6a2 100644
--- a/include/log.h
+++ b/include/log.h
@@ -106,6 +106,8 @@
LOGC_EXPO,
/** @LOGC_CONSOLE: Related to the console and stdio */
LOGC_CONSOLE,
+ /** @LOGC_TEST: Related to testing */
+ LOGC_TEST,
/** @LOGC_COUNT: Number of log categories */
LOGC_COUNT,
/** @LOGC_END: Sentinel value for lists of log categories */
diff --git a/include/malloc.h b/include/malloc.h
index 07d3e90..9e0be48 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -981,6 +981,14 @@
extern ulong mem_malloc_end;
extern ulong mem_malloc_brk;
+/**
+ * mem_malloc_init() - Set up the malloc() pool
+ *
+ * Sets the region of memory to be used for all future calls to malloc(), etc.
+ *
+ * @start: Start address
+ * @size: Size in bytes
+ */
void mem_malloc_init(ulong start, ulong size);
#ifdef __cplusplus
diff --git a/include/mux.h b/include/mux.h
index e5deaba..cbb1c33 100644
--- a/include/mux.h
+++ b/include/mux.h
@@ -117,40 +117,40 @@
int dm_mux_init(void);
#else
-unsigned int mux_control_states(struct mux_control *mux)
+static inline unsigned int mux_control_states(struct mux_control *mux)
{
return -ENOSYS;
}
-int __must_check mux_control_select(struct mux_control *mux,
- unsigned int state)
+static inline int __must_check mux_control_select(struct mux_control *mux,
+ unsigned int state)
{
return -ENOSYS;
}
#define mux_control_try_select(mux, state) mux_control_select(mux, state)
-int mux_control_deselect(struct mux_control *mux)
+static inline int mux_control_deselect(struct mux_control *mux)
{
return -ENOSYS;
}
-struct mux_control *mux_control_get(struct udevice *dev, const char *mux_name)
+static inline struct mux_control *mux_control_get(struct udevice *dev, const char *mux_name)
{
return NULL;
}
-void mux_control_put(struct mux_control *mux)
+static inline void mux_control_put(struct mux_control *mux)
{
}
-struct mux_control *devm_mux_control_get(struct udevice *dev,
- const char *mux_name)
+static inline struct mux_control *devm_mux_control_get(struct udevice *dev,
+ const char *mux_name)
{
return NULL;
}
-int dm_mux_init(void)
+static inline int dm_mux_init(void)
{
return -ENOSYS;
}
diff --git a/include/net-common.h b/include/net-common.h
new file mode 100644
index 0000000..fd7c5e7
--- /dev/null
+++ b/include/net-common.h
@@ -0,0 +1,509 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NET_COMMON_H__
+#define __NET_COMMON_H__
+
+#include <asm/cache.h>
+#include <command.h>
+#include <env.h>
+#include <hexdump.h>
+#include <linux/if_ether.h>
+#include <linux/types.h>
+#include <rand.h>
+#include <time.h>
+
+#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */
+
+/*
+ * The number of receive packet buffers, and the required packet buffer
+ * alignment in memory.
+ *
+ */
+#define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER
+#define PKTALIGN ARCH_DMA_MINALIGN
+
+/* IPv4 addresses are always 32 bits in size */
+struct in_addr {
+ __be32 s_addr;
+};
+
+#define PROT_IP 0x0800 /* IP protocol */
+#define PROT_ARP 0x0806 /* IP ARP protocol */
+#define PROT_WOL 0x0842 /* ether-wake WoL protocol */
+#define PROT_RARP 0x8035 /* IP ARP protocol */
+#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
+#define PROT_IPV6 0x86dd /* IPv6 over bluebook */
+#define PROT_PPP_SES 0x8864 /* PPPoE session messages */
+#define PROT_NCSI 0x88f8 /* NC-SI control packets */
+
+#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
+#define IPPROTO_TCP 6 /* Transmission Control Protocol */
+#define IPPROTO_UDP 17 /* User Datagram Protocol */
+
+#define IP_OFFS 0x1fff /* ip offset *= 8 */
+#define IP_FLAGS 0xe000 /* first 3 bits */
+#define IP_FLAGS_RES 0x8000 /* reserved */
+#define IP_FLAGS_DFRAG 0x4000 /* don't fragments */
+#define IP_FLAGS_MFRAG 0x2000 /* more fragments */
+
+#define IP_HDR_SIZE (sizeof(struct ip_hdr))
+
+#define IP_MIN_FRAG_DATAGRAM_SIZE (IP_HDR_SIZE + 8)
+
+/*
+ * Internet Protocol (IP) + UDP header.
+ */
+struct ip_udp_hdr {
+ u8 ip_hl_v; /* header length and version */
+ u8 ip_tos; /* type of service */
+ u16 ip_len; /* total length */
+ u16 ip_id; /* identification */
+ u16 ip_off; /* fragment offset field */
+ u8 ip_ttl; /* time to live */
+ u8 ip_p; /* protocol */
+ u16 ip_sum; /* checksum */
+ struct in_addr ip_src; /* Source IP address */
+ struct in_addr ip_dst; /* Destination IP address */
+ u16 udp_src; /* UDP source port */
+ u16 udp_dst; /* UDP destination port */
+ u16 udp_len; /* Length of UDP packet */
+ u16 udp_xsum; /* Checksum */
+} __attribute__((packed));
+
+#define IP_UDP_HDR_SIZE (sizeof(struct ip_udp_hdr))
+#define UDP_HDR_SIZE (IP_UDP_HDR_SIZE - IP_HDR_SIZE)
+
+/* Number of packets processed together */
+#define ETH_PACKETS_BATCH_RECV 32
+
+/* ARP hardware address length */
+#define ARP_HLEN 6
+/*
+ * The size of a MAC address in string form, each digit requires two chars
+ * and five separator characters to form '00:00:00:00:00:00'.
+ */
+#define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1)
+
+#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */
+
+# define ARP_ETHER 1 /* Ethernet hardware address */
+
+/*
+ * Maximum packet size; used to allocate packet storage. Use
+ * the maxium Ethernet frame size as specified by the Ethernet
+ * standard including the 802.1Q tag (VLAN tagging).
+ * maximum packet size = 1522
+ * maximum packet size and multiple of 32 bytes = 1536
+ */
+#define PKTSIZE 1522
+#ifndef CONFIG_DM_DSA
+#define PKTSIZE_ALIGN 1536
+#else
+/* Maximum DSA tagging overhead (headroom and/or tailroom) */
+#define DSA_MAX_OVR 256
+#define PKTSIZE_ALIGN (1536 + DSA_MAX_OVR)
+#endif
+
+/*
+ * Maximum receive ring size; that is, the number of packets
+ * we can buffer before overflow happens. Basically, this just
+ * needs to be enough to prevent a packet being discarded while
+ * we are processing the previous one.
+ * Used only in drivers/net/mvgbe.c.
+ */
+#define RINGSZ 4
+#define RINGSZ_LOG2 2
+
+extern int net_restart_wrap; /* Tried all network devices */
+extern uchar *net_rx_packets[PKTBUFSRX]; /* Receive packets */
+extern const u8 net_bcast_ethaddr[ARP_HLEN]; /* Ethernet broadcast address */
+extern char net_boot_file_name[1024];/* Boot File name */
+extern struct in_addr net_ip; /* Our IP addr (0 = unknown) */
+/* Indicates whether the pxe path prefix / config file was specified in dhcp option */
+extern char *pxelinux_configfile;
+
+/**
+ * compute_ip_checksum() - Compute IP checksum
+ *
+ * @addr: Address to check (must be 16-bit aligned)
+ * @nbytes: Number of bytes to check (normally a multiple of 2)
+ * Return: 16-bit IP checksum
+ */
+unsigned compute_ip_checksum(const void *addr, unsigned nbytes);
+
+/**
+ * ip_checksum_ok() - check if a checksum is correct
+ *
+ * This works by making sure the checksum sums to 0
+ *
+ * @addr: Address to check (must be 16-bit aligned)
+ * @nbytes: Number of bytes to check (normally a multiple of 2)
+ * Return: true if the checksum matches, false if not
+ */
+int ip_checksum_ok(const void *addr, unsigned nbytes);
+
+/**
+ * add_ip_checksums() - add two IP checksums
+ *
+ * @offset: Offset of first sum (if odd we do a byte-swap)
+ * @sum: First checksum
+ * @new_sum: New checksum to add
+ * Return: updated 16-bit IP checksum
+ */
+unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum);
+
+/*
+ * The devname can be either an exact name given by the driver or device tree
+ * or it can be an alias of the form "eth%d"
+ */
+struct udevice *eth_get_dev_by_name(const char *devname);
+int eth_is_active(struct udevice *dev); /* Test device for active state */
+
+/*
+ * Get the hardware address for an ethernet interface .
+ * Args:
+ * base_name - base name for device (normally "eth")
+ * index - device index number (0 for first)
+ * enetaddr - returns 6 byte hardware address
+ * Returns:
+ * Return true if the address is valid.
+ */
+int eth_env_get_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+/**
+ * eth_env_set_enetaddr_by_index() - set the MAC address environment variable
+ *
+ * This sets up an environment variable with the given MAC address (@enetaddr).
+ * The environment variable to be set is defined by <@base_name><@index>addr.
+ * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
+ * eth1addr, etc.
+ *
+ * @base_name: Base name for variable, typically "eth"
+ * @index: Index of interface being updated (>=0)
+ * @enetaddr: Pointer to MAC address to put into the variable
+ * Return: 0 if OK, other value on error
+ */
+int eth_env_set_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+/*
+ * Initialize USB ethernet device with CONFIG_DM_ETH
+ * Returns:
+ * 0 is success, non-zero is error status.
+ */
+int usb_ether_init(void);
+
+int eth_init(void); /* Initialize the device */
+int eth_start_udev(struct udevice *dev); /* ->start() if not already running */
+int eth_send(void *packet, int length); /* Send a packet */
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
+int eth_receive(void *packet, int length); /* Receive a packet*/
+extern void (*push_packet)(void *packet, int length);
+#endif
+int eth_rx(void); /* Check for received packets */
+
+/**
+ * reset_phy() - Reset the Ethernet PHY
+ *
+ * This should be implemented by boards if CONFIG_RESET_PHY_R is enabled
+ */
+void reset_phy(void);
+
+#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)
+/**
+ * eth_set_enable_bootdevs() - Enable or disable binding of Ethernet bootdevs
+ *
+ * These get in the way of bootstd testing, so are normally disabled by tests.
+ * This provide control of this setting. It only affects binding of Ethernet
+ * devices, so if that has already happened, this flag does nothing.
+ *
+ * @enable: true to enable binding of bootdevs when binding new Ethernet
+ * devices, false to disable it
+ */
+void eth_set_enable_bootdevs(bool enable);
+#else
+static inline void eth_set_enable_bootdevs(bool enable) {}
+#endif
+
+static inline void net_send_packet(uchar *pkt, int len)
+{
+ if (DEBUG_NET_PKT_TRACE)
+ print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len);
+ /* Currently no way to return errors from eth_send() */
+ (void) eth_send(pkt, len);
+}
+
+enum eth_recv_flags {
+ /*
+ * Check hardware device for new packets (otherwise only return those
+ * which are already in the memory buffer ready to process)
+ */
+ ETH_RECV_CHECK_DEVICE = 1 << 0,
+};
+
+/**
+ * struct eth_ops - functions of Ethernet MAC controllers
+ *
+ * start: Prepare the hardware to send and receive packets
+ * send: Send the bytes passed in "packet" as a packet on the wire
+ * recv: Check if the hardware received a packet. If so, set the pointer to the
+ * packet buffer in the packetp parameter. If not, return an error or 0 to
+ * indicate that the hardware receive FIFO is empty. If 0 is returned, the
+ * network stack will not process the empty packet, but free_pkt() will be
+ * called if supplied
+ * free_pkt: Give the driver an opportunity to manage its packet buffer memory
+ * when the network stack is finished processing it. This will only be
+ * called when no error was returned from recv - optional
+ * stop: Stop the hardware from looking for packets - may be called even if
+ * state == PASSIVE
+ * mcast: Join or leave a multicast group (for TFTP) - optional
+ * write_hwaddr: Write a MAC address to the hardware (used to pass it to Linux
+ * on some platforms like ARM). This function expects the
+ * eth_pdata::enetaddr field to be populated. The method can
+ * return -ENOSYS to indicate that this is not implemented for
+ this hardware - optional.
+ * read_rom_hwaddr: Some devices have a backup of the MAC address stored in a
+ * ROM on the board. This is how the driver should expose it
+ * to the network stack. This function should fill in the
+ * eth_pdata::enetaddr field - optional
+ * set_promisc: Enable or Disable promiscuous mode
+ * get_sset_count: Number of statistics counters
+ * get_string: Names of the statistic counters
+ * get_stats: The values of the statistic counters
+ */
+struct eth_ops {
+ int (*start)(struct udevice *dev);
+ int (*send)(struct udevice *dev, void *packet, int length);
+ int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+ int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+ void (*stop)(struct udevice *dev);
+ int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
+ int (*write_hwaddr)(struct udevice *dev);
+ int (*read_rom_hwaddr)(struct udevice *dev);
+ int (*set_promisc)(struct udevice *dev, bool enable);
+ int (*get_sset_count)(struct udevice *dev);
+ void (*get_strings)(struct udevice *dev, u8 *data);
+ void (*get_stats)(struct udevice *dev, u64 *data);
+};
+
+#define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
+
+struct udevice *eth_get_dev(void); /* get the current device */
+unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
+int eth_rx(void); /* Check for received packets */
+void eth_halt(void); /* stop SCC */
+const char *eth_get_name(void); /* get name of current device */
+int eth_get_dev_index(void);
+
+int eth_initialize(void); /* Initialize network subsystem */
+void eth_try_another(int first_restart); /* Change the device */
+void eth_set_current(void); /* set nterface to ethcur var */
+
+enum eth_state_t {
+ ETH_STATE_INIT,
+ ETH_STATE_PASSIVE,
+ ETH_STATE_ACTIVE
+};
+
+/**
+ * struct eth_pdata - Platform data for Ethernet MAC controllers
+ *
+ * @iobase: The base address of the hardware registers
+ * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env
+ * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_...
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @priv_pdata: device specific plat
+ */
+struct eth_pdata {
+ phys_addr_t iobase;
+ unsigned char enetaddr[ARP_HLEN];
+ int phy_interface;
+ int max_speed;
+ void *priv_pdata;
+};
+
+struct ethernet_hdr {
+ u8 et_dest[ARP_HLEN]; /* Destination node */
+ u8 et_src[ARP_HLEN]; /* Source node */
+ u16 et_protlen; /* Protocol or length */
+} __attribute__((packed));
+
+/* Ethernet header size */
+#define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr))
+
+/**
+ * net_random_ethaddr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void net_random_ethaddr(uchar *addr)
+{
+ int i;
+ unsigned int seed = get_ticks();
+
+ for (i = 0; i < 6; i++)
+ addr[i] = rand_r(&seed);
+
+ addr[0] &= 0xfe; /* clear multicast bit */
+ addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+}
+
+/**
+ * is_zero_ethaddr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ethaddr(const u8 *addr)
+{
+ return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ethaddr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ethaddr(const u8 *addr)
+{
+ return 0x01 & addr[0];
+}
+
+/*
+ * is_broadcast_ethaddr - Determine if the Ethernet address is broadcast
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is the broadcast address.
+ */
+static inline int is_broadcast_ethaddr(const u8 *addr)
+{
+ return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) ==
+ 0xff;
+}
+
+/*
+ * is_valid_ethaddr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ethaddr(const u8 *addr)
+{
+ /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+ * explicitly check for it here. */
+ return !is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr);
+}
+
+/**
+ * string_to_enetaddr() - Parse a MAC address
+ *
+ * Convert a string MAC address
+ *
+ * Implemented in lib/net_utils.c (built unconditionally)
+ *
+ * @addr: MAC address in aa:bb:cc:dd:ee:ff format, where each part is a 2-digit
+ * hex value
+ * @enetaddr: Place to put MAC address (6 bytes)
+ */
+void string_to_enetaddr(const char *addr, uint8_t *enetaddr);
+
+/**
+ * string_to_ip() - Convert a string to ip address
+ *
+ * Implemented in lib/net_utils.c (built unconditionally)
+ *
+ * @s: Input string to parse
+ * @return: in_addr struct containing the parsed IP address
+ */
+struct in_addr string_to_ip(const char *s);
+
+/* copy a filename (allow for "..." notation, limit length) */
+void copy_filename(char *dst, const char *src, int size);
+
+/* Processes a received packet */
+void net_process_received_packet(uchar *in_packet, int len);
+
+/**
+ * update_tftp - Update firmware over TFTP (via DFU)
+ *
+ * This function updates board's firmware via TFTP
+ *
+ * @param addr - memory address where data is stored
+ * @param interface - the DFU medium name - e.g. "mmc"
+ * @param devstring - the DFU medium number - e.g. "1"
+ *
+ * Return: - 0 on success, other value on failure
+ */
+int update_tftp(ulong addr, char *interface, char *devstring);
+
+/**
+ * env_get_ip() - Convert an environment value to to an ip address
+ *
+ * @var: Environment variable to convert. The value of this variable must be
+ * in the format format a.b.c.d, where each value is a decimal number from
+ * 0 to 255
+ * Return: IP address, or 0 if invalid
+ */
+static inline struct in_addr env_get_ip(char *var)
+{
+ return string_to_ip(env_get(var));
+}
+
+int net_init(void);
+
+/* NET compatibility */
+enum proto_t;
+int net_loop(enum proto_t protocol);
+
+/**
+ * dhcp_run() - Run DHCP on the current ethernet device
+ *
+ * This sets the autoload variable, then puts it back to similar to its original
+ * state (y, n or unset).
+ *
+ * @addr: Address to load the file into (0 if @autoload is false)
+ * @fname: Filename of file to load (NULL if @autoload is false or to use the
+ * default filename)
+ * @autoload: true to load the file, false to just get the network IP
+ * @return 0 if OK, -EINVAL if the environment failed, -ENOENT if ant file was
+ * not found
+ */
+int dhcp_run(ulong addr, const char *fname, bool autoload);
+
+/**
+ * do_tftpb - Run the tftpboot command
+ *
+ * @cmdtp: Command information for tftpboot
+ * @flag: Command flags (CMD_FLAG_...)
+ * @argc: Number of arguments
+ * @argv: List of arguments
+ * Return: result (see enum command_ret_t)
+ */
+int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
+/**
+ * wget_with_dns() - runs dns host IP address resulution before wget
+ *
+ * @dst_addr: destination address to download the file
+ * @uri: uri string of target file of wget
+ * Return: downloaded file size, negative if failed
+ */
+int wget_with_dns(ulong dst_addr, char *uri);
+/**
+ * wget_validate_uri() - varidate the uri
+ *
+ * @uri: uri string of target file of wget
+ * Return: true if uri is valid, false if uri is invalid
+ */
+bool wget_validate_uri(char *uri);
+//int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+
+#endif /* __NET_COMMON_H__ */
diff --git a/include/net-legacy.h b/include/net-legacy.h
new file mode 100644
index 0000000..ca1efd1
--- /dev/null
+++ b/include/net-legacy.h
@@ -0,0 +1,541 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * LiMon Monitor (LiMon) - Network.
+ *
+ * Copyright 1994 - 2000 Neil Russell.
+ * (See License)
+ *
+ * History
+ * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
+ */
+
+#ifndef __NET_LEGACY_H__
+#define __NET_LEGACY_H__
+
+#include <linux/types.h>
+#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
+#include <log.h>
+#include <time.h>
+#include <linux/if_ether.h>
+
+struct bd_info;
+struct cmd_tbl;
+struct udevice;
+
+#define DEBUG_LL_STATE 0 /* Link local state machine changes */
+#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */
+#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */
+#define DEBUG_INT_STATE 0 /* Internal network state changes */
+
+/* ARP hardware address length */
+#define ARP_HLEN 6
+/*
+ * The size of a MAC address in string form, each digit requires two chars
+ * and five separator characters to form '00:00:00:00:00:00'.
+ */
+#define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1)
+
+/**
+ * An incoming packet handler.
+ * @param pkt pointer to the application packet
+ * @param dport destination UDP port
+ * @param sip source IP address
+ * @param sport source UDP port
+ * @param len packet length
+ */
+typedef void rxhand_f(uchar *pkt, unsigned dport,
+ struct in_addr sip, unsigned sport,
+ unsigned len);
+
+/**
+ * An incoming ICMP packet handler.
+ * @param type ICMP type
+ * @param code ICMP code
+ * @param dport destination UDP port
+ * @param sip source IP address
+ * @param sport source UDP port
+ * @param pkt pointer to the ICMP packet data
+ * @param len packet length
+ */
+typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
+ struct in_addr sip, unsigned sport, uchar *pkt, unsigned len);
+
+/*
+ * A timeout handler. Called after time interval has expired.
+ */
+typedef void thand_f(void);
+
+/*
+ * The devname can be either an exact name given by the driver or device tree
+ * or it can be an alias of the form "eth%d"
+ */
+struct udevice *eth_get_dev_by_name(const char *devname);
+int eth_init_state_only(void); /* Set active state */
+void eth_halt_state_only(void); /* Set passive state */
+
+/**
+ * eth_env_set_enetaddr_by_index() - set the MAC address environment variable
+ *
+ * This sets up an environment variable with the given MAC address (@enetaddr).
+ * The environment variable to be set is defined by <@base_name><@index>addr.
+ * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
+ * eth1addr, etc.
+ *
+ * @base_name: Base name for variable, typically "eth"
+ * @index: Index of interface being updated (>=0)
+ * @enetaddr: Pointer to MAC address to put into the variable
+ * Return: 0 if OK, other value on error
+ */
+int eth_env_set_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+/*
+ * Get the hardware address for an ethernet interface .
+ * Args:
+ * base_name - base name for device (normally "eth")
+ * index - device index number (0 for first)
+ * enetaddr - returns 6 byte hardware address
+ * Returns:
+ * Return true if the address is valid.
+ */
+int eth_env_get_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+int eth_send(void *packet, int length); /* Send a packet */
+
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
+int eth_receive(void *packet, int length); /* Receive a packet*/
+extern void (*push_packet)(void *packet, int length);
+#endif
+int eth_mcast_join(struct in_addr mcast_addr, int join);
+
+/**********************************************************************/
+/*
+ * Protocol headers.
+ */
+
+#define ETH_FCS_LEN 4 /* Octets in the FCS */
+
+struct e802_hdr {
+ u8 et_dest[ARP_HLEN]; /* Destination node */
+ u8 et_src[ARP_HLEN]; /* Source node */
+ u16 et_protlen; /* Protocol or length */
+ u8 et_dsap; /* 802 DSAP */
+ u8 et_ssap; /* 802 SSAP */
+ u8 et_ctl; /* 802 control */
+ u8 et_snap1; /* SNAP */
+ u8 et_snap2;
+ u8 et_snap3;
+ u16 et_prot; /* 802 protocol */
+} __attribute__((packed));
+
+/* 802 + SNAP + ethernet header size */
+#define E802_HDR_SIZE (sizeof(struct e802_hdr))
+
+/*
+ * Virtual LAN Ethernet header
+ */
+struct vlan_ethernet_hdr {
+ u8 vet_dest[ARP_HLEN]; /* Destination node */
+ u8 vet_src[ARP_HLEN]; /* Source node */
+ u16 vet_vlan_type; /* PROT_VLAN */
+ u16 vet_tag; /* TAG of VLAN */
+ u16 vet_type; /* protocol type */
+} __attribute__((packed));
+
+/* VLAN Ethernet header size */
+#define VLAN_ETHER_HDR_SIZE (sizeof(struct vlan_ethernet_hdr))
+
+/*
+ * Internet Protocol (IP) header.
+ */
+struct ip_hdr {
+ u8 ip_hl_v; /* header length and version */
+ u8 ip_tos; /* type of service */
+ u16 ip_len; /* total length */
+ u16 ip_id; /* identification */
+ u16 ip_off; /* fragment offset field */
+ u8 ip_ttl; /* time to live */
+ u8 ip_p; /* protocol */
+ u16 ip_sum; /* checksum */
+ struct in_addr ip_src; /* Source IP address */
+ struct in_addr ip_dst; /* Destination IP address */
+} __attribute__((packed));
+
+#define IP_OFFS 0x1fff /* ip offset *= 8 */
+#define IP_FLAGS 0xe000 /* first 3 bits */
+#define IP_FLAGS_RES 0x8000 /* reserved */
+#define IP_FLAGS_DFRAG 0x4000 /* don't fragments */
+#define IP_FLAGS_MFRAG 0x2000 /* more fragments */
+
+#define IP_HDR_SIZE (sizeof(struct ip_hdr))
+
+#define IP_MIN_FRAG_DATAGRAM_SIZE (IP_HDR_SIZE + 8)
+
+/*
+ * Address Resolution Protocol (ARP) header.
+ */
+struct arp_hdr {
+ u16 ar_hrd; /* Format of hardware address */
+# define ARP_ETHER 1 /* Ethernet hardware address */
+ u16 ar_pro; /* Format of protocol address */
+ u8 ar_hln; /* Length of hardware address */
+ u8 ar_pln; /* Length of protocol address */
+# define ARP_PLEN 4
+ u16 ar_op; /* Operation */
+# define ARPOP_REQUEST 1 /* Request to resolve address */
+# define ARPOP_REPLY 2 /* Response to previous request */
+
+# define RARPOP_REQUEST 3 /* Request to resolve address */
+# define RARPOP_REPLY 4 /* Response to previous request */
+
+ /*
+ * The remaining fields are variable in size, according to
+ * the sizes above, and are defined as appropriate for
+ * specific hardware/protocol combinations.
+ */
+ u8 ar_data[0];
+#define ar_sha ar_data[0]
+#define ar_spa ar_data[ARP_HLEN]
+#define ar_tha ar_data[ARP_HLEN + ARP_PLEN]
+#define ar_tpa ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN]
+#if 0
+ u8 ar_sha[]; /* Sender hardware address */
+ u8 ar_spa[]; /* Sender protocol address */
+ u8 ar_tha[]; /* Target hardware address */
+ u8 ar_tpa[]; /* Target protocol address */
+#endif /* 0 */
+} __attribute__((packed));
+
+
+/*
+ * ICMP stuff (just enough to handle (host) redirect messages)
+ */
+#define ICMP_ECHO_REPLY 0 /* Echo reply */
+#define ICMP_NOT_REACH 3 /* Detination unreachable */
+#define ICMP_REDIRECT 5 /* Redirect (change route) */
+#define ICMP_ECHO_REQUEST 8 /* Echo request */
+
+/* Codes for REDIRECT. */
+#define ICMP_REDIR_NET 0 /* Redirect Net */
+#define ICMP_REDIR_HOST 1 /* Redirect Host */
+
+/* Codes for NOT_REACH */
+#define ICMP_NOT_REACH_PORT 3 /* Port unreachable */
+
+struct icmp_hdr {
+ u8 type;
+ u8 code;
+ u16 checksum;
+ union {
+ struct {
+ u16 id;
+ u16 sequence;
+ } echo;
+ u32 gateway;
+ struct {
+ u16 unused;
+ u16 mtu;
+ } frag;
+ u8 data[0];
+ } un;
+} __attribute__((packed));
+
+#define ICMP_HDR_SIZE (sizeof(struct icmp_hdr))
+#define IP_ICMP_HDR_SIZE (IP_HDR_SIZE + ICMP_HDR_SIZE)
+
+/*
+ * Maximum packet size; used to allocate packet storage. Use
+ * the maxium Ethernet frame size as specified by the Ethernet
+ * standard including the 802.1Q tag (VLAN tagging).
+ * maximum packet size = 1522
+ * maximum packet size and multiple of 32 bytes = 1536
+ */
+#define PKTSIZE 1522
+#ifndef CONFIG_DM_DSA
+#define PKTSIZE_ALIGN 1536
+#else
+/* Maximum DSA tagging overhead (headroom and/or tailroom) */
+#define DSA_MAX_OVR 256
+#define PKTSIZE_ALIGN (1536 + DSA_MAX_OVR)
+#endif
+
+/**********************************************************************/
+/*
+ * Globals.
+ *
+ * Note:
+ *
+ * All variables of type struct in_addr are stored in NETWORK byte order
+ * (big endian).
+ */
+
+/* net.c */
+/** BOOTP EXTENTIONS **/
+extern struct in_addr net_gateway; /* Our gateway IP address */
+extern struct in_addr net_netmask; /* Our subnet mask (0 = unknown) */
+/* Our Domain Name Server (0 = unknown) */
+extern struct in_addr net_dns_server;
+#if defined(CONFIG_BOOTP_DNS2)
+/* Our 2nd Domain Name Server (0 = unknown) */
+extern struct in_addr net_dns_server2;
+#endif
+extern char net_nis_domain[32]; /* Our IS domain */
+extern char net_hostname[32]; /* Our hostname */
+#ifdef CONFIG_NET
+extern char net_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN]; /* Our root path */
+#endif
+/** END OF BOOTP EXTENTIONS **/
+extern u8 net_ethaddr[ARP_HLEN]; /* Our ethernet address */
+extern u8 net_server_ethaddr[ARP_HLEN]; /* Boot server enet address */
+extern struct in_addr net_server_ip; /* Server IP addr (0 = unknown) */
+extern uchar *net_tx_packet; /* THE transmit packet */
+extern uchar *net_rx_packets[PKTBUFSRX]; /* Receive packets */
+extern uchar *net_rx_packet; /* Current receive packet */
+extern int net_rx_packet_len; /* Current rx packet length */
+extern const u8 net_null_ethaddr[ARP_HLEN];
+
+#define VLAN_NONE 4095 /* untagged */
+#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */
+extern ushort net_our_vlan; /* Our VLAN */
+extern ushort net_native_vlan; /* Our Native VLAN */
+
+extern int net_restart_wrap; /* Tried all network devices */
+
+enum proto_t {
+ BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
+ NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT_UDP, FASTBOOT_TCP,
+ WOL, UDP, NCSI, WGET, RS
+};
+/* Indicates whether the file name was specified on the command line */
+extern bool net_boot_file_name_explicit;
+/* The actual transferred size of the bootfile (in bytes) */
+extern u32 net_boot_file_size;
+/* Boot file size in blocks as reported by the DHCP server */
+extern u32 net_boot_file_expected_size_in_blocks;
+
+#if defined(CONFIG_CMD_DNS)
+extern char *net_dns_resolve; /* The host to resolve */
+extern char *net_dns_env_var; /* the env var to put the ip into */
+#endif
+
+#if defined(CONFIG_CMD_PING)
+extern struct in_addr net_ping_ip; /* the ip address to ping */
+#endif
+
+#if defined(CONFIG_CMD_CDP)
+/* when CDP completes these hold the return values */
+extern ushort cdp_native_vlan; /* CDP returned native VLAN */
+extern ushort cdp_appliance_vlan; /* CDP returned appliance VLAN */
+
+/*
+ * Check for a CDP packet by examining the received MAC address field
+ */
+static inline int is_cdp_packet(const uchar *ethaddr)
+{
+ extern const u8 net_cdp_ethaddr[ARP_HLEN];
+
+ return memcmp(ethaddr, net_cdp_ethaddr, ARP_HLEN) == 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_SNTP)
+extern struct in_addr net_ntp_server; /* the ip address to NTP */
+extern int net_ntp_time_offset; /* offset time from UTC */
+#endif
+
+int net_loop(enum proto_t);
+
+/* Load failed. Start again. */
+int net_start_again(void);
+
+/* Get size of the ethernet header when we send */
+int net_eth_hdr_size(void);
+
+/* Set ethernet header; returns the size of the header */
+int net_set_ether(uchar *xet, const uchar *dest_ethaddr, uint prot);
+int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
+
+/* Set IP header */
+void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
+ u16 pkt_len, u8 proto);
+void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
+ int sport, int len);
+
+/* Callbacks */
+rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */
+void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */
+rxhand_f *net_get_arp_handler(void); /* Get ARP RX packet handler */
+void net_set_arp_handler(rxhand_f *); /* Set ARP RX packet handler */
+bool arp_is_waiting(void); /* Waiting for ARP reply? */
+void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
+void net_set_timeout_handler(ulong, thand_f *);/* Set timeout handler */
+
+/* Network loop state */
+enum net_loop_state {
+ NETLOOP_CONTINUE,
+ NETLOOP_RESTART,
+ NETLOOP_SUCCESS,
+ NETLOOP_FAIL
+};
+extern enum net_loop_state net_state;
+
+static inline void net_set_state(enum net_loop_state state)
+{
+ debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
+ net_state = state;
+}
+
+/*
+ * net_get_async_tx_pkt_buf - Get a packet buffer that is not in use for
+ * sending an asynchronous reply
+ *
+ * returns - ptr to packet buffer
+ */
+uchar * net_get_async_tx_pkt_buf(void);
+
+/**
+ * net_send_ip_packet() - Transmit "net_tx_packet" as UDP or TCP packet,
+ * send ARP request if needed (ether will be populated)
+ * @ether: Raw packet buffer
+ * @dest: IP address to send the datagram to
+ * @dport: Destination UDP port
+ * @sport: Source UDP port
+ * @payload_len: Length of data after the UDP header
+ * @action: TCP action to be performed
+ * @tcp_seq_num: TCP sequence number of this transmission
+ * @tcp_ack_num: TCP stream acknolegement number
+ *
+ * Return: 0 on success, other value on failure
+ */
+int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
+ int payload_len, int proto, u8 action, u32 tcp_seq_num,
+ u32 tcp_ack_num);
+/**
+ * net_send_tcp_packet() - Transmit TCP packet.
+ * @payload_len: length of payload
+ * @dport: Destination TCP port
+ * @sport: Source TCP port
+ * @action: TCP action to be performed
+ * @tcp_seq_num: TCP sequence number of this transmission
+ * @tcp_ack_num: TCP stream acknolegement number
+ *
+ * Return: 0 on success, other value on failure
+ */
+int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action,
+ u32 tcp_seq_num, u32 tcp_ack_num);
+int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
+ int sport, int payload_len);
+
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
+void nc_start(void);
+int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
+ unsigned src_port, unsigned len);
+#endif
+
+static __always_inline int eth_is_on_demand_init(void)
+{
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
+ extern enum proto_t net_loop_last_protocol;
+
+ return net_loop_last_protocol != NETCONS;
+#else
+ return 1;
+#endif
+}
+
+static inline void eth_set_last_protocol(int protocol)
+{
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
+ extern enum proto_t net_loop_last_protocol;
+
+ net_loop_last_protocol = protocol;
+#endif
+}
+
+/*
+ * Check if autoload is enabled. If so, use either NFS or TFTP to download
+ * the boot file.
+ */
+void net_auto_load(void);
+
+/*
+ * The following functions are a bit ugly, but necessary to deal with
+ * alignment restrictions on ARM.
+ *
+ * We're using inline functions, which had the smallest memory
+ * footprint in our tests.
+ */
+/* return IP *in network byteorder* */
+static inline struct in_addr net_read_ip(void *from)
+{
+ struct in_addr ip;
+
+ memcpy((void *)&ip, (void *)from, sizeof(ip));
+ return ip;
+}
+
+/* return ulong *in network byteorder* */
+static inline u32 net_read_u32(void *from)
+{
+ u32 l;
+
+ memcpy((void *)&l, (void *)from, sizeof(l));
+ return l;
+}
+
+/* write IP *in network byteorder* */
+static inline void net_write_ip(void *to, struct in_addr ip)
+{
+ memcpy(to, (void *)&ip, sizeof(ip));
+}
+
+/* copy IP */
+static inline void net_copy_ip(void *to, void *from)
+{
+ memcpy((void *)to, from, sizeof(struct in_addr));
+}
+
+/* copy ulong */
+static inline void net_copy_u32(void *to, void *from)
+{
+ memcpy((void *)to, (void *)from, sizeof(u32));
+}
+
+/* Convert an IP address to a string */
+void ip_to_string(struct in_addr x, char *s);
+
+/**
+ * string_to_ip() - Convert a string to ip address
+ *
+ * Implemented in lib/net_utils.c (built unconditionally)
+ *
+ * @s: Input string to parse
+ * @return: in_addr struct containing the parsed IP address
+ */
+struct in_addr string_to_ip(const char *s);
+
+/* Convert a VLAN id to a string */
+void vlan_to_string(ushort x, char *s);
+
+/* Convert a string to a vlan id */
+ushort string_to_vlan(const char *s);
+
+/* read a VLAN id from an environment variable */
+ushort env_get_vlan(char *);
+
+/* check if serverip is specified in filename from the command line */
+int is_serverip_in_cmd(void);
+
+/**
+ * net_parse_bootfile - Parse the bootfile env var / cmd line param
+ *
+ * @param ipaddr - a pointer to the ipaddr to populate if included in bootfile
+ * @param filename - a pointer to the string to save the filename part
+ * @param max_len - The longest - 1 that the filename part can be
+ *
+ * return 1 if parsed, 0 if bootfile is empty
+ */
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
+
+#endif /* __NET_LEGACY_H__ */
diff --git a/include/net-lwip.h b/include/net-lwip.h
new file mode 100644
index 0000000..1c3583f
--- /dev/null
+++ b/include/net-lwip.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __NET_LWIP_H__
+#define __NET_LWIP_H__
+
+#include <lwip/ip4.h>
+#include <lwip/netif.h>
+
+enum proto_t {
+ TFTPGET
+};
+
+struct netif *net_lwip_new_netif(struct udevice *udev);
+struct netif *net_lwip_new_netif_noip(struct udevice *udev);
+void net_lwip_remove_netif(struct netif *netif);
+struct netif *net_lwip_get_netif(void);
+int net_lwip_rx(struct udevice *udev, struct netif *netif);
+
+/**
+ * wget_with_dns() - runs dns host IP address resulution before wget
+ *
+ * @dst_addr: destination address to download the file
+ * @uri: uri string of target file of wget
+ * Return: downloaded file size, negative if failed
+ */
+
+int wget_with_dns(ulong dst_addr, char *uri);
+/**
+ * wget_validate_uri() - varidate the uri
+ *
+ * @uri: uri string of target file of wget
+ * Return: true if uri is valid, false if uri is invalid
+ */
+bool wget_validate_uri(char *uri);
+
+int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+
+#endif /* __NET_LWIP_H__ */
diff --git a/include/net.h b/include/net.h
index dc8b5e9..afa46f2 100644
--- a/include/net.h
+++ b/include/net.h
@@ -1,949 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * LiMon Monitor (LiMon) - Network.
- *
- * Copyright 1994 - 2000 Neil Russell.
- * (See License)
- *
- * History
- * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
- */
#ifndef __NET_H__
#define __NET_H__
-#include <linux/types.h>
-#include <asm/cache.h>
-#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
-#include <env.h>
-#include <hexdump.h>
-#include <log.h>
-#include <time.h>
-#include <linux/if_ether.h>
-#include <rand.h>
+#include <net-common.h>
-struct bd_info;
-struct cmd_tbl;
-struct udevice;
-
-#define DEBUG_LL_STATE 0 /* Link local state machine changes */
-#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */
-#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */
-#define DEBUG_INT_STATE 0 /* Internal network state changes */
-#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */
-
-/*
- * The number of receive packet buffers, and the required packet buffer
- * alignment in memory.
- *
- */
-#define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER
-#define PKTALIGN ARCH_DMA_MINALIGN
-
-/* Number of packets processed together */
-#define ETH_PACKETS_BATCH_RECV 32
-
-/* ARP hardware address length */
-#define ARP_HLEN 6
-/*
- * The size of a MAC address in string form, each digit requires two chars
- * and five separator characters to form '00:00:00:00:00:00'.
- */
-#define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1)
-
-/* IPv4 addresses are always 32 bits in size */
-struct in_addr {
- __be32 s_addr;
-};
-
-/**
- * do_tftpb - Run the tftpboot command
- *
- * @cmdtp: Command information for tftpboot
- * @flag: Command flags (CMD_FLAG_...)
- * @argc: Number of arguments
- * @argv: List of arguments
- * Return: result (see enum command_ret_t)
- */
-int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-
-/**
- * dhcp_run() - Run DHCP on the current ethernet device
- *
- * This sets the autoload variable, then puts it back to similar to its original
- * state (y, n or unset).
- *
- * @addr: Address to load the file into (0 if @autoload is false)
- * @fname: Filename of file to load (NULL if @autoload is false or to use the
- * default filename)
- * @autoload: true to load the file, false to just get the network IP
- * @return 0 if OK, -EINVAL if the environment failed, -ENOENT if ant file was
- * not found
- */
-int dhcp_run(ulong addr, const char *fname, bool autoload);
-
-/**
- * An incoming packet handler.
- * @param pkt pointer to the application packet
- * @param dport destination UDP port
- * @param sip source IP address
- * @param sport source UDP port
- * @param len packet length
- */
-typedef void rxhand_f(uchar *pkt, unsigned dport,
- struct in_addr sip, unsigned sport,
- unsigned len);
-
-/**
- * An incoming ICMP packet handler.
- * @param type ICMP type
- * @param code ICMP code
- * @param dport destination UDP port
- * @param sip source IP address
- * @param sport source UDP port
- * @param pkt pointer to the ICMP packet data
- * @param len packet length
- */
-typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
- struct in_addr sip, unsigned sport, uchar *pkt, unsigned len);
-
-/*
- * A timeout handler. Called after time interval has expired.
- */
-typedef void thand_f(void);
-
-enum eth_state_t {
- ETH_STATE_INIT,
- ETH_STATE_PASSIVE,
- ETH_STATE_ACTIVE
-};
-
-/**
- * struct eth_pdata - Platform data for Ethernet MAC controllers
- *
- * @iobase: The base address of the hardware registers
- * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env
- * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_...
- * @max_speed: Maximum speed of Ethernet connection supported by MAC
- * @priv_pdata: device specific plat
- */
-struct eth_pdata {
- phys_addr_t iobase;
- unsigned char enetaddr[ARP_HLEN];
- int phy_interface;
- int max_speed;
- void *priv_pdata;
-};
-
-enum eth_recv_flags {
- /*
- * Check hardware device for new packets (otherwise only return those
- * which are already in the memory buffer ready to process)
- */
- ETH_RECV_CHECK_DEVICE = 1 << 0,
-};
-
-/**
- * struct eth_ops - functions of Ethernet MAC controllers
- *
- * start: Prepare the hardware to send and receive packets
- * send: Send the bytes passed in "packet" as a packet on the wire
- * recv: Check if the hardware received a packet. If so, set the pointer to the
- * packet buffer in the packetp parameter. If not, return an error or 0 to
- * indicate that the hardware receive FIFO is empty. If 0 is returned, the
- * network stack will not process the empty packet, but free_pkt() will be
- * called if supplied
- * free_pkt: Give the driver an opportunity to manage its packet buffer memory
- * when the network stack is finished processing it. This will only be
- * called when no error was returned from recv - optional
- * stop: Stop the hardware from looking for packets - may be called even if
- * state == PASSIVE
- * mcast: Join or leave a multicast group (for TFTP) - optional
- * write_hwaddr: Write a MAC address to the hardware (used to pass it to Linux
- * on some platforms like ARM). This function expects the
- * eth_pdata::enetaddr field to be populated. The method can
- * return -ENOSYS to indicate that this is not implemented for
- this hardware - optional.
- * read_rom_hwaddr: Some devices have a backup of the MAC address stored in a
- * ROM on the board. This is how the driver should expose it
- * to the network stack. This function should fill in the
- * eth_pdata::enetaddr field - optional
- * set_promisc: Enable or Disable promiscuous mode
- * get_sset_count: Number of statistics counters
- * get_string: Names of the statistic counters
- * get_stats: The values of the statistic counters
- */
-struct eth_ops {
- int (*start)(struct udevice *dev);
- int (*send)(struct udevice *dev, void *packet, int length);
- int (*recv)(struct udevice *dev, int flags, uchar **packetp);
- int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
- void (*stop)(struct udevice *dev);
- int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
- int (*write_hwaddr)(struct udevice *dev);
- int (*read_rom_hwaddr)(struct udevice *dev);
- int (*set_promisc)(struct udevice *dev, bool enable);
- int (*get_sset_count)(struct udevice *dev);
- void (*get_strings)(struct udevice *dev, u8 *data);
- void (*get_stats)(struct udevice *dev, u64 *data);
-};
-
-#define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
-
-struct udevice *eth_get_dev(void); /* get the current device */
-/*
- * The devname can be either an exact name given by the driver or device tree
- * or it can be an alias of the form "eth%d"
- */
-struct udevice *eth_get_dev_by_name(const char *devname);
-unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
-
-/* Used only when NetConsole is enabled */
-int eth_is_active(struct udevice *dev); /* Test device for active state */
-int eth_init_state_only(void); /* Set active state */
-void eth_halt_state_only(void); /* Set passive state */
-
-int eth_initialize(void); /* Initialize network subsystem */
-void eth_try_another(int first_restart); /* Change the device */
-void eth_set_current(void); /* set nterface to ethcur var */
-
-int eth_get_dev_index(void); /* get the device index */
-
-/**
- * eth_env_set_enetaddr_by_index() - set the MAC address environment variable
- *
- * This sets up an environment variable with the given MAC address (@enetaddr).
- * The environment variable to be set is defined by <@base_name><@index>addr.
- * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
- * eth1addr, etc.
- *
- * @base_name: Base name for variable, typically "eth"
- * @index: Index of interface being updated (>=0)
- * @enetaddr: Pointer to MAC address to put into the variable
- * Return: 0 if OK, other value on error
- */
-int eth_env_set_enetaddr_by_index(const char *base_name, int index,
- uchar *enetaddr);
-
-/*
- * Initialize USB ethernet device with CONFIG_DM_ETH
- * Returns:
- * 0 is success, non-zero is error status.
- */
-int usb_ether_init(void);
-
-/*
- * Get the hardware address for an ethernet interface .
- * Args:
- * base_name - base name for device (normally "eth")
- * index - device index number (0 for first)
- * enetaddr - returns 6 byte hardware address
- * Returns:
- * Return true if the address is valid.
- */
-int eth_env_get_enetaddr_by_index(const char *base_name, int index,
- uchar *enetaddr);
-
-int eth_init(void); /* Initialize the device */
-int eth_send(void *packet, int length); /* Send a packet */
-
-#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
-int eth_receive(void *packet, int length); /* Receive a packet*/
-extern void (*push_packet)(void *packet, int length);
-#endif
-int eth_rx(void); /* Check for received packets */
-void eth_halt(void); /* stop SCC */
-const char *eth_get_name(void); /* get name of current device */
-int eth_mcast_join(struct in_addr mcast_addr, int join);
-
-/**********************************************************************/
-/*
- * Protocol headers.
- */
-
-/*
- * Ethernet header
- */
-
-struct ethernet_hdr {
- u8 et_dest[ARP_HLEN]; /* Destination node */
- u8 et_src[ARP_HLEN]; /* Source node */
- u16 et_protlen; /* Protocol or length */
-} __attribute__((packed));
-
-/* Ethernet header size */
-#define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr))
-
-#define ETH_FCS_LEN 4 /* Octets in the FCS */
-
-struct e802_hdr {
- u8 et_dest[ARP_HLEN]; /* Destination node */
- u8 et_src[ARP_HLEN]; /* Source node */
- u16 et_protlen; /* Protocol or length */
- u8 et_dsap; /* 802 DSAP */
- u8 et_ssap; /* 802 SSAP */
- u8 et_ctl; /* 802 control */
- u8 et_snap1; /* SNAP */
- u8 et_snap2;
- u8 et_snap3;
- u16 et_prot; /* 802 protocol */
-} __attribute__((packed));
-
-/* 802 + SNAP + ethernet header size */
-#define E802_HDR_SIZE (sizeof(struct e802_hdr))
-
-/*
- * Virtual LAN Ethernet header
- */
-struct vlan_ethernet_hdr {
- u8 vet_dest[ARP_HLEN]; /* Destination node */
- u8 vet_src[ARP_HLEN]; /* Source node */
- u16 vet_vlan_type; /* PROT_VLAN */
- u16 vet_tag; /* TAG of VLAN */
- u16 vet_type; /* protocol type */
-} __attribute__((packed));
-
-/* VLAN Ethernet header size */
-#define VLAN_ETHER_HDR_SIZE (sizeof(struct vlan_ethernet_hdr))
-
-#define PROT_IP 0x0800 /* IP protocol */
-#define PROT_ARP 0x0806 /* IP ARP protocol */
-#define PROT_WOL 0x0842 /* ether-wake WoL protocol */
-#define PROT_RARP 0x8035 /* IP ARP protocol */
-#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
-#define PROT_IPV6 0x86dd /* IPv6 over bluebook */
-#define PROT_PPP_SES 0x8864 /* PPPoE session messages */
-#define PROT_NCSI 0x88f8 /* NC-SI control packets */
-
-#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
-#define IPPROTO_TCP 6 /* Transmission Control Protocol */
-#define IPPROTO_UDP 17 /* User Datagram Protocol */
-
-/*
- * Internet Protocol (IP) header.
- */
-struct ip_hdr {
- u8 ip_hl_v; /* header length and version */
- u8 ip_tos; /* type of service */
- u16 ip_len; /* total length */
- u16 ip_id; /* identification */
- u16 ip_off; /* fragment offset field */
- u8 ip_ttl; /* time to live */
- u8 ip_p; /* protocol */
- u16 ip_sum; /* checksum */
- struct in_addr ip_src; /* Source IP address */
- struct in_addr ip_dst; /* Destination IP address */
-} __attribute__((packed));
-
-#define IP_OFFS 0x1fff /* ip offset *= 8 */
-#define IP_FLAGS 0xe000 /* first 3 bits */
-#define IP_FLAGS_RES 0x8000 /* reserved */
-#define IP_FLAGS_DFRAG 0x4000 /* don't fragments */
-#define IP_FLAGS_MFRAG 0x2000 /* more fragments */
-
-#define IP_HDR_SIZE (sizeof(struct ip_hdr))
-
-#define IP_MIN_FRAG_DATAGRAM_SIZE (IP_HDR_SIZE + 8)
-
-/*
- * Internet Protocol (IP) + UDP header.
- */
-struct ip_udp_hdr {
- u8 ip_hl_v; /* header length and version */
- u8 ip_tos; /* type of service */
- u16 ip_len; /* total length */
- u16 ip_id; /* identification */
- u16 ip_off; /* fragment offset field */
- u8 ip_ttl; /* time to live */
- u8 ip_p; /* protocol */
- u16 ip_sum; /* checksum */
- struct in_addr ip_src; /* Source IP address */
- struct in_addr ip_dst; /* Destination IP address */
- u16 udp_src; /* UDP source port */
- u16 udp_dst; /* UDP destination port */
- u16 udp_len; /* Length of UDP packet */
- u16 udp_xsum; /* Checksum */
-} __attribute__((packed));
-
-#define IP_UDP_HDR_SIZE (sizeof(struct ip_udp_hdr))
-#define UDP_HDR_SIZE (IP_UDP_HDR_SIZE - IP_HDR_SIZE)
-
-/*
- * Address Resolution Protocol (ARP) header.
- */
-struct arp_hdr {
- u16 ar_hrd; /* Format of hardware address */
-# define ARP_ETHER 1 /* Ethernet hardware address */
- u16 ar_pro; /* Format of protocol address */
- u8 ar_hln; /* Length of hardware address */
- u8 ar_pln; /* Length of protocol address */
-# define ARP_PLEN 4
- u16 ar_op; /* Operation */
-# define ARPOP_REQUEST 1 /* Request to resolve address */
-# define ARPOP_REPLY 2 /* Response to previous request */
-
-# define RARPOP_REQUEST 3 /* Request to resolve address */
-# define RARPOP_REPLY 4 /* Response to previous request */
-
- /*
- * The remaining fields are variable in size, according to
- * the sizes above, and are defined as appropriate for
- * specific hardware/protocol combinations.
- */
- u8 ar_data[0];
-#define ar_sha ar_data[0]
-#define ar_spa ar_data[ARP_HLEN]
-#define ar_tha ar_data[ARP_HLEN + ARP_PLEN]
-#define ar_tpa ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN]
-#if 0
- u8 ar_sha[]; /* Sender hardware address */
- u8 ar_spa[]; /* Sender protocol address */
- u8 ar_tha[]; /* Target hardware address */
- u8 ar_tpa[]; /* Target protocol address */
-#endif /* 0 */
-} __attribute__((packed));
-
-#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */
-
-/*
- * ICMP stuff (just enough to handle (host) redirect messages)
- */
-#define ICMP_ECHO_REPLY 0 /* Echo reply */
-#define ICMP_NOT_REACH 3 /* Detination unreachable */
-#define ICMP_REDIRECT 5 /* Redirect (change route) */
-#define ICMP_ECHO_REQUEST 8 /* Echo request */
-
-/* Codes for REDIRECT. */
-#define ICMP_REDIR_NET 0 /* Redirect Net */
-#define ICMP_REDIR_HOST 1 /* Redirect Host */
-
-/* Codes for NOT_REACH */
-#define ICMP_NOT_REACH_PORT 3 /* Port unreachable */
-
-struct icmp_hdr {
- u8 type;
- u8 code;
- u16 checksum;
- union {
- struct {
- u16 id;
- u16 sequence;
- } echo;
- u32 gateway;
- struct {
- u16 unused;
- u16 mtu;
- } frag;
- u8 data[0];
- } un;
-} __attribute__((packed));
-
-#define ICMP_HDR_SIZE (sizeof(struct icmp_hdr))
-#define IP_ICMP_HDR_SIZE (IP_HDR_SIZE + ICMP_HDR_SIZE)
-
-/*
- * Maximum packet size; used to allocate packet storage. Use
- * the maxium Ethernet frame size as specified by the Ethernet
- * standard including the 802.1Q tag (VLAN tagging).
- * maximum packet size = 1522
- * maximum packet size and multiple of 32 bytes = 1536
- */
-#define PKTSIZE 1522
-#ifndef CONFIG_DM_DSA
-#define PKTSIZE_ALIGN 1536
+#if defined(CONFIG_NET_LWIP)
+#include <net-lwip.h>
#else
-/* Maximum DSA tagging overhead (headroom and/or tailroom) */
-#define DSA_MAX_OVR 256
-#define PKTSIZE_ALIGN (1536 + DSA_MAX_OVR)
-#endif
-
-/*
- * Maximum receive ring size; that is, the number of packets
- * we can buffer before overflow happens. Basically, this just
- * needs to be enough to prevent a packet being discarded while
- * we are processing the previous one.
- */
-#define RINGSZ 4
-#define RINGSZ_LOG2 2
-
-/**********************************************************************/
-/*
- * Globals.
- *
- * Note:
- *
- * All variables of type struct in_addr are stored in NETWORK byte order
- * (big endian).
- */
-
-/* net.c */
-/** BOOTP EXTENTIONS **/
-extern struct in_addr net_gateway; /* Our gateway IP address */
-extern struct in_addr net_netmask; /* Our subnet mask (0 = unknown) */
-/* Our Domain Name Server (0 = unknown) */
-extern struct in_addr net_dns_server;
-#if defined(CONFIG_BOOTP_DNS2)
-/* Our 2nd Domain Name Server (0 = unknown) */
-extern struct in_addr net_dns_server2;
+#include <net-legacy.h>
#endif
-extern char net_nis_domain[32]; /* Our IS domain */
-extern char net_hostname[32]; /* Our hostname */
-#ifdef CONFIG_NET
-extern char net_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN]; /* Our root path */
-#endif
-/* Indicates whether the pxe path prefix / config file was specified in dhcp option */
-extern char *pxelinux_configfile;
-/** END OF BOOTP EXTENTIONS **/
-extern u8 net_ethaddr[ARP_HLEN]; /* Our ethernet address */
-extern u8 net_server_ethaddr[ARP_HLEN]; /* Boot server enet address */
-extern struct in_addr net_ip; /* Our IP addr (0 = unknown) */
-extern struct in_addr net_server_ip; /* Server IP addr (0 = unknown) */
-extern uchar *net_tx_packet; /* THE transmit packet */
-extern uchar *net_rx_packets[PKTBUFSRX]; /* Receive packets */
-extern uchar *net_rx_packet; /* Current receive packet */
-extern int net_rx_packet_len; /* Current rx packet length */
-extern const u8 net_bcast_ethaddr[ARP_HLEN]; /* Ethernet broadcast address */
-extern const u8 net_null_ethaddr[ARP_HLEN];
-
-#define VLAN_NONE 4095 /* untagged */
-#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */
-extern ushort net_our_vlan; /* Our VLAN */
-extern ushort net_native_vlan; /* Our Native VLAN */
-
-extern int net_restart_wrap; /* Tried all network devices */
-
-enum proto_t {
- BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
- NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT_UDP, FASTBOOT_TCP,
- WOL, UDP, NCSI, WGET, RS
-};
-
-extern char net_boot_file_name[1024];/* Boot File name */
-/* Indicates whether the file name was specified on the command line */
-extern bool net_boot_file_name_explicit;
-/* The actual transferred size of the bootfile (in bytes) */
-extern u32 net_boot_file_size;
-/* Boot file size in blocks as reported by the DHCP server */
-extern u32 net_boot_file_expected_size_in_blocks;
-
-#if defined(CONFIG_CMD_DNS)
-extern char *net_dns_resolve; /* The host to resolve */
-extern char *net_dns_env_var; /* the env var to put the ip into */
-#endif
-
-#if defined(CONFIG_CMD_PING)
-extern struct in_addr net_ping_ip; /* the ip address to ping */
-#endif
-
-#if defined(CONFIG_CMD_CDP)
-/* when CDP completes these hold the return values */
-extern ushort cdp_native_vlan; /* CDP returned native VLAN */
-extern ushort cdp_appliance_vlan; /* CDP returned appliance VLAN */
-
-/*
- * Check for a CDP packet by examining the received MAC address field
- */
-static inline int is_cdp_packet(const uchar *ethaddr)
-{
- extern const u8 net_cdp_ethaddr[ARP_HLEN];
-
- return memcmp(ethaddr, net_cdp_ethaddr, ARP_HLEN) == 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_SNTP)
-extern struct in_addr net_ntp_server; /* the ip address to NTP */
-extern int net_ntp_time_offset; /* offset time from UTC */
-#endif
-
-/* Initialize the network adapter */
-int net_init(void);
-int net_loop(enum proto_t);
-
-/* Load failed. Start again. */
-int net_start_again(void);
-
-/* Get size of the ethernet header when we send */
-int net_eth_hdr_size(void);
-
-/* Set ethernet header; returns the size of the header */
-int net_set_ether(uchar *xet, const uchar *dest_ethaddr, uint prot);
-int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
-
-/* Set IP header */
-void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
- u16 pkt_len, u8 proto);
-void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
- int sport, int len);
-
-/**
- * compute_ip_checksum() - Compute IP checksum
- *
- * @addr: Address to check (must be 16-bit aligned)
- * @nbytes: Number of bytes to check (normally a multiple of 2)
- * Return: 16-bit IP checksum
- */
-unsigned compute_ip_checksum(const void *addr, unsigned nbytes);
-
-/**
- * add_ip_checksums() - add two IP checksums
- *
- * @offset: Offset of first sum (if odd we do a byte-swap)
- * @sum: First checksum
- * @new_sum: New checksum to add
- * Return: updated 16-bit IP checksum
- */
-unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum);
-
-/**
- * ip_checksum_ok() - check if a checksum is correct
- *
- * This works by making sure the checksum sums to 0
- *
- * @addr: Address to check (must be 16-bit aligned)
- * @nbytes: Number of bytes to check (normally a multiple of 2)
- * Return: true if the checksum matches, false if not
- */
-int ip_checksum_ok(const void *addr, unsigned nbytes);
-
-/* Callbacks */
-rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */
-void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */
-rxhand_f *net_get_arp_handler(void); /* Get ARP RX packet handler */
-void net_set_arp_handler(rxhand_f *); /* Set ARP RX packet handler */
-bool arp_is_waiting(void); /* Waiting for ARP reply? */
-void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
-void net_set_timeout_handler(ulong, thand_f *);/* Set timeout handler */
-
-/* Network loop state */
-enum net_loop_state {
- NETLOOP_CONTINUE,
- NETLOOP_RESTART,
- NETLOOP_SUCCESS,
- NETLOOP_FAIL
-};
-extern enum net_loop_state net_state;
-
-static inline void net_set_state(enum net_loop_state state)
-{
- debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
- net_state = state;
-}
-
-/*
- * net_get_async_tx_pkt_buf - Get a packet buffer that is not in use for
- * sending an asynchronous reply
- *
- * returns - ptr to packet buffer
- */
-uchar * net_get_async_tx_pkt_buf(void);
-
-/* Transmit a packet */
-static inline void net_send_packet(uchar *pkt, int len)
-{
- if (DEBUG_NET_PKT_TRACE)
- print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len);
- /* Currently no way to return errors from eth_send() */
- (void) eth_send(pkt, len);
-}
-
-/**
- * net_send_ip_packet() - Transmit "net_tx_packet" as UDP or TCP packet,
- * send ARP request if needed (ether will be populated)
- * @ether: Raw packet buffer
- * @dest: IP address to send the datagram to
- * @dport: Destination UDP port
- * @sport: Source UDP port
- * @payload_len: Length of data after the UDP header
- * @action: TCP action to be performed
- * @tcp_seq_num: TCP sequence number of this transmission
- * @tcp_ack_num: TCP stream acknolegement number
- *
- * Return: 0 on success, other value on failure
- */
-int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
- int payload_len, int proto, u8 action, u32 tcp_seq_num,
- u32 tcp_ack_num);
-/**
- * net_send_tcp_packet() - Transmit TCP packet.
- * @payload_len: length of payload
- * @dport: Destination TCP port
- * @sport: Source TCP port
- * @action: TCP action to be performed
- * @tcp_seq_num: TCP sequence number of this transmission
- * @tcp_ack_num: TCP stream acknolegement number
- *
- * Return: 0 on success, other value on failure
- */
-int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action,
- u32 tcp_seq_num, u32 tcp_ack_num);
-int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
- int sport, int payload_len);
-
-/* Processes a received packet */
-void net_process_received_packet(uchar *in_packet, int len);
-
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
-void nc_start(void);
-int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
- unsigned src_port, unsigned len);
-#endif
-
-static __always_inline int eth_is_on_demand_init(void)
-{
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
- extern enum proto_t net_loop_last_protocol;
-
- return net_loop_last_protocol != NETCONS;
-#else
- return 1;
-#endif
-}
-
-static inline void eth_set_last_protocol(int protocol)
-{
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD)
- extern enum proto_t net_loop_last_protocol;
-
- net_loop_last_protocol = protocol;
-#endif
-}
-
-/*
- * Check if autoload is enabled. If so, use either NFS or TFTP to download
- * the boot file.
- */
-void net_auto_load(void);
-
-/*
- * The following functions are a bit ugly, but necessary to deal with
- * alignment restrictions on ARM.
- *
- * We're using inline functions, which had the smallest memory
- * footprint in our tests.
- */
-/* return IP *in network byteorder* */
-static inline struct in_addr net_read_ip(void *from)
-{
- struct in_addr ip;
-
- memcpy((void *)&ip, (void *)from, sizeof(ip));
- return ip;
-}
-
-/* return ulong *in network byteorder* */
-static inline u32 net_read_u32(void *from)
-{
- u32 l;
-
- memcpy((void *)&l, (void *)from, sizeof(l));
- return l;
-}
-
-/* write IP *in network byteorder* */
-static inline void net_write_ip(void *to, struct in_addr ip)
-{
- memcpy(to, (void *)&ip, sizeof(ip));
-}
-
-/* copy IP */
-static inline void net_copy_ip(void *to, void *from)
-{
- memcpy((void *)to, from, sizeof(struct in_addr));
-}
-
-/* copy ulong */
-static inline void net_copy_u32(void *to, void *from)
-{
- memcpy((void *)to, (void *)from, sizeof(u32));
-}
-
-/**
- * is_zero_ethaddr - Determine if give Ethernet address is all zeros.
- * @addr: Pointer to a six-byte array containing the Ethernet address
- *
- * Return true if the address is all zeroes.
- */
-static inline int is_zero_ethaddr(const u8 *addr)
-{
- return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
-}
-
-/**
- * is_multicast_ethaddr - Determine if the Ethernet address is a multicast.
- * @addr: Pointer to a six-byte array containing the Ethernet address
- *
- * Return true if the address is a multicast address.
- * By definition the broadcast address is also a multicast address.
- */
-static inline int is_multicast_ethaddr(const u8 *addr)
-{
- return 0x01 & addr[0];
-}
-
-/*
- * is_broadcast_ethaddr - Determine if the Ethernet address is broadcast
- * @addr: Pointer to a six-byte array containing the Ethernet address
- *
- * Return true if the address is the broadcast address.
- */
-static inline int is_broadcast_ethaddr(const u8 *addr)
-{
- return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) ==
- 0xff;
-}
-
-/*
- * is_valid_ethaddr - Determine if the given Ethernet address is valid
- * @addr: Pointer to a six-byte array containing the Ethernet address
- *
- * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
- * a multicast address, and is not FF:FF:FF:FF:FF:FF.
- *
- * Return true if the address is valid.
- */
-static inline int is_valid_ethaddr(const u8 *addr)
-{
- /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
- * explicitly check for it here. */
- return !is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr);
-}
-
-/**
- * net_random_ethaddr - Generate software assigned random Ethernet address
- * @addr: Pointer to a six-byte array containing the Ethernet address
- *
- * Generate a random Ethernet address (MAC) that is not multicast
- * and has the local assigned bit set.
- */
-static inline void net_random_ethaddr(uchar *addr)
-{
- int i;
- unsigned int seed = get_ticks();
-
- for (i = 0; i < 6; i++)
- addr[i] = rand_r(&seed);
-
- addr[0] &= 0xfe; /* clear multicast bit */
- addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
-}
-
-/**
- * string_to_enetaddr() - Parse a MAC address
- *
- * Convert a string MAC address
- *
- * Implemented in lib/net_utils.c (built unconditionally)
- *
- * @addr: MAC address in aa:bb:cc:dd:ee:ff format, where each part is a 2-digit
- * hex value
- * @enetaddr: Place to put MAC address (6 bytes)
- */
-void string_to_enetaddr(const char *addr, uint8_t *enetaddr);
-
-/* Convert an IP address to a string */
-void ip_to_string(struct in_addr x, char *s);
-
-/**
- * string_to_ip() - Convert a string to ip address
- *
- * Implemented in lib/net_utils.c (built unconditionally)
- *
- * @s: Input string to parse
- * @return: in_addr struct containing the parsed IP address
- */
-struct in_addr string_to_ip(const char *s);
-
-/* Convert a VLAN id to a string */
-void vlan_to_string(ushort x, char *s);
-
-/* Convert a string to a vlan id */
-ushort string_to_vlan(const char *s);
-
-/* read a VLAN id from an environment variable */
-ushort env_get_vlan(char *);
-
-/* copy a filename (allow for "..." notation, limit length) */
-void copy_filename(char *dst, const char *src, int size);
-
-/* check if serverip is specified in filename from the command line */
-int is_serverip_in_cmd(void);
-
-/**
- * net_parse_bootfile - Parse the bootfile env var / cmd line param
- *
- * @param ipaddr - a pointer to the ipaddr to populate if included in bootfile
- * @param filename - a pointer to the string to save the filename part
- * @param max_len - The longest - 1 that the filename part can be
- *
- * return 1 if parsed, 0 if bootfile is empty
- */
-int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
-
-/**
- * update_tftp - Update firmware over TFTP (via DFU)
- *
- * This function updates board's firmware via TFTP
- *
- * @param addr - memory address where data is stored
- * @param interface - the DFU medium name - e.g. "mmc"
- * @param devstring - the DFU medium number - e.g. "1"
- *
- * Return: - 0 on success, other value on failure
- */
-int update_tftp(ulong addr, char *interface, char *devstring);
-
-/**
- * env_get_ip() - Convert an environment value to to an ip address
- *
- * @var: Environment variable to convert. The value of this variable must be
- * in the format format a.b.c.d, where each value is a decimal number from
- * 0 to 255
- * Return: IP address, or 0 if invalid
- */
-static inline struct in_addr env_get_ip(char *var)
-{
- return string_to_ip(env_get(var));
-}
-
-/**
- * reset_phy() - Reset the Ethernet PHY
- *
- * This should be implemented by boards if CONFIG_RESET_PHY_R is enabled
- */
-void reset_phy(void);
-
-#if CONFIG_IS_ENABLED(NET)
-/**
- * eth_set_enable_bootdevs() - Enable or disable binding of Ethernet bootdevs
- *
- * These get in the way of bootstd testing, so are normally disabled by tests.
- * This provide control of this setting. It only affects binding of Ethernet
- * devices, so if that has already happened, this flag does nothing.
- *
- * @enable: true to enable binding of bootdevs when binding new Ethernet
- * devices, false to disable it
- */
-void eth_set_enable_bootdevs(bool enable);
-#else
-static inline void eth_set_enable_bootdevs(bool enable) {}
-#endif
-
-/**
- * wget_with_dns() - runs dns host IP address resulution before wget
- *
- * @dst_addr: destination address to download the file
- * @uri: uri string of target file of wget
- * Return: downloaded file size, negative if failed
- */
-int wget_with_dns(ulong dst_addr, char *uri);
-
-/**
- * wget_validate_uri() - varidate the uri
- *
- * @uri: uri string of target file of wget
- * Return: true if uri is valid, false if uri is invalid
- */
-bool wget_validate_uri(char *uri);
#endif /* __NET_H__ */
diff --git a/include/serial.h b/include/serial.h
index d129dc3..e5f6d98 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -124,6 +124,7 @@
enum serial_chip_type {
SERIAL_CHIP_UNKNOWN = -1,
SERIAL_CHIP_16550_COMPATIBLE,
+ SERIAL_CHIP_PL01X,
};
enum adr_space_type {
@@ -298,9 +299,11 @@
struct serial_dev_priv {
struct stdio_dev *sdev;
- char *buf;
- int rd_ptr;
- int wr_ptr;
+#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
+ char buf[CONFIG_SERIAL_RX_BUFFER_SIZE];
+ uint rd_ptr;
+ uint wr_ptr;
+#endif
};
/* Access the serial operations for a device */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 10d19fd..2e703e8 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -139,6 +139,40 @@
void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs);
#else
+/* Compatibility functions for when DM_SPI_FLASH is disabled */
+static inline int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+ struct udevice **devp)
+{
+ return -ENODEV;
+}
+
+static inline int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ return -ENODEV;
+}
+
+static inline int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ return -ENODEV;
+}
+
+static inline int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len)
+{
+ return -ENODEV;
+}
+
+static inline int spl_flash_get_sw_write_prot(struct udevice *dev)
+{
+ return -ENODEV;
+}
+
+static inline int spi_flash_std_probe(struct udevice *dev)
+{
+ return -ENODEV;
+}
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
diff --git a/include/test/cedit-test.h b/include/test/cedit-test.h
index 475ecc9..0d38a95 100644
--- a/include/test/cedit-test.h
+++ b/include/test/cedit-test.h
@@ -9,24 +9,24 @@
#ifndef __cedit_test_h
#define __cedit_test_h
-#define ID_PROMPT 1
-#define ID_SCENE1 2
-#define ID_SCENE1_TITLE 3
+#define ID_PROMPT 5
+#define ID_SCENE1 6
+#define ID_SCENE1_TITLE 7
-#define ID_CPU_SPEED 4
-#define ID_CPU_SPEED_TITLE 5
-#define ID_CPU_SPEED_1 6
-#define ID_CPU_SPEED_2 7
-#define ID_CPU_SPEED_3 8
+#define ID_CPU_SPEED 8
+#define ID_CPU_SPEED_TITLE 9
+#define ID_CPU_SPEED_1 10
+#define ID_CPU_SPEED_2 11
+#define ID_CPU_SPEED_3 12
-#define ID_POWER_LOSS 9
-#define ID_AC_OFF 10
-#define ID_AC_ON 11
-#define ID_AC_MEMORY 12
+#define ID_POWER_LOSS 13
+#define ID_AC_OFF 14
+#define ID_AC_ON 15
+#define ID_AC_MEMORY 16
-#define ID_MACHINE_NAME 13
-#define ID_MACHINE_NAME_EDIT 14
+#define ID_MACHINE_NAME 17
+#define ID_MACHINE_NAME_EDIT 18
-#define ID_DYNAMIC_START 15
+#define ID_DYNAMIC_START 19
#endif
diff --git a/include/test/test.h b/include/test/test.h
index 92eec2e..21c0478 100644
--- a/include/test/test.h
+++ b/include/test/test.h
@@ -29,6 +29,7 @@
* @of_other: Live tree for the other FDT
* @runs_per_test: Number of times to run each test (typically 1)
* @force_run: true to run tests marked with the UTF_MANUAL flag
+ * @old_bloblist: stores the old gd->bloblist pointer
* @expect_str: Temporary string used to hold expected string value
* @actual_str: Temporary string used to hold actual string value
*/
@@ -50,6 +51,7 @@
struct device_node *of_other;
int runs_per_test;
bool force_run;
+ void *old_bloblist;
char expect_str[512];
char actual_str[512];
};
@@ -73,6 +75,7 @@
UTF_MANUAL = BIT(8),
UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */
UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */
+ UFT_BLOBLIST = BIT(11), /* test changes gd->bloblist */
};
/**
diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h
index 8f9f5e7..f0ac0f3 100644
--- a/include/u-boot/ecdsa.h
+++ b/include/u-boot/ecdsa.h
@@ -65,6 +65,7 @@
/** @} */
#define ECDSA256_BYTES (256 / 8)
+#define ECDSA384_BYTES (384 / 8)
#define ECDSA521_BYTES ((521 + 7) / 8)
#endif
diff --git a/include/u-boot/schedule.h b/include/u-boot/schedule.h
new file mode 100644
index 0000000..4fd34c4
--- /dev/null
+++ b/include/u-boot/schedule.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _U_BOOT_SCHEDULE_H
+#define _U_BOOT_SCHEDULE_H
+
+#if CONFIG_IS_ENABLED(CYCLIC)
+/**
+ * schedule() - Schedule all potentially waiting tasks
+ *
+ * Run all pending tasks registered via the cyclic framework, and
+ * potentially perform other actions that need to be done
+ * periodically.
+ */
+void schedule(void);
+
+#else
+
+static inline void schedule(void)
+{
+}
+
+#endif
+
+#endif
diff --git a/include/usb/pd.h b/include/usb/pd.h
new file mode 100644
index 0000000..cacda32
--- /dev/null
+++ b/include/usb/pd.h
@@ -0,0 +1,516 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_H
+#define __LINUX_USB_PD_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+enum typec_port_type {
+ TYPEC_PORT_SRC,
+ TYPEC_PORT_SNK,
+ TYPEC_PORT_DRP,
+};
+
+enum typec_data_role {
+ TYPEC_DEVICE,
+ TYPEC_HOST,
+};
+
+enum typec_role {
+ TYPEC_SINK,
+ TYPEC_SOURCE,
+};
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+ /* 0 Reserved */
+ PD_CTRL_GOOD_CRC = 1,
+ PD_CTRL_GOTO_MIN = 2,
+ PD_CTRL_ACCEPT = 3,
+ PD_CTRL_REJECT = 4,
+ PD_CTRL_PING = 5,
+ PD_CTRL_PS_RDY = 6,
+ PD_CTRL_GET_SOURCE_CAP = 7,
+ PD_CTRL_GET_SINK_CAP = 8,
+ PD_CTRL_DR_SWAP = 9,
+ PD_CTRL_PR_SWAP = 10,
+ PD_CTRL_VCONN_SWAP = 11,
+ PD_CTRL_WAIT = 12,
+ PD_CTRL_SOFT_RESET = 13,
+ /* 14-15 Reserved */
+ PD_CTRL_NOT_SUPP = 16,
+ PD_CTRL_GET_SOURCE_CAP_EXT = 17,
+ PD_CTRL_GET_STATUS = 18,
+ PD_CTRL_FR_SWAP = 19,
+ PD_CTRL_GET_PPS_STATUS = 20,
+ PD_CTRL_GET_COUNTRY_CODES = 21,
+ /* 22-31 Reserved */
+};
+
+enum pd_data_msg_type {
+ /* 0 Reserved */
+ PD_DATA_SOURCE_CAP = 1,
+ PD_DATA_REQUEST = 2,
+ PD_DATA_BIST = 3,
+ PD_DATA_SINK_CAP = 4,
+ PD_DATA_BATT_STATUS = 5,
+ PD_DATA_ALERT = 6,
+ PD_DATA_GET_COUNTRY_INFO = 7,
+ PD_DATA_ENTER_USB = 8,
+ /* 9-14 Reserved */
+ PD_DATA_VENDOR_DEF = 15,
+ /* 16-31 Reserved */
+};
+
+enum pd_ext_msg_type {
+ /* 0 Reserved */
+ PD_EXT_SOURCE_CAP_EXT = 1,
+ PD_EXT_STATUS = 2,
+ PD_EXT_GET_BATT_CAP = 3,
+ PD_EXT_GET_BATT_STATUS = 4,
+ PD_EXT_BATT_CAP = 5,
+ PD_EXT_GET_MANUFACTURER_INFO = 6,
+ PD_EXT_MANUFACTURER_INFO = 7,
+ PD_EXT_SECURITY_REQUEST = 8,
+ PD_EXT_SECURITY_RESPONSE = 9,
+ PD_EXT_FW_UPDATE_REQUEST = 10,
+ PD_EXT_FW_UPDATE_RESPONSE = 11,
+ PD_EXT_PPS_STATUS = 12,
+ PD_EXT_COUNTRY_INFO = 13,
+ PD_EXT_COUNTRY_CODES = 14,
+ /* 15-31 Reserved */
+};
+
+#define PD_REV10 0x0
+#define PD_REV20 0x1
+#define PD_REV30 0x2
+#define PD_MAX_REV PD_REV30
+
+#define PD_HEADER_EXT_HDR BIT(15)
+#define PD_HEADER_CNT_SHIFT 12
+#define PD_HEADER_CNT_MASK 0x7
+#define PD_HEADER_ID_SHIFT 9
+#define PD_HEADER_ID_MASK 0x7
+#define PD_HEADER_PWR_ROLE BIT(8)
+#define PD_HEADER_REV_SHIFT 6
+#define PD_HEADER_REV_MASK 0x3
+#define PD_HEADER_DATA_ROLE BIT(5)
+#define PD_HEADER_TYPE_SHIFT 0
+#define PD_HEADER_TYPE_MASK 0x1f
+
+#define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr) \
+ ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \
+ ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \
+ ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \
+ ((rev) << PD_HEADER_REV_SHIFT) | \
+ (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \
+ (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT) | \
+ ((ext_hdr) ? PD_HEADER_EXT_HDR : 0))
+
+#define PD_HEADER_LE(type, pwr, data, rev, id, cnt) \
+ cpu_to_le16(PD_HEADER((type), (pwr), (data), (rev), (id), (cnt), (0)))
+
+static inline unsigned int pd_header_cnt(u16 header)
+{
+ return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+ return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(u16 header)
+{
+ return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+ return pd_header_type(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_msgid(u16 header)
+{
+ return (header >> PD_HEADER_ID_SHIFT) & PD_HEADER_ID_MASK;
+}
+
+static inline unsigned int pd_header_msgid_le(__le16 header)
+{
+ return pd_header_msgid(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_rev(u16 header)
+{
+ return (header >> PD_HEADER_REV_SHIFT) & PD_HEADER_REV_MASK;
+}
+
+static inline unsigned int pd_header_rev_le(__le16 header)
+{
+ return pd_header_rev(le16_to_cpu(header));
+}
+
+#define PD_EXT_HDR_CHUNKED BIT(15)
+#define PD_EXT_HDR_CHUNK_NUM_SHIFT 11
+#define PD_EXT_HDR_CHUNK_NUM_MASK 0xf
+#define PD_EXT_HDR_REQ_CHUNK BIT(10)
+#define PD_EXT_HDR_DATA_SIZE_SHIFT 0
+#define PD_EXT_HDR_DATA_SIZE_MASK 0x1ff
+
+#define PD_EXT_HDR(data_size, req_chunk, chunk_num, chunked) \
+ ((((data_size) & PD_EXT_HDR_DATA_SIZE_MASK) << PD_EXT_HDR_DATA_SIZE_SHIFT) | \
+ ((req_chunk) ? PD_EXT_HDR_REQ_CHUNK : 0) | \
+ (((chunk_num) & PD_EXT_HDR_CHUNK_NUM_MASK) << PD_EXT_HDR_CHUNK_NUM_SHIFT) | \
+ ((chunked) ? PD_EXT_HDR_CHUNKED : 0))
+
+#define PD_EXT_HDR_LE(data_size, req_chunk, chunk_num, chunked) \
+ cpu_to_le16(PD_EXT_HDR((data_size), (req_chunk), (chunk_num), (chunked)))
+
+static inline unsigned int pd_ext_header_chunk_num(u16 ext_header)
+{
+ return (ext_header >> PD_EXT_HDR_CHUNK_NUM_SHIFT) &
+ PD_EXT_HDR_CHUNK_NUM_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size(u16 ext_header)
+{
+ return (ext_header >> PD_EXT_HDR_DATA_SIZE_SHIFT) &
+ PD_EXT_HDR_DATA_SIZE_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size_le(__le16 ext_header)
+{
+ return pd_ext_header_data_size(le16_to_cpu(ext_header));
+}
+
+#define PD_MAX_PAYLOAD 7
+#define PD_EXT_MAX_CHUNK_DATA 26
+
+/*
+ * struct pd_chunked_ext_message_data - PD chunked extended message data as
+ * seen on wire
+ * @header: PD extended message header
+ * @data: PD extended message data
+ */
+struct pd_chunked_ext_message_data {
+ __le16 header;
+ u8 data[PD_EXT_MAX_CHUNK_DATA];
+} __packed;
+
+/*
+ * struct pd_message - PD message as seen on wire
+ * @header: PD message header
+ * @payload: PD message payload
+ * @ext_msg: PD message chunked extended message data
+ */
+struct pd_message {
+ __le16 header;
+ union {
+ __le32 payload[PD_MAX_PAYLOAD];
+ struct pd_chunked_ext_message_data ext_msg;
+ };
+} __packed;
+
+/* PDO: Power Data Object */
+#define PDO_MAX_OBJECTS 7
+
+enum pd_pdo_type {
+ PDO_TYPE_FIXED = 0,
+ PDO_TYPE_BATT = 1,
+ PDO_TYPE_VAR = 2,
+ PDO_TYPE_APDO = 3,
+};
+
+#define PDO_TYPE_SHIFT 30
+#define PDO_TYPE_MASK 0x3
+
+#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK 0x3ff
+#define PDO_CURR_MASK 0x3ff
+#define PDO_PWR_MASK 0x3ff
+
+#define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */
+#define PDO_FIXED_UNCHUNK_EXT BIT(24) /* Unchunked Extended Message supported (Source) */
+#define PDO_FIXED_FRS_CURR_MASK (BIT(24) | BIT(23)) /* FR_Swap Current (Sink) */
+#define PDO_FIXED_FRS_CURR_SHIFT 23
+#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags) \
+ (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \
+ PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw) \
+ (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \
+ PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \
+ PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+enum pd_apdo_type {
+ APDO_TYPE_PPS = 0,
+};
+
+#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK 0x3
+
+#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK 0xff
+#define PDO_PPS_APDO_CURR_MASK 0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma) \
+ ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \
+ PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \
+ PDO_PPS_APDO_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(u32 pdo)
+{
+ return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(u32 pdo)
+{
+ return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+static inline enum pd_apdo_type pdo_apdo_type(u32 pdo)
+{
+ return (pdo >> PDO_APDO_TYPE_SHIFT) & PDO_APDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_pps_apdo_min_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MIN_VOLT_SHIFT) &
+ PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MAX_VOLT_SHIFT) &
+ PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_current(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MAX_CURR_SHIFT) &
+ PDO_PPS_APDO_CURR_MASK) * 50;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT 28
+#define RDO_OBJ_POS_MASK 0x7
+#define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */
+#define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK 0x3ff
+#define RDO_CURR_MASK 0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT 10
+#define RDO_FIXED_MAX_CURR_SHIFT 0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+#define RDO_PROG_VOLT_MASK 0x7ff
+#define RDO_PROG_CURR_MASK 0x7f
+
+#define RDO_PROG_VOLT_SHIFT 9
+#define RDO_PROG_CURR_SHIFT 0
+
+#define RDO_PROG_VOLT_MV_STEP 20
+#define RDO_PROG_CURR_MA_STEP 50
+
+#define PDO_PROG_OUT_VOLT(mv) \
+ ((((mv) / RDO_PROG_VOLT_MV_STEP) & RDO_PROG_VOLT_MASK) << RDO_PROG_VOLT_SHIFT)
+#define PDO_PROG_OP_CURR(ma) \
+ ((((ma) / RDO_PROG_CURR_MA_STEP) & RDO_PROG_CURR_MASK) << RDO_PROG_CURR_SHIFT)
+
+#define RDO_PROG(idx, out_mv, op_ma, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ PDO_PROG_OUT_VOLT(out_mv) | PDO_PROG_OP_CURR(op_ma))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+ return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+ return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+ return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+ RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+ return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+ return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+/* Enter_USB Data Object */
+#define EUDO_USB_MODE_MASK GENMASK(30, 28)
+#define EUDO_USB_MODE_SHIFT 28
+#define EUDO_USB_MODE_USB2 0
+#define EUDO_USB_MODE_USB3 1
+#define EUDO_USB_MODE_USB4 2
+#define EUDO_USB4_DRD BIT(26)
+#define EUDO_USB3_DRD BIT(25)
+#define EUDO_CABLE_SPEED_MASK GENMASK(23, 21)
+#define EUDO_CABLE_SPEED_SHIFT 21
+#define EUDO_CABLE_SPEED_USB2 0
+#define EUDO_CABLE_SPEED_USB3_GEN1 1
+#define EUDO_CABLE_SPEED_USB4_GEN2 2
+#define EUDO_CABLE_SPEED_USB4_GEN3 3
+#define EUDO_CABLE_TYPE_MASK GENMASK(20, 19)
+#define EUDO_CABLE_TYPE_SHIFT 19
+#define EUDO_CABLE_TYPE_PASSIVE 0
+#define EUDO_CABLE_TYPE_RE_TIMER 1
+#define EUDO_CABLE_TYPE_RE_DRIVER 2
+#define EUDO_CABLE_TYPE_OPTICAL 3
+#define EUDO_CABLE_CURRENT_MASK GENMASK(18, 17)
+#define EUDO_CABLE_CURRENT_SHIFT 17
+#define EUDO_CABLE_CURRENT_NOTSUPP 0
+#define EUDO_CABLE_CURRENT_3A 2
+#define EUDO_CABLE_CURRENT_5A 3
+#define EUDO_PCIE_SUPPORT BIT(16)
+#define EUDO_DP_SUPPORT BIT(15)
+#define EUDO_TBT_SUPPORT BIT(14)
+#define EUDO_HOST_PRESENT BIT(13)
+
+/* USB PD timers and counters */
+#define PD_T_NO_RESPONSE 5000 /* 4.5 - 5.5 seconds */
+#define PD_T_DB_DETECT 10000 /* 10 - 15 seconds */
+#define PD_T_SEND_SOURCE_CAP 150 /* 100 - 200 ms */
+#define PD_T_SENDER_RESPONSE 60 /* 24 - 30 ms, relaxed */
+#define PD_T_RECEIVER_RESPONSE 15 /* 15ms max */
+#define PD_T_SOURCE_ACTIVITY 45
+#define PD_T_SINK_ACTIVITY 135
+#define PD_T_SINK_WAIT_CAP 310 /* 310 - 620 ms */
+#define PD_T_PS_TRANSITION 500
+#define PD_T_SRC_TRANSITION 35
+#define PD_T_DRP_SNK 40
+#define PD_T_DRP_SRC 30
+#define PD_T_PS_SOURCE_OFF 920
+#define PD_T_PS_SOURCE_ON 480
+#define PD_T_PS_SOURCE_ON_PRS 450 /* 390 - 480ms */
+#define PD_T_PS_HARD_RESET 30
+#define PD_T_SRC_RECOVER 760
+#define PD_T_SRC_RECOVER_MAX 1000
+#define PD_T_SRC_TURN_ON 275
+#define PD_T_SAFE_0V 650
+#define PD_T_VCONN_SOURCE_ON 100
+#define PD_T_SINK_REQUEST 100 /* 100 ms minimum */
+#define PD_T_ERROR_RECOVERY 100 /* minimum 25 is insufficient */
+#define PD_T_SRCSWAPSTDBY 625 /* Maximum of 650ms */
+#define PD_T_NEWSRC 250 /* Maximum of 275ms */
+#define PD_T_SWAP_SRC_START 20 /* Minimum of 20ms */
+#define PD_T_BIST_CONT_MODE 50 /* 30 - 60 ms */
+#define PD_T_SINK_TX 16 /* 16 - 20 ms */
+#define PD_T_CHUNK_NOT_SUPP 42 /* 40 - 50 ms */
+
+#define PD_T_DRP_TRY 100 /* 75 - 150 ms */
+#define PD_T_DRP_TRYWAIT 600 /* 400 - 800 ms */
+
+#define PD_T_CC_DEBOUNCE 200 /* 100 - 200 ms */
+#define PD_T_PD_DEBOUNCE 20 /* 10 - 20 ms */
+#define PD_T_TRY_CC_DEBOUNCE 15 /* 10 - 20 ms */
+
+#define PD_N_CAPS_COUNT (PD_T_NO_RESPONSE / PD_T_SEND_SOURCE_CAP)
+#define PD_N_HARD_RESET_COUNT 1
+
+#define PD_P_SNK_STDBY_MW 2500 /* 2500 mW */
+
+/* Time to wait for TCPC to complete transmit */
+#define PD_T_TCPC_TX_TIMEOUT 100 /* in ms */
+
+#endif /* __LINUX_USB_PD_H */
diff --git a/include/usb/tcpm.h b/include/usb/tcpm.h
new file mode 100644
index 0000000..10f0515
--- /dev/null
+++ b/include/usb/tcpm.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ * Copyright 2024 Collabora
+ */
+
+#ifndef __LINUX_USB_TCPM_H
+#define __LINUX_USB_TCPM_H
+
+#include <dm/of.h>
+#include <linux/bitops.h>
+#include "pd.h"
+
+enum typec_orientation {
+ TYPEC_ORIENTATION_NONE,
+ TYPEC_ORIENTATION_NORMAL,
+ TYPEC_ORIENTATION_REVERSE,
+};
+
+enum typec_cc_status {
+ TYPEC_CC_OPEN,
+ TYPEC_CC_RA,
+ TYPEC_CC_RD,
+ TYPEC_CC_RP_DEF,
+ TYPEC_CC_RP_1_5,
+ TYPEC_CC_RP_3_0,
+};
+
+enum typec_cc_polarity {
+ TYPEC_POLARITY_CC1,
+ TYPEC_POLARITY_CC2,
+};
+
+enum tcpm_transmit_status {
+ TCPC_TX_SUCCESS = 0,
+ TCPC_TX_DISCARDED = 1,
+ TCPC_TX_FAILED = 2,
+};
+
+enum tcpm_transmit_type {
+ TCPC_TX_SOP = 0,
+ TCPC_TX_SOP_PRIME = 1,
+ TCPC_TX_SOP_PRIME_PRIME = 2,
+ TCPC_TX_SOP_DEBUG_PRIME = 3,
+ TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
+ TCPC_TX_HARD_RESET = 5,
+ TCPC_TX_CABLE_RESET = 6,
+ TCPC_TX_BIST_MODE_2 = 7
+};
+
+struct dm_tcpm_ops {
+ int (*get_connector_node)(struct udevice *dev, ofnode *connector_node);
+ int (*init)(struct udevice *dev);
+ int (*get_vbus)(struct udevice *dev);
+ int (*set_cc)(struct udevice *dev, enum typec_cc_status cc);
+ int (*get_cc)(struct udevice *dev, enum typec_cc_status *cc1,
+ enum typec_cc_status *cc2);
+ int (*set_polarity)(struct udevice *dev,
+ enum typec_cc_polarity polarity);
+ int (*set_vconn)(struct udevice *dev, bool on);
+ int (*set_vbus)(struct udevice *dev, bool on, bool charge);
+ int (*set_pd_rx)(struct udevice *dev, bool on);
+ int (*set_roles)(struct udevice *dev, bool attached,
+ enum typec_role role, enum typec_data_role data);
+ int (*start_toggling)(struct udevice *dev,
+ enum typec_port_type port_type,
+ enum typec_cc_status cc);
+ int (*pd_transmit)(struct udevice *dev, enum tcpm_transmit_type type,
+ const struct pd_message *msg, unsigned int negotiated_rev);
+ void (*poll_event)(struct udevice *dev);
+ int (*enter_low_power_mode)(struct udevice *dev, bool attached, bool pd_capable);
+};
+
+/* API for drivers */
+void tcpm_vbus_change(struct udevice *dev);
+void tcpm_cc_change(struct udevice *dev);
+void tcpm_pd_receive(struct udevice *dev, const struct pd_message *msg);
+void tcpm_pd_transmit_complete(struct udevice *dev,
+ enum tcpm_transmit_status status);
+void tcpm_pd_hard_reset(struct udevice *dev);
+
+/* API for boards */
+extern const char * const typec_pd_rev_name[];
+extern const char * const typec_orientation_name[];
+extern const char * const typec_role_name[];
+extern const char * const typec_data_role_name[];
+extern const char * const typec_cc_status_name[];
+
+int tcpm_get(int index, struct udevice **devp);
+int tcpm_get_pd_rev(struct udevice *dev);
+int tcpm_get_current(struct udevice *dev);
+int tcpm_get_voltage(struct udevice *dev);
+enum typec_orientation tcpm_get_orientation(struct udevice *dev);
+enum typec_role tcpm_get_pwr_role(struct udevice *dev);
+enum typec_data_role tcpm_get_data_role(struct udevice *dev);
+bool tcpm_is_connected(struct udevice *dev);
+const char *tcpm_get_state(struct udevice *dev);
+
+#endif /* __LINUX_USB_TCPM_H */
diff --git a/include/video.h b/include/video.h
index 606c8a3..4ec71ab 100644
--- a/include/video.h
+++ b/include/video.h
@@ -57,12 +57,8 @@
VIDEO_BPP32,
};
-/*
- * Convert enum video_log2_bpp to bytes and bits. Note we omit the outer
- * brackets to allow multiplication by fractional pixels.
- */
+/* Convert enum video_log2_bpp to bytes and bits */
#define VNBYTES(bpix) ((1 << (bpix)) / 8)
-
#define VNBITS(bpix) (1 << (bpix))
enum video_format {
@@ -78,7 +74,8 @@
*
* @xsize: Number of pixel columns (e.g. 1366)
* @ysize: Number of pixels rows (e.g.. 768)
- * @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.)
+ * @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.). THis
+ * does not affect @xsize and @ysize
* @bpix: Encoded bits per pixel (enum video_log2_bpp)
* @format: Pixel format (enum video_format)
* @vidconsole_drv_name: Driver to use for the text console, NULL to
@@ -181,6 +178,7 @@
VID_LIGHT_MAGENTA,
VID_LIGHT_CYAN,
VID_WHITE,
+ VID_DARK_GREY,
VID_COLOUR_COUNT
};
diff --git a/include/video_console.h b/include/video_console.h
index 8b5928d..723d231 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -27,6 +27,14 @@
* Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe()
* method. Drivers may set up @xstart_frac if desired.
*
+ * Note that these values relate to the rotated console, so that an 80x25
+ * console which is rotated 90 degrees will have rows=80 and cols=25
+ *
+ * The xcur_frac and ycur values refer to the unrotated coordinates, that is
+ * xcur_frac always advances with each character, even if its limit might be
+ * vid_priv->ysize instead of vid_priv->xsize if the console is rotated 90 or
+ * 270 degrees.
+ *
* @sdev: stdio device, acting as an output sink
* @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
* @ycur: Current Y position in pixels (0=top)
diff --git a/include/watchdog.h b/include/watchdog.h
index d1956fa..0149b44 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -10,7 +10,7 @@
#ifndef _WATCHDOG_H_
#define _WATCHDOG_H_
-#include <cyclic.h>
+#include <u-boot/schedule.h> // to be removed later
/*
* Reset the watchdog timer, always returns 0
diff --git a/lib/Kconfig b/lib/Kconfig
index fc2db74..56ffdfa 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -315,6 +315,22 @@
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
+config ACPI_PARKING_PROTOCOL
+ bool "Support ACPI parking protocol method"
+ depends on GENERATE_ACPI_TABLE
+ depends on ARMV8_MULTIENTRY
+ depends on BLOBLIST_TABLES
+ default y if !SEC_FIRMWARE_ARMV8_PSCI && !ARMV8_PSCI
+ help
+ Say Y here to support "ACPI parking protocol" enable method
+ for booting Linux.
+
+ To use this feature, you must do:
+ - Bring secondary CPUs into U-Boot proper in a board-specific
+ manner. This must be done *after* relocation. Otherwise, the
+ secondary CPUs will spin in unprotected memory-area because the
+ master CPU protects the relocated spin code.
+
config SPL_TINY_MEMSET
bool "Use a very small memset() in SPL"
depends on SPL
@@ -988,12 +1004,15 @@
config BLOBLIST_TABLES
bool "Put tables in a bloblist"
- depends on X86 && BLOBLIST
+ depends on BLOBLIST
+ default y if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE)
+ default n
help
- Normally tables are placed at address 0xf0000 and can be up to 64KB
- long. With this option, tables are instead placed in the bloblist
- with a pointer from 0xf0000. The size can then be larger and the
- tables can be placed high in memory.
+ On x86 normally tables are placed at address 0xf0000 and can be up
+ to 64KB long. With this option, tables are instead placed in the
+ bloblist with a pointer from 0xf0000. The size can then be larger
+ and the tables can be placed high in memory.
+ On other architectures the tables are always placed in high memory.
config GENERATE_SMBIOS_TABLE
bool "Generate an SMBIOS (System Management BIOS) table"
diff --git a/lib/Makefile b/lib/Makefile
index 3fc428c..dbcfa87 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -99,6 +99,8 @@
obj-$(CONFIG_MBEDTLS_LIB) += mbedtls/
+obj-$(CONFIG_NET_LWIP) += lwip/
+
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16-ccitt.o
obj-$(CONFIG_$(PHASE_)HASH) += crc16-ccitt.o
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 6dbfdb2..150f750 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -5,15 +5,28 @@
* Copyright 2019 Google LLC
*/
-#include <dm.h>
+#include <bloblist.h>
#include <cpu.h>
+#include <dm.h>
+#include <efi_api.h>
+#include <efi_loader.h>
#include <log.h>
#include <mapmem.h>
#include <tables_csum.h>
+#include <serial.h>
#include <version_string.h>
#include <acpi/acpi_table.h>
+#include <acpi/acpi_device.h>
#include <asm/global_data.h>
#include <dm/acpi.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+
+enum {
+ TABLE_SIZE = SZ_64K,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* OEM_REVISION is 32-bit unsigned number. It should be increased only when
@@ -61,9 +74,9 @@
{
switch (table) {
case ACPITAB_FADT:
- return ACPI_FADT_REV_ACPI_3_0;
+ return ACPI_FADT_REV_ACPI_6_0;
case ACPITAB_MADT:
- return ACPI_MADT_REV_ACPI_3_0;
+ return ACPI_MADT_REV_ACPI_6_2;
case ACPITAB_MCFG:
return ACPI_MCFG_REV_ACPI_3_0;
case ACPITAB_TCPA:
@@ -105,6 +118,10 @@
return 1;
case ACPITAB_SPCR:
return 2;
+ case ACPITAB_PPTT: /* ACPI 6.2: 1 */
+ return 1;
+ case ACPITAB_GTDT: /* ACPI 6.2: 2, ACPI 6.3: 3 */
+ return 2;
default:
return -EINVAL;
}
@@ -151,55 +168,148 @@
struct acpi_rsdt *rsdt;
struct acpi_xsdt *xsdt;
- /* The RSDT is mandatory while the XSDT is not */
- rsdt = ctx->rsdt;
+ /* On legacy x86 platforms the RSDT is mandatory while the XSDT is not.
+ * On other platforms there might be no memory below 4GiB, thus RSDT is NULL.
+ */
+ if (ctx->rsdt) {
+ rsdt = ctx->rsdt;
+
+ /* This should always be MAX_ACPI_TABLES */
+ entries_num = ARRAY_SIZE(rsdt->entry);
+
+ for (i = 0; i < entries_num; i++) {
+ if (rsdt->entry[i] == 0)
+ break;
+ }
- /* This should always be MAX_ACPI_TABLES */
- entries_num = ARRAY_SIZE(rsdt->entry);
+ if (i >= entries_num) {
+ log_err("ACPI: Error: too many tables\n");
+ return -E2BIG;
+ }
- for (i = 0; i < entries_num; i++) {
- if (rsdt->entry[i] == 0)
- break;
+ /* Add table to the RSDT */
+ rsdt->entry[i] = nomap_to_sysmem(table);
+
+ /* Fix RSDT length or the kernel will assume invalid entries */
+ rsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u32) * (i + 1));
+
+ /* Re-calculate checksum */
+ rsdt->header.checksum = 0;
+ rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
+ rsdt->header.length);
}
- if (i >= entries_num) {
- log_err("ACPI: Error: too many tables\n");
- return -E2BIG;
+ if (ctx->xsdt) {
+ /*
+ * And now the same thing for the XSDT. We use the same index as for
+ * now we want the XSDT and RSDT to always be in sync in U-Boot
+ */
+ xsdt = ctx->xsdt;
+
+ /* This should always be MAX_ACPI_TABLES */
+ entries_num = ARRAY_SIZE(xsdt->entry);
+
+ for (i = 0; i < entries_num; i++) {
+ if (xsdt->entry[i] == 0)
+ break;
+ }
+
+ if (i >= entries_num) {
+ log_err("ACPI: Error: too many tables\n");
+ return -E2BIG;
+ }
+
+ /* Add table to the XSDT */
+ xsdt->entry[i] = nomap_to_sysmem(table);
+
+ /* Fix XSDT length */
+ xsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u64) * (i + 1));
+
+ /* Re-calculate checksum */
+ xsdt->header.checksum = 0;
+ xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
+ xsdt->header.length);
}
- /* Add table to the RSDT */
- rsdt->entry[i] = nomap_to_sysmem(table);
+ return 0;
+}
- /* Fix RSDT length or the kernel will assume invalid entries */
- rsdt->header.length = sizeof(struct acpi_table_header) +
- (sizeof(u32) * (i + 1));
+int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_fadt *fadt;
- /* Re-calculate checksum */
- rsdt->header.checksum = 0;
- rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
- rsdt->header.length);
+ fadt = ctx->current;
+ header = &fadt->header;
- /*
- * And now the same thing for the XSDT. We use the same index as for
- * now we want the XSDT and RSDT to always be in sync in U-Boot
- */
- xsdt = ctx->xsdt;
+ memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
- /* Add table to the XSDT */
- xsdt->entry[i] = nomap_to_sysmem(table);
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = acpi_get_table_revision(ACPITAB_FADT);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+ memcpy(header->creator_id, ASLC_ID, 4);
+ header->creator_revision = 1;
+ fadt->minor_revision = 2;
+
+ fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
+ fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
+
+ if (fadt->x_firmware_ctrl < 0x100000000ULL)
+ fadt->firmware_ctrl = fadt->x_firmware_ctrl;
+
+ if (fadt->x_dsdt < 0x100000000ULL)
+ fadt->dsdt = fadt->x_dsdt;
- /* Fix XSDT length */
- xsdt->header.length = sizeof(struct acpi_table_header) +
- (sizeof(u64) * (i + 1));
+ fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
- /* Re-calculate checksum */
- xsdt->header.checksum = 0;
- xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
- xsdt->header.length);
+ acpi_fill_fadt(fadt);
+
+ header->checksum = table_compute_checksum(fadt, header->length);
+
+ return acpi_add_fadt(ctx, fadt);
+}
+
+ACPI_WRITER(5fadt, "FADT", acpi_write_fadt, 0);
+
+int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_header *header;
+ struct acpi_madt *madt;
+ void *current;
+
+ madt = ctx->current;
+
+ memset(madt, '\0', sizeof(struct acpi_madt));
+ header = &madt->header;
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "APIC");
+ header->length = sizeof(struct acpi_madt);
+ header->revision = acpi_get_table_revision(ACPITAB_MADT);
+
+ acpi_inc(ctx, sizeof(struct acpi_madt));
+ /* TODO: Get rid of acpi_fill_madt and use driver model */
+ current = acpi_fill_madt(madt, ctx);
+
+ /* (Re)calculate length and checksum */
+ header->length = (uintptr_t)current - (uintptr_t)madt;
+
+ if (IS_ENABLED(CONFIG_ACPI_PARKING_PROTOCOL))
+ acpi_write_park(madt);
+
+ header->checksum = table_compute_checksum((void *)madt, header->length);
+ acpi_add_table(ctx, madt);
+ ctx->current = (void *)madt + madt->header.length;
return 0;
}
+ACPI_WRITER(5madt, "MADT", acpi_write_madt, 0);
+
void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
int port_type, int port_subtype,
struct acpi_gen_regaddr *address, u32 address_size,
@@ -262,3 +372,451 @@
header->length = current - (uintptr_t)dbg2;
header->checksum = table_compute_checksum(dbg2, header->length);
}
+
+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
+ uint access_size)
+{
+ struct acpi_dbg2_header *dbg2 = ctx->current;
+ char path[ACPI_PATH_MAX];
+ struct acpi_gen_regaddr address;
+ u64 addr;
+ int ret;
+
+ if (!device_active(dev)) {
+ log_info("Device not enabled\n");
+ return -EACCES;
+ }
+ /*
+ * PCI devices don't remember their resource allocation information in
+ * U-Boot at present. We assume that MMIO is used for the UART and that
+ * the address space is 32 bytes: ns16550 uses 8 registers of up to
+ * 32-bits each. This is only for debugging so it is not a big deal.
+ */
+ addr = dm_pci_read_bar32(dev, 0);
+ log_debug("UART addr %lx\n", (ulong)addr);
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+
+ memset(&address, '\0', sizeof(address));
+ address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ address.addrl = (uint32_t)addr;
+ address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
+ address.access_size = access_size;
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
+ ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
+
+ acpi_inc_align(ctx, dbg2->header.length);
+ acpi_add_table(ctx, dbg2);
+
+ return 0;
+}
+
+static int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct serial_device_info serial_info = {0};
+ u64 serial_address, serial_offset;
+ struct acpi_table_header *header;
+ struct acpi_spcr *spcr;
+ struct udevice *dev;
+ uint serial_config;
+ uint serial_width;
+ int access_size;
+ int space_id;
+ int ret = -ENODEV;
+
+ spcr = ctx->current;
+ header = &spcr->header;
+
+ memset(spcr, '\0', sizeof(struct acpi_spcr));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "SPCR");
+ header->length = sizeof(struct acpi_spcr);
+ header->revision = 2;
+
+ /* Read the device once, here. It is reused below */
+ dev = gd->cur_serial_dev;
+ if (dev)
+ ret = serial_getinfo(dev, &serial_info);
+ if (ret)
+ serial_info.type = SERIAL_CHIP_UNKNOWN;
+
+ /* Encode chip type */
+ switch (serial_info.type) {
+ case SERIAL_CHIP_16550_COMPATIBLE:
+ spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
+ break;
+ case SERIAL_CHIP_PL01X:
+ spcr->interface_type = ACPI_DBG2_ARM_PL011;
+ break;
+ case SERIAL_CHIP_UNKNOWN:
+ default:
+ spcr->interface_type = ACPI_DBG2_UNKNOWN;
+ break;
+ }
+
+ /* Encode address space */
+ switch (serial_info.addr_space) {
+ case SERIAL_ADDRESS_SPACE_MEMORY:
+ space_id = ACPI_ADDRESS_SPACE_MEMORY;
+ break;
+ case SERIAL_ADDRESS_SPACE_IO:
+ default:
+ space_id = ACPI_ADDRESS_SPACE_IO;
+ break;
+ }
+
+ serial_width = serial_info.reg_width * 8;
+ serial_offset = ((u64)serial_info.reg_offset) << serial_info.reg_shift;
+ serial_address = serial_info.addr + serial_offset;
+
+ /* Encode register access size */
+ switch (serial_info.reg_shift) {
+ case 0:
+ access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ break;
+ case 1:
+ access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ break;
+ case 2:
+ access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ break;
+ case 3:
+ access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
+ break;
+ default:
+ access_size = ACPI_ACCESS_SIZE_UNDEFINED;
+ break;
+ }
+
+ debug("UART type %u @ %llx\n", spcr->interface_type, serial_address);
+
+ /* Fill GAS */
+ spcr->serial_port.space_id = space_id;
+ spcr->serial_port.bit_width = serial_width;
+ spcr->serial_port.bit_offset = 0;
+ spcr->serial_port.access_size = access_size;
+ spcr->serial_port.addrl = lower_32_bits(serial_address);
+ spcr->serial_port.addrh = upper_32_bits(serial_address);
+
+ /* Encode baud rate */
+ switch (serial_info.baudrate) {
+ case 9600:
+ spcr->baud_rate = 3;
+ break;
+ case 19200:
+ spcr->baud_rate = 4;
+ break;
+ case 57600:
+ spcr->baud_rate = 6;
+ break;
+ case 115200:
+ spcr->baud_rate = 7;
+ break;
+ default:
+ spcr->baud_rate = 0;
+ break;
+ }
+
+ serial_config = SERIAL_DEFAULT_CONFIG;
+ if (dev)
+ ret = serial_getconfig(dev, &serial_config);
+
+ spcr->parity = SERIAL_GET_PARITY(serial_config);
+ spcr->stop_bits = SERIAL_GET_STOP(serial_config);
+
+ /* No PCI devices for now */
+ spcr->pci_device_id = 0xffff;
+ spcr->pci_vendor_id = 0xffff;
+
+ /*
+ * SPCR has no clue if the UART base clock speed is different
+ * to the default one. However, the SPCR 1.04 defines baud rate
+ * 0 as a preconfigured state of UART and OS is supposed not
+ * to touch the configuration of the serial device.
+ */
+ if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
+ spcr->baud_rate = 0;
+
+ /* Fix checksum */
+ header->checksum = table_compute_checksum((void *)spcr, header->length);
+
+ acpi_add_table(ctx, spcr);
+ acpi_inc(ctx, spcr->header.length);
+
+ return 0;
+}
+
+ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
+
+__weak int acpi_fill_iort(struct acpi_ctx *ctx)
+{
+ return 0;
+}
+
+int acpi_iort_add_its_group(struct acpi_ctx *ctx,
+ const u32 its_count,
+ const u32 *identifiers)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_its_group *group;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_ITS_GROUP;
+ node->revision = 1;
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_its_group);
+ node->length += sizeof(u32) * its_count;
+
+ group = (struct acpi_iort_its_group *)node->node_data;
+ group->its_count = its_count;
+ memcpy(&group->identifiers, identifiers, sizeof(u32) * its_count);
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_named_component(struct acpi_ctx *ctx,
+ const u32 node_flags,
+ const u64 memory_properties,
+ const u8 memory_address_limit,
+ const char *device_name)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_named_component *comp;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_NAMED_COMPONENT;
+ node->revision = 4;
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_named_component);
+ node->length += strlen(device_name) + 1;
+
+ comp = (struct acpi_iort_named_component *)node->node_data;
+
+ comp->node_flags = node_flags;
+ comp->memory_properties = memory_properties;
+ comp->memory_address_limit = memory_address_limit;
+ memcpy(comp->device_name, device_name, strlen(device_name) + 1);
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_rc(struct acpi_ctx *ctx,
+ const u64 mem_access_properties,
+ const u32 ats_attributes,
+ const u32 pci_segment_number,
+ const u8 memory_address_size_limit,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map)
+{
+ struct acpi_iort_id_mapping *mapping;
+ struct acpi_iort_node *node;
+ struct acpi_iort_rc *rc;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
+ node->revision = 2;
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_rc);
+ node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
+
+ rc = (struct acpi_iort_rc *)node->node_data;
+ rc->mem_access_properties = mem_access_properties;
+ rc->ats_attributes = ats_attributes;
+ rc->pci_segment_number = pci_segment_number;
+ rc->memory_address_size_limit = memory_address_size_limit;
+
+ mapping = (struct acpi_iort_id_mapping *)(rc + 1);
+ for (int i = 0; i < num_mappings; i++) {
+ memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
+ mapping++;
+ }
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
+ const u64 base_address,
+ const u32 flags,
+ const u64 vatos_address,
+ const u32 model,
+ const u32 event_gsiv,
+ const u32 pri_gsiv,
+ const u32 gerr_gsiv,
+ const u32 sync_gsiv,
+ const u32 pxm,
+ const u32 id_mapping_index,
+ const int num_mappings,
+ const struct acpi_iort_id_mapping *map)
+{
+ struct acpi_iort_node *node;
+ struct acpi_iort_smmu_v3 *smmu;
+ struct acpi_iort_id_mapping *mapping;
+ int offset;
+
+ offset = ctx->current - ctx->tab_start;
+
+ node = ctx->current;
+ memset(node, '\0', sizeof(struct acpi_iort_node));
+
+ node->type = ACPI_IORT_NODE_SMMU_V3;
+ node->revision = 5;
+ node->mapping_count = num_mappings;
+ node->mapping_offset = sizeof(struct acpi_iort_node) + sizeof(struct acpi_iort_smmu_v3);
+
+ node->length = sizeof(struct acpi_iort_node);
+ node->length += sizeof(struct acpi_iort_smmu_v3);
+ node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
+
+ smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+
+ smmu->base_address = base_address;
+ smmu->flags = flags;
+ smmu->vatos_address = vatos_address;
+ smmu->model = model;
+ smmu->event_gsiv = event_gsiv;
+ smmu->pri_gsiv = pri_gsiv;
+ smmu->gerr_gsiv = gerr_gsiv;
+ smmu->sync_gsiv = sync_gsiv;
+ smmu->pxm = pxm;
+ smmu->id_mapping_index = id_mapping_index;
+
+ mapping = (struct acpi_iort_id_mapping *)(smmu + 1);
+ for (int i = 0; i < num_mappings; i++) {
+ memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
+ mapping++;
+ }
+
+ ctx->current += node->length;
+
+ return offset;
+}
+
+static int acpi_write_iort(struct acpi_ctx *ctx, const struct acpi_writer *entry)
+{
+ struct acpi_table_iort *iort;
+ struct acpi_iort_node *node;
+ u32 offset;
+ int ret;
+
+ iort = ctx->current;
+ ctx->tab_start = ctx->current;
+ memset(iort, '\0', sizeof(struct acpi_table_iort));
+
+ acpi_fill_header(&iort->header, "IORT");
+ iort->header.revision = 1;
+ iort->header.creator_revision = 1;
+ iort->header.length = sizeof(struct acpi_table_iort);
+ iort->node_offset = sizeof(struct acpi_table_iort);
+
+ acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+ offset = sizeof(struct acpi_table_iort);
+ ret = acpi_fill_iort(ctx);
+ if (ret) {
+ ctx->current = iort;
+ return log_msg_ret("fill", ret);
+ }
+
+ /* Count nodes filled in */
+ for (node = (void *)iort + iort->node_offset;
+ node->length > 0 && (void *)node < ctx->current;
+ node = (void *)node + node->length)
+ iort->node_count++;
+
+ /* (Re)calculate length and checksum */
+ iort->header.length = ctx->current - (void *)iort;
+ iort->header.checksum = table_compute_checksum((void *)iort, iort->header.length);
+ log_debug("IORT at %p, length %x\n", iort, iort->header.length);
+
+ /* Drop the table if it is empty */
+ if (iort->header.length == sizeof(struct acpi_table_iort))
+ return log_msg_ret("fill", -ENOENT);
+ acpi_add_table(ctx, iort);
+
+ return 0;
+}
+
+ACPI_WRITER(5iort, "IORT", acpi_write_iort, 0);
+
+/*
+ * Allocate memory for ACPI tables and write ACPI tables to the
+ * allocated buffer.
+ *
+ * Return: status code
+ */
+static int alloc_write_acpi_tables(void)
+{
+ u64 table_end;
+ void *addr;
+
+ if (IS_ENABLED(CONFIG_X86) ||
+ IS_ENABLED(CONFIG_QFW_ACPI) ||
+ IS_ENABLED(CONFIG_SANDBOX)) {
+ log_debug("Skipping writing ACPI tables as already done\n");
+ return 0;
+ }
+
+ if (!IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+ log_debug("Skipping writing ACPI tables as BLOBLIST_TABLES is not selected\n");
+ return 0;
+ }
+
+ /* Align the table to a 4KB boundary to keep EFI happy */
+ addr = bloblist_add(BLOBLISTT_ACPI_TABLES, TABLE_SIZE,
+ ilog2(SZ_4K));
+
+ if (!addr)
+ return log_msg_ret("mem", -ENOMEM);
+
+ gd->arch.table_start_high = virt_to_phys(addr);
+ gd->arch.table_end_high = gd->arch.table_start_high + TABLE_SIZE;
+
+ table_end = write_acpi_tables(gd->arch.table_start_high);
+ if (!table_end) {
+ log_err("Can't create ACPI configuration table\n");
+ return -EINTR;
+ }
+
+ log_debug("- wrote 'acpi' to %lx, end %llx\n", gd->arch.table_start_high, table_end);
+ if (table_end > gd->arch.table_end_high) {
+ log_err("Out of space for configuration tables: need %llx, have %x\n",
+ table_end - gd->arch.table_start_high, TABLE_SIZE);
+ return log_msg_ret("acpi", -ENOSPC);
+ }
+
+ log_debug("- done writing tables\n");
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, alloc_write_acpi_tables);
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index ecff5a5..fa9dad3 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -361,6 +361,17 @@
acpigen_emit_byte(ctx, pblock_len);
}
+void acpigen_write_processor_device(struct acpi_ctx *ctx, uint cpuindex)
+{
+ char pscope[16];
+
+ snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex);
+ acpigen_write_device(ctx, pscope);
+ acpigen_write_name_string(ctx, "_HID", "ACPI0007");
+ acpigen_write_name_integer(ctx, "_UID", cpuindex);
+ acpigen_pop_len(ctx); /* Device */
+}
+
void acpigen_write_processor_package(struct acpi_ctx *ctx,
const char *const name,
const uint first_core,
diff --git a/lib/alist.c b/lib/alist.c
index b7928ca..4ce651f 100644
--- a/lib/alist.c
+++ b/lib/alist.c
@@ -41,6 +41,11 @@
memset(lst, '\0', sizeof(struct alist));
}
+void alist_empty(struct alist *lst)
+{
+ lst->count = 0;
+}
+
/**
* alist_expand_to() - Expand a list to the given size
*
@@ -106,6 +111,42 @@
return lst->data + index * lst->obj_size;
}
+int alist_calc_index(const struct alist *lst, const void *ptr)
+{
+ uint index;
+
+ if (!lst->count || ptr < lst->data)
+ return -1;
+
+ index = (ptr - lst->data) / lst->obj_size;
+
+ return index;
+}
+
+void alist_update_end(struct alist *lst, const void *ptr)
+{
+ int index;
+
+ index = alist_calc_index(lst, ptr);
+ lst->count = index == -1 ? 0 : index;
+}
+
+bool alist_chk_ptr(const struct alist *lst, const void *ptr)
+{
+ int index = alist_calc_index(lst, ptr);
+
+ return index >= 0 && index < lst->count;
+}
+
+const void *alist_next_ptrd(const struct alist *lst, const void *ptr)
+{
+ int index = alist_calc_index(lst, ptr);
+
+ assert(index != -1);
+
+ return alist_get_ptr(lst, index + 1);
+}
+
void *alist_ensure_ptr(struct alist *lst, uint index)
{
uint minsize = index + 1;
diff --git a/lib/binman.c b/lib/binman.c
index 9047f52..93d8554 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -137,6 +137,7 @@
{
int ret;
+ return 0;
binman = malloc(sizeof(struct binman_info));
if (!binman)
return log_msg_ret("space for binman", -ENOMEM);
diff --git a/lib/ecdsa/ecdsa-verify.c b/lib/ecdsa/ecdsa-verify.c
index 4d1835b..629b662 100644
--- a/lib/ecdsa/ecdsa-verify.c
+++ b/lib/ecdsa/ecdsa-verify.c
@@ -22,8 +22,10 @@
{
if (!strcmp(curve_name, "prime256v1"))
return 256;
- else
- return 0;
+ else if (!strcmp(curve_name, "secp384r1"))
+ return 384;
+
+ return 0;
}
static int fdt_get_key(struct ecdsa_public_key *key, const void *fdt, int node)
@@ -121,12 +123,18 @@
return ecdsa_verify_hash(dev, info, hash, sig, sig_len);
}
-U_BOOT_CRYPTO_ALGO(ecdsa) = {
+U_BOOT_CRYPTO_ALGO(ecdsa256) = {
.name = "ecdsa256",
.key_len = ECDSA256_BYTES,
.verify = ecdsa_verify,
};
+U_BOOT_CRYPTO_ALGO(ecdsa384) = {
+ .name = "ecdsa384",
+ .key_len = ECDSA384_BYTES,
+ .verify = ecdsa_verify,
+};
+
/*
* uclass definition for ECDSA API
*
diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c
index 34a0365..19a5ee2 100644
--- a/lib/efi_driver/efi_block_device.c
+++ b/lib/efi_driver/efi_block_device.c
@@ -133,15 +133,13 @@
sprintf(name, "efiblk#%d", devnum);
/* Create driver model udevice for the EFI block io device */
- if (blk_create_device(parent, "efi_blk", name, UCLASS_EFI_LOADER,
- devnum, io->media->block_size,
- (lbaint_t)io->media->last_block, &bdev)) {
+ if (blk_create_devicef(parent, "efi_blk", name, UCLASS_EFI_LOADER,
+ devnum, io->media->block_size,
+ (lbaint_t)io->media->last_block, &bdev)) {
ret = EFI_OUT_OF_RESOURCES;
free(name);
goto err;
}
- /* Set the DM_FLAG_NAME_ALLOCED flag to avoid a memory leak */
- device_set_name_alloced(bdev);
plat = dev_get_plat(bdev);
plat->handle = handle;
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 69b2c93..066f0ca 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -545,6 +545,8 @@
config EFI_HTTP_BOOT
bool "EFI HTTP Boot support"
+ depends on NET || NET_LWIP
+ select CMD_NET
select CMD_DNS
select CMD_WGET
select BLKMAP
diff --git a/lib/efi_loader/dtbdump.c b/lib/efi_loader/dtbdump.c
index 9f1d8fb..a3d59a2 100644
--- a/lib/efi_loader/dtbdump.c
+++ b/lib/efi_loader/dtbdump.c
@@ -225,7 +225,7 @@
* @systable: system table
* Return: device tree or NULL
*/
-void *get_dtb(struct efi_system_table *systable)
+static void *get_dtb(struct efi_system_table *systable)
{
void *dtb = NULL;
efi_uintn_t i;
@@ -246,7 +246,7 @@
* @pos: UTF-16 string
* Return: pointer to first non-whitespace
*/
-u16 *skip_whitespace(u16 *pos)
+static u16 *skip_whitespace(u16 *pos)
{
for (; *pos && *pos <= 0x20; ++pos)
;
@@ -260,7 +260,7 @@
* @keyword: keyword to be searched
* Return: true fi @string starts with the keyword
*/
-bool starts_with(u16 *string, u16 *keyword)
+static bool starts_with(u16 *string, u16 *keyword)
{
for (; *keyword; ++string, ++keyword) {
if (*string != *keyword)
@@ -272,7 +272,7 @@
/**
* do_help() - print help
*/
-void do_help(void)
+static void do_help(void)
{
error(u"dump - print device-tree\r\n");
error(u"load <dtb> - load device-tree from file\r\n");
@@ -332,7 +332,7 @@
* @filename: file name
* Return: status code
*/
-efi_status_t do_load(u16 *filename)
+static efi_status_t do_load(u16 *filename)
{
struct efi_dt_fixup_protocol *dt_fixup_prot;
struct efi_simple_file_system_protocol *file_system;
@@ -469,7 +469,7 @@
* @filename: file name
* Return: status code
*/
-efi_status_t do_save(u16 *filename)
+static efi_status_t do_save(u16 *filename)
{
struct efi_simple_file_system_protocol *file_system;
efi_uintn_t dtb_size;
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index a87006b..bf38392 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -137,6 +137,7 @@
*/
file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
(uintptr_t)source_buffer,
+ (uintptr_t)source_buffer +
source_size);
/*
* Make sure that device for device_path exist
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index a3aa2b8..f9b5988 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -385,7 +385,7 @@
* @ctx: event context
* Return: status code
*/
-efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx)
+static efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx)
{
efi_status_t ret = EFI_SUCCESS;
efi_status_t ret2 = EFI_SUCCESS;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 9de3b95..d744458 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -1073,7 +1073,8 @@
efi_get_image_parameters(&image_addr, &image_size);
dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)image_addr, image_size);
+ (uintptr_t)image_addr,
+ (uintptr_t)image_addr + image_size);
} else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) {
dp = efi_dp_from_eth();
} else if (!strcmp(dev, "Uart")) {
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 93a9a5a..1f3de0a 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -561,11 +561,9 @@
{
struct efi_disk_obj *disk;
struct blk_desc *desc;
- int diskid;
efi_status_t ret;
desc = dev_get_uclass_plat(dev);
- diskid = desc->devnum;
ret = efi_disk_add_dev(NULL, NULL, desc,
NULL, 0, &disk, agent_handle);
@@ -608,7 +606,6 @@
struct disk_part *part_data;
struct disk_partition *info;
unsigned int part;
- int diskid;
struct efi_handler *handler;
struct efi_device_path *dp_parent;
struct efi_disk_obj *disk;
@@ -618,7 +615,6 @@
return -1;
desc = dev_get_uclass_plat(dev_get_parent(dev));
- diskid = desc->devnum;
part_data = dev_get_uclass_plat(dev);
part = part_data->partnum;
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index c92d8cc..95b3c89 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -864,8 +864,16 @@
}
ret = efi_get_file_size(fh, &file_size);
- if (ret != EFI_SUCCESS)
- goto error;
+ if (ret != EFI_SUCCESS) {
+ if (!fh->isdir)
+ goto error;
+ /*
+ * Some file drivers don't implement fs_size() for
+ * directories. Use a dummy non-zero value.
+ */
+ file_size = 4096;
+ ret = EFI_SUCCESS;
+ }
memset(info, 0, required_size);
@@ -976,14 +984,16 @@
}
free(new_file_name);
/* Check for truncation */
- ret = efi_get_file_size(fh, &file_size);
- if (ret != EFI_SUCCESS)
- goto out;
- if (file_size != info->file_size) {
- /* TODO: we do not support truncation */
- EFI_PRINT("Truncation not supported\n");
- ret = EFI_ACCESS_DENIED;
- goto out;
+ if (!fh->isdir) {
+ ret = efi_get_file_size(fh, &file_size);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ if (file_size != info->file_size) {
+ /* TODO: we do not support truncation */
+ EFI_PRINT("Truncation not supported\n");
+ ret = EFI_ACCESS_DENIED;
+ goto out;
+ }
}
/*
* We do not care for the other attributes
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index a481eb4..00167bd 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -412,7 +412,7 @@
EFI_ACPI_RECLAIM_MEMORY, fdt_pages,
&new_fdt_addr);
if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to reserve space for FDT\n");
+ log_err("Failed to reserve space for FDT\n");
goto done;
}
new_fdt = (void *)(uintptr_t)new_fdt_addr;
@@ -468,7 +468,7 @@
* but not both.
*/
if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
- log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
+ log_warning("Can't have ACPI table and device tree - ignoring DT.\n");
if (fdt == EFI_FDT_USE_INTERNAL) {
const char *fdt_opt;
@@ -483,13 +483,13 @@
if (!fdt_opt) {
fdt_opt = env_get("fdtcontroladdr");
if (!fdt_opt) {
- log_err("ERROR: need device tree\n");
+ log_err("need device tree\n");
return EFI_NOT_FOUND;
}
}
fdt_addr = hextoul(fdt_opt, NULL);
if (!fdt_addr) {
- log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n");
+ log_err("invalid $fdt_addr or $fdtcontroladdr\n");
return EFI_LOAD_ERROR;
}
fdt = map_sysmem(fdt_addr, 0);
@@ -497,7 +497,7 @@
/* Install device tree */
if (fdt_check_header(fdt)) {
- log_err("ERROR: invalid device tree\n");
+ log_err("invalid device tree\n");
return EFI_LOAD_ERROR;
}
@@ -510,12 +510,12 @@
/* Prepare device tree for payload */
ret = copy_fdt(&fdt);
if (ret) {
- log_err("ERROR: out of memory\n");
+ log_err("out of memory\n");
return EFI_OUT_OF_RESOURCES;
}
if (image_setup_libfdt(&img, fdt, false)) {
- log_err("ERROR: failed to process device tree\n");
+ log_err("failed to process device tree\n");
return EFI_LOAD_ERROR;
}
@@ -527,7 +527,7 @@
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
ret = efi_tcg2_measure_dtb(fdt);
if (ret == EFI_SECURITY_VIOLATION) {
- log_err("ERROR: failed to measure DTB\n");
+ log_err("failed to measure DTB\n");
return ret;
}
}
@@ -535,7 +535,7 @@
/* Install device tree as UEFI table */
ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
if (ret != EFI_SUCCESS) {
- log_err("ERROR: failed to install device tree\n");
+ log_err("failed to install device tree\n");
return ret;
}
@@ -574,7 +574,7 @@
*/
ret = efi_set_watchdog(300);
if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to set watchdog timer\n");
+ log_err("failed to set watchdog timer\n");
goto out;
}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index b63b5cc..d2f5d56 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -472,7 +472,8 @@
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
- addr = (u64)lmb_alloc_flags(len, EFI_PAGE_SIZE, flags);
+ addr = (u64)lmb_alloc_base_flags(len, EFI_PAGE_SIZE,
+ LMB_ALLOC_ANYWHERE, flags);
if (!addr)
return EFI_OUT_OF_RESOURCES;
break;
@@ -520,7 +521,6 @@
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
u64 len;
- uint flags;
long status;
efi_status_t ret;
@@ -535,18 +535,17 @@
return EFI_INVALID_PARAMETER;
}
- flags = LMB_NOOVERWRITE | LMB_NONOTIFY;
len = (u64)pages << EFI_PAGE_SHIFT;
+ /*
+ * The 'memory' variable for sandbox holds a pointer which has already
+ * been mapped with map_sysmem() from efi_allocate_pages(). Convert
+ * it back to an address LMB understands
+ */
status = lmb_free_flags(map_to_sysmem((void *)(uintptr_t)memory), len,
- flags);
+ LMB_NOOVERWRITE);
if (status)
return EFI_NOT_FOUND;
- ret = efi_add_memory_map_pg(memory, pages, EFI_CONVENTIONAL_MEMORY,
- false);
- if (ret != EFI_SUCCESS)
- return EFI_NOT_FOUND;
-
return ret;
}
@@ -652,7 +651,7 @@
if (efi_allocate_pool(EFI_BOOT_SERVICES_DATA, size, &buf) !=
EFI_SUCCESS) {
- log_err("out of memory");
+ log_err("out of memory\n");
return NULL;
}
memset(buf, 0, size);
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index a610e03..aa59bc7 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -86,7 +86,6 @@
return ret;
}
-#ifdef CONFIG_EFI_SECURE_BOOT
/**
* efi_init_secure_boot - initialize secure boot state
*
@@ -112,12 +111,6 @@
return ret;
}
-#else
-static efi_status_t efi_init_secure_boot(void)
-{
- return EFI_SUCCESS;
-}
-#endif /* CONFIG_EFI_SECURE_BOOT */
/**
* efi_init_capsule - initialize capsule update state
@@ -302,9 +295,11 @@
}
/* Secure boot */
- ret = efi_init_secure_boot();
- if (ret != EFI_SUCCESS)
- goto out;
+ if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) {
+ ret = efi_init_secure_boot();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
/* Indicate supported runtime services */
ret = efi_init_runtime_supported();
@@ -322,11 +317,11 @@
if (ret != EFI_SUCCESS)
goto out;
}
-#ifdef CONFIG_NETDEVICES
- ret = efi_net_register();
- if (ret != EFI_SUCCESS)
- goto out;
-#endif
+ if (IS_ENABLED(CONFIG_NETDEVICES)) {
+ ret = efi_net_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
if (IS_ENABLED(CONFIG_ACPI)) {
ret = efi_acpi_register();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 45f451e..866a529 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -789,7 +789,7 @@
/**
* tcg2_uninit - remove the final event table and free efi memory on failures
*/
-void tcg2_uninit(void)
+static void tcg2_uninit(void)
{
efi_status_t ret;
diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
index 413e179..ba0bf33 100644
--- a/lib/efi_loader/efi_var_file.c
+++ b/lib/efi_loader/efi_var_file.c
@@ -37,18 +37,16 @@
char part_str[PART_STR_LEN];
int r;
- if (efi_system_partition.uclass_id == UCLASS_INVALID) {
- log_err("No EFI system partition\n");
+ if (efi_system_partition.uclass_id == UCLASS_INVALID)
return EFI_DEVICE_ERROR;
- }
+
snprintf(part_str, PART_STR_LEN, "%x:%x",
efi_system_partition.devnum, efi_system_partition.part);
r = fs_set_blk_dev(blk_get_uclass_name(efi_system_partition.uclass_id),
part_str, FS_TYPE_ANY);
- if (r) {
- log_err("Cannot read EFI system partition\n");
+ if (r)
return EFI_DEVICE_ERROR;
- }
+
return EFI_SUCCESS;
}
@@ -67,14 +65,21 @@
loff_t len;
loff_t actlen;
int r;
+ static bool once;
ret = efi_var_collect(&buf, &len, EFI_VARIABLE_NON_VOLATILE);
if (ret != EFI_SUCCESS)
goto error;
ret = efi_set_blk_dev_to_system_partition();
- if (ret != EFI_SUCCESS)
- goto error;
+ if (ret != EFI_SUCCESS) {
+ if (!once) {
+ log_warning("Cannot persist EFI variables without system partition\n");
+ once = true;
+ }
+ goto out;
+ }
+ once = false;
r = fs_write(EFI_VAR_FILE_NAME, map_to_sysmem(buf), 0, len, &actlen);
if (r || len != actlen)
@@ -83,6 +88,7 @@
error:
if (ret != EFI_SUCCESS)
log_err("Failed to persist EFI variables\n");
+out:
free(buf);
return ret;
#else
diff --git a/lib/efi_loader/smbiosdump.c b/lib/efi_loader/smbiosdump.c
index 2f0b91a..d7f2ba3 100644
--- a/lib/efi_loader/smbiosdump.c
+++ b/lib/efi_loader/smbiosdump.c
@@ -289,7 +289,7 @@
* @len: length of buffer
* Return: checksum
*/
-u8 checksum(void *buf, int len)
+static u8 checksum(void *buf, int len)
{
u8 ret = 0;
@@ -304,7 +304,7 @@
*
* Return: status code
*/
-efi_status_t do_check(void)
+static efi_status_t do_check(void)
{
struct smbios3_entry *smbios3_anchor;
void *table, *table_end;
@@ -401,7 +401,7 @@
* @buf: buffer to write
* @size: size of the buffer
*/
-efi_status_t save_file(u16 *filename, void *buf, efi_uintn_t size)
+static efi_status_t save_file(u16 *filename, void *buf, efi_uintn_t size)
{
efi_uintn_t ret;
struct efi_simple_file_system_protocol *file_system;
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index f219c01..c363df4 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -913,7 +913,7 @@
goto out;
}
- efi_st_printf("got languages are %s\n", languages);
+ efi_st_printf("Available languages: %s\n", languages);
result = EFI_ST_SUCCESS;
diff --git a/lib/efi_selftest/efi_selftest_hii_data.c b/lib/efi_selftest/efi_selftest_hii_data.c
index d19f068..5fc8901 100644
--- a/lib/efi_selftest/efi_selftest_hii_data.c
+++ b/lib/efi_selftest/efi_selftest_hii_data.c
@@ -39,7 +39,7 @@
/* HII keyboard layout */
#define EFI_NULL_MODIFIER 0x0000
-u8 packagelist1[] = {
+static u8 packagelist1[] = {
// EFI_HII_PACKAGE_LIST_HEADER, length = 20
// SimpleFont, Font, GUID, Form, String, Image, DevicePath,
// (74) (110) 20 (8) 78 (67) (8)
@@ -262,7 +262,7 @@
EFI_HII_PACKAGE_END
};
-u8 packagelist2[] = {
+static u8 packagelist2[] = {
// EFI_HII_PACKAGE_LIST_HEADER, length = 20
// SimpleFont, Font, GUID, KeyboardLayout, Form, End
// (74) (122) 20 192 (8) 4
@@ -424,30 +424,10 @@
EFI_HII_PACKAGE_END // 1
};
-efi_guid_t packagelist_guid1 =
- EFI_GUID(0x03abcd89, 0x03f4, 0x7044,
- 0x81, 0xde, 0x99, 0xb1, 0x81, 0x20, 0xf7, 0x68);
-
-efi_guid_t packagelist_guid2 =
- EFI_GUID(0x8685ded3, 0x1bce, 0x43f3,
- 0xa2, 0x0c, 0xa3, 0x06, 0xec, 0x69, 0x72, 0xdd);
-
-efi_guid_t kb_layout_guid11 =
+static efi_guid_t kb_layout_guid11 =
EFI_GUID(0x8d40e495, 0xe2aa, 0x4c6f,
0x89, 0x70, 0x68, 0x85, 0x09, 0xee, 0xc7, 0xd2);
-efi_guid_t kb_layout_guid12 =
- EFI_GUID(0x2ae60b3e, 0xb9d6, 0x49d8,
- 0x9a, 0x16, 0xc2, 0x48, 0xf1, 0xeb, 0xa8, 0xdb);
-
-efi_guid_t kb_layout_guid21 =
- EFI_GUID(0xe0f56a1f, 0xdf6b, 0x4a7e,
- 0xa3, 0x9a, 0xe7, 0xa5, 0x19, 0x15, 0x45, 0xd6);
-
-efi_guid_t kb_layout_guid22 =
- EFI_GUID(0x47be6ac9, 0x54cc, 0x46f9,
- 0xa2, 0x62, 0xd5, 0x3b, 0x25, 0x6a, 0x0c, 0x34);
-
-efi_guid_t package_guid =
+static efi_guid_t package_guid =
EFI_GUID(0x0387c95a, 0xd703, 0x2346,
0xb2, 0xab, 0xd0, 0xc7, 0xdd, 0x90, 0x44, 0xf8);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 85f4426..b065598 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1172,10 +1172,10 @@
void *dst;
int rc;
- if (CONFIG_IS_ENABLED(GZIP))
+ if (CONFIG_IS_ENABLED(GZIP) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP))
if (gzip_parse_header(src, sz_in) >= 0)
gzip = 1;
- if (CONFIG_IS_ENABLED(LZO))
+ if (CONFIG_IS_ENABLED(LZO) && CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO))
if (!gzip && lzop_is_valid_header(src))
lzo = 1;
diff --git a/lib/lmb.c b/lib/lmb.c
index 78fe2d4..2ed0da2 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -27,9 +27,6 @@
#define MAP_OP_FREE (u8)0x2
#define MAP_OP_ADD (u8)0x3
-#define LMB_ALLOC_ANYWHERE 0
-#define LMB_ALIST_INITIAL_SIZE 4
-
static struct lmb lmb;
static bool lmb_should_notify(enum lmb_flags flags)
@@ -38,9 +35,8 @@
CONFIG_IS_ENABLED(EFI_LOADER);
}
-static int __maybe_unused lmb_map_update_notify(phys_addr_t addr,
- phys_size_t size,
- u8 op)
+static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op,
+ enum lmb_flags flags)
{
u64 efi_addr;
u64 pages;
@@ -51,6 +47,9 @@
return -1;
}
+ if (!lmb_should_notify(flags))
+ return 0;
+
efi_addr = (uintptr_t)map_sysmem(addr, 0);
pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
efi_addr &= ~EFI_PAGE_MASK;
@@ -64,9 +63,10 @@
log_err("%s: LMB Map notify failure %lu\n", __func__,
status & ~EFI_ERROR_MASK);
return -1;
- } else {
- return 0;
}
+ unmap_sysmem((void *)(uintptr_t)efi_addr);
+
+ return 0;
}
static void lmb_print_region_flags(enum lmb_flags flags)
@@ -76,6 +76,7 @@
do {
bitpos = flags ? fls(flags) - 1 : 0;
+ assert_noisy(bitpos < ARRAY_SIZE(flag_str));
printf("%s", flag_str[bitpos]);
flags &= ~(1ull << bitpos);
puts(flags ? ", " : "\n");
@@ -450,7 +451,7 @@
}
if (coalesced)
- return coalesced;
+ return 0;
if (alist_full(lmb_rgn_lst) &&
!alist_expand_by(lmb_rgn_lst, lmb_rgn_lst->alloc))
@@ -490,10 +491,7 @@
if (ret)
return ret;
- if (lmb_should_notify(LMB_NONE))
- return lmb_map_update_notify(base, size, MAP_OP_ADD);
-
- return 0;
+ return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE);
}
static long _lmb_free(phys_addr_t base, phys_size_t size)
@@ -566,10 +564,7 @@
if (ret < 0)
return ret;
- if (lmb_should_notify(flags))
- return lmb_map_update_notify(base, size, MAP_OP_FREE);
-
- return ret;
+ return lmb_map_update_notify(base, size, MAP_OP_FREE, flags);
}
long lmb_free(phys_addr_t base, phys_size_t size)
@@ -583,13 +578,10 @@
struct alist *lmb_rgn_lst = &lmb.used_mem;
ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
- if (ret < 0)
- return -1;
-
- if (lmb_should_notify(flags))
- return lmb_map_update_notify(base, size, MAP_OP_RESERVE);
+ if (ret)
+ return ret;
- return ret;
+ return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags);
}
long lmb_reserve(phys_addr_t base, phys_size_t size)
@@ -621,7 +613,6 @@
static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align,
phys_addr_t max_addr, enum lmb_flags flags)
{
- u8 op;
int ret;
long i, rgn;
phys_addr_t base = 0;
@@ -651,16 +642,14 @@
if (rgn < 0) {
/* This area isn't reserved, take it */
if (lmb_add_region_flags(&lmb.used_mem, base,
- size, flags) < 0)
+ size, flags))
return 0;
- if (lmb_should_notify(flags)) {
- op = MAP_OP_RESERVE;
- ret = lmb_map_update_notify(base, size,
- op);
- if (ret)
- return ret;
- }
+ ret = lmb_map_update_notify(base, size,
+ MAP_OP_RESERVE,
+ flags);
+ if (ret)
+ return ret;
return base;
}
@@ -679,23 +668,6 @@
return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
}
-/**
- * lmb_alloc_flags() - Allocate memory region with specified attributes
- * @size: Size of the region requested
- * @align: Alignment of the memory region requested
- * @flags: Memory region attributes to be set
- *
- * Allocate a region of memory with the attributes specified through the
- * parameter.
- *
- * Return: base address on success, 0 on error
- */
-phys_addr_t lmb_alloc_flags(phys_size_t size, ulong align, uint flags)
-{
- return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE,
- flags);
-}
-
phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr)
{
phys_addr_t alloc;
@@ -887,12 +859,12 @@
return 0;
}
-#if CONFIG_IS_ENABLED(UNIT_TEST)
struct lmb *lmb_get(void)
{
return &lmb;
}
+#if CONFIG_IS_ENABLED(UNIT_TEST)
int lmb_push(struct lmb *store)
{
int ret;
diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile
new file mode 100644
index 0000000..dfcd700
--- /dev/null
+++ b/lib/lwip/Makefile
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Linaro Ltd.
+
+obj-y += \
+ lwip/src/api/api_lib.o \
+ lwip/src/api/api_msg.o \
+ lwip/src/api/err.o \
+ lwip/src/api/if_api.o \
+ lwip/src/api/netbuf.o \
+ lwip/src/api/netdb.o \
+ lwip/src/api/netifapi.o \
+ lwip/src/api/sockets.o \
+ lwip/src/api/tcpip.o \
+ lwip/src/apps/http/http_client.o \
+ lwip/src/apps/tftp/tftp.o \
+ lwip/src/core/altcp_alloc.o \
+ lwip/src/core/altcp.o \
+ lwip/src/core/altcp_tcp.o \
+ lwip/src/core/def.o \
+ lwip/src/core/dns.o \
+ lwip/src/core/inet_chksum.o \
+ lwip/src/core/init.o \
+ lwip/src/core/ip.o \
+ lwip/src/core/ipv4/acd.o \
+ lwip/src/core/ipv4/autoip.o \
+ lwip/src/core/ipv4/dhcp.o \
+ lwip/src/core/ipv4/etharp.o \
+ lwip/src/core/ipv4/icmp.o \
+ lwip/src/core/ipv4/igmp.o \
+ lwip/src/core/ipv4/ip4_addr.o \
+ lwip/src/core/ipv4/ip4.o \
+ lwip/src/core/ipv4/ip4_frag.o \
+ lwip/src/core/ipv6/dhcp6.o \
+ lwip/src/core/ipv6/ethip6.o \
+ lwip/src/core/ipv6/icmp6.o \
+ lwip/src/core/ipv6/inet6.o \
+ lwip/src/core/ipv6/ip6_addr.o \
+ lwip/src/core/ipv6/ip6.o \
+ lwip/src/core/ipv6/ip6_frag.o \
+ lwip/src/core/ipv6/mld6.o \
+ lwip/src/core/ipv6/nd6.o \
+ lwip/src/core/mem.o \
+ lwip/src/core/memp.o \
+ lwip/src/core/netif.o \
+ lwip/src/core/pbuf.o \
+ lwip/src/core/raw.o \
+ lwip/src/core/stats.o \
+ lwip/src/core/sys.o \
+ lwip/src/core/tcp.o \
+ lwip/src/core/tcp_in.o \
+ lwip/src/core/tcp_out.o \
+ lwip/src/core/timeouts.o \
+ lwip/src/core/udp.o \
+ lwip/src/netif/ethernet.o
diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c
index ddfdbfc..56aeabc 100644
--- a/lib/lwip/lwip/src/apps/tftp/tftp.c
+++ b/lib/lwip/lwip/src/apps/tftp/tftp.c
@@ -57,7 +57,7 @@
#include "lwip/timeouts.h"
#include "lwip/debug.h"
-#define TFTP_MAX_PAYLOAD_SIZE 512
+#define TFTP_DEFAULT_BLOCK_SIZE 512
#define TFTP_HEADER_LENGTH 4
#define TFTP_RRQ 1
@@ -65,6 +65,7 @@
#define TFTP_DATA 3
#define TFTP_ACK 4
#define TFTP_ERROR 5
+#define TFTP_OACK 6
enum tftp_error {
TFTP_ERROR_FILE_NOT_FOUND = 1,
@@ -88,9 +89,11 @@
int timer;
int last_pkt;
u16_t blknum;
+ u16_t blksize;
u8_t retries;
u8_t mode_write;
u8_t tftp_mode;
+ bool wait_oack;
};
static struct tftp_state tftp_state;
@@ -137,10 +140,22 @@
{
size_t fname_length = strlen(fname)+1;
size_t mode_length = strlen(mode)+1;
- struct pbuf* p = init_packet(opcode, 0, fname_length + mode_length - 2);
+ size_t blksize_length = 0;
+ int blksize = tftp_state.blksize;
+ struct pbuf* p;
char* payload;
err_t ret;
+ if (blksize) {
+ /* 'blksize\0'.\0" with . = 1 digit */
+ blksize_length = strlen("blksize") + 1 + 1 + 1;
+ while (blksize >= 10) {
+ blksize /= 10;
+ blksize_length++;
+ }
+ }
+
+ p = init_packet(opcode, 0, fname_length + mode_length + blksize_length - 2);
if (p == NULL) {
return ERR_MEM;
}
@@ -148,7 +163,10 @@
payload = (char*) p->payload;
MEMCPY(payload+2, fname, fname_length);
MEMCPY(payload+2+fname_length, mode, mode_length);
+ if (tftp_state.blksize)
+ sprintf(payload+2+fname_length+mode_length, "blksize%c%d%c", 0, tftp_state.blksize, 0);
+ tftp_state.wait_oack = true;
ret = udp_sendto(tftp_state.upcb, p, addr, port);
pbuf_free(p);
return ret;
@@ -221,14 +239,14 @@
pbuf_free(tftp_state.last_data);
}
- tftp_state.last_data = init_packet(TFTP_DATA, tftp_state.blknum, TFTP_MAX_PAYLOAD_SIZE);
+ tftp_state.last_data = init_packet(TFTP_DATA, tftp_state.blknum, TFTP_DEFAULT_BLOCK_SIZE);
if (tftp_state.last_data == NULL) {
return;
}
payload = (u16_t *) tftp_state.last_data->payload;
- ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE);
+ ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_DEFAULT_BLOCK_SIZE);
if (ret < 0) {
send_error(addr, port, TFTP_ERROR_ACCESS_VIOLATION, "Error occurred while reading the file.");
close_handle();
@@ -239,6 +257,28 @@
resend_data(addr, port);
}
+static u16_t payload_size(void)
+{
+ if (tftp_state.blksize)
+ return tftp_state.blksize;
+ return TFTP_DEFAULT_BLOCK_SIZE;
+}
+
+static const char *
+find_option(struct pbuf *p, const char *option)
+{
+ int i;
+ u16_t optlen = strlen(option);
+ const char *b = p->payload;
+
+ for (i = 0; i + optlen + 1 < p->len; i++) {
+ if (lwip_strnstr(b + i, option, optlen))
+ return b + i + optlen + 2;
+ }
+
+ return NULL;
+}
+
static void
tftp_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
{
@@ -338,6 +378,15 @@
}
blknum = lwip_ntohs(sbuf[1]);
+ if (tftp_state.blksize && tftp_state.wait_oack) {
+ /*
+ * Data received while we are expecting an OACK for our blksize option.
+ * This means the server doesn't support it, let's switch back to the
+ * default block size.
+ */
+ tftp_state.blksize = 0;
+ tftp_state.wait_oack = false;
+ }
if (blknum == tftp_state.blknum) {
pbuf_remove_header(p, TFTP_HEADER_LENGTH);
@@ -349,7 +398,7 @@
send_ack(addr, port, blknum);
}
- if (p->tot_len < TFTP_MAX_PAYLOAD_SIZE) {
+ if (p->tot_len < payload_size()) {
close_handle();
} else {
tftp_state.blknum++;
@@ -386,7 +435,7 @@
lastpkt = 0;
if (tftp_state.last_data != NULL) {
- lastpkt = tftp_state.last_data->tot_len != (TFTP_MAX_PAYLOAD_SIZE + TFTP_HEADER_LENGTH);
+ lastpkt = tftp_state.last_data->tot_len != (TFTP_DEFAULT_BLOCK_SIZE + TFTP_HEADER_LENGTH);
}
if (!lastpkt) {
@@ -404,7 +453,26 @@
tftp_state.ctx->error(tftp_state.handle, sbuf[1], (const char*)p->payload, p->len);
close_handle();
}
+ break;
+ case PP_HTONS(TFTP_OACK): {
+ const char *optval = find_option(p, "blksize");
+ u16_t srv_blksize = 0;
+ tftp_state.wait_oack = false;
+ if (optval) {
+ if (!tftp_state.blksize) {
+ /* We did not request this option */
+ send_error(addr, port, TFTP_ERROR_ILLEGAL_OPERATION, "blksize unexpected");
+ }
+ srv_blksize = atoi(optval);
+ if (srv_blksize <= 0 || srv_blksize > tftp_state.blksize) {
+ send_error(addr, port, TFTP_ERROR_ILLEGAL_OPERATION, "Invalid blksize");
+ }
+ LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: accepting blksize=%d\n", srv_blksize));
+ tftp_state.blksize = srv_blksize;
+ }
+ send_ack(addr, port, 0);
break;
+ }
default:
send_error(addr, port, TFTP_ERROR_ILLEGAL_OPERATION, "Unknown operation");
break;
@@ -454,10 +522,12 @@
return ERR_MEM;
}
- ret = udp_bind(pcb, IP_ANY_TYPE, TFTP_PORT);
- if (ret != ERR_OK) {
- udp_remove(pcb);
- return ret;
+ if (mode == LWIP_TFTP_MODE_SERVER) {
+ ret = udp_bind(pcb, IP_ANY_TYPE, TFTP_PORT);
+ if (ret != ERR_OK) {
+ udp_remove(pcb);
+ return ret;
+ }
}
tftp_state.handle = NULL;
@@ -494,6 +564,18 @@
}
/** @ingroup tftp
+ * Set the block size to be used by the TFTP client. The server may choose to
+ * accept a lower value.
+ * @param blksize Block size in bytes
+ */
+void
+tftp_client_set_blksize(u16_t blksize)
+{
+ if (blksize != TFTP_DEFAULT_BLOCK_SIZE)
+ tftp_state.blksize = blksize;
+}
+
+/** @ingroup tftp
* Deinitialize ("turn off") TFTP client/server.
*/
void tftp_cleanup(void)
diff --git a/lib/lwip/lwip/src/include/lwip/apps/tftp_client.h b/lib/lwip/lwip/src/include/lwip/apps/tftp_client.h
index 24dbda6..e1e21d0 100644
--- a/lib/lwip/lwip/src/include/lwip/apps/tftp_client.h
+++ b/lib/lwip/lwip/src/include/lwip/apps/tftp_client.h
@@ -44,6 +44,7 @@
};
err_t tftp_init_client(const struct tftp_context* ctx);
+void tftp_client_set_blksize(u16_t blksize);
err_t tftp_get(void* handle, const ip_addr_t *addr, u16_t port, const char* fname, enum tftp_transfer_mode mode);
err_t tftp_put(void* handle, const ip_addr_t *addr, u16_t port, const char* fname, enum tftp_transfer_mode mode);
diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h
new file mode 100644
index 0000000..563d3bf
--- /dev/null
+++ b/lib/lwip/u-boot/arch/cc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2023 Linaro Ltd. <maxim.uvarov@linaro.org> */
+
+#ifndef LWIP_ARCH_CC_H
+#define LWIP_ARCH_CC_H
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <vsprintf.h>
+#include <rand.h>
+
+#define LWIP_ERRNO_INCLUDE <errno.h>
+
+#define LWIP_ERRNO_STDINCLUDE 1
+#define LWIP_NO_UNISTD_H 1
+#define LWIP_TIMEVAL_PRIVATE 1
+
+#ifdef CONFIG_LIB_RAND
+#define LWIP_RAND() ((u32_t)rand())
+#else
+#define LWIP_DNS_SECURE 0
+#endif
+
+/* different handling for unit test, normally not needed */
+#ifdef LWIP_NOASSERT_ON_ERROR
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+ handler; }} while (0)
+#endif
+
+#define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
+
+#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
+ x, __LINE__, __FILE__); } while (0)
+
+#define atoi(str) (int)dectoul(str, NULL)
+#define lwip_strnstr(a, b, c) strstr(a, b)
+
+#define LWIP_ERR_T int
+#define LWIP_CONST_CAST(target_type, val) ((target_type)((uintptr_t)val))
+
+#if defined(CONFIG_SYS_BIG_ENDIAN)
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+
+#endif /* LWIP_ARCH_CC_H */
diff --git a/lib/lwip/u-boot/arch/sys_arch.h b/lib/lwip/u-boot/arch/sys_arch.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/lib/lwip/u-boot/arch/sys_arch.h
diff --git a/lib/lwip/u-boot/limits.h b/lib/lwip/u-boot/limits.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/lib/lwip/u-boot/limits.h
diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h
new file mode 100644
index 0000000..9d61862
--- /dev/null
+++ b/lib/lwip/u-boot/lwipopts.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* Copyright (C) 2023 Linaro Ltd. <maxim.uvarov@linaro.org> */
+
+#ifndef LWIP_UBOOT_LWIPOPTS_H
+#define LWIP_UBOOT_LWIPOPTS_H
+
+#if defined(CONFIG_LWIP_DEBUG)
+#define LWIP_DEBUG 1
+#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL
+#define LWIP_DBG_TYPES_ON LWIP_DBG_ON
+#define ETHARP_DEBUG LWIP_DBG_ON
+#define NETIF_DEBUG LWIP_DBG_ON
+#define PBUF_DEBUG LWIP_DBG_OFF
+#define API_LIB_DEBUG LWIP_DBG_ON
+#define API_MSG_DEBUG LWIP_DBG_OFF
+#define SOCKETS_DEBUG LWIP_DBG_OFF
+#define ICMP_DEBUG LWIP_DBG_OFF
+#define IGMP_DEBUG LWIP_DBG_OFF
+#define INET_DEBUG LWIP_DBG_OFF
+#define IP_DEBUG LWIP_DBG_ON
+#define IP_REASS_DEBUG LWIP_DBG_OFF
+#define RAW_DEBUG LWIP_DBG_OFF
+#define MEM_DEBUG LWIP_DBG_OFF
+#define MEMP_DEBUG LWIP_DBG_OFF
+#define SYS_DEBUG LWIP_DBG_OFF
+#define TIMERS_DEBUG LWIP_DBG_ON
+#define TCP_DEBUG LWIP_DBG_OFF
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
+#define TCP_FR_DEBUG LWIP_DBG_OFF
+#define TCP_RTO_DEBUG LWIP_DBG_OFF
+#define TCP_CWND_DEBUG LWIP_DBG_OFF
+#define TCP_WND_DEBUG LWIP_DBG_OFF
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
+#define TCP_RST_DEBUG LWIP_DBG_OFF
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
+#define UDP_DEBUG LWIP_DBG_OFF
+#define TCPIP_DEBUG LWIP_DBG_OFF
+#define SLIP_DEBUG LWIP_DBG_OFF
+#define DHCP_DEBUG LWIP_DBG_ON
+#define AUTOIP_DEBUG LWIP_DBG_ON
+#define DNS_DEBUG LWIP_DBG_ON
+#define IP6_DEBUG LWIP_DBG_OFF
+#define DHCP6_DEBUG LWIP_DBG_OFF
+#endif
+
+#define LWIP_TESTMODE 0
+
+#if !defined(CONFIG_LWIP_ASSERT)
+#define LWIP_NOASSERT 1
+#define LWIP_ASSERT(message, assertion)
+#endif
+
+#include "lwip/debug.h"
+
+#define SYS_LIGHTWEIGHT_PROT 0
+#define NO_SYS 1
+
+#define LWIP_IPV4 1
+#define LWIP_IPV6 0
+
+#define MEM_ALIGNMENT 8
+
+#define MEMP_NUM_TCP_SEG 16
+#define PBUF_POOL_SIZE 8
+
+#define LWIP_ARP 1
+#define ARP_TABLE_SIZE 4
+#define ARP_QUEUEING 1
+
+#define IP_FORWARD 0
+#define IP_OPTIONS_ALLOWED 1
+#define IP_REASSEMBLY 0
+#define IP_FRAG 0
+#define IP_REASS_MAXAGE 3
+#define IP_REASS_MAX_PBUFS 4
+#define IP_FRAG_USES_STATIC_BUF 0
+
+#define IP_DEFAULT_TTL 255
+
+#define LWIP_ICMP 0
+
+#if defined(CONFIG_PROT_RAW_LWIP)
+#define LWIP_RAW 1
+#else
+#define LWIP_RAW 0
+#endif
+
+#if defined(CONFIG_PROT_DHCP_LWIP)
+#define LWIP_DHCP 1
+#define LWIP_DHCP_BOOTP_FILE 1
+#else
+#define LWIP_DHCP 0
+#endif
+
+#define LWIP_DHCP_DOES_ACD_CHECK 0
+
+#define LWIP_AUTOIP 0
+
+#define LWIP_SNMP 0
+
+#define LWIP_IGMP 0
+
+#if defined(CONFIG_PROT_DNS_LWIP)
+#define LWIP_DNS 1
+#define DNS_TABLE_SIZE 1
+#else
+#define LWIP_DNS 0
+#endif
+
+#if defined(CONFIG_PROT_UDP_LWIP)
+#define LWIP_UDP 1
+#else
+#define LWIP_UDP 0
+#endif
+
+#if defined(CONFIG_PROT_TCP_LWIP)
+#define LWIP_TCP 1
+#define TCP_MSS 1460
+#define TCP_WND CONFIG_LWIP_TCP_WND
+#define LWIP_WND_SCALE 1
+#define TCP_RCV_SCALE 0x7
+#define TCP_SND_BUF (2 * TCP_MSS)
+#ifdef CONFIG_PROT_TCP_SACK_LWIP
+#define LWIP_TCP_SACK_OUT 1
+#endif
+#else
+#define LWIP_TCP 0
+#endif
+
+#define LWIP_LISTEN_BACKLOG 0
+
+#define PBUF_LINK_HLEN 14
+#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_HLEN)
+
+#define LWIP_HAVE_LOOPIF 0
+
+#define LWIP_NETCONN 0
+#define LWIP_DISABLE_MEMP_SANITY_CHECKS 1
+
+#define LWIP_SOCKET 0
+#define SO_REUSE 0
+
+#define LWIP_STATS 0
+
+#define PPP_SUPPORT 0
+
+#define LWIP_TCPIP_CORE_LOCKING 0
+
+#define LWIP_NETIF_LOOPBACK 0
+
+/* use malloc instead of pool */
+#define MEMP_MEM_MALLOC 1
+#define MEMP_MEM_INIT 1
+#define MEM_LIBC_MALLOC 1
+
+#endif /* LWIP_UBOOT_LWIPOPTS_H */
diff --git a/lib/mbedtls/pkcs7_parser.c b/lib/mbedtls/pkcs7_parser.c
index 69ca784..ecfcc46 100644
--- a/lib/mbedtls/pkcs7_parser.c
+++ b/lib/mbedtls/pkcs7_parser.c
@@ -206,9 +206,6 @@
p += seq_len;
}
- if (ret && ret != MBEDTLS_ERR_ASN1_OUT_OF_DATA)
- return ret;
-
msg->have_authattrs = true;
/*
@@ -361,8 +358,10 @@
signed_info->sig = s;
/* Save the Authenticate Attributes data if exists */
- if (!mb_sinfo->authattrs.data || !mb_sinfo->authattrs.data_len)
+ if (!mb_sinfo->authattrs.data || !mb_sinfo->authattrs.data_len) {
+ kfree(mctx);
goto no_authattrs;
+ }
mctx->authattrs_data = kmemdup(mb_sinfo->authattrs.data,
mb_sinfo->authattrs.data_len,
diff --git a/lib/mbedtls/x509_cert_parser.c b/lib/mbedtls/x509_cert_parser.c
index cb42018..e163e16 100644
--- a/lib/mbedtls/x509_cert_parser.c
+++ b/lib/mbedtls/x509_cert_parser.c
@@ -66,7 +66,7 @@
static char *x509_populate_dn_name_string(const mbedtls_x509_name *name)
{
size_t len = 256;
- size_t wb;
+ int wb;
char *name_str;
do {
diff --git a/lib/sha1.c b/lib/sha1.c
index 8141228..a9d6497 100644
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -17,7 +17,7 @@
#endif
#ifndef USE_HOSTCC
-#include <cyclic.h>
+#include <u-boot/schedule.h>
#endif /* USE_HOSTCC */
#include <string.h>
#include <u-boot/sha1.h>
diff --git a/lib/sha256.c b/lib/sha256.c
index 665ba6f..329802f 100644
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -6,7 +6,7 @@
*/
#ifndef USE_HOSTCC
-#include <cyclic.h>
+#include <u-boot/schedule.h>
#endif /* USE_HOSTCC */
#include <string.h>
#include <u-boot/sha256.h>
diff --git a/lib/sha512.c b/lib/sha512.c
index ffe2c5c..ea555ff 100644
--- a/lib/sha512.c
+++ b/lib/sha512.c
@@ -11,7 +11,7 @@
*/
#ifndef USE_HOSTCC
-#include <cyclic.h>
+#include <u-boot/schedule.h>
#endif /* USE_HOSTCC */
#include <compiler.h>
#include <u-boot/sha512.h>
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 64dee77..cc1dfe6 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -269,7 +269,8 @@
}
break;
case 'p':
- if (CONFIG_IS_ENABLED(NET) || _DEBUG) {
+ if (CONFIG_IS_ENABLED(NET) ||
+ CONFIG_IS_ENABLED(NET_LWIP) || _DEBUG) {
pointer(info, fmt, va_arg(va, void *));
/*
* Skip this because it pulls in _ctype which is
diff --git a/net/Kconfig b/net/Kconfig
index 7cb80b8..76ab7d9 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -2,11 +2,6 @@
# Network configuration
#
-menuconfig NET
- bool "Networking support"
- default y
- imply NETDEVICES
-
if NET
config ARP_TIMEOUT
@@ -26,15 +21,6 @@
Enable a generic udp framework that allows defining a custom
handler for udp protocol.
-config BOOTDEV_ETH
- bool "Enable bootdev for ethernet"
- depends on BOOTSTD
- default y
- help
- Provide a bootdev for ethernet so that is it possible to boot
- an operationg system over the network, using the PXE (Preboot
- Execution Environment) protocol.
-
config BOOTP_SEND_HOSTNAME
bool "Send hostname to DNS server"
help
@@ -45,15 +31,6 @@
of the "hostname" environment variable is passed as
option 12 to the DHCP server.
-config NET_RANDOM_ETHADDR
- bool "Random ethaddr if unset"
- help
- Selecting this will allow the Ethernet interface to function even
- when the ethaddr variable for that interface is unset. In this case,
- a random MAC address in the locally administered address space is
- generated. It will be saved to the appropriate environment variable,
- too.
-
config NETCONSOLE
bool "NetConsole support"
help
@@ -83,16 +60,6 @@
this option is active, then CONFIG_SYS_FAULT_MII_ADDR also needs to
be configured.
-config TFTP_BLOCKSIZE
- int "TFTP block size"
- default 1468
- help
- Default TFTP block size.
- The MTU is typically 1500 for ethernet, so a TFTP block of
- 1468 (MTU minus eth.hdrs) provides a good throughput with
- almost-MTU block sizes.
- You can also activate CONFIG_IP_DEFRAG to set a larger block.
-
config TFTP_PORT
bool "Set TFTP UDP source/destination ports via the environment"
help
@@ -255,11 +222,45 @@
endif # if NET
-config SYS_RX_ETH_BUFFER
- int "Number of receive packet buffers"
- default 4
+source "net/lwip/Kconfig"
+
+if NET || NET_LWIP
+
+config BOOTDEV_ETH
+ bool "Enable bootdev for ethernet"
+ depends on BOOTSTD
+ default y
+ help
+ Provide a bootdev for ethernet so that is it possible to boot
+ an operating system over the network, using the PXE (Preboot
+ Execution Environment) protocol.
+
+config NET_RANDOM_ETHADDR
+ bool "Random ethaddr if unset"
+ help
+ Selecting this will allow the Ethernet interface to function even
+ when the ethaddr variable for that interface is unset. In this case,
+ a random MAC address in the locally administered address space is
+ generated. It will be saved to the appropriate environment variable,
+ too.
+
+config TFTP_BLOCKSIZE
+ int "TFTP block size"
+ default 1468
help
- Defines the number of Ethernet receive buffers. On some Ethernet
- controllers it is recommended to set this value to 8 or even higher,
- since all buffers can be full shortly after enabling the interface on
- high Ethernet traffic.
+ Default TFTP block size.
+ The MTU is typically 1500 for ethernet, so a TFTP block of
+ 1468 (MTU minus eth.hdrs) provides a good throughput with
+ almost-MTU block sizes.
+ You can also activate CONFIG_IP_DEFRAG to set a larger block.
+
+endif # if NET || NET_LWIP
+
+config SYS_RX_ETH_BUFFER
+ int "Number of receive packet buffers"
+ default 4
+ help
+ Defines the number of Ethernet receive buffers. On some Ethernet
+ controllers it is recommended to set this value to 8 or even higher,
+ since all buffers can be full shortly after enabling the interface on
+ high Ethernet traffic.
diff --git a/net/Makefile b/net/Makefile
index a7075c3..209377a 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -5,16 +5,13 @@
#ccflags-y += -DDEBUG
+ifeq ($(CONFIG_NET),y)
+
obj-$(CONFIG_NET) += arp.o
obj-$(CONFIG_CMD_BOOTP) += bootp.o
obj-$(CONFIG_CMD_CDP) += cdp.o
obj-$(CONFIG_CMD_DNS) += dns.o
obj-$(CONFIG_DM_DSA) += dsa-uclass.o
-obj-$(CONFIG_$(XPL_)DM_ETH) += eth-uclass.o
-obj-$(CONFIG_$(PHASE_)BOOTDEV_ETH) += eth_bootdev.o
-obj-$(CONFIG_DM_MDIO) += mdio-uclass.o
-obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o
-obj-$(CONFIG_$(XPL_)DM_ETH) += eth_common.o
obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
obj-$(CONFIG_IPV6) += ndisc.o
obj-$(CONFIG_$(XPL_)DM_ETH) += net.o
@@ -38,3 +35,16 @@
# sprintf(buf, index ? "foo%d" : "foo", index)
# and this is intentional usage.
CFLAGS_eth_common.o += -Wno-format-extra-args
+
+endif
+
+ifeq ($(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)),y)
+obj-$(CONFIG_$(XPL_)DM_ETH) += eth-uclass.o
+obj-$(CONFIG_$(PHASE_)BOOTDEV_ETH) += eth_bootdev.o
+obj-$(CONFIG_DM_MDIO) += mdio-uclass.o
+obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o
+obj-$(CONFIG_$(XPL_)DM_ETH) += eth_common.o
+obj-y += net-common.o
+endif
+
+obj-$(CONFIG_NET_LWIP) += lwip/
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e34d7af..5555f82 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -284,6 +284,27 @@
}
U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr);
+int eth_start_udev(struct udevice *dev)
+{
+ struct eth_device_priv *priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ if (priv->running)
+ return 0;
+
+ if (!device_active(dev))
+ return -EINVAL;
+
+ ret = eth_get_ops(dev)->start(dev);
+ if (ret < 0)
+ return ret;
+
+ priv->state = ETH_STATE_ACTIVE;
+ priv->running = true;
+
+ return 0;
+}
+
int eth_init(void)
{
struct udevice *current = NULL;
@@ -328,20 +349,11 @@
if (current) {
debug("Trying %s\n", current->name);
- if (device_active(current)) {
- ret = eth_get_ops(current)->start(current);
- if (ret >= 0) {
- struct eth_device_priv *priv =
- dev_get_uclass_priv(current);
-
- priv->state = ETH_STATE_ACTIVE;
- priv->running = true;
- ret = 0;
- goto end;
- }
- } else {
+ ret = eth_start_udev(current);
+ if (ret < 0)
ret = eth_errno;
- }
+ else
+ break;
debug("FAIL\n");
} else {
diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig
new file mode 100644
index 0000000..8a67de4
--- /dev/null
+++ b/net/lwip/Kconfig
@@ -0,0 +1,49 @@
+#
+# Network configuration (with lwIP stack)
+#
+
+if NET_LWIP
+
+config LWIP_DEBUG
+ bool "Enable debug traces in the lwIP library"
+
+config LWIP_ASSERT
+ bool "Enable assertions in the lwIP library"
+
+config PROT_DHCP_LWIP
+ bool
+ select PROT_UDP_LWIP
+
+config PROT_DNS_LWIP
+ bool
+ select PROT_UDP_LWIP
+
+config PROT_RAW_LWIP
+ bool
+
+config PROT_TCP_LWIP
+ bool
+
+config PROT_TCP_SACK_LWIP
+ bool "TCP SACK support"
+ depends on PROT_TCP_LWIP
+ default y
+ help
+ TCP protocol with selective acknowledgements. Improves
+ file transfer speed in wget.
+
+config PROT_UDP_LWIP
+ bool
+
+config LWIP_TCP_WND
+ int "Value of TCP_WND"
+ default 8000 if ARCH_QEMU
+ default 3000000
+ help
+ Default value for TCP_WND in the lwIP configuration
+ Lower values result in slower wget transfer speeds in
+ general, especially when the latency on the network is high,
+ but QEMU with "-net user" needs no more than a few KB or the
+ transfer will stall and eventually time out.
+
+endif # NET_LWIP
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
new file mode 100644
index 0000000..f2558f8
--- /dev/null
+++ b/net/lwip/Makefile
@@ -0,0 +1,8 @@
+ccflags-y += -I$(srctree)/lib/lwip/lwip/src/include -I$(srctree)/lib/lwip/u-boot
+
+obj-$(CONFIG_$(SPL_)DM_ETH) += net-lwip.o
+obj-$(CONFIG_CMD_DHCP) += dhcp.o
+obj-$(CONFIG_CMD_DNS) += dns.o
+obj-$(CONFIG_CMD_PING) += ping.o
+obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
+obj-$(CONFIG_CMD_WGET) += wget.o
diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c
new file mode 100644
index 0000000..23b5622
--- /dev/null
+++ b/net/lwip/dhcp.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <console.h>
+#include <dm/device.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <lwip/dhcp.h>
+#include <lwip/dns.h>
+#include <lwip/timeouts.h>
+#include <net.h>
+#include <time.h>
+
+#define DHCP_TIMEOUT_MS 10000
+
+#ifdef CONFIG_CMD_TFTPBOOT
+/* Boot file obtained from DHCP (if present) */
+static char boot_file_name[DHCP_BOOT_FILE_LEN];
+#endif
+
+static void call_lwip_dhcp_fine_tmr(void *ctx)
+{
+ dhcp_fine_tmr();
+ sys_timeout(10, call_lwip_dhcp_fine_tmr, NULL);
+}
+
+static int dhcp_loop(struct udevice *udev)
+{
+ char *ipstr = "ipaddr\0\0";
+ char *maskstr = "netmask\0\0";
+ char *gwstr = "gatewayip\0\0";
+ unsigned long start;
+ struct netif *netif;
+ struct dhcp *dhcp;
+ bool bound;
+ int idx;
+
+ idx = dev_seq(udev);
+ if (idx < 0 || idx > 99) {
+ log_err("unexpected idx %d\n", idx);
+ return CMD_RET_FAILURE;
+ }
+
+ netif = net_lwip_new_netif_noip(udev);
+ if (!netif)
+ return CMD_RET_FAILURE;
+
+ start = get_timer(0);
+
+ if (dhcp_start(netif))
+ return CMD_RET_FAILURE;
+
+ call_lwip_dhcp_fine_tmr(NULL);
+
+ /* Wait for DHCP to complete */
+ do {
+ net_lwip_rx(udev, netif);
+ sys_check_timeouts();
+ bound = dhcp_supplied_address(netif);
+ if (bound)
+ break;
+ if (ctrlc()) {
+ printf("Abort\n");
+ break;
+ }
+ mdelay(1);
+ } while (get_timer(start) < DHCP_TIMEOUT_MS);
+
+ sys_untimeout(call_lwip_dhcp_fine_tmr, NULL);
+
+ if (!bound) {
+ net_lwip_remove_netif(netif);
+ return CMD_RET_FAILURE;
+ }
+
+ dhcp = netif_dhcp_data(netif);
+
+ env_set("bootfile", dhcp->boot_file_name);
+
+ if (idx > 0) {
+ sprintf(ipstr, "ipaddr%d", idx);
+ sprintf(maskstr, "netmask%d", idx);
+ sprintf(gwstr, "gatewayip%d", idx);
+ } else {
+ net_ip.s_addr = dhcp->offered_ip_addr.addr;
+ }
+
+ env_set(ipstr, ip4addr_ntoa(&dhcp->offered_ip_addr));
+ env_set(maskstr, ip4addr_ntoa(&dhcp->offered_sn_mask));
+ env_set("serverip", ip4addr_ntoa(&dhcp->server_ip_addr));
+ if (dhcp->offered_gw_addr.addr != 0)
+ env_set(gwstr, ip4addr_ntoa(&dhcp->offered_gw_addr));
+
+#ifdef CONFIG_PROT_DNS_LWIP
+ env_set("dnsip", ip4addr_ntoa(dns_getserver(0)));
+ env_set("dnsip2", ip4addr_ntoa(dns_getserver(1)));
+#endif
+#ifdef CONFIG_CMD_TFTPBOOT
+ if (dhcp->boot_file_name[0] != '\0')
+ strncpy(boot_file_name, dhcp->boot_file_name,
+ sizeof(boot_file_name));
+#endif
+
+ printf("DHCP client bound to address %pI4 (%lu ms)\n",
+ &dhcp->offered_ip_addr, get_timer(start));
+
+ net_lwip_remove_netif(netif);
+ return CMD_RET_SUCCESS;
+}
+
+int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ eth_set_current();
+
+ return dhcp_loop(eth_get_dev());
+}
+
+int dhcp_run(ulong addr, const char *fname, bool autoload)
+{
+ char *dhcp_argv[] = {"dhcp", NULL, };
+#ifdef CONFIG_CMD_TFTPBOOT
+ char *tftp_argv[] = {"tftpboot", boot_file_name, NULL, };
+#endif
+ struct cmd_tbl cmdtp = {}; /* dummy */
+
+ if (autoload) {
+#ifdef CONFIG_CMD_TFTPBOOT
+ /* Assume DHCP was already performed */
+ if (boot_file_name[0])
+ return do_tftpb(&cmdtp, 0, 2, tftp_argv);
+ return 0;
+#else
+ return -EOPNOTSUPP;
+#endif
+ }
+
+ return do_dhcp(&cmdtp, 0, 1, dhcp_argv);
+}
diff --git a/net/lwip/dns.c b/net/lwip/dns.c
new file mode 100644
index 0000000..4b937fe
--- /dev/null
+++ b/net/lwip/dns.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <console.h>
+#include <lwip/dns.h>
+#include <lwip/timeouts.h>
+#include <net.h>
+#include <time.h>
+
+#define DNS_RESEND_MS 1000
+#define DNS_TIMEOUT_MS 10000
+
+struct dns_cb_arg {
+ ip_addr_t host_ipaddr;
+ const char *var;
+ bool done;
+};
+
+static void do_dns_tmr(void *arg)
+{
+ dns_tmr();
+}
+
+static void dns_cb(const char *name, const ip_addr_t *ipaddr, void *arg)
+{
+ struct dns_cb_arg *dns_cb_arg = arg;
+ char *ipstr = ip4addr_ntoa(ipaddr);
+
+ dns_cb_arg->done = true;
+
+ if (!ipaddr) {
+ printf("DNS: host not found\n");
+ dns_cb_arg->host_ipaddr.addr = 0;
+ return;
+ }
+
+ if (dns_cb_arg->var)
+ env_set(dns_cb_arg->var, ipstr);
+
+ printf("%s\n", ipstr);
+}
+
+static int dns_loop(struct udevice *udev, const char *name, const char *var)
+{
+ struct dns_cb_arg dns_cb_arg = { };
+ bool has_server = false;
+ struct netif *netif;
+ ip_addr_t ipaddr;
+ ip_addr_t ns;
+ ulong start;
+ char *nsenv;
+ int ret;
+
+ dns_cb_arg.var = var;
+
+ netif = net_lwip_new_netif(udev);
+ if (!netif)
+ return -1;
+
+ dns_init();
+
+ nsenv = env_get("dnsip");
+ if (nsenv && ipaddr_aton(nsenv, &ns)) {
+ dns_setserver(0, &ns);
+ has_server = true;
+ }
+
+ nsenv = env_get("dnsip2");
+ if (nsenv && ipaddr_aton(nsenv, &ns)) {
+ dns_setserver(1, &ns);
+ has_server = true;
+ }
+
+ if (!has_server) {
+ log_err("No valid name server (dnsip/dnsip2)\n");
+ net_lwip_remove_netif(netif);
+ return CMD_RET_FAILURE;
+ }
+
+ dns_cb_arg.done = false;
+
+ ret = dns_gethostbyname(name, &ipaddr, dns_cb, &dns_cb_arg);
+
+ if (ret == ERR_OK) {
+ dns_cb(name, &ipaddr, &dns_cb_arg);
+ } else if (ret == ERR_INPROGRESS) {
+ start = get_timer(0);
+ sys_timeout(DNS_RESEND_MS, do_dns_tmr, NULL);
+ do {
+ net_lwip_rx(udev, netif);
+ if (dns_cb_arg.done)
+ break;
+ sys_check_timeouts();
+ if (ctrlc()) {
+ printf("\nAbort\n");
+ break;
+ }
+ } while (get_timer(start) < DNS_TIMEOUT_MS);
+ sys_untimeout(do_dns_tmr, NULL);
+ }
+
+ net_lwip_remove_netif(netif);
+
+ if (dns_cb_arg.done && dns_cb_arg.host_ipaddr.addr != 0)
+ return CMD_RET_SUCCESS;
+
+ return CMD_RET_FAILURE;
+}
+
+int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *name;
+ char *var = NULL;
+
+ if (argc == 1 || argc > 3)
+ return CMD_RET_USAGE;
+
+ name = argv[1];
+
+ if (argc == 3)
+ var = argv[2];
+
+ eth_set_current();
+
+ return dns_loop(eth_get_dev(), name, var);
+}
diff --git a/net/lwip/eth_internal.h b/net/lwip/eth_internal.h
new file mode 100644
index 0000000..0b829a8
--- /dev/null
+++ b/net/lwip/eth_internal.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001-2015
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Joe Hershberger, National Instruments
+ */
+
+#ifndef __ETH_INTERNAL_H
+#define __ETH_INTERNAL_H
+
+/* Do init that is common to driver model and legacy networking */
+void eth_common_init(void);
+
+/**
+ * eth_env_set_enetaddr_by_index() - set the MAC address environment variable
+ *
+ * This sets up an environment variable with the given MAC address (@enetaddr).
+ * The environment variable to be set is defined by <@base_name><@index>addr.
+ * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
+ * eth1addr, etc.
+ *
+ * @base_name: Base name for variable, typically "eth"
+ * @index: Index of interface being updated (>=0)
+ * @enetaddr: Pointer to MAC address to put into the variable
+ * Return: 0 if OK, other value on error
+ */
+int eth_env_set_enetaddr_by_index(const char *base_name, int index,
+ uchar *enetaddr);
+
+int eth_mac_skip(int index);
+void eth_current_changed(void);
+void eth_set_dev(struct udevice *dev);
+void eth_set_current_to_next(void);
+
+#endif
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
new file mode 100644
index 0000000..5c2bb2e
--- /dev/null
+++ b/net/lwip/net-lwip.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <lwip/ip4_addr.h>
+#include <lwip/err.h>
+#include <lwip/netif.h>
+#include <lwip/pbuf.h>
+#include <lwip/etharp.h>
+#include <lwip/init.h>
+#include <lwip/prot/etharp.h>
+#include <net.h>
+
+/* xx:xx:xx:xx:xx:xx\0 */
+#define MAC_ADDR_STRLEN 18
+
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
+void (*push_packet)(void *, int len) = 0;
+#endif
+int net_restart_wrap;
+static uchar net_pkt_buf[(PKTBUFSRX) * PKTSIZE_ALIGN + PKTALIGN];
+uchar *net_rx_packets[PKTBUFSRX];
+uchar *net_rx_packet;
+const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+char *pxelinux_configfile;
+/* Our IP addr (0 = unknown) */
+struct in_addr net_ip;
+char net_boot_file_name[1024];
+
+static err_t linkoutput(struct netif *netif, struct pbuf *p)
+{
+ struct udevice *udev = netif->state;
+ void *pp = NULL;
+ int err;
+
+ if ((unsigned long)p->payload % PKTALIGN) {
+ /*
+ * Some net drivers have strict alignment requirements and may
+ * fail or output invalid data if the packet is not aligned.
+ */
+ pp = memalign(PKTALIGN, p->len);
+ if (!pp)
+ return ERR_ABRT;
+ memcpy(pp, p->payload, p->len);
+ }
+
+ err = eth_get_ops(udev)->send(udev, pp ? pp : p->payload, p->len);
+ free(pp);
+ if (err) {
+ log_err("send error %d\n", err);
+ return ERR_ABRT;
+ }
+
+ return ERR_OK;
+}
+
+static err_t net_lwip_if_init(struct netif *netif)
+{
+ netif->output = etharp_output;
+ netif->linkoutput = linkoutput;
+ netif->mtu = 1500;
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+ return ERR_OK;
+}
+
+static void eth_init_rings(void)
+{
+ int i;
+
+ for (i = 0; i < PKTBUFSRX; i++)
+ net_rx_packets[i] = net_pkt_buf + i * PKTSIZE_ALIGN;
+}
+
+struct netif *net_lwip_get_netif(void)
+{
+ struct netif *netif, *found = NULL;
+
+ NETIF_FOREACH(netif) {
+ if (!found)
+ found = netif;
+ else
+ printf("Error: more than one netif in lwIP\n");
+ }
+ return found;
+}
+
+static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip,
+ ip4_addr_t *mask, ip4_addr_t *gw)
+{
+ char *ipstr = "ipaddr\0\0";
+ char *maskstr = "netmask\0\0";
+ char *gwstr = "gatewayip\0\0";
+ int idx = dev_seq(dev);
+ char *env;
+
+ if (idx < 0 || idx > 99) {
+ log_err("unexpected idx %d\n", idx);
+ return -1;
+ }
+
+ if (idx) {
+ sprintf(ipstr, "ipaddr%d", idx);
+ sprintf(maskstr, "netmask%d", idx);
+ sprintf(gwstr, "gatewayip%d", idx);
+ }
+
+ ip4_addr_set_zero(ip);
+ ip4_addr_set_zero(mask);
+ ip4_addr_set_zero(gw);
+
+ env = env_get(ipstr);
+ if (env)
+ ip4addr_aton(env, ip);
+
+ env = env_get(maskstr);
+ if (env)
+ ip4addr_aton(env, mask);
+
+ env = env_get(gwstr);
+ if (env)
+ ip4addr_aton(env, gw);
+
+ return 0;
+}
+
+static struct netif *new_netif(struct udevice *udev, bool with_ip)
+{
+ unsigned char enetaddr[ARP_HLEN];
+ char hwstr[MAC_ADDR_STRLEN];
+ ip4_addr_t ip, mask, gw;
+ struct netif *netif;
+ int ret = 0;
+ static bool first_call = true;
+
+ if (!udev)
+ return NULL;
+
+ if (first_call) {
+ eth_init_rings();
+ /* Pick a valid active device, if any */
+ eth_init();
+ lwip_init();
+ first_call = false;
+ }
+
+ if (eth_start_udev(udev) < 0) {
+ log_err("Could not start %s\n", udev->name);
+ return NULL;
+ }
+
+ netif_remove(net_lwip_get_netif());
+
+ ip4_addr_set_zero(&ip);
+ ip4_addr_set_zero(&mask);
+ ip4_addr_set_zero(&gw);
+
+ if (with_ip)
+ if (get_udev_ipv4_info(udev, &ip, &mask, &gw) < 0)
+ return NULL;
+
+ eth_env_get_enetaddr_by_index("eth", dev_seq(udev), enetaddr);
+ ret = snprintf(hwstr, MAC_ADDR_STRLEN, "%pM", enetaddr);
+ if (ret < 0 || ret >= MAC_ADDR_STRLEN)
+ return NULL;
+
+ netif = calloc(1, sizeof(struct netif));
+ if (!netif)
+ return NULL;
+
+ netif->name[0] = 'e';
+ netif->name[1] = 't';
+
+ string_to_enetaddr(hwstr, netif->hwaddr);
+ netif->hwaddr_len = ETHARP_HWADDR_LEN;
+ debug("adding lwIP netif for %s with hwaddr:%s ip:%s ", udev->name,
+ hwstr, ip4addr_ntoa(&ip));
+ debug("mask:%s ", ip4addr_ntoa(&mask));
+ debug("gw:%s\n", ip4addr_ntoa(&gw));
+
+ if (!netif_add(netif, &ip, &mask, &gw, udev, net_lwip_if_init,
+ netif_input)) {
+ printf("error: netif_add() failed\n");
+ free(netif);
+ return NULL;
+ }
+
+ netif_set_up(netif);
+ netif_set_link_up(netif);
+ /* Routing: use this interface to reach the default gateway */
+ netif_set_default(netif);
+
+ return netif;
+}
+
+struct netif *net_lwip_new_netif(struct udevice *udev)
+{
+ return new_netif(udev, true);
+}
+
+struct netif *net_lwip_new_netif_noip(struct udevice *udev)
+{
+
+ return new_netif(udev, false);
+}
+
+void net_lwip_remove_netif(struct netif *netif)
+{
+ netif_remove(netif);
+ free(netif);
+}
+
+int net_init(void)
+{
+ eth_set_current();
+
+ net_lwip_new_netif(eth_get_dev());
+
+ return 0;
+}
+
+static struct pbuf *alloc_pbuf_and_copy(uchar *data, int len)
+{
+ struct pbuf *p, *q;
+
+ /* We allocate a pbuf chain of pbufs from the pool. */
+ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+ if (!p) {
+ LINK_STATS_INC(link.memerr);
+ LINK_STATS_INC(link.drop);
+ return NULL;
+ }
+
+ for (q = p; q != NULL; q = q->next) {
+ memcpy(q->payload, data, q->len);
+ data += q->len;
+ }
+
+ LINK_STATS_INC(link.recv);
+
+ return p;
+}
+
+int net_lwip_rx(struct udevice *udev, struct netif *netif)
+{
+ struct pbuf *pbuf;
+ uchar *packet;
+ int flags;
+ int len;
+ int i;
+
+ if (!eth_is_active(udev))
+ return -EINVAL;
+
+ flags = ETH_RECV_CHECK_DEVICE;
+ for (i = 0; i < ETH_PACKETS_BATCH_RECV; i++) {
+ len = eth_get_ops(udev)->recv(udev, flags, &packet);
+ flags = 0;
+
+ if (len > 0) {
+ pbuf = alloc_pbuf_and_copy(packet, len);
+ if (pbuf)
+ netif->input(pbuf, netif);
+ }
+ if (len >= 0 && eth_get_ops(udev)->free_pkt)
+ eth_get_ops(udev)->free_pkt(udev, packet, len);
+ if (len <= 0)
+ break;
+ }
+ if (len == -EAGAIN)
+ len = 0;
+
+ return len;
+}
+
+void net_process_received_packet(uchar *in_packet, int len)
+{
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
+ if (push_packet)
+ (*push_packet)(in_packet, len);
+#endif
+}
+
+int net_loop(enum proto_t protocol)
+{
+ char *argv[1];
+
+ switch (protocol) {
+ case TFTPGET:
+ argv[0] = "tftpboot";
+ return do_tftpb(NULL, 0, 1, argv);
+ default:
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+u32_t sys_now(void)
+{
+ return get_timer(0);
+}
diff --git a/net/lwip/ping.c b/net/lwip/ping.c
new file mode 100644
index 0000000..8dafa25
--- /dev/null
+++ b/net/lwip/ping.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <console.h>
+#include <dm/device.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <lwip/icmp.h>
+#include <lwip/inet_chksum.h>
+#include <lwip/raw.h>
+#include <lwip/timeouts.h>
+#include <net.h>
+#include <time.h>
+
+#define PING_DELAY_MS 1000
+#define PING_COUNT 5
+/* Ping identifier - must fit on a u16_t */
+#define PING_ID 0xAFAF
+
+struct ping_ctx {
+ ip_addr_t target;
+ struct raw_pcb *pcb;
+ struct icmp_echo_hdr *iecho;
+ uint16_t seq_num;
+ bool alive;
+};
+
+static u8_t ping_recv(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *addr)
+{
+ struct ping_ctx *ctx = arg;
+ struct icmp_echo_hdr *iecho = ctx->iecho;
+
+ if (addr->addr != ctx->target.addr)
+ return 0;
+
+ if ((p->tot_len >= (IP_HLEN + sizeof(struct icmp_echo_hdr))) &&
+ pbuf_remove_header(p, IP_HLEN) == 0) {
+ iecho = (struct icmp_echo_hdr *)p->payload;
+
+ if ((iecho->id == PING_ID) &&
+ (iecho->seqno == lwip_htons(ctx->seq_num))) {
+ ctx->alive = true;
+ printf("host %s is alive\n", ipaddr_ntoa(addr));
+ pbuf_free(p);
+ return 1; /* eat the packet */
+ }
+ /* not eaten, restore original packet */
+ pbuf_add_header(p, IP_HLEN);
+ }
+
+ return 0; /* don't eat the packet */
+}
+
+static int ping_raw_init(struct ping_ctx *ctx)
+{
+ ctx->pcb = raw_new(IP_PROTO_ICMP);
+ if (!ctx->pcb)
+ return -ENOMEM;
+
+ raw_recv(ctx->pcb, ping_recv, ctx);
+ raw_bind(ctx->pcb, IP_ADDR_ANY);
+
+ return 0;
+}
+
+static void ping_raw_stop(struct ping_ctx *ctx)
+{
+ if (ctx->pcb)
+ raw_remove(ctx->pcb);
+}
+
+static void ping_prepare_echo(struct ping_ctx *ctx)
+{
+ struct icmp_echo_hdr *iecho = ctx->iecho;
+
+ ICMPH_TYPE_SET(iecho, ICMP_ECHO);
+ ICMPH_CODE_SET(iecho, 0);
+ iecho->chksum = 0;
+ iecho->id = PING_ID;
+ iecho->seqno = lwip_htons(ctx->seq_num);
+
+ iecho->chksum = inet_chksum(iecho, sizeof(*iecho));
+}
+
+static void ping_send_icmp(struct ping_ctx *ctx)
+{
+ struct pbuf *p;
+ size_t ping_size = sizeof(struct icmp_echo_hdr);
+
+ p = pbuf_alloc(PBUF_IP, (u16_t)ping_size, PBUF_RAM);
+ if (!p)
+ return;
+
+ if ((p->len == p->tot_len) && !p->next) {
+ ctx->iecho = (struct icmp_echo_hdr *)p->payload;
+ ping_prepare_echo(ctx);
+ raw_sendto(ctx->pcb, p, &ctx->target);
+ }
+
+ pbuf_free(p);
+}
+
+static void ping_send(void *arg)
+{
+ struct ping_ctx *ctx = arg;
+
+ ctx->seq_num++;
+ if (ctx->seq_num <= PING_COUNT) {
+ ping_send_icmp(ctx);
+ sys_timeout(PING_DELAY_MS, ping_send, ctx);
+ }
+}
+
+static int ping_loop(struct udevice *udev, const ip_addr_t* addr)
+{
+ struct ping_ctx ctx = {};
+ struct netif *netif;
+ int ret;
+
+ netif = net_lwip_new_netif(udev);
+ if (!netif)
+ return CMD_RET_FAILURE;
+
+ printf("Using %s device\n", udev->name);
+
+ ret = ping_raw_init(&ctx);
+ if (ret < 0) {
+ net_lwip_remove_netif(netif);
+ return ret;
+ }
+
+ ctx.target = *addr;
+
+ ping_send(&ctx);
+
+ do {
+ sys_check_timeouts();
+ net_lwip_rx(udev, netif);
+ if (ctx.alive)
+ break;
+ if (ctrlc()) {
+ printf("\nAbort\n");
+ break;
+ }
+ } while (ctx.seq_num <= PING_COUNT);
+
+ sys_untimeout(ping_send, &ctx);
+ ping_raw_stop(&ctx);
+
+ net_lwip_remove_netif(netif);
+
+ if (ctx.alive)
+ return 0;
+
+ printf("ping failed; host %s is not alive\n", ipaddr_ntoa(addr));
+ return -1;
+}
+
+int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ ip_addr_t addr;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!ipaddr_aton(argv[1], &addr))
+ return CMD_RET_USAGE;
+
+ eth_set_current();
+
+ if (ping_loop(eth_get_dev(), &addr) < 0)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c
new file mode 100644
index 0000000..f4d0a6a
--- /dev/null
+++ b/net/lwip/tftp.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <console.h>
+#include <display_options.h>
+#include <dm/device.h>
+#include <efi_loader.h>
+#include <image.h>
+#include <linux/delay.h>
+#include <lwip/apps/tftp_client.h>
+#include <lwip/timeouts.h>
+#include <mapmem.h>
+#include <net.h>
+#include <time.h>
+
+#define PROGRESS_PRINT_STEP_BYTES (10 * 1024)
+
+enum done_state {
+ NOT_DONE = 0,
+ SUCCESS,
+ FAILURE,
+ ABORTED
+};
+
+struct tftp_ctx {
+ ulong daddr;
+ ulong size;
+ ulong block_count;
+ ulong start_time;
+ enum done_state done;
+};
+
+static void *tftp_open(const char *fname, const char *mode, u8_t is_write)
+{
+ return NULL;
+}
+
+static void tftp_close(void *handle)
+{
+ struct tftp_ctx *ctx = handle;
+ ulong elapsed;
+
+ if (ctx->done == FAILURE || ctx->done == ABORTED) {
+ /* Closing after an error or Ctrl-C */
+ return;
+ }
+ ctx->done = SUCCESS;
+
+ elapsed = get_timer(ctx->start_time);
+ if (elapsed > 0) {
+ puts("\n\t "); /* Line up with "Loading: " */
+ print_size(ctx->size / elapsed * 1000, "/s");
+ }
+ puts("\ndone\n");
+ printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size);
+
+ if (env_set_hex("filesize", ctx->size)) {
+ log_err("filesize not updated\n");
+ return;
+ }
+}
+
+static int tftp_read(void *handle, void *buf, int bytes)
+{
+ return 0;
+}
+
+static int tftp_write(void *handle, struct pbuf *p)
+{
+ struct tftp_ctx *ctx = handle;
+ struct pbuf *q;
+
+ for (q = p; q != NULL; q = q->next) {
+ memcpy((void *)ctx->daddr, q->payload, q->len);
+ ctx->daddr += q->len;
+ ctx->size += q->len;
+ ctx->block_count++;
+ if (ctx->block_count % 10 == 0) {
+ putc('#');
+ if (ctx->block_count % (65 * 10) == 0)
+ puts("\n\t ");
+ }
+ }
+
+ return 0;
+}
+
+static void tftp_error(void *handle, int err, const char *msg, int size)
+{
+ struct tftp_ctx *ctx = handle;
+ char message[100];
+
+ ctx->done = FAILURE;
+ memset(message, 0, sizeof(message));
+ memcpy(message, msg, LWIP_MIN(sizeof(message) - 1, (size_t)size));
+
+ printf("\nTFTP error: %d (%s)\n", err, message);
+}
+
+static const struct tftp_context tftp_context = {
+ tftp_open,
+ tftp_close,
+ tftp_read,
+ tftp_write,
+ tftp_error
+};
+
+static int tftp_loop(struct udevice *udev, ulong addr, char *fname,
+ ip_addr_t srvip, uint16_t srvport)
+{
+ struct netif *netif;
+ struct tftp_ctx ctx;
+ err_t err;
+
+ if (!fname || addr == 0)
+ return -1;
+
+ if (!srvport)
+ srvport = TFTP_PORT;
+
+ netif = net_lwip_new_netif(udev);
+ if (!netif)
+ return -1;
+
+ ctx.done = NOT_DONE;
+ ctx.size = 0;
+ ctx.block_count = 0;
+ ctx.daddr = addr;
+
+ printf("Using %s device\n", udev->name);
+ printf("TFTP from server %s; our IP address is %s\n",
+ ip4addr_ntoa(&srvip), env_get("ipaddr"));
+ printf("Filename '%s'.\n", fname);
+ printf("Load address: 0x%lx\n", ctx.daddr);
+ printf("Loading: ");
+
+ err = tftp_init_client(&tftp_context);
+ if (!(err == ERR_OK || err == ERR_USE))
+ log_err("tftp_init_client err: %d\n", err);
+
+ tftp_client_set_blksize(CONFIG_TFTP_BLOCKSIZE);
+
+ ctx.start_time = get_timer(0);
+ err = tftp_get(&ctx, &srvip, srvport, fname, TFTP_MODE_OCTET);
+ /* might return different errors, like routing problems */
+ if (err != ERR_OK) {
+ printf("tftp_get() error %d\n", err);
+ net_lwip_remove_netif(netif);
+ return -1;
+ }
+
+ while (!ctx.done) {
+ net_lwip_rx(udev, netif);
+ sys_check_timeouts();
+ if (ctrlc()) {
+ printf("\nAbort\n");
+ ctx.done = ABORTED;
+ break;
+ }
+ }
+
+ tftp_cleanup();
+
+ net_lwip_remove_netif(netif);
+
+ if (ctx.done == SUCCESS) {
+ if (env_set_hex("fileaddr", addr)) {
+ log_err("fileaddr not updated\n");
+ return -1;
+ }
+ efi_set_bootdev("Net", "", fname, map_sysmem(addr, 0),
+ ctx.size);
+ return 0;
+ }
+
+ return -1;
+}
+
+int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = CMD_RET_SUCCESS;
+ char *arg = NULL;
+ char *words[3] = { };
+ char *fname = NULL;
+ char *server_ip = NULL;
+ char *server_port = NULL;
+ char *end;
+ ip_addr_t srvip;
+ uint16_t port = TFTP_PORT;
+ ulong laddr;
+ ulong addr;
+ int i;
+
+ laddr = env_get_ulong("loadaddr", 16, image_load_addr);
+
+ switch (argc) {
+ case 1:
+ fname = env_get("bootfile");
+ break;
+ case 2:
+ /*
+ * Only one arg - accept two forms:
+ * Just load address, or just boot file name. The latter
+ * form must be written in a format which can not be
+ * mis-interpreted as a valid number.
+ */
+ addr = hextoul(argv[1], &end);
+ if (end == (argv[1] + strlen(argv[1]))) {
+ laddr = addr;
+ fname = env_get("bootfile");
+ } else {
+ arg = strdup(argv[1]);
+ }
+ break;
+ case 3:
+ laddr = hextoul(argv[1], NULL);
+ arg = strdup(argv[2]);
+ break;
+ default:
+ ret = CMD_RET_USAGE;
+ goto out;
+ }
+
+ if (!arg)
+ arg = net_boot_file_name;
+
+ if (arg) {
+ /* Parse [ip:[port:]]fname */
+ i = 0;
+ while ((*(words + i) = strsep(&arg,":")))
+ i++;
+
+ switch (i) {
+ case 3:
+ server_ip = words[0];
+ server_port = words[1];
+ fname = words[2];
+ break;
+ case 2:
+ server_ip = words[0];
+ fname = words[1];
+ break;
+ case 1:
+ fname = words[0];
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!server_ip)
+ server_ip = env_get("tftpserverip");
+ if (!server_ip)
+ server_ip = env_get("serverip");
+ if (!server_ip) {
+ log_err("error: tftpserverip/serverip has to be set\n");
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ if (server_port)
+ port = dectoul(server_port, NULL);
+
+ if (!ipaddr_aton(server_ip, &srvip)) {
+ log_err("error: ipaddr_aton\n");
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ if (!fname) {
+ log_err("error: no file name\n");
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ if (!laddr) {
+ log_err("error: no load address\n");
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ eth_set_current();
+
+ if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0)
+ ret = CMD_RET_FAILURE;
+out:
+ free(arg);
+ return ret;
+}
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
new file mode 100644
index 0000000..b495ebd
--- /dev/null
+++ b/net/lwip/wget.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2024 Linaro Ltd. */
+
+#include <command.h>
+#include <console.h>
+#include <display_options.h>
+#include <efi_loader.h>
+#include <image.h>
+#include <lwip/apps/http_client.h>
+#include <lwip/timeouts.h>
+#include <mapmem.h>
+#include <net.h>
+#include <time.h>
+
+#define SERVER_NAME_SIZE 200
+#define HTTP_PORT_DEFAULT 80
+#define PROGRESS_PRINT_STEP_BYTES (100 * 1024)
+
+enum done_state {
+ NOT_DONE = 0,
+ SUCCESS = 1,
+ FAILURE = 2
+};
+
+struct wget_ctx {
+ char *path;
+ ulong daddr;
+ ulong saved_daddr;
+ ulong size;
+ ulong prevsize;
+ ulong start_time;
+ enum done_state done;
+};
+
+static int parse_url(char *url, char *host, u16 *port, char **path)
+{
+ char *p, *pp;
+ long lport;
+
+ p = strstr(url, "http://");
+ if (!p) {
+ log_err("only http:// is supported\n");
+ return -EINVAL;
+ }
+
+ p += strlen("http://");
+
+ /* Parse hostname */
+ pp = strchr(p, ':');
+ if (!pp)
+ pp = strchr(p, '/');
+ if (!pp)
+ return -EINVAL;
+
+ if (p + SERVER_NAME_SIZE <= pp)
+ return -EINVAL;
+
+ memcpy(host, p, pp - p);
+ host[pp - p] = '\0';
+
+ if (*pp == ':') {
+ /* Parse port number */
+ p = pp + 1;
+ lport = simple_strtol(p, &pp, 10);
+ if (pp && *pp != '/')
+ return -EINVAL;
+ if (lport > 65535)
+ return -EINVAL;
+ *port = (u16)lport;
+ } else {
+ *port = HTTP_PORT_DEFAULT;
+ }
+ if (*pp != '/')
+ return -EINVAL;
+ *path = pp;
+
+ return 0;
+}
+
+/*
+ * Legacy syntax support
+ * Convert [<server_name_or_ip>:]filename into a URL if needed
+ */
+static int parse_legacy_arg(char *arg, char *nurl, size_t rem)
+{
+ char *p = nurl;
+ size_t n;
+ char *col = strchr(arg, ':');
+ char *env;
+ char *server;
+ char *path;
+
+ if (strstr(arg, "http") == arg) {
+ n = snprintf(nurl, rem, "%s", arg);
+ if (n < 0 || n > rem)
+ return -1;
+ return 0;
+ }
+
+ n = snprintf(p, rem, "%s", "http://");
+ if (n < 0 || n > rem)
+ return -1;
+ p += n;
+ rem -= n;
+
+ if (col) {
+ n = col - arg;
+ server = arg;
+ path = col + 1;
+ } else {
+ env = env_get("httpserverip");
+ if (!env)
+ env = env_get("serverip");
+ if (!env) {
+ log_err("error: httpserver/serverip has to be set\n");
+ return -1;
+ }
+ n = strlen(env);
+ server = env;
+ path = arg;
+ }
+
+ if (rem < n)
+ return -1;
+ strncpy(p, server, n);
+ p += n;
+ rem -= n;
+ if (rem < 1)
+ return -1;
+ *p = '/';
+ p++;
+ rem--;
+ n = strlen(path);
+ if (rem < n)
+ return -1;
+ strncpy(p, path, n);
+ p += n;
+ rem -= n;
+ if (rem < 1)
+ return -1;
+ *p = '\0';
+
+ return 0;
+}
+
+static err_t httpc_recv_cb(void *arg, struct altcp_pcb *pcb, struct pbuf *pbuf,
+ err_t err)
+{
+ struct wget_ctx *ctx = arg;
+ struct pbuf *buf;
+
+ if (!pbuf)
+ return ERR_BUF;
+
+ if (!ctx->start_time)
+ ctx->start_time = get_timer(0);
+
+ for (buf = pbuf; buf; buf = buf->next) {
+ memcpy((void *)ctx->daddr, buf->payload, buf->len);
+ ctx->daddr += buf->len;
+ ctx->size += buf->len;
+ if (ctx->size - ctx->prevsize > PROGRESS_PRINT_STEP_BYTES) {
+ printf("#");
+ ctx->prevsize = ctx->size;
+ }
+ }
+
+ altcp_recved(pcb, pbuf->tot_len);
+ pbuf_free(pbuf);
+ return ERR_OK;
+}
+
+static void httpc_result_cb(void *arg, httpc_result_t httpc_result,
+ u32_t rx_content_len, u32_t srv_res, err_t err)
+{
+ struct wget_ctx *ctx = arg;
+ ulong elapsed;
+
+ if (httpc_result != HTTPC_RESULT_OK) {
+ log_err("\nHTTP client error %d\n", httpc_result);
+ ctx->done = FAILURE;
+ return;
+ }
+ if (srv_res != 200) {
+ log_err("\nHTTP server error %d\n", srv_res);
+ ctx->done = FAILURE;
+ return;
+ }
+
+ elapsed = get_timer(ctx->start_time);
+ if (!elapsed)
+ elapsed = 1;
+ if (rx_content_len > PROGRESS_PRINT_STEP_BYTES)
+ printf("\n");
+ printf("%u bytes transferred in %lu ms (", rx_content_len, elapsed);
+ print_size(rx_content_len / elapsed * 1000, "/s)\n");
+ printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size);
+ efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0),
+ rx_content_len);
+ if (env_set_hex("filesize", rx_content_len) ||
+ env_set_hex("fileaddr", ctx->saved_daddr)) {
+ log_err("Could not set filesize or fileaddr\n");
+ ctx->done = FAILURE;
+ return;
+ }
+
+ ctx->done = SUCCESS;
+}
+
+static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
+{
+ char server_name[SERVER_NAME_SIZE];
+ httpc_connection_t conn;
+ httpc_state_t *state;
+ struct netif *netif;
+ struct wget_ctx ctx;
+ char *path;
+ u16 port;
+
+ ctx.daddr = dst_addr;
+ ctx.saved_daddr = dst_addr;
+ ctx.done = NOT_DONE;
+ ctx.size = 0;
+ ctx.prevsize = 0;
+ ctx.start_time = 0;
+
+ if (parse_url(uri, server_name, &port, &path))
+ return CMD_RET_USAGE;
+
+ netif = net_lwip_new_netif(udev);
+ if (!netif)
+ return -1;
+
+ memset(&conn, 0, sizeof(conn));
+ conn.result_fn = httpc_result_cb;
+ ctx.path = path;
+ if (httpc_get_file_dns(server_name, port, path, &conn, httpc_recv_cb,
+ &ctx, &state)) {
+ net_lwip_remove_netif(netif);
+ return CMD_RET_FAILURE;
+ }
+
+ while (!ctx.done) {
+ net_lwip_rx(udev, netif);
+ sys_check_timeouts();
+ if (ctrlc())
+ break;
+ }
+
+ net_lwip_remove_netif(netif);
+
+ if (ctx.done == SUCCESS)
+ return 0;
+
+ return -1;
+}
+
+int wget_with_dns(ulong dst_addr, char *uri)
+{
+ eth_set_current();
+
+ return wget_loop(eth_get_dev(), dst_addr, uri);
+}
+
+int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *end;
+ char *url;
+ ulong dst_addr;
+ char nurl[1024];
+
+ if (argc < 2 || argc > 3)
+ return CMD_RET_USAGE;
+
+ dst_addr = hextoul(argv[1], &end);
+ if (end == (argv[1] + strlen(argv[1]))) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ url = argv[2];
+ } else {
+ dst_addr = image_load_addr;
+ url = argv[1];
+ }
+
+ if (parse_legacy_arg(url, nurl, sizeof(nurl)))
+ return CMD_RET_FAILURE;
+
+ if (wget_with_dns(dst_addr, nurl))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * wget_validate_uri() - validate the uri for wget
+ *
+ * @uri: uri string
+ *
+ * This function follows the current U-Boot wget implementation.
+ * scheme: only "http:" is supported
+ * authority:
+ * - user information: not supported
+ * - host: supported
+ * - port: not supported(always use the default port)
+ *
+ * Uri is expected to be correctly percent encoded.
+ * This is the minimum check, control codes(0x1-0x19, 0x7F, except '\0')
+ * and space character(0x20) are not allowed.
+ *
+ * TODO: stricter uri conformance check
+ *
+ * Return: true on success, false on failure
+ */
+bool wget_validate_uri(char *uri)
+{
+ char c;
+ bool ret = true;
+ char *str_copy, *s, *authority;
+
+ for (c = 0x1; c < 0x21; c++) {
+ if (strchr(uri, c)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+ }
+ if (strchr(uri, 0x7f)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+
+ if (strncmp(uri, "http://", 7)) {
+ log_err("only http:// is supported\n");
+ return false;
+ }
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return false;
+
+ s = str_copy + strlen("http://");
+ authority = strsep(&s, "/");
+ if (!s) {
+ log_err("invalid uri, no file path\n");
+ ret = false;
+ goto out;
+ }
+ s = strchr(authority, '@');
+ if (s) {
+ log_err("user information is not supported\n");
+ ret = false;
+ goto out;
+ }
+
+out:
+ free(str_copy);
+
+ return ret;
+}
diff --git a/net/net-common.c b/net/net-common.c
new file mode 100644
index 0000000..a7f767d
--- /dev/null
+++ b/net/net-common.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+void copy_filename(char *dst, const char *src, int size)
+{
+ if (src && *src && (*src == '"')) {
+ ++src;
+ --size;
+ }
+
+ while ((--size > 0) && src && *src && (*src != '"'))
+ *dst++ = *src++;
+ *dst = '\0';
+}
diff --git a/net/net.c b/net/net.c
index 64bcf69..f47e9fb 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1693,18 +1693,6 @@
ip->udp_xsum = 0;
}
-void copy_filename(char *dst, const char *src, int size)
-{
- if (src && *src && (*src == '"')) {
- ++src;
- --size;
- }
-
- while ((--size > 0) && src && *src && (*src != '"'))
- *dst++ = *src++;
- *dst = '\0';
-}
-
int is_serverip_in_cmd(void)
{
return !!strchr(net_boot_file_name, ':');
diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts
index 1fe142f..685e337 100644
--- a/scripts/Makefile.dts
+++ b/scripts/Makefile.dts
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST)))
+dtb-y += $(patsubst %,%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
ifeq ($(CONFIG_OF_UPSTREAM_BUILD_VENDOR),y)
ifeq ($(CONFIG_ARM64),y)
@@ -21,4 +22,10 @@
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
+ifneq ($(CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS),)
+PHONY += dtbos
+dtbos: $(addprefix $(obj)/, $(filter-out %.dtb,$(dtb-y)))
+ @:
+endif
+
clean-files := *.dtb *.dtbo */*.dtb */*.dtbo *_HS
diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped
index 56cc5d4..e465948 100644
--- a/scripts/dtc/pylibfdt/libfdt.i_shipped
+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped
@@ -1037,7 +1037,7 @@
fdt_string(fdt1, fdt32_to_cpu($1->nameoff)));
buff = PyByteArray_FromStringAndSize(
(const char *)($1 + 1), fdt32_to_cpu($1->len));
- resultobj = SWIG_Python_AppendOutput(resultobj, buff);
+ resultobj = SWIG_AppendOutput(resultobj, buff);
}
}
@@ -1076,7 +1076,7 @@
%typemap(argout) int *depth {
PyObject *val = Py_BuildValue("i", *arg$argnum);
- resultobj = SWIG_Python_AppendOutput(resultobj, val);
+ resultobj = SWIG_AppendOutput(resultobj, val);
}
%apply int *depth { int *depth };
@@ -1092,7 +1092,7 @@
if (PyTuple_GET_SIZE(resultobj) == 0)
resultobj = val;
else
- resultobj = SWIG_Python_AppendOutput(resultobj, val);
+ resultobj = SWIG_AppendOutput(resultobj, val);
}
}
diff --git a/test/bloblist.c b/test/bloblist.c
index fd85c7a..e0ad94e 100644
--- a/test/bloblist.c
+++ b/test/bloblist.c
@@ -94,7 +94,7 @@
return 1;
}
-BLOBLIST_TEST(bloblist_test_init, 0);
+BLOBLIST_TEST(bloblist_test_init, UFT_BLOBLIST);
static int bloblist_test_blob(struct unit_test_state *uts)
{
@@ -134,7 +134,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_blob, 0);
+BLOBLIST_TEST(bloblist_test_blob, UFT_BLOBLIST);
/* Check bloblist_ensure_size_ret() */
static int bloblist_test_blob_ensure(struct unit_test_state *uts)
@@ -168,7 +168,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_blob_ensure, 0);
+BLOBLIST_TEST(bloblist_test_blob_ensure, UFT_BLOBLIST);
static int bloblist_test_bad_blob(struct unit_test_state *uts)
{
@@ -184,7 +184,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_bad_blob, 0);
+BLOBLIST_TEST(bloblist_test_bad_blob, UFT_BLOBLIST);
static int bloblist_test_checksum(struct unit_test_state *uts)
{
@@ -257,7 +257,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_checksum, 0);
+BLOBLIST_TEST(bloblist_test_checksum, UFT_BLOBLIST);
/* Test the 'bloblist info' command */
static int bloblist_test_cmd_info(struct unit_test_state *uts)
@@ -278,7 +278,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_info, UTF_CONSOLE);
+BLOBLIST_TEST(bloblist_test_cmd_info, UFT_BLOBLIST | UTF_CONSOLE);
/* Test the 'bloblist list' command */
static int bloblist_test_cmd_list(struct unit_test_state *uts)
@@ -300,7 +300,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_list, UTF_CONSOLE);
+BLOBLIST_TEST(bloblist_test_cmd_list, UFT_BLOBLIST | UTF_CONSOLE);
/* Test alignment of bloblist blobs */
static int bloblist_test_align(struct unit_test_state *uts)
@@ -358,7 +358,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_align, 0);
+BLOBLIST_TEST(bloblist_test_align, UFT_BLOBLIST);
/* Test relocation of a bloblist */
static int bloblist_test_reloc(struct unit_test_state *uts)
@@ -392,7 +392,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_reloc, 0);
+BLOBLIST_TEST(bloblist_test_reloc, UFT_BLOBLIST);
/* Test expansion of a blob */
static int bloblist_test_grow(struct unit_test_state *uts)
@@ -445,7 +445,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_grow, 0);
+BLOBLIST_TEST(bloblist_test_grow, UFT_BLOBLIST);
/* Test shrinking of a blob */
static int bloblist_test_shrink(struct unit_test_state *uts)
@@ -495,7 +495,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_shrink, 0);
+BLOBLIST_TEST(bloblist_test_shrink, UFT_BLOBLIST);
/* Test failing to adjust a blob size */
static int bloblist_test_resize_fail(struct unit_test_state *uts)
@@ -530,7 +530,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_resize_fail, 0);
+BLOBLIST_TEST(bloblist_test_resize_fail, UFT_BLOBLIST);
/* Test expanding the last blob in a bloblist */
static int bloblist_test_resize_last(struct unit_test_state *uts)
@@ -581,7 +581,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_resize_last, 0);
+BLOBLIST_TEST(bloblist_test_resize_last, UFT_BLOBLIST);
/* Check a completely full bloblist */
static int bloblist_test_blob_maxsize(struct unit_test_state *uts)
@@ -604,7 +604,7 @@
return 0;
}
-BLOBLIST_TEST(bloblist_test_blob_maxsize, 0);
+BLOBLIST_TEST(bloblist_test_blob_maxsize, UFT_BLOBLIST);
int do_ut_bloblist(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 369105c..369c611 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -630,7 +630,7 @@
ut_assertok(bootdev_next_label(&iter, &dev, &mflags));
ut_assert_nextline("scanning bus for devices...");
ut_assert_skip_to_line(
- " Capacity: 1.9 MB = 0.0 GB (4095 x 512)");
+ " Capacity: 2.0 MB = 0.0 GB (4096 x 512)");
ut_assert_console_end();
ut_assertnonnull(dev);
ut_asserteq_str("scsi.id0lun0.bootdev", dev->name);
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 154dea7..2f859c4 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -370,7 +370,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_iter, UTF_DM | UTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_iter, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL)
/* Check using the system bootdev */
@@ -542,7 +542,7 @@
/* Enable the script bootmeth too */
ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_2script),
- "bootmeth_script", 0, ofnode_null(), &dev));
+ "script", 0, ofnode_null(), &dev));
/* Enable the cros bootmeth if needed */
if (IS_ENABLED(CONFIG_BOOTMETH_CROS) && bind_cros_android) {
@@ -857,6 +857,9 @@
ofnode node;
int i;
+ if (!CONFIG_IS_ENABLED(BOOTSTD_MENU))
+ return -EAGAIN;
+
ut_assertok(scan_mmc4_bootdev(uts));
ut_assertok(bootflow_menu_new(&exp));
diff --git a/test/boot/cedit.c b/test/boot/cedit.c
index 1f7af8e..4d1b99b 100644
--- a/test/boot/cedit.c
+++ b/test/boot/cedit.c
@@ -31,9 +31,11 @@
* ^N Move down to second item
* ^M Select item
* \e Quit
+ *
+ * cedit_run() returns -EACCESS so this command returns CMD_RET_FAILURE
*/
console_in_puts("\x0e\x0d\x0e\x0d\e");
- ut_assertok(run_command("cedit run", 0));
+ ut_asserteq(1, run_command("cedit run", 0));
exp = cur_exp;
scn = expo_lookup_scene_id(exp, exp->scene_id);
@@ -94,14 +96,16 @@
ut_asserteq(ID_CPU_SPEED_2,
ofnode_read_u32_default(node, "cpu-speed", 0));
+ ut_asserteq(3,
+ ofnode_read_u32_default(node, "cpu-speed-value", 0));
ut_asserteq_str("2.5 GHz", ofnode_read_string(node, "cpu-speed-str"));
ut_asserteq_str("my-machine", ofnode_read_string(node, "machine-name"));
- /* There should only be 5 properties */
+ /* There should only be 7 properties */
for (i = 0, ofnode_first_property(node, &prop); ofprop_valid(&prop);
i++, ofnode_next_property(&prop))
;
- ut_asserteq(5, i);
+ ut_asserteq(7, i);
ut_assert_console_end();
@@ -147,14 +151,16 @@
strcpy(str, "my-machine");
ut_assertok(run_command("cedit write_env -v", 0));
- ut_assert_nextlinen("c.cpu-speed=7");
+ ut_assert_nextlinen("c.cpu-speed=11");
ut_assert_nextlinen("c.cpu-speed-str=2.5 GHz");
- ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_nextlinen("c.cpu-speed-value=3");
+ ut_assert_nextlinen("c.power-loss=14");
ut_assert_nextlinen("c.power-loss-str=Always Off");
+ ut_assert_nextlinen("c.power-loss-value=0");
ut_assert_nextlinen("c.machine-name=my-machine");
ut_assert_console_end();
- ut_asserteq(7, env_get_ulong("c.cpu-speed", 10, 0));
+ ut_asserteq(11, env_get_ulong("c.cpu-speed", 10, 0));
ut_asserteq_str("2.5 GHz", env_get("c.cpu-speed-str"));
ut_asserteq_str("my-machine", env_get("c.machine-name"));
@@ -163,8 +169,8 @@
*str = '\0';
ut_assertok(run_command("cedit read_env -v", 0));
- ut_assert_nextlinen("c.cpu-speed=7");
- ut_assert_nextlinen("c.power-loss=10");
+ ut_assert_nextlinen("c.cpu-speed=11");
+ ut_assert_nextlinen("c.power-loss=14");
ut_assert_nextlinen("c.machine-name=my-machine");
ut_assert_console_end();
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 9b4aa80..db14ff8 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -91,7 +91,7 @@
*name = '\0';
ut_assertnonnull(exp);
ut_asserteq(0, exp->scene_id);
- ut_asserteq(0, exp->next_id);
+ ut_asserteq(EXPOID_BASE_ID, exp->next_id);
/* Make sure the name was allocated */
ut_assertnonnull(exp->name);
@@ -130,7 +130,7 @@
ut_assertok(expo_new(EXPO_NAME, NULL, &exp));
scn = NULL;
- ut_asserteq(0, exp->next_id);
+ ut_asserteq(EXPOID_BASE_ID, exp->next_id);
strcpy(name, SCENE_NAME1);
id = scene_new(exp, name, SCENE1, &scn);
*name = '\0';
@@ -151,7 +151,7 @@
scn = NULL;
id = scene_new(exp, SCENE_NAME2, 0, &scn);
ut_assertnonnull(scn);
- ut_assertok(scene_title_set(scn, title_id));
+ scn->title_id = title_id;
ut_asserteq(STR_SCENE_TITLE + 1, id);
ut_asserteq(STR_SCENE_TITLE + 2, exp->next_id);
ut_asserteq_ptr(exp, scn->expo);
@@ -167,6 +167,25 @@
}
BOOTSTD_TEST(expo_scene, UTF_DM | UTF_SCAN_FDT);
+/* Check creating a scene with no ID */
+static int expo_scene_no_id(struct unit_test_state *uts)
+{
+ struct scene *scn;
+ struct expo *exp;
+ char name[100];
+ int id;
+
+ ut_assertok(expo_new(EXPO_NAME, NULL, &exp));
+ ut_asserteq(EXPOID_BASE_ID, exp->next_id);
+
+ strcpy(name, SCENE_NAME1);
+ id = scene_new(exp, SCENE_NAME1, 0, &scn);
+ ut_asserteq(EXPOID_BASE_ID, scn->id);
+
+ return 0;
+}
+BOOTSTD_TEST(expo_scene_no_id, UTF_DM | UTF_SCAN_FDT);
+
/* Check creating a scene with objects */
static int expo_object(struct unit_test_state *uts)
{
@@ -698,6 +717,7 @@
ut_asserteq(0, item->desc_id);
ut_asserteq(0, item->preview_id);
ut_asserteq(0, item->flags);
+ ut_asserteq(0, item->value);
txt = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE);
ut_asserteq_str("2 GHz", expo_get_str(exp, txt->str_id));
diff --git a/test/boot/files/expo_ids.h b/test/boot/files/expo_ids.h
index a86e0d0..ffb5113 100644
--- a/test/boot/files/expo_ids.h
+++ b/test/boot/files/expo_ids.h
@@ -4,8 +4,7 @@
*/
enum {
- ZERO,
- ID_PROMPT,
+ ID_PROMPT = EXPOID_BASE_ID,
ID_SCENE1,
ID_SCENE1_TITLE,
diff --git a/test/boot/files/expo_layout.dts b/test/boot/files/expo_layout.dts
index bed5522..9bc1e49 100644
--- a/test/boot/files/expo_layout.dts
+++ b/test/boot/files/expo_layout.dts
@@ -39,8 +39,11 @@
item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2
ID_CPU_SPEED_3>;
+ /* values for the menu items */
+ item-value = <0 3 6>;
+
start-bit = <0x400>;
- bit-length = <2>;
+ bit-length = <3>;
};
power-loss {
diff --git a/test/bootm.c b/test/bootm.c
index 26c1555..52b83f1 100644
--- a/test/bootm.c
+++ b/test/bootm.c
@@ -26,12 +26,15 @@
{
char buf[BUF_SIZE];
+ /* This tests relies on GD_FLG_SILENT not being set */
+ gd->flags &= ~GD_FLG_SILENT;
+
*buf = '\0';
- ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, true));
+ ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
ut_asserteq_str("", buf);
strcpy(buf, "test");
- ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, true));
+ ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
ut_asserteq_str("test", buf);
return 0;
@@ -43,23 +46,26 @@
{
char buf[BUF_SIZE];
+ /* This tests relies on GD_FLG_SILENT not being set */
+ gd->flags &= ~GD_FLG_SILENT;
+
/* Zero buffer size */
*buf = '\0';
- ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, 0, true));
+ ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, 0, BOOTM_CL_ALL));
/* Buffer string not terminated */
memset(buf, 'a', BUF_SIZE);
- ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, BUF_SIZE, true));
+ ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
/* Not enough space to copy string */
memset(buf, '\0', BUF_SIZE);
memset(buf, 'a', BUF_SIZE / 2);
- ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, BUF_SIZE, true));
+ ut_asserteq(-ENOSPC, bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
/* Just enough space */
memset(buf, '\0', BUF_SIZE);
memset(buf, 'a', BUF_SIZE / 2 - 1);
- ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, true));
+ ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
return 0;
}
@@ -70,6 +76,9 @@
{
char buf[BUF_SIZE];
+ /* This tests relies on GD_FLG_SILENT not being set */
+ gd->flags &= ~GD_FLG_SILENT;
+
/* 'silent_linux' not set should do nothing */
env_set("silent_linux", NULL);
strcpy(buf, CONSOLE_STR);
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 8f21349..0055330 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -12,25 +12,30 @@
obj-$(CONFIG_CMD_PAUSE) += test_pause.o
endif
obj-y += exit.o mem.o
+obj-$(CONFIG_X86) += cpuid.o msr.o
obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
+obj-$(CONFIG_COREBOOT_SYSINFO) += coreboot.o
obj-$(CONFIG_CMD_FDT) += fdt.o
obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
obj-$(CONFIG_CMD_HISTORY) += history.o
obj-$(CONFIG_CMD_LOADM) += loadm.o
-obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
+obj-$(CONFIG_CMD_MEMINFO) += meminfo.o
obj-$(CONFIG_CMD_MEMORY) += mem_copy.o
+obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
ifdef CONFIG_CMD_PCI
obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o
endif
-obj-$(CONFIG_CMD_PINMUX) += pinmux.o
-obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_SEAMA) += seama.o
ifdef CONFIG_SANDBOX
obj-$(CONFIG_CMD_MBR) += mbr.o
+obj-$(CONFIG_CMD_PINMUX) += pinmux.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
+ifdef CONFIG_NET
obj-$(CONFIG_CMD_WGET) += wget.o
+endif
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
-obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
diff --git a/test/cmd/coreboot.c b/test/cmd/coreboot.c
new file mode 100644
index 0000000..a99898d
--- /dev/null
+++ b/test/cmd/coreboot.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for coreboot commands
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <cedit.h>
+#include <command.h>
+#include <dm.h>
+#include <expo.h>
+#include <rtc.h>
+#include <test/cedit-test.h>
+#include <test/cmd.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include "../../boot/scene_internal.h"
+
+enum {
+ CSUM_LOC = 0x3f0 / 8,
+};
+
+/**
+ * test_cmd_cbsysinfo() - test the cbsysinfo command produces expected output
+ *
+ * This includes ensuring that the coreboot build has the expected options
+ * enabled
+ */
+static int test_cmd_cbsysinfo(struct unit_test_state *uts)
+{
+ ut_assertok(run_command("cbsysinfo", 0));
+ ut_assert_nextlinen("Coreboot table at");
+
+ /* Make sure CMOS options are enabled */
+ ut_assert_skip_to_line(
+ " 1c0 1 e 1 power_on_after_fail 0:Disable 1:Enable");
+ ut_assert_skip_to_line("CMOS start : 1c0");
+ ut_assert_nextline(" CMOS end : 1cf");
+ ut_assert_nextline(" CMOS csum loc: 3f0");
+
+ /* Make sure the linear frame buffer is enabled */
+ ut_assert_skip_to_linen("Framebuffer");
+ ut_assert_nextlinen(" Phys addr");
+
+ ut_assert_skip_to_line("Chrome OS VPD: 00000000");
+ ut_assert_nextlinen("RSDP");
+ ut_assert_nextlinen("Unimpl.");
+ ut_assert_console_end();
+
+ return 0;
+}
+CMD_TEST(test_cmd_cbsysinfo, UTF_CONSOLE);
+
+/* test cbcmos command */
+static int test_cmd_cbcmos(struct unit_test_state *uts)
+{
+ u16 old_csum, new_csum;
+ struct udevice *dev;
+
+ /* initially the checksum should be correct */
+ ut_assertok(run_command("cbcmos check", 0));
+ ut_assert_console_end();
+
+ /* make a change to the checksum */
+ ut_assertok(uclass_first_device_err(UCLASS_RTC, &dev));
+ ut_assertok(rtc_read16(dev, CSUM_LOC, &old_csum));
+ ut_assertok(rtc_write16(dev, CSUM_LOC, old_csum + 1));
+
+ /* now the command should fail */
+ ut_asserteq(1, run_command("cbcmos check", 0));
+ ut_assert_nextline("Checksum %04x error: calculated %04x",
+ old_csum + 1, old_csum);
+ ut_assert_console_end();
+
+ /* now get it to fix the checksum */
+ ut_assertok(run_command("cbcmos update", 0));
+ ut_assert_nextline("Checksum %04x written", old_csum);
+ ut_assert_console_end();
+
+ /* check the RTC looks right */
+ ut_assertok(rtc_read16(dev, CSUM_LOC, &new_csum));
+ ut_asserteq(old_csum, new_csum);
+ ut_assert_console_end();
+
+ return 0;
+}
+CMD_TEST(test_cmd_cbcmos, UTF_CONSOLE);
+
+/* test 'cedit cb_load' command */
+static int test_cmd_cedit_cb_load(struct unit_test_state *uts)
+{
+ struct scene_obj_menu *menu;
+ struct video_priv *vid_priv;
+ struct scene_obj_txt *txt;
+ struct scene *scn;
+ struct expo *exp;
+ int scn_id;
+
+ ut_assertok(run_command("cedit cb_load", 0));
+ ut_assertok(run_command("cedit read_cmos", 0));
+ ut_assert_console_end();
+
+ exp = cur_exp;
+ scn_id = cedit_prepare(exp, &vid_priv, &scn);
+ ut_assert(scn_id > 0);
+ ut_assertnonnull(scn);
+
+ /* just do a very basic test that the first menu is present */
+ menu = scene_obj_find(scn, scn->highlight_id, SCENEOBJT_NONE);
+ ut_assertnonnull(menu);
+
+ txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE);
+ ut_assertnonnull(txt);
+ ut_asserteq_str("Boot option", expo_get_str(exp, txt->str_id));
+
+ return 0;
+}
+CMD_TEST(test_cmd_cedit_cb_load, UTF_CONSOLE);
diff --git a/test/cmd/cpuid.c b/test/cmd/cpuid.c
new file mode 100644
index 0000000..e07f5fd
--- /dev/null
+++ b/test/cmd/cpuid.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for cpuid command
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <test/cmd.h>
+#include <test/ut.h>
+
+static int cmd_test_cpuid(struct unit_test_state *uts)
+{
+ ut_assertok(run_commandf("cpuid 1"));
+ ut_assert_nextline("eax 00060fb1");
+ ut_assert_nextline("ebx 00000800");
+ ut_assert_nextline("ecx 80002001");
+ ut_assert_nextline("edx 078bfbfd");
+
+ return 0;
+}
+CMD_TEST(cmd_test_cpuid, UTF_CONSOLE);
diff --git a/test/cmd/font.c b/test/cmd/font.c
index 25d365d..3335dd6 100644
--- a/test/cmd/font.c
+++ b/test/cmd/font.c
@@ -27,14 +27,20 @@
ut_assertok(uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev));
ut_assertok(run_command("font list", 0));
- ut_assert_nextline("nimbus_sans_l_regular");
+ if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_NIMBUS))
+ ut_assert_nextline("nimbus_sans_l_regular");
+ if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_ANKACODER))
+ ut_assert_nextline("ankacoder_c75_r");
if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
ut_assert_nextline("cantoraone_regular");
ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
- ut_asserteq_str("nimbus_sans_l_regular", name);
- ut_asserteq(18, size);
+ if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_ANKACODER))
+ ut_asserteq_str("ankacoder_c75_r", name);
+ else
+ ut_asserteq_str("nimbus_sans_l_regular", name);
+ ut_asserteq(CONFIG_CONSOLE_TRUETYPE_SIZE, size);
if (!IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
return 0;
@@ -58,10 +64,19 @@
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
ut_asserteq(40, size);
+ ut_assertok(ut_check_console_end(uts));
+
+ ut_assertok(run_command("font size", 0));
+ ut_assert_nextline("40");
+ ut_assertok(ut_check_console_end(uts));
ut_assertok(run_command("font size 30", 0));
ut_assert_console_end();
+ ut_assertok(run_command("font size", 0));
+ ut_assert_nextline("30");
+ ut_assertok(ut_check_console_end(uts));
+
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
ut_asserteq(30, size);
diff --git a/test/cmd/mem_copy.c b/test/cmd/mem_copy.c
index 1ba0ceb..67eca32 100644
--- a/test/cmd/mem_copy.c
+++ b/test/cmd/mem_copy.c
@@ -21,7 +21,7 @@
static int do_test(struct unit_test_state *uts,
const char *suffix, int d, int s, int count)
{
- const long addr = 0x1000;
+ const long addr = CONFIG_SYS_LOAD_ADDR + 0x1000;
u8 shadow[BUF_SIZE];
u8 *buf;
int i, w, bytes;
diff --git a/test/cmd/meminfo.c b/test/cmd/meminfo.c
new file mode 100644
index 0000000..53b41e3
--- /dev/null
+++ b/test/cmd/meminfo.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for 'meminfo' command
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <dm/test.h>
+#include <test/cmd.h>
+#include <test/ut.h>
+
+/* Test 'meminfo' command */
+static int cmd_test_meminfo(struct unit_test_state *uts)
+{
+ ut_assertok(run_command("meminfo", 0));
+ ut_assert_nextline("DRAM: 256 MiB");
+ ut_assert_nextline_empty();
+
+ ut_assert_nextline("Region Base Size End Gap");
+ ut_assert_nextlinen("-");
+
+ /* For now we don't worry about checking the values */
+ ut_assert_nextlinen("video");
+ ut_assert_nextlinen("code");
+ ut_assert_nextlinen("malloc");
+ ut_assert_nextlinen("board_info");
+ ut_assert_nextlinen("global_data");
+ ut_assert_nextlinen("devicetree");
+ ut_assert_nextlinen("bootstage");
+ ut_assert_nextlinen("bloblist");
+ ut_assert_nextlinen("stack");
+
+ /* we expect at least one lmb line, but don't know how many */
+ ut_assert_nextlinen("lmb");
+ ut_assert_skip_to_linen("free");
+
+ ut_assert_console_end();
+
+ return 0;
+}
+CMD_TEST(cmd_test_meminfo, UTF_CONSOLE);
diff --git a/test/cmd/msr.c b/test/cmd/msr.c
new file mode 100644
index 0000000..e9a152e
--- /dev/null
+++ b/test/cmd/msr.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for msr command
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <test/cmd.h>
+#include <test/ut.h>
+
+static int cmd_test_msr(struct unit_test_state *uts)
+{
+ ut_assertok(run_commandf("msr read 200"));
+ ut_assert_nextline("00000000 ffe00006");
+ ut_assert_console_end();
+
+ /* change the first variable msr and see it reflected in the mtrr cmd */
+ ut_assertok(run_commandf("mtrr"));
+ ut_assert_nextline("CPU 65537:");
+ ut_assert_nextlinen("Reg");
+ ut_assert_nextlinen("0 Y Back 00000000ffe00000");
+ ut_assertok(console_record_reset_enable());
+
+ /* change the type from 6 to 5 */
+ ut_assertok(run_commandf("msr write 200 0 ffe00005"));
+ ut_assert_console_end();
+
+ /* Now it shows 'Protect' */
+ ut_assertok(run_commandf("mtrr"));
+ ut_assert_nextline("CPU 65537:");
+ ut_assert_nextlinen("Reg");
+ ut_assert_nextlinen("0 Y Protect 00000000ffe00000");
+ ut_assertok(console_record_reset_enable());
+
+ return 0;
+}
+CMD_TEST(cmd_test_msr, UTF_CONSOLE);
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 6c9ebb8..bcb52ef 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -48,7 +48,9 @@
obj-$(CONFIG_DM_DSA) += dsa.o
obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
+ifdef CONFIG_NET
obj-$(CONFIG_DM_ETH) += eth.o
+endif
obj-$(CONFIG_EXTCON) += extcon.o
ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 7ccd7f8..39a26bb 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -95,6 +95,21 @@
return acpi_copy_name(out_name, ACPI_TEST_DEV_NAME);
}
+static int testacpi_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ u64 *data = ctx->current;
+
+ /* Only fill madt once */
+ if (device_get_uclass_id(dev->parent) != UCLASS_TEST_ACPI)
+ return 0;
+
+ *data = 0xdeadbeef;
+
+ acpi_inc(ctx, sizeof(u64));
+
+ return 0;
+}
+
static int testacpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
{
const char *data;
@@ -124,6 +139,7 @@
struct acpi_ops testacpi_ops = {
.get_name = testacpi_get_name,
.write_tables = testacpi_write_tables,
+ .fill_madt = testacpi_fill_madt,
.fill_ssdt = testacpi_fill_ssdt,
.inject_dsdt = testacpi_inject_dsdt,
};
@@ -527,6 +543,33 @@
}
DM_TEST(dm_test_acpi_fill_ssdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+/* Test acpi_fill_madt() */
+static int dm_test_acpi_fill_madt(struct unit_test_state *uts)
+{
+ struct acpi_ctx ctx;
+ u64 *buf;
+
+ buf = malloc(BUF_SIZE);
+ ut_assertnonnull(buf);
+
+ acpi_reset_items();
+ ctx.current = buf;
+ buf[1] = 'z'; /* sentinel */
+ ut_assertok(acpi_fill_madt_subtbl(&ctx));
+
+ /*
+ * These values come from acpi-test2's acpi-ssdt-test-data property.
+ * This device comes first because of u-boot,acpi-ssdt-order
+ */
+ ut_asserteq(0xdeadbeef, buf[0]);
+
+ ut_asserteq('z', buf[1]);
+
+ return 0;
+}
+
+DM_TEST(dm_test_acpi_fill_madt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
/* Test acpi_inject_dsdt() */
static int dm_test_acpi_inject_dsdt(struct unit_test_state *uts)
{
diff --git a/test/dm/core.c b/test/dm/core.c
index e0c5b9e..7371d3f 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -1351,3 +1351,25 @@
return 0;
}
DM_TEST(dm_test_dev_get_mem, UTF_SCAN_FDT);
+
+/* Test uclass_try_first_device() */
+static int dm_test_try_first_device(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ /* Check that it doesn't create a device or uclass */
+ ut_assertnull(uclass_find(UCLASS_TEST));
+ ut_assertnull(uclass_try_first_device(UCLASS_TEST));
+ ut_assertnull(uclass_try_first_device(UCLASS_TEST));
+ ut_assertnull(uclass_find(UCLASS_TEST));
+
+ /* Create a test device */
+ ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual,
+ &dev));
+ dev = uclass_try_first_device(UCLASS_TEST);
+ ut_assertnonnull(dev);
+ ut_asserteq(UCLASS_TEST, device_get_uclass_id(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_try_first_device, 0);
diff --git a/test/dm/irq.c b/test/dm/irq.c
index 836f2d8..ca3e188 100644
--- a/test/dm/irq.c
+++ b/test/dm/irq.c
@@ -76,6 +76,21 @@
}
DM_TEST(dm_test_request, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+/* Test of irq_get_by_index() */
+static int dm_test_irq_get_by_index(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct irq irq;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_TEST_FDT, "f-test",
+ &dev));
+ ut_assertok(irq_get_by_index(dev, 0, &irq));
+ ut_asserteq(4, irq.id);
+
+ return 0;
+}
+DM_TEST(dm_test_irq_get_by_index, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
/* Test of irq_get_acpi() */
static int dm_test_irq_get_acpi(struct unit_test_state *uts)
{
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 541bcba..bef2959 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -3,7 +3,6 @@
* Copyright 2017 Google, Inc
*/
-#include <cyclic.h>
#include <dm.h>
#include <time.h>
#include <wdt.h>
@@ -14,6 +13,7 @@
#include <test/test.h>
#include <test/ut.h>
#include <linux/delay.h>
+#include <u-boot/schedule.h>
#include <watchdog.h>
/* Test that watchdog driver functions are called */
@@ -71,7 +71,7 @@
ut_assertok(wdt_reset(wdt));
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
- ut_asserteq(-ENOSYS, wdt_stop(wdt));
+ ut_asserteq(-EOPNOTSUPP, wdt_stop(wdt));
return 0;
}
@@ -103,7 +103,7 @@
ut_assertok(wdt_reset(wdt));
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
- ut_asserteq(-ENOSYS, wdt_stop(wdt));
+ ut_asserteq(-EOPNOTSUPP, wdt_stop(wdt));
return 0;
}
@@ -131,7 +131,7 @@
/* Neither device should be "started", so watchdog_reset() should be a no-op. */
reset_count = state->wdt.reset_count;
val = sandbox_gpio_get_value(gpio, offset);
- cyclic_run();
+ schedule();
ut_asserteq(reset_count, state->wdt.reset_count);
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
@@ -141,19 +141,19 @@
/* Make sure both devices have just been pinged. */
timer_test_add_offset(100);
- cyclic_run();
+ schedule();
reset_count = state->wdt.reset_count;
val = sandbox_gpio_get_value(gpio, offset);
/* The gpio watchdog should be pinged, the sandbox one not. */
timer_test_add_offset(30);
- cyclic_run();
+ schedule();
ut_asserteq(reset_count, state->wdt.reset_count);
ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset));
/* After another ~30ms, both devices should get pinged. */
timer_test_add_offset(30);
- cyclic_run();
+ schedule();
ut_asserteq(reset_count + 1, state->wdt.reset_count);
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
diff --git a/test/hush/Makefile b/test/hush/Makefile
index a2d9881..4c3a0be 100644
--- a/test/hush/Makefile
+++ b/test/hush/Makefile
@@ -5,6 +5,8 @@
obj-y += cmd_ut_hush.o
obj-y += if.o
+ifdef CONFIG_CONSOLE_RECORD
obj-y += dollar.o
+endif
obj-y += list.o
obj-y += loop.o
diff --git a/test/lib/alist.c b/test/lib/alist.c
index d41845c..0bf2457 100644
--- a/test/lib/alist.c
+++ b/test/lib/alist.c
@@ -240,3 +240,256 @@
return 0;
}
LIB_TEST(lib_test_alist_add, 0);
+
+/* Test alist_next() */
+static int lib_test_alist_next(struct unit_test_state *uts)
+{
+ const struct my_struct *ptr;
+ struct my_struct data, *ptr2;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ data.val = 123;
+ data.other_val = 0;
+ alist_add(&lst, data);
+
+ data.val = 321;
+ alist_add(&lst, data);
+
+ data.val = 789;
+ alist_add(&lst, data);
+
+ ptr = alist_get(&lst, 0, struct my_struct);
+ ut_assertnonnull(ptr);
+ ut_asserteq(123, ptr->val);
+
+ ptr = alist_next(&lst, ptr);
+ ut_assertnonnull(ptr);
+ ut_asserteq(321, ptr->val);
+
+ ptr2 = (struct my_struct *)ptr;
+ ptr2 = alist_nextw(&lst, ptr2);
+ ut_assertnonnull(ptr2);
+
+ ptr = alist_next(&lst, ptr);
+ ut_assertnonnull(ptr);
+ ut_asserteq(789, ptr->val);
+ ut_asserteq_ptr(ptr, ptr2);
+ ptr2->val = 89;
+ ut_asserteq(89, ptr->val);
+
+ ptr = alist_next(&lst, ptr);
+ ut_assertnull(ptr);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_next, 0);
+
+/* Test alist_for_each() */
+static int lib_test_alist_for_each(struct unit_test_state *uts)
+{
+ const struct my_struct *ptr;
+ struct my_struct data, *ptr2;
+ struct alist lst;
+ ulong start;
+ int sum;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq_ptr(NULL, alist_end(&lst, struct my_struct));
+
+ sum = 0;
+ alist_for_each(ptr, &lst)
+ sum++;
+ ut_asserteq(0, sum);
+
+ alist_for_each(ptr, &lst)
+ sum++;
+ ut_asserteq(0, sum);
+
+ /* add three items */
+ data.val = 1;
+ data.other_val = 0;
+ alist_add(&lst, data);
+
+ ptr = lst.data;
+ ut_asserteq_ptr(ptr + 1, alist_end(&lst, struct my_struct));
+
+ data.val = 2;
+ alist_add(&lst, data);
+ ut_asserteq_ptr(ptr + 2, alist_end(&lst, struct my_struct));
+
+ data.val = 3;
+ alist_add(&lst, data);
+ ut_asserteq_ptr(ptr + 3, alist_end(&lst, struct my_struct));
+
+ /* check alist_chk_ptr() */
+ ut_asserteq(true, alist_chk_ptr(&lst, ptr + 2));
+ ut_asserteq(false, alist_chk_ptr(&lst, ptr + 3));
+ ut_asserteq(false, alist_chk_ptr(&lst, ptr + 4));
+ ut_asserteq(true, alist_chk_ptr(&lst, ptr));
+ ut_asserteq(false, alist_chk_ptr(&lst, ptr - 1));
+
+ /* sum all items */
+ sum = 0;
+ alist_for_each(ptr, &lst)
+ sum += ptr->val;
+ ut_asserteq(6, sum);
+
+ /* increment all items */
+ alist_for_each(ptr2, &lst)
+ ptr2->val += 1;
+
+ /* sum all items again */
+ sum = 0;
+ alist_for_each(ptr, &lst)
+ sum += ptr->val;
+ ut_asserteq(9, sum);
+
+ ptr = lst.data;
+ ut_asserteq_ptr(ptr + 3, alist_end(&lst, struct my_struct));
+
+ /* empty the list and try again */
+ alist_empty(&lst);
+ ut_asserteq_ptr(ptr, alist_end(&lst, struct my_struct));
+ ut_assertnull(alist_get(&lst, 0, struct my_struct));
+
+ sum = 0;
+ alist_for_each(ptr, &lst)
+ sum += ptr->val;
+ ut_asserteq(0, sum);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_for_each, 0);
+
+/* Test alist_empty() */
+static int lib_test_alist_empty(struct unit_test_state *uts)
+{
+ struct my_struct data;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq(0, lst.count);
+ data.val = 1;
+ data.other_val = 0;
+ alist_add(&lst, data);
+ ut_asserteq(1, lst.count);
+ ut_asserteq(4, lst.alloc);
+
+ alist_empty(&lst);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(4, lst.alloc);
+ ut_assertnonnull(lst.data);
+ ut_asserteq(sizeof(data), lst.obj_size);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_empty, 0);
+
+static int lib_test_alist_filter(struct unit_test_state *uts)
+{
+ struct my_struct *from, *to, *ptr;
+ struct my_struct data;
+ struct alist lst;
+ ulong start;
+ int count;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ data.val = 1;
+ data.other_val = 0;
+ alist_add(&lst, data);
+
+ data.val = 2;
+ alist_add(&lst, data);
+
+ data.val = 3;
+ alist_add(&lst, data);
+ ptr = lst.data;
+
+ /* filter out all values except 2 */
+ alist_for_each_filter(from, to, &lst) {
+ if (from->val != 2)
+ *to++ = *from;
+ }
+ alist_update_end(&lst, to);
+
+ ut_asserteq(2, lst.count);
+ ut_assertnonnull(lst.data);
+
+ ut_asserteq(1, alist_get(&lst, 0, struct my_struct)->val);
+ ut_asserteq(3, alist_get(&lst, 1, struct my_struct)->val);
+ ut_asserteq_ptr(ptr + 3, from);
+ ut_asserteq_ptr(ptr + 2, to);
+
+ /* filter out nothing */
+ alist_for_each_filter(from, to, &lst) {
+ if (from->val != 2)
+ *to++ = *from;
+ }
+ alist_update_end(&lst, to);
+ ut_asserteq_ptr(ptr + 2, from);
+ ut_asserteq_ptr(ptr + 2, to);
+
+ ut_asserteq(2, lst.count);
+ ut_assertnonnull(lst.data);
+
+ ut_asserteq(1, alist_get(&lst, 0, struct my_struct)->val);
+ ut_asserteq(3, alist_get(&lst, 1, struct my_struct)->val);
+
+ /* filter out everything */
+ alist_for_each_filter(from, to, &lst) {
+ if (from->val == 2)
+ *to++ = *from;
+ }
+ alist_update_end(&lst, to);
+ ut_asserteq_ptr(ptr + 2, from);
+ ut_asserteq_ptr(ptr, to);
+
+ /* filter out everything (nop) */
+ count = 0;
+ alist_for_each_filter(from, to, &lst) {
+ if (from->val == 2)
+ *to++ = *from;
+ count++;
+ }
+ alist_update_end(&lst, to);
+ ut_asserteq_ptr(ptr, from);
+ ut_asserteq_ptr(ptr, to);
+ ut_asserteq(0, count);
+
+ ut_asserteq(0, lst.count);
+ ut_assertnonnull(lst.data);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_filter, 0);
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index b2c54fb..c917115 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -473,7 +473,7 @@
/* allocate overlapping region should return the coalesced count */
ret = lmb_reserve(0x40011000, 0x10000);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000,
0, 0, 0, 0);
/* allocate 3nd region */
@@ -748,13 +748,13 @@
/* merge after */
ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000,
0, 0, 0, 0);
/* merge before */
ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000,
0, 0, 0, 0);
@@ -770,7 +770,7 @@
/* test that old API use LMB_NONE */
ret = lmb_reserve(0x40040000, 0x10000);
- ut_asserteq(ret, 1);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000,
0x40030000, 0x20000, 0, 0);
@@ -789,7 +789,7 @@
/* merge with 2 adjacent regions */
ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 2);
+ ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000,
0x40030000, 0x20000, 0x40050000, 0x30000);
diff --git a/test/py/tests/test_android/test_ab.py b/test/py/tests/test_android/test_ab.py
index c79cb07..9bf1a0e 100644
--- a/test/py/tests/test_android/test_ab.py
+++ b/test/py/tests/test_android/test_ab.py
@@ -54,22 +54,45 @@
di = ABTestDiskImage(u_boot_console)
return di
+def ab_dump(u_boot_console, slot_num, crc):
+ output = u_boot_console.run_command('bcb ab_dump host 0#misc')
+ header, slot0, slot1 = output.split('\r\r\n\r\r\n')
+ slots = [slot0, slot1]
+ slot_suffixes = ['_a', '_b']
+
+ header = dict(map(lambda x: map(str.strip, x.split(':')), header.split('\r\r\n')))
+ assert header['Bootloader Control'] == '[misc]'
+ assert header['Active Slot'] == slot_suffixes[slot_num]
+ assert header['Magic Number'] == '0x42414342'
+ assert header['Version'] == '1'
+ assert header['Number of Slots'] == '2'
+ assert header['Recovery Tries Remaining'] == '0'
+ assert header['CRC'] == '{} (Valid)'.format(crc)
+
+ slot = dict(map(lambda x: map(str.strip, x.split(':')), slots[slot_num].split('\r\r\n\t- ')[1:]))
+ assert slot['Priority'] == '15'
+ assert slot['Tries Remaining'] == '6'
+ assert slot['Successful Boot'] == '0'
+ assert slot['Verity Corrupted'] == '0'
+
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('android_ab')
-@pytest.mark.buildconfigspec('cmd_ab_select')
+@pytest.mark.buildconfigspec('cmd_bcb')
@pytest.mark.requiredtool('sgdisk')
def test_ab(ab_disk_image, u_boot_console):
- """Test the 'ab_select' command."""
+ """Test the 'bcb ab_select' command."""
u_boot_console.run_command('host bind 0 ' + ab_disk_image.path)
- output = u_boot_console.run_command('ab_select slot_name host 0#misc')
+ output = u_boot_console.run_command('bcb ab_select slot_name host 0#misc')
assert 're-initializing A/B metadata' in output
assert 'Attempting slot a, tries remaining 7' in output
output = u_boot_console.run_command('printenv slot_name')
assert 'slot_name=a' in output
+ ab_dump(u_boot_console, 0, '0xd438d1b9')
- output = u_boot_console.run_command('ab_select slot_name host 0:1')
+ output = u_boot_console.run_command('bcb ab_select slot_name host 0:1')
assert 'Attempting slot b, tries remaining 7' in output
output = u_boot_console.run_command('printenv slot_name')
assert 'slot_name=b' in output
+ ab_dump(u_boot_console, 1, '0x011ec016')
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 707b2c9..3343493 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -182,7 +182,7 @@
do_test_efi_helloworld_net(u_boot_console, PROTO_TFTP);
@pytest.mark.buildconfigspec('of_control')
-@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile')
+@pytest.mark.buildconfigspec('bootefi_hello_compile')
@pytest.mark.buildconfigspec('cmd_wget')
def test_efi_helloworld_net_http(u_boot_console):
"""Run the helloworld.efi binary via HTTP.
diff --git a/test/py/tests/test_eficonfig/test_eficonfig.py b/test/py/tests/test_eficonfig/test_eficonfig.py
index 1d8e033..d98de52 100644
--- a/test/py/tests/test_eficonfig/test_eficonfig.py
+++ b/test/py/tests/test_eficonfig/test_eficonfig.py
@@ -117,7 +117,7 @@
press_up_down_enter_and_wait(0, 0, True, 'Quit')
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 1', 'Quit')
@@ -166,7 +166,7 @@
press_up_down_enter_and_wait(0, 0, True, 'Quit')
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 2', 'Quit')
@@ -278,7 +278,7 @@
u_boot_console.p.expect([i])
# Press the enter key to select 'Description:' entry, then enter Description
- press_up_down_enter_and_wait(0, 0, True, 'enter description:')
+ press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
# Send Description user input, press ENTER key to complete
send_user_input_and_wait('test 3', 'Quit')
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 00bcccd..4471db7 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -488,7 +488,7 @@
assert 'Loading Environment from EXT4... OK' in response
response = c.run_command('ext4ls host 0:0')
- assert '8192 uboot.env' in response
+ assert '8192 uboot.env' in response
response = c.run_command('env info')
assert 'env_valid = valid' in response
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index e282c67..45143c1 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -18,6 +18,7 @@
-------------------- ------------------------------ ------------------------------
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.*
+EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.*
EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.*
EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.*
EVT_TEST h_adder_simple .*test/common/event.c:'''
diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py
index 71f3e86..b5f4704 100644
--- a/test/py/tests/test_fs/test_basic.py
+++ b/test/py/tests/test_fs/test_basic.py
@@ -33,10 +33,7 @@
# In addition, test with a nonexistent directory to see if we crash.
output = u_boot_console.run_command(
'%sls host 0:0 invalid_d' % fs_type)
- if fs_type == 'ext4':
- assert('Can not find directory' in output)
- else:
- assert('' == output)
+ assert('' == output)
def test_fs2(self, u_boot_console, fs_obj_basic):
"""
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index 3160d58..caca930 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -693,4 +693,16 @@
u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
)
+ # Read to relocation address
+ output = u_boot_console.run_command('bdinfo')
+ m = re.search('relocaddr\s*= (.+)', output)
+ res_area = int(m.group(1), 16)
+
+ start = 0
+ size = 0x2000
+ error_msg = 'ERROR: trying to overwrite reserved memory'
+ flash_ops(
+ u_boot_console, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
+ )
+
i = i + 1
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index fb3d20f..2397fd3 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -288,6 +288,47 @@
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
+def usb_fatload_fatwrite(u_boot_console, fs, x, part):
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ size = random.randint(4, 1 * 1024 * 1024)
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+
+ file = '%s_%d' % ('uboot_test', size)
+ output = u_boot_console.run_command(
+ '%swrite usb %d:%s %x %s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
+
+ alignment = int(
+ u_boot_console.config.buildconfig.get(
+ 'config_sys_cacheline_size', 128
+ )
+ )
+ offset = random.randrange(alignment, 1024, alignment)
+ output = u_boot_console.run_command(
+ '%sload usb %d:%s %x %s' % (fs, x, part, addr + offset, file)
+ )
+ assert 'Invalid FAT entry' not in output
+ assert 'Unable to read file' not in output
+ assert 'Misaligned buffer address' not in output
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
+
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
+
+ return file, size, expected_crc32
+
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_fat')
@pytest.mark.buildconfigspec('cmd_memory')
@@ -309,49 +350,11 @@
for part in partitions:
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- size = random.randint(4, 1 * 1024 * 1024)
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
-
- file = '%s_%d' % ('uboot_test', size)
- output = u_boot_console.run_command(
- '%swrite usb %d:%s %x %s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
-
- alignment = int(
- u_boot_console.config.buildconfig.get(
- 'config_sys_cacheline_size', 128
- )
- )
- offset = random.randrange(alignment, 1024, alignment)
- output = u_boot_console.run_command(
- '%sload usb %d:%s %x %s' % (fs, x, part, addr + offset, file)
- )
- assert 'Invalid FAT entry' not in output
- assert 'Unable to read file' not in output
- assert 'Misaligned buffer address' not in output
- expected_text = '%d bytes read' % size
- assert expected_text in output
-
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ usb_fatload_fatwrite(u_boot_console, fs, x, part)
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
- return file, size
-
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext4')
def test_usb_ext4ls(u_boot_console):
@@ -380,9 +383,42 @@
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
+def usb_ext4load_ext4write(u_boot_console, fs, x, part):
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ size = random.randint(4, 1 * 1024 * 1024)
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ file = '%s_%d' % ('uboot_test', size)
+
+ output = u_boot_console.run_command(
+ '%swrite usb %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
+
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ '%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
+
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
+
+ return file, size, expected_crc32
+
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext4')
-@pytest.mark.buildconfigspec('ext4_write')
+@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
def test_usb_ext4load_ext4write(u_boot_console):
devices, controllers, storage_device = test_usb_part(u_boot_console)
@@ -402,41 +438,11 @@
for part in partitions:
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- size = random.randint(4, 1 * 1024 * 1024)
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
- file = '%s_%d' % ('uboot_test', size)
-
- output = u_boot_console.run_command(
- '%swrite usb %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
-
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- '%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
-
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ usb_ext4load_ext4write(u_boot_console, fs, x, part)
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
- return file, size
-
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext2')
def test_usb_ext2ls(u_boot_console):
@@ -469,11 +475,10 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext2')
@pytest.mark.buildconfigspec('cmd_ext4')
-@pytest.mark.buildconfigspec('ext4_write')
+@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
def test_usb_ext2load(u_boot_console):
devices, controllers, storage_device = test_usb_part(u_boot_console)
- file, size = test_usb_ext4load_ext4write(u_boot_console)
if not devices:
pytest.skip('No devices detected')
@@ -491,12 +496,9 @@
for part in partitions:
part_detect = 1
+ file, size, expected_crc32 = \
+ usb_ext4load_ext4write(u_boot_console, 'ext4', x, part)
addr = u_boot_utils.find_ram_base(u_boot_console)
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
offset = random.randrange(128, 1024, 128)
output = u_boot_console.run_command(
@@ -543,6 +545,7 @@
pytest.skip('No partition detected')
@pytest.mark.buildconfigspec('cmd_usb')
+@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_fs_generic')
def test_usb_load(u_boot_console):
devices, controllers, storage_device = test_usb_part(u_boot_console)
@@ -565,15 +568,11 @@
addr = u_boot_utils.find_ram_base(u_boot_console)
if fs == 'fat':
- file, size = test_usb_fatload_fatwrite(u_boot_console)
+ file, size, expected_crc32 = \
+ usb_fatload_fatwrite(u_boot_console, fs, x, part)
elif fs == 'ext4':
- file, size = test_usb_ext4load_ext4write(u_boot_console)
-
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
+ file, size, expected_crc32 = \
+ usb_ext4load_ext4write(u_boot_console, fs, x, part)
offset = random.randrange(128, 1024, 128)
output = u_boot_console.run_command(
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 39aa103..9166c8f 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -208,8 +208,6 @@
cons, f'echo here {kernel} {symlink}')
os.symlink(kernel, symlink)
- u_boot_utils.run_and_log(
- cons, f'mkimage -C none -A arm -T script -d {cmd_fname} {scr_fname}')
complete = True
except ValueError as exc:
diff --git a/test/test-main.c b/test/test-main.c
index da5b07c..7a1f74a 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -4,6 +4,8 @@
* Written by Simon Glass <sjg@chromium.org>
*/
+#define LOG_CATEGORY LOGC_TEST
+
#include <blk.h>
#include <console.h>
#include <cyclic.h>
@@ -240,15 +242,22 @@
* ut_list_has_dm_tests() - Check if a list of tests has driver model ones
*
* @tests: List of tests to run
- * @count: Number of tests to ru
+ * @count: Number of tests to run
+ * @prefix: String prefix for the tests. Any tests that have this prefix will be
+ * printed without the prefix, so that it is easier to see the unique part
+ * of the test name. If NULL, no prefix processing is done
+ * @select_name: Name of a single test being run (from the list provided). If
+ * NULL all tests are being run
* Return: true if any of the tests have the UTF_DM flag
*/
-static bool ut_list_has_dm_tests(struct unit_test *tests, int count)
+static bool ut_list_has_dm_tests(struct unit_test *tests, int count,
+ const char *prefix, const char *select_name)
{
struct unit_test *test;
for (test = tests; test < tests + count; test++) {
- if (test->flags & UTF_DM)
+ if (test_matches(prefix, test->name, select_name) &&
+ (test->flags & UTF_DM))
return true;
}
@@ -379,6 +388,12 @@
return -EAGAIN;
}
}
+ if (test->flags & UFT_BLOBLIST) {
+ log_debug("save bloblist %p\n", gd_bloblist());
+ uts->old_bloblist = gd_bloblist();
+ gd_set_bloblist(NULL);
+ }
+
ut_silence_console(uts);
return 0;
@@ -402,6 +417,11 @@
free(uts->of_other);
uts->of_other = NULL;
+ if (test->flags & UFT_BLOBLIST) {
+ gd_set_bloblist(uts->old_bloblist);
+ log_debug("restore bloblist %p\n", gd_bloblist());
+ }
+
blkcache_free();
return 0;
@@ -550,6 +570,9 @@
* @count: Number of tests to run
* @select_name: Name of a single test to run (from the list provided). If NULL
* then all tests are run
+ * @test_insert: String describing a test to run after n other tests run, in the
+ * format n:name where n is the number of tests to run before this one and
+ * name is the name of the test to run
* Return: 0 if all tests passed, -ENOENT if test @select_name was not found,
* -EBADF if any failed
*/
@@ -646,7 +669,7 @@
int ret;
if (!CONFIG_IS_ENABLED(OF_PLATDATA) &&
- ut_list_has_dm_tests(tests, count)) {
+ ut_list_has_dm_tests(tests, count, prefix, select_name)) {
has_dm_tests = true;
/*
* If we have no device tree, or it only has a root node, then
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index f9a3a42..381e556 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -2099,12 +2099,15 @@
-------------
Binman is a critical tool and is designed to be very testable. Entry
-implementations target 100% test coverage. Run 'binman test -T' to check this.
+implementations target 100% test coverage. Run ``binman test -T`` to check this.
To enable Python test coverage on Debian-type distributions (e.g. Ubuntu)::
$ sudo apt-get install python-coverage python3-coverage python-pytest
+You can also check the coverage provided by a single test, e.g.::
+
+ binman test -T testSimple
Exit status
-----------
@@ -2190,6 +2193,11 @@
Use '-P 1' to disable this. It is automatically disabled when code coverage is
being used (-T) since they are incompatible.
+
+Writing tests
+-------------
+
+See :doc:`../binman_tests`.
Debugging tests
---------------
diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool/mkimage.py
index 39a4c8c..78d3301 100644
--- a/tools/binman/btool/mkimage.py
+++ b/tools/binman/btool/mkimage.py
@@ -22,7 +22,7 @@
# pylint: disable=R0913
def run(self, reset_timestamp=False, output_fname=None, external=False,
- pad=None, align=None):
+ pad=None, align=None, priv_keys_dir=None):
"""Run mkimage
Args:
@@ -34,6 +34,7 @@
other things to be easily added later, if required, such as
signatures
align: Bytes to use for alignment of the FIT and its external data
+ priv_keys_dir: Path to directory containing private keys
version: True to get the mkimage version
"""
args = []
@@ -45,6 +46,8 @@
args += ['-B', f'{align:x}']
if reset_timestamp:
args.append('-t')
+ if priv_keys_dir:
+ args += ['-k', f'{priv_keys_dir}']
if output_fname:
args += ['-F', output_fname]
return self.run_cmd(*args)
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 3006c59..e918162 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -864,6 +864,13 @@
fit,fdt-list-dir = "arch/arm/dts
+ fit,sign
+ Enable signing FIT images via mkimage as described in
+ verified-boot.rst. If the property is found, the private keys path is
+ detected among binman include directories and passed to mkimage via
+ -k flag. All the keys required for signing FIT must be available at
+ time of signing and must be located in single include directory.
+
Substitutions
~~~~~~~~~~~~~
diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index 0abe1c7..b5afbda 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py
@@ -9,6 +9,7 @@
import os
import libfdt
+import os
from binman.entry import Entry, EntryArg
from binman.etype.section import Entry_section
@@ -101,6 +102,14 @@
In this case the input directories are ignored and all devicetree
files must be in that directory.
+ fit,sign
+ Enable signing FIT images via mkimage as described in
+ verified-boot.rst. If the property is found, the private keys path
+ is detected among binman include directories and passed to mkimage
+ via -k flag. All the keys required for signing FIT must be
+ available at time of signing and must be located in single include
+ directory.
+
Substitutions
~~~~~~~~~~~~~
@@ -426,6 +435,7 @@
self._remove_props = props.split()
self.mkimage = None
self.fdtgrep = None
+ self._fit_sign = None
def ReadNode(self):
super().ReadNode()
@@ -508,6 +518,45 @@
# are removed from self._entries later.
self._priv_entries = dict(self._entries)
+ def _get_priv_keys_dir(self, data):
+ """Detect private keys path among binman include directories
+
+ Args:
+ data: FIT image in binary format
+
+ Returns:
+ str: Single path containing all private keys found or None
+
+ Raises:
+ ValueError: Filename 'rsa2048.key' not found in input path
+ ValueError: Multiple key paths found
+ """
+ def _find_keys_dir(node):
+ for subnode in node.subnodes:
+ if subnode.name.startswith('signature'):
+ if subnode.props.get('key-name-hint') is None:
+ continue
+ hint = subnode.props['key-name-hint'].value
+ name = tools.get_input_filename(f"{hint}.key")
+ path = os.path.dirname(name)
+ if path not in paths:
+ paths.append(path)
+ else:
+ _find_keys_dir(subnode)
+ return None
+
+ fdt = Fdt.FromData(data)
+ fdt.Scan()
+
+ paths = []
+
+ _find_keys_dir(fdt.GetRoot())
+
+ if len(paths) > 1:
+ self.Raise("multiple key paths found (%s)" % ",".join(paths))
+
+ return paths[0] if len(paths) else None
+
def BuildSectionData(self, required):
"""Build FIT entry contents
@@ -538,6 +587,8 @@
align = self._fit_props.get('fit,align')
if align is not None:
args.update({'align': fdt_util.fdt32_to_cpu(align.value)})
+ if self._fit_props.get('fit,sign') is not None:
+ args.update({'priv_keys_dir': self._get_priv_keys_dir(data)})
if self.mkimage.run(reset_timestamp=True, output_fname=output_fname,
**args) is None:
if not self.GetAllowMissing():
@@ -637,8 +688,8 @@
"""
val = fdt_util.GetStringList(node, 'fit,firmware')
if val is None:
- return None, self._loadables
- valid_entries = list(self._loadables)
+ return None, loadables
+ valid_entries = list(loadables)
for name, entry in self.GetEntries().items():
missing = []
entry.CheckMissing(missing)
@@ -653,7 +704,7 @@
firmware = name
elif name not in result:
result.append(name)
- for name in self._loadables:
+ for name in loadables:
if name != firmware and name not in result:
result.append(name)
return firmware, result
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
index a7d8db4..dd9f226 100644
--- a/tools/binman/etype/nxp_imx8mcst.py
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -165,6 +165,8 @@
args = ['-i', cfg_fname, '-o', output_fname]
if self.cst.run_cmd(*args) is not None:
outdata = tools.read_file(output_fname)
+ # fixme: 0x2000 should be CONFIG_CSF_SIZE
+ outdata += tools.get_bytes(0, 0x2000 - 0x20 - len(outdata))
return data + outdata
else:
# Bintool is missing; just use the input data as the output
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index e3f231e..156567a 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -7804,6 +7804,101 @@
"""Test that binman can produce an iMX8 image"""
self._DoTestFile('339_nxp_imx8.dts')
+ def testFitSignSimple(self):
+ """Test that image with FIT and signature nodes can be signed"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ entry_args = {
+ 'of-list': 'test-fdt1',
+ 'default-dt': 'test-fdt1',
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ data = tools.read_file(self.TestFile("340_rsa2048.key"))
+ self._MakeInputFile("keys/rsa2048.key", data)
+
+ test_subdir = os.path.join(self._indir, TEST_FDT_SUBDIR)
+ keys_subdir = os.path.join(self._indir, "keys")
+ data = self._DoReadFileDtb(
+ '340_fit_signature.dts',
+ entry_args=entry_args,
+ extra_indirs=[test_subdir, keys_subdir])[0]
+
+ dtb = fdt.Fdt.FromData(data)
+ dtb.Scan()
+
+ conf = dtb.GetNode('/configurations/conf-uboot-1')
+ self.assertIsNotNone(conf)
+ signature = conf.FindNode('signature')
+ self.assertIsNotNone(signature)
+ self.assertIsNotNone(signature.props.get('value'))
+
+ images = dtb.GetNode('/images')
+ self.assertIsNotNone(images)
+ for subnode in images.subnodes:
+ signature = subnode.FindNode('signature')
+ self.assertIsNotNone(signature)
+ self.assertIsNotNone(signature.props.get('value'))
+
+ def testFitSignKeyNotFound(self):
+ """Test that missing keys raise an error"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ entry_args = {
+ 'of-list': 'test-fdt1',
+ 'default-dt': 'test-fdt1',
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ test_subdir = os.path.join(self._indir, TEST_FDT_SUBDIR)
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb(
+ '340_fit_signature.dts',
+ entry_args=entry_args,
+ extra_indirs=[test_subdir])[0]
+ self.assertIn(
+ 'Filename \'rsa2048.key\' not found in input path',
+ str(e.exception))
+
+ def testFitSignMultipleKeyPaths(self):
+ """Test that keys found in multiple paths raise an error"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ entry_args = {
+ 'of-list': 'test-fdt1',
+ 'default-dt': 'test-fdt1',
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ data = tools.read_file(self.TestFile("340_rsa2048.key"))
+ self._MakeInputFile("keys1/rsa2048.key", data)
+ data = tools.read_file(self.TestFile("340_rsa2048.key"))
+ self._MakeInputFile("keys2/conf-rsa2048.key", data)
+
+ test_subdir = os.path.join(self._indir, TEST_FDT_SUBDIR)
+ keys_subdir1 = os.path.join(self._indir, "keys1")
+ keys_subdir2 = os.path.join(self._indir, "keys2")
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb(
+ '341_fit_signature.dts',
+ entry_args=entry_args,
+ extra_indirs=[test_subdir, keys_subdir1, keys_subdir2])[0]
+ self.assertIn(
+ 'Node \'/binman/fit\': multiple key paths found',
+ str(e.exception))
+
+ def testFitSignNoSingatureNodes(self):
+ """Test that fit,sign doens't raise error if no signature nodes found"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ entry_args = {
+ 'of-list': 'test-fdt1',
+ 'default-dt': 'test-fdt1',
+ 'atf-bl31-path': 'bl31.elf',
+ }
+ test_subdir = os.path.join(self._indir, TEST_FDT_SUBDIR)
+ self._DoReadFileDtb(
+ '342_fit_signature.dts',
+ entry_args=entry_args,
+ extra_indirs=[test_subdir])[0]
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/main.py b/tools/binman/main.py
index dc817dd..619840e 100755
--- a/tools/binman/main.py
+++ b/tools/binman/main.py
@@ -85,7 +85,7 @@
return (0 if result.wasSuccessful() else 1)
-def RunTestCoverage(toolpath, build_dir):
+def RunTestCoverage(toolpath, build_dir, args):
"""Run the tests and check that we get 100% coverage"""
glob_list = control.GetEntryModules(False)
all_set = set([os.path.splitext(os.path.basename(item))[0]
@@ -97,7 +97,7 @@
test_util.run_test_coverage('tools/binman/binman', None,
['*test*', '*main.py', 'tools/patman/*', 'tools/dtoc/*',
'tools/u_boot_pylib/*'],
- build_dir, all_set, extra_args or None)
+ build_dir, all_set, extra_args or None, args=args)
def RunBinman(args):
"""Main entry point to binman once arguments are parsed
@@ -117,7 +117,7 @@
if args.cmd == 'test':
if args.test_coverage:
- RunTestCoverage(args.toolpath, args.build_dir)
+ RunTestCoverage(args.toolpath, args.build_dir, args.tests)
else:
ret_code = RunTests(args.debug, args.verbosity, args.processes,
args.test_preserve_dirs, args.tests,
diff --git a/tools/binman/test/340_fit_signature.dts b/tools/binman/test/340_fit_signature.dts
new file mode 100644
index 0000000..9dce62e
--- /dev/null
+++ b/tools/binman/test/340_fit_signature.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test desc";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,sign;
+
+ images {
+ u-boot {
+ description = "test u-boot";
+ type = "standalone";
+ arch = "arm64";
+ os = "u-boot";
+ compression = "none";
+ load = <0x00000000>;
+ entry = <0x00000000>;
+
+ u-boot-nodtb {
+ };
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ @atf-SEQ {
+ fit,operation = "split-elf";
+ description = "test tf-a";
+ type = "firmware";
+ arch = "arm64";
+ os = "arm-trusted-firmware";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ atf-bl31 {
+ };
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ @fdt-SEQ {
+ description = "test fdt";
+ type = "flat_dt";
+ compression = "none";
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ };
+
+ configurations {
+ default = "@conf-uboot-DEFAULT-SEQ";
+ @conf-uboot-SEQ {
+ description = "uboot config";
+ fdt = "fdt-SEQ";
+ fit,firmware = "u-boot";
+ fit,loadables;
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ sign-images = "firmware", "loadables", "fdt";
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/340_rsa2048.key b/tools/binman/test/340_rsa2048.key
new file mode 100644
index 0000000..e74b20c
--- /dev/null
+++ b/tools/binman/test/340_rsa2048.key
@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDVUiT2JAF8Ajcx
+3XTB5qdGxuPMVFcXKJH+4L66oSt4YUBGi1bClo80U2azu08BTzk2Jzv6hez/mvzL
+hBvL3WnPwMl5vdOxb1kvUQyKLSw2bkM8VB0X1jGsKsKjzArg/aI8RknfiaSc5jua
+2lqwUFwv2RMF8jvIMN/1GnTLdECeMFVgVFSFkzIocISAHGPoGUOxTf8xK7o0x4RX
+NzB+95RtIqTQ5Az/KPVCOcQR5ETrUBXHF1I0rYjJjHHO4dUxxfDqFabt60EzQ/R2
+oZu58C4y0TrRI98g4hVPBYapildWjaNQm1Exa4ZaSDVl01OXsFW9Dm80PqfW4tTH
+Cm4nuCq5AgMBAAECggEBAIoG5b2SHJfFwzrzpQmVmeTU6i6a3+MvMBAwEZkmkb8J
+hhJfNFsiGjTsRgbDiuI5BbbBejCmmWvmN+3jZCzr7fwsLPEl36TufFF+atO5WOM7
+Qyv07QIwaOGSpXBgpSVhV6kSfdgy8p1G54hSAt4UkSGwnnt5ei8VWMP6Q1oltW3k
+f9DQ/ar4UEVa4jlJU3xqchcUTiKBKSH6pMC/Fqlq8x5JTLmk1Yb6C2UNcgJYez1u
+sHkdCA0FG3rFPrpFoQ1LUjMj1uEYNAxM3jOxE7Uvmk4yo9WpQDY7cRb2+Th9YY8a
+IKQ2s81Yg2TmkGzr8f5nrZz3WbAmQhQgsKbwlo6snjUCgYEA7kBOt0JlU7bJTfOr
+9s51g2VUfIH9lDS2Eh8MY+Bt6Y0Kdw/UK4HR8ZlN/nn0bHuHkc12K8lXEsQpgIEW
+DaqHytZJHqFs2egzKu/IvQYZ2WXEMj47LZQxEDHO9gtjE+5qCW9yJGqxW9BJKPVD
+F4spus4NqC+yD5OHM+6ESUtL/wMCgYEA5TZj6OHmECeh3efrwHqjDcjrqQbOTozU
+KPCNCY3Pv4Cg4xas/L93TE2CY6HJTr6mwEMUM+M4Ujjj15VCmSDQ/YYcGau1jo+f
+XdphOEENrPwoe9ATWIyBpT/wDrEz3L6JbE9dWMYY8vKYESt3qhVqDlbpmnYl8Jm+
+O3r5Cy2NlJMCgYEAyqzsCZuy5QcesnByvm8dqpxdxdkzJYu9wyakfKZj+gUgfO57
+OFOkjFk07yFB27MuPctCFredmfpDr+ygHRoPkG7AHw2Fss2EEaeP5bU18ilPQMqN
+vxVMs5EblVVUgJUVoVcsC2yz2f4S7oPOAk5BPoehOIzydauznWrvIAas7I8CgYBr
+CFHxLoNq6cbZQ3JACERZrIf2/vmZjoOHtoR1gKYRK7R1NmKDB7lihRMtCSBix/4/
+61Lkw+bJ5kzmn4lgzgUpTdWTWy5FquVlQxOA3EfRjlItNsXB5KKpksi7Y53vJ34u
+eIUDbkW6NPQzmFOhtaw3k/gzq5Yd2v0M82iWAqiJRwKBgQCl2+e2cjISK31QhKTC
+puhwQ0/YuC3zlwMXQgB3nPw8b9RlaDTMrRBCIUFIrrX11tHswGWpyVsxW2AvZ3Zm
+jsWpwGkUdpRdXJBhSaisV/PA+x3kYhpibzEI8FrzhU69zNROCb8CTkN4WcdBdq6J
+PUh/jRtKoE79qrlnIlNvFoz2gQ==
+-----END PRIVATE KEY-----
diff --git a/tools/binman/test/341_fit_signature.dts b/tools/binman/test/341_fit_signature.dts
new file mode 100644
index 0000000..77bec8d
--- /dev/null
+++ b/tools/binman/test/341_fit_signature.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test desc";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,sign;
+
+ images {
+ u-boot {
+ description = "test u-boot";
+ type = "standalone";
+ arch = "arm64";
+ os = "u-boot";
+ compression = "none";
+ load = <0x00000000>;
+ entry = <0x00000000>;
+
+ u-boot-nodtb {
+ };
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ @atf-SEQ {
+ fit,operation = "split-elf";
+ description = "test tf-a";
+ type = "firmware";
+ arch = "arm64";
+ os = "arm-trusted-firmware";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ atf-bl31 {
+ };
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ @fdt-SEQ {
+ description = "test fdt";
+ type = "flat_dt";
+ compression = "none";
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "rsa2048";
+ };
+ };
+ };
+
+ configurations {
+ default = "@conf-uboot-DEFAULT-SEQ";
+ @conf-uboot-SEQ {
+ description = "uboot config";
+ fdt = "fdt-SEQ";
+ fit,firmware = "u-boot";
+ fit,loadables;
+
+ hash {
+ algo = "sha256";
+ };
+
+ signature {
+ algo = "sha256,rsa2048";
+ key-name-hint = "conf-rsa2048";
+ sign-images = "firmware", "loadables", "fdt";
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/342_fit_signature.dts b/tools/binman/test/342_fit_signature.dts
new file mode 100644
index 0000000..267105d
--- /dev/null
+++ b/tools/binman/test/342_fit_signature.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ fit {
+ description = "test desc";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,sign;
+
+ images {
+ u-boot {
+ description = "test u-boot";
+ type = "standalone";
+ arch = "arm64";
+ os = "u-boot";
+ compression = "none";
+ load = <0x00000000>;
+ entry = <0x00000000>;
+
+ u-boot-nodtb {
+ };
+ };
+ @atf-SEQ {
+ fit,operation = "split-elf";
+ description = "test tf-a";
+ type = "firmware";
+ arch = "arm64";
+ os = "arm-trusted-firmware";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ atf-bl31 {
+ };
+ };
+ @fdt-SEQ {
+ description = "test fdt";
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "@conf-uboot-DEFAULT-SEQ";
+ @conf-uboot-SEQ {
+ description = "uboot config";
+ fdt = "fdt-SEQ";
+ fit,firmware = "u-boot";
+ fit,loadables;
+ };
+ };
+ };
+ };
+};
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 4090d32..cbf1345 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -34,7 +34,7 @@
# Error in reading or end of file.
# <<
# which indicates that BREAK_ME has an empty default
-RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+RE_NO_DEFAULT = re.compile(br'\((\w+)\) \[] \(NEW\)')
# Symbol types which appear in the bloat feature (-B). Others are silently
# dropped when reading in the 'nm' output
@@ -374,9 +374,9 @@
self._re_function = re.compile('(.*): In function.*')
self._re_files = re.compile('In file included from.*')
- self._re_warning = re.compile('(.*):(\d*):(\d*): warning: .*')
+ self._re_warning = re.compile(r'(.*):(\d*):(\d*): warning: .*')
self._re_dtb_warning = re.compile('(.*): Warning .*')
- self._re_note = re.compile('(.*):(\d*):(\d*): note: this is the location of the previous.*')
+ self._re_note = re.compile(r'(.*):(\d*):(\d*): note: this is the location of the previous.*')
self._re_migration_warning = re.compile(r'^={21} WARNING ={22}\n.*\n=+\n',
re.MULTILINE | re.DOTALL)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index a7d7883..0c8a4fa 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -440,12 +440,12 @@
This converts ${blah} within the string to the value of blah.
This function works recursively.
+ Resolved string
+
Args:
var_dict: Dictionary containing variables and their values
args: String containing make arguments
Returns:
- Resolved string
-
>>> bsettings.setup(None)
>>> tcs = Toolchains()
>>> tcs.Add('fred', False)
@@ -456,7 +456,7 @@
>>> tcs.ResolveReferences(var_dict, 'this=${oblique}_set${first}nd')
'this=OBLIQUE_setfi2ndrstnd'
"""
- re_var = re.compile('(\$\{[-_a-z0-9A-Z]{1,}\})')
+ re_var = re.compile(r'(\$\{[-_a-z0-9A-Z]{1,}\})')
while True:
m = re_var.search(args)
@@ -495,7 +495,7 @@
self._make_flags['target'] = brd.target
arg_str = self.ResolveReferences(self._make_flags,
self._make_flags.get(brd.target, ''))
- args = re.findall("(?:\".*?\"|\S)+", arg_str)
+ args = re.findall(r"(?:\".*?\"|\S)+", arg_str)
i = 0
while i < len(args):
args[i] = args[i].replace('"', '')
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index c401170..967ac89 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -244,12 +244,15 @@
rm -rf /tmp/trace
# Build coreboot
-RUN wget -O - https://coreboot.org/releases/coreboot-4.22.01.tar.xz | tar -C /tmp -xJ && \
- cd /tmp/coreboot-4.22.01 && \
+RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp -xJ && \
+ cd /tmp/coreboot-24.08 && \
make crossgcc-i386 CPUS=$(nproc) && \
make -C payloads/coreinfo olddefconfig && \
make -C payloads/coreinfo && \
make olddefconfig && \
+ echo CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y | tee -a .config && \
+ echo CONFIG_USE_OPTION_TABLE=y | tee -a .config && \
+ make olddefconfig && \
make -j $(nproc) && \
sudo mkdir /opt/coreboot && \
sudo cp build/coreboot.rom build/cbfstool /opt/coreboot/
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 74451ec..425faf3 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -9,6 +9,8 @@
#define _GNU_SOURCE
+#include "fw_env_private.h"
+
#include <compiler.h>
#include <env.h>
#include <errno.h>
@@ -39,7 +41,6 @@
#include <mtd/ubi-user.h>
-#include "fw_env_private.h"
#include "fw_env.h"
struct env_opts default_opts = {
diff --git a/tools/expo.py b/tools/expo.py
index ea80c70..44995f2 100755
--- a/tools/expo.py
+++ b/tools/expo.py
@@ -20,17 +20,22 @@
# Parse:
# SCENE1 = 7,
+# or SCENE1 = EXPOID_BASE_ID,
# or SCENE2,
-RE_ENUM = re.compile(r'(\S*)(\s*= (\d))?,')
+RE_ENUM = re.compile(r'(\S*)(\s*= ([0-9A-Z_]+))?,')
# Parse #define <name> "string"
RE_DEF = re.compile(r'#define (\S*)\s*"(.*)"')
-def calc_ids(fname):
+# Parse EXPOID_BASE_ID = 5,
+RE_BASE_ID = re.compile(r'\s*EXPOID_BASE_ID\s*= (\d+),')
+
+def calc_ids(fname, base_id):
"""Figure out the value of the enums in a C file
Args:
fname (str): Filename to parse
+ base_id (int): Base ID (value of EXPOID_BASE_ID)
Returns:
OrderedDict():
@@ -55,8 +60,12 @@
if not line or line.startswith('/*'):
continue
m_enum = RE_ENUM.match(line)
- if m_enum.group(3):
- cur_id = int(m_enum.group(3))
+ enum_name = m_enum.group(3)
+ if enum_name:
+ if enum_name == 'EXPOID_BASE_ID':
+ cur_id = base_id
+ else:
+ cur_id = int(enum_name)
vals[m_enum.group(1)] = cur_id
cur_id += 1
else:
@@ -66,11 +75,25 @@
return vals
+
+def find_base_id():
+ fname = 'include/expo.h'
+ base_id = None
+ with open(fname, 'r', encoding='utf-8') as inf:
+ for line in inf.readlines():
+ m_base_id = RE_BASE_ID.match(line)
+ if m_base_id:
+ base_id = int(m_base_id.group(1))
+ if base_id is None:
+ raise ValueError('EXPOID_BASE_ID not found in expo.h')
+ #print(f'EXPOID_BASE_ID={base_id}')
+ return base_id
def run_expo(args):
"""Run the expo program"""
+ base_id = find_base_id()
fname = args.enum_fname or args.layout
- ids = calc_ids(fname)
+ ids = calc_ids(fname, base_id)
if not ids:
print(f"Warning: No enum ID values found in file '{fname}'")
diff --git a/tools/image-host.c b/tools/image-host.c
index 49ce743..5e01b85 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -1333,7 +1333,7 @@
if (ret) {
fprintf(stderr, "Can't add verification data for node '%s' (%s)\n",
fdt_get_name(fit, noffset, NULL),
- fdt_strerror(ret));
+ strerror(-ret));
return ret;
}
}
diff --git a/tools/image-sig-host.c b/tools/image-sig-host.c
index 21b4fa5..5285263 100644
--- a/tools/image-sig-host.c
+++ b/tools/image-sig-host.c
@@ -77,6 +77,13 @@
.verify = ecdsa_verify,
},
{
+ .name = "ecdsa384",
+ .key_len = ECDSA384_BYTES,
+ .sign = ecdsa_sign,
+ .add_verify_data = ecdsa_add_verify_data,
+ .verify = ecdsa_verify,
+ },
+ {
.name = "secp521r1",
.key_len = ECDSA521_BYTES,
.sign = ecdsa_sign,
diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py
index 857ce58..dd67196 100644
--- a/tools/u_boot_pylib/test_util.py
+++ b/tools/u_boot_pylib/test_util.py
@@ -23,8 +23,9 @@
use_concurrent = False
-def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None,
- extra_args=None, single_thread='-P1'):
+def run_test_coverage(prog, filter_fname, exclude_list, build_dir,
+ required=None, extra_args=None, single_thread='-P1',
+ args=None):
"""Run tests and check that we get 100% coverage
Args:
@@ -42,6 +43,7 @@
single_thread (str): Argument string to make the tests run
single-threaded. This is necessary to get proper coverage results.
The default is '-P0'
+ args (list of str): List of tests to run, or None to run all
Raises:
ValueError if the code coverage is not 100%
@@ -66,9 +68,10 @@
'coverage')
cmd = ('%s%s run '
- '--omit "%s" %s %s %s %s' % (prefix, covtool, ','.join(glob_list),
- prog, extra_args or '', test_cmd,
- single_thread or '-P1'))
+ '--omit "%s" %s %s %s %s %s' % (prefix, covtool, ','.join(glob_list),
+ prog, extra_args or '', test_cmd,
+ single_thread or '-P1',
+ ' '.join(args) if args else ''))
os.system(cmd)
stdout = command.output(covtool, 'report')
lines = stdout.splitlines()