Merge branch 'master' of git://git.denx.de/u-boot-sh
- Limit bootloader size to 1 MiB on R-Car Gen3
diff --git a/MAINTAINERS b/MAINTAINERS
index 1842569..37ff21a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -345,6 +345,7 @@
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
F: arch/arm/mach-stm32mp/
+F: doc/board/st/
F: drivers/adc/stm32-adc*
F: drivers/clk/clk_stm32mp1.c
F: drivers/gpio/stm32_gpio.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index be4cf02..9c593b2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -333,6 +333,7 @@
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
+ socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts
new file mode 100644
index 0000000..dadf766
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5_secu1.dts
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2020 ABB
+ */
+
+#include "socfpga_arria5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ABB SoC SECU1 Board";
+ compatible = "altr,socfpga-secu1", "altr,socfpga";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x20000000>; /* 512MB */
+ };
+
+ aliases {
+ /*
+ * this allow the ethaddr uboot environment variable contents
+ * to be added to the gmac0 device tree blob.
+ */
+ ethernet0 = &gmac0;
+ spi0 = &spi1;
+ };
+
+ i2c_gpio: i2c@0 {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&portc 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* SDA */
+ &portc 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* SCL */
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ i2c-gpio,deblock;
+
+ temp_sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "at,24c08";
+ reg = <0x50>;
+ };
+
+ rtc: rtc@68 {
+ compatible = "st,m41st87";
+ reg = <0x68>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 42 0x4>;
+ };
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+ bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
+
+&nand0 {
+ status = "okay";
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts
index 744b36e..7968d52 100644
--- a/arch/arm/dts/uniphier-ld11-global.dts
+++ b/arch/arm/dts/uniphier-ld11-global.dts
@@ -132,7 +132,7 @@
};
eeprom@50 {
- compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 337a353..e0737ac 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -433,7 +433,7 @@
};
};
- emmc: sdhc@5a000000 {
+ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
@@ -566,7 +566,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-ld11-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -621,7 +621,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -631,7 +631,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 3721110..59e4191 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -559,7 +559,7 @@
};
};
- emmc: sdhc@5a000000 {
+ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
@@ -578,7 +578,7 @@
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
@@ -664,7 +664,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-ld20-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -944,7 +944,7 @@
socionext,syscon = <&soc_glue>;
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -954,7 +954,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index c2706ce..1eebc7f 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -245,7 +245,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -265,7 +265,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -375,7 +375,7 @@
interrupt-controller;
};
- aidet: aidet@61830000 {
+ aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-ld4-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
@@ -398,7 +398,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -408,7 +408,8 @@
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
index ce8ea7b..92cc48d 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -50,10 +50,9 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
- u-boot,i2c-offset-len = <2>;
};
};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
index 686dd3a..3b68a7c 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -45,10 +45,9 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
- u-boot,i2c-offset-len = <2>;
};
};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index d090fc7..d006b45 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -279,7 +279,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -299,7 +299,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -317,7 +317,7 @@
non-removable;
};
- sd1: sdhc@5a600000 {
+ sd1: mmc@5a600000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
@@ -426,7 +426,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -626,7 +626,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -636,7 +636,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 9cad79d..ba7e224 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -144,7 +144,7 @@
next-level-cache = <&l3>;
};
- l3: l3-cache@500c8000 {
+ l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
@@ -408,7 +408,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -489,7 +489,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -499,10 +499,11 @@
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
- emmc: sdhc@68400000 {
+ emmc: mmc@68400000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
@@ -518,7 +519,7 @@
non-removable;
};
- sd: sdhc@68800000 {
+ sd: mmc@68800000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
index b13d627..e27fd4f 100644
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -48,10 +48,9 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
- u-boot,i2c-offset-len = <2>;
};
};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 4e11e85..8d968d3 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -446,7 +446,7 @@
};
};
- emmc: sdhc@5a000000 {
+ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
@@ -462,7 +462,7 @@
non-removable;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
@@ -508,7 +508,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -799,7 +799,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -809,7 +809,8 @@
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index b1aff28..ed079c1 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -353,7 +353,7 @@
};
};
- emmc: sdhc@5a000000 {
+ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
@@ -372,7 +372,7 @@
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
@@ -462,7 +462,7 @@
};
};
- aidet: aidet@5fc20000 {
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pxs3-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -821,7 +821,7 @@
socionext,syscon = <&soc_glue>;
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -831,7 +831,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
index 9240a31..a118976 100644
--- a/arch/arm/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -7,9 +7,8 @@
&i2c0 {
eeprom@50 {
- compatible = "microchip,24lc128", "i2c-eeprom";
+ compatible = "microchip,24lc128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
- u-boot,i2c-offset-len = <2>;
};
};
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index efce027..393157e 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -249,7 +249,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -269,7 +269,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -379,7 +379,7 @@
interrupt-controller;
};
- aidet: aidet@61830000 {
+ aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-sld8-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
@@ -402,7 +402,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -412,7 +412,8 @@
pinctrl-0 = <&pinctrl_nand2cs>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 969698c..38d6c1b 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -96,6 +96,11 @@
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
+config TARGET_SOCFPGA_ARRIA5_SECU1
+ bool "ABB SECU1 (Arria V)"
+ select TARGET_SOCFPGA_ARRIA5
+ select VENDOR_KM
+
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -158,6 +163,7 @@
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -173,6 +179,7 @@
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -184,6 +191,7 @@
config SYS_CONFIG_NAME
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -199,4 +207,6 @@
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+source "board/keymile/Kconfig"
+
endif
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 115af24..769778c 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-y += pinctrl-glue.o
obj-$(CONFIG_MMC) += mmc-first-dev.o
+obj-$(CONFIG_NAND_DENALI) += nand-reset.o
obj-y += fdt-fixup.o
endif
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index 99727a3..4f9cd6e 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -141,6 +141,10 @@
support_card_late_init();
+ led_puts("U4");
+
+ uniphier_nand_reset_assert();
+
led_puts("Uboo");
return 0;
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 7932830..378aad0 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -14,25 +14,9 @@
#include <stdio.h>
#include <linux/io.h>
#include <linux/printk.h>
-#include <../drivers/mtd/nand/raw/denali.h>
#include "init.h"
-static void nand_denali_wp_disable(void)
-{
-#ifdef CONFIG_NAND_DENALI
- /*
- * Since the boot rom enables the write protection for NAND boot mode,
- * it must be disabled somewhere for "nand write", "nand erase", etc.
- * The workaround is here to not disturb the Denali NAND controller
- * driver just for a really SoC-specific thing.
- */
- void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-
- writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
-#endif
-}
-
static void uniphier_set_env_fdt_file(void)
{
DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +98,6 @@
case BOOT_DEVICE_NAND:
printf("NAND Boot");
env_set("bootdev", "nand");
- nand_denali_wp_disable();
break;
case BOOT_DEVICE_NOR:
printf("NOR Boot");
diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
index f32f78d..0f9ce65 100644
--- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -15,13 +15,6 @@
{
u32 tmp;
- /* deassert reset */
- if (spl_boot_device() != BOOT_DEVICE_NAND) {
- tmp = readl(sc_base + SC_RSTCTRL);
- tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, sc_base + SC_RSTCTRL);
- };
-
/* provide clocks */
tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 9dc5b88..3c77f48 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -101,6 +101,14 @@
int uniphier_have_internal_stm(void);
int uniphier_boot_from_backend(void);
int uniphier_pin_init(const char *pinconfig_name);
+
+#ifdef CONFIG_NAND_DENALI
+void uniphier_nand_reset_assert(void);
+#else
+static inline void uniphier_nand_reset_assert(void)
+{
+}
+#endif
#ifdef CONFIG_ARM64
void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);
#else
diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c
index 4687901..c71470a 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -1,39 +1,58 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
+ * Copyright (C) 2015-2020 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <common.h>
+#include <dm/of.h>
+#include <fdt_support.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include "micro-support-card.h"
-#define MICRO_SUPPORT_CARD_BASE 0x43f00000
-#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
-#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
-#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
-#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
-#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
+#define SMC911X_OFFSET 0x00000
+#define LED_OFFSET 0x90000
+#define NS16550A_OFFSET 0xb0000
+#define MICRO_SUPPORT_CARD_RESET 0xd0034
+#define MICRO_SUPPORT_CARD_REVISION 0xd00e0
static bool support_card_found;
+static void __iomem *support_card_base;
static void support_card_detect(void)
{
DECLARE_GLOBAL_DATA_PTR;
const void *fdt = gd->fdt_blob;
int offset;
+ u64 addr, addr2;
offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118");
if (offset < 0)
return;
+ addr = fdt_get_base_address(fdt, offset);
+ if (addr == OF_BAD_ADDR)
+ return;
+ addr -= SMC911X_OFFSET;
+
offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a");
if (offset < 0)
return;
+ addr2 = fdt_get_base_address(fdt, offset);
+ if (addr2 == OF_BAD_ADDR)
+ return;
+ addr2 -= NS16550A_OFFSET;
+
+ /* sanity check */
+ if (addr != addr2)
+ return;
+
+ support_card_base = ioremap(addr, 0x100000);
+
support_card_found = true;
}
@@ -45,19 +64,19 @@
*/
static void support_card_reset_deassert(void)
{
- writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
+ writel(0x00010000, support_card_base + MICRO_SUPPORT_CARD_RESET);
}
static void support_card_reset(void)
{
- writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
+ writel(0x00020003, support_card_base + MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
- revision = readl(MICRO_SUPPORT_CARD_REVISION);
+ revision = readl(support_card_base + MICRO_SUPPORT_CARD_REVISION);
revision &= 0xff;
/* revision 3.6.x card changed the revision format */
@@ -94,7 +113,7 @@
if (!support_card_found)
return 0;
- return smc911x_initialize(0, SMC911X_BASE);
+ return smc911x_initialize(0, (unsigned long)support_card_base + SMC911X_OFFSET);
}
#endif
@@ -264,5 +283,5 @@
s++;
}
- writel(~val, LED_BASE);
+ writel(~val, support_card_base + LED_OFFSET);
}
diff --git a/arch/arm/mach-uniphier/mmc-first-dev.c b/arch/arm/mach-uniphier/mmc-first-dev.c
index 149e662..e2f4f4e 100644
--- a/arch/arm/mach-uniphier/mmc-first-dev.c
+++ b/arch/arm/mach-uniphier/mmc-first-dev.c
@@ -9,13 +9,14 @@
#include <mmc.h>
#include <linux/errno.h>
-static int find_first_mmc_device(void)
+static int find_first_mmc_device(bool is_sd)
{
struct mmc *mmc;
int i;
for (i = 0; (mmc = find_mmc_device(i)); i++) {
- if (!mmc_init(mmc) && IS_MMC(mmc))
+ if (!mmc_init(mmc) &&
+ ((is_sd && IS_SD(mmc)) || (!is_sd && IS_MMC(mmc))))
return i;
}
@@ -24,14 +25,14 @@
int mmc_get_env_dev(void)
{
- return find_first_mmc_device();
+ return find_first_mmc_device(false);
}
static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int dev;
- dev = find_first_mmc_device();
+ dev = find_first_mmc_device(false);
if (dev < 0)
return CMD_RET_FAILURE;
@@ -44,3 +45,21 @@
"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
""
);
+
+static int do_sdsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int dev;
+
+ dev = find_first_mmc_device(true);
+ if (dev < 0)
+ return CMD_RET_FAILURE;
+
+ env_set_ulong("sd_first_dev", dev);
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ sdsetn, 1, 1, do_sdsetn,
+ "Set the first SD dev number to \"sd_first_dev\" environment",
+ ""
+);
diff --git a/arch/arm/mach-uniphier/nand-reset.c b/arch/arm/mach-uniphier/nand-reset.c
new file mode 100644
index 0000000..11cadaa
--- /dev/null
+++ b/arch/arm/mach-uniphier/nand-reset.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0 or later
+/*
+ * Copyright (C) 2020 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/errno.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <reset.h>
+
+#include "init.h"
+
+/*
+ * Assert the Denali NAND controller reset if found.
+ *
+ * On LD4, the bootstrap process starts running after power-on reset regardless
+ * of the boot mode, here the pin-mux is not necessarily set up for NAND, then
+ * the controller is stuck. Assert the controller reset here, and should be
+ * deasserted in the driver after the pin-mux is correctly handled. For other
+ * SoCs, the bootstrap runs only when the boot mode selects ONFi, but it is yet
+ * effective when the boot swap is on. So, the reset should be asserted anyway.
+ */
+void uniphier_nand_reset_assert(void)
+{
+ struct udevice *dev;
+ struct reset_ctl_bulk resets;
+ int ret;
+
+ ret = uclass_find_first_device(UCLASS_MTD, &dev);
+ if (ret || !dev)
+ return;
+
+ /* make sure this is the Denali NAND controller */
+ if (strcmp(dev->driver->name, "denali-nand-dt"))
+ return;
+
+ ret = reset_get_bulk(dev, &resets);
+ if (ret)
+ return;
+
+ reset_assert_bulk(&resets);
+}
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 634dbbe..7f4cad8 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -14,6 +14,7 @@
config KM_PNVRAM
hex "Pseudo RAM"
default 0x80000
+ depends on !ARCH_SOCFPGA
help
Start address of the pseudo non-volatile RAM for application.
@@ -21,6 +22,7 @@
hex "Physical RAM"
default 0x17F000 if ARM
default 0x100000 if PPC
+ depends on !ARCH_SOCFPGA
help
Start address of the physical RAM, which is the mounted /var folder.
@@ -29,6 +31,7 @@
default 0x801000 if KIRKWOOD
default 0x0 if MPC83xx
default 0x1000 if MPC85xx
+ depends on !ARCH_SOCFPGA
help
Reserved physical RAM area at the end of memory for special purposes.
@@ -37,6 +40,7 @@
default 0x2400000 if KIRKWOOD
default 0xC00000 if MPC83xx
default 0x2000000 if MPC85xx
+ depends on !ARCH_SOCFPGA
help
Start address of the CRAMFS containing the Linux kernel.
@@ -44,13 +48,13 @@
hex "Kernel Load Address"
default 0x2000000 if KIRKWOOD
default 0x400000 if MPC83xx
- default 0x1000000 if MPC85xx
+ default 0x1000000 if MPC85xx || ARCH_SOCFPGA
help
Address where to load Linux kernel in RAM.
config KM_FDT_ADDR
hex "FDT Load Address"
- default 0x23E0000 if KIRKWOOD
+ default 0x23E0000 if KIRKWOOD || ARCH_SOCFPGA
default 0xB80000 if MPC83xx
default 0x1F80000 if MPC85xx
help
@@ -71,7 +75,7 @@
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
default y if KIRKWOOD || MPC83xx
- default n if MPC85xx
+ default n if MPC85xx || ARCH_SOCFPGA
help
Use the Ethernet initialization implemented in common code, which
detects if a Piggy board is present.
@@ -91,6 +95,7 @@
config KM_IVM_BUS
int "IVM I2C Bus"
+ default 0 if ARCH_SOCFPGA
default 1 if KIRKWOOD || MPC85xx
default 2 if MPC83xx
help
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index fee7f03..60b89fe 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -328,7 +328,24 @@
int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *eedev = NULL;
+ ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev);
+ if (ret) {
+ printf("failed to get device for EEPROM at address 0x%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return 1;
+ }
+
+ ret = dm_i2c_read(eedev, 0, buf, len);
+ if (ret != 0) {
+ printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ return 1;
+ }
+#else
i2c_set_bus_num(CONFIG_KM_IVM_BUS);
/* add deblocking here */
i2c_make_abort();
@@ -338,6 +355,6 @@
printf("Error reading EEprom\n");
return -2;
}
-
+#endif
return ivm_populate_env(buf, len, mac_address_offset);
}
diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS
new file mode 100644
index 0000000..5dc4aa6
--- /dev/null
+++ b/board/keymile/secu1/MAINTAINERS
@@ -0,0 +1,5 @@
+ABB SECU1 BOARD
+M: Holger Brunck <holger.brunck@ch.abb.com>
+S: Maintained
+F: include/configs/socfpga_arria5_secu1.h
+F: configs/socfpga_secu1_defconfig
diff --git a/board/keymile/secu1/Makefile b/board/keymile/secu1/Makefile
new file mode 100644
index 0000000..4704d59
--- /dev/null
+++ b/board/keymile/secu1/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2020 ABB
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o ../common/ivm.o
diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h
new file mode 100644
index 0000000..7640c56
--- /dev/null
+++ b/board/keymile/secu1/qts/iocsr_config.h
@@ -0,0 +1,694 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00080000,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x00001000,
+ 0x00000000,
+ 0x0300C000,
+ 0x0000000C,
+ 0x00000000,
+ 0x00000000,
+ 0x00000800,
+ 0x01806018,
+ 0x00000000,
+ 0x01800000,
+ 0x00001806,
+ 0x00001806,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00020000,
+ 0x08000000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x00010000,
+ 0x04000000,
+ 0x00000000,
+ 0x00000010,
+ 0x00004000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x00000006,
+ 0x00000008,
+ 0x00601806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+ 0x00000000,
+ 0x00601800,
+ 0x80600000,
+ 0x80000001,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00080000,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00018060,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x00001000,
+ 0x0300C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+ 0x01806018,
+ 0x01806000,
+ 0x00000006,
+ 0x00000000,
+ 0x00601806,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+ 0x00601806,
+ 0x80601800,
+ 0x80600001,
+ 0x80000601,
+ 0x00180601,
+ 0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x2CC20D80,
+ 0x082000FF,
+ 0x08028001,
+ 0x00100000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x00000000,
+ 0xC0000010,
+ 0x00C00512,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xA2580000,
+ 0x60001800,
+ 0x00600289,
+ 0x800A2580,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x512C0000,
+ 0xB0000C00,
+ 0x00300144,
+ 0xC00512C0,
+ 0x144B0000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xA0680514,
+ 0xC3034028,
+ 0x06181A00,
+ 0x805140D0,
+ 0x34069A06,
+ 0x01A034D0,
+ 0x240D0000,
+ 0x28A06809,
+ 0x00000340,
+ 0xD000001A,
+ 0x06809240,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x80000000,
+ 0x01800A25,
+ 0x00289600,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x44B00000,
+ 0xC0003001,
+ 0x00C00512,
+ 0x00000FF0,
+ 0x512C0000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x581D8000,
+ 0x60001800,
+ 0x00600289,
+ 0x800A2580,
+ 0x16076001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x512C0000,
+ 0xB0000C00,
+ 0x00300144,
+ 0xC00512C0,
+ 0x144B0000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xA0680514,
+ 0x4D034028,
+ 0x1A681A03,
+ 0x805140D0,
+ 0x34069A06,
+ 0x01A00020,
+ 0x240D0001,
+ 0x49206809,
+ 0x034D0340,
+ 0xD01A681A,
+ 0x06805140,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x80000000,
+ 0x01800A25,
+ 0x00289600,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x44B0090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x1C864000,
+ 0x45147A07,
+ 0xA228A3DA,
+ 0xF491451E,
+ 0x0358D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x028A0680,
+ 0xDA79E47A,
+ 0x1EA228A3,
+ 0xC8F49965,
+ 0x000344B2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x60120800,
+ 0x00600289,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xC228A3DC,
+ 0xF491451E,
+ 0x0344B2C8,
+ 0x821A034D,
+ 0x0000D000,
+ 0x00000680,
+ 0xD469A47A,
+ 0x1E83CF23,
+ 0xC8F71E79,
+ 0x000344B2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x0C864000,
+ 0x79E47A03,
+ 0x92AAA3D2,
+ 0xF595551E,
+ 0x034CF3C8,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDA79E47A,
+ 0x1EA32CA3,
+ 0xC8F69965,
+ 0x000354F3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020000,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00002000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x0C864000,
+ 0x59647A03,
+ 0xC3CF23DC,
+ 0xF711451E,
+ 0x0358D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD459647A,
+ 0x1E83CF23,
+ 0x48F51E79,
+ 0x000348D3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x00000000,
+ 0x00000010,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00141419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/pinmux_config.h b/board/keymile/secu1/qts/pinmux_config.h
new file mode 100644
index 0000000..a940606
--- /dev/null
+++ b/board/keymile/secu1/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 0, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 0, /* FLASHIO2 */
+ 0, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 0, /* FLASHIO9 */
+ 0, /* FLASHIO10 */
+ 0, /* FLASHIO11 */
+ 3, /* GENERALIO0 */
+ 3, /* GENERALIO1 */
+ 3, /* GENERALIO2 */
+ 3, /* GENERALIO3 */
+ 3, /* GENERALIO4 */
+ 3, /* GENERALIO5 */
+ 3, /* GENERALIO6 */
+ 3, /* GENERALIO7 */
+ 3, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 3, /* GENERALIO13 */
+ 3, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 3, /* MIXED1IO0 */
+ 3, /* MIXED1IO1 */
+ 3, /* MIXED1IO2 */
+ 3, /* MIXED1IO3 */
+ 3, /* MIXED1IO4 */
+ 3, /* MIXED1IO5 */
+ 3, /* MIXED1IO6 */
+ 3, /* MIXED1IO7 */
+ 3, /* MIXED1IO8 */
+ 3, /* MIXED1IO9 */
+ 3, /* MIXED1IO10 */
+ 3, /* MIXED1IO11 */
+ 3, /* MIXED1IO12 */
+ 3, /* MIXED1IO13 */
+ 3, /* MIXED1IO14 */
+ 0, /* MIXED1IO15 */
+ 0, /* MIXED1IO16 */
+ 0, /* MIXED1IO17 */
+ 0, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 1, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h
new file mode 100644
index 0000000..f0c3186
--- /dev/null
+++ b/board/keymile/secu1/qts/pll_config.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 40000000
+#define CONFIG_HPS_CLK_OSC2_HZ 40000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
+#define CONFIG_HPS_CLK_NAND_HZ 31250000
+#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h
new file mode 100644
index 0000000..b0ff86e
--- /dev/null
+++ b/board/keymile/secu1/qts/sdram_config.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x11
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14
+#define RW_MGR_CLEAR_DQS_ENABLE 0x4B
+#define RW_MGR_EMR 0x09
+#define RW_MGR_EMR2 0x0D
+#define RW_MGR_EMR3 0x0F
+#define RW_MGR_EMR_OCD_ENABLE 0x0B
+#define RW_MGR_GUARANTEED_READ 0x4E
+#define RW_MGR_GUARANTEED_READ_CONT 0x56
+#define RW_MGR_GUARANTEED_WRITE 0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x77
+#define RW_MGR_IDLE_LOOP2 0x76
+#define RW_MGR_INIT_CKE_0 0x71
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37
+#define RW_MGR_MR_CALIB 0x05
+#define RW_MGR_MR_DLL_RESET 0x07
+#define RW_MGR_MR_USER 0x03
+#define RW_MGR_NOP 0x01
+#define RW_MGR_PRECHARGE_ALL 0x16
+#define RW_MGR_READ_B2B 0x5B
+#define RW_MGR_READ_B2B_WAIT1 0x63
+#define RW_MGR_READ_B2B_WAIT2 0x6D
+#define RW_MGR_REFRESH 0x18
+
+/* Sequencer defines configuration */
+#define AFI_CLK_FREQ 301
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 6
+#define CALIB_VFIFO_OFFSET 4
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 416
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 74
+#define TINIT_CNTR1_VAL 20
+#define TINIT_CNTR2_VAL 20
+#define TRESET_CNTR0_VAL 74
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x30700000,
+ 0x38700000,
+ 0x30700000,
+ 0x20700000,
+ 0x10000853,
+ 0x10000853,
+ 0x10000953,
+ 0x10010000,
+ 0x10010380,
+ 0x10020000,
+ 0x10030000,
+ 0x10300400,
+ 0x10600000,
+ 0x10620000,
+ 0x10200400,
+ 0x10400000,
+ 0x1c900000,
+ 0x1c920000,
+ 0x1c900008,
+ 0x1c920008,
+ 0x38f00000,
+ 0x3cf00000,
+ 0x38700000,
+ 0x10100000,
+ 0x18900000,
+ 0x13500000,
+ 0x13520000,
+ 0x13500008,
+ 0x13520008,
+ 0x33700000,
+ 0x10500008
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80180,
+ 0x100,
+ 0x80000,
+ 0x200,
+ 0x80000,
+ 0x280,
+ 0x80000,
+ 0x300,
+ 0x80000,
+ 0x380,
+ 0x80000,
+ 0x400,
+ 0x80000,
+ 0x480,
+ 0x80000,
+ 0x500,
+ 0x80000,
+ 0x600,
+ 0x8000,
+ 0x680,
+ 0xa000,
+ 0x80000,
+ 0x700,
+ 0x80000,
+ 0x780,
+ 0x80000,
+ 0x968,
+ 0xcae8,
+ 0x8e8,
+ 0x8ae8,
+ 0x988,
+ 0xea88,
+ 0x808,
+ 0xaa88,
+ 0x80000,
+ 0xcc00,
+ 0xcb80,
+ 0xe080,
+ 0xa00,
+ 0x20ae0,
+ 0x20ae0,
+ 0x20ae0,
+ 0x20ae0,
+ 0xb00,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x60c80,
+ 0x60e80,
+ 0x60e80,
+ 0x60e80,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0xcc00,
+ 0xcb80,
+ 0xe080,
+ 0xa00,
+ 0x30ae0,
+ 0x30ae0,
+ 0x30ae0,
+ 0x30ae0,
+ 0xb00,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x70c80,
+ 0x70e80,
+ 0x70e80,
+ 0x70e80,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0xf58,
+ 0x58,
+ 0x80000,
+ 0xf68,
+ 0x168,
+ 0x168,
+ 0x8168,
+ 0x40de8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0xf68,
+ 0x168,
+ 0x168,
+ 0xa168,
+ 0x80000,
+ 0x40c88,
+ 0x40e88,
+ 0x40e88,
+ 0x40e88,
+ 0x40d68,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0xa000,
+ 0x40de8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40e08,
+ 0x40e88,
+ 0x40e88,
+ 0x40e88,
+ 0xf00,
+ 0xc000,
+ 0x8000,
+ 0xe000,
+ 0x80000,
+ 0x180,
+ 0x8180,
+ 0xa180,
+ 0xc180,
+ 0x80180,
+ 0x8000,
+ 0xa000,
+ 0x80000
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c
new file mode 100644
index 0000000..dc04a21
--- /dev/null
+++ b/board/keymile/secu1/socfpga.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 ABB
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+#include "../common/common.h"
+
+/*
+ * For FU1, the MAC address associated with the mgmt port should
+ * be the base address (as read from the IVM) + 4, and for FU2 it
+ * is + 10
+ */
+#define MAC_ADDRESS_OFFSET_FU1 4
+#define MAC_ADDRESS_OFFSET_FU2 10
+
+/*
+ * This function reads the state of GPIO40 and returns true (non-zero)
+ * if it is '1' and false(0) otherwise.
+ *
+ * This pin is routed to a pull-up on FU2 and a pull-down on
+ */
+#define GPIO_FU_DETECTION 40
+
+int secu1_is_fu2(void)
+{
+ int value;
+ int ret = gpio_request(GPIO_FU_DETECTION, "secu");
+
+ if (ret) {
+ printf("gpio: failed to request pin for FU detection\n");
+ return 1;
+ }
+ gpio_direction_input(GPIO_FU_DETECTION);
+ value = gpio_get_value(GPIO_FU_DETECTION);
+
+ if (value == 1)
+ printf("FU2 detected\n");
+ else
+ printf("FU1 detected\n");
+
+ return value;
+}
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+ if (secu1_is_fu2())
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ MAC_ADDRESS_OFFSET_FU2);
+ else
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ MAC_ADDRESS_OFFSET_FU1);
+
+ return 0;
+}
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
index 5d7465a..8172d26 100644
--- a/board/st/stm32mp1/README
+++ b/board/st/stm32mp1/README
@@ -1,519 +1 @@
-SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-#
-# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
-#
-
-U-Boot on STMicroelectronics STM32MP15x
-=======================================
-
-1. Summary
-==========
-This is a quick instruction for setup stm32mp1 boards.
-
-2. Supported devices
-====================
-U-Boot supports STMP32MP15x SoCs: STM32MP157, STM32MP153 and STM32MP151
-
-The STM32MP15x is a Cortex-A MPU aimed at various applications.
-It features:
-- Dual core Cortex-A7 application core (Single on STM32MP151)
-- 2D/3D image composition with GPU (only on STM32MP157)
-- Standard memories interface support
-- Standard connectivity, widely inherited from the STM32 MCU family
-- Comprehensive security support
-
-Everything is supported in Linux but U-Boot is limited to:
-1. UART
-2. SDCard/MMC controller (SDMMC)
-3. NAND controller (FMC)
-4. NOR controller (QSPI)
-5. USB controller (OTG DWC2)
-6. Ethernet controller
-
-And the necessary drivers
-1. I2C
-2. STPMIC1 (PMIC and regulator)
-3. Clock, Reset, Sysreset
-4. Fuse
-
-Currently the following boards are supported:
-+ stm32mp157a-avenger96.dts
-+ stm32mp157a-dk1.dts
-+ stm32mp157c-dk2.dts
-+ stm32mp157c-ed1.dts
-+ stm32mp157c-ev1.dts
-
-3. Boot Sequences
-=================
-
-BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
-
-with FSBL = First Stage Bootloader
- SSBL = Second Stage Bootloader
-
-3 boot configurations are supported:
-
-1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig)
- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
- TF-A performs a full initialization of Secure peripherals and installs a
- secure monitor.
- U-Boot is running in normal world and uses TF-A monitor
- to access to secure resources.
-
-2) The "Trusted" boot chain with OP-TEE
- (defconfig_file : stm32mp15_optee_defconfig)
- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
- TF-A performs a full initialization of Secure peripherals and installs OP-TEE
- from specific partitions (teeh, teed, teex).
- U-Boot is running in normal world and uses OP-TEE monitor to access
- to secure resources.
-
-3) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
- BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
- SPL has limited security initialisation
- U-Boot is running in secure mode and provide a secure monitor to the kernel
- with only PSCI support (Power State Coordination Interface defined by ARM).
-
-All the STM32MP15x boards supported by U-Boot use the same generic board
-stm32mp1 which support all the bootable devices.
-
-Each board is configurated only with the associated device tree.
-
-4. Device Tree Selection
-========================
-
-You need to select the appropriate device tree for your board,
-the supported device trees for stm32mp157 are:
-
-+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
- dts: stm32mp157c-ev1
-
-+ ed1: daughter board with pmic stpmic1
- dts: stm32mp157c-ed1
-
-+ dk1: Discovery board
- dts: stm32mp157a-dk1
-
-+ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
- dts: stm32mp157c-dk2
-
-+ avenger96: Avenger96 board from Arrow Electronics
- dts: stm32mp157a-avenger96
-
-5. Build Procedure
-==================
-
-1. Install required tools for U-Boot
-
- + install package needed in U-Boot makefile
- (libssl-dev, swig, libpython-dev...)
- + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
- from SDK for STM32MP15x, or any crosstoolchains from your distribution)
-
-2. Set the cross compiler:
-
- # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
- (you can use any gcc cross compiler compatible with U-Boot)
-
-3. Select the output directory (optional)
-
- # export KBUILD_OUTPUT=/path/to/output
-
- for example: use one output directory for each configuration
- # export KBUILD_OUTPUT=stm32mp15_trusted
- # export KBUILD_OUTPUT=stm32mp15_optee
- # export KBUILD_OUTPUT=stm32mp15_basic
-
- you can build outside of code directory:
- # export KBUILD_OUTPUT=../build/stm32mp15_trusted
-
-4. Configure U-Boot:
-
- # make <defconfig_file>
-
- - For trusted boot mode : "stm32mp15_trusted_defconfig"
- - For trusted with OP-TEE boot mode : "stm32mp15_optee_defconfig"
- - For basic boot mode: "stm32mp15_basic_defconfig"
-
-5. Configure the device-tree and build the U-Boot image:
-
- # make DEVICE_TREE=<name> all
-
- example:
- a) trusted boot on ev1
- # export KBUILD_OUTPUT=stm32mp15_trusted
- # make stm32mp15_trusted_defconfig
- # make DEVICE_TREE=stm32mp157c-ev1 all
-
- b) trusted with OP-TEE boot on dk2
- # export KBUILD_OUTPUT=stm32mp15_optee
- # make stm32mp15_optee_defconfig
- # make DEVICE_TREE=stm32mp157c-dk2 all
-
- c) basic boot on ev1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157c-ev1 all
-
- d) basic boot on ed1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157c-ed1 all
-
- e) basic boot on dk1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157a-dk1 all
-
- f) basic boot on avenger96
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157a-avenger96 all
-
-6. Output files
-
- BootRom and TF-A expect binaries with STM32 image header
- SPL expects file with U-Boot uImage header
-
- So in the output directory (selected by KBUILD_OUTPUT),
- you can found the needed files:
-
- a) For Trusted boot (with or without OP-TEE)
- + FSBL = tf-a.stm32 (provided by TF-A compilation)
- + SSBL = u-boot.stm32
-
- b) For Basic boot
- + FSBL = spl/u-boot-spl.stm32
- + SSBL = u-boot.img
-
-6. Switch Setting for Boot Mode
-===============================
-
-You can select the boot mode, on the board with one switch :
-
-- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2
-
- -----------------------------------
- Boot Mode BOOT2 BOOT1 BOOT0
- -----------------------------------
- Reserved 0 0 0
- NOR 0 0 1
- SD-Card 1 0 1
- eMMC 0 1 0
- NAND 0 1 1
- Recovery 1 1 0
- Recovery 0 0 0
-
-- on board DK1/DK2 with the switch SW1 : BOOT0, BOOT2
- (BOOT1 forced to 0, NOR not supported)
-
- --------------------------
- Boot Mode BOOT2 BOOT0
- --------------------------
- Reserved 1 0
- SD-Card 1 1
- Recovery 0 0
-
-- Boot mode of Avenger96 can be selected using switch S3
-
- -----------------------------------
- Boot Mode BOOT2 BOOT1 BOOT0
- -----------------------------------
- Recovery 0 0 0
- NOR 0 0 1
- SD-Card 1 0 1
- eMMC 0 1 0
- NAND 0 1 1
- Reserved 1 0 0
- Recovery 1 1 0
- SD-Card 1 1 1
-
-Recovery is a boot from serial link (UART/USB) and it is used with
-STM32CubeProgrammer tool to load executable in RAM and to update the flash
-devices available on the board (NOR/NAND/eMMC/SDCARD).
-The communication between HOST and board is based on
-- for UARTs : the uart protocol used with all MCU STM32
-- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
-
-7. Prepare an SDCard
-===================
-
-The minimal requirements for STMP32MP1 boot up to U-Boot are:
-- GPT partitioning (with gdisk or with sgdisk)
-- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
-- one ssbl partition for U-Boot
-
-Then the minimal GPT partition is:
- ----- ------- --------- --------------
- | Num | Name | Size | Content |
- ----- ------- -------- ---------------
- | 1 | fsbl1 | 256 KiB | TF-A or SPL |
- | 2 | fsbl2 | 256 KiB | TF-A or SPL |
- | 3 | ssbl | enought | U-Boot |
- | * | - | - | Boot/Rootfs |
- ----- ------- --------- --------------
-
-(*) add bootable partition for extlinux.conf
- following Generic Distribution
- (doc/README.distro for use)
-
- according the used card reader select the block device
- (/dev/sdx or /dev/mmcblk0)
- in the next example I use /dev/mmcblk0
-
-for example: with gpt table with 128 entries
-
- a) remove previous formatting
- # sgdisk -o /dev/<SDCard dev>
-
- b) create minimal image
- # sgdisk --resize-table=128 -a 1 \
- -n 1:34:545 -c 1:fsbl1 \
- -n 2:546:1057 -c 2:fsbl2 \
- -n 3:1058:5153 -c 3:ssbl \
- -p /dev/<SDCard dev>
-
- you can add other partitions for kernel
- one partition rootfs for example:
- -n 4:5154: -c 4:rootfs \
-
- c) copy the FSBL (2 times) and SSBL file on the correct partition.
- in this example in partition 1 to 3
-
- for basic boot mode : <SDCard dev> = /dev/mmcblk0
- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
- # dd if=u-boot.img of=/dev/mmcblk0p3
-
- for trusted boot mode :
- # dd if=tf-a.stm32 of=/dev/mmcblk0p1
- # dd if=tf-a.stm32 of=/dev/mmcblk0p2
- # dd if=u-boot.stm32 of=/dev/mmcblk0p3
-
-To boot from SDCard, select BootPinMode = 1 0 1 and reset.
-
-8. Prepare eMMC
-===============
-You can use U-Boot to copy binary in eMMC.
-
-In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img)
-are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs).
-
-To boot from SDCard, select BootPinMode = 1 0 1 and reset.
-
-Then you update the eMMC with the next U-Boot command :
-
-a) prepare GPT on eMMC,
- example with 2 partitions, bootfs and roots:
-
- # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512"
- # gpt write mmc 1 ${emmc_part}
-
-b) copy SPL on eMMC on firts boot partition
- (SPL max size is 256kB, with LBA 512, 0x200)
-
- # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32
- # mmc dev 1
- # mmc partconf 1 1 1 1
- # mmc write ${fileaddr} 0 200
- # mmc partconf 1 1 1 0
-
-c) copy U-Boot in first GPT partition of eMMC
-
- # ext4load mmc 0:4 0xC0000000 u-boot.img
- # mmc dev 1
- # part start mmc 1 1 partstart
- # mmc write ${fileaddr} ${partstart} ${filesize}
-
-To boot from eMMC, select BootPinMode = 0 1 0 and reset.
-
-9. MAC Address
-==============
-
-Please read doc/README.enetaddr for the implementation guidelines for mac id
-usage. Basically, environment has precedence over board specific storage.
-
-For STMicroelectonics board, it is retrieved in STM32MP15x otp :
-- OTP_57[31:0] = MAC_ADDR[31:0]
-- OTP_58[15:0] = MAC_ADDR[47:32]
-
-To program a MAC address on virgin OTP words above, you can use the fuse command
-on bank 0 to access to internal OTP:
-
- Prerequisite: check if a MAC address isn't yet programmed in OTP
-
- 1- check OTP: their value must be equal to 0
-
- STM32MP> fuse sense 0 57 2
- Sensing bank 0:
- Word 0x00000039: 00000000 00000000
-
- 2- check environment variable
-
- STM32MP> env print ethaddr
- ## Error: "ethaddr" not defined
-
- Example to set mac address "12:34:56:78:9a:bc"
-
- 1- Write OTP
- STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
-
- 2- Read OTP
- STM32MP> fuse sense 0 57 2
- Sensing bank 0:
- Word 0x00000039: 78563412 0000bc9a
-
- 3- next REBOOT :
- ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
-
- 4 check env update
- STM32MP> env print ethaddr
- ethaddr=12:34:56:78:9a:bc
-
-warning:: This MAC address provisioning can't be executed twice on the same
- board as the OTP are protected. It is already done for the board
- provided by STMicroelectronics.
-
-10. Coprocessor firmware
-========================
-
-U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
-
-A/ Manuallly by using rproc commands (update the bootcmd)
- Configurations
- # env set name_copro "rproc-m4-fw.elf"
- # env set dev_copro 0
- # env set loadaddr_copro 0xC1000000
-
- Load binary from bootfs partition (number 4) on SDCard (mmc 0)
- # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro}
- => ${filesize} updated with the size of the loaded file
-
- Start M4 firmware with remote proc command
- # rproc init
- # rproc load ${dev_copro} ${loadaddr_copro} ${filesize}
- # rproc start ${dev_copro}
-
-B/ Automatically by using FIT feature and generic DISTRO bootcmd
-
- see examples in this directory :
-
- Generate FIT including kernel + device tree + M4 firmware
- with cfg with M4 boot
- $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
-
- Then using DISTRO configuration file: see extlinux.conf to select
- the correct configuration
- => stm32mp157c-ev1-m4
- => stm32mp157c-dk2-m4
-
-11. DFU support
-===============
-
-The DFU is supported on ST board.
-The env variable dfu_alt_info is automatically build, and all
-the memory present on the ST boards are exported.
-
-The mode is started by
-
-STM32MP> dfu 0
-
-On EV1 board:
-
-STM32MP> dfu 0 list
-
-DFU alt settings list:
-dev: RAM alt: 0 name: uImage layout: RAM_ADDR
-dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR
-dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR
-dev: eMMC alt: 3 name: sdcard_fsbl1 layout: RAW_ADDR
-dev: eMMC alt: 4 name: sdcard_fsbl2 layout: RAW_ADDR
-dev: eMMC alt: 5 name: sdcard_ssbl layout: RAW_ADDR
-dev: eMMC alt: 6 name: sdcard_bootfs layout: RAW_ADDR
-dev: eMMC alt: 7 name: sdcard_vendorfs layout: RAW_ADDR
-dev: eMMC alt: 8 name: sdcard_rootfs layout: RAW_ADDR
-dev: eMMC alt: 9 name: sdcard_userfs layout: RAW_ADDR
-dev: eMMC alt: 10 name: emmc_fsbl1 layout: RAW_ADDR
-dev: eMMC alt: 11 name: emmc_fsbl2 layout: RAW_ADDR
-dev: eMMC alt: 12 name: emmc_ssbl layout: RAW_ADDR
-dev: eMMC alt: 13 name: emmc_bootfs layout: RAW_ADDR
-dev: eMMC alt: 14 name: emmc_vendorfs layout: RAW_ADDR
-dev: eMMC alt: 15 name: emmc_rootfs layout: RAW_ADDR
-dev: eMMC alt: 16 name: emmc_userfs layout: RAW_ADDR
-dev: MTD alt: 17 name: nor_fsbl1 layout: RAW_ADDR
-dev: MTD alt: 18 name: nor_fsbl2 layout: RAW_ADDR
-dev: MTD alt: 19 name: nor_ssbl layout: RAW_ADDR
-dev: MTD alt: 20 name: nor_env layout: RAW_ADDR
-dev: MTD alt: 21 name: nand_fsbl layout: RAW_ADDR
-dev: MTD alt: 22 name: nand_ssbl1 layout: RAW_ADDR
-dev: MTD alt: 23 name: nand_ssbl2 layout: RAW_ADDR
-dev: MTD alt: 24 name: nand_UBI layout: RAW_ADDR
-dev: VIRT alt: 25 name: OTP layout: RAW_ADDR
-dev: VIRT alt: 26 name: PMIC layout: RAW_ADDR
-
-All the supported device are exported for dfu-util tool:
-
-$> dfu-util -l
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=26, name="PMIC", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=25, name="OTP", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=24, name="nand_UBI", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=23, name="nand_ssbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=22, name="nand_ssbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="nand_fsbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="nor_env", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nor_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="emmc_userfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="emmc_rootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="emmc_vendorfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="emmc_bootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="emmc_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="emmc_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="emmc_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="sdcard_userfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="sdcard_rootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="sdcard_vendorfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="sdcard_bootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="sdcard_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="sdcard_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="sdcard_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330"
-
-You can update the boot device:
-
-#SDCARD
-$> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
-
-#EMMC
-$> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
-
-#NOR
-$> dfu-util -d 0483:5720 -a 17 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 18 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 19 -D u-boot-stm32mp157c-ev1-trusted.img
-
-#NAND (UBI partition used for NAND only boot or NOR + NAND boot)
-$> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 22 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 24 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
-
-And you can also dump the OTP and the PMIC NVM with:
-
-$> dfu-util -d 0483:5720 -a 25 -U otp.bin
-$> dfu-util -d 0483:5720 -a 26 -U pmic.bin
+see doc/board/st/stm32mp1.rst
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index fc6463a..78bcd84 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -5,3 +5,4 @@
F: board/xilinx/zynq/
F: include/configs/zynq*.h
F: configs/zynq_*_defconfig
+F: configs/xilinx_zynq_*
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 6a2acee..096a7ac 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -13,6 +13,11 @@
$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
endif
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
ifeq ($(init-objs),)
hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
index 7c6bc9f..a376ba5 100644
--- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -219,8 +219,8 @@
EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
- EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
- EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 174f4ed..398c6aa 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -13,6 +13,11 @@
$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
endif
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
ifeq ($(init-objs),)
hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 510e258..21dfd44 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -244,6 +244,10 @@
EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID,
},
{
+ "Load File2",
+ EFI_LOAD_FILE2_PROTOCOL_GUID,
+ },
+ {
"Simple Network",
EFI_SIMPLE_NETWORK_PROTOCOL_GUID,
},
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
new file mode 100644
index 0000000..230959e
--- /dev/null
+++ b/configs/socfpga_secu1_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_DM_GPIO=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_SOCFPGA_ARRIA5_SECU1=y
+CONFIG_ENV_OFFSET_REDUND=0x120000
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_SPI_SUPPORT is not set
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp"
+CONFIG_FIT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_secu1.dtb"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_MTDIDS_DEFAULT="nand0=denali-nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=denali-nand:512k(nand.4spl),512k(nand.uboot),128k(nand.env1),128k(nand.env2),0x1000000(nand.rec),0x3ee40000(nand.ubi),0x80000@0x3ff80000(nand.bbt)"
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1"
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SPL_BLK is not set
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_EEPROM_SIZE=1024
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_DENALI_DT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2
+CONFIG_SPL_NAND_DENALI=y
+# CONFIG_DM_SPI_FLASH is not set
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_MV88E6352_SWITCH=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_GZIP is not set
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index d8ce198..4514468a 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -39,10 +39,10 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MTD=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
similarity index 100%
rename from configs/zynq_virt_defconfig
rename to configs/xilinx_zynq_virt_defconfig
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 12e1367..1dee757 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -6,7 +6,7 @@
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0001000
-CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
diff --git a/doc/api/efi.rst b/doc/api/efi.rst
index bc59382..631c0ce 100644
--- a/doc/api/efi.rst
+++ b/doc/api/efi.rst
@@ -125,6 +125,15 @@
.. kernel-doc:: lib/efi_loader/efi_gop.c
:internal:
+Load file 2 protocol
+~~~~~~~~~~~~~~~~~~~~
+
+The load file 2 protocol can be used by the Linux kernel to load the initial
+RAM disk. U-Boot can be configured to provide an implementation.
+
+.. kernel-doc:: lib/efi_loader/efi_load_initrd.c
+ :internal:
+
Network protocols
~~~~~~~~~~~~~~~~~
diff --git a/doc/board/index.rst b/doc/board/index.rst
index b8b956d..d43e536 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -16,4 +16,5 @@
renesas/index
rockchip/index
sifive/index
+ st/index
xilinx/index
diff --git a/doc/board/st/index.rst b/doc/board/st/index.rst
new file mode 100644
index 0000000..91f1d51
--- /dev/null
+++ b/doc/board/st/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+STMicroelectronics
+==================
+
+.. toctree::
+ :maxdepth: 2
+
+ stm32mp1
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
new file mode 100644
index 0000000..1640bf9
--- /dev/null
+++ b/doc/board/st/stm32mp1.rst
@@ -0,0 +1,611 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Patrick Delaunay <patrick.delaunay@st.com>
+
+STM32MP15x boards
+=================
+
+This is a quick instruction for setup STM32MP15x boards.
+
+Supported devices
+-----------------
+
+U-Boot supports STMP32MP15x SoCs:
+
+ - STM32MP157
+ - STM32MP153
+ - STM32MP151
+
+The STM32MP15x is a Cortex-A MPU aimed at various applications.
+
+It features:
+
+ - Dual core Cortex-A7 application core (Single on STM32MP151)
+ - 2D/3D image composition with GPU (only on STM32MP157)
+ - Standard memories interface support
+ - Standard connectivity, widely inherited from the STM32 MCU family
+ - Comprehensive security support
+
+Everything is supported in Linux but U-Boot is limited to:
+
+ 1. UART
+ 2. SD card/MMC controller (SDMMC)
+ 3. NAND controller (FMC)
+ 4. NOR controller (QSPI)
+ 5. USB controller (OTG DWC2)
+ 6. Ethernet controller
+
+And the necessary drivers
+
+ 1. I2C
+ 2. STPMIC1 (PMIC and regulator)
+ 3. Clock, Reset, Sysreset
+ 4. Fuse
+
+Currently the following boards are supported:
+
+ + stm32mp157a-avenger96.dts
+ + stm32mp157a-dk1.dts
+ + stm32mp157c-dk2.dts
+ + stm32mp157c-ed1.dts
+ + stm32mp157c-ev1.dts
+
+Boot Sequences
+--------------
+
+3 boot configurations are supported with:
+
++----------+------------------------+-------------------------+--------------+
+| **ROM** | **FSBL** | **SSBL** | **OS** |
++ **code** +------------------------+-------------------------+--------------+
+| | First Stage Bootloader | Second Stage Bootloader | Linux Kernel |
++ +------------------------+-------------------------+--------------+
+| | embedded RAM | DDR |
++----------+------------------------+-------------------------+--------------+
+
+The **Trusted** boot chain
+``````````````````````````
+
+defconfig_file : stm32mp15_trusted_defconfig
+
+ +-------------+-------------------------+------------+-------+
+ | ROM code | FSBL | SSBL | OS |
+ + +-------------------------+------------+-------+
+ | |Trusted Firmware-A (TF-A)| U-Boot | Linux |
+ +-------------+-------------------------+------------+-------+
+ | TrustZone |TF-A secure monitor |
+ +-------------+-------------------------+------------+-------+
+
+TF-A performs a full initialization of Secure peripherals and installs a
+secure monitor (BL32=SPMin).
+
+U-Boot is running in normal world and uses TF-A monitor to access
+to secure resources.
+
+The **Trusted** boot chain with **OP-TEE**
+``````````````````````````````````````````
+
+defconfig_file : stm32mp15_optee_defconfig
+
+ +-------------+-------------------------+------------+-------+
+ | ROM code | FSBL | SSBL | OS |
+ + +-------------------------+------------+-------+
+ | |Trusted Firmware-A (TF-A)| U-Boot | Linux |
+ +-------------+-------------------------+------------+-------+
+ | TrustZone |OP-TEE |
+ +-------------+-------------------------+------------+-------+
+
+TF-A performs a full initialization of Secure peripherals and installs OP-TEE
+from specific partitions (teeh, teed, teex).
+
+U-Boot is running in normal world and uses OP-TEE monitor to access
+to secure resources.
+
+The **Basic** boot chain
+````````````````````````
+
+defconfig_file : stm32mp15_basic_defconfig
+
+ +-------------+------------+------------+-------+
+ | ROM code | FSBL | SSBL | OS |
+ + +------------+------------+-------+
+ | |U-Boot SPL | U-Boot | Linux |
+ +-------------+------------+------------+-------+
+ | TrustZone | | PSCI from U-Boot |
+ +-------------+------------+------------+-------+
+
+SPL has limited security initialization
+
+U-Boot is running in secure mode and provide a secure monitor to the kernel
+with only PSCI support (Power State Coordination Interface defined by ARM).
+
+All the STM32MP15x boards supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configured only with the associated device tree.
+
+Device Tree Selection
+---------------------
+
+You need to select the appropriate device tree for your board,
+the supported device trees for STM32MP15x are:
+
++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
+
+ + stm32mp157c-ev1
+
++ ed1: daughter board with pmic stpmic1
+
+ + stm32mp157c-ed1
+
++ dk1: Discovery board
+
+ + stm32mp157a-dk1
+
++ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
+
+ + stm32mp157c-dk2
+
++ avenger96: Avenger96 board from Arrow Electronics
+
+ + stm32mp157a-avenger96
+
+Build Procedure
+---------------
+
+1. Install the required tools for U-Boot
+
+ * install package needed in U-Boot makefile
+ (libssl-dev, swig, libpython-dev...)
+
+ * install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+ from SDK for STM32MP15x, or any crosstoolchains from your distribution)
+ (you can use any gcc cross compiler compatible with U-Boot)
+
+2. Set the cross compiler::
+
+ # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+
+3. Select the output directory (optional)::
+
+ # export KBUILD_OUTPUT=/path/to/output
+
+ for example: use one output directory for each configuration::
+
+ # export KBUILD_OUTPUT=stm32mp15_trusted
+ # export KBUILD_OUTPUT=stm32mp15_optee
+ # export KBUILD_OUTPUT=stm32mp15_basic
+
+ you can build outside of code directory::
+
+ # export KBUILD_OUTPUT=../build/stm32mp15_trusted
+
+4. Configure U-Boot::
+
+ # make <defconfig_file>
+
+ with <defconfig_file>:
+
+ - For **trusted** boot mode : **stm32mp15_trusted_defconfig**
+ - For **trusted** with OP-TEE boot mode : **stm32mp15_optee_defconfig**
+ - For basic boot mode: stm32mp15_basic_defconfig
+
+5. Configure the device-tree and build the U-Boot image::
+
+ # make DEVICE_TREE=<name> all
+
+ Examples:
+
+ a) trusted boot on ev1::
+
+ # export KBUILD_OUTPUT=stm32mp15_trusted
+ # make stm32mp15_trusted_defconfig
+ # make DEVICE_TREE=stm32mp157c-ev1 all
+
+ b) trusted with OP-TEE boot on dk2::
+
+ # export KBUILD_OUTPUT=stm32mp15_optee
+ # make stm32mp15_optee_defconfig
+ # make DEVICE_TREE=stm32mp157c-dk2 all
+
+ c) basic boot on ev1::
+
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-ev1 all
+
+ d) basic boot on ed1::
+
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-ed1 all
+
+ e) basic boot on dk1::
+
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157a-dk1 all
+
+ f) basic boot on avenger96::
+
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157a-avenger96 all
+
+6. Output files
+
+ BootRom and TF-A expect binaries with STM32 image header
+ SPL expects file with U-Boot uImage header
+
+ So in the output directory (selected by KBUILD_OUTPUT),
+ you can found the needed files:
+
+ - For **Trusted** boot (with or without OP-TEE)
+
+ - FSBL = **tf-a.stm32** (provided by TF-A compilation)
+ - SSBL = **u-boot.stm32**
+
+ - For Basic boot
+
+ - FSBL = spl/u-boot-spl.stm32
+ - SSBL = u-boot.img
+
+Switch Setting for Boot Mode
+----------------------------
+
+You can select the boot mode, on the board with one switch, to select
+the boot pin values = BOOT0, BOOT1, BOOT2
+
+ +-------------+---------+---------+---------+
+ |*Boot Mode* | *BOOT2* | *BOOT1* | *BOOT0* |
+ +=============+=========+=========+=========+
+ | Recovery | 0 | 0 | 0 |
+ +-------------+---------+---------+---------+
+ | NOR | 0 | 0 | 1 |
+ +-------------+---------+---------+---------+
+ | eMMC | 0 | 1 | 0 |
+ +-------------+---------+---------+---------+
+ | NAND | 0 | 1 | 1 |
+ +-------------+---------+---------+---------+
+ | Reserved | 1 | 0 | 0 |
+ +-------------+---------+---------+---------+
+ | SD-Card | 1 | 0 | 1 |
+ +-------------+---------+---------+---------+
+ | Recovery | 1 | 1 | 0 |
+ +-------------+---------+---------+---------+
+ | SPI-NAND | 1 | 1 | 1 |
+ +-------------+---------+---------+---------+
+
+- on the **daugther board ed1 = MB1263** with the switch SW1
+- on **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable)
+- on board **DK1/DK2** with the switch SW1 = BOOT0, BOOT2
+ with only 2 pins available (BOOT1 is forced to 0 and NOR not supported),
+ the possible value becomes:
+
+ +-------------+---------+---------+
+ |*Boot Mode* | *BOOT2* | *BOOT0* |
+ +=============+=========+=========+
+ | Recovery | 0 | 0 |
+ +-------------+---------+---------+
+ | NOR (NA)| 0 | 1 |
+ +-------------+---------+---------+
+ | Reserved | 1 | 0 |
+ +-------------+---------+---------+
+ | SD-Card | 1 | 1 |
+ +-------------+---------+---------+
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SD card).
+
+The communication between HOST and board is based on
+
+ - for UARTs : the uart protocol used with all MCU STM32
+ - for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
+
+Prepare an SD card
+------------------
+
+The minimal requirements for STMP32MP15x boot up to U-Boot are:
+
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+
+ +-------+--------+---------+-------------+
+ | *Num* | *Name* | *Size* | *Content* |
+ +=======+========+=========+=============+
+ | 1 | fsbl1 | 256 KiB | TF-A or SPL |
+ +-------+--------+---------+-------------+
+ | 2 | fsbl2 | 256 KiB | TF-A or SPL |
+ +-------+--------+---------+-------------+
+ | 3 | ssbl | enought | U-Boot |
+ +-------+--------+---------+-------------+
+ | 4 | <any> | <any> | Rootfs |
+ +-------+--------+---------+-------------+
+
+Add a 4th partition (Rootfs) marked bootable with a file extlinux.conf
+following the Generic Distribution feature (doc/README.distro for use).
+
+According the used card reader select the correct block device
+(for example /dev/sdx or /dev/mmcblk0).
+
+In the next example, it is /dev/mmcblk0
+
+For example: with gpt table with 128 entries
+
+a) remove previous formatting::
+
+ # sgdisk -o /dev/<SD card dev>
+
+b) create minimal image::
+
+ # sgdisk --resize-table=128 -a 1 \
+ -n 1:34:545 -c 1:fsbl1 \
+ -n 2:546:1057 -c 2:fsbl2 \
+ -n 3:1058:5153 -c 3:ssbl \
+ -n 4:5154: -c 4:rootfs \
+ -p /dev/<SD card dev>
+
+ With other partition for kernel one partition rootfs for kernel.
+
+c) copy the FSBL (2 times) and SSBL file on the correct partition.
+ in this example in partition 1 to 3
+
+ for basic boot mode : <SD card dev> = /dev/mmcblk0::
+
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+ # dd if=u-boot.img of=/dev/mmcblk0p3
+
+ for trusted boot mode: ::
+
+ # dd if=tf-a.stm32 of=/dev/mmcblk0p1
+ # dd if=tf-a.stm32 of=/dev/mmcblk0p2
+ # dd if=u-boot.stm32 of=/dev/mmcblk0p3
+
+To boot from SD card, select BootPinMode = 1 0 1 and reset.
+
+Prepare eMMC
+------------
+
+You can use U-Boot to copy binary in eMMC.
+
+In the next example, you need to boot from SD card and the images
+(u-boot-spl.stm32, u-boot.img) are presents on SD card (mmc 0)
+in ext4 partition 4 (bootfs).
+
+To boot from SD card, select BootPinMode = 1 0 1 and reset.
+
+Then you update the eMMC with the next U-Boot command :
+
+a) prepare GPT on eMMC,
+ example with 2 partitions, bootfs and roots::
+
+ # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512"
+ # gpt write mmc 1 ${emmc_part}
+
+b) copy SPL on eMMC on firts boot partition
+ (SPL max size is 256kB, with LBA 512, 0x200)::
+
+ # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32
+ # mmc dev 1
+ # mmc partconf 1 1 1 1
+ # mmc write ${fileaddr} 0 200
+ # mmc partconf 1 1 1 0
+
+c) copy U-Boot in first GPT partition of eMMC::
+
+ # ext4load mmc 0:4 0xC0000000 u-boo t.img
+ # mmc dev 1
+ # part start mmc 1 1 partstart
+ # mmc write ${fileaddr} ${partstart} ${filesize}
+
+To boot from eMMC, select BootPinMode = 0 1 0 and reset.
+
+MAC Address
+-----------
+
+Please read doc/README.enetaddr for the implementation guidelines for mac id
+usage. Basically, environment has precedence over board specific storage.
+
+For STMicroelectonics board, it is retrieved in STM32MP15x OTP :
+
+ - OTP_57[31:0] = MAC_ADDR[31:0]
+ - OTP_58[15:0] = MAC_ADDR[47:32]
+
+To program a MAC address on virgin OTP words above, you can use the fuse command
+on bank 0 to access to internal OTP:
+
+Prerequisite: check if a MAC address isn't yet programmed in OTP
+
+1) check OTP: their value must be equal to 0
+
+ STM32MP> fuse sense 0 57 2
+ Sensing bank 0:
+ Word 0x00000039: 00000000 00000000
+
+2) check environment variable
+
+ STM32MP> env print ethaddr
+ ## Error: "ethaddr" not defined
+
+Example to set mac address "12:34:56:78:9a:bc"
+
+1) Write OTP::
+
+ STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
+
+2) Read OTP::
+
+ STM32MP> fuse sense 0 57 2
+ Sensing bank 0:
+ Word 0x00000039: 78563412 0000bc9a
+
+3) next REBOOT, in the trace::
+
+ ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
+
+4) check env update::
+
+ STM32MP> env print ethaddr
+ ethaddr=12:34:56:78:9a:bc
+
+.. warning:: This command can't be executed twice on the same board as
+ OTP are protected. It is already done for the board
+ provided by STMicroelectronics.
+
+Coprocessor firmware
+--------------------
+
+U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
+
+a) Manuallly by using rproc commands (update the bootcmd)
+
+ Configurations::
+
+ # env set name_copro "rproc-m4-fw.elf"
+ # env set dev_copro 0
+ # env set loadaddr_copro 0xC1000000
+
+ Load binary from bootfs partition (number 4) on SD card (mmc 0)::
+
+ # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro}
+
+ => ${filesize} variable is updated with the size of the loaded file.
+
+ Start M4 firmware with remote proc command::
+
+ # rproc init
+ # rproc load ${dev_copro} ${loadaddr_copro} ${filesize}
+ # rproc start ${dev_copro}"00270033
+
+b) Automatically by using FIT feature and generic DISTRO bootcmd
+
+ see examples in the board stm32mp1 directory: fit_copro_kernel_dtb.its
+
+ Generate FIT including kernel + device tree + M4 firmware with cfg with M4 boot::
+
+ $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
+
+ Then using DISTRO configuration file: see extlinux.conf to select the correct
+ configuration:
+
+ - stm32mp157c-ev1-m4
+ - stm32mp157c-dk2-m4
+
+DFU support
+-----------
+
+The DFU is supported on ST board.
+
+The env variable dfu_alt_info is automatically build, and all
+the memory present on the ST boards are exported.
+
+The dfu mode is started by the command::
+
+ STM32MP> dfu 0
+
+On EV1 board, booting from SD card, without OP-TEE::
+
+ STM32MP> dfu 0 list
+ DFU alt settings list:
+ dev: RAM alt: 0 name: uImage layout: RAM_ADDR
+ dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR
+ dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR
+ dev: eMMC alt: 3 name: sdcard_fsbl1 layout: RAW_ADDR
+ dev: eMMC alt: 4 name: sdcard_fsbl2 layout: RAW_ADDR
+ dev: eMMC alt: 5 name: sdcard_ssbl layout: RAW_ADDR
+ dev: eMMC alt: 6 name: sdcard_bootfs layout: RAW_ADDR
+ dev: eMMC alt: 7 name: sdcard_vendorfs layout: RAW_ADDR
+ dev: eMMC alt: 8 name: sdcard_rootfs layout: RAW_ADDR
+ dev: eMMC alt: 9 name: sdcard_userfs layout: RAW_ADDR
+ dev: eMMC alt: 10 name: emmc_fsbl1 layout: RAW_ADDR
+ dev: eMMC alt: 11 name: emmc_fsbl2 layout: RAW_ADDR
+ dev: eMMC alt: 12 name: emmc_ssbl layout: RAW_ADDR
+ dev: eMMC alt: 13 name: emmc_bootfs layout: RAW_ADDR
+ dev: eMMC alt: 14 name: emmc_vendorfs layout: RAW_ADDR
+ dev: eMMC alt: 15 name: emmc_rootfs layout: RAW_ADDR
+ dev: eMMC alt: 16 name: emmc_userfs layout: RAW_ADDR
+ dev: MTD alt: 17 name: nor_fsbl1 layout: RAW_ADDR
+ dev: MTD alt: 18 name: nor_fsbl2 layout: RAW_ADDR
+ dev: MTD alt: 19 name: nor_ssbl layout: RAW_ADDR
+ dev: MTD alt: 20 name: nor_env layout: RAW_ADDR
+ dev: MTD alt: 21 name: nand_fsbl layout: RAW_ADDR
+ dev: MTD alt: 22 name: nand_ssbl1 layout: RAW_ADDR
+ dev: MTD alt: 23 name: nand_ssbl2 layout: RAW_ADDR
+ dev: MTD alt: 24 name: nand_UBI layout: RAW_ADDR
+ dev: VIRT alt: 25 name: OTP layout: RAW_ADDR
+ dev: VIRT alt: 26 name: PMIC layout: RAW_ADDR
+
+All the supported device are exported for dfu-util tool::
+
+ $> dfu-util -l
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=26, name="PMIC", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=25, name="OTP", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=24, name="nand_UBI", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=23, name="nand_ssbl2", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=22, name="nand_ssbl1", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="nand_fsbl", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="nor_env", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nor_ssbl", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor_fsbl2", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor_fsbl1", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="emmc_userfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="emmc_rootfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="emmc_vendorfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="emmc_bootfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="emmc_ssbl", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="emmc_fsbl2", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="emmc_fsbl1", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="sdcard_userfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="sdcard_rootfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="sdcard_vendorfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="sdcard_bootfs", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="sdcard_ssbl", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="sdcard_fsbl2", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="sdcard_fsbl1", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330"
+
+You can update the boot device:
+
+- SD card (mmc0) ::
+
+ $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img
+ $> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
+
+- EMMC (mmc1)::
+
+ $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img
+ $> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
+ $> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
+
+- NOR::
+
+ $> dfu-util -d 0483:5720 -a 17 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 18 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 19 -D u-boot-stm32mp157c-ev1-trusted.img
+
+- NAND (UBI partition used for NAND only boot or NOR + NAND boot)::
+
+ $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32
+ $> dfu-util -d 0483:5720 -a 22 -D u-boot-stm32mp157c-ev1-trusted.img
+ $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img
+ $> dfu-util -d 0483:5720 -a 24 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
+
+- you can also dump the OTP and the PMIC NVM with::
+
+ $> dfu-util -d 0483:5720 -a 25 -U otp.bin
+ $> dfu-util -d 0483:5720 -a 26 -U pmic.bin
diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst
index a8fd886..cfe2d84 100644
--- a/doc/uefi/uefi.rst
+++ b/doc/uefi/uefi.rst
@@ -356,6 +356,18 @@
CONFIG_BLK=y
CONFIG_PARTITIONS=y
+Miscellaneous
+-------------
+
+Load file 2 protocol
+~~~~~~~~~~~~~~~~~~~~
+
+The load file 2 protocol can be used by the Linux kernel to load the initial
+RAM disk. U-Boot can be configured to provide an implementation with::
+
+ EFI_LOAD_FILE2_INITRD=y
+ EFI_INITRD_FILESPEC=interface dev:part path_to_initrd
+
Links
-----
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 9d4d214..d3673a5 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -571,6 +571,12 @@
continue;
clock[i].valid = attr & CLK_VALID_MASK;
+
+ /* skip query for Invalid clock */
+ ret = versal_is_valid_clock(i);
+ if (ret != CLK_VALID_MASK)
+ continue;
+
clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 444e34b..ff5b28c 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -194,8 +194,9 @@
}
}
- if (!(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF) &&
- (dev != gd->cur_serial_dev))
+ if (!(drv->flags &
+ (DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_REMOVE_WITH_PD_ON)) &&
+ dev != gd->cur_serial_dev)
dev_power_domain_off(dev);
if (flags_remove(flags, drv->flags)) {
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index d1b1a42..110c32b 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -1120,12 +1120,15 @@
static void arasan_check_ondie(struct mtd_info *mtd)
{
struct nand_chip *nand_chip = mtd_to_nand(mtd);
- struct nand_config *nand = nand_get_controller_data(nand_chip);
+ struct nand_drv *info = nand_get_controller_data(nand_chip);
+ struct nand_config *nand = &info->config;
u8 maf_id, dev_id;
u8 get_feature[4];
u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
u32 i;
+ nand_chip->select_chip(mtd, 0);
+
/* Send the command for reading device ID */
nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
@@ -1150,10 +1153,12 @@
for (i = 0; i < 4; i++)
get_feature[i] = nand_chip->read_byte(mtd);
- if (get_feature[0] & ENABLE_ONDIE_ECC)
+ if (get_feature[0] & ENABLE_ONDIE_ECC) {
nand->on_die_ecc_enabled = true;
- else
+ printf("On-DIE ECC Enabled\n");
+ } else {
printf("%s: Unable to enable OnDie ECC\n", __func__);
+ }
/* Use the BBT pattern descriptors */
nand_chip->bbt_td = &bbt_main_descr;
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 08935d9..0098997 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -65,6 +65,7 @@
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
#define DP83867_MDI_CROSSOVER 5
#define DP83867_MDI_CROSSOVER_MDIX 2
#define DP83867_PHYCTRL_SGMIIEN 0x0800
@@ -284,6 +285,9 @@
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
+ /* Do not force link good */
+ val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
/* The code below checks if "port mirroring" N/A MODE4 has been
* enabled during power on bootstrap.
*
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 288037e..5f2f87d 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -655,14 +655,16 @@
return -ENOMEM;
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
- u32 addr = (ulong)priv->rxbuffers;
+ ulong addr = (ulong)priv->rxbuffers;
flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
barrier();
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
- if (!bd_space)
- return -ENOMEM;
+ if (!bd_space) {
+ ret = -ENOMEM;
+ goto err1;
+ }
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
BD_SPACE, DCACHE_OFF);
@@ -674,7 +676,7 @@
ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
if (ret < 0) {
dev_err(dev, "failed to get clock\n");
- return -EINVAL;
+ goto err1;
}
priv->bus = mdio_alloc();
@@ -684,9 +686,19 @@
ret = mdio_register_seq(priv->bus, dev->seq);
if (ret)
+ goto err2;
+
+ ret = zynq_phy_init(dev);
+ if (ret)
- return ret;
+ goto err2;
+
+ return ret;
- return zynq_phy_init(dev);
+err2:
+ free(priv->rxbuffers);
+err1:
+ free(priv->tx_bd);
+ return ret;
}
static int zynq_gem_remove(struct udevice *dev)
diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c
index dab3b99..e0f0a66 100644
--- a/drivers/rng/stm32mp1_rng.c
+++ b/drivers/rng/stm32mp1_rng.c
@@ -33,7 +33,7 @@
static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
{
- int retval = 0, i;
+ int retval, i;
u32 sr, count, reg;
size_t increment;
struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 6161b76..f52e129 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -173,6 +173,7 @@
static const struct udevice_id m41t62_rtc_ids[] = {
{ .compatible = "st,m41t62" },
{ .compatible = "st,m41t82" },
+ { .compatible = "st,m41st87" },
{ .compatible = "microcrystal,rv4162" },
{ }
};
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 6756155..a4a57ba 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -596,6 +596,11 @@
debug("req_type: 0x%x ctrl->bRequest: 0x%x f_dfu->dfu_state: 0x%x\n",
req_type, ctrl->bRequest, f_dfu->dfu_state);
+#ifdef CONFIG_DFU_TIMEOUT
+ /* Forbid aborting by timeout. Next dfu command may update this */
+ dfu_set_timeout(0);
+#endif
+
if (req_type == USB_TYPE_STANDARD) {
if (ctrl->bRequest == USB_REQ_GET_DESCRIPTOR &&
(w_value >> 8) == DFU_DT_FUNC) {
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index 5a023a2..ee646fd 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -174,7 +174,7 @@
transfer_buffer, THOR_STORE_UNIT_SIZE,
(*cnt)++);
if (ret) {
- pr_err("DFU write failed [%d] cnt: %d",
+ pr_err("DFU write failed [%d] cnt: %d\n",
ret, *cnt);
return ret;
}
@@ -224,14 +224,14 @@
transfer_buffer = dfu_get_buf(dfu_entity);
if (!transfer_buffer) {
- pr_err("Transfer buffer not allocated!");
+ pr_err("Transfer buffer not allocated!\n");
return -ENXIO;
}
if (left) {
ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++);
if (ret) {
- pr_err("DFU write failed [%d]: left: %llu", ret, left);
+ pr_err("DFU write failed[%d]: left: %llu\n", ret, left);
return ret;
}
}
@@ -245,7 +245,7 @@
*/
ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt);
if (ret)
- pr_err("DFU flush failed!");
+ pr_err("DFU flush failed!\n");
return ret;
}
@@ -290,7 +290,7 @@
alt_setting_num = dfu_get_alt(f_name);
if (alt_setting_num < 0) {
- pr_err("Alt setting [%d] to write not found!",
+ pr_err("Alt setting [%d] to write not found!\n",
alt_setting_num);
rsp->ack = -ENODEV;
ret = rsp->ack;
@@ -316,7 +316,7 @@
debug("DL EXIT\n");
break;
default:
- pr_err("Operation not supported: %d", rqt->rqt_data);
+ pr_err("Operation not supported: %d\n", rqt->rqt_data);
ret = -ENOTSUPP;
}
@@ -347,7 +347,7 @@
puts("RQT: UPLOAD not supported!\n");
break;
default:
- pr_err("unknown request (%d)", rqt->rqt);
+ pr_err("unknown request (%d)\n", rqt->rqt);
}
return ret;
@@ -546,7 +546,7 @@
status = usb_ep_queue(dev->out_ep, dev->out_req, 0);
if (status) {
- pr_err("kill %s: resubmit %d bytes --> %d",
+ pr_err("kill %s: resubmit %d bytes --> %d\n",
dev->out_ep->name, dev->out_req->length, status);
usb_ep_set_halt(dev->out_ep);
return -EAGAIN;
@@ -580,7 +580,7 @@
status = usb_ep_queue(dev->in_ep, dev->in_req, 0);
if (status) {
- pr_err("kill %s: resubmit %d bytes --> %d",
+ pr_err("kill %s: resubmit %d bytes --> %d\n",
dev->in_ep->name, dev->in_req->length, status);
usb_ep_set_halt(dev->in_ep);
}
@@ -613,7 +613,7 @@
case -ESHUTDOWN: /* disconnect from host */
case -EREMOTEIO: /* short read */
case -EOVERFLOW:
- pr_err("ERROR:%d", status);
+ pr_err("ERROR:%d\n", status);
break;
}
@@ -653,7 +653,7 @@
break;
default:
- pr_err("thor_setup: unknown request: %d", ctrl->bRequest);
+ pr_err("thor_setup: unknown request: %d\n", ctrl->bRequest);
}
if (value >= 0) {
@@ -984,7 +984,7 @@
debug("Communication Data interface\n");
result = thor_eps_setup(f);
if (result)
- pr_err("%s: EPs setup failed!", __func__);
+ pr_err("%s: EPs setup failed!\n", __func__);
dev->configuration_done = 1;
break;
}
diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c
index 4eb6639..aa8c0a9 100644
--- a/drivers/video/meson/meson_vpu.c
+++ b/drivers/video/meson/meson_vpu.c
@@ -210,5 +210,5 @@
.probe = meson_vpu_probe,
.bind = meson_vpu_bind,
.priv_auto_alloc_size = sizeof(struct meson_vpu_priv),
- .flags = DM_FLAG_PRE_RELOC,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_REMOVE_WITH_PD_ON,
};
diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h
new file mode 100644
index 0000000..b059100
--- /dev/null
+++ b/include/configs/socfpga_arria5_secu1.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017-2020 ABB
+ *
+ */
+#ifndef __CONFIG_SOCFPGA_SECU1_H__
+#define __CONFIG_SOCFPGA_SECU1_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Call misc_init_r */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HUSH_INIT_VAR
+/* Eternal oscillator */
+#define CONFIG_SYS_TIMER_RATE 40000000
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
+
+/*
+ * We use bootcounter in i2c nvram of the RTC (0x68)
+ * The offset fopr the bootcounter is 0x9e, which are
+ * the last two bytes of the 128 bytes large NVRAM in the
+ * RTC which begin at address 0x20
+ */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0," __stringify(CONFIG_BAUDRATE) \
+ " ubi.fm_autoconvert=1" \
+ " uio_pdrv_genirq.of_id=\"idq,regbank\""
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootcmd '" \
+ "bridge enable; " \
+ "if test ${bootnum} = \"b\"; " \
+ "then run _fpga_loadsafe; " \
+ "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
+ "run _fpga_loaduser; " \
+ "fi;" \
+ "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
+ "' && " \
+ "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
+ "saveenv && saveenv && boot;"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Autoboot
+ *
+ * After 45s of inactivity in the prompt, the board will reset.
+ * Set 'bootretry' in the environment to -1 to disable this behavior
+ */
+#define CONFIG_BOOT_RETRY_TIME 45
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR
+
+/*
+ * FPGA Remote Update related environment
+ *
+ * Note that since those commands access the FPGA, the HPS-to-FPGA
+ * bridges MUST have been previously enabled (for example
+ * with 'bridge enable').
+ */
+#define FPGA_RMTU_ENV \
+ "rmtu_page=0xFF29000C\0" \
+ "rmtu_reconfig=0xFF290018\0" \
+ "fpga_safebase=0x0\0" \
+ "fpga_userbase=0x2000000\0" \
+ "_fpga_loaduser=echo Loading FPGA USER image..." \
+ " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \
+ "_fpga_loadsafe=echo Loading FPGA SAFE image..." \
+ " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=" \
+ "nand erase 0x100000 0x40000\0"
+
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
+ "release=" \
+ "run newenv; reset\0" \
+ "develop=" \
+ "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ FPGA_RMTU_ENV \
+ CONFIG_KM_DEF_ENV_BOOTTARGETS \
+ CONFIG_KM_NEW_ENV \
+ "socfpga_legacy_reset_compat=1\0" \
+ "altbootcmd=run bootcmd;\0" \
+ "bootlimit=6\0" \
+ "bootnum=1\0" \
+ "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \
+ "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
+ "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \
+ "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \
+ "userload=ubi part nand.ubi &&" \
+ "ubi check rootfs$bootnum &&" \
+ "ubi read $fdt_addr dtb$bootnum &&" \
+ "ubi read $loadaddr kernel$bootnum\0" \
+ "userboot=setenv bootargs " CONFIG_BOOTARGS \
+ " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \
+ " ro rootfstype=squashfs init=sbin/preinit;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "verify=y\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#endif
+
+#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
+
+#endif /* __CONFIG_SOCFPGA_SECU1_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8d10469..ec41843 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -94,12 +94,13 @@
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#ifndef CONFIG_SYS_TIMER_RATE
#define CONFIG_SYS_TIMER_RATE 25000000
#endif
+#endif
/*
* L4 Watchdog
@@ -120,6 +121,7 @@
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index b95fb9c..55fa85e 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -160,6 +160,7 @@
"emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
"nandboot=run bootcmd_ubifs0\0" \
"norboot=run tftpboot\0" \
+ "sdboot=sdsetn && run bootcmd_mmc${sd_first_dev}\0" \
"usbboot=run bootcmd_usb0\0" \
"emmcscript=setenv devtype mmc && " \
"mmcsetn && " \
@@ -170,6 +171,10 @@
"ubifsmount ubi0:boot && " \
"ubifsload ${loadaddr} ${script} && " \
"source $loadaddr\0" \
+ "sdscript=setenv devtype mmc && " \
+ "sdsetn && " \
+ "setenv devnum ${sd_first_dev} && " \
+ "run loadscript_fat\0" \
"norscript=echo Running ${script} from tftp ... && " \
"tftpboot ${script} &&" \
"source $loadaddr\0" \
@@ -196,6 +201,12 @@
"nand write $loadaddr 0 0x00020000 && " \
"tftpboot $third_image && " \
"nand write $loadaddr 0x00020000 0x001e0000\0" \
+ "sdupdate=sdsetn &&" \
+ "mmc dev $sd_first_dev &&" \
+ "tftpboot $second_image && " \
+ "mmc write $loadaddr 0 100 && " \
+ "tftpboot $third_image && " \
+ "mmc write $loadaddr 100 f00\0" \
"usbupdate=usb start &&" \
"tftpboot $second_image && " \
"usb write $loadaddr 0 100 && " \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 2d53237..b1cef4d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -41,8 +41,6 @@
# define CONFIG_BOOTP_MAY_FAIL
#endif
-/* QSPI */
-
/* NOR */
#ifdef CONFIG_MTD_NOR_FLASH
# define CONFIG_SYS_FLASH_BASE 0xE2000000
diff --git a/include/dm/device.h b/include/dm/device.h
index ab806d0..a56164b 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -68,6 +68,12 @@
#define DM_FLAG_PLATDATA_VALID (1 << 12)
/*
+ * Device is removed without switching off its power domain. This might
+ * be required, i. e. for serial console (debug) output when booting OS.
+ */
+#define DM_FLAG_REMOVE_WITH_PD_ON (1 << 13)
+
+/*
* One or multiple of these flags are passed to device_remove() so that
* a selective device removal as specified by the remove-stage and the
* driver flags can be done.
diff --git a/include/efi_api.h b/include/efi_api.h
index b7b68cb..3d1a6be 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -331,6 +331,14 @@
EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \
0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+#define EFI_LOAD_FILE_PROTOCOL_GUID \
+ EFI_GUID(0x56ec3091, 0x954c, 0x11d2, \
+ 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_LOAD_FILE2_PROTOCOL_GUID \
+ EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, \
+ 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d)
+
struct efi_configuration_table {
efi_guid_t guid;
void *table;
@@ -486,6 +494,7 @@
#define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04
# define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01
# define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02
+# define DEVICE_PATH_SUB_TYPE_VENDOR_PATH 0x03
# define DEVICE_PATH_SUB_TYPE_FILE_PATH 0x04
struct efi_device_path_hard_drive_path {
@@ -1619,6 +1628,14 @@
char *supported_languages;
};
+struct efi_load_file_protocol {
+ efi_status_t (EFIAPI *load_file)(struct efi_load_file_protocol *this,
+ struct efi_device_path *file_path,
+ bool boot_policy,
+ efi_uintn_t *buffer_size,
+ void *buffer);
+};
+
/* Boot manager load options */
#define LOAD_OPTION_ACTIVE 0x00000001
#define LOAD_OPTION_FORCE_RECONNECT 0x00000002
diff --git a/include/efi_load_initrd.h b/include/efi_load_initrd.h
new file mode 100644
index 0000000..478ae80
--- /dev/null
+++ b/include/efi_load_initrd.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#if !defined _EFI_LOAD_INITRD_H_
+#define _EFI_LOAD_INITRD_H_
+
+#include <efi.h>
+#include <efi_api.h>
+
+/*
+ * Vendor GUID used by Linux to identify the handle with the
+ * EFI_LOAD_FILE2_PROTOCOL and load an initial ramdisk.
+ */
+#define EFI_INITRD_MEDIA_GUID \
+ EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, \
+ 0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
+
+struct efi_initrd_dp {
+ struct efi_device_path_vendor vendor;
+ struct efi_device_path end;
+} __packed;
+
+#endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index d4c59b5..8e34379 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -378,6 +378,7 @@
efi_status_t efi_net_register(void);
/* Called by bootefi to make the watchdog available */
efi_status_t efi_watchdog_register(void);
+efi_status_t efi_initrd_register(void);
/* Called by bootefi to make SMBIOS tables available */
/**
* efi_acpi_register() - write out ACPI tables
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 76f43ec..9890144 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -130,4 +130,19 @@
Provide a EFI_RNG_PROTOCOL implementation using the hardware random
number generator of the platform.
+config EFI_LOAD_FILE2_INITRD
+ bool "EFI_FILE_LOAD2_PROTOCOL for Linux initial ramdisk"
+ default n
+ help
+ Expose a EFI_FILE_LOAD2_PROTOCOL that the Linux UEFI stub can
+ use to load the initial ramdisk. Once this is enabled using
+ initrd=<ramdisk> will stop working.
+
+config EFI_INITRD_FILESPEC
+ string "initramfs path"
+ default "host 0:1 initrd"
+ depends on EFI_LOAD_FILE2_INITRD
+ help
+ Full path of the initramfs file, e.g. mmc 0:2 initramfs.cpio.gz.
+
endif
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 04dc864..9b3b704 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -43,3 +43,4 @@
obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
+obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o
diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c
new file mode 100644
index 0000000..574a83d
--- /dev/null
+++ b/lib/efi_loader/efi_load_initrd.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#include <common.h>
+#include <env.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <dm.h>
+#include <fs.h>
+#include <efi_loader.h>
+#include <efi_load_initrd.h>
+
+static const efi_guid_t efi_guid_load_file2_protocol =
+ EFI_LOAD_FILE2_PROTOCOL_GUID;
+
+static efi_status_t EFIAPI
+efi_load_file2_initrd(struct efi_load_file_protocol *this,
+ struct efi_device_path *file_path, bool boot_policy,
+ efi_uintn_t *buffer_size, void *buffer);
+
+static const struct efi_load_file_protocol efi_lf2_protocol = {
+ .load_file = efi_load_file2_initrd,
+};
+
+/*
+ * Device path defined by Linux to identify the handle providing the
+ * EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk.
+ */
+static const struct efi_initrd_dp dp = {
+ .vendor = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+ sizeof(dp.vendor),
+ },
+ EFI_INITRD_MEDIA_GUID,
+ },
+ .end = {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(dp.end),
+ }
+};
+
+/**
+ * get_file_size() - retrieve the size of initramfs, set efi status on error
+ *
+ * @dev: device to read from. i.e "mmc"
+ * @part: device partition. i.e "0:1"
+ * @file: name fo file
+ * @status: EFI exit code in case of failure
+ *
+ * Return: size of file
+ */
+static loff_t get_file_size(const char *dev, const char *part, const char *file,
+ efi_status_t *status)
+{
+ loff_t sz = 0;
+ int ret;
+
+ ret = fs_set_blk_dev(dev, part, FS_TYPE_ANY);
+ if (ret) {
+ *status = EFI_NO_MEDIA;
+ goto out;
+ }
+
+ ret = fs_size(file, &sz);
+ if (ret) {
+ sz = 0;
+ *status = EFI_NOT_FOUND;
+ goto out;
+ }
+
+out:
+ return sz;
+}
+
+/**
+ * load_file2() - get information about random number generation
+ *
+ * This function implement the LoadFile2() service in order to load an initram
+ * disk requested by the Linux kernel stub.
+ * See the UEFI spec for details.
+ *
+ * @this: loadfile2 protocol instance
+ * @file_path: relative path of the file. "" in this case
+ * @boot_policy: must be false for Loadfile2
+ * @buffer_size: size of allocated buffer
+ * @buffer: buffer to load the file
+ *
+ * Return: status code
+ */
+static efi_status_t EFIAPI
+efi_load_file2_initrd(struct efi_load_file_protocol *this,
+ struct efi_device_path *file_path, bool boot_policy,
+ efi_uintn_t *buffer_size, void *buffer)
+{
+ const char *filespec = CONFIG_EFI_INITRD_FILESPEC;
+ efi_status_t status = EFI_NOT_FOUND;
+ loff_t file_sz = 0, read_sz = 0;
+ char *dev, *part, *file;
+ char *s;
+ int ret;
+
+ EFI_ENTRY("%p, %p, %d, %p, %p", this, file_path, boot_policy,
+ buffer_size, buffer);
+
+ s = strdup(filespec);
+ if (!s)
+ goto out;
+
+ if (!this || this != &efi_lf2_protocol ||
+ !buffer_size) {
+ status = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (file_path->type != dp.end.type ||
+ file_path->sub_type != dp.end.sub_type) {
+ status = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (boot_policy) {
+ status = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ /* expect something like 'mmc 0:1 initrd.cpio.gz' */
+ dev = strsep(&s, " ");
+ if (!dev)
+ goto out;
+ part = strsep(&s, " ");
+ if (!part)
+ goto out;
+ file = strsep(&s, " ");
+ if (!file)
+ goto out;
+
+ file_sz = get_file_size(dev, part, file, &status);
+ if (!file_sz)
+ goto out;
+
+ if (!buffer || *buffer_size < file_sz) {
+ status = EFI_BUFFER_TOO_SMALL;
+ *buffer_size = file_sz;
+ } else {
+ ret = fs_set_blk_dev(dev, part, FS_TYPE_ANY);
+ if (ret) {
+ status = EFI_NO_MEDIA;
+ goto out;
+ }
+
+ ret = fs_read(file, map_to_sysmem(buffer), 0, *buffer_size,
+ &read_sz);
+ if (ret || read_sz != file_sz)
+ goto out;
+ *buffer_size = read_sz;
+
+ status = EFI_SUCCESS;
+ }
+
+out:
+ free(s);
+ return EFI_EXIT(status);
+}
+
+/**
+ * efi_initrd_register() - Register a handle and loadfile2 protocol
+ *
+ * This function creates a new handle and installs a linux specific GUID
+ * to handle initram disk loading during boot.
+ * See the UEFI spec for details.
+ *
+ * Return: status code
+ */
+efi_status_t efi_initrd_register(void)
+{
+ efi_handle_t efi_initrd_handle = NULL;
+ efi_status_t ret;
+
+ /*
+ * Set up the handle with the EFI_LOAD_FILE2_PROTOCOL which Linux may
+ * use to load the initial ramdisk.
+ */
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces
+ (&efi_initrd_handle,
+ /* initramfs */
+ &efi_guid_device_path, &dp,
+ /* LOAD_FILE2 */
+ &efi_guid_load_file2_protocol,
+ (void *)&efi_lf2_protocol,
+ NULL));
+
+ return ret;
+}
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 2060307..b458093 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -155,6 +155,11 @@
if (ret != EFI_SUCCESS)
goto out;
#endif
+#ifdef CONFIG_EFI_LOAD_FILE2_INITRD
+ ret = efi_initrd_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+#endif
#ifdef CONFIG_NET
ret = efi_net_register();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 3ad96e1..cf132c3 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -49,6 +49,7 @@
obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_selftest_rng.o
obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o
+obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_selftest_load_initrd.o
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
obj-y += efi_selftest_fdt.o
diff --git a/lib/efi_selftest/efi_selftest_load_initrd.c b/lib/efi_selftest/efi_selftest_load_initrd.c
new file mode 100644
index 0000000..e16163c
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_load_initrd.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_load_initrd
+ *
+ * Copyright (c) 2020 Ilias Apalodimas <ilias.apalodimas@linaro.org>
+ *
+ * This test checks the FileLoad2 protocol.
+ * A known file is read from the file system and verified.
+ *
+ * An example usage - given a file image with a file system in partition 1
+ * holding file initrd - is:
+ *
+ * * Configure the sandbox with
+ *
+ * CONFIG_EFI_SELFTEST=y
+ * CONFIG_EFI_LOAD_FILE2_INITRD=y
+ * CONFIG_EFI_INITRD_FILESPEC="host 0:1 initrd"
+ *
+ * * Run ./u-boot and execute
+ *
+ * host bind 0 image
+ * setenv efi_selftest load initrd
+ * bootefi selftest
+ *
+ * This would provide a test output like:
+ *
+ * Testing EFI API implementation
+ *
+ * Selected test: 'load initrd'
+ *
+ * Setting up 'load initrd'
+ * Setting up 'load initrd' succeeded
+ *
+ * Executing 'load initrd'
+ * Loaded 12378613 bytes
+ * CRC32 2997478465
+ *
+ * Now the size and CRC32 can be compared to the provided file.
+ */
+
+#include <efi_selftest.h>
+#include <efi_loader.h>
+#include <efi_load_initrd.h>
+
+static struct efi_boot_services *boottime;
+
+static struct efi_initrd_dp dp = {
+ .vendor = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+ sizeof(dp.vendor),
+ },
+ EFI_INITRD_MEDIA_GUID,
+ },
+ .end = {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(dp.end),
+ }
+};
+
+static struct efi_initrd_dp dp_invalid = {
+ .vendor = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+ sizeof(dp.vendor),
+ },
+ EFI_INITRD_MEDIA_GUID,
+ },
+ .end = {
+ 0x8f, /* invalid */
+ 0xfe, /* invalid */
+ sizeof(dp.end),
+ }
+};
+
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ boottime = systable->boottime;
+
+ return EFI_ST_SUCCESS;
+}
+
+static int execute(void)
+{
+ efi_guid_t lf2_proto_guid = EFI_LOAD_FILE2_PROTOCOL_GUID;
+ struct efi_load_file_protocol *lf2;
+ struct efi_device_path *dp2, *dp2_invalid;
+ efi_status_t status;
+ efi_handle_t handle;
+ char buffer[64];
+ efi_uintn_t buffer_size;
+ void *buf;
+ u32 crc32;
+
+ memset(buffer, 0, sizeof(buffer));
+
+ dp2 = (struct efi_device_path *)&dp;
+ status = boottime->locate_device_path(&lf2_proto_guid, &dp2, &handle);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Unable to locate device path\n");
+ return EFI_ST_FAILURE;
+ }
+
+ status = boottime->handle_protocol(handle, &lf2_proto_guid,
+ (void **)&lf2);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Unable to locate protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Case 1:
+ * buffer_size can't be NULL
+ * protocol can't be NULL
+ */
+ status = lf2->load_file(lf2, dp2, false, NULL, &buffer);
+ if (status != EFI_INVALID_PARAMETER) {
+ efi_st_error("Buffer size can't be NULL\n");
+ return EFI_ST_FAILURE;
+ }
+ buffer_size = sizeof(buffer);
+ status = lf2->load_file(NULL, dp2, false, &buffer_size, &buffer);
+ if (status != EFI_INVALID_PARAMETER) {
+ efi_st_error("Protocol can't be NULL\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Case 2: Match end node type/sub-type on device path
+ */
+ dp2_invalid = (struct efi_device_path *)&dp_invalid;
+ buffer_size = sizeof(buffer);
+ status = lf2->load_file(lf2, dp2_invalid, false, &buffer_size, &buffer);
+ if (status != EFI_INVALID_PARAMETER) {
+ efi_st_error("Invalid device path type must return EFI_INVALID_PARAMETER\n");
+ return EFI_ST_FAILURE;
+ }
+
+ status = lf2->load_file(lf2, dp2_invalid, false, &buffer_size, &buffer);
+ if (status != EFI_INVALID_PARAMETER) {
+ efi_st_error("Invalid device path sub-type must return EFI_INVALID_PARAMETER\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Case 3:
+ * BootPolicy 'true' must return EFI_UNSUPPORTED
+ */
+ buffer_size = sizeof(buffer);
+ status = lf2->load_file(lf2, dp2, true, &buffer_size, &buffer);
+ if (status != EFI_UNSUPPORTED) {
+ efi_st_error("BootPolicy true must return EFI_UNSUPPORTED\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Case: Pass buffer size as zero, firmware must return
+ * EFI_BUFFER_TOO_SMALL and an appropriate size
+ */
+ buffer_size = 0;
+ status = lf2->load_file(lf2, dp2, false, &buffer_size, NULL);
+ if (status != EFI_BUFFER_TOO_SMALL || !buffer_size) {
+ efi_st_printf("buffer_size: %u\n", (unsigned int)buffer_size);
+ efi_st_printf("status: %x\n", (unsigned int)status);
+ efi_st_error("Buffer size not updated\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Case: Pass buffer size as smaller than the file_size,
+ * firmware must return * EFI_BUFFER_TOO_SMALL and an appropriate size
+ */
+ buffer_size = 1;
+ status = lf2->load_file(lf2, dp2, false, &buffer_size, &buffer);
+ if (status != EFI_BUFFER_TOO_SMALL || buffer_size <= 1) {
+ efi_st_error("Buffer size not updated\n");
+ return EFI_ST_FAILURE;
+ }
+
+ status = boottime->allocate_pool(EFI_BOOT_SERVICES_DATA, buffer_size,
+ &buf);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Cannot allocate buffer\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Case: Pass correct buffer, load the file and verify checksum*/
+ status = lf2->load_file(lf2, dp2, false, &buffer_size, buf);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Loading initrd failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ efi_st_printf("Loaded %u bytes\n", (unsigned int)buffer_size);
+ status = boottime->calculate_crc32(buf, buffer_size, &crc32);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Could not determine CRC32\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("CRC32 %u\n", (unsigned int)crc32);
+
+ status = boottime->free_pool(buf);
+ if (status != EFI_SUCCESS) {
+ efi_st_error("Cannot free buffer\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(load_initrd) = {
+ .name = "load initrd",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .on_request = true,
+};